1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_MAIN_H 5 #define __HCLGE_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include <linux/phy.h> 9 #include <linux/if_vlan.h> 10 #include <linux/kfifo.h> 11 #include <net/devlink.h> 12 13 #include "hclge_cmd.h" 14 #include "hclge_ptp.h" 15 #include "hnae3.h" 16 17 #define HCLGE_MOD_VERSION "1.0" 18 #define HCLGE_DRIVER_NAME "hclge" 19 20 #define HCLGE_MAX_PF_NUM 8 21 22 #define HCLGE_VF_VPORT_START_NUM 1 23 24 #define HCLGE_RD_FIRST_STATS_NUM 2 25 #define HCLGE_RD_OTHER_STATS_NUM 4 26 27 #define HCLGE_INVALID_VPORT 0xffff 28 29 #define HCLGE_PF_CFG_BLOCK_SIZE 32 30 #define HCLGE_PF_CFG_DESC_NUM \ 31 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) 32 33 #define HCLGE_VECTOR_REG_BASE 0x20000 34 #define HCLGE_VECTOR_EXT_REG_BASE 0x30000 35 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400 36 37 #define HCLGE_VECTOR_REG_OFFSET 0x4 38 #define HCLGE_VECTOR_REG_OFFSET_H 0x1000 39 #define HCLGE_VECTOR_VF_OFFSET 0x100000 40 41 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 42 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 43 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 44 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 45 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 46 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 47 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701C 48 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 49 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 50 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 51 52 #define HCLGE_CMDQ_INTR_STS_REG 0x27104 53 #define HCLGE_CMDQ_INTR_EN_REG 0x27108 54 #define HCLGE_CMDQ_INTR_GEN_REG 0x2710C 55 56 /* bar registers for common func */ 57 #define HCLGE_GRO_EN_REG 0x28000 58 #define HCLGE_RXD_ADV_LAYOUT_EN_REG 0x28008 59 60 /* bar registers for rcb */ 61 #define HCLGE_RING_RX_ADDR_L_REG 0x80000 62 #define HCLGE_RING_RX_ADDR_H_REG 0x80004 63 #define HCLGE_RING_RX_BD_NUM_REG 0x80008 64 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C 65 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014 66 #define HCLGE_RING_RX_TAIL_REG 0x80018 67 #define HCLGE_RING_RX_HEAD_REG 0x8001C 68 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020 69 #define HCLGE_RING_RX_OFFSET_REG 0x80024 70 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028 71 #define HCLGE_RING_RX_STASH_REG 0x80030 72 #define HCLGE_RING_RX_BD_ERR_REG 0x80034 73 #define HCLGE_RING_TX_ADDR_L_REG 0x80040 74 #define HCLGE_RING_TX_ADDR_H_REG 0x80044 75 #define HCLGE_RING_TX_BD_NUM_REG 0x80048 76 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C 77 #define HCLGE_RING_TX_TC_REG 0x80050 78 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054 79 #define HCLGE_RING_TX_TAIL_REG 0x80058 80 #define HCLGE_RING_TX_HEAD_REG 0x8005C 81 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060 82 #define HCLGE_RING_TX_OFFSET_REG 0x80064 83 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068 84 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070 85 #define HCLGE_RING_TX_BD_ERR_REG 0x80074 86 #define HCLGE_RING_EN_REG 0x80090 87 88 /* bar registers for tqp interrupt */ 89 #define HCLGE_TQP_INTR_CTRL_REG 0x20000 90 #define HCLGE_TQP_INTR_GL0_REG 0x20100 91 #define HCLGE_TQP_INTR_GL1_REG 0x20200 92 #define HCLGE_TQP_INTR_GL2_REG 0x20300 93 #define HCLGE_TQP_INTR_RL_REG 0x20900 94 95 #define HCLGE_RSS_IND_TBL_SIZE 512 96 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0) 97 #define HCLGE_RSS_KEY_SIZE 40 98 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0 99 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1 100 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2 101 #define HCLGE_RSS_HASH_ALGO_MASK GENMASK(3, 0) 102 103 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 104 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 105 #define HCLGE_D_PORT_BIT BIT(0) 106 #define HCLGE_S_PORT_BIT BIT(1) 107 #define HCLGE_D_IP_BIT BIT(2) 108 #define HCLGE_S_IP_BIT BIT(3) 109 #define HCLGE_V_TAG_BIT BIT(4) 110 #define HCLGE_RSS_INPUT_TUPLE_SCTP_NO_PORT \ 111 (HCLGE_D_IP_BIT | HCLGE_S_IP_BIT | HCLGE_V_TAG_BIT) 112 113 #define HCLGE_RSS_TC_SIZE_0 1 114 #define HCLGE_RSS_TC_SIZE_1 2 115 #define HCLGE_RSS_TC_SIZE_2 4 116 #define HCLGE_RSS_TC_SIZE_3 8 117 #define HCLGE_RSS_TC_SIZE_4 16 118 #define HCLGE_RSS_TC_SIZE_5 32 119 #define HCLGE_RSS_TC_SIZE_6 64 120 #define HCLGE_RSS_TC_SIZE_7 128 121 122 #define HCLGE_UMV_TBL_SIZE 3072 123 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \ 124 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM) 125 126 #define HCLGE_TQP_RESET_TRY_TIMES 200 127 128 #define HCLGE_PHY_PAGE_MDIX 0 129 #define HCLGE_PHY_PAGE_COPPER 0 130 131 /* Page Selection Reg. */ 132 #define HCLGE_PHY_PAGE_REG 22 133 134 /* Copper Specific Control Register */ 135 #define HCLGE_PHY_CSC_REG 16 136 137 /* Copper Specific Status Register */ 138 #define HCLGE_PHY_CSS_REG 17 139 140 #define HCLGE_PHY_MDIX_CTRL_S 5 141 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) 142 143 #define HCLGE_PHY_MDIX_STATUS_B 6 144 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11 145 146 #define HCLGE_GET_DFX_REG_TYPE_CNT 4 147 148 /* Factor used to calculate offset and bitmap of VF num */ 149 #define HCLGE_VF_NUM_PER_CMD 64 150 151 #define HCLGE_MAX_QSET_NUM 1024 152 153 #define HCLGE_DBG_RESET_INFO_LEN 1024 154 155 enum HLCGE_PORT_TYPE { 156 HOST_PORT, 157 NETWORK_PORT 158 }; 159 160 #define PF_VPORT_ID 0 161 162 #define HCLGE_PF_ID_S 0 163 #define HCLGE_PF_ID_M GENMASK(2, 0) 164 #define HCLGE_VF_ID_S 3 165 #define HCLGE_VF_ID_M GENMASK(10, 3) 166 #define HCLGE_PORT_TYPE_B 11 167 #define HCLGE_NETWORK_PORT_ID_S 0 168 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0) 169 170 /* Reset related Registers */ 171 #define HCLGE_PF_OTHER_INT_REG 0x20600 172 #define HCLGE_MISC_RESET_STS_REG 0x20700 173 #define HCLGE_MISC_VECTOR_INT_STS 0x20800 174 #define HCLGE_GLOBAL_RESET_REG 0x20A00 175 #define HCLGE_GLOBAL_RESET_BIT 0 176 #define HCLGE_CORE_RESET_BIT 1 177 #define HCLGE_IMP_RESET_BIT 2 178 #define HCLGE_RESET_INT_M GENMASK(7, 5) 179 #define HCLGE_FUN_RST_ING 0x20C00 180 #define HCLGE_FUN_RST_ING_B 0 181 182 /* Vector0 register bits define */ 183 #define HCLGE_VECTOR0_REG_PTP_INT_B 0 184 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5 185 #define HCLGE_VECTOR0_CORERESET_INT_B 6 186 #define HCLGE_VECTOR0_IMPRESET_INT_B 7 187 188 /* Vector0 interrupt CMDQ event source register(RW) */ 189 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100 190 /* CMDQ register bits for RX event(=MBX event) */ 191 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 192 193 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1 194 #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U 195 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U 196 #define HCLGE_VECTOR0_ALL_MSIX_ERR_B 6U 197 #define HCLGE_TRIGGER_IMP_RESET_B 7U 198 199 #define HCLGE_MAC_DEFAULT_FRAME \ 200 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN) 201 #define HCLGE_MAC_MIN_FRAME 64 202 #define HCLGE_MAC_MAX_FRAME 9728 203 204 #define HCLGE_SUPPORT_1G_BIT BIT(0) 205 #define HCLGE_SUPPORT_10G_BIT BIT(1) 206 #define HCLGE_SUPPORT_25G_BIT BIT(2) 207 #define HCLGE_SUPPORT_50G_BIT BIT(3) 208 #define HCLGE_SUPPORT_100G_BIT BIT(4) 209 /* to be compatible with exsit board */ 210 #define HCLGE_SUPPORT_40G_BIT BIT(5) 211 #define HCLGE_SUPPORT_100M_BIT BIT(6) 212 #define HCLGE_SUPPORT_10M_BIT BIT(7) 213 #define HCLGE_SUPPORT_200G_BIT BIT(8) 214 #define HCLGE_SUPPORT_GE \ 215 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT) 216 217 enum HCLGE_DEV_STATE { 218 HCLGE_STATE_REINITING, 219 HCLGE_STATE_DOWN, 220 HCLGE_STATE_DISABLED, 221 HCLGE_STATE_REMOVING, 222 HCLGE_STATE_NIC_REGISTERED, 223 HCLGE_STATE_ROCE_REGISTERED, 224 HCLGE_STATE_SERVICE_INITED, 225 HCLGE_STATE_RST_SERVICE_SCHED, 226 HCLGE_STATE_RST_HANDLING, 227 HCLGE_STATE_MBX_SERVICE_SCHED, 228 HCLGE_STATE_MBX_HANDLING, 229 HCLGE_STATE_ERR_SERVICE_SCHED, 230 HCLGE_STATE_STATISTICS_UPDATING, 231 HCLGE_STATE_CMD_DISABLE, 232 HCLGE_STATE_LINK_UPDATING, 233 HCLGE_STATE_RST_FAIL, 234 HCLGE_STATE_FD_TBL_CHANGED, 235 HCLGE_STATE_FD_CLEAR_ALL, 236 HCLGE_STATE_FD_USER_DEF_CHANGED, 237 HCLGE_STATE_PTP_EN, 238 HCLGE_STATE_PTP_TX_HANDLING, 239 HCLGE_STATE_MAX 240 }; 241 242 enum hclge_evt_cause { 243 HCLGE_VECTOR0_EVENT_RST, 244 HCLGE_VECTOR0_EVENT_MBX, 245 HCLGE_VECTOR0_EVENT_ERR, 246 HCLGE_VECTOR0_EVENT_PTP, 247 HCLGE_VECTOR0_EVENT_OTHER, 248 }; 249 250 enum HCLGE_MAC_SPEED { 251 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */ 252 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */ 253 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */ 254 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ 255 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ 256 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ 257 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ 258 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ 259 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */ 260 HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */ 261 }; 262 263 enum HCLGE_MAC_DUPLEX { 264 HCLGE_MAC_HALF, 265 HCLGE_MAC_FULL 266 }; 267 268 #define QUERY_SFP_SPEED 0 269 #define QUERY_ACTIVE_SPEED 1 270 271 struct hclge_mac { 272 u8 mac_id; 273 u8 phy_addr; 274 u8 flag; 275 u8 media_type; /* port media type, e.g. fibre/copper/backplane */ 276 u8 mac_addr[ETH_ALEN]; 277 u8 autoneg; 278 u8 duplex; 279 u8 support_autoneg; 280 u8 speed_type; /* 0: sfp speed, 1: active speed */ 281 u32 speed; 282 u32 max_speed; 283 u32 speed_ability; /* speed ability supported by current media */ 284 u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */ 285 u32 fec_mode; /* active fec mode */ 286 u32 user_fec_mode; 287 u32 fec_ability; 288 int link; /* store the link status of mac & phy (if phy exists) */ 289 struct phy_device *phydev; 290 struct mii_bus *mdio_bus; 291 phy_interface_t phy_if; 292 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 293 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 294 }; 295 296 struct hclge_hw { 297 void __iomem *io_base; 298 void __iomem *mem_base; 299 struct hclge_mac mac; 300 int num_vec; 301 struct hclge_cmq cmq; 302 }; 303 304 /* TQP stats */ 305 struct hlcge_tqp_stats { 306 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 307 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 308 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 309 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 310 }; 311 312 struct hclge_tqp { 313 /* copy of device pointer from pci_dev, 314 * used when perform DMA mapping 315 */ 316 struct device *dev; 317 struct hnae3_queue q; 318 struct hlcge_tqp_stats tqp_stats; 319 u16 index; /* Global index in a NIC controller */ 320 321 bool alloced; 322 }; 323 324 enum hclge_fc_mode { 325 HCLGE_FC_NONE, 326 HCLGE_FC_RX_PAUSE, 327 HCLGE_FC_TX_PAUSE, 328 HCLGE_FC_FULL, 329 HCLGE_FC_PFC, 330 HCLGE_FC_DEFAULT 331 }; 332 333 #define HCLGE_FILTER_TYPE_VF 0 334 #define HCLGE_FILTER_TYPE_PORT 1 335 #define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0) 336 #define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0) 337 #define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1) 338 #define HCLGE_FILTER_FE_ROCE_INGRESS_B BIT(2) 339 #define HCLGE_FILTER_FE_ROCE_EGRESS_B BIT(3) 340 #define HCLGE_FILTER_FE_EGRESS (HCLGE_FILTER_FE_NIC_EGRESS_B \ 341 | HCLGE_FILTER_FE_ROCE_EGRESS_B) 342 #define HCLGE_FILTER_FE_INGRESS (HCLGE_FILTER_FE_NIC_INGRESS_B \ 343 | HCLGE_FILTER_FE_ROCE_INGRESS_B) 344 345 enum hclge_vlan_fltr_cap { 346 HCLGE_VLAN_FLTR_DEF, 347 HCLGE_VLAN_FLTR_CAN_MDF, 348 }; 349 enum hclge_link_fail_code { 350 HCLGE_LF_NORMAL, 351 HCLGE_LF_REF_CLOCK_LOST, 352 HCLGE_LF_XSFP_TX_DISABLE, 353 HCLGE_LF_XSFP_ABSENT, 354 }; 355 356 #define HCLGE_LINK_STATUS_DOWN 0 357 #define HCLGE_LINK_STATUS_UP 1 358 359 #define HCLGE_PG_NUM 4 360 #define HCLGE_SCH_MODE_SP 0 361 #define HCLGE_SCH_MODE_DWRR 1 362 struct hclge_pg_info { 363 u8 pg_id; 364 u8 pg_sch_mode; /* 0: sp; 1: dwrr */ 365 u8 tc_bit_map; 366 u32 bw_limit; 367 u8 tc_dwrr[HNAE3_MAX_TC]; 368 }; 369 370 struct hclge_tc_info { 371 u8 tc_id; 372 u8 tc_sch_mode; /* 0: sp; 1: dwrr */ 373 u8 pgid; 374 u32 bw_limit; 375 }; 376 377 struct hclge_cfg { 378 u8 tc_num; 379 u8 vlan_fliter_cap; 380 u16 tqp_desc_num; 381 u16 rx_buf_len; 382 u16 vf_rss_size_max; 383 u16 pf_rss_size_max; 384 u8 phy_addr; 385 u8 media_type; 386 u8 mac_addr[ETH_ALEN]; 387 u8 default_speed; 388 u32 numa_node_map; 389 u32 tx_spare_buf_size; 390 u16 speed_ability; 391 u16 umv_space; 392 }; 393 394 struct hclge_tm_info { 395 u8 num_tc; 396 u8 num_pg; /* It must be 1 if vNET-Base schd */ 397 u8 pg_dwrr[HCLGE_PG_NUM]; 398 u8 prio_tc[HNAE3_MAX_USER_PRIO]; 399 struct hclge_pg_info pg_info[HCLGE_PG_NUM]; 400 struct hclge_tc_info tc_info[HNAE3_MAX_TC]; 401 enum hclge_fc_mode fc_mode; 402 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */ 403 u8 pfc_en; /* PFC enabled or not for user priority */ 404 }; 405 406 /* max number of mac statistics on each version */ 407 #define HCLGE_MAC_STATS_MAX_NUM_V1 87 408 #define HCLGE_MAC_STATS_MAX_NUM_V2 105 409 410 struct hclge_comm_stats_str { 411 char desc[ETH_GSTRING_LEN]; 412 u32 stats_num; 413 unsigned long offset; 414 }; 415 416 /* mac stats ,opcode id: 0x0032 */ 417 struct hclge_mac_stats { 418 u64 mac_tx_mac_pause_num; 419 u64 mac_rx_mac_pause_num; 420 u64 rsv0; 421 u64 mac_tx_pfc_pri0_pkt_num; 422 u64 mac_tx_pfc_pri1_pkt_num; 423 u64 mac_tx_pfc_pri2_pkt_num; 424 u64 mac_tx_pfc_pri3_pkt_num; 425 u64 mac_tx_pfc_pri4_pkt_num; 426 u64 mac_tx_pfc_pri5_pkt_num; 427 u64 mac_tx_pfc_pri6_pkt_num; 428 u64 mac_tx_pfc_pri7_pkt_num; 429 u64 mac_rx_pfc_pri0_pkt_num; 430 u64 mac_rx_pfc_pri1_pkt_num; 431 u64 mac_rx_pfc_pri2_pkt_num; 432 u64 mac_rx_pfc_pri3_pkt_num; 433 u64 mac_rx_pfc_pri4_pkt_num; 434 u64 mac_rx_pfc_pri5_pkt_num; 435 u64 mac_rx_pfc_pri6_pkt_num; 436 u64 mac_rx_pfc_pri7_pkt_num; 437 u64 mac_tx_total_pkt_num; 438 u64 mac_tx_total_oct_num; 439 u64 mac_tx_good_pkt_num; 440 u64 mac_tx_bad_pkt_num; 441 u64 mac_tx_good_oct_num; 442 u64 mac_tx_bad_oct_num; 443 u64 mac_tx_uni_pkt_num; 444 u64 mac_tx_multi_pkt_num; 445 u64 mac_tx_broad_pkt_num; 446 u64 mac_tx_undersize_pkt_num; 447 u64 mac_tx_oversize_pkt_num; 448 u64 mac_tx_64_oct_pkt_num; 449 u64 mac_tx_65_127_oct_pkt_num; 450 u64 mac_tx_128_255_oct_pkt_num; 451 u64 mac_tx_256_511_oct_pkt_num; 452 u64 mac_tx_512_1023_oct_pkt_num; 453 u64 mac_tx_1024_1518_oct_pkt_num; 454 u64 mac_tx_1519_2047_oct_pkt_num; 455 u64 mac_tx_2048_4095_oct_pkt_num; 456 u64 mac_tx_4096_8191_oct_pkt_num; 457 u64 rsv1; 458 u64 mac_tx_8192_9216_oct_pkt_num; 459 u64 mac_tx_9217_12287_oct_pkt_num; 460 u64 mac_tx_12288_16383_oct_pkt_num; 461 u64 mac_tx_1519_max_good_oct_pkt_num; 462 u64 mac_tx_1519_max_bad_oct_pkt_num; 463 464 u64 mac_rx_total_pkt_num; 465 u64 mac_rx_total_oct_num; 466 u64 mac_rx_good_pkt_num; 467 u64 mac_rx_bad_pkt_num; 468 u64 mac_rx_good_oct_num; 469 u64 mac_rx_bad_oct_num; 470 u64 mac_rx_uni_pkt_num; 471 u64 mac_rx_multi_pkt_num; 472 u64 mac_rx_broad_pkt_num; 473 u64 mac_rx_undersize_pkt_num; 474 u64 mac_rx_oversize_pkt_num; 475 u64 mac_rx_64_oct_pkt_num; 476 u64 mac_rx_65_127_oct_pkt_num; 477 u64 mac_rx_128_255_oct_pkt_num; 478 u64 mac_rx_256_511_oct_pkt_num; 479 u64 mac_rx_512_1023_oct_pkt_num; 480 u64 mac_rx_1024_1518_oct_pkt_num; 481 u64 mac_rx_1519_2047_oct_pkt_num; 482 u64 mac_rx_2048_4095_oct_pkt_num; 483 u64 mac_rx_4096_8191_oct_pkt_num; 484 u64 rsv2; 485 u64 mac_rx_8192_9216_oct_pkt_num; 486 u64 mac_rx_9217_12287_oct_pkt_num; 487 u64 mac_rx_12288_16383_oct_pkt_num; 488 u64 mac_rx_1519_max_good_oct_pkt_num; 489 u64 mac_rx_1519_max_bad_oct_pkt_num; 490 491 u64 mac_tx_fragment_pkt_num; 492 u64 mac_tx_undermin_pkt_num; 493 u64 mac_tx_jabber_pkt_num; 494 u64 mac_tx_err_all_pkt_num; 495 u64 mac_tx_from_app_good_pkt_num; 496 u64 mac_tx_from_app_bad_pkt_num; 497 u64 mac_rx_fragment_pkt_num; 498 u64 mac_rx_undermin_pkt_num; 499 u64 mac_rx_jabber_pkt_num; 500 u64 mac_rx_fcs_err_pkt_num; 501 u64 mac_rx_send_app_good_pkt_num; 502 u64 mac_rx_send_app_bad_pkt_num; 503 u64 mac_tx_pfc_pause_pkt_num; 504 u64 mac_rx_pfc_pause_pkt_num; 505 u64 mac_tx_ctrl_pkt_num; 506 u64 mac_rx_ctrl_pkt_num; 507 508 /* duration of pfc */ 509 u64 mac_tx_pfc_pri0_xoff_time; 510 u64 mac_tx_pfc_pri1_xoff_time; 511 u64 mac_tx_pfc_pri2_xoff_time; 512 u64 mac_tx_pfc_pri3_xoff_time; 513 u64 mac_tx_pfc_pri4_xoff_time; 514 u64 mac_tx_pfc_pri5_xoff_time; 515 u64 mac_tx_pfc_pri6_xoff_time; 516 u64 mac_tx_pfc_pri7_xoff_time; 517 u64 mac_rx_pfc_pri0_xoff_time; 518 u64 mac_rx_pfc_pri1_xoff_time; 519 u64 mac_rx_pfc_pri2_xoff_time; 520 u64 mac_rx_pfc_pri3_xoff_time; 521 u64 mac_rx_pfc_pri4_xoff_time; 522 u64 mac_rx_pfc_pri5_xoff_time; 523 u64 mac_rx_pfc_pri6_xoff_time; 524 u64 mac_rx_pfc_pri7_xoff_time; 525 526 /* duration of pause */ 527 u64 mac_tx_pause_xoff_time; 528 u64 mac_rx_pause_xoff_time; 529 }; 530 531 #define HCLGE_STATS_TIMER_INTERVAL 300UL 532 533 struct hclge_vlan_type_cfg { 534 u16 rx_ot_fst_vlan_type; 535 u16 rx_ot_sec_vlan_type; 536 u16 rx_in_fst_vlan_type; 537 u16 rx_in_sec_vlan_type; 538 u16 tx_ot_vlan_type; 539 u16 tx_in_vlan_type; 540 }; 541 542 enum HCLGE_FD_MODE { 543 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1, 544 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2, 545 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1, 546 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2, 547 }; 548 549 enum HCLGE_FD_KEY_TYPE { 550 HCLGE_FD_KEY_BASE_ON_PTYPE, 551 HCLGE_FD_KEY_BASE_ON_TUPLE, 552 }; 553 554 enum HCLGE_FD_STAGE { 555 HCLGE_FD_STAGE_1, 556 HCLGE_FD_STAGE_2, 557 MAX_STAGE_NUM, 558 }; 559 560 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet 561 * INNER_XXX indicate tuples in tunneled header of tunnel packet or 562 * tuples of non-tunnel packet 563 */ 564 enum HCLGE_FD_TUPLE { 565 OUTER_DST_MAC, 566 OUTER_SRC_MAC, 567 OUTER_VLAN_TAG_FST, 568 OUTER_VLAN_TAG_SEC, 569 OUTER_ETH_TYPE, 570 OUTER_L2_RSV, 571 OUTER_IP_TOS, 572 OUTER_IP_PROTO, 573 OUTER_SRC_IP, 574 OUTER_DST_IP, 575 OUTER_L3_RSV, 576 OUTER_SRC_PORT, 577 OUTER_DST_PORT, 578 OUTER_L4_RSV, 579 OUTER_TUN_VNI, 580 OUTER_TUN_FLOW_ID, 581 INNER_DST_MAC, 582 INNER_SRC_MAC, 583 INNER_VLAN_TAG_FST, 584 INNER_VLAN_TAG_SEC, 585 INNER_ETH_TYPE, 586 INNER_L2_RSV, 587 INNER_IP_TOS, 588 INNER_IP_PROTO, 589 INNER_SRC_IP, 590 INNER_DST_IP, 591 INNER_L3_RSV, 592 INNER_SRC_PORT, 593 INNER_DST_PORT, 594 INNER_L4_RSV, 595 MAX_TUPLE, 596 }; 597 598 #define HCLGE_FD_TUPLE_USER_DEF_TUPLES \ 599 (BIT(INNER_L2_RSV) | BIT(INNER_L3_RSV) | BIT(INNER_L4_RSV)) 600 601 enum HCLGE_FD_META_DATA { 602 PACKET_TYPE_ID, 603 IP_FRAGEMENT, 604 ROCE_TYPE, 605 NEXT_KEY, 606 VLAN_NUMBER, 607 SRC_VPORT, 608 DST_VPORT, 609 TUNNEL_PACKET, 610 MAX_META_DATA, 611 }; 612 613 enum HCLGE_FD_KEY_OPT { 614 KEY_OPT_U8, 615 KEY_OPT_LE16, 616 KEY_OPT_LE32, 617 KEY_OPT_MAC, 618 KEY_OPT_IP, 619 KEY_OPT_VNI, 620 }; 621 622 struct key_info { 623 u8 key_type; 624 u8 key_length; /* use bit as unit */ 625 enum HCLGE_FD_KEY_OPT key_opt; 626 int offset; 627 int moffset; 628 }; 629 630 #define MAX_KEY_LENGTH 400 631 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4) 632 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4) 633 #define MAX_META_DATA_LENGTH 32 634 635 #define HCLGE_FD_MAX_USER_DEF_OFFSET 9000 636 #define HCLGE_FD_USER_DEF_DATA GENMASK(15, 0) 637 #define HCLGE_FD_USER_DEF_OFFSET GENMASK(15, 0) 638 #define HCLGE_FD_USER_DEF_OFFSET_UNMASK GENMASK(15, 0) 639 640 /* assigned by firmware, the real filter number for each pf may be less */ 641 #define MAX_FD_FILTER_NUM 4096 642 #define HCLGE_ARFS_EXPIRE_INTERVAL 5UL 643 644 enum HCLGE_FD_ACTIVE_RULE_TYPE { 645 HCLGE_FD_RULE_NONE, 646 HCLGE_FD_ARFS_ACTIVE, 647 HCLGE_FD_EP_ACTIVE, 648 HCLGE_FD_TC_FLOWER_ACTIVE, 649 }; 650 651 enum HCLGE_FD_PACKET_TYPE { 652 NIC_PACKET, 653 ROCE_PACKET, 654 }; 655 656 enum HCLGE_FD_ACTION { 657 HCLGE_FD_ACTION_SELECT_QUEUE, 658 HCLGE_FD_ACTION_DROP_PACKET, 659 HCLGE_FD_ACTION_SELECT_TC, 660 }; 661 662 enum HCLGE_FD_NODE_STATE { 663 HCLGE_FD_TO_ADD, 664 HCLGE_FD_TO_DEL, 665 HCLGE_FD_ACTIVE, 666 HCLGE_FD_DELETED, 667 }; 668 669 enum HCLGE_FD_USER_DEF_LAYER { 670 HCLGE_FD_USER_DEF_NONE, 671 HCLGE_FD_USER_DEF_L2, 672 HCLGE_FD_USER_DEF_L3, 673 HCLGE_FD_USER_DEF_L4, 674 }; 675 676 #define HCLGE_FD_USER_DEF_LAYER_NUM 3 677 struct hclge_fd_user_def_cfg { 678 u16 ref_cnt; 679 u16 offset; 680 }; 681 682 struct hclge_fd_user_def_info { 683 enum HCLGE_FD_USER_DEF_LAYER layer; 684 u16 data; 685 u16 data_mask; 686 u16 offset; 687 }; 688 689 struct hclge_fd_key_cfg { 690 u8 key_sel; 691 u8 inner_sipv6_word_en; 692 u8 inner_dipv6_word_en; 693 u8 outer_sipv6_word_en; 694 u8 outer_dipv6_word_en; 695 u32 tuple_active; 696 u32 meta_data_active; 697 }; 698 699 struct hclge_fd_cfg { 700 u8 fd_mode; 701 u16 max_key_length; /* use bit as unit */ 702 u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */ 703 u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */ 704 struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM]; 705 struct hclge_fd_user_def_cfg user_def_cfg[HCLGE_FD_USER_DEF_LAYER_NUM]; 706 }; 707 708 #define IPV4_INDEX 3 709 #define IPV6_SIZE 4 710 struct hclge_fd_rule_tuples { 711 u8 src_mac[ETH_ALEN]; 712 u8 dst_mac[ETH_ALEN]; 713 /* Be compatible for ip address of both ipv4 and ipv6. 714 * For ipv4 address, we store it in src/dst_ip[3]. 715 */ 716 u32 src_ip[IPV6_SIZE]; 717 u32 dst_ip[IPV6_SIZE]; 718 u16 src_port; 719 u16 dst_port; 720 u16 vlan_tag1; 721 u16 ether_proto; 722 u16 l2_user_def; 723 u16 l3_user_def; 724 u32 l4_user_def; 725 u8 ip_tos; 726 u8 ip_proto; 727 }; 728 729 struct hclge_fd_rule { 730 struct hlist_node rule_node; 731 struct hclge_fd_rule_tuples tuples; 732 struct hclge_fd_rule_tuples tuples_mask; 733 u32 unused_tuple; 734 u32 flow_type; 735 union { 736 struct { 737 unsigned long cookie; 738 u8 tc; 739 } cls_flower; 740 struct { 741 u16 flow_id; /* only used for arfs */ 742 } arfs; 743 struct { 744 struct hclge_fd_user_def_info user_def; 745 } ep; 746 }; 747 u16 queue_id; 748 u16 vf_id; 749 u16 location; 750 enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type; 751 enum HCLGE_FD_NODE_STATE state; 752 u8 action; 753 }; 754 755 struct hclge_fd_ad_data { 756 u16 ad_id; 757 u8 drop_packet; 758 u8 forward_to_direct_queue; 759 u16 queue_id; 760 u8 use_counter; 761 u8 counter_id; 762 u8 use_next_stage; 763 u8 write_rule_id_to_bd; 764 u8 next_input_key; 765 u16 rule_id; 766 u16 tc_size; 767 u8 override_tc; 768 }; 769 770 enum HCLGE_MAC_NODE_STATE { 771 HCLGE_MAC_TO_ADD, 772 HCLGE_MAC_TO_DEL, 773 HCLGE_MAC_ACTIVE 774 }; 775 776 struct hclge_mac_node { 777 struct list_head node; 778 enum HCLGE_MAC_NODE_STATE state; 779 u8 mac_addr[ETH_ALEN]; 780 }; 781 782 enum HCLGE_MAC_ADDR_TYPE { 783 HCLGE_MAC_ADDR_UC, 784 HCLGE_MAC_ADDR_MC 785 }; 786 787 struct hclge_vport_vlan_cfg { 788 struct list_head node; 789 int hd_tbl_status; 790 u16 vlan_id; 791 }; 792 793 struct hclge_rst_stats { 794 u32 reset_done_cnt; /* the number of reset has completed */ 795 u32 hw_reset_done_cnt; /* the number of HW reset has completed */ 796 u32 pf_rst_cnt; /* the number of PF reset */ 797 u32 flr_rst_cnt; /* the number of FLR */ 798 u32 global_rst_cnt; /* the number of GLOBAL */ 799 u32 imp_rst_cnt; /* the number of IMP reset */ 800 u32 reset_cnt; /* the number of reset */ 801 u32 reset_fail_cnt; /* the number of reset fail */ 802 }; 803 804 /* time and register status when mac tunnel interruption occur */ 805 struct hclge_mac_tnl_stats { 806 u64 time; 807 u32 status; 808 }; 809 810 #define HCLGE_RESET_INTERVAL (10 * HZ) 811 #define HCLGE_WAIT_RESET_DONE 100 812 813 #pragma pack(1) 814 struct hclge_vf_vlan_cfg { 815 u8 mbx_cmd; 816 u8 subcode; 817 union { 818 struct { 819 u8 is_kill; 820 u16 vlan; 821 u16 proto; 822 }; 823 u8 enable; 824 }; 825 }; 826 827 #pragma pack() 828 829 /* For each bit of TCAM entry, it uses a pair of 'x' and 830 * 'y' to indicate which value to match, like below: 831 * ---------------------------------- 832 * | bit x | bit y | search value | 833 * ---------------------------------- 834 * | 0 | 0 | always hit | 835 * ---------------------------------- 836 * | 1 | 0 | match '0' | 837 * ---------------------------------- 838 * | 0 | 1 | match '1' | 839 * ---------------------------------- 840 * | 1 | 1 | invalid | 841 * ---------------------------------- 842 * Then for input key(k) and mask(v), we can calculate the value by 843 * the formulae: 844 * x = (~k) & v 845 * y = (k ^ ~v) & k 846 */ 847 #define calc_x(x, k, v) (x = ~(k) & (v)) 848 #define calc_y(y, k, v) \ 849 do { \ 850 const typeof(k) _k_ = (k); \ 851 const typeof(v) _v_ = (v); \ 852 (y) = (_k_ ^ ~_v_) & (_k_); \ 853 } while (0) 854 855 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f)) 856 #define HCLGE_STATS_READ(p, offset) (*(u64 *)((u8 *)(p) + (offset))) 857 858 #define HCLGE_MAC_TNL_LOG_SIZE 8 859 #define HCLGE_VPORT_NUM 256 860 struct hclge_dev { 861 struct pci_dev *pdev; 862 struct hnae3_ae_dev *ae_dev; 863 struct hclge_hw hw; 864 struct hclge_misc_vector misc_vector; 865 struct hclge_mac_stats mac_stats; 866 unsigned long state; 867 unsigned long flr_state; 868 unsigned long last_reset_time; 869 870 enum hnae3_reset_type reset_type; 871 enum hnae3_reset_type reset_level; 872 unsigned long default_reset_request; 873 unsigned long reset_request; /* reset has been requested */ 874 unsigned long reset_pending; /* client rst is pending to be served */ 875 struct hclge_rst_stats rst_stats; 876 struct semaphore reset_sem; /* protect reset process */ 877 u32 fw_version; 878 u16 num_tqps; /* Num task queue pairs of this PF */ 879 u16 num_req_vfs; /* Num VFs requested for this PF */ 880 881 u16 base_tqp_pid; /* Base task tqp physical id of this PF */ 882 u16 alloc_rss_size; /* Allocated RSS task queue */ 883 u16 vf_rss_size_max; /* HW defined VF max RSS task queue */ 884 u16 pf_rss_size_max; /* HW defined PF max RSS task queue */ 885 u32 tx_spare_buf_size; /* HW defined TX spare buffer size */ 886 887 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */ 888 u16 num_alloc_vport; /* Num vports this driver supports */ 889 u32 numa_node_mask; 890 u16 rx_buf_len; 891 u16 num_tx_desc; /* desc num of per tx queue */ 892 u16 num_rx_desc; /* desc num of per rx queue */ 893 u8 hw_tc_map; 894 enum hclge_fc_mode fc_mode_last_time; 895 u8 support_sfp_query; 896 897 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1 898 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2 899 u8 tx_sch_mode; 900 u8 tc_max; 901 u8 pfc_max; 902 903 u8 default_up; 904 u8 dcbx_cap; 905 struct hclge_tm_info tm_info; 906 907 u16 num_msi; 908 u16 num_msi_left; 909 u16 num_msi_used; 910 u16 *vector_status; 911 int *vector_irq; 912 u16 num_nic_msi; /* Num of nic vectors for this PF */ 913 u16 num_roce_msi; /* Num of roce vectors for this PF */ 914 915 unsigned long service_timer_period; 916 unsigned long service_timer_previous; 917 struct timer_list reset_timer; 918 struct delayed_work service_task; 919 920 bool cur_promisc; 921 int num_alloc_vfs; /* Actual number of VFs allocated */ 922 923 struct hclge_tqp *htqp; 924 struct hclge_vport *vport; 925 926 struct dentry *hclge_dbgfs; 927 928 struct hnae3_client *nic_client; 929 struct hnae3_client *roce_client; 930 931 #define HCLGE_FLAG_MAIN BIT(0) 932 #define HCLGE_FLAG_DCB_CAPABLE BIT(1) 933 #define HCLGE_FLAG_DCB_ENABLE BIT(2) 934 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3) 935 u32 flag; 936 937 u32 pkt_buf_size; /* Total pf buf size for tx/rx */ 938 u32 tx_buf_size; /* Tx buffer size for each TC */ 939 u32 dv_buf_size; /* Dv buffer size for each TC */ 940 941 u32 mps; /* Max packet size */ 942 /* vport_lock protect resource shared by vports */ 943 struct mutex vport_lock; 944 945 struct hclge_vlan_type_cfg vlan_type_cfg; 946 947 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 948 unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 949 950 unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 951 952 struct hclge_fd_cfg fd_cfg; 953 struct hlist_head fd_rule_list; 954 spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */ 955 u16 hclge_fd_rule_num; 956 unsigned long serv_processed_cnt; 957 unsigned long last_serv_processed; 958 unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)]; 959 enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type; 960 u8 fd_en; 961 bool gro_en; 962 963 u16 wanted_umv_size; 964 /* max available unicast mac vlan space */ 965 u16 max_umv_size; 966 /* private unicast mac vlan space, it's same for PF and its VFs */ 967 u16 priv_umv_size; 968 /* unicast mac vlan space shared by PF and its VFs */ 969 u16 share_umv_size; 970 /* multicast mac address number used by PF and its VFs */ 971 u16 used_mc_mac_num; 972 973 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats, 974 HCLGE_MAC_TNL_LOG_SIZE); 975 976 /* affinity mask and notify for misc interrupt */ 977 cpumask_t affinity_mask; 978 struct hclge_ptp *ptp; 979 struct devlink *devlink; 980 }; 981 982 /* VPort level vlan tag configuration for TX direction */ 983 struct hclge_tx_vtag_cfg { 984 bool accept_tag1; /* Whether accept tag1 packet from host */ 985 bool accept_untag1; /* Whether accept untag1 packet from host */ 986 bool accept_tag2; 987 bool accept_untag2; 988 bool insert_tag1_en; /* Whether insert inner vlan tag */ 989 bool insert_tag2_en; /* Whether insert outer vlan tag */ 990 u16 default_tag1; /* The default inner vlan tag to insert */ 991 u16 default_tag2; /* The default outer vlan tag to insert */ 992 bool tag_shift_mode_en; 993 }; 994 995 /* VPort level vlan tag configuration for RX direction */ 996 struct hclge_rx_vtag_cfg { 997 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ 998 bool strip_tag1_en; /* Whether strip inner vlan tag */ 999 bool strip_tag2_en; /* Whether strip outer vlan tag */ 1000 bool vlan1_vlan_prionly; /* Inner vlan tag up to descriptor enable */ 1001 bool vlan2_vlan_prionly; /* Outer vlan tag up to descriptor enable */ 1002 bool strip_tag1_discard_en; /* Inner vlan tag discard for BD enable */ 1003 bool strip_tag2_discard_en; /* Outer vlan tag discard for BD enable */ 1004 }; 1005 1006 struct hclge_rss_tuple_cfg { 1007 u8 ipv4_tcp_en; 1008 u8 ipv4_udp_en; 1009 u8 ipv4_sctp_en; 1010 u8 ipv4_fragment_en; 1011 u8 ipv6_tcp_en; 1012 u8 ipv6_udp_en; 1013 u8 ipv6_sctp_en; 1014 u8 ipv6_fragment_en; 1015 }; 1016 1017 enum HCLGE_VPORT_STATE { 1018 HCLGE_VPORT_STATE_ALIVE, 1019 HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 1020 HCLGE_VPORT_STATE_PROMISC_CHANGE, 1021 HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 1022 HCLGE_VPORT_STATE_MAX 1023 }; 1024 1025 struct hclge_vlan_info { 1026 u16 vlan_proto; /* so far support 802.1Q only */ 1027 u16 qos; 1028 u16 vlan_tag; 1029 }; 1030 1031 struct hclge_port_base_vlan_config { 1032 u16 state; 1033 struct hclge_vlan_info vlan_info; 1034 }; 1035 1036 struct hclge_vf_info { 1037 int link_state; 1038 u8 mac[ETH_ALEN]; 1039 u32 spoofchk; 1040 u32 max_tx_rate; 1041 u32 trusted; 1042 u8 request_uc_en; 1043 u8 request_mc_en; 1044 u8 request_bc_en; 1045 }; 1046 1047 struct hclge_vport { 1048 u16 alloc_tqps; /* Allocated Tx/Rx queues */ 1049 1050 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */ 1051 /* User configured lookup table entries */ 1052 u16 *rss_indirection_tbl; 1053 int rss_algo; /* User configured hash algorithm */ 1054 /* User configured rss tuple sets */ 1055 struct hclge_rss_tuple_cfg rss_tuple_sets; 1056 1057 u16 alloc_rss_size; 1058 1059 u16 qs_offset; 1060 u32 bw_limit; /* VSI BW Limit (0 = disabled) */ 1061 u8 dwrr; 1062 1063 bool req_vlan_fltr_en; 1064 bool cur_vlan_fltr_en; 1065 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 1066 struct hclge_port_base_vlan_config port_base_vlan_cfg; 1067 struct hclge_tx_vtag_cfg txvlan_cfg; 1068 struct hclge_rx_vtag_cfg rxvlan_cfg; 1069 1070 u16 used_umv_num; 1071 1072 u16 vport_id; 1073 struct hclge_dev *back; /* Back reference to associated dev */ 1074 struct hnae3_handle nic; 1075 struct hnae3_handle roce; 1076 1077 unsigned long state; 1078 unsigned long last_active_jiffies; 1079 u32 mps; /* Max packet size */ 1080 struct hclge_vf_info vf_info; 1081 1082 u8 overflow_promisc_flags; 1083 u8 last_promisc_flags; 1084 1085 spinlock_t mac_list_lock; /* protect mac address need to add/detele */ 1086 struct list_head uc_mac_list; /* Store VF unicast table */ 1087 struct list_head mc_mac_list; /* Store VF multicast table */ 1088 struct list_head vlan_list; /* Store VF vlan table */ 1089 }; 1090 1091 struct hclge_speed_bit_map { 1092 u32 speed; 1093 u32 speed_bit; 1094 }; 1095 1096 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 1097 bool en_mc_pmc, bool en_bc_pmc); 1098 int hclge_add_uc_addr_common(struct hclge_vport *vport, 1099 const unsigned char *addr); 1100 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 1101 const unsigned char *addr); 1102 int hclge_add_mc_addr_common(struct hclge_vport *vport, 1103 const unsigned char *addr); 1104 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 1105 const unsigned char *addr); 1106 1107 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle); 1108 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 1109 int vector_id, bool en, 1110 struct hnae3_ring_chain_node *ring_chain); 1111 1112 static inline int hclge_get_queue_id(struct hnae3_queue *queue) 1113 { 1114 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q); 1115 1116 return tqp->index; 1117 } 1118 1119 static inline bool hclge_is_reset_pending(struct hclge_dev *hdev) 1120 { 1121 return !!hdev->reset_pending; 1122 } 1123 1124 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport); 1125 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex); 1126 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 1127 u16 vlan_id, bool is_kill); 1128 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable); 1129 1130 int hclge_buffer_alloc(struct hclge_dev *hdev); 1131 int hclge_rss_init_hw(struct hclge_dev *hdev); 1132 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev); 1133 1134 void hclge_mbx_handler(struct hclge_dev *hdev); 1135 int hclge_reset_tqp(struct hnae3_handle *handle); 1136 int hclge_cfg_flowctrl(struct hclge_dev *hdev); 1137 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id); 1138 int hclge_vport_start(struct hclge_vport *vport); 1139 void hclge_vport_stop(struct hclge_vport *vport); 1140 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu); 1141 int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, 1142 char *buf, int len); 1143 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id); 1144 int hclge_notify_client(struct hclge_dev *hdev, 1145 enum hnae3_reset_notify_type type); 1146 int hclge_update_mac_list(struct hclge_vport *vport, 1147 enum HCLGE_MAC_NODE_STATE state, 1148 enum HCLGE_MAC_ADDR_TYPE mac_type, 1149 const unsigned char *addr); 1150 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 1151 const u8 *old_addr, const u8 *new_addr); 1152 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 1153 enum HCLGE_MAC_ADDR_TYPE mac_type); 1154 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list); 1155 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev); 1156 void hclge_restore_mac_table_common(struct hclge_vport *vport); 1157 void hclge_restore_vport_vlan_table(struct hclge_vport *vport); 1158 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 1159 struct hclge_vlan_info *vlan_info); 1160 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid, 1161 u16 state, 1162 struct hclge_vlan_info *vlan_info); 1163 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time); 1164 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, 1165 struct hclge_desc *desc); 1166 void hclge_report_hw_error(struct hclge_dev *hdev, 1167 enum hnae3_hw_error_type type); 1168 void hclge_inform_vf_promisc_info(struct hclge_vport *vport); 1169 int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len); 1170 int hclge_push_vf_link_status(struct hclge_vport *vport); 1171 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en); 1172 int hclge_mac_update_stats(struct hclge_dev *hdev); 1173 #endif 1174