1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_MAIN_H 5 #define __HCLGE_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include <linux/phy.h> 9 #include <linux/if_vlan.h> 10 #include <linux/kfifo.h> 11 12 #include "hclge_cmd.h" 13 #include "hnae3.h" 14 15 #define HCLGE_MOD_VERSION "1.0" 16 #define HCLGE_DRIVER_NAME "hclge" 17 18 #define HCLGE_MAX_PF_NUM 8 19 20 #define HCLGE_RD_FIRST_STATS_NUM 2 21 #define HCLGE_RD_OTHER_STATS_NUM 4 22 23 #define HCLGE_INVALID_VPORT 0xffff 24 25 #define HCLGE_PF_CFG_BLOCK_SIZE 32 26 #define HCLGE_PF_CFG_DESC_NUM \ 27 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) 28 29 #define HCLGE_VECTOR_REG_BASE 0x20000 30 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400 31 32 #define HCLGE_VECTOR_REG_OFFSET 0x4 33 #define HCLGE_VECTOR_VF_OFFSET 0x100000 34 35 #define HCLGE_CMDQ_TX_ADDR_L_REG 0x27000 36 #define HCLGE_CMDQ_TX_ADDR_H_REG 0x27004 37 #define HCLGE_CMDQ_TX_DEPTH_REG 0x27008 38 #define HCLGE_CMDQ_TX_TAIL_REG 0x27010 39 #define HCLGE_CMDQ_TX_HEAD_REG 0x27014 40 #define HCLGE_CMDQ_RX_ADDR_L_REG 0x27018 41 #define HCLGE_CMDQ_RX_ADDR_H_REG 0x2701C 42 #define HCLGE_CMDQ_RX_DEPTH_REG 0x27020 43 #define HCLGE_CMDQ_RX_TAIL_REG 0x27024 44 #define HCLGE_CMDQ_RX_HEAD_REG 0x27028 45 #define HCLGE_CMDQ_INTR_SRC_REG 0x27100 46 #define HCLGE_CMDQ_INTR_STS_REG 0x27104 47 #define HCLGE_CMDQ_INTR_EN_REG 0x27108 48 #define HCLGE_CMDQ_INTR_GEN_REG 0x2710C 49 50 /* bar registers for common func */ 51 #define HCLGE_VECTOR0_OTER_EN_REG 0x20600 52 #define HCLGE_RAS_OTHER_STS_REG 0x20B00 53 #define HCLGE_FUNC_RESET_STS_REG 0x20C00 54 #define HCLGE_GRO_EN_REG 0x28000 55 56 /* bar registers for rcb */ 57 #define HCLGE_RING_RX_ADDR_L_REG 0x80000 58 #define HCLGE_RING_RX_ADDR_H_REG 0x80004 59 #define HCLGE_RING_RX_BD_NUM_REG 0x80008 60 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C 61 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014 62 #define HCLGE_RING_RX_TAIL_REG 0x80018 63 #define HCLGE_RING_RX_HEAD_REG 0x8001C 64 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020 65 #define HCLGE_RING_RX_OFFSET_REG 0x80024 66 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028 67 #define HCLGE_RING_RX_STASH_REG 0x80030 68 #define HCLGE_RING_RX_BD_ERR_REG 0x80034 69 #define HCLGE_RING_TX_ADDR_L_REG 0x80040 70 #define HCLGE_RING_TX_ADDR_H_REG 0x80044 71 #define HCLGE_RING_TX_BD_NUM_REG 0x80048 72 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C 73 #define HCLGE_RING_TX_TC_REG 0x80050 74 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054 75 #define HCLGE_RING_TX_TAIL_REG 0x80058 76 #define HCLGE_RING_TX_HEAD_REG 0x8005C 77 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060 78 #define HCLGE_RING_TX_OFFSET_REG 0x80064 79 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068 80 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070 81 #define HCLGE_RING_TX_BD_ERR_REG 0x80074 82 #define HCLGE_RING_EN_REG 0x80090 83 84 /* bar registers for tqp interrupt */ 85 #define HCLGE_TQP_INTR_CTRL_REG 0x20000 86 #define HCLGE_TQP_INTR_GL0_REG 0x20100 87 #define HCLGE_TQP_INTR_GL1_REG 0x20200 88 #define HCLGE_TQP_INTR_GL2_REG 0x20300 89 #define HCLGE_TQP_INTR_RL_REG 0x20900 90 91 #define HCLGE_RSS_IND_TBL_SIZE 512 92 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0) 93 #define HCLGE_RSS_KEY_SIZE 40 94 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0 95 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1 96 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2 97 #define HCLGE_RSS_HASH_ALGO_MASK GENMASK(3, 0) 98 #define HCLGE_RSS_CFG_TBL_NUM \ 99 (HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE) 100 101 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 102 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 103 #define HCLGE_D_PORT_BIT BIT(0) 104 #define HCLGE_S_PORT_BIT BIT(1) 105 #define HCLGE_D_IP_BIT BIT(2) 106 #define HCLGE_S_IP_BIT BIT(3) 107 #define HCLGE_V_TAG_BIT BIT(4) 108 109 #define HCLGE_RSS_TC_SIZE_0 1 110 #define HCLGE_RSS_TC_SIZE_1 2 111 #define HCLGE_RSS_TC_SIZE_2 4 112 #define HCLGE_RSS_TC_SIZE_3 8 113 #define HCLGE_RSS_TC_SIZE_4 16 114 #define HCLGE_RSS_TC_SIZE_5 32 115 #define HCLGE_RSS_TC_SIZE_6 64 116 #define HCLGE_RSS_TC_SIZE_7 128 117 118 #define HCLGE_UMV_TBL_SIZE 3072 119 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \ 120 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM) 121 122 #define HCLGE_TQP_RESET_TRY_TIMES 10 123 124 #define HCLGE_PHY_PAGE_MDIX 0 125 #define HCLGE_PHY_PAGE_COPPER 0 126 127 /* Page Selection Reg. */ 128 #define HCLGE_PHY_PAGE_REG 22 129 130 /* Copper Specific Control Register */ 131 #define HCLGE_PHY_CSC_REG 16 132 133 /* Copper Specific Status Register */ 134 #define HCLGE_PHY_CSS_REG 17 135 136 #define HCLGE_PHY_MDIX_CTRL_S 5 137 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) 138 139 #define HCLGE_PHY_MDIX_STATUS_B 6 140 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11 141 142 /* Factor used to calculate offset and bitmap of VF num */ 143 #define HCLGE_VF_NUM_PER_CMD 64 144 #define HCLGE_VF_NUM_PER_BYTE 8 145 146 enum HLCGE_PORT_TYPE { 147 HOST_PORT, 148 NETWORK_PORT 149 }; 150 151 #define HCLGE_PF_ID_S 0 152 #define HCLGE_PF_ID_M GENMASK(2, 0) 153 #define HCLGE_VF_ID_S 3 154 #define HCLGE_VF_ID_M GENMASK(10, 3) 155 #define HCLGE_PORT_TYPE_B 11 156 #define HCLGE_NETWORK_PORT_ID_S 0 157 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0) 158 159 /* Reset related Registers */ 160 #define HCLGE_PF_OTHER_INT_REG 0x20600 161 #define HCLGE_MISC_RESET_STS_REG 0x20700 162 #define HCLGE_MISC_VECTOR_INT_STS 0x20800 163 #define HCLGE_GLOBAL_RESET_REG 0x20A00 164 #define HCLGE_GLOBAL_RESET_BIT 0 165 #define HCLGE_CORE_RESET_BIT 1 166 #define HCLGE_IMP_RESET_BIT 2 167 #define HCLGE_FUN_RST_ING 0x20C00 168 #define HCLGE_FUN_RST_ING_B 0 169 170 /* Vector0 register bits define */ 171 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5 172 #define HCLGE_VECTOR0_CORERESET_INT_B 6 173 #define HCLGE_VECTOR0_IMPRESET_INT_B 7 174 175 /* Vector0 interrupt CMDQ event source register(RW) */ 176 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100 177 /* CMDQ register bits for RX event(=MBX event) */ 178 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 179 180 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1 181 182 #define HCLGE_MAC_DEFAULT_FRAME \ 183 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN) 184 #define HCLGE_MAC_MIN_FRAME 64 185 #define HCLGE_MAC_MAX_FRAME 9728 186 187 #define HCLGE_SUPPORT_1G_BIT BIT(0) 188 #define HCLGE_SUPPORT_10G_BIT BIT(1) 189 #define HCLGE_SUPPORT_25G_BIT BIT(2) 190 #define HCLGE_SUPPORT_50G_BIT BIT(3) 191 #define HCLGE_SUPPORT_100G_BIT BIT(4) 192 #define HCLGE_SUPPORT_100M_BIT BIT(6) 193 #define HCLGE_SUPPORT_10M_BIT BIT(7) 194 #define HCLGE_SUPPORT_GE \ 195 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT) 196 197 enum HCLGE_DEV_STATE { 198 HCLGE_STATE_REINITING, 199 HCLGE_STATE_DOWN, 200 HCLGE_STATE_DISABLED, 201 HCLGE_STATE_REMOVING, 202 HCLGE_STATE_SERVICE_INITED, 203 HCLGE_STATE_SERVICE_SCHED, 204 HCLGE_STATE_RST_SERVICE_SCHED, 205 HCLGE_STATE_RST_HANDLING, 206 HCLGE_STATE_MBX_SERVICE_SCHED, 207 HCLGE_STATE_MBX_HANDLING, 208 HCLGE_STATE_STATISTICS_UPDATING, 209 HCLGE_STATE_CMD_DISABLE, 210 HCLGE_STATE_MAX 211 }; 212 213 enum hclge_evt_cause { 214 HCLGE_VECTOR0_EVENT_RST, 215 HCLGE_VECTOR0_EVENT_MBX, 216 HCLGE_VECTOR0_EVENT_ERR, 217 HCLGE_VECTOR0_EVENT_OTHER, 218 }; 219 220 #define HCLGE_MPF_ENBALE 1 221 222 enum HCLGE_MAC_SPEED { 223 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */ 224 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */ 225 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */ 226 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ 227 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ 228 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ 229 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ 230 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ 231 HCLGE_MAC_SPEED_100G = 100000 /* 100000 Mbps = 100 Gbps */ 232 }; 233 234 enum HCLGE_MAC_DUPLEX { 235 HCLGE_MAC_HALF, 236 HCLGE_MAC_FULL 237 }; 238 239 struct hclge_mac { 240 u8 phy_addr; 241 u8 flag; 242 u8 media_type; 243 u8 mac_addr[ETH_ALEN]; 244 u8 autoneg; 245 u8 duplex; 246 u32 speed; 247 int link; /* store the link status of mac & phy (if phy exit)*/ 248 struct phy_device *phydev; 249 struct mii_bus *mdio_bus; 250 phy_interface_t phy_if; 251 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 252 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 253 }; 254 255 struct hclge_hw { 256 void __iomem *io_base; 257 struct hclge_mac mac; 258 int num_vec; 259 struct hclge_cmq cmq; 260 }; 261 262 /* TQP stats */ 263 struct hlcge_tqp_stats { 264 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 265 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 266 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 267 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 268 }; 269 270 struct hclge_tqp { 271 /* copy of device pointer from pci_dev, 272 * used when perform DMA mapping 273 */ 274 struct device *dev; 275 struct hnae3_queue q; 276 struct hlcge_tqp_stats tqp_stats; 277 u16 index; /* Global index in a NIC controller */ 278 279 bool alloced; 280 }; 281 282 enum hclge_fc_mode { 283 HCLGE_FC_NONE, 284 HCLGE_FC_RX_PAUSE, 285 HCLGE_FC_TX_PAUSE, 286 HCLGE_FC_FULL, 287 HCLGE_FC_PFC, 288 HCLGE_FC_DEFAULT 289 }; 290 291 #define HCLGE_PG_NUM 4 292 #define HCLGE_SCH_MODE_SP 0 293 #define HCLGE_SCH_MODE_DWRR 1 294 struct hclge_pg_info { 295 u8 pg_id; 296 u8 pg_sch_mode; /* 0: sp; 1: dwrr */ 297 u8 tc_bit_map; 298 u32 bw_limit; 299 u8 tc_dwrr[HNAE3_MAX_TC]; 300 }; 301 302 struct hclge_tc_info { 303 u8 tc_id; 304 u8 tc_sch_mode; /* 0: sp; 1: dwrr */ 305 u8 pgid; 306 u32 bw_limit; 307 }; 308 309 struct hclge_cfg { 310 u8 vmdq_vport_num; 311 u8 tc_num; 312 u16 tqp_desc_num; 313 u16 rx_buf_len; 314 u16 rss_size_max; 315 u8 phy_addr; 316 u8 media_type; 317 u8 mac_addr[ETH_ALEN]; 318 u8 default_speed; 319 u32 numa_node_map; 320 u8 speed_ability; 321 u16 umv_space; 322 }; 323 324 struct hclge_tm_info { 325 u8 num_tc; 326 u8 num_pg; /* It must be 1 if vNET-Base schd */ 327 u8 pg_dwrr[HCLGE_PG_NUM]; 328 u8 prio_tc[HNAE3_MAX_USER_PRIO]; 329 struct hclge_pg_info pg_info[HCLGE_PG_NUM]; 330 struct hclge_tc_info tc_info[HNAE3_MAX_TC]; 331 enum hclge_fc_mode fc_mode; 332 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */ 333 u8 pfc_en; /* PFC enabled or not for user priority */ 334 }; 335 336 struct hclge_comm_stats_str { 337 char desc[ETH_GSTRING_LEN]; 338 unsigned long offset; 339 }; 340 341 /* mac stats ,opcode id: 0x0032 */ 342 struct hclge_mac_stats { 343 u64 mac_tx_mac_pause_num; 344 u64 mac_rx_mac_pause_num; 345 u64 mac_tx_pfc_pri0_pkt_num; 346 u64 mac_tx_pfc_pri1_pkt_num; 347 u64 mac_tx_pfc_pri2_pkt_num; 348 u64 mac_tx_pfc_pri3_pkt_num; 349 u64 mac_tx_pfc_pri4_pkt_num; 350 u64 mac_tx_pfc_pri5_pkt_num; 351 u64 mac_tx_pfc_pri6_pkt_num; 352 u64 mac_tx_pfc_pri7_pkt_num; 353 u64 mac_rx_pfc_pri0_pkt_num; 354 u64 mac_rx_pfc_pri1_pkt_num; 355 u64 mac_rx_pfc_pri2_pkt_num; 356 u64 mac_rx_pfc_pri3_pkt_num; 357 u64 mac_rx_pfc_pri4_pkt_num; 358 u64 mac_rx_pfc_pri5_pkt_num; 359 u64 mac_rx_pfc_pri6_pkt_num; 360 u64 mac_rx_pfc_pri7_pkt_num; 361 u64 mac_tx_total_pkt_num; 362 u64 mac_tx_total_oct_num; 363 u64 mac_tx_good_pkt_num; 364 u64 mac_tx_bad_pkt_num; 365 u64 mac_tx_good_oct_num; 366 u64 mac_tx_bad_oct_num; 367 u64 mac_tx_uni_pkt_num; 368 u64 mac_tx_multi_pkt_num; 369 u64 mac_tx_broad_pkt_num; 370 u64 mac_tx_undersize_pkt_num; 371 u64 mac_tx_oversize_pkt_num; 372 u64 mac_tx_64_oct_pkt_num; 373 u64 mac_tx_65_127_oct_pkt_num; 374 u64 mac_tx_128_255_oct_pkt_num; 375 u64 mac_tx_256_511_oct_pkt_num; 376 u64 mac_tx_512_1023_oct_pkt_num; 377 u64 mac_tx_1024_1518_oct_pkt_num; 378 u64 mac_tx_1519_2047_oct_pkt_num; 379 u64 mac_tx_2048_4095_oct_pkt_num; 380 u64 mac_tx_4096_8191_oct_pkt_num; 381 u64 rsv0; 382 u64 mac_tx_8192_9216_oct_pkt_num; 383 u64 mac_tx_9217_12287_oct_pkt_num; 384 u64 mac_tx_12288_16383_oct_pkt_num; 385 u64 mac_tx_1519_max_good_oct_pkt_num; 386 u64 mac_tx_1519_max_bad_oct_pkt_num; 387 388 u64 mac_rx_total_pkt_num; 389 u64 mac_rx_total_oct_num; 390 u64 mac_rx_good_pkt_num; 391 u64 mac_rx_bad_pkt_num; 392 u64 mac_rx_good_oct_num; 393 u64 mac_rx_bad_oct_num; 394 u64 mac_rx_uni_pkt_num; 395 u64 mac_rx_multi_pkt_num; 396 u64 mac_rx_broad_pkt_num; 397 u64 mac_rx_undersize_pkt_num; 398 u64 mac_rx_oversize_pkt_num; 399 u64 mac_rx_64_oct_pkt_num; 400 u64 mac_rx_65_127_oct_pkt_num; 401 u64 mac_rx_128_255_oct_pkt_num; 402 u64 mac_rx_256_511_oct_pkt_num; 403 u64 mac_rx_512_1023_oct_pkt_num; 404 u64 mac_rx_1024_1518_oct_pkt_num; 405 u64 mac_rx_1519_2047_oct_pkt_num; 406 u64 mac_rx_2048_4095_oct_pkt_num; 407 u64 mac_rx_4096_8191_oct_pkt_num; 408 u64 rsv1; 409 u64 mac_rx_8192_9216_oct_pkt_num; 410 u64 mac_rx_9217_12287_oct_pkt_num; 411 u64 mac_rx_12288_16383_oct_pkt_num; 412 u64 mac_rx_1519_max_good_oct_pkt_num; 413 u64 mac_rx_1519_max_bad_oct_pkt_num; 414 415 u64 mac_tx_fragment_pkt_num; 416 u64 mac_tx_undermin_pkt_num; 417 u64 mac_tx_jabber_pkt_num; 418 u64 mac_tx_err_all_pkt_num; 419 u64 mac_tx_from_app_good_pkt_num; 420 u64 mac_tx_from_app_bad_pkt_num; 421 u64 mac_rx_fragment_pkt_num; 422 u64 mac_rx_undermin_pkt_num; 423 u64 mac_rx_jabber_pkt_num; 424 u64 mac_rx_fcs_err_pkt_num; 425 u64 mac_rx_send_app_good_pkt_num; 426 u64 mac_rx_send_app_bad_pkt_num; 427 u64 mac_tx_pfc_pause_pkt_num; 428 u64 mac_rx_pfc_pause_pkt_num; 429 u64 mac_tx_ctrl_pkt_num; 430 u64 mac_rx_ctrl_pkt_num; 431 }; 432 433 #define HCLGE_STATS_TIMER_INTERVAL (60 * 5) 434 struct hclge_hw_stats { 435 struct hclge_mac_stats mac_stats; 436 u32 stats_timer; 437 }; 438 439 struct hclge_vlan_type_cfg { 440 u16 rx_ot_fst_vlan_type; 441 u16 rx_ot_sec_vlan_type; 442 u16 rx_in_fst_vlan_type; 443 u16 rx_in_sec_vlan_type; 444 u16 tx_ot_vlan_type; 445 u16 tx_in_vlan_type; 446 }; 447 448 enum HCLGE_FD_MODE { 449 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1, 450 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2, 451 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1, 452 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2, 453 }; 454 455 enum HCLGE_FD_KEY_TYPE { 456 HCLGE_FD_KEY_BASE_ON_PTYPE, 457 HCLGE_FD_KEY_BASE_ON_TUPLE, 458 }; 459 460 enum HCLGE_FD_STAGE { 461 HCLGE_FD_STAGE_1, 462 HCLGE_FD_STAGE_2, 463 }; 464 465 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet 466 * INNER_XXX indicate tuples in tunneled header of tunnel packet or 467 * tuples of non-tunnel packet 468 */ 469 enum HCLGE_FD_TUPLE { 470 OUTER_DST_MAC, 471 OUTER_SRC_MAC, 472 OUTER_VLAN_TAG_FST, 473 OUTER_VLAN_TAG_SEC, 474 OUTER_ETH_TYPE, 475 OUTER_L2_RSV, 476 OUTER_IP_TOS, 477 OUTER_IP_PROTO, 478 OUTER_SRC_IP, 479 OUTER_DST_IP, 480 OUTER_L3_RSV, 481 OUTER_SRC_PORT, 482 OUTER_DST_PORT, 483 OUTER_L4_RSV, 484 OUTER_TUN_VNI, 485 OUTER_TUN_FLOW_ID, 486 INNER_DST_MAC, 487 INNER_SRC_MAC, 488 INNER_VLAN_TAG_FST, 489 INNER_VLAN_TAG_SEC, 490 INNER_ETH_TYPE, 491 INNER_L2_RSV, 492 INNER_IP_TOS, 493 INNER_IP_PROTO, 494 INNER_SRC_IP, 495 INNER_DST_IP, 496 INNER_L3_RSV, 497 INNER_SRC_PORT, 498 INNER_DST_PORT, 499 INNER_L4_RSV, 500 MAX_TUPLE, 501 }; 502 503 enum HCLGE_FD_META_DATA { 504 PACKET_TYPE_ID, 505 IP_FRAGEMENT, 506 ROCE_TYPE, 507 NEXT_KEY, 508 VLAN_NUMBER, 509 SRC_VPORT, 510 DST_VPORT, 511 TUNNEL_PACKET, 512 MAX_META_DATA, 513 }; 514 515 struct key_info { 516 u8 key_type; 517 u8 key_length; 518 }; 519 520 static const struct key_info meta_data_key_info[] = { 521 { PACKET_TYPE_ID, 6}, 522 { IP_FRAGEMENT, 1}, 523 { ROCE_TYPE, 1}, 524 { NEXT_KEY, 5}, 525 { VLAN_NUMBER, 2}, 526 { SRC_VPORT, 12}, 527 { DST_VPORT, 12}, 528 { TUNNEL_PACKET, 1}, 529 }; 530 531 static const struct key_info tuple_key_info[] = { 532 { OUTER_DST_MAC, 48}, 533 { OUTER_SRC_MAC, 48}, 534 { OUTER_VLAN_TAG_FST, 16}, 535 { OUTER_VLAN_TAG_SEC, 16}, 536 { OUTER_ETH_TYPE, 16}, 537 { OUTER_L2_RSV, 16}, 538 { OUTER_IP_TOS, 8}, 539 { OUTER_IP_PROTO, 8}, 540 { OUTER_SRC_IP, 32}, 541 { OUTER_DST_IP, 32}, 542 { OUTER_L3_RSV, 16}, 543 { OUTER_SRC_PORT, 16}, 544 { OUTER_DST_PORT, 16}, 545 { OUTER_L4_RSV, 32}, 546 { OUTER_TUN_VNI, 24}, 547 { OUTER_TUN_FLOW_ID, 8}, 548 { INNER_DST_MAC, 48}, 549 { INNER_SRC_MAC, 48}, 550 { INNER_VLAN_TAG_FST, 16}, 551 { INNER_VLAN_TAG_SEC, 16}, 552 { INNER_ETH_TYPE, 16}, 553 { INNER_L2_RSV, 16}, 554 { INNER_IP_TOS, 8}, 555 { INNER_IP_PROTO, 8}, 556 { INNER_SRC_IP, 32}, 557 { INNER_DST_IP, 32}, 558 { INNER_L3_RSV, 16}, 559 { INNER_SRC_PORT, 16}, 560 { INNER_DST_PORT, 16}, 561 { INNER_L4_RSV, 32}, 562 }; 563 564 #define MAX_KEY_LENGTH 400 565 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4) 566 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4) 567 #define MAX_META_DATA_LENGTH 32 568 569 enum HCLGE_FD_PACKET_TYPE { 570 NIC_PACKET, 571 ROCE_PACKET, 572 }; 573 574 enum HCLGE_FD_ACTION { 575 HCLGE_FD_ACTION_ACCEPT_PACKET, 576 HCLGE_FD_ACTION_DROP_PACKET, 577 }; 578 579 struct hclge_fd_key_cfg { 580 u8 key_sel; 581 u8 inner_sipv6_word_en; 582 u8 inner_dipv6_word_en; 583 u8 outer_sipv6_word_en; 584 u8 outer_dipv6_word_en; 585 u32 tuple_active; 586 u32 meta_data_active; 587 }; 588 589 struct hclge_fd_cfg { 590 u8 fd_mode; 591 u16 max_key_length; 592 u32 proto_support; 593 u32 rule_num[2]; /* rule entry number */ 594 u16 cnt_num[2]; /* rule hit counter number */ 595 struct hclge_fd_key_cfg key_cfg[2]; 596 }; 597 598 struct hclge_fd_rule_tuples { 599 u8 src_mac[6]; 600 u8 dst_mac[6]; 601 u32 src_ip[4]; 602 u32 dst_ip[4]; 603 u16 src_port; 604 u16 dst_port; 605 u16 vlan_tag1; 606 u16 ether_proto; 607 u8 ip_tos; 608 u8 ip_proto; 609 }; 610 611 struct hclge_fd_rule { 612 struct hlist_node rule_node; 613 struct hclge_fd_rule_tuples tuples; 614 struct hclge_fd_rule_tuples tuples_mask; 615 u32 unused_tuple; 616 u32 flow_type; 617 u8 action; 618 u16 vf_id; 619 u16 queue_id; 620 u16 location; 621 }; 622 623 struct hclge_fd_ad_data { 624 u16 ad_id; 625 u8 drop_packet; 626 u8 forward_to_direct_queue; 627 u16 queue_id; 628 u8 use_counter; 629 u8 counter_id; 630 u8 use_next_stage; 631 u8 write_rule_id_to_bd; 632 u8 next_input_key; 633 u16 rule_id; 634 }; 635 636 struct hclge_vport_mac_addr_cfg { 637 struct list_head node; 638 int hd_tbl_status; 639 u8 mac_addr[ETH_ALEN]; 640 }; 641 642 enum HCLGE_MAC_ADDR_TYPE { 643 HCLGE_MAC_ADDR_UC, 644 HCLGE_MAC_ADDR_MC 645 }; 646 647 struct hclge_vport_vlan_cfg { 648 struct list_head node; 649 int hd_tbl_status; 650 u16 vlan_id; 651 }; 652 653 struct hclge_rst_stats { 654 u32 reset_done_cnt; /* the number of reset has completed */ 655 u32 hw_reset_done_cnt; /* the number of HW reset has completed */ 656 u32 pf_rst_cnt; /* the number of PF reset */ 657 u32 flr_rst_cnt; /* the number of FLR */ 658 u32 core_rst_cnt; /* the number of CORE reset */ 659 u32 global_rst_cnt; /* the number of GLOBAL */ 660 u32 imp_rst_cnt; /* the number of IMP reset */ 661 u32 reset_cnt; /* the number of reset */ 662 }; 663 664 /* time and register status when mac tunnel interruption occur */ 665 struct hclge_mac_tnl_stats { 666 u64 time; 667 u32 status; 668 }; 669 670 /* For each bit of TCAM entry, it uses a pair of 'x' and 671 * 'y' to indicate which value to match, like below: 672 * ---------------------------------- 673 * | bit x | bit y | search value | 674 * ---------------------------------- 675 * | 0 | 0 | always hit | 676 * ---------------------------------- 677 * | 1 | 0 | match '0' | 678 * ---------------------------------- 679 * | 0 | 1 | match '1' | 680 * ---------------------------------- 681 * | 1 | 1 | invalid | 682 * ---------------------------------- 683 * Then for input key(k) and mask(v), we can calculate the value by 684 * the formulae: 685 * x = (~k) & v 686 * y = (k ^ ~v) & k 687 */ 688 #define calc_x(x, k, v) ((x) = (~(k) & (v))) 689 #define calc_y(y, k, v) \ 690 do { \ 691 const typeof(k) _k_ = (k); \ 692 const typeof(v) _v_ = (v); \ 693 (y) = (_k_ ^ ~_v_) & (_k_); \ 694 } while (0) 695 696 #define HCLGE_MAC_TNL_LOG_SIZE 8 697 #define HCLGE_VPORT_NUM 256 698 struct hclge_dev { 699 struct pci_dev *pdev; 700 struct hnae3_ae_dev *ae_dev; 701 struct hclge_hw hw; 702 struct hclge_misc_vector misc_vector; 703 struct hclge_hw_stats hw_stats; 704 unsigned long state; 705 unsigned long flr_state; 706 unsigned long last_reset_time; 707 708 enum hnae3_reset_type reset_type; 709 enum hnae3_reset_type reset_level; 710 unsigned long default_reset_request; 711 unsigned long reset_request; /* reset has been requested */ 712 unsigned long reset_pending; /* client rst is pending to be served */ 713 struct hclge_rst_stats rst_stats; 714 u32 reset_fail_cnt; 715 u32 fw_version; 716 u16 num_vmdq_vport; /* Num vmdq vport this PF has set up */ 717 u16 num_tqps; /* Num task queue pairs of this PF */ 718 u16 num_req_vfs; /* Num VFs requested for this PF */ 719 720 u16 base_tqp_pid; /* Base task tqp physical id of this PF */ 721 u16 alloc_rss_size; /* Allocated RSS task queue */ 722 u16 rss_size_max; /* HW defined max RSS task queue */ 723 724 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */ 725 u16 num_alloc_vport; /* Num vports this driver supports */ 726 u32 numa_node_mask; 727 u16 rx_buf_len; 728 u16 num_tx_desc; /* desc num of per tx queue */ 729 u16 num_rx_desc; /* desc num of per rx queue */ 730 u8 hw_tc_map; 731 u8 tc_num_last_time; 732 enum hclge_fc_mode fc_mode_last_time; 733 u8 support_sfp_query; 734 735 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1 736 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2 737 u8 tx_sch_mode; 738 u8 tc_max; 739 u8 pfc_max; 740 741 u8 default_up; 742 u8 dcbx_cap; 743 struct hclge_tm_info tm_info; 744 745 u16 num_msi; 746 u16 num_msi_left; 747 u16 num_msi_used; 748 u16 roce_base_msix_offset; 749 u32 base_msi_vector; 750 u16 *vector_status; 751 int *vector_irq; 752 u16 num_roce_msi; /* Num of roce vectors for this PF */ 753 int roce_base_vector; 754 755 u16 pending_udp_bitmap; 756 757 u16 rx_itr_default; 758 u16 tx_itr_default; 759 760 u16 adminq_work_limit; /* Num of admin receive queue desc to process */ 761 unsigned long service_timer_period; 762 unsigned long service_timer_previous; 763 struct timer_list service_timer; 764 struct timer_list reset_timer; 765 struct work_struct service_task; 766 struct work_struct rst_service_task; 767 struct work_struct mbx_service_task; 768 769 bool cur_promisc; 770 int num_alloc_vfs; /* Actual number of VFs allocated */ 771 772 struct hclge_tqp *htqp; 773 struct hclge_vport *vport; 774 775 struct dentry *hclge_dbgfs; 776 777 struct hnae3_client *nic_client; 778 struct hnae3_client *roce_client; 779 780 #define HCLGE_FLAG_MAIN BIT(0) 781 #define HCLGE_FLAG_DCB_CAPABLE BIT(1) 782 #define HCLGE_FLAG_DCB_ENABLE BIT(2) 783 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3) 784 u32 flag; 785 786 u32 pkt_buf_size; /* Total pf buf size for tx/rx */ 787 u32 tx_buf_size; /* Tx buffer size for each TC */ 788 u32 dv_buf_size; /* Dv buffer size for each TC */ 789 790 u32 mps; /* Max packet size */ 791 /* vport_lock protect resource shared by vports */ 792 struct mutex vport_lock; 793 794 struct hclge_vlan_type_cfg vlan_type_cfg; 795 796 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 797 798 struct hclge_fd_cfg fd_cfg; 799 struct hlist_head fd_rule_list; 800 u16 hclge_fd_rule_num; 801 u8 fd_en; 802 803 u16 wanted_umv_size; 804 /* max available unicast mac vlan space */ 805 u16 max_umv_size; 806 /* private unicast mac vlan space, it's same for PF and its VFs */ 807 u16 priv_umv_size; 808 /* unicast mac vlan space shared by PF and its VFs */ 809 u16 share_umv_size; 810 struct mutex umv_mutex; /* protect share_umv_size */ 811 812 struct mutex vport_cfg_mutex; /* Protect stored vf table */ 813 814 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats, 815 HCLGE_MAC_TNL_LOG_SIZE); 816 }; 817 818 /* VPort level vlan tag configuration for TX direction */ 819 struct hclge_tx_vtag_cfg { 820 bool accept_tag1; /* Whether accept tag1 packet from host */ 821 bool accept_untag1; /* Whether accept untag1 packet from host */ 822 bool accept_tag2; 823 bool accept_untag2; 824 bool insert_tag1_en; /* Whether insert inner vlan tag */ 825 bool insert_tag2_en; /* Whether insert outer vlan tag */ 826 u16 default_tag1; /* The default inner vlan tag to insert */ 827 u16 default_tag2; /* The default outer vlan tag to insert */ 828 }; 829 830 /* VPort level vlan tag configuration for RX direction */ 831 struct hclge_rx_vtag_cfg { 832 u8 rx_vlan_offload_en; /* Whether enable rx vlan offload */ 833 u8 strip_tag1_en; /* Whether strip inner vlan tag */ 834 u8 strip_tag2_en; /* Whether strip outer vlan tag */ 835 u8 vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */ 836 u8 vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */ 837 }; 838 839 struct hclge_rss_tuple_cfg { 840 u8 ipv4_tcp_en; 841 u8 ipv4_udp_en; 842 u8 ipv4_sctp_en; 843 u8 ipv4_fragment_en; 844 u8 ipv6_tcp_en; 845 u8 ipv6_udp_en; 846 u8 ipv6_sctp_en; 847 u8 ipv6_fragment_en; 848 }; 849 850 enum HCLGE_VPORT_STATE { 851 HCLGE_VPORT_STATE_ALIVE, 852 HCLGE_VPORT_STATE_MAX 853 }; 854 855 struct hclge_vlan_info { 856 u16 vlan_proto; /* so far support 802.1Q only */ 857 u16 qos; 858 u16 vlan_tag; 859 }; 860 861 struct hclge_port_base_vlan_config { 862 u16 state; 863 struct hclge_vlan_info vlan_info; 864 }; 865 866 struct hclge_vport { 867 u16 alloc_tqps; /* Allocated Tx/Rx queues */ 868 869 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */ 870 /* User configured lookup table entries */ 871 u8 rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE]; 872 int rss_algo; /* User configured hash algorithm */ 873 /* User configured rss tuple sets */ 874 struct hclge_rss_tuple_cfg rss_tuple_sets; 875 876 u16 alloc_rss_size; 877 878 u16 qs_offset; 879 u32 bw_limit; /* VSI BW Limit (0 = disabled) */ 880 u8 dwrr; 881 882 struct hclge_port_base_vlan_config port_base_vlan_cfg; 883 struct hclge_tx_vtag_cfg txvlan_cfg; 884 struct hclge_rx_vtag_cfg rxvlan_cfg; 885 886 u16 used_umv_num; 887 888 int vport_id; 889 struct hclge_dev *back; /* Back reference to associated dev */ 890 struct hnae3_handle nic; 891 struct hnae3_handle roce; 892 893 unsigned long state; 894 unsigned long last_active_jiffies; 895 u32 mps; /* Max packet size */ 896 897 struct list_head uc_mac_list; /* Store VF unicast table */ 898 struct list_head mc_mac_list; /* Store VF multicast table */ 899 struct list_head vlan_list; /* Store VF vlan table */ 900 }; 901 902 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc, 903 bool en_mc, bool en_bc, int vport_id); 904 905 int hclge_add_uc_addr_common(struct hclge_vport *vport, 906 const unsigned char *addr); 907 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 908 const unsigned char *addr); 909 int hclge_add_mc_addr_common(struct hclge_vport *vport, 910 const unsigned char *addr); 911 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 912 const unsigned char *addr); 913 914 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle); 915 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 916 int vector_id, bool en, 917 struct hnae3_ring_chain_node *ring_chain); 918 919 static inline int hclge_get_queue_id(struct hnae3_queue *queue) 920 { 921 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q); 922 923 return tqp->index; 924 } 925 926 static inline bool hclge_is_reset_pending(struct hclge_dev *hdev) 927 { 928 return !!hdev->reset_pending; 929 } 930 931 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport); 932 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex); 933 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 934 u16 vlan_id, bool is_kill); 935 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable); 936 937 int hclge_buffer_alloc(struct hclge_dev *hdev); 938 int hclge_rss_init_hw(struct hclge_dev *hdev); 939 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev); 940 941 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport); 942 void hclge_mbx_handler(struct hclge_dev *hdev); 943 int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id); 944 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id); 945 int hclge_cfg_flowctrl(struct hclge_dev *hdev); 946 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id); 947 int hclge_vport_start(struct hclge_vport *vport); 948 void hclge_vport_stop(struct hclge_vport *vport); 949 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu); 950 int hclge_dbg_run_cmd(struct hnae3_handle *handle, char *cmd_buf); 951 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id); 952 int hclge_notify_client(struct hclge_dev *hdev, 953 enum hnae3_reset_notify_type type); 954 void hclge_add_vport_mac_table(struct hclge_vport *vport, const u8 *mac_addr, 955 enum HCLGE_MAC_ADDR_TYPE mac_type); 956 void hclge_rm_vport_mac_table(struct hclge_vport *vport, const u8 *mac_addr, 957 bool is_write_tbl, 958 enum HCLGE_MAC_ADDR_TYPE mac_type); 959 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 960 enum HCLGE_MAC_ADDR_TYPE mac_type); 961 void hclge_uninit_vport_mac_table(struct hclge_dev *hdev); 962 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list); 963 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev); 964 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 965 struct hclge_vlan_info *vlan_info); 966 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid, 967 u16 state, u16 vlan_tag, u16 qos, 968 u16 vlan_proto); 969 #endif 970