1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_MAIN_H 5 #define __HCLGE_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include <linux/phy.h> 9 #include <linux/if_vlan.h> 10 #include <linux/kfifo.h> 11 #include <net/devlink.h> 12 13 #include "hclge_cmd.h" 14 #include "hclge_ptp.h" 15 #include "hnae3.h" 16 17 #define HCLGE_MOD_VERSION "1.0" 18 #define HCLGE_DRIVER_NAME "hclge" 19 20 #define HCLGE_MAX_PF_NUM 8 21 22 #define HCLGE_VF_VPORT_START_NUM 1 23 24 #define HCLGE_RD_FIRST_STATS_NUM 2 25 #define HCLGE_RD_OTHER_STATS_NUM 4 26 27 #define HCLGE_INVALID_VPORT 0xffff 28 29 #define HCLGE_PF_CFG_BLOCK_SIZE 32 30 #define HCLGE_PF_CFG_DESC_NUM \ 31 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) 32 33 #define HCLGE_VECTOR_REG_BASE 0x20000 34 #define HCLGE_VECTOR_EXT_REG_BASE 0x30000 35 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400 36 37 #define HCLGE_VECTOR_REG_OFFSET 0x4 38 #define HCLGE_VECTOR_REG_OFFSET_H 0x1000 39 #define HCLGE_VECTOR_VF_OFFSET 0x100000 40 41 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 42 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 43 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 44 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 45 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 46 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 47 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701C 48 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 49 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 50 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 51 52 #define HCLGE_CMDQ_INTR_STS_REG 0x27104 53 #define HCLGE_CMDQ_INTR_EN_REG 0x27108 54 #define HCLGE_CMDQ_INTR_GEN_REG 0x2710C 55 56 /* bar registers for common func */ 57 #define HCLGE_GRO_EN_REG 0x28000 58 #define HCLGE_RXD_ADV_LAYOUT_EN_REG 0x28008 59 60 /* bar registers for rcb */ 61 #define HCLGE_RING_RX_ADDR_L_REG 0x80000 62 #define HCLGE_RING_RX_ADDR_H_REG 0x80004 63 #define HCLGE_RING_RX_BD_NUM_REG 0x80008 64 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C 65 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014 66 #define HCLGE_RING_RX_TAIL_REG 0x80018 67 #define HCLGE_RING_RX_HEAD_REG 0x8001C 68 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020 69 #define HCLGE_RING_RX_OFFSET_REG 0x80024 70 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028 71 #define HCLGE_RING_RX_STASH_REG 0x80030 72 #define HCLGE_RING_RX_BD_ERR_REG 0x80034 73 #define HCLGE_RING_TX_ADDR_L_REG 0x80040 74 #define HCLGE_RING_TX_ADDR_H_REG 0x80044 75 #define HCLGE_RING_TX_BD_NUM_REG 0x80048 76 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C 77 #define HCLGE_RING_TX_TC_REG 0x80050 78 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054 79 #define HCLGE_RING_TX_TAIL_REG 0x80058 80 #define HCLGE_RING_TX_HEAD_REG 0x8005C 81 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060 82 #define HCLGE_RING_TX_OFFSET_REG 0x80064 83 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068 84 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070 85 #define HCLGE_RING_TX_BD_ERR_REG 0x80074 86 #define HCLGE_RING_EN_REG 0x80090 87 88 /* bar registers for tqp interrupt */ 89 #define HCLGE_TQP_INTR_CTRL_REG 0x20000 90 #define HCLGE_TQP_INTR_GL0_REG 0x20100 91 #define HCLGE_TQP_INTR_GL1_REG 0x20200 92 #define HCLGE_TQP_INTR_GL2_REG 0x20300 93 #define HCLGE_TQP_INTR_RL_REG 0x20900 94 95 #define HCLGE_RSS_IND_TBL_SIZE 512 96 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0) 97 #define HCLGE_RSS_KEY_SIZE 40 98 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0 99 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1 100 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2 101 #define HCLGE_RSS_HASH_ALGO_MASK GENMASK(3, 0) 102 103 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 104 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 105 #define HCLGE_D_PORT_BIT BIT(0) 106 #define HCLGE_S_PORT_BIT BIT(1) 107 #define HCLGE_D_IP_BIT BIT(2) 108 #define HCLGE_S_IP_BIT BIT(3) 109 #define HCLGE_V_TAG_BIT BIT(4) 110 #define HCLGE_RSS_INPUT_TUPLE_SCTP_NO_PORT \ 111 (HCLGE_D_IP_BIT | HCLGE_S_IP_BIT | HCLGE_V_TAG_BIT) 112 113 #define HCLGE_RSS_TC_SIZE_0 1 114 #define HCLGE_RSS_TC_SIZE_1 2 115 #define HCLGE_RSS_TC_SIZE_2 4 116 #define HCLGE_RSS_TC_SIZE_3 8 117 #define HCLGE_RSS_TC_SIZE_4 16 118 #define HCLGE_RSS_TC_SIZE_5 32 119 #define HCLGE_RSS_TC_SIZE_6 64 120 #define HCLGE_RSS_TC_SIZE_7 128 121 122 #define HCLGE_UMV_TBL_SIZE 3072 123 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \ 124 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM) 125 126 #define HCLGE_TQP_RESET_TRY_TIMES 200 127 128 #define HCLGE_PHY_PAGE_MDIX 0 129 #define HCLGE_PHY_PAGE_COPPER 0 130 131 /* Page Selection Reg. */ 132 #define HCLGE_PHY_PAGE_REG 22 133 134 /* Copper Specific Control Register */ 135 #define HCLGE_PHY_CSC_REG 16 136 137 /* Copper Specific Status Register */ 138 #define HCLGE_PHY_CSS_REG 17 139 140 #define HCLGE_PHY_MDIX_CTRL_S 5 141 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) 142 143 #define HCLGE_PHY_MDIX_STATUS_B 6 144 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11 145 146 #define HCLGE_GET_DFX_REG_TYPE_CNT 4 147 148 /* Factor used to calculate offset and bitmap of VF num */ 149 #define HCLGE_VF_NUM_PER_CMD 64 150 151 #define HCLGE_MAX_QSET_NUM 1024 152 153 #define HCLGE_DBG_RESET_INFO_LEN 1024 154 155 enum HLCGE_PORT_TYPE { 156 HOST_PORT, 157 NETWORK_PORT 158 }; 159 160 #define PF_VPORT_ID 0 161 162 #define HCLGE_PF_ID_S 0 163 #define HCLGE_PF_ID_M GENMASK(2, 0) 164 #define HCLGE_VF_ID_S 3 165 #define HCLGE_VF_ID_M GENMASK(10, 3) 166 #define HCLGE_PORT_TYPE_B 11 167 #define HCLGE_NETWORK_PORT_ID_S 0 168 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0) 169 170 /* Reset related Registers */ 171 #define HCLGE_PF_OTHER_INT_REG 0x20600 172 #define HCLGE_MISC_RESET_STS_REG 0x20700 173 #define HCLGE_MISC_VECTOR_INT_STS 0x20800 174 #define HCLGE_GLOBAL_RESET_REG 0x20A00 175 #define HCLGE_GLOBAL_RESET_BIT 0 176 #define HCLGE_CORE_RESET_BIT 1 177 #define HCLGE_IMP_RESET_BIT 2 178 #define HCLGE_RESET_INT_M GENMASK(7, 5) 179 #define HCLGE_FUN_RST_ING 0x20C00 180 #define HCLGE_FUN_RST_ING_B 0 181 182 /* Vector0 register bits define */ 183 #define HCLGE_VECTOR0_REG_PTP_INT_B 0 184 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5 185 #define HCLGE_VECTOR0_CORERESET_INT_B 6 186 #define HCLGE_VECTOR0_IMPRESET_INT_B 7 187 188 /* Vector0 interrupt CMDQ event source register(RW) */ 189 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100 190 /* CMDQ register bits for RX event(=MBX event) */ 191 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 192 193 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1 194 #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U 195 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U 196 #define HCLGE_VECTOR0_ALL_MSIX_ERR_B 6U 197 #define HCLGE_TRIGGER_IMP_RESET_B 7U 198 199 #define HCLGE_MAC_DEFAULT_FRAME \ 200 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN) 201 #define HCLGE_MAC_MIN_FRAME 64 202 #define HCLGE_MAC_MAX_FRAME 9728 203 204 #define HCLGE_SUPPORT_1G_BIT BIT(0) 205 #define HCLGE_SUPPORT_10G_BIT BIT(1) 206 #define HCLGE_SUPPORT_25G_BIT BIT(2) 207 #define HCLGE_SUPPORT_50G_BIT BIT(3) 208 #define HCLGE_SUPPORT_100G_BIT BIT(4) 209 /* to be compatible with exsit board */ 210 #define HCLGE_SUPPORT_40G_BIT BIT(5) 211 #define HCLGE_SUPPORT_100M_BIT BIT(6) 212 #define HCLGE_SUPPORT_10M_BIT BIT(7) 213 #define HCLGE_SUPPORT_200G_BIT BIT(8) 214 #define HCLGE_SUPPORT_GE \ 215 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT) 216 217 enum HCLGE_DEV_STATE { 218 HCLGE_STATE_REINITING, 219 HCLGE_STATE_DOWN, 220 HCLGE_STATE_DISABLED, 221 HCLGE_STATE_REMOVING, 222 HCLGE_STATE_NIC_REGISTERED, 223 HCLGE_STATE_ROCE_REGISTERED, 224 HCLGE_STATE_SERVICE_INITED, 225 HCLGE_STATE_RST_SERVICE_SCHED, 226 HCLGE_STATE_RST_HANDLING, 227 HCLGE_STATE_MBX_SERVICE_SCHED, 228 HCLGE_STATE_MBX_HANDLING, 229 HCLGE_STATE_ERR_SERVICE_SCHED, 230 HCLGE_STATE_STATISTICS_UPDATING, 231 HCLGE_STATE_CMD_DISABLE, 232 HCLGE_STATE_LINK_UPDATING, 233 HCLGE_STATE_RST_FAIL, 234 HCLGE_STATE_FD_TBL_CHANGED, 235 HCLGE_STATE_FD_CLEAR_ALL, 236 HCLGE_STATE_FD_USER_DEF_CHANGED, 237 HCLGE_STATE_PTP_EN, 238 HCLGE_STATE_PTP_TX_HANDLING, 239 HCLGE_STATE_MAX 240 }; 241 242 enum hclge_evt_cause { 243 HCLGE_VECTOR0_EVENT_RST, 244 HCLGE_VECTOR0_EVENT_MBX, 245 HCLGE_VECTOR0_EVENT_ERR, 246 HCLGE_VECTOR0_EVENT_PTP, 247 HCLGE_VECTOR0_EVENT_OTHER, 248 }; 249 250 enum HCLGE_MAC_SPEED { 251 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */ 252 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */ 253 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */ 254 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ 255 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ 256 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ 257 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ 258 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ 259 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */ 260 HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */ 261 }; 262 263 enum HCLGE_MAC_DUPLEX { 264 HCLGE_MAC_HALF, 265 HCLGE_MAC_FULL 266 }; 267 268 #define QUERY_SFP_SPEED 0 269 #define QUERY_ACTIVE_SPEED 1 270 271 struct hclge_mac { 272 u8 mac_id; 273 u8 phy_addr; 274 u8 flag; 275 u8 media_type; /* port media type, e.g. fibre/copper/backplane */ 276 u8 mac_addr[ETH_ALEN]; 277 u8 autoneg; 278 u8 duplex; 279 u8 support_autoneg; 280 u8 speed_type; /* 0: sfp speed, 1: active speed */ 281 u32 speed; 282 u32 max_speed; 283 u32 speed_ability; /* speed ability supported by current media */ 284 u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */ 285 u32 fec_mode; /* active fec mode */ 286 u32 user_fec_mode; 287 u32 fec_ability; 288 int link; /* store the link status of mac & phy (if phy exists) */ 289 struct phy_device *phydev; 290 struct mii_bus *mdio_bus; 291 phy_interface_t phy_if; 292 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 293 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 294 }; 295 296 struct hclge_hw { 297 void __iomem *io_base; 298 void __iomem *mem_base; 299 struct hclge_mac mac; 300 int num_vec; 301 struct hclge_cmq cmq; 302 }; 303 304 /* TQP stats */ 305 struct hlcge_tqp_stats { 306 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 307 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 308 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 309 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 310 }; 311 312 struct hclge_tqp { 313 /* copy of device pointer from pci_dev, 314 * used when perform DMA mapping 315 */ 316 struct device *dev; 317 struct hnae3_queue q; 318 struct hlcge_tqp_stats tqp_stats; 319 u16 index; /* Global index in a NIC controller */ 320 321 bool alloced; 322 }; 323 324 enum hclge_fc_mode { 325 HCLGE_FC_NONE, 326 HCLGE_FC_RX_PAUSE, 327 HCLGE_FC_TX_PAUSE, 328 HCLGE_FC_FULL, 329 HCLGE_FC_PFC, 330 HCLGE_FC_DEFAULT 331 }; 332 333 #define HCLGE_FILTER_TYPE_VF 0 334 #define HCLGE_FILTER_TYPE_PORT 1 335 #define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0) 336 #define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0) 337 #define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1) 338 #define HCLGE_FILTER_FE_ROCE_INGRESS_B BIT(2) 339 #define HCLGE_FILTER_FE_ROCE_EGRESS_B BIT(3) 340 #define HCLGE_FILTER_FE_EGRESS (HCLGE_FILTER_FE_NIC_EGRESS_B \ 341 | HCLGE_FILTER_FE_ROCE_EGRESS_B) 342 #define HCLGE_FILTER_FE_INGRESS (HCLGE_FILTER_FE_NIC_INGRESS_B \ 343 | HCLGE_FILTER_FE_ROCE_INGRESS_B) 344 345 enum hclge_vlan_fltr_cap { 346 HCLGE_VLAN_FLTR_DEF, 347 HCLGE_VLAN_FLTR_CAN_MDF, 348 }; 349 enum hclge_link_fail_code { 350 HCLGE_LF_NORMAL, 351 HCLGE_LF_REF_CLOCK_LOST, 352 HCLGE_LF_XSFP_TX_DISABLE, 353 HCLGE_LF_XSFP_ABSENT, 354 }; 355 356 #define HCLGE_LINK_STATUS_DOWN 0 357 #define HCLGE_LINK_STATUS_UP 1 358 359 #define HCLGE_PG_NUM 4 360 #define HCLGE_SCH_MODE_SP 0 361 #define HCLGE_SCH_MODE_DWRR 1 362 struct hclge_pg_info { 363 u8 pg_id; 364 u8 pg_sch_mode; /* 0: sp; 1: dwrr */ 365 u8 tc_bit_map; 366 u32 bw_limit; 367 u8 tc_dwrr[HNAE3_MAX_TC]; 368 }; 369 370 struct hclge_tc_info { 371 u8 tc_id; 372 u8 tc_sch_mode; /* 0: sp; 1: dwrr */ 373 u8 pgid; 374 u32 bw_limit; 375 }; 376 377 struct hclge_cfg { 378 u8 tc_num; 379 u8 vlan_fliter_cap; 380 u16 tqp_desc_num; 381 u16 rx_buf_len; 382 u16 vf_rss_size_max; 383 u16 pf_rss_size_max; 384 u8 phy_addr; 385 u8 media_type; 386 u8 mac_addr[ETH_ALEN]; 387 u8 default_speed; 388 u32 numa_node_map; 389 u32 tx_spare_buf_size; 390 u16 speed_ability; 391 u16 umv_space; 392 }; 393 394 struct hclge_tm_info { 395 u8 num_tc; 396 u8 num_pg; /* It must be 1 if vNET-Base schd */ 397 u8 pg_dwrr[HCLGE_PG_NUM]; 398 u8 prio_tc[HNAE3_MAX_USER_PRIO]; 399 struct hclge_pg_info pg_info[HCLGE_PG_NUM]; 400 struct hclge_tc_info tc_info[HNAE3_MAX_TC]; 401 enum hclge_fc_mode fc_mode; 402 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */ 403 u8 pfc_en; /* PFC enabled or not for user priority */ 404 }; 405 406 struct hclge_comm_stats_str { 407 char desc[ETH_GSTRING_LEN]; 408 unsigned long offset; 409 }; 410 411 /* mac stats ,opcode id: 0x0032 */ 412 struct hclge_mac_stats { 413 u64 mac_tx_mac_pause_num; 414 u64 mac_rx_mac_pause_num; 415 u64 mac_tx_pfc_pri0_pkt_num; 416 u64 mac_tx_pfc_pri1_pkt_num; 417 u64 mac_tx_pfc_pri2_pkt_num; 418 u64 mac_tx_pfc_pri3_pkt_num; 419 u64 mac_tx_pfc_pri4_pkt_num; 420 u64 mac_tx_pfc_pri5_pkt_num; 421 u64 mac_tx_pfc_pri6_pkt_num; 422 u64 mac_tx_pfc_pri7_pkt_num; 423 u64 mac_rx_pfc_pri0_pkt_num; 424 u64 mac_rx_pfc_pri1_pkt_num; 425 u64 mac_rx_pfc_pri2_pkt_num; 426 u64 mac_rx_pfc_pri3_pkt_num; 427 u64 mac_rx_pfc_pri4_pkt_num; 428 u64 mac_rx_pfc_pri5_pkt_num; 429 u64 mac_rx_pfc_pri6_pkt_num; 430 u64 mac_rx_pfc_pri7_pkt_num; 431 u64 mac_tx_total_pkt_num; 432 u64 mac_tx_total_oct_num; 433 u64 mac_tx_good_pkt_num; 434 u64 mac_tx_bad_pkt_num; 435 u64 mac_tx_good_oct_num; 436 u64 mac_tx_bad_oct_num; 437 u64 mac_tx_uni_pkt_num; 438 u64 mac_tx_multi_pkt_num; 439 u64 mac_tx_broad_pkt_num; 440 u64 mac_tx_undersize_pkt_num; 441 u64 mac_tx_oversize_pkt_num; 442 u64 mac_tx_64_oct_pkt_num; 443 u64 mac_tx_65_127_oct_pkt_num; 444 u64 mac_tx_128_255_oct_pkt_num; 445 u64 mac_tx_256_511_oct_pkt_num; 446 u64 mac_tx_512_1023_oct_pkt_num; 447 u64 mac_tx_1024_1518_oct_pkt_num; 448 u64 mac_tx_1519_2047_oct_pkt_num; 449 u64 mac_tx_2048_4095_oct_pkt_num; 450 u64 mac_tx_4096_8191_oct_pkt_num; 451 u64 rsv0; 452 u64 mac_tx_8192_9216_oct_pkt_num; 453 u64 mac_tx_9217_12287_oct_pkt_num; 454 u64 mac_tx_12288_16383_oct_pkt_num; 455 u64 mac_tx_1519_max_good_oct_pkt_num; 456 u64 mac_tx_1519_max_bad_oct_pkt_num; 457 458 u64 mac_rx_total_pkt_num; 459 u64 mac_rx_total_oct_num; 460 u64 mac_rx_good_pkt_num; 461 u64 mac_rx_bad_pkt_num; 462 u64 mac_rx_good_oct_num; 463 u64 mac_rx_bad_oct_num; 464 u64 mac_rx_uni_pkt_num; 465 u64 mac_rx_multi_pkt_num; 466 u64 mac_rx_broad_pkt_num; 467 u64 mac_rx_undersize_pkt_num; 468 u64 mac_rx_oversize_pkt_num; 469 u64 mac_rx_64_oct_pkt_num; 470 u64 mac_rx_65_127_oct_pkt_num; 471 u64 mac_rx_128_255_oct_pkt_num; 472 u64 mac_rx_256_511_oct_pkt_num; 473 u64 mac_rx_512_1023_oct_pkt_num; 474 u64 mac_rx_1024_1518_oct_pkt_num; 475 u64 mac_rx_1519_2047_oct_pkt_num; 476 u64 mac_rx_2048_4095_oct_pkt_num; 477 u64 mac_rx_4096_8191_oct_pkt_num; 478 u64 rsv1; 479 u64 mac_rx_8192_9216_oct_pkt_num; 480 u64 mac_rx_9217_12287_oct_pkt_num; 481 u64 mac_rx_12288_16383_oct_pkt_num; 482 u64 mac_rx_1519_max_good_oct_pkt_num; 483 u64 mac_rx_1519_max_bad_oct_pkt_num; 484 485 u64 mac_tx_fragment_pkt_num; 486 u64 mac_tx_undermin_pkt_num; 487 u64 mac_tx_jabber_pkt_num; 488 u64 mac_tx_err_all_pkt_num; 489 u64 mac_tx_from_app_good_pkt_num; 490 u64 mac_tx_from_app_bad_pkt_num; 491 u64 mac_rx_fragment_pkt_num; 492 u64 mac_rx_undermin_pkt_num; 493 u64 mac_rx_jabber_pkt_num; 494 u64 mac_rx_fcs_err_pkt_num; 495 u64 mac_rx_send_app_good_pkt_num; 496 u64 mac_rx_send_app_bad_pkt_num; 497 u64 mac_tx_pfc_pause_pkt_num; 498 u64 mac_rx_pfc_pause_pkt_num; 499 u64 mac_tx_ctrl_pkt_num; 500 u64 mac_rx_ctrl_pkt_num; 501 }; 502 503 #define HCLGE_STATS_TIMER_INTERVAL 300UL 504 505 struct hclge_vlan_type_cfg { 506 u16 rx_ot_fst_vlan_type; 507 u16 rx_ot_sec_vlan_type; 508 u16 rx_in_fst_vlan_type; 509 u16 rx_in_sec_vlan_type; 510 u16 tx_ot_vlan_type; 511 u16 tx_in_vlan_type; 512 }; 513 514 enum HCLGE_FD_MODE { 515 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1, 516 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2, 517 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1, 518 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2, 519 }; 520 521 enum HCLGE_FD_KEY_TYPE { 522 HCLGE_FD_KEY_BASE_ON_PTYPE, 523 HCLGE_FD_KEY_BASE_ON_TUPLE, 524 }; 525 526 enum HCLGE_FD_STAGE { 527 HCLGE_FD_STAGE_1, 528 HCLGE_FD_STAGE_2, 529 MAX_STAGE_NUM, 530 }; 531 532 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet 533 * INNER_XXX indicate tuples in tunneled header of tunnel packet or 534 * tuples of non-tunnel packet 535 */ 536 enum HCLGE_FD_TUPLE { 537 OUTER_DST_MAC, 538 OUTER_SRC_MAC, 539 OUTER_VLAN_TAG_FST, 540 OUTER_VLAN_TAG_SEC, 541 OUTER_ETH_TYPE, 542 OUTER_L2_RSV, 543 OUTER_IP_TOS, 544 OUTER_IP_PROTO, 545 OUTER_SRC_IP, 546 OUTER_DST_IP, 547 OUTER_L3_RSV, 548 OUTER_SRC_PORT, 549 OUTER_DST_PORT, 550 OUTER_L4_RSV, 551 OUTER_TUN_VNI, 552 OUTER_TUN_FLOW_ID, 553 INNER_DST_MAC, 554 INNER_SRC_MAC, 555 INNER_VLAN_TAG_FST, 556 INNER_VLAN_TAG_SEC, 557 INNER_ETH_TYPE, 558 INNER_L2_RSV, 559 INNER_IP_TOS, 560 INNER_IP_PROTO, 561 INNER_SRC_IP, 562 INNER_DST_IP, 563 INNER_L3_RSV, 564 INNER_SRC_PORT, 565 INNER_DST_PORT, 566 INNER_L4_RSV, 567 MAX_TUPLE, 568 }; 569 570 #define HCLGE_FD_TUPLE_USER_DEF_TUPLES \ 571 (BIT(INNER_L2_RSV) | BIT(INNER_L3_RSV) | BIT(INNER_L4_RSV)) 572 573 enum HCLGE_FD_META_DATA { 574 PACKET_TYPE_ID, 575 IP_FRAGEMENT, 576 ROCE_TYPE, 577 NEXT_KEY, 578 VLAN_NUMBER, 579 SRC_VPORT, 580 DST_VPORT, 581 TUNNEL_PACKET, 582 MAX_META_DATA, 583 }; 584 585 enum HCLGE_FD_KEY_OPT { 586 KEY_OPT_U8, 587 KEY_OPT_LE16, 588 KEY_OPT_LE32, 589 KEY_OPT_MAC, 590 KEY_OPT_IP, 591 KEY_OPT_VNI, 592 }; 593 594 struct key_info { 595 u8 key_type; 596 u8 key_length; /* use bit as unit */ 597 enum HCLGE_FD_KEY_OPT key_opt; 598 int offset; 599 int moffset; 600 }; 601 602 #define MAX_KEY_LENGTH 400 603 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4) 604 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4) 605 #define MAX_META_DATA_LENGTH 32 606 607 #define HCLGE_FD_MAX_USER_DEF_OFFSET 9000 608 #define HCLGE_FD_USER_DEF_DATA GENMASK(15, 0) 609 #define HCLGE_FD_USER_DEF_OFFSET GENMASK(15, 0) 610 #define HCLGE_FD_USER_DEF_OFFSET_UNMASK GENMASK(15, 0) 611 612 /* assigned by firmware, the real filter number for each pf may be less */ 613 #define MAX_FD_FILTER_NUM 4096 614 #define HCLGE_ARFS_EXPIRE_INTERVAL 5UL 615 616 enum HCLGE_FD_ACTIVE_RULE_TYPE { 617 HCLGE_FD_RULE_NONE, 618 HCLGE_FD_ARFS_ACTIVE, 619 HCLGE_FD_EP_ACTIVE, 620 HCLGE_FD_TC_FLOWER_ACTIVE, 621 }; 622 623 enum HCLGE_FD_PACKET_TYPE { 624 NIC_PACKET, 625 ROCE_PACKET, 626 }; 627 628 enum HCLGE_FD_ACTION { 629 HCLGE_FD_ACTION_SELECT_QUEUE, 630 HCLGE_FD_ACTION_DROP_PACKET, 631 HCLGE_FD_ACTION_SELECT_TC, 632 }; 633 634 enum HCLGE_FD_NODE_STATE { 635 HCLGE_FD_TO_ADD, 636 HCLGE_FD_TO_DEL, 637 HCLGE_FD_ACTIVE, 638 HCLGE_FD_DELETED, 639 }; 640 641 enum HCLGE_FD_USER_DEF_LAYER { 642 HCLGE_FD_USER_DEF_NONE, 643 HCLGE_FD_USER_DEF_L2, 644 HCLGE_FD_USER_DEF_L3, 645 HCLGE_FD_USER_DEF_L4, 646 }; 647 648 #define HCLGE_FD_USER_DEF_LAYER_NUM 3 649 struct hclge_fd_user_def_cfg { 650 u16 ref_cnt; 651 u16 offset; 652 }; 653 654 struct hclge_fd_user_def_info { 655 enum HCLGE_FD_USER_DEF_LAYER layer; 656 u16 data; 657 u16 data_mask; 658 u16 offset; 659 }; 660 661 struct hclge_fd_key_cfg { 662 u8 key_sel; 663 u8 inner_sipv6_word_en; 664 u8 inner_dipv6_word_en; 665 u8 outer_sipv6_word_en; 666 u8 outer_dipv6_word_en; 667 u32 tuple_active; 668 u32 meta_data_active; 669 }; 670 671 struct hclge_fd_cfg { 672 u8 fd_mode; 673 u16 max_key_length; /* use bit as unit */ 674 u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */ 675 u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */ 676 struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM]; 677 struct hclge_fd_user_def_cfg user_def_cfg[HCLGE_FD_USER_DEF_LAYER_NUM]; 678 }; 679 680 #define IPV4_INDEX 3 681 #define IPV6_SIZE 4 682 struct hclge_fd_rule_tuples { 683 u8 src_mac[ETH_ALEN]; 684 u8 dst_mac[ETH_ALEN]; 685 /* Be compatible for ip address of both ipv4 and ipv6. 686 * For ipv4 address, we store it in src/dst_ip[3]. 687 */ 688 u32 src_ip[IPV6_SIZE]; 689 u32 dst_ip[IPV6_SIZE]; 690 u16 src_port; 691 u16 dst_port; 692 u16 vlan_tag1; 693 u16 ether_proto; 694 u16 l2_user_def; 695 u16 l3_user_def; 696 u32 l4_user_def; 697 u8 ip_tos; 698 u8 ip_proto; 699 }; 700 701 struct hclge_fd_rule { 702 struct hlist_node rule_node; 703 struct hclge_fd_rule_tuples tuples; 704 struct hclge_fd_rule_tuples tuples_mask; 705 u32 unused_tuple; 706 u32 flow_type; 707 union { 708 struct { 709 unsigned long cookie; 710 u8 tc; 711 } cls_flower; 712 struct { 713 u16 flow_id; /* only used for arfs */ 714 } arfs; 715 struct { 716 struct hclge_fd_user_def_info user_def; 717 } ep; 718 }; 719 u16 queue_id; 720 u16 vf_id; 721 u16 location; 722 enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type; 723 enum HCLGE_FD_NODE_STATE state; 724 u8 action; 725 }; 726 727 struct hclge_fd_ad_data { 728 u16 ad_id; 729 u8 drop_packet; 730 u8 forward_to_direct_queue; 731 u16 queue_id; 732 u8 use_counter; 733 u8 counter_id; 734 u8 use_next_stage; 735 u8 write_rule_id_to_bd; 736 u8 next_input_key; 737 u16 rule_id; 738 u16 tc_size; 739 u8 override_tc; 740 }; 741 742 enum HCLGE_MAC_NODE_STATE { 743 HCLGE_MAC_TO_ADD, 744 HCLGE_MAC_TO_DEL, 745 HCLGE_MAC_ACTIVE 746 }; 747 748 struct hclge_mac_node { 749 struct list_head node; 750 enum HCLGE_MAC_NODE_STATE state; 751 u8 mac_addr[ETH_ALEN]; 752 }; 753 754 enum HCLGE_MAC_ADDR_TYPE { 755 HCLGE_MAC_ADDR_UC, 756 HCLGE_MAC_ADDR_MC 757 }; 758 759 struct hclge_vport_vlan_cfg { 760 struct list_head node; 761 int hd_tbl_status; 762 u16 vlan_id; 763 }; 764 765 struct hclge_rst_stats { 766 u32 reset_done_cnt; /* the number of reset has completed */ 767 u32 hw_reset_done_cnt; /* the number of HW reset has completed */ 768 u32 pf_rst_cnt; /* the number of PF reset */ 769 u32 flr_rst_cnt; /* the number of FLR */ 770 u32 global_rst_cnt; /* the number of GLOBAL */ 771 u32 imp_rst_cnt; /* the number of IMP reset */ 772 u32 reset_cnt; /* the number of reset */ 773 u32 reset_fail_cnt; /* the number of reset fail */ 774 }; 775 776 /* time and register status when mac tunnel interruption occur */ 777 struct hclge_mac_tnl_stats { 778 u64 time; 779 u32 status; 780 }; 781 782 #define HCLGE_RESET_INTERVAL (10 * HZ) 783 #define HCLGE_WAIT_RESET_DONE 100 784 785 #pragma pack(1) 786 struct hclge_vf_vlan_cfg { 787 u8 mbx_cmd; 788 u8 subcode; 789 union { 790 struct { 791 u8 is_kill; 792 u16 vlan; 793 u16 proto; 794 }; 795 u8 enable; 796 }; 797 }; 798 799 #pragma pack() 800 801 /* For each bit of TCAM entry, it uses a pair of 'x' and 802 * 'y' to indicate which value to match, like below: 803 * ---------------------------------- 804 * | bit x | bit y | search value | 805 * ---------------------------------- 806 * | 0 | 0 | always hit | 807 * ---------------------------------- 808 * | 1 | 0 | match '0' | 809 * ---------------------------------- 810 * | 0 | 1 | match '1' | 811 * ---------------------------------- 812 * | 1 | 1 | invalid | 813 * ---------------------------------- 814 * Then for input key(k) and mask(v), we can calculate the value by 815 * the formulae: 816 * x = (~k) & v 817 * y = (k ^ ~v) & k 818 */ 819 #define calc_x(x, k, v) (x = ~(k) & (v)) 820 #define calc_y(y, k, v) \ 821 do { \ 822 const typeof(k) _k_ = (k); \ 823 const typeof(v) _v_ = (v); \ 824 (y) = (_k_ ^ ~_v_) & (_k_); \ 825 } while (0) 826 827 #define HCLGE_MAC_TNL_LOG_SIZE 8 828 #define HCLGE_VPORT_NUM 256 829 struct hclge_dev { 830 struct pci_dev *pdev; 831 struct hnae3_ae_dev *ae_dev; 832 struct hclge_hw hw; 833 struct hclge_misc_vector misc_vector; 834 struct hclge_mac_stats mac_stats; 835 unsigned long state; 836 unsigned long flr_state; 837 unsigned long last_reset_time; 838 839 enum hnae3_reset_type reset_type; 840 enum hnae3_reset_type reset_level; 841 unsigned long default_reset_request; 842 unsigned long reset_request; /* reset has been requested */ 843 unsigned long reset_pending; /* client rst is pending to be served */ 844 struct hclge_rst_stats rst_stats; 845 struct semaphore reset_sem; /* protect reset process */ 846 u32 fw_version; 847 u16 num_tqps; /* Num task queue pairs of this PF */ 848 u16 num_req_vfs; /* Num VFs requested for this PF */ 849 850 u16 base_tqp_pid; /* Base task tqp physical id of this PF */ 851 u16 alloc_rss_size; /* Allocated RSS task queue */ 852 u16 vf_rss_size_max; /* HW defined VF max RSS task queue */ 853 u16 pf_rss_size_max; /* HW defined PF max RSS task queue */ 854 u32 tx_spare_buf_size; /* HW defined TX spare buffer size */ 855 856 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */ 857 u16 num_alloc_vport; /* Num vports this driver supports */ 858 u32 numa_node_mask; 859 u16 rx_buf_len; 860 u16 num_tx_desc; /* desc num of per tx queue */ 861 u16 num_rx_desc; /* desc num of per rx queue */ 862 u8 hw_tc_map; 863 enum hclge_fc_mode fc_mode_last_time; 864 u8 support_sfp_query; 865 866 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1 867 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2 868 u8 tx_sch_mode; 869 u8 tc_max; 870 u8 pfc_max; 871 872 u8 default_up; 873 u8 dcbx_cap; 874 struct hclge_tm_info tm_info; 875 876 u16 num_msi; 877 u16 num_msi_left; 878 u16 num_msi_used; 879 u32 base_msi_vector; 880 u16 *vector_status; 881 int *vector_irq; 882 u16 num_nic_msi; /* Num of nic vectors for this PF */ 883 u16 num_roce_msi; /* Num of roce vectors for this PF */ 884 int roce_base_vector; 885 886 unsigned long service_timer_period; 887 unsigned long service_timer_previous; 888 struct timer_list reset_timer; 889 struct delayed_work service_task; 890 891 bool cur_promisc; 892 int num_alloc_vfs; /* Actual number of VFs allocated */ 893 894 struct hclge_tqp *htqp; 895 struct hclge_vport *vport; 896 897 struct dentry *hclge_dbgfs; 898 899 struct hnae3_client *nic_client; 900 struct hnae3_client *roce_client; 901 902 #define HCLGE_FLAG_MAIN BIT(0) 903 #define HCLGE_FLAG_DCB_CAPABLE BIT(1) 904 #define HCLGE_FLAG_DCB_ENABLE BIT(2) 905 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3) 906 u32 flag; 907 908 u32 pkt_buf_size; /* Total pf buf size for tx/rx */ 909 u32 tx_buf_size; /* Tx buffer size for each TC */ 910 u32 dv_buf_size; /* Dv buffer size for each TC */ 911 912 u32 mps; /* Max packet size */ 913 /* vport_lock protect resource shared by vports */ 914 struct mutex vport_lock; 915 916 struct hclge_vlan_type_cfg vlan_type_cfg; 917 918 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 919 unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 920 921 unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 922 923 struct hclge_fd_cfg fd_cfg; 924 struct hlist_head fd_rule_list; 925 spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */ 926 u16 hclge_fd_rule_num; 927 unsigned long serv_processed_cnt; 928 unsigned long last_serv_processed; 929 unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)]; 930 enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type; 931 u8 fd_en; 932 bool gro_en; 933 934 u16 wanted_umv_size; 935 /* max available unicast mac vlan space */ 936 u16 max_umv_size; 937 /* private unicast mac vlan space, it's same for PF and its VFs */ 938 u16 priv_umv_size; 939 /* unicast mac vlan space shared by PF and its VFs */ 940 u16 share_umv_size; 941 942 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats, 943 HCLGE_MAC_TNL_LOG_SIZE); 944 945 /* affinity mask and notify for misc interrupt */ 946 cpumask_t affinity_mask; 947 struct irq_affinity_notify affinity_notify; 948 struct hclge_ptp *ptp; 949 struct devlink *devlink; 950 }; 951 952 /* VPort level vlan tag configuration for TX direction */ 953 struct hclge_tx_vtag_cfg { 954 bool accept_tag1; /* Whether accept tag1 packet from host */ 955 bool accept_untag1; /* Whether accept untag1 packet from host */ 956 bool accept_tag2; 957 bool accept_untag2; 958 bool insert_tag1_en; /* Whether insert inner vlan tag */ 959 bool insert_tag2_en; /* Whether insert outer vlan tag */ 960 u16 default_tag1; /* The default inner vlan tag to insert */ 961 u16 default_tag2; /* The default outer vlan tag to insert */ 962 bool tag_shift_mode_en; 963 }; 964 965 /* VPort level vlan tag configuration for RX direction */ 966 struct hclge_rx_vtag_cfg { 967 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ 968 bool strip_tag1_en; /* Whether strip inner vlan tag */ 969 bool strip_tag2_en; /* Whether strip outer vlan tag */ 970 bool vlan1_vlan_prionly; /* Inner vlan tag up to descriptor enable */ 971 bool vlan2_vlan_prionly; /* Outer vlan tag up to descriptor enable */ 972 bool strip_tag1_discard_en; /* Inner vlan tag discard for BD enable */ 973 bool strip_tag2_discard_en; /* Outer vlan tag discard for BD enable */ 974 }; 975 976 struct hclge_rss_tuple_cfg { 977 u8 ipv4_tcp_en; 978 u8 ipv4_udp_en; 979 u8 ipv4_sctp_en; 980 u8 ipv4_fragment_en; 981 u8 ipv6_tcp_en; 982 u8 ipv6_udp_en; 983 u8 ipv6_sctp_en; 984 u8 ipv6_fragment_en; 985 }; 986 987 enum HCLGE_VPORT_STATE { 988 HCLGE_VPORT_STATE_ALIVE, 989 HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 990 HCLGE_VPORT_STATE_PROMISC_CHANGE, 991 HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 992 HCLGE_VPORT_STATE_MAX 993 }; 994 995 struct hclge_vlan_info { 996 u16 vlan_proto; /* so far support 802.1Q only */ 997 u16 qos; 998 u16 vlan_tag; 999 }; 1000 1001 struct hclge_port_base_vlan_config { 1002 u16 state; 1003 struct hclge_vlan_info vlan_info; 1004 }; 1005 1006 struct hclge_vf_info { 1007 int link_state; 1008 u8 mac[ETH_ALEN]; 1009 u32 spoofchk; 1010 u32 max_tx_rate; 1011 u32 trusted; 1012 u8 request_uc_en; 1013 u8 request_mc_en; 1014 u8 request_bc_en; 1015 }; 1016 1017 struct hclge_vport { 1018 u16 alloc_tqps; /* Allocated Tx/Rx queues */ 1019 1020 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */ 1021 /* User configured lookup table entries */ 1022 u16 *rss_indirection_tbl; 1023 int rss_algo; /* User configured hash algorithm */ 1024 /* User configured rss tuple sets */ 1025 struct hclge_rss_tuple_cfg rss_tuple_sets; 1026 1027 u16 alloc_rss_size; 1028 1029 u16 qs_offset; 1030 u32 bw_limit; /* VSI BW Limit (0 = disabled) */ 1031 u8 dwrr; 1032 1033 bool req_vlan_fltr_en; 1034 bool cur_vlan_fltr_en; 1035 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 1036 struct hclge_port_base_vlan_config port_base_vlan_cfg; 1037 struct hclge_tx_vtag_cfg txvlan_cfg; 1038 struct hclge_rx_vtag_cfg rxvlan_cfg; 1039 1040 u16 used_umv_num; 1041 1042 u16 vport_id; 1043 struct hclge_dev *back; /* Back reference to associated dev */ 1044 struct hnae3_handle nic; 1045 struct hnae3_handle roce; 1046 1047 unsigned long state; 1048 unsigned long last_active_jiffies; 1049 u32 mps; /* Max packet size */ 1050 struct hclge_vf_info vf_info; 1051 1052 u8 overflow_promisc_flags; 1053 u8 last_promisc_flags; 1054 1055 spinlock_t mac_list_lock; /* protect mac address need to add/detele */ 1056 struct list_head uc_mac_list; /* Store VF unicast table */ 1057 struct list_head mc_mac_list; /* Store VF multicast table */ 1058 struct list_head vlan_list; /* Store VF vlan table */ 1059 }; 1060 1061 struct hclge_speed_bit_map { 1062 u32 speed; 1063 u32 speed_bit; 1064 }; 1065 1066 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 1067 bool en_mc_pmc, bool en_bc_pmc); 1068 int hclge_add_uc_addr_common(struct hclge_vport *vport, 1069 const unsigned char *addr); 1070 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 1071 const unsigned char *addr); 1072 int hclge_add_mc_addr_common(struct hclge_vport *vport, 1073 const unsigned char *addr); 1074 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 1075 const unsigned char *addr); 1076 1077 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle); 1078 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 1079 int vector_id, bool en, 1080 struct hnae3_ring_chain_node *ring_chain); 1081 1082 static inline int hclge_get_queue_id(struct hnae3_queue *queue) 1083 { 1084 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q); 1085 1086 return tqp->index; 1087 } 1088 1089 static inline bool hclge_is_reset_pending(struct hclge_dev *hdev) 1090 { 1091 return !!hdev->reset_pending; 1092 } 1093 1094 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport); 1095 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex); 1096 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 1097 u16 vlan_id, bool is_kill); 1098 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable); 1099 1100 int hclge_buffer_alloc(struct hclge_dev *hdev); 1101 int hclge_rss_init_hw(struct hclge_dev *hdev); 1102 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev); 1103 1104 void hclge_mbx_handler(struct hclge_dev *hdev); 1105 int hclge_reset_tqp(struct hnae3_handle *handle); 1106 int hclge_cfg_flowctrl(struct hclge_dev *hdev); 1107 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id); 1108 int hclge_vport_start(struct hclge_vport *vport); 1109 void hclge_vport_stop(struct hclge_vport *vport); 1110 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu); 1111 int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, 1112 char *buf, int len); 1113 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id); 1114 int hclge_notify_client(struct hclge_dev *hdev, 1115 enum hnae3_reset_notify_type type); 1116 int hclge_update_mac_list(struct hclge_vport *vport, 1117 enum HCLGE_MAC_NODE_STATE state, 1118 enum HCLGE_MAC_ADDR_TYPE mac_type, 1119 const unsigned char *addr); 1120 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 1121 const u8 *old_addr, const u8 *new_addr); 1122 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 1123 enum HCLGE_MAC_ADDR_TYPE mac_type); 1124 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list); 1125 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev); 1126 void hclge_restore_mac_table_common(struct hclge_vport *vport); 1127 void hclge_restore_vport_vlan_table(struct hclge_vport *vport); 1128 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 1129 struct hclge_vlan_info *vlan_info); 1130 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid, 1131 u16 state, 1132 struct hclge_vlan_info *vlan_info); 1133 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time); 1134 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, 1135 struct hclge_desc *desc); 1136 void hclge_report_hw_error(struct hclge_dev *hdev, 1137 enum hnae3_hw_error_type type); 1138 void hclge_inform_vf_promisc_info(struct hclge_vport *vport); 1139 int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len); 1140 int hclge_push_vf_link_status(struct hclge_vport *vport); 1141 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en); 1142 #endif 1143