1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_MAIN_H 5 #define __HCLGE_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include <linux/phy.h> 9 #include <linux/if_vlan.h> 10 #include <linux/kfifo.h> 11 12 #include "hclge_cmd.h" 13 #include "hnae3.h" 14 15 #define HCLGE_MOD_VERSION "1.0" 16 #define HCLGE_DRIVER_NAME "hclge" 17 18 #define HCLGE_MAX_PF_NUM 8 19 20 #define HCLGE_VF_VPORT_START_NUM 1 21 22 #define HCLGE_RD_FIRST_STATS_NUM 2 23 #define HCLGE_RD_OTHER_STATS_NUM 4 24 25 #define HCLGE_INVALID_VPORT 0xffff 26 27 #define HCLGE_PF_CFG_BLOCK_SIZE 32 28 #define HCLGE_PF_CFG_DESC_NUM \ 29 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) 30 31 #define HCLGE_VECTOR_REG_BASE 0x20000 32 #define HCLGE_VECTOR_EXT_REG_BASE 0x30000 33 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400 34 35 #define HCLGE_VECTOR_REG_OFFSET 0x4 36 #define HCLGE_VECTOR_REG_OFFSET_H 0x1000 37 #define HCLGE_VECTOR_VF_OFFSET 0x100000 38 39 #define HCLGE_CMDQ_TX_ADDR_L_REG 0x27000 40 #define HCLGE_CMDQ_TX_ADDR_H_REG 0x27004 41 #define HCLGE_CMDQ_TX_DEPTH_REG 0x27008 42 #define HCLGE_CMDQ_TX_TAIL_REG 0x27010 43 #define HCLGE_CMDQ_TX_HEAD_REG 0x27014 44 #define HCLGE_CMDQ_RX_ADDR_L_REG 0x27018 45 #define HCLGE_CMDQ_RX_ADDR_H_REG 0x2701C 46 #define HCLGE_CMDQ_RX_DEPTH_REG 0x27020 47 #define HCLGE_CMDQ_RX_TAIL_REG 0x27024 48 #define HCLGE_CMDQ_RX_HEAD_REG 0x27028 49 #define HCLGE_CMDQ_INTR_STS_REG 0x27104 50 #define HCLGE_CMDQ_INTR_EN_REG 0x27108 51 #define HCLGE_CMDQ_INTR_GEN_REG 0x2710C 52 53 /* bar registers for common func */ 54 #define HCLGE_VECTOR0_OTER_EN_REG 0x20600 55 #define HCLGE_GRO_EN_REG 0x28000 56 #define HCLGE_RXD_ADV_LAYOUT_EN_REG 0x28008 57 58 /* bar registers for rcb */ 59 #define HCLGE_RING_RX_ADDR_L_REG 0x80000 60 #define HCLGE_RING_RX_ADDR_H_REG 0x80004 61 #define HCLGE_RING_RX_BD_NUM_REG 0x80008 62 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C 63 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014 64 #define HCLGE_RING_RX_TAIL_REG 0x80018 65 #define HCLGE_RING_RX_HEAD_REG 0x8001C 66 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020 67 #define HCLGE_RING_RX_OFFSET_REG 0x80024 68 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028 69 #define HCLGE_RING_RX_STASH_REG 0x80030 70 #define HCLGE_RING_RX_BD_ERR_REG 0x80034 71 #define HCLGE_RING_TX_ADDR_L_REG 0x80040 72 #define HCLGE_RING_TX_ADDR_H_REG 0x80044 73 #define HCLGE_RING_TX_BD_NUM_REG 0x80048 74 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C 75 #define HCLGE_RING_TX_TC_REG 0x80050 76 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054 77 #define HCLGE_RING_TX_TAIL_REG 0x80058 78 #define HCLGE_RING_TX_HEAD_REG 0x8005C 79 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060 80 #define HCLGE_RING_TX_OFFSET_REG 0x80064 81 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068 82 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070 83 #define HCLGE_RING_TX_BD_ERR_REG 0x80074 84 #define HCLGE_RING_EN_REG 0x80090 85 86 /* bar registers for tqp interrupt */ 87 #define HCLGE_TQP_INTR_CTRL_REG 0x20000 88 #define HCLGE_TQP_INTR_GL0_REG 0x20100 89 #define HCLGE_TQP_INTR_GL1_REG 0x20200 90 #define HCLGE_TQP_INTR_GL2_REG 0x20300 91 #define HCLGE_TQP_INTR_RL_REG 0x20900 92 93 #define HCLGE_RSS_IND_TBL_SIZE 512 94 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0) 95 #define HCLGE_RSS_KEY_SIZE 40 96 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0 97 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1 98 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2 99 #define HCLGE_RSS_HASH_ALGO_MASK GENMASK(3, 0) 100 101 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 102 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 103 #define HCLGE_D_PORT_BIT BIT(0) 104 #define HCLGE_S_PORT_BIT BIT(1) 105 #define HCLGE_D_IP_BIT BIT(2) 106 #define HCLGE_S_IP_BIT BIT(3) 107 #define HCLGE_V_TAG_BIT BIT(4) 108 #define HCLGE_RSS_INPUT_TUPLE_SCTP_NO_PORT \ 109 (HCLGE_D_IP_BIT | HCLGE_S_IP_BIT | HCLGE_V_TAG_BIT) 110 111 #define HCLGE_RSS_TC_SIZE_0 1 112 #define HCLGE_RSS_TC_SIZE_1 2 113 #define HCLGE_RSS_TC_SIZE_2 4 114 #define HCLGE_RSS_TC_SIZE_3 8 115 #define HCLGE_RSS_TC_SIZE_4 16 116 #define HCLGE_RSS_TC_SIZE_5 32 117 #define HCLGE_RSS_TC_SIZE_6 64 118 #define HCLGE_RSS_TC_SIZE_7 128 119 120 #define HCLGE_UMV_TBL_SIZE 3072 121 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \ 122 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM) 123 124 #define HCLGE_TQP_RESET_TRY_TIMES 200 125 126 #define HCLGE_PHY_PAGE_MDIX 0 127 #define HCLGE_PHY_PAGE_COPPER 0 128 129 /* Page Selection Reg. */ 130 #define HCLGE_PHY_PAGE_REG 22 131 132 /* Copper Specific Control Register */ 133 #define HCLGE_PHY_CSC_REG 16 134 135 /* Copper Specific Status Register */ 136 #define HCLGE_PHY_CSS_REG 17 137 138 #define HCLGE_PHY_MDIX_CTRL_S 5 139 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) 140 141 #define HCLGE_PHY_MDIX_STATUS_B 6 142 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11 143 144 #define HCLGE_GET_DFX_REG_TYPE_CNT 4 145 146 /* Factor used to calculate offset and bitmap of VF num */ 147 #define HCLGE_VF_NUM_PER_CMD 64 148 149 #define HCLGE_MAX_QSET_NUM 1024 150 151 #define HCLGE_DBG_RESET_INFO_LEN 1024 152 153 enum HLCGE_PORT_TYPE { 154 HOST_PORT, 155 NETWORK_PORT 156 }; 157 158 #define PF_VPORT_ID 0 159 160 #define HCLGE_PF_ID_S 0 161 #define HCLGE_PF_ID_M GENMASK(2, 0) 162 #define HCLGE_VF_ID_S 3 163 #define HCLGE_VF_ID_M GENMASK(10, 3) 164 #define HCLGE_PORT_TYPE_B 11 165 #define HCLGE_NETWORK_PORT_ID_S 0 166 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0) 167 168 /* Reset related Registers */ 169 #define HCLGE_PF_OTHER_INT_REG 0x20600 170 #define HCLGE_MISC_RESET_STS_REG 0x20700 171 #define HCLGE_MISC_VECTOR_INT_STS 0x20800 172 #define HCLGE_GLOBAL_RESET_REG 0x20A00 173 #define HCLGE_GLOBAL_RESET_BIT 0 174 #define HCLGE_CORE_RESET_BIT 1 175 #define HCLGE_IMP_RESET_BIT 2 176 #define HCLGE_RESET_INT_M GENMASK(7, 5) 177 #define HCLGE_FUN_RST_ING 0x20C00 178 #define HCLGE_FUN_RST_ING_B 0 179 180 /* Vector0 register bits define */ 181 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5 182 #define HCLGE_VECTOR0_CORERESET_INT_B 6 183 #define HCLGE_VECTOR0_IMPRESET_INT_B 7 184 185 /* Vector0 interrupt CMDQ event source register(RW) */ 186 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100 187 /* CMDQ register bits for RX event(=MBX event) */ 188 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 189 190 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1 191 #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U 192 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U 193 194 #define HCLGE_MAC_DEFAULT_FRAME \ 195 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN) 196 #define HCLGE_MAC_MIN_FRAME 64 197 #define HCLGE_MAC_MAX_FRAME 9728 198 199 #define HCLGE_SUPPORT_1G_BIT BIT(0) 200 #define HCLGE_SUPPORT_10G_BIT BIT(1) 201 #define HCLGE_SUPPORT_25G_BIT BIT(2) 202 #define HCLGE_SUPPORT_50G_BIT BIT(3) 203 #define HCLGE_SUPPORT_100G_BIT BIT(4) 204 /* to be compatible with exsit board */ 205 #define HCLGE_SUPPORT_40G_BIT BIT(5) 206 #define HCLGE_SUPPORT_100M_BIT BIT(6) 207 #define HCLGE_SUPPORT_10M_BIT BIT(7) 208 #define HCLGE_SUPPORT_200G_BIT BIT(8) 209 #define HCLGE_SUPPORT_GE \ 210 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT) 211 212 enum HCLGE_DEV_STATE { 213 HCLGE_STATE_REINITING, 214 HCLGE_STATE_DOWN, 215 HCLGE_STATE_DISABLED, 216 HCLGE_STATE_REMOVING, 217 HCLGE_STATE_NIC_REGISTERED, 218 HCLGE_STATE_ROCE_REGISTERED, 219 HCLGE_STATE_SERVICE_INITED, 220 HCLGE_STATE_RST_SERVICE_SCHED, 221 HCLGE_STATE_RST_HANDLING, 222 HCLGE_STATE_MBX_SERVICE_SCHED, 223 HCLGE_STATE_MBX_HANDLING, 224 HCLGE_STATE_STATISTICS_UPDATING, 225 HCLGE_STATE_CMD_DISABLE, 226 HCLGE_STATE_LINK_UPDATING, 227 HCLGE_STATE_RST_FAIL, 228 HCLGE_STATE_FD_TBL_CHANGED, 229 HCLGE_STATE_FD_CLEAR_ALL, 230 HCLGE_STATE_FD_USER_DEF_CHANGED, 231 HCLGE_STATE_MAX 232 }; 233 234 enum hclge_evt_cause { 235 HCLGE_VECTOR0_EVENT_RST, 236 HCLGE_VECTOR0_EVENT_MBX, 237 HCLGE_VECTOR0_EVENT_ERR, 238 HCLGE_VECTOR0_EVENT_OTHER, 239 }; 240 241 enum HCLGE_MAC_SPEED { 242 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */ 243 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */ 244 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */ 245 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ 246 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ 247 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ 248 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ 249 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ 250 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */ 251 HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */ 252 }; 253 254 enum HCLGE_MAC_DUPLEX { 255 HCLGE_MAC_HALF, 256 HCLGE_MAC_FULL 257 }; 258 259 #define QUERY_SFP_SPEED 0 260 #define QUERY_ACTIVE_SPEED 1 261 262 struct hclge_mac { 263 u8 mac_id; 264 u8 phy_addr; 265 u8 flag; 266 u8 media_type; /* port media type, e.g. fibre/copper/backplane */ 267 u8 mac_addr[ETH_ALEN]; 268 u8 autoneg; 269 u8 duplex; 270 u8 support_autoneg; 271 u8 speed_type; /* 0: sfp speed, 1: active speed */ 272 u32 speed; 273 u32 max_speed; 274 u32 speed_ability; /* speed ability supported by current media */ 275 u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */ 276 u32 fec_mode; /* active fec mode */ 277 u32 user_fec_mode; 278 u32 fec_ability; 279 int link; /* store the link status of mac & phy (if phy exists) */ 280 struct phy_device *phydev; 281 struct mii_bus *mdio_bus; 282 phy_interface_t phy_if; 283 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 284 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 285 }; 286 287 struct hclge_hw { 288 void __iomem *io_base; 289 void __iomem *mem_base; 290 struct hclge_mac mac; 291 int num_vec; 292 struct hclge_cmq cmq; 293 }; 294 295 /* TQP stats */ 296 struct hlcge_tqp_stats { 297 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 298 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 299 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 300 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 301 }; 302 303 struct hclge_tqp { 304 /* copy of device pointer from pci_dev, 305 * used when perform DMA mapping 306 */ 307 struct device *dev; 308 struct hnae3_queue q; 309 struct hlcge_tqp_stats tqp_stats; 310 u16 index; /* Global index in a NIC controller */ 311 312 bool alloced; 313 }; 314 315 enum hclge_fc_mode { 316 HCLGE_FC_NONE, 317 HCLGE_FC_RX_PAUSE, 318 HCLGE_FC_TX_PAUSE, 319 HCLGE_FC_FULL, 320 HCLGE_FC_PFC, 321 HCLGE_FC_DEFAULT 322 }; 323 324 #define HCLGE_FILTER_TYPE_VF 0 325 #define HCLGE_FILTER_TYPE_PORT 1 326 #define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0) 327 #define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0) 328 #define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1) 329 #define HCLGE_FILTER_FE_ROCE_INGRESS_B BIT(2) 330 #define HCLGE_FILTER_FE_ROCE_EGRESS_B BIT(3) 331 #define HCLGE_FILTER_FE_EGRESS (HCLGE_FILTER_FE_NIC_EGRESS_B \ 332 | HCLGE_FILTER_FE_ROCE_EGRESS_B) 333 #define HCLGE_FILTER_FE_INGRESS (HCLGE_FILTER_FE_NIC_INGRESS_B \ 334 | HCLGE_FILTER_FE_ROCE_INGRESS_B) 335 336 enum hclge_vlan_fltr_cap { 337 HCLGE_VLAN_FLTR_DEF, 338 HCLGE_VLAN_FLTR_CAN_MDF, 339 }; 340 enum hclge_link_fail_code { 341 HCLGE_LF_NORMAL, 342 HCLGE_LF_REF_CLOCK_LOST, 343 HCLGE_LF_XSFP_TX_DISABLE, 344 HCLGE_LF_XSFP_ABSENT, 345 }; 346 347 #define HCLGE_LINK_STATUS_DOWN 0 348 #define HCLGE_LINK_STATUS_UP 1 349 350 #define HCLGE_PG_NUM 4 351 #define HCLGE_SCH_MODE_SP 0 352 #define HCLGE_SCH_MODE_DWRR 1 353 struct hclge_pg_info { 354 u8 pg_id; 355 u8 pg_sch_mode; /* 0: sp; 1: dwrr */ 356 u8 tc_bit_map; 357 u32 bw_limit; 358 u8 tc_dwrr[HNAE3_MAX_TC]; 359 }; 360 361 struct hclge_tc_info { 362 u8 tc_id; 363 u8 tc_sch_mode; /* 0: sp; 1: dwrr */ 364 u8 pgid; 365 u32 bw_limit; 366 }; 367 368 struct hclge_cfg { 369 u8 tc_num; 370 u8 vlan_fliter_cap; 371 u16 tqp_desc_num; 372 u16 rx_buf_len; 373 u16 vf_rss_size_max; 374 u16 pf_rss_size_max; 375 u8 phy_addr; 376 u8 media_type; 377 u8 mac_addr[ETH_ALEN]; 378 u8 default_speed; 379 u32 numa_node_map; 380 u16 speed_ability; 381 u16 umv_space; 382 }; 383 384 struct hclge_tm_info { 385 u8 num_tc; 386 u8 num_pg; /* It must be 1 if vNET-Base schd */ 387 u8 pg_dwrr[HCLGE_PG_NUM]; 388 u8 prio_tc[HNAE3_MAX_USER_PRIO]; 389 struct hclge_pg_info pg_info[HCLGE_PG_NUM]; 390 struct hclge_tc_info tc_info[HNAE3_MAX_TC]; 391 enum hclge_fc_mode fc_mode; 392 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */ 393 u8 pfc_en; /* PFC enabled or not for user priority */ 394 }; 395 396 struct hclge_comm_stats_str { 397 char desc[ETH_GSTRING_LEN]; 398 unsigned long offset; 399 }; 400 401 /* mac stats ,opcode id: 0x0032 */ 402 struct hclge_mac_stats { 403 u64 mac_tx_mac_pause_num; 404 u64 mac_rx_mac_pause_num; 405 u64 mac_tx_pfc_pri0_pkt_num; 406 u64 mac_tx_pfc_pri1_pkt_num; 407 u64 mac_tx_pfc_pri2_pkt_num; 408 u64 mac_tx_pfc_pri3_pkt_num; 409 u64 mac_tx_pfc_pri4_pkt_num; 410 u64 mac_tx_pfc_pri5_pkt_num; 411 u64 mac_tx_pfc_pri6_pkt_num; 412 u64 mac_tx_pfc_pri7_pkt_num; 413 u64 mac_rx_pfc_pri0_pkt_num; 414 u64 mac_rx_pfc_pri1_pkt_num; 415 u64 mac_rx_pfc_pri2_pkt_num; 416 u64 mac_rx_pfc_pri3_pkt_num; 417 u64 mac_rx_pfc_pri4_pkt_num; 418 u64 mac_rx_pfc_pri5_pkt_num; 419 u64 mac_rx_pfc_pri6_pkt_num; 420 u64 mac_rx_pfc_pri7_pkt_num; 421 u64 mac_tx_total_pkt_num; 422 u64 mac_tx_total_oct_num; 423 u64 mac_tx_good_pkt_num; 424 u64 mac_tx_bad_pkt_num; 425 u64 mac_tx_good_oct_num; 426 u64 mac_tx_bad_oct_num; 427 u64 mac_tx_uni_pkt_num; 428 u64 mac_tx_multi_pkt_num; 429 u64 mac_tx_broad_pkt_num; 430 u64 mac_tx_undersize_pkt_num; 431 u64 mac_tx_oversize_pkt_num; 432 u64 mac_tx_64_oct_pkt_num; 433 u64 mac_tx_65_127_oct_pkt_num; 434 u64 mac_tx_128_255_oct_pkt_num; 435 u64 mac_tx_256_511_oct_pkt_num; 436 u64 mac_tx_512_1023_oct_pkt_num; 437 u64 mac_tx_1024_1518_oct_pkt_num; 438 u64 mac_tx_1519_2047_oct_pkt_num; 439 u64 mac_tx_2048_4095_oct_pkt_num; 440 u64 mac_tx_4096_8191_oct_pkt_num; 441 u64 rsv0; 442 u64 mac_tx_8192_9216_oct_pkt_num; 443 u64 mac_tx_9217_12287_oct_pkt_num; 444 u64 mac_tx_12288_16383_oct_pkt_num; 445 u64 mac_tx_1519_max_good_oct_pkt_num; 446 u64 mac_tx_1519_max_bad_oct_pkt_num; 447 448 u64 mac_rx_total_pkt_num; 449 u64 mac_rx_total_oct_num; 450 u64 mac_rx_good_pkt_num; 451 u64 mac_rx_bad_pkt_num; 452 u64 mac_rx_good_oct_num; 453 u64 mac_rx_bad_oct_num; 454 u64 mac_rx_uni_pkt_num; 455 u64 mac_rx_multi_pkt_num; 456 u64 mac_rx_broad_pkt_num; 457 u64 mac_rx_undersize_pkt_num; 458 u64 mac_rx_oversize_pkt_num; 459 u64 mac_rx_64_oct_pkt_num; 460 u64 mac_rx_65_127_oct_pkt_num; 461 u64 mac_rx_128_255_oct_pkt_num; 462 u64 mac_rx_256_511_oct_pkt_num; 463 u64 mac_rx_512_1023_oct_pkt_num; 464 u64 mac_rx_1024_1518_oct_pkt_num; 465 u64 mac_rx_1519_2047_oct_pkt_num; 466 u64 mac_rx_2048_4095_oct_pkt_num; 467 u64 mac_rx_4096_8191_oct_pkt_num; 468 u64 rsv1; 469 u64 mac_rx_8192_9216_oct_pkt_num; 470 u64 mac_rx_9217_12287_oct_pkt_num; 471 u64 mac_rx_12288_16383_oct_pkt_num; 472 u64 mac_rx_1519_max_good_oct_pkt_num; 473 u64 mac_rx_1519_max_bad_oct_pkt_num; 474 475 u64 mac_tx_fragment_pkt_num; 476 u64 mac_tx_undermin_pkt_num; 477 u64 mac_tx_jabber_pkt_num; 478 u64 mac_tx_err_all_pkt_num; 479 u64 mac_tx_from_app_good_pkt_num; 480 u64 mac_tx_from_app_bad_pkt_num; 481 u64 mac_rx_fragment_pkt_num; 482 u64 mac_rx_undermin_pkt_num; 483 u64 mac_rx_jabber_pkt_num; 484 u64 mac_rx_fcs_err_pkt_num; 485 u64 mac_rx_send_app_good_pkt_num; 486 u64 mac_rx_send_app_bad_pkt_num; 487 u64 mac_tx_pfc_pause_pkt_num; 488 u64 mac_rx_pfc_pause_pkt_num; 489 u64 mac_tx_ctrl_pkt_num; 490 u64 mac_rx_ctrl_pkt_num; 491 }; 492 493 #define HCLGE_STATS_TIMER_INTERVAL 300UL 494 495 struct hclge_vlan_type_cfg { 496 u16 rx_ot_fst_vlan_type; 497 u16 rx_ot_sec_vlan_type; 498 u16 rx_in_fst_vlan_type; 499 u16 rx_in_sec_vlan_type; 500 u16 tx_ot_vlan_type; 501 u16 tx_in_vlan_type; 502 }; 503 504 enum HCLGE_FD_MODE { 505 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1, 506 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2, 507 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1, 508 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2, 509 }; 510 511 enum HCLGE_FD_KEY_TYPE { 512 HCLGE_FD_KEY_BASE_ON_PTYPE, 513 HCLGE_FD_KEY_BASE_ON_TUPLE, 514 }; 515 516 enum HCLGE_FD_STAGE { 517 HCLGE_FD_STAGE_1, 518 HCLGE_FD_STAGE_2, 519 MAX_STAGE_NUM, 520 }; 521 522 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet 523 * INNER_XXX indicate tuples in tunneled header of tunnel packet or 524 * tuples of non-tunnel packet 525 */ 526 enum HCLGE_FD_TUPLE { 527 OUTER_DST_MAC, 528 OUTER_SRC_MAC, 529 OUTER_VLAN_TAG_FST, 530 OUTER_VLAN_TAG_SEC, 531 OUTER_ETH_TYPE, 532 OUTER_L2_RSV, 533 OUTER_IP_TOS, 534 OUTER_IP_PROTO, 535 OUTER_SRC_IP, 536 OUTER_DST_IP, 537 OUTER_L3_RSV, 538 OUTER_SRC_PORT, 539 OUTER_DST_PORT, 540 OUTER_L4_RSV, 541 OUTER_TUN_VNI, 542 OUTER_TUN_FLOW_ID, 543 INNER_DST_MAC, 544 INNER_SRC_MAC, 545 INNER_VLAN_TAG_FST, 546 INNER_VLAN_TAG_SEC, 547 INNER_ETH_TYPE, 548 INNER_L2_RSV, 549 INNER_IP_TOS, 550 INNER_IP_PROTO, 551 INNER_SRC_IP, 552 INNER_DST_IP, 553 INNER_L3_RSV, 554 INNER_SRC_PORT, 555 INNER_DST_PORT, 556 INNER_L4_RSV, 557 MAX_TUPLE, 558 }; 559 560 #define HCLGE_FD_TUPLE_USER_DEF_TUPLES \ 561 (BIT(INNER_L2_RSV) | BIT(INNER_L3_RSV) | BIT(INNER_L4_RSV)) 562 563 enum HCLGE_FD_META_DATA { 564 PACKET_TYPE_ID, 565 IP_FRAGEMENT, 566 ROCE_TYPE, 567 NEXT_KEY, 568 VLAN_NUMBER, 569 SRC_VPORT, 570 DST_VPORT, 571 TUNNEL_PACKET, 572 MAX_META_DATA, 573 }; 574 575 enum HCLGE_FD_KEY_OPT { 576 KEY_OPT_U8, 577 KEY_OPT_LE16, 578 KEY_OPT_LE32, 579 KEY_OPT_MAC, 580 KEY_OPT_IP, 581 KEY_OPT_VNI, 582 }; 583 584 struct key_info { 585 u8 key_type; 586 u8 key_length; /* use bit as unit */ 587 enum HCLGE_FD_KEY_OPT key_opt; 588 int offset; 589 int moffset; 590 }; 591 592 #define MAX_KEY_LENGTH 400 593 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4) 594 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4) 595 #define MAX_META_DATA_LENGTH 32 596 597 #define HCLGE_FD_MAX_USER_DEF_OFFSET 9000 598 #define HCLGE_FD_USER_DEF_DATA GENMASK(15, 0) 599 #define HCLGE_FD_USER_DEF_OFFSET GENMASK(15, 0) 600 #define HCLGE_FD_USER_DEF_OFFSET_UNMASK GENMASK(15, 0) 601 602 /* assigned by firmware, the real filter number for each pf may be less */ 603 #define MAX_FD_FILTER_NUM 4096 604 #define HCLGE_ARFS_EXPIRE_INTERVAL 5UL 605 606 enum HCLGE_FD_ACTIVE_RULE_TYPE { 607 HCLGE_FD_RULE_NONE, 608 HCLGE_FD_ARFS_ACTIVE, 609 HCLGE_FD_EP_ACTIVE, 610 HCLGE_FD_TC_FLOWER_ACTIVE, 611 }; 612 613 enum HCLGE_FD_PACKET_TYPE { 614 NIC_PACKET, 615 ROCE_PACKET, 616 }; 617 618 enum HCLGE_FD_ACTION { 619 HCLGE_FD_ACTION_SELECT_QUEUE, 620 HCLGE_FD_ACTION_DROP_PACKET, 621 HCLGE_FD_ACTION_SELECT_TC, 622 }; 623 624 enum HCLGE_FD_NODE_STATE { 625 HCLGE_FD_TO_ADD, 626 HCLGE_FD_TO_DEL, 627 HCLGE_FD_ACTIVE, 628 HCLGE_FD_DELETED, 629 }; 630 631 enum HCLGE_FD_USER_DEF_LAYER { 632 HCLGE_FD_USER_DEF_NONE, 633 HCLGE_FD_USER_DEF_L2, 634 HCLGE_FD_USER_DEF_L3, 635 HCLGE_FD_USER_DEF_L4, 636 }; 637 638 #define HCLGE_FD_USER_DEF_LAYER_NUM 3 639 struct hclge_fd_user_def_cfg { 640 u16 ref_cnt; 641 u16 offset; 642 }; 643 644 struct hclge_fd_user_def_info { 645 enum HCLGE_FD_USER_DEF_LAYER layer; 646 u16 data; 647 u16 data_mask; 648 u16 offset; 649 }; 650 651 struct hclge_fd_key_cfg { 652 u8 key_sel; 653 u8 inner_sipv6_word_en; 654 u8 inner_dipv6_word_en; 655 u8 outer_sipv6_word_en; 656 u8 outer_dipv6_word_en; 657 u32 tuple_active; 658 u32 meta_data_active; 659 }; 660 661 struct hclge_fd_cfg { 662 u8 fd_mode; 663 u16 max_key_length; /* use bit as unit */ 664 u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */ 665 u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */ 666 struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM]; 667 struct hclge_fd_user_def_cfg user_def_cfg[HCLGE_FD_USER_DEF_LAYER_NUM]; 668 }; 669 670 #define IPV4_INDEX 3 671 #define IPV6_SIZE 4 672 struct hclge_fd_rule_tuples { 673 u8 src_mac[ETH_ALEN]; 674 u8 dst_mac[ETH_ALEN]; 675 /* Be compatible for ip address of both ipv4 and ipv6. 676 * For ipv4 address, we store it in src/dst_ip[3]. 677 */ 678 u32 src_ip[IPV6_SIZE]; 679 u32 dst_ip[IPV6_SIZE]; 680 u16 src_port; 681 u16 dst_port; 682 u16 vlan_tag1; 683 u16 ether_proto; 684 u16 l2_user_def; 685 u16 l3_user_def; 686 u32 l4_user_def; 687 u8 ip_tos; 688 u8 ip_proto; 689 }; 690 691 struct hclge_fd_rule { 692 struct hlist_node rule_node; 693 struct hclge_fd_rule_tuples tuples; 694 struct hclge_fd_rule_tuples tuples_mask; 695 u32 unused_tuple; 696 u32 flow_type; 697 union { 698 struct { 699 unsigned long cookie; 700 u8 tc; 701 } cls_flower; 702 struct { 703 u16 flow_id; /* only used for arfs */ 704 } arfs; 705 struct { 706 struct hclge_fd_user_def_info user_def; 707 } ep; 708 }; 709 u16 queue_id; 710 u16 vf_id; 711 u16 location; 712 enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type; 713 enum HCLGE_FD_NODE_STATE state; 714 u8 action; 715 }; 716 717 struct hclge_fd_ad_data { 718 u16 ad_id; 719 u8 drop_packet; 720 u8 forward_to_direct_queue; 721 u16 queue_id; 722 u8 use_counter; 723 u8 counter_id; 724 u8 use_next_stage; 725 u8 write_rule_id_to_bd; 726 u8 next_input_key; 727 u16 rule_id; 728 u16 tc_size; 729 u8 override_tc; 730 }; 731 732 enum HCLGE_MAC_NODE_STATE { 733 HCLGE_MAC_TO_ADD, 734 HCLGE_MAC_TO_DEL, 735 HCLGE_MAC_ACTIVE 736 }; 737 738 struct hclge_mac_node { 739 struct list_head node; 740 enum HCLGE_MAC_NODE_STATE state; 741 u8 mac_addr[ETH_ALEN]; 742 }; 743 744 enum HCLGE_MAC_ADDR_TYPE { 745 HCLGE_MAC_ADDR_UC, 746 HCLGE_MAC_ADDR_MC 747 }; 748 749 struct hclge_vport_vlan_cfg { 750 struct list_head node; 751 int hd_tbl_status; 752 u16 vlan_id; 753 }; 754 755 struct hclge_rst_stats { 756 u32 reset_done_cnt; /* the number of reset has completed */ 757 u32 hw_reset_done_cnt; /* the number of HW reset has completed */ 758 u32 pf_rst_cnt; /* the number of PF reset */ 759 u32 flr_rst_cnt; /* the number of FLR */ 760 u32 global_rst_cnt; /* the number of GLOBAL */ 761 u32 imp_rst_cnt; /* the number of IMP reset */ 762 u32 reset_cnt; /* the number of reset */ 763 u32 reset_fail_cnt; /* the number of reset fail */ 764 }; 765 766 /* time and register status when mac tunnel interruption occur */ 767 struct hclge_mac_tnl_stats { 768 u64 time; 769 u32 status; 770 }; 771 772 #define HCLGE_RESET_INTERVAL (10 * HZ) 773 #define HCLGE_WAIT_RESET_DONE 100 774 775 #pragma pack(1) 776 struct hclge_vf_vlan_cfg { 777 u8 mbx_cmd; 778 u8 subcode; 779 union { 780 struct { 781 u8 is_kill; 782 u16 vlan; 783 u16 proto; 784 }; 785 u8 enable; 786 }; 787 }; 788 789 #pragma pack() 790 791 /* For each bit of TCAM entry, it uses a pair of 'x' and 792 * 'y' to indicate which value to match, like below: 793 * ---------------------------------- 794 * | bit x | bit y | search value | 795 * ---------------------------------- 796 * | 0 | 0 | always hit | 797 * ---------------------------------- 798 * | 1 | 0 | match '0' | 799 * ---------------------------------- 800 * | 0 | 1 | match '1' | 801 * ---------------------------------- 802 * | 1 | 1 | invalid | 803 * ---------------------------------- 804 * Then for input key(k) and mask(v), we can calculate the value by 805 * the formulae: 806 * x = (~k) & v 807 * y = (k ^ ~v) & k 808 */ 809 #define calc_x(x, k, v) (x = ~(k) & (v)) 810 #define calc_y(y, k, v) \ 811 do { \ 812 const typeof(k) _k_ = (k); \ 813 const typeof(v) _v_ = (v); \ 814 (y) = (_k_ ^ ~_v_) & (_k_); \ 815 } while (0) 816 817 #define HCLGE_MAC_TNL_LOG_SIZE 8 818 #define HCLGE_VPORT_NUM 256 819 struct hclge_dev { 820 struct pci_dev *pdev; 821 struct hnae3_ae_dev *ae_dev; 822 struct hclge_hw hw; 823 struct hclge_misc_vector misc_vector; 824 struct hclge_mac_stats mac_stats; 825 unsigned long state; 826 unsigned long flr_state; 827 unsigned long last_reset_time; 828 829 enum hnae3_reset_type reset_type; 830 enum hnae3_reset_type reset_level; 831 unsigned long default_reset_request; 832 unsigned long reset_request; /* reset has been requested */ 833 unsigned long reset_pending; /* client rst is pending to be served */ 834 struct hclge_rst_stats rst_stats; 835 struct semaphore reset_sem; /* protect reset process */ 836 u32 fw_version; 837 u16 num_tqps; /* Num task queue pairs of this PF */ 838 u16 num_req_vfs; /* Num VFs requested for this PF */ 839 840 u16 base_tqp_pid; /* Base task tqp physical id of this PF */ 841 u16 alloc_rss_size; /* Allocated RSS task queue */ 842 u16 vf_rss_size_max; /* HW defined VF max RSS task queue */ 843 u16 pf_rss_size_max; /* HW defined PF max RSS task queue */ 844 845 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */ 846 u16 num_alloc_vport; /* Num vports this driver supports */ 847 u32 numa_node_mask; 848 u16 rx_buf_len; 849 u16 num_tx_desc; /* desc num of per tx queue */ 850 u16 num_rx_desc; /* desc num of per rx queue */ 851 u8 hw_tc_map; 852 enum hclge_fc_mode fc_mode_last_time; 853 u8 support_sfp_query; 854 855 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1 856 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2 857 u8 tx_sch_mode; 858 u8 tc_max; 859 u8 pfc_max; 860 861 u8 default_up; 862 u8 dcbx_cap; 863 struct hclge_tm_info tm_info; 864 865 u16 num_msi; 866 u16 num_msi_left; 867 u16 num_msi_used; 868 u32 base_msi_vector; 869 u16 *vector_status; 870 int *vector_irq; 871 u16 num_nic_msi; /* Num of nic vectors for this PF */ 872 u16 num_roce_msi; /* Num of roce vectors for this PF */ 873 int roce_base_vector; 874 875 unsigned long service_timer_period; 876 unsigned long service_timer_previous; 877 struct timer_list reset_timer; 878 struct delayed_work service_task; 879 880 bool cur_promisc; 881 int num_alloc_vfs; /* Actual number of VFs allocated */ 882 883 struct hclge_tqp *htqp; 884 struct hclge_vport *vport; 885 886 struct dentry *hclge_dbgfs; 887 888 struct hnae3_client *nic_client; 889 struct hnae3_client *roce_client; 890 891 #define HCLGE_FLAG_MAIN BIT(0) 892 #define HCLGE_FLAG_DCB_CAPABLE BIT(1) 893 #define HCLGE_FLAG_DCB_ENABLE BIT(2) 894 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3) 895 u32 flag; 896 897 u32 pkt_buf_size; /* Total pf buf size for tx/rx */ 898 u32 tx_buf_size; /* Tx buffer size for each TC */ 899 u32 dv_buf_size; /* Dv buffer size for each TC */ 900 901 u32 mps; /* Max packet size */ 902 /* vport_lock protect resource shared by vports */ 903 struct mutex vport_lock; 904 905 struct hclge_vlan_type_cfg vlan_type_cfg; 906 907 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 908 unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 909 910 unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 911 912 struct hclge_fd_cfg fd_cfg; 913 struct hlist_head fd_rule_list; 914 spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */ 915 u16 hclge_fd_rule_num; 916 unsigned long serv_processed_cnt; 917 unsigned long last_serv_processed; 918 unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)]; 919 enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type; 920 u8 fd_en; 921 922 u16 wanted_umv_size; 923 /* max available unicast mac vlan space */ 924 u16 max_umv_size; 925 /* private unicast mac vlan space, it's same for PF and its VFs */ 926 u16 priv_umv_size; 927 /* unicast mac vlan space shared by PF and its VFs */ 928 u16 share_umv_size; 929 930 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats, 931 HCLGE_MAC_TNL_LOG_SIZE); 932 933 /* affinity mask and notify for misc interrupt */ 934 cpumask_t affinity_mask; 935 struct irq_affinity_notify affinity_notify; 936 }; 937 938 /* VPort level vlan tag configuration for TX direction */ 939 struct hclge_tx_vtag_cfg { 940 bool accept_tag1; /* Whether accept tag1 packet from host */ 941 bool accept_untag1; /* Whether accept untag1 packet from host */ 942 bool accept_tag2; 943 bool accept_untag2; 944 bool insert_tag1_en; /* Whether insert inner vlan tag */ 945 bool insert_tag2_en; /* Whether insert outer vlan tag */ 946 u16 default_tag1; /* The default inner vlan tag to insert */ 947 u16 default_tag2; /* The default outer vlan tag to insert */ 948 bool tag_shift_mode_en; 949 }; 950 951 /* VPort level vlan tag configuration for RX direction */ 952 struct hclge_rx_vtag_cfg { 953 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ 954 bool strip_tag1_en; /* Whether strip inner vlan tag */ 955 bool strip_tag2_en; /* Whether strip outer vlan tag */ 956 bool vlan1_vlan_prionly; /* Inner vlan tag up to descriptor enable */ 957 bool vlan2_vlan_prionly; /* Outer vlan tag up to descriptor enable */ 958 bool strip_tag1_discard_en; /* Inner vlan tag discard for BD enable */ 959 bool strip_tag2_discard_en; /* Outer vlan tag discard for BD enable */ 960 }; 961 962 struct hclge_rss_tuple_cfg { 963 u8 ipv4_tcp_en; 964 u8 ipv4_udp_en; 965 u8 ipv4_sctp_en; 966 u8 ipv4_fragment_en; 967 u8 ipv6_tcp_en; 968 u8 ipv6_udp_en; 969 u8 ipv6_sctp_en; 970 u8 ipv6_fragment_en; 971 }; 972 973 enum HCLGE_VPORT_STATE { 974 HCLGE_VPORT_STATE_ALIVE, 975 HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 976 HCLGE_VPORT_STATE_PROMISC_CHANGE, 977 HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 978 HCLGE_VPORT_STATE_MAX 979 }; 980 981 struct hclge_vlan_info { 982 u16 vlan_proto; /* so far support 802.1Q only */ 983 u16 qos; 984 u16 vlan_tag; 985 }; 986 987 struct hclge_port_base_vlan_config { 988 u16 state; 989 struct hclge_vlan_info vlan_info; 990 }; 991 992 struct hclge_vf_info { 993 int link_state; 994 u8 mac[ETH_ALEN]; 995 u32 spoofchk; 996 u32 max_tx_rate; 997 u32 trusted; 998 u8 request_uc_en; 999 u8 request_mc_en; 1000 u8 request_bc_en; 1001 }; 1002 1003 struct hclge_vport { 1004 u16 alloc_tqps; /* Allocated Tx/Rx queues */ 1005 1006 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */ 1007 /* User configured lookup table entries */ 1008 u16 *rss_indirection_tbl; 1009 int rss_algo; /* User configured hash algorithm */ 1010 /* User configured rss tuple sets */ 1011 struct hclge_rss_tuple_cfg rss_tuple_sets; 1012 1013 u16 alloc_rss_size; 1014 1015 u16 qs_offset; 1016 u32 bw_limit; /* VSI BW Limit (0 = disabled) */ 1017 u8 dwrr; 1018 1019 bool req_vlan_fltr_en; 1020 bool cur_vlan_fltr_en; 1021 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 1022 struct hclge_port_base_vlan_config port_base_vlan_cfg; 1023 struct hclge_tx_vtag_cfg txvlan_cfg; 1024 struct hclge_rx_vtag_cfg rxvlan_cfg; 1025 1026 u16 used_umv_num; 1027 1028 u16 vport_id; 1029 struct hclge_dev *back; /* Back reference to associated dev */ 1030 struct hnae3_handle nic; 1031 struct hnae3_handle roce; 1032 1033 unsigned long state; 1034 unsigned long last_active_jiffies; 1035 u32 mps; /* Max packet size */ 1036 struct hclge_vf_info vf_info; 1037 1038 u8 overflow_promisc_flags; 1039 u8 last_promisc_flags; 1040 1041 spinlock_t mac_list_lock; /* protect mac address need to add/detele */ 1042 struct list_head uc_mac_list; /* Store VF unicast table */ 1043 struct list_head mc_mac_list; /* Store VF multicast table */ 1044 struct list_head vlan_list; /* Store VF vlan table */ 1045 }; 1046 1047 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 1048 bool en_mc_pmc, bool en_bc_pmc); 1049 int hclge_add_uc_addr_common(struct hclge_vport *vport, 1050 const unsigned char *addr); 1051 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 1052 const unsigned char *addr); 1053 int hclge_add_mc_addr_common(struct hclge_vport *vport, 1054 const unsigned char *addr); 1055 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 1056 const unsigned char *addr); 1057 1058 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle); 1059 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 1060 int vector_id, bool en, 1061 struct hnae3_ring_chain_node *ring_chain); 1062 1063 static inline int hclge_get_queue_id(struct hnae3_queue *queue) 1064 { 1065 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q); 1066 1067 return tqp->index; 1068 } 1069 1070 static inline bool hclge_is_reset_pending(struct hclge_dev *hdev) 1071 { 1072 return !!hdev->reset_pending; 1073 } 1074 1075 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport); 1076 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex); 1077 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 1078 u16 vlan_id, bool is_kill); 1079 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable); 1080 1081 int hclge_buffer_alloc(struct hclge_dev *hdev); 1082 int hclge_rss_init_hw(struct hclge_dev *hdev); 1083 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev); 1084 1085 void hclge_mbx_handler(struct hclge_dev *hdev); 1086 int hclge_reset_tqp(struct hnae3_handle *handle); 1087 int hclge_cfg_flowctrl(struct hclge_dev *hdev); 1088 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id); 1089 int hclge_vport_start(struct hclge_vport *vport); 1090 void hclge_vport_stop(struct hclge_vport *vport); 1091 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu); 1092 int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, 1093 char *buf, int len); 1094 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id); 1095 int hclge_notify_client(struct hclge_dev *hdev, 1096 enum hnae3_reset_notify_type type); 1097 int hclge_update_mac_list(struct hclge_vport *vport, 1098 enum HCLGE_MAC_NODE_STATE state, 1099 enum HCLGE_MAC_ADDR_TYPE mac_type, 1100 const unsigned char *addr); 1101 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 1102 const u8 *old_addr, const u8 *new_addr); 1103 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 1104 enum HCLGE_MAC_ADDR_TYPE mac_type); 1105 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list); 1106 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev); 1107 void hclge_restore_mac_table_common(struct hclge_vport *vport); 1108 void hclge_restore_vport_vlan_table(struct hclge_vport *vport); 1109 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 1110 struct hclge_vlan_info *vlan_info); 1111 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid, 1112 u16 state, 1113 struct hclge_vlan_info *vlan_info); 1114 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time); 1115 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, 1116 struct hclge_desc *desc); 1117 void hclge_report_hw_error(struct hclge_dev *hdev, 1118 enum hnae3_hw_error_type type); 1119 void hclge_inform_vf_promisc_info(struct hclge_vport *vport); 1120 int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len); 1121 int hclge_push_vf_link_status(struct hclge_vport *vport); 1122 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en); 1123 #endif 1124