1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_MAIN_H 5 #define __HCLGE_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include <linux/phy.h> 9 #include <linux/if_vlan.h> 10 #include <linux/kfifo.h> 11 12 #include "hclge_cmd.h" 13 #include "hnae3.h" 14 15 #define HCLGE_MOD_VERSION "1.0" 16 #define HCLGE_DRIVER_NAME "hclge" 17 18 #define HCLGE_MAX_PF_NUM 8 19 20 #define HCLGE_RD_FIRST_STATS_NUM 2 21 #define HCLGE_RD_OTHER_STATS_NUM 4 22 23 #define HCLGE_INVALID_VPORT 0xffff 24 25 #define HCLGE_PF_CFG_BLOCK_SIZE 32 26 #define HCLGE_PF_CFG_DESC_NUM \ 27 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) 28 29 #define HCLGE_VECTOR_REG_BASE 0x20000 30 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400 31 32 #define HCLGE_VECTOR_REG_OFFSET 0x4 33 #define HCLGE_VECTOR_VF_OFFSET 0x100000 34 35 #define HCLGE_CMDQ_TX_ADDR_L_REG 0x27000 36 #define HCLGE_CMDQ_TX_ADDR_H_REG 0x27004 37 #define HCLGE_CMDQ_TX_DEPTH_REG 0x27008 38 #define HCLGE_CMDQ_TX_TAIL_REG 0x27010 39 #define HCLGE_CMDQ_TX_HEAD_REG 0x27014 40 #define HCLGE_CMDQ_RX_ADDR_L_REG 0x27018 41 #define HCLGE_CMDQ_RX_ADDR_H_REG 0x2701C 42 #define HCLGE_CMDQ_RX_DEPTH_REG 0x27020 43 #define HCLGE_CMDQ_RX_TAIL_REG 0x27024 44 #define HCLGE_CMDQ_RX_HEAD_REG 0x27028 45 #define HCLGE_CMDQ_INTR_SRC_REG 0x27100 46 #define HCLGE_CMDQ_INTR_STS_REG 0x27104 47 #define HCLGE_CMDQ_INTR_EN_REG 0x27108 48 #define HCLGE_CMDQ_INTR_GEN_REG 0x2710C 49 50 /* bar registers for common func */ 51 #define HCLGE_VECTOR0_OTER_EN_REG 0x20600 52 #define HCLGE_RAS_OTHER_STS_REG 0x20B00 53 #define HCLGE_FUNC_RESET_STS_REG 0x20C00 54 #define HCLGE_GRO_EN_REG 0x28000 55 56 /* bar registers for rcb */ 57 #define HCLGE_RING_RX_ADDR_L_REG 0x80000 58 #define HCLGE_RING_RX_ADDR_H_REG 0x80004 59 #define HCLGE_RING_RX_BD_NUM_REG 0x80008 60 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C 61 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014 62 #define HCLGE_RING_RX_TAIL_REG 0x80018 63 #define HCLGE_RING_RX_HEAD_REG 0x8001C 64 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020 65 #define HCLGE_RING_RX_OFFSET_REG 0x80024 66 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028 67 #define HCLGE_RING_RX_STASH_REG 0x80030 68 #define HCLGE_RING_RX_BD_ERR_REG 0x80034 69 #define HCLGE_RING_TX_ADDR_L_REG 0x80040 70 #define HCLGE_RING_TX_ADDR_H_REG 0x80044 71 #define HCLGE_RING_TX_BD_NUM_REG 0x80048 72 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C 73 #define HCLGE_RING_TX_TC_REG 0x80050 74 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054 75 #define HCLGE_RING_TX_TAIL_REG 0x80058 76 #define HCLGE_RING_TX_HEAD_REG 0x8005C 77 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060 78 #define HCLGE_RING_TX_OFFSET_REG 0x80064 79 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068 80 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070 81 #define HCLGE_RING_TX_BD_ERR_REG 0x80074 82 #define HCLGE_RING_EN_REG 0x80090 83 84 /* bar registers for tqp interrupt */ 85 #define HCLGE_TQP_INTR_CTRL_REG 0x20000 86 #define HCLGE_TQP_INTR_GL0_REG 0x20100 87 #define HCLGE_TQP_INTR_GL1_REG 0x20200 88 #define HCLGE_TQP_INTR_GL2_REG 0x20300 89 #define HCLGE_TQP_INTR_RL_REG 0x20900 90 91 #define HCLGE_RSS_IND_TBL_SIZE 512 92 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0) 93 #define HCLGE_RSS_KEY_SIZE 40 94 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0 95 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1 96 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2 97 #define HCLGE_RSS_HASH_ALGO_MASK GENMASK(3, 0) 98 #define HCLGE_RSS_CFG_TBL_NUM \ 99 (HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE) 100 101 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 102 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 103 #define HCLGE_D_PORT_BIT BIT(0) 104 #define HCLGE_S_PORT_BIT BIT(1) 105 #define HCLGE_D_IP_BIT BIT(2) 106 #define HCLGE_S_IP_BIT BIT(3) 107 #define HCLGE_V_TAG_BIT BIT(4) 108 109 #define HCLGE_RSS_TC_SIZE_0 1 110 #define HCLGE_RSS_TC_SIZE_1 2 111 #define HCLGE_RSS_TC_SIZE_2 4 112 #define HCLGE_RSS_TC_SIZE_3 8 113 #define HCLGE_RSS_TC_SIZE_4 16 114 #define HCLGE_RSS_TC_SIZE_5 32 115 #define HCLGE_RSS_TC_SIZE_6 64 116 #define HCLGE_RSS_TC_SIZE_7 128 117 118 #define HCLGE_UMV_TBL_SIZE 3072 119 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \ 120 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM) 121 122 #define HCLGE_TQP_RESET_TRY_TIMES 200 123 124 #define HCLGE_PHY_PAGE_MDIX 0 125 #define HCLGE_PHY_PAGE_COPPER 0 126 127 /* Page Selection Reg. */ 128 #define HCLGE_PHY_PAGE_REG 22 129 130 /* Copper Specific Control Register */ 131 #define HCLGE_PHY_CSC_REG 16 132 133 /* Copper Specific Status Register */ 134 #define HCLGE_PHY_CSS_REG 17 135 136 #define HCLGE_PHY_MDIX_CTRL_S 5 137 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) 138 139 #define HCLGE_PHY_MDIX_STATUS_B 6 140 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11 141 142 #define HCLGE_GET_DFX_REG_TYPE_CNT 4 143 144 /* Factor used to calculate offset and bitmap of VF num */ 145 #define HCLGE_VF_NUM_PER_CMD 64 146 147 enum HLCGE_PORT_TYPE { 148 HOST_PORT, 149 NETWORK_PORT 150 }; 151 152 #define PF_VPORT_ID 0 153 154 #define HCLGE_PF_ID_S 0 155 #define HCLGE_PF_ID_M GENMASK(2, 0) 156 #define HCLGE_VF_ID_S 3 157 #define HCLGE_VF_ID_M GENMASK(10, 3) 158 #define HCLGE_PORT_TYPE_B 11 159 #define HCLGE_NETWORK_PORT_ID_S 0 160 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0) 161 162 /* Reset related Registers */ 163 #define HCLGE_PF_OTHER_INT_REG 0x20600 164 #define HCLGE_MISC_RESET_STS_REG 0x20700 165 #define HCLGE_MISC_VECTOR_INT_STS 0x20800 166 #define HCLGE_GLOBAL_RESET_REG 0x20A00 167 #define HCLGE_GLOBAL_RESET_BIT 0 168 #define HCLGE_CORE_RESET_BIT 1 169 #define HCLGE_IMP_RESET_BIT 2 170 #define HCLGE_RESET_INT_M GENMASK(7, 5) 171 #define HCLGE_FUN_RST_ING 0x20C00 172 #define HCLGE_FUN_RST_ING_B 0 173 174 /* Vector0 register bits define */ 175 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5 176 #define HCLGE_VECTOR0_CORERESET_INT_B 6 177 #define HCLGE_VECTOR0_IMPRESET_INT_B 7 178 179 /* Vector0 interrupt CMDQ event source register(RW) */ 180 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100 181 /* CMDQ register bits for RX event(=MBX event) */ 182 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 183 184 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1 185 #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U 186 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U 187 188 #define HCLGE_MAC_DEFAULT_FRAME \ 189 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN) 190 #define HCLGE_MAC_MIN_FRAME 64 191 #define HCLGE_MAC_MAX_FRAME 9728 192 193 #define HCLGE_SUPPORT_1G_BIT BIT(0) 194 #define HCLGE_SUPPORT_10G_BIT BIT(1) 195 #define HCLGE_SUPPORT_25G_BIT BIT(2) 196 #define HCLGE_SUPPORT_50G_BIT BIT(3) 197 #define HCLGE_SUPPORT_100G_BIT BIT(4) 198 /* to be compatible with exsit board */ 199 #define HCLGE_SUPPORT_40G_BIT BIT(5) 200 #define HCLGE_SUPPORT_100M_BIT BIT(6) 201 #define HCLGE_SUPPORT_10M_BIT BIT(7) 202 #define HCLGE_SUPPORT_GE \ 203 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT) 204 205 enum HCLGE_DEV_STATE { 206 HCLGE_STATE_REINITING, 207 HCLGE_STATE_DOWN, 208 HCLGE_STATE_DISABLED, 209 HCLGE_STATE_REMOVING, 210 HCLGE_STATE_NIC_REGISTERED, 211 HCLGE_STATE_ROCE_REGISTERED, 212 HCLGE_STATE_SERVICE_INITED, 213 HCLGE_STATE_RST_SERVICE_SCHED, 214 HCLGE_STATE_RST_HANDLING, 215 HCLGE_STATE_MBX_SERVICE_SCHED, 216 HCLGE_STATE_MBX_HANDLING, 217 HCLGE_STATE_STATISTICS_UPDATING, 218 HCLGE_STATE_CMD_DISABLE, 219 HCLGE_STATE_LINK_UPDATING, 220 HCLGE_STATE_RST_FAIL, 221 HCLGE_STATE_MAX 222 }; 223 224 enum hclge_evt_cause { 225 HCLGE_VECTOR0_EVENT_RST, 226 HCLGE_VECTOR0_EVENT_MBX, 227 HCLGE_VECTOR0_EVENT_ERR, 228 HCLGE_VECTOR0_EVENT_OTHER, 229 }; 230 231 enum HCLGE_MAC_SPEED { 232 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */ 233 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */ 234 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */ 235 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ 236 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ 237 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ 238 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ 239 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ 240 HCLGE_MAC_SPEED_100G = 100000 /* 100000 Mbps = 100 Gbps */ 241 }; 242 243 enum HCLGE_MAC_DUPLEX { 244 HCLGE_MAC_HALF, 245 HCLGE_MAC_FULL 246 }; 247 248 #define QUERY_SFP_SPEED 0 249 #define QUERY_ACTIVE_SPEED 1 250 251 struct hclge_mac { 252 u8 phy_addr; 253 u8 flag; 254 u8 media_type; /* port media type, e.g. fibre/copper/backplane */ 255 u8 mac_addr[ETH_ALEN]; 256 u8 autoneg; 257 u8 duplex; 258 u8 support_autoneg; 259 u8 speed_type; /* 0: sfp speed, 1: active speed */ 260 u32 speed; 261 u32 max_speed; 262 u32 speed_ability; /* speed ability supported by current media */ 263 u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */ 264 u32 fec_mode; /* active fec mode */ 265 u32 user_fec_mode; 266 u32 fec_ability; 267 int link; /* store the link status of mac & phy (if phy exit) */ 268 struct phy_device *phydev; 269 struct mii_bus *mdio_bus; 270 phy_interface_t phy_if; 271 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 272 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 273 }; 274 275 struct hclge_hw { 276 void __iomem *io_base; 277 struct hclge_mac mac; 278 int num_vec; 279 struct hclge_cmq cmq; 280 }; 281 282 /* TQP stats */ 283 struct hlcge_tqp_stats { 284 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 285 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 286 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 287 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 288 }; 289 290 struct hclge_tqp { 291 /* copy of device pointer from pci_dev, 292 * used when perform DMA mapping 293 */ 294 struct device *dev; 295 struct hnae3_queue q; 296 struct hlcge_tqp_stats tqp_stats; 297 u16 index; /* Global index in a NIC controller */ 298 299 bool alloced; 300 }; 301 302 enum hclge_fc_mode { 303 HCLGE_FC_NONE, 304 HCLGE_FC_RX_PAUSE, 305 HCLGE_FC_TX_PAUSE, 306 HCLGE_FC_FULL, 307 HCLGE_FC_PFC, 308 HCLGE_FC_DEFAULT 309 }; 310 311 enum hclge_link_fail_code { 312 HCLGE_LF_NORMAL, 313 HCLGE_LF_REF_CLOCK_LOST, 314 HCLGE_LF_XSFP_TX_DISABLE, 315 HCLGE_LF_XSFP_ABSENT, 316 }; 317 318 #define HCLGE_PG_NUM 4 319 #define HCLGE_SCH_MODE_SP 0 320 #define HCLGE_SCH_MODE_DWRR 1 321 struct hclge_pg_info { 322 u8 pg_id; 323 u8 pg_sch_mode; /* 0: sp; 1: dwrr */ 324 u8 tc_bit_map; 325 u32 bw_limit; 326 u8 tc_dwrr[HNAE3_MAX_TC]; 327 }; 328 329 struct hclge_tc_info { 330 u8 tc_id; 331 u8 tc_sch_mode; /* 0: sp; 1: dwrr */ 332 u8 pgid; 333 u32 bw_limit; 334 }; 335 336 struct hclge_cfg { 337 u8 vmdq_vport_num; 338 u8 tc_num; 339 u16 tqp_desc_num; 340 u16 rx_buf_len; 341 u16 rss_size_max; 342 u8 phy_addr; 343 u8 media_type; 344 u8 mac_addr[ETH_ALEN]; 345 u8 default_speed; 346 u32 numa_node_map; 347 u8 speed_ability; 348 u16 umv_space; 349 }; 350 351 struct hclge_tm_info { 352 u8 num_tc; 353 u8 num_pg; /* It must be 1 if vNET-Base schd */ 354 u8 pg_dwrr[HCLGE_PG_NUM]; 355 u8 prio_tc[HNAE3_MAX_USER_PRIO]; 356 struct hclge_pg_info pg_info[HCLGE_PG_NUM]; 357 struct hclge_tc_info tc_info[HNAE3_MAX_TC]; 358 enum hclge_fc_mode fc_mode; 359 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */ 360 u8 pfc_en; /* PFC enabled or not for user priority */ 361 }; 362 363 struct hclge_comm_stats_str { 364 char desc[ETH_GSTRING_LEN]; 365 unsigned long offset; 366 }; 367 368 /* mac stats ,opcode id: 0x0032 */ 369 struct hclge_mac_stats { 370 u64 mac_tx_mac_pause_num; 371 u64 mac_rx_mac_pause_num; 372 u64 mac_tx_pfc_pri0_pkt_num; 373 u64 mac_tx_pfc_pri1_pkt_num; 374 u64 mac_tx_pfc_pri2_pkt_num; 375 u64 mac_tx_pfc_pri3_pkt_num; 376 u64 mac_tx_pfc_pri4_pkt_num; 377 u64 mac_tx_pfc_pri5_pkt_num; 378 u64 mac_tx_pfc_pri6_pkt_num; 379 u64 mac_tx_pfc_pri7_pkt_num; 380 u64 mac_rx_pfc_pri0_pkt_num; 381 u64 mac_rx_pfc_pri1_pkt_num; 382 u64 mac_rx_pfc_pri2_pkt_num; 383 u64 mac_rx_pfc_pri3_pkt_num; 384 u64 mac_rx_pfc_pri4_pkt_num; 385 u64 mac_rx_pfc_pri5_pkt_num; 386 u64 mac_rx_pfc_pri6_pkt_num; 387 u64 mac_rx_pfc_pri7_pkt_num; 388 u64 mac_tx_total_pkt_num; 389 u64 mac_tx_total_oct_num; 390 u64 mac_tx_good_pkt_num; 391 u64 mac_tx_bad_pkt_num; 392 u64 mac_tx_good_oct_num; 393 u64 mac_tx_bad_oct_num; 394 u64 mac_tx_uni_pkt_num; 395 u64 mac_tx_multi_pkt_num; 396 u64 mac_tx_broad_pkt_num; 397 u64 mac_tx_undersize_pkt_num; 398 u64 mac_tx_oversize_pkt_num; 399 u64 mac_tx_64_oct_pkt_num; 400 u64 mac_tx_65_127_oct_pkt_num; 401 u64 mac_tx_128_255_oct_pkt_num; 402 u64 mac_tx_256_511_oct_pkt_num; 403 u64 mac_tx_512_1023_oct_pkt_num; 404 u64 mac_tx_1024_1518_oct_pkt_num; 405 u64 mac_tx_1519_2047_oct_pkt_num; 406 u64 mac_tx_2048_4095_oct_pkt_num; 407 u64 mac_tx_4096_8191_oct_pkt_num; 408 u64 rsv0; 409 u64 mac_tx_8192_9216_oct_pkt_num; 410 u64 mac_tx_9217_12287_oct_pkt_num; 411 u64 mac_tx_12288_16383_oct_pkt_num; 412 u64 mac_tx_1519_max_good_oct_pkt_num; 413 u64 mac_tx_1519_max_bad_oct_pkt_num; 414 415 u64 mac_rx_total_pkt_num; 416 u64 mac_rx_total_oct_num; 417 u64 mac_rx_good_pkt_num; 418 u64 mac_rx_bad_pkt_num; 419 u64 mac_rx_good_oct_num; 420 u64 mac_rx_bad_oct_num; 421 u64 mac_rx_uni_pkt_num; 422 u64 mac_rx_multi_pkt_num; 423 u64 mac_rx_broad_pkt_num; 424 u64 mac_rx_undersize_pkt_num; 425 u64 mac_rx_oversize_pkt_num; 426 u64 mac_rx_64_oct_pkt_num; 427 u64 mac_rx_65_127_oct_pkt_num; 428 u64 mac_rx_128_255_oct_pkt_num; 429 u64 mac_rx_256_511_oct_pkt_num; 430 u64 mac_rx_512_1023_oct_pkt_num; 431 u64 mac_rx_1024_1518_oct_pkt_num; 432 u64 mac_rx_1519_2047_oct_pkt_num; 433 u64 mac_rx_2048_4095_oct_pkt_num; 434 u64 mac_rx_4096_8191_oct_pkt_num; 435 u64 rsv1; 436 u64 mac_rx_8192_9216_oct_pkt_num; 437 u64 mac_rx_9217_12287_oct_pkt_num; 438 u64 mac_rx_12288_16383_oct_pkt_num; 439 u64 mac_rx_1519_max_good_oct_pkt_num; 440 u64 mac_rx_1519_max_bad_oct_pkt_num; 441 442 u64 mac_tx_fragment_pkt_num; 443 u64 mac_tx_undermin_pkt_num; 444 u64 mac_tx_jabber_pkt_num; 445 u64 mac_tx_err_all_pkt_num; 446 u64 mac_tx_from_app_good_pkt_num; 447 u64 mac_tx_from_app_bad_pkt_num; 448 u64 mac_rx_fragment_pkt_num; 449 u64 mac_rx_undermin_pkt_num; 450 u64 mac_rx_jabber_pkt_num; 451 u64 mac_rx_fcs_err_pkt_num; 452 u64 mac_rx_send_app_good_pkt_num; 453 u64 mac_rx_send_app_bad_pkt_num; 454 u64 mac_tx_pfc_pause_pkt_num; 455 u64 mac_rx_pfc_pause_pkt_num; 456 u64 mac_tx_ctrl_pkt_num; 457 u64 mac_rx_ctrl_pkt_num; 458 }; 459 460 #define HCLGE_STATS_TIMER_INTERVAL 300UL 461 462 struct hclge_vlan_type_cfg { 463 u16 rx_ot_fst_vlan_type; 464 u16 rx_ot_sec_vlan_type; 465 u16 rx_in_fst_vlan_type; 466 u16 rx_in_sec_vlan_type; 467 u16 tx_ot_vlan_type; 468 u16 tx_in_vlan_type; 469 }; 470 471 enum HCLGE_FD_MODE { 472 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1, 473 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2, 474 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1, 475 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2, 476 }; 477 478 enum HCLGE_FD_KEY_TYPE { 479 HCLGE_FD_KEY_BASE_ON_PTYPE, 480 HCLGE_FD_KEY_BASE_ON_TUPLE, 481 }; 482 483 enum HCLGE_FD_STAGE { 484 HCLGE_FD_STAGE_1, 485 HCLGE_FD_STAGE_2, 486 MAX_STAGE_NUM, 487 }; 488 489 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet 490 * INNER_XXX indicate tuples in tunneled header of tunnel packet or 491 * tuples of non-tunnel packet 492 */ 493 enum HCLGE_FD_TUPLE { 494 OUTER_DST_MAC, 495 OUTER_SRC_MAC, 496 OUTER_VLAN_TAG_FST, 497 OUTER_VLAN_TAG_SEC, 498 OUTER_ETH_TYPE, 499 OUTER_L2_RSV, 500 OUTER_IP_TOS, 501 OUTER_IP_PROTO, 502 OUTER_SRC_IP, 503 OUTER_DST_IP, 504 OUTER_L3_RSV, 505 OUTER_SRC_PORT, 506 OUTER_DST_PORT, 507 OUTER_L4_RSV, 508 OUTER_TUN_VNI, 509 OUTER_TUN_FLOW_ID, 510 INNER_DST_MAC, 511 INNER_SRC_MAC, 512 INNER_VLAN_TAG_FST, 513 INNER_VLAN_TAG_SEC, 514 INNER_ETH_TYPE, 515 INNER_L2_RSV, 516 INNER_IP_TOS, 517 INNER_IP_PROTO, 518 INNER_SRC_IP, 519 INNER_DST_IP, 520 INNER_L3_RSV, 521 INNER_SRC_PORT, 522 INNER_DST_PORT, 523 INNER_L4_RSV, 524 MAX_TUPLE, 525 }; 526 527 enum HCLGE_FD_META_DATA { 528 PACKET_TYPE_ID, 529 IP_FRAGEMENT, 530 ROCE_TYPE, 531 NEXT_KEY, 532 VLAN_NUMBER, 533 SRC_VPORT, 534 DST_VPORT, 535 TUNNEL_PACKET, 536 MAX_META_DATA, 537 }; 538 539 struct key_info { 540 u8 key_type; 541 u8 key_length; /* use bit as unit */ 542 }; 543 544 #define MAX_KEY_LENGTH 400 545 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4) 546 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4) 547 #define MAX_META_DATA_LENGTH 32 548 549 /* assigned by firmware, the real filter number for each pf may be less */ 550 #define MAX_FD_FILTER_NUM 4096 551 #define HCLGE_ARFS_EXPIRE_INTERVAL 5UL 552 553 enum HCLGE_FD_ACTIVE_RULE_TYPE { 554 HCLGE_FD_RULE_NONE, 555 HCLGE_FD_ARFS_ACTIVE, 556 HCLGE_FD_EP_ACTIVE, 557 }; 558 559 enum HCLGE_FD_PACKET_TYPE { 560 NIC_PACKET, 561 ROCE_PACKET, 562 }; 563 564 enum HCLGE_FD_ACTION { 565 HCLGE_FD_ACTION_ACCEPT_PACKET, 566 HCLGE_FD_ACTION_DROP_PACKET, 567 }; 568 569 struct hclge_fd_key_cfg { 570 u8 key_sel; 571 u8 inner_sipv6_word_en; 572 u8 inner_dipv6_word_en; 573 u8 outer_sipv6_word_en; 574 u8 outer_dipv6_word_en; 575 u32 tuple_active; 576 u32 meta_data_active; 577 }; 578 579 struct hclge_fd_cfg { 580 u8 fd_mode; 581 u16 max_key_length; /* use bit as unit */ 582 u32 proto_support; 583 u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */ 584 u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */ 585 struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM]; 586 }; 587 588 #define IPV4_INDEX 3 589 #define IPV6_SIZE 4 590 struct hclge_fd_rule_tuples { 591 u8 src_mac[ETH_ALEN]; 592 u8 dst_mac[ETH_ALEN]; 593 /* Be compatible for ip address of both ipv4 and ipv6. 594 * For ipv4 address, we store it in src/dst_ip[3]. 595 */ 596 u32 src_ip[IPV6_SIZE]; 597 u32 dst_ip[IPV6_SIZE]; 598 u16 src_port; 599 u16 dst_port; 600 u16 vlan_tag1; 601 u16 ether_proto; 602 u8 ip_tos; 603 u8 ip_proto; 604 }; 605 606 struct hclge_fd_rule { 607 struct hlist_node rule_node; 608 struct hclge_fd_rule_tuples tuples; 609 struct hclge_fd_rule_tuples tuples_mask; 610 u32 unused_tuple; 611 u32 flow_type; 612 u8 action; 613 u16 vf_id; 614 u16 queue_id; 615 u16 location; 616 u16 flow_id; /* only used for arfs */ 617 enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type; 618 }; 619 620 struct hclge_fd_ad_data { 621 u16 ad_id; 622 u8 drop_packet; 623 u8 forward_to_direct_queue; 624 u16 queue_id; 625 u8 use_counter; 626 u8 counter_id; 627 u8 use_next_stage; 628 u8 write_rule_id_to_bd; 629 u8 next_input_key; 630 u16 rule_id; 631 }; 632 633 struct hclge_vport_mac_addr_cfg { 634 struct list_head node; 635 int hd_tbl_status; 636 u8 mac_addr[ETH_ALEN]; 637 }; 638 639 enum HCLGE_MAC_ADDR_TYPE { 640 HCLGE_MAC_ADDR_UC, 641 HCLGE_MAC_ADDR_MC 642 }; 643 644 struct hclge_vport_vlan_cfg { 645 struct list_head node; 646 int hd_tbl_status; 647 u16 vlan_id; 648 }; 649 650 struct hclge_rst_stats { 651 u32 reset_done_cnt; /* the number of reset has completed */ 652 u32 hw_reset_done_cnt; /* the number of HW reset has completed */ 653 u32 pf_rst_cnt; /* the number of PF reset */ 654 u32 flr_rst_cnt; /* the number of FLR */ 655 u32 global_rst_cnt; /* the number of GLOBAL */ 656 u32 imp_rst_cnt; /* the number of IMP reset */ 657 u32 reset_cnt; /* the number of reset */ 658 u32 reset_fail_cnt; /* the number of reset fail */ 659 }; 660 661 /* time and register status when mac tunnel interruption occur */ 662 struct hclge_mac_tnl_stats { 663 u64 time; 664 u32 status; 665 }; 666 667 #define HCLGE_RESET_INTERVAL (10 * HZ) 668 #define HCLGE_WAIT_RESET_DONE 100 669 670 #pragma pack(1) 671 struct hclge_vf_vlan_cfg { 672 u8 mbx_cmd; 673 u8 subcode; 674 u8 is_kill; 675 u16 vlan; 676 u16 proto; 677 }; 678 679 #pragma pack() 680 681 /* For each bit of TCAM entry, it uses a pair of 'x' and 682 * 'y' to indicate which value to match, like below: 683 * ---------------------------------- 684 * | bit x | bit y | search value | 685 * ---------------------------------- 686 * | 0 | 0 | always hit | 687 * ---------------------------------- 688 * | 1 | 0 | match '0' | 689 * ---------------------------------- 690 * | 0 | 1 | match '1' | 691 * ---------------------------------- 692 * | 1 | 1 | invalid | 693 * ---------------------------------- 694 * Then for input key(k) and mask(v), we can calculate the value by 695 * the formulae: 696 * x = (~k) & v 697 * y = (k ^ ~v) & k 698 */ 699 #define calc_x(x, k, v) ((x) = (~(k) & (v))) 700 #define calc_y(y, k, v) \ 701 do { \ 702 const typeof(k) _k_ = (k); \ 703 const typeof(v) _v_ = (v); \ 704 (y) = (_k_ ^ ~_v_) & (_k_); \ 705 } while (0) 706 707 #define HCLGE_MAC_TNL_LOG_SIZE 8 708 #define HCLGE_VPORT_NUM 256 709 struct hclge_dev { 710 struct pci_dev *pdev; 711 struct hnae3_ae_dev *ae_dev; 712 struct hclge_hw hw; 713 struct hclge_misc_vector misc_vector; 714 struct hclge_mac_stats mac_stats; 715 unsigned long state; 716 unsigned long flr_state; 717 unsigned long last_reset_time; 718 719 enum hnae3_reset_type reset_type; 720 enum hnae3_reset_type reset_level; 721 unsigned long default_reset_request; 722 unsigned long reset_request; /* reset has been requested */ 723 unsigned long reset_pending; /* client rst is pending to be served */ 724 struct hclge_rst_stats rst_stats; 725 struct semaphore reset_sem; /* protect reset process */ 726 u32 fw_version; 727 u16 num_vmdq_vport; /* Num vmdq vport this PF has set up */ 728 u16 num_tqps; /* Num task queue pairs of this PF */ 729 u16 num_req_vfs; /* Num VFs requested for this PF */ 730 731 u16 base_tqp_pid; /* Base task tqp physical id of this PF */ 732 u16 alloc_rss_size; /* Allocated RSS task queue */ 733 u16 rss_size_max; /* HW defined max RSS task queue */ 734 735 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */ 736 u16 num_alloc_vport; /* Num vports this driver supports */ 737 u32 numa_node_mask; 738 u16 rx_buf_len; 739 u16 num_tx_desc; /* desc num of per tx queue */ 740 u16 num_rx_desc; /* desc num of per rx queue */ 741 u8 hw_tc_map; 742 u8 tc_num_last_time; 743 enum hclge_fc_mode fc_mode_last_time; 744 u8 support_sfp_query; 745 746 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1 747 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2 748 u8 tx_sch_mode; 749 u8 tc_max; 750 u8 pfc_max; 751 752 u8 default_up; 753 u8 dcbx_cap; 754 struct hclge_tm_info tm_info; 755 756 u16 num_msi; 757 u16 num_msi_left; 758 u16 num_msi_used; 759 u16 roce_base_msix_offset; 760 u32 base_msi_vector; 761 u16 *vector_status; 762 int *vector_irq; 763 u16 num_nic_msi; /* Num of nic vectors for this PF */ 764 u16 num_roce_msi; /* Num of roce vectors for this PF */ 765 int roce_base_vector; 766 767 u16 pending_udp_bitmap; 768 769 u16 rx_itr_default; 770 u16 tx_itr_default; 771 772 u16 adminq_work_limit; /* Num of admin receive queue desc to process */ 773 unsigned long service_timer_period; 774 unsigned long service_timer_previous; 775 struct timer_list reset_timer; 776 struct delayed_work service_task; 777 778 bool cur_promisc; 779 int num_alloc_vfs; /* Actual number of VFs allocated */ 780 781 struct hclge_tqp *htqp; 782 struct hclge_vport *vport; 783 784 struct dentry *hclge_dbgfs; 785 786 struct hnae3_client *nic_client; 787 struct hnae3_client *roce_client; 788 789 #define HCLGE_FLAG_MAIN BIT(0) 790 #define HCLGE_FLAG_DCB_CAPABLE BIT(1) 791 #define HCLGE_FLAG_DCB_ENABLE BIT(2) 792 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3) 793 u32 flag; 794 795 u32 pkt_buf_size; /* Total pf buf size for tx/rx */ 796 u32 tx_buf_size; /* Tx buffer size for each TC */ 797 u32 dv_buf_size; /* Dv buffer size for each TC */ 798 799 u32 mps; /* Max packet size */ 800 /* vport_lock protect resource shared by vports */ 801 struct mutex vport_lock; 802 803 struct hclge_vlan_type_cfg vlan_type_cfg; 804 805 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 806 unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 807 808 struct hclge_fd_cfg fd_cfg; 809 struct hlist_head fd_rule_list; 810 spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */ 811 u16 hclge_fd_rule_num; 812 unsigned long serv_processed_cnt; 813 unsigned long last_serv_processed; 814 unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)]; 815 enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type; 816 u8 fd_en; 817 818 u16 wanted_umv_size; 819 /* max available unicast mac vlan space */ 820 u16 max_umv_size; 821 /* private unicast mac vlan space, it's same for PF and its VFs */ 822 u16 priv_umv_size; 823 /* unicast mac vlan space shared by PF and its VFs */ 824 u16 share_umv_size; 825 struct mutex umv_mutex; /* protect share_umv_size */ 826 827 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats, 828 HCLGE_MAC_TNL_LOG_SIZE); 829 830 /* affinity mask and notify for misc interrupt */ 831 cpumask_t affinity_mask; 832 struct irq_affinity_notify affinity_notify; 833 }; 834 835 /* VPort level vlan tag configuration for TX direction */ 836 struct hclge_tx_vtag_cfg { 837 bool accept_tag1; /* Whether accept tag1 packet from host */ 838 bool accept_untag1; /* Whether accept untag1 packet from host */ 839 bool accept_tag2; 840 bool accept_untag2; 841 bool insert_tag1_en; /* Whether insert inner vlan tag */ 842 bool insert_tag2_en; /* Whether insert outer vlan tag */ 843 u16 default_tag1; /* The default inner vlan tag to insert */ 844 u16 default_tag2; /* The default outer vlan tag to insert */ 845 }; 846 847 /* VPort level vlan tag configuration for RX direction */ 848 struct hclge_rx_vtag_cfg { 849 u8 rx_vlan_offload_en; /* Whether enable rx vlan offload */ 850 u8 strip_tag1_en; /* Whether strip inner vlan tag */ 851 u8 strip_tag2_en; /* Whether strip outer vlan tag */ 852 u8 vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */ 853 u8 vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */ 854 }; 855 856 struct hclge_rss_tuple_cfg { 857 u8 ipv4_tcp_en; 858 u8 ipv4_udp_en; 859 u8 ipv4_sctp_en; 860 u8 ipv4_fragment_en; 861 u8 ipv6_tcp_en; 862 u8 ipv6_udp_en; 863 u8 ipv6_sctp_en; 864 u8 ipv6_fragment_en; 865 }; 866 867 enum HCLGE_VPORT_STATE { 868 HCLGE_VPORT_STATE_ALIVE, 869 HCLGE_VPORT_STATE_MAX 870 }; 871 872 struct hclge_vlan_info { 873 u16 vlan_proto; /* so far support 802.1Q only */ 874 u16 qos; 875 u16 vlan_tag; 876 }; 877 878 struct hclge_port_base_vlan_config { 879 u16 state; 880 struct hclge_vlan_info vlan_info; 881 }; 882 883 struct hclge_vf_info { 884 int link_state; 885 u8 mac[ETH_ALEN]; 886 u32 spoofchk; 887 u32 max_tx_rate; 888 u32 trusted; 889 u16 promisc_enable; 890 }; 891 892 struct hclge_vport { 893 u16 alloc_tqps; /* Allocated Tx/Rx queues */ 894 895 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */ 896 /* User configured lookup table entries */ 897 u8 rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE]; 898 int rss_algo; /* User configured hash algorithm */ 899 /* User configured rss tuple sets */ 900 struct hclge_rss_tuple_cfg rss_tuple_sets; 901 902 u16 alloc_rss_size; 903 904 u16 qs_offset; 905 u32 bw_limit; /* VSI BW Limit (0 = disabled) */ 906 u8 dwrr; 907 908 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 909 struct hclge_port_base_vlan_config port_base_vlan_cfg; 910 struct hclge_tx_vtag_cfg txvlan_cfg; 911 struct hclge_rx_vtag_cfg rxvlan_cfg; 912 913 u16 used_umv_num; 914 915 u16 vport_id; 916 struct hclge_dev *back; /* Back reference to associated dev */ 917 struct hnae3_handle nic; 918 struct hnae3_handle roce; 919 920 unsigned long state; 921 unsigned long last_active_jiffies; 922 u32 mps; /* Max packet size */ 923 struct hclge_vf_info vf_info; 924 925 struct list_head uc_mac_list; /* Store VF unicast table */ 926 struct list_head mc_mac_list; /* Store VF multicast table */ 927 struct list_head vlan_list; /* Store VF vlan table */ 928 }; 929 930 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 931 bool en_mc_pmc, bool en_bc_pmc); 932 int hclge_add_uc_addr_common(struct hclge_vport *vport, 933 const unsigned char *addr); 934 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 935 const unsigned char *addr); 936 int hclge_add_mc_addr_common(struct hclge_vport *vport, 937 const unsigned char *addr); 938 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 939 const unsigned char *addr); 940 941 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle); 942 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 943 int vector_id, bool en, 944 struct hnae3_ring_chain_node *ring_chain); 945 946 static inline int hclge_get_queue_id(struct hnae3_queue *queue) 947 { 948 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q); 949 950 return tqp->index; 951 } 952 953 static inline bool hclge_is_reset_pending(struct hclge_dev *hdev) 954 { 955 return !!hdev->reset_pending; 956 } 957 958 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport); 959 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex); 960 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 961 u16 vlan_id, bool is_kill); 962 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable); 963 964 int hclge_buffer_alloc(struct hclge_dev *hdev); 965 int hclge_rss_init_hw(struct hclge_dev *hdev); 966 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev); 967 968 void hclge_mbx_handler(struct hclge_dev *hdev); 969 int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id); 970 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id); 971 int hclge_cfg_flowctrl(struct hclge_dev *hdev); 972 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id); 973 int hclge_vport_start(struct hclge_vport *vport); 974 void hclge_vport_stop(struct hclge_vport *vport); 975 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu); 976 int hclge_dbg_run_cmd(struct hnae3_handle *handle, const char *cmd_buf); 977 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id); 978 int hclge_notify_client(struct hclge_dev *hdev, 979 enum hnae3_reset_notify_type type); 980 void hclge_add_vport_mac_table(struct hclge_vport *vport, const u8 *mac_addr, 981 enum HCLGE_MAC_ADDR_TYPE mac_type); 982 void hclge_rm_vport_mac_table(struct hclge_vport *vport, const u8 *mac_addr, 983 bool is_write_tbl, 984 enum HCLGE_MAC_ADDR_TYPE mac_type); 985 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 986 enum HCLGE_MAC_ADDR_TYPE mac_type); 987 void hclge_uninit_vport_mac_table(struct hclge_dev *hdev); 988 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list); 989 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev); 990 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 991 struct hclge_vlan_info *vlan_info); 992 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid, 993 u16 state, u16 vlan_tag, u16 qos, 994 u16 vlan_proto); 995 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time); 996 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, 997 struct hclge_desc *desc); 998 void hclge_report_hw_error(struct hclge_dev *hdev, 999 enum hnae3_hw_error_type type); 1000 void hclge_inform_vf_promisc_info(struct hclge_vport *vport); 1001 void hclge_dbg_dump_rst_info(struct hclge_dev *hdev); 1002 #endif 1003