1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_MAIN_H 5 #define __HCLGE_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include <linux/phy.h> 9 #include <linux/if_vlan.h> 10 #include <linux/kfifo.h> 11 12 #include "hclge_cmd.h" 13 #include "hclge_ptp.h" 14 #include "hnae3.h" 15 16 #define HCLGE_MOD_VERSION "1.0" 17 #define HCLGE_DRIVER_NAME "hclge" 18 19 #define HCLGE_MAX_PF_NUM 8 20 21 #define HCLGE_VF_VPORT_START_NUM 1 22 23 #define HCLGE_RD_FIRST_STATS_NUM 2 24 #define HCLGE_RD_OTHER_STATS_NUM 4 25 26 #define HCLGE_INVALID_VPORT 0xffff 27 28 #define HCLGE_PF_CFG_BLOCK_SIZE 32 29 #define HCLGE_PF_CFG_DESC_NUM \ 30 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) 31 32 #define HCLGE_VECTOR_REG_BASE 0x20000 33 #define HCLGE_VECTOR_EXT_REG_BASE 0x30000 34 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400 35 36 #define HCLGE_VECTOR_REG_OFFSET 0x4 37 #define HCLGE_VECTOR_REG_OFFSET_H 0x1000 38 #define HCLGE_VECTOR_VF_OFFSET 0x100000 39 40 #define HCLGE_CMDQ_TX_ADDR_L_REG 0x27000 41 #define HCLGE_CMDQ_TX_ADDR_H_REG 0x27004 42 #define HCLGE_CMDQ_TX_DEPTH_REG 0x27008 43 #define HCLGE_CMDQ_TX_TAIL_REG 0x27010 44 #define HCLGE_CMDQ_TX_HEAD_REG 0x27014 45 #define HCLGE_CMDQ_RX_ADDR_L_REG 0x27018 46 #define HCLGE_CMDQ_RX_ADDR_H_REG 0x2701C 47 #define HCLGE_CMDQ_RX_DEPTH_REG 0x27020 48 #define HCLGE_CMDQ_RX_TAIL_REG 0x27024 49 #define HCLGE_CMDQ_RX_HEAD_REG 0x27028 50 #define HCLGE_CMDQ_INTR_STS_REG 0x27104 51 #define HCLGE_CMDQ_INTR_EN_REG 0x27108 52 #define HCLGE_CMDQ_INTR_GEN_REG 0x2710C 53 54 /* bar registers for common func */ 55 #define HCLGE_VECTOR0_OTER_EN_REG 0x20600 56 #define HCLGE_GRO_EN_REG 0x28000 57 #define HCLGE_RXD_ADV_LAYOUT_EN_REG 0x28008 58 59 /* bar registers for rcb */ 60 #define HCLGE_RING_RX_ADDR_L_REG 0x80000 61 #define HCLGE_RING_RX_ADDR_H_REG 0x80004 62 #define HCLGE_RING_RX_BD_NUM_REG 0x80008 63 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C 64 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014 65 #define HCLGE_RING_RX_TAIL_REG 0x80018 66 #define HCLGE_RING_RX_HEAD_REG 0x8001C 67 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020 68 #define HCLGE_RING_RX_OFFSET_REG 0x80024 69 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028 70 #define HCLGE_RING_RX_STASH_REG 0x80030 71 #define HCLGE_RING_RX_BD_ERR_REG 0x80034 72 #define HCLGE_RING_TX_ADDR_L_REG 0x80040 73 #define HCLGE_RING_TX_ADDR_H_REG 0x80044 74 #define HCLGE_RING_TX_BD_NUM_REG 0x80048 75 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C 76 #define HCLGE_RING_TX_TC_REG 0x80050 77 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054 78 #define HCLGE_RING_TX_TAIL_REG 0x80058 79 #define HCLGE_RING_TX_HEAD_REG 0x8005C 80 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060 81 #define HCLGE_RING_TX_OFFSET_REG 0x80064 82 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068 83 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070 84 #define HCLGE_RING_TX_BD_ERR_REG 0x80074 85 #define HCLGE_RING_EN_REG 0x80090 86 87 /* bar registers for tqp interrupt */ 88 #define HCLGE_TQP_INTR_CTRL_REG 0x20000 89 #define HCLGE_TQP_INTR_GL0_REG 0x20100 90 #define HCLGE_TQP_INTR_GL1_REG 0x20200 91 #define HCLGE_TQP_INTR_GL2_REG 0x20300 92 #define HCLGE_TQP_INTR_RL_REG 0x20900 93 94 #define HCLGE_RSS_IND_TBL_SIZE 512 95 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0) 96 #define HCLGE_RSS_KEY_SIZE 40 97 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0 98 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1 99 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2 100 #define HCLGE_RSS_HASH_ALGO_MASK GENMASK(3, 0) 101 102 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 103 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 104 #define HCLGE_D_PORT_BIT BIT(0) 105 #define HCLGE_S_PORT_BIT BIT(1) 106 #define HCLGE_D_IP_BIT BIT(2) 107 #define HCLGE_S_IP_BIT BIT(3) 108 #define HCLGE_V_TAG_BIT BIT(4) 109 #define HCLGE_RSS_INPUT_TUPLE_SCTP_NO_PORT \ 110 (HCLGE_D_IP_BIT | HCLGE_S_IP_BIT | HCLGE_V_TAG_BIT) 111 112 #define HCLGE_RSS_TC_SIZE_0 1 113 #define HCLGE_RSS_TC_SIZE_1 2 114 #define HCLGE_RSS_TC_SIZE_2 4 115 #define HCLGE_RSS_TC_SIZE_3 8 116 #define HCLGE_RSS_TC_SIZE_4 16 117 #define HCLGE_RSS_TC_SIZE_5 32 118 #define HCLGE_RSS_TC_SIZE_6 64 119 #define HCLGE_RSS_TC_SIZE_7 128 120 121 #define HCLGE_UMV_TBL_SIZE 3072 122 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \ 123 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM) 124 125 #define HCLGE_TQP_RESET_TRY_TIMES 200 126 127 #define HCLGE_PHY_PAGE_MDIX 0 128 #define HCLGE_PHY_PAGE_COPPER 0 129 130 /* Page Selection Reg. */ 131 #define HCLGE_PHY_PAGE_REG 22 132 133 /* Copper Specific Control Register */ 134 #define HCLGE_PHY_CSC_REG 16 135 136 /* Copper Specific Status Register */ 137 #define HCLGE_PHY_CSS_REG 17 138 139 #define HCLGE_PHY_MDIX_CTRL_S 5 140 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) 141 142 #define HCLGE_PHY_MDIX_STATUS_B 6 143 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11 144 145 #define HCLGE_GET_DFX_REG_TYPE_CNT 4 146 147 /* Factor used to calculate offset and bitmap of VF num */ 148 #define HCLGE_VF_NUM_PER_CMD 64 149 150 #define HCLGE_MAX_QSET_NUM 1024 151 152 #define HCLGE_DBG_RESET_INFO_LEN 1024 153 154 enum HLCGE_PORT_TYPE { 155 HOST_PORT, 156 NETWORK_PORT 157 }; 158 159 #define PF_VPORT_ID 0 160 161 #define HCLGE_PF_ID_S 0 162 #define HCLGE_PF_ID_M GENMASK(2, 0) 163 #define HCLGE_VF_ID_S 3 164 #define HCLGE_VF_ID_M GENMASK(10, 3) 165 #define HCLGE_PORT_TYPE_B 11 166 #define HCLGE_NETWORK_PORT_ID_S 0 167 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0) 168 169 /* Reset related Registers */ 170 #define HCLGE_PF_OTHER_INT_REG 0x20600 171 #define HCLGE_MISC_RESET_STS_REG 0x20700 172 #define HCLGE_MISC_VECTOR_INT_STS 0x20800 173 #define HCLGE_GLOBAL_RESET_REG 0x20A00 174 #define HCLGE_GLOBAL_RESET_BIT 0 175 #define HCLGE_CORE_RESET_BIT 1 176 #define HCLGE_IMP_RESET_BIT 2 177 #define HCLGE_RESET_INT_M GENMASK(7, 5) 178 #define HCLGE_FUN_RST_ING 0x20C00 179 #define HCLGE_FUN_RST_ING_B 0 180 181 /* Vector0 register bits define */ 182 #define HCLGE_VECTOR0_REG_PTP_INT_B 0 183 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5 184 #define HCLGE_VECTOR0_CORERESET_INT_B 6 185 #define HCLGE_VECTOR0_IMPRESET_INT_B 7 186 187 /* Vector0 interrupt CMDQ event source register(RW) */ 188 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100 189 /* CMDQ register bits for RX event(=MBX event) */ 190 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 191 192 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1 193 #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U 194 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U 195 #define HCLGE_VECTOR0_ALL_MSIX_ERR_B 6U 196 197 #define HCLGE_MAC_DEFAULT_FRAME \ 198 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN) 199 #define HCLGE_MAC_MIN_FRAME 64 200 #define HCLGE_MAC_MAX_FRAME 9728 201 202 #define HCLGE_SUPPORT_1G_BIT BIT(0) 203 #define HCLGE_SUPPORT_10G_BIT BIT(1) 204 #define HCLGE_SUPPORT_25G_BIT BIT(2) 205 #define HCLGE_SUPPORT_50G_BIT BIT(3) 206 #define HCLGE_SUPPORT_100G_BIT BIT(4) 207 /* to be compatible with exsit board */ 208 #define HCLGE_SUPPORT_40G_BIT BIT(5) 209 #define HCLGE_SUPPORT_100M_BIT BIT(6) 210 #define HCLGE_SUPPORT_10M_BIT BIT(7) 211 #define HCLGE_SUPPORT_200G_BIT BIT(8) 212 #define HCLGE_SUPPORT_GE \ 213 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT) 214 215 enum HCLGE_DEV_STATE { 216 HCLGE_STATE_REINITING, 217 HCLGE_STATE_DOWN, 218 HCLGE_STATE_DISABLED, 219 HCLGE_STATE_REMOVING, 220 HCLGE_STATE_NIC_REGISTERED, 221 HCLGE_STATE_ROCE_REGISTERED, 222 HCLGE_STATE_SERVICE_INITED, 223 HCLGE_STATE_RST_SERVICE_SCHED, 224 HCLGE_STATE_RST_HANDLING, 225 HCLGE_STATE_MBX_SERVICE_SCHED, 226 HCLGE_STATE_MBX_HANDLING, 227 HCLGE_STATE_ERR_SERVICE_SCHED, 228 HCLGE_STATE_STATISTICS_UPDATING, 229 HCLGE_STATE_CMD_DISABLE, 230 HCLGE_STATE_LINK_UPDATING, 231 HCLGE_STATE_RST_FAIL, 232 HCLGE_STATE_FD_TBL_CHANGED, 233 HCLGE_STATE_FD_CLEAR_ALL, 234 HCLGE_STATE_FD_USER_DEF_CHANGED, 235 HCLGE_STATE_PTP_EN, 236 HCLGE_STATE_PTP_TX_HANDLING, 237 HCLGE_STATE_MAX 238 }; 239 240 enum hclge_evt_cause { 241 HCLGE_VECTOR0_EVENT_RST, 242 HCLGE_VECTOR0_EVENT_MBX, 243 HCLGE_VECTOR0_EVENT_ERR, 244 HCLGE_VECTOR0_EVENT_PTP, 245 HCLGE_VECTOR0_EVENT_OTHER, 246 }; 247 248 enum HCLGE_MAC_SPEED { 249 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */ 250 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */ 251 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */ 252 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ 253 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ 254 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ 255 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ 256 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ 257 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */ 258 HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */ 259 }; 260 261 enum HCLGE_MAC_DUPLEX { 262 HCLGE_MAC_HALF, 263 HCLGE_MAC_FULL 264 }; 265 266 #define QUERY_SFP_SPEED 0 267 #define QUERY_ACTIVE_SPEED 1 268 269 struct hclge_mac { 270 u8 mac_id; 271 u8 phy_addr; 272 u8 flag; 273 u8 media_type; /* port media type, e.g. fibre/copper/backplane */ 274 u8 mac_addr[ETH_ALEN]; 275 u8 autoneg; 276 u8 duplex; 277 u8 support_autoneg; 278 u8 speed_type; /* 0: sfp speed, 1: active speed */ 279 u32 speed; 280 u32 max_speed; 281 u32 speed_ability; /* speed ability supported by current media */ 282 u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */ 283 u32 fec_mode; /* active fec mode */ 284 u32 user_fec_mode; 285 u32 fec_ability; 286 int link; /* store the link status of mac & phy (if phy exists) */ 287 struct phy_device *phydev; 288 struct mii_bus *mdio_bus; 289 phy_interface_t phy_if; 290 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 291 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 292 }; 293 294 struct hclge_hw { 295 void __iomem *io_base; 296 void __iomem *mem_base; 297 struct hclge_mac mac; 298 int num_vec; 299 struct hclge_cmq cmq; 300 }; 301 302 /* TQP stats */ 303 struct hlcge_tqp_stats { 304 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 305 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 306 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 307 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 308 }; 309 310 struct hclge_tqp { 311 /* copy of device pointer from pci_dev, 312 * used when perform DMA mapping 313 */ 314 struct device *dev; 315 struct hnae3_queue q; 316 struct hlcge_tqp_stats tqp_stats; 317 u16 index; /* Global index in a NIC controller */ 318 319 bool alloced; 320 }; 321 322 enum hclge_fc_mode { 323 HCLGE_FC_NONE, 324 HCLGE_FC_RX_PAUSE, 325 HCLGE_FC_TX_PAUSE, 326 HCLGE_FC_FULL, 327 HCLGE_FC_PFC, 328 HCLGE_FC_DEFAULT 329 }; 330 331 #define HCLGE_FILTER_TYPE_VF 0 332 #define HCLGE_FILTER_TYPE_PORT 1 333 #define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0) 334 #define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0) 335 #define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1) 336 #define HCLGE_FILTER_FE_ROCE_INGRESS_B BIT(2) 337 #define HCLGE_FILTER_FE_ROCE_EGRESS_B BIT(3) 338 #define HCLGE_FILTER_FE_EGRESS (HCLGE_FILTER_FE_NIC_EGRESS_B \ 339 | HCLGE_FILTER_FE_ROCE_EGRESS_B) 340 #define HCLGE_FILTER_FE_INGRESS (HCLGE_FILTER_FE_NIC_INGRESS_B \ 341 | HCLGE_FILTER_FE_ROCE_INGRESS_B) 342 343 enum hclge_vlan_fltr_cap { 344 HCLGE_VLAN_FLTR_DEF, 345 HCLGE_VLAN_FLTR_CAN_MDF, 346 }; 347 enum hclge_link_fail_code { 348 HCLGE_LF_NORMAL, 349 HCLGE_LF_REF_CLOCK_LOST, 350 HCLGE_LF_XSFP_TX_DISABLE, 351 HCLGE_LF_XSFP_ABSENT, 352 }; 353 354 #define HCLGE_LINK_STATUS_DOWN 0 355 #define HCLGE_LINK_STATUS_UP 1 356 357 #define HCLGE_PG_NUM 4 358 #define HCLGE_SCH_MODE_SP 0 359 #define HCLGE_SCH_MODE_DWRR 1 360 struct hclge_pg_info { 361 u8 pg_id; 362 u8 pg_sch_mode; /* 0: sp; 1: dwrr */ 363 u8 tc_bit_map; 364 u32 bw_limit; 365 u8 tc_dwrr[HNAE3_MAX_TC]; 366 }; 367 368 struct hclge_tc_info { 369 u8 tc_id; 370 u8 tc_sch_mode; /* 0: sp; 1: dwrr */ 371 u8 pgid; 372 u32 bw_limit; 373 }; 374 375 struct hclge_cfg { 376 u8 tc_num; 377 u8 vlan_fliter_cap; 378 u16 tqp_desc_num; 379 u16 rx_buf_len; 380 u16 vf_rss_size_max; 381 u16 pf_rss_size_max; 382 u8 phy_addr; 383 u8 media_type; 384 u8 mac_addr[ETH_ALEN]; 385 u8 default_speed; 386 u32 numa_node_map; 387 u32 tx_spare_buf_size; 388 u16 speed_ability; 389 u16 umv_space; 390 }; 391 392 struct hclge_tm_info { 393 u8 num_tc; 394 u8 num_pg; /* It must be 1 if vNET-Base schd */ 395 u8 pg_dwrr[HCLGE_PG_NUM]; 396 u8 prio_tc[HNAE3_MAX_USER_PRIO]; 397 struct hclge_pg_info pg_info[HCLGE_PG_NUM]; 398 struct hclge_tc_info tc_info[HNAE3_MAX_TC]; 399 enum hclge_fc_mode fc_mode; 400 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */ 401 u8 pfc_en; /* PFC enabled or not for user priority */ 402 }; 403 404 struct hclge_comm_stats_str { 405 char desc[ETH_GSTRING_LEN]; 406 unsigned long offset; 407 }; 408 409 /* mac stats ,opcode id: 0x0032 */ 410 struct hclge_mac_stats { 411 u64 mac_tx_mac_pause_num; 412 u64 mac_rx_mac_pause_num; 413 u64 mac_tx_pfc_pri0_pkt_num; 414 u64 mac_tx_pfc_pri1_pkt_num; 415 u64 mac_tx_pfc_pri2_pkt_num; 416 u64 mac_tx_pfc_pri3_pkt_num; 417 u64 mac_tx_pfc_pri4_pkt_num; 418 u64 mac_tx_pfc_pri5_pkt_num; 419 u64 mac_tx_pfc_pri6_pkt_num; 420 u64 mac_tx_pfc_pri7_pkt_num; 421 u64 mac_rx_pfc_pri0_pkt_num; 422 u64 mac_rx_pfc_pri1_pkt_num; 423 u64 mac_rx_pfc_pri2_pkt_num; 424 u64 mac_rx_pfc_pri3_pkt_num; 425 u64 mac_rx_pfc_pri4_pkt_num; 426 u64 mac_rx_pfc_pri5_pkt_num; 427 u64 mac_rx_pfc_pri6_pkt_num; 428 u64 mac_rx_pfc_pri7_pkt_num; 429 u64 mac_tx_total_pkt_num; 430 u64 mac_tx_total_oct_num; 431 u64 mac_tx_good_pkt_num; 432 u64 mac_tx_bad_pkt_num; 433 u64 mac_tx_good_oct_num; 434 u64 mac_tx_bad_oct_num; 435 u64 mac_tx_uni_pkt_num; 436 u64 mac_tx_multi_pkt_num; 437 u64 mac_tx_broad_pkt_num; 438 u64 mac_tx_undersize_pkt_num; 439 u64 mac_tx_oversize_pkt_num; 440 u64 mac_tx_64_oct_pkt_num; 441 u64 mac_tx_65_127_oct_pkt_num; 442 u64 mac_tx_128_255_oct_pkt_num; 443 u64 mac_tx_256_511_oct_pkt_num; 444 u64 mac_tx_512_1023_oct_pkt_num; 445 u64 mac_tx_1024_1518_oct_pkt_num; 446 u64 mac_tx_1519_2047_oct_pkt_num; 447 u64 mac_tx_2048_4095_oct_pkt_num; 448 u64 mac_tx_4096_8191_oct_pkt_num; 449 u64 rsv0; 450 u64 mac_tx_8192_9216_oct_pkt_num; 451 u64 mac_tx_9217_12287_oct_pkt_num; 452 u64 mac_tx_12288_16383_oct_pkt_num; 453 u64 mac_tx_1519_max_good_oct_pkt_num; 454 u64 mac_tx_1519_max_bad_oct_pkt_num; 455 456 u64 mac_rx_total_pkt_num; 457 u64 mac_rx_total_oct_num; 458 u64 mac_rx_good_pkt_num; 459 u64 mac_rx_bad_pkt_num; 460 u64 mac_rx_good_oct_num; 461 u64 mac_rx_bad_oct_num; 462 u64 mac_rx_uni_pkt_num; 463 u64 mac_rx_multi_pkt_num; 464 u64 mac_rx_broad_pkt_num; 465 u64 mac_rx_undersize_pkt_num; 466 u64 mac_rx_oversize_pkt_num; 467 u64 mac_rx_64_oct_pkt_num; 468 u64 mac_rx_65_127_oct_pkt_num; 469 u64 mac_rx_128_255_oct_pkt_num; 470 u64 mac_rx_256_511_oct_pkt_num; 471 u64 mac_rx_512_1023_oct_pkt_num; 472 u64 mac_rx_1024_1518_oct_pkt_num; 473 u64 mac_rx_1519_2047_oct_pkt_num; 474 u64 mac_rx_2048_4095_oct_pkt_num; 475 u64 mac_rx_4096_8191_oct_pkt_num; 476 u64 rsv1; 477 u64 mac_rx_8192_9216_oct_pkt_num; 478 u64 mac_rx_9217_12287_oct_pkt_num; 479 u64 mac_rx_12288_16383_oct_pkt_num; 480 u64 mac_rx_1519_max_good_oct_pkt_num; 481 u64 mac_rx_1519_max_bad_oct_pkt_num; 482 483 u64 mac_tx_fragment_pkt_num; 484 u64 mac_tx_undermin_pkt_num; 485 u64 mac_tx_jabber_pkt_num; 486 u64 mac_tx_err_all_pkt_num; 487 u64 mac_tx_from_app_good_pkt_num; 488 u64 mac_tx_from_app_bad_pkt_num; 489 u64 mac_rx_fragment_pkt_num; 490 u64 mac_rx_undermin_pkt_num; 491 u64 mac_rx_jabber_pkt_num; 492 u64 mac_rx_fcs_err_pkt_num; 493 u64 mac_rx_send_app_good_pkt_num; 494 u64 mac_rx_send_app_bad_pkt_num; 495 u64 mac_tx_pfc_pause_pkt_num; 496 u64 mac_rx_pfc_pause_pkt_num; 497 u64 mac_tx_ctrl_pkt_num; 498 u64 mac_rx_ctrl_pkt_num; 499 }; 500 501 #define HCLGE_STATS_TIMER_INTERVAL 300UL 502 503 struct hclge_vlan_type_cfg { 504 u16 rx_ot_fst_vlan_type; 505 u16 rx_ot_sec_vlan_type; 506 u16 rx_in_fst_vlan_type; 507 u16 rx_in_sec_vlan_type; 508 u16 tx_ot_vlan_type; 509 u16 tx_in_vlan_type; 510 }; 511 512 enum HCLGE_FD_MODE { 513 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1, 514 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2, 515 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1, 516 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2, 517 }; 518 519 enum HCLGE_FD_KEY_TYPE { 520 HCLGE_FD_KEY_BASE_ON_PTYPE, 521 HCLGE_FD_KEY_BASE_ON_TUPLE, 522 }; 523 524 enum HCLGE_FD_STAGE { 525 HCLGE_FD_STAGE_1, 526 HCLGE_FD_STAGE_2, 527 MAX_STAGE_NUM, 528 }; 529 530 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet 531 * INNER_XXX indicate tuples in tunneled header of tunnel packet or 532 * tuples of non-tunnel packet 533 */ 534 enum HCLGE_FD_TUPLE { 535 OUTER_DST_MAC, 536 OUTER_SRC_MAC, 537 OUTER_VLAN_TAG_FST, 538 OUTER_VLAN_TAG_SEC, 539 OUTER_ETH_TYPE, 540 OUTER_L2_RSV, 541 OUTER_IP_TOS, 542 OUTER_IP_PROTO, 543 OUTER_SRC_IP, 544 OUTER_DST_IP, 545 OUTER_L3_RSV, 546 OUTER_SRC_PORT, 547 OUTER_DST_PORT, 548 OUTER_L4_RSV, 549 OUTER_TUN_VNI, 550 OUTER_TUN_FLOW_ID, 551 INNER_DST_MAC, 552 INNER_SRC_MAC, 553 INNER_VLAN_TAG_FST, 554 INNER_VLAN_TAG_SEC, 555 INNER_ETH_TYPE, 556 INNER_L2_RSV, 557 INNER_IP_TOS, 558 INNER_IP_PROTO, 559 INNER_SRC_IP, 560 INNER_DST_IP, 561 INNER_L3_RSV, 562 INNER_SRC_PORT, 563 INNER_DST_PORT, 564 INNER_L4_RSV, 565 MAX_TUPLE, 566 }; 567 568 #define HCLGE_FD_TUPLE_USER_DEF_TUPLES \ 569 (BIT(INNER_L2_RSV) | BIT(INNER_L3_RSV) | BIT(INNER_L4_RSV)) 570 571 enum HCLGE_FD_META_DATA { 572 PACKET_TYPE_ID, 573 IP_FRAGEMENT, 574 ROCE_TYPE, 575 NEXT_KEY, 576 VLAN_NUMBER, 577 SRC_VPORT, 578 DST_VPORT, 579 TUNNEL_PACKET, 580 MAX_META_DATA, 581 }; 582 583 enum HCLGE_FD_KEY_OPT { 584 KEY_OPT_U8, 585 KEY_OPT_LE16, 586 KEY_OPT_LE32, 587 KEY_OPT_MAC, 588 KEY_OPT_IP, 589 KEY_OPT_VNI, 590 }; 591 592 struct key_info { 593 u8 key_type; 594 u8 key_length; /* use bit as unit */ 595 enum HCLGE_FD_KEY_OPT key_opt; 596 int offset; 597 int moffset; 598 }; 599 600 #define MAX_KEY_LENGTH 400 601 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4) 602 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4) 603 #define MAX_META_DATA_LENGTH 32 604 605 #define HCLGE_FD_MAX_USER_DEF_OFFSET 9000 606 #define HCLGE_FD_USER_DEF_DATA GENMASK(15, 0) 607 #define HCLGE_FD_USER_DEF_OFFSET GENMASK(15, 0) 608 #define HCLGE_FD_USER_DEF_OFFSET_UNMASK GENMASK(15, 0) 609 610 /* assigned by firmware, the real filter number for each pf may be less */ 611 #define MAX_FD_FILTER_NUM 4096 612 #define HCLGE_ARFS_EXPIRE_INTERVAL 5UL 613 614 enum HCLGE_FD_ACTIVE_RULE_TYPE { 615 HCLGE_FD_RULE_NONE, 616 HCLGE_FD_ARFS_ACTIVE, 617 HCLGE_FD_EP_ACTIVE, 618 HCLGE_FD_TC_FLOWER_ACTIVE, 619 }; 620 621 enum HCLGE_FD_PACKET_TYPE { 622 NIC_PACKET, 623 ROCE_PACKET, 624 }; 625 626 enum HCLGE_FD_ACTION { 627 HCLGE_FD_ACTION_SELECT_QUEUE, 628 HCLGE_FD_ACTION_DROP_PACKET, 629 HCLGE_FD_ACTION_SELECT_TC, 630 }; 631 632 enum HCLGE_FD_NODE_STATE { 633 HCLGE_FD_TO_ADD, 634 HCLGE_FD_TO_DEL, 635 HCLGE_FD_ACTIVE, 636 HCLGE_FD_DELETED, 637 }; 638 639 enum HCLGE_FD_USER_DEF_LAYER { 640 HCLGE_FD_USER_DEF_NONE, 641 HCLGE_FD_USER_DEF_L2, 642 HCLGE_FD_USER_DEF_L3, 643 HCLGE_FD_USER_DEF_L4, 644 }; 645 646 #define HCLGE_FD_USER_DEF_LAYER_NUM 3 647 struct hclge_fd_user_def_cfg { 648 u16 ref_cnt; 649 u16 offset; 650 }; 651 652 struct hclge_fd_user_def_info { 653 enum HCLGE_FD_USER_DEF_LAYER layer; 654 u16 data; 655 u16 data_mask; 656 u16 offset; 657 }; 658 659 struct hclge_fd_key_cfg { 660 u8 key_sel; 661 u8 inner_sipv6_word_en; 662 u8 inner_dipv6_word_en; 663 u8 outer_sipv6_word_en; 664 u8 outer_dipv6_word_en; 665 u32 tuple_active; 666 u32 meta_data_active; 667 }; 668 669 struct hclge_fd_cfg { 670 u8 fd_mode; 671 u16 max_key_length; /* use bit as unit */ 672 u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */ 673 u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */ 674 struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM]; 675 struct hclge_fd_user_def_cfg user_def_cfg[HCLGE_FD_USER_DEF_LAYER_NUM]; 676 }; 677 678 #define IPV4_INDEX 3 679 #define IPV6_SIZE 4 680 struct hclge_fd_rule_tuples { 681 u8 src_mac[ETH_ALEN]; 682 u8 dst_mac[ETH_ALEN]; 683 /* Be compatible for ip address of both ipv4 and ipv6. 684 * For ipv4 address, we store it in src/dst_ip[3]. 685 */ 686 u32 src_ip[IPV6_SIZE]; 687 u32 dst_ip[IPV6_SIZE]; 688 u16 src_port; 689 u16 dst_port; 690 u16 vlan_tag1; 691 u16 ether_proto; 692 u16 l2_user_def; 693 u16 l3_user_def; 694 u32 l4_user_def; 695 u8 ip_tos; 696 u8 ip_proto; 697 }; 698 699 struct hclge_fd_rule { 700 struct hlist_node rule_node; 701 struct hclge_fd_rule_tuples tuples; 702 struct hclge_fd_rule_tuples tuples_mask; 703 u32 unused_tuple; 704 u32 flow_type; 705 union { 706 struct { 707 unsigned long cookie; 708 u8 tc; 709 } cls_flower; 710 struct { 711 u16 flow_id; /* only used for arfs */ 712 } arfs; 713 struct { 714 struct hclge_fd_user_def_info user_def; 715 } ep; 716 }; 717 u16 queue_id; 718 u16 vf_id; 719 u16 location; 720 enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type; 721 enum HCLGE_FD_NODE_STATE state; 722 u8 action; 723 }; 724 725 struct hclge_fd_ad_data { 726 u16 ad_id; 727 u8 drop_packet; 728 u8 forward_to_direct_queue; 729 u16 queue_id; 730 u8 use_counter; 731 u8 counter_id; 732 u8 use_next_stage; 733 u8 write_rule_id_to_bd; 734 u8 next_input_key; 735 u16 rule_id; 736 u16 tc_size; 737 u8 override_tc; 738 }; 739 740 enum HCLGE_MAC_NODE_STATE { 741 HCLGE_MAC_TO_ADD, 742 HCLGE_MAC_TO_DEL, 743 HCLGE_MAC_ACTIVE 744 }; 745 746 struct hclge_mac_node { 747 struct list_head node; 748 enum HCLGE_MAC_NODE_STATE state; 749 u8 mac_addr[ETH_ALEN]; 750 }; 751 752 enum HCLGE_MAC_ADDR_TYPE { 753 HCLGE_MAC_ADDR_UC, 754 HCLGE_MAC_ADDR_MC 755 }; 756 757 struct hclge_vport_vlan_cfg { 758 struct list_head node; 759 int hd_tbl_status; 760 u16 vlan_id; 761 }; 762 763 struct hclge_rst_stats { 764 u32 reset_done_cnt; /* the number of reset has completed */ 765 u32 hw_reset_done_cnt; /* the number of HW reset has completed */ 766 u32 pf_rst_cnt; /* the number of PF reset */ 767 u32 flr_rst_cnt; /* the number of FLR */ 768 u32 global_rst_cnt; /* the number of GLOBAL */ 769 u32 imp_rst_cnt; /* the number of IMP reset */ 770 u32 reset_cnt; /* the number of reset */ 771 u32 reset_fail_cnt; /* the number of reset fail */ 772 }; 773 774 /* time and register status when mac tunnel interruption occur */ 775 struct hclge_mac_tnl_stats { 776 u64 time; 777 u32 status; 778 }; 779 780 #define HCLGE_RESET_INTERVAL (10 * HZ) 781 #define HCLGE_WAIT_RESET_DONE 100 782 783 #pragma pack(1) 784 struct hclge_vf_vlan_cfg { 785 u8 mbx_cmd; 786 u8 subcode; 787 union { 788 struct { 789 u8 is_kill; 790 u16 vlan; 791 u16 proto; 792 }; 793 u8 enable; 794 }; 795 }; 796 797 #pragma pack() 798 799 /* For each bit of TCAM entry, it uses a pair of 'x' and 800 * 'y' to indicate which value to match, like below: 801 * ---------------------------------- 802 * | bit x | bit y | search value | 803 * ---------------------------------- 804 * | 0 | 0 | always hit | 805 * ---------------------------------- 806 * | 1 | 0 | match '0' | 807 * ---------------------------------- 808 * | 0 | 1 | match '1' | 809 * ---------------------------------- 810 * | 1 | 1 | invalid | 811 * ---------------------------------- 812 * Then for input key(k) and mask(v), we can calculate the value by 813 * the formulae: 814 * x = (~k) & v 815 * y = (k ^ ~v) & k 816 */ 817 #define calc_x(x, k, v) (x = ~(k) & (v)) 818 #define calc_y(y, k, v) \ 819 do { \ 820 const typeof(k) _k_ = (k); \ 821 const typeof(v) _v_ = (v); \ 822 (y) = (_k_ ^ ~_v_) & (_k_); \ 823 } while (0) 824 825 #define HCLGE_MAC_TNL_LOG_SIZE 8 826 #define HCLGE_VPORT_NUM 256 827 struct hclge_dev { 828 struct pci_dev *pdev; 829 struct hnae3_ae_dev *ae_dev; 830 struct hclge_hw hw; 831 struct hclge_misc_vector misc_vector; 832 struct hclge_mac_stats mac_stats; 833 unsigned long state; 834 unsigned long flr_state; 835 unsigned long last_reset_time; 836 837 enum hnae3_reset_type reset_type; 838 enum hnae3_reset_type reset_level; 839 unsigned long default_reset_request; 840 unsigned long reset_request; /* reset has been requested */ 841 unsigned long reset_pending; /* client rst is pending to be served */ 842 struct hclge_rst_stats rst_stats; 843 struct semaphore reset_sem; /* protect reset process */ 844 u32 fw_version; 845 u16 num_tqps; /* Num task queue pairs of this PF */ 846 u16 num_req_vfs; /* Num VFs requested for this PF */ 847 848 u16 base_tqp_pid; /* Base task tqp physical id of this PF */ 849 u16 alloc_rss_size; /* Allocated RSS task queue */ 850 u16 vf_rss_size_max; /* HW defined VF max RSS task queue */ 851 u16 pf_rss_size_max; /* HW defined PF max RSS task queue */ 852 u32 tx_spare_buf_size; /* HW defined TX spare buffer size */ 853 854 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */ 855 u16 num_alloc_vport; /* Num vports this driver supports */ 856 u32 numa_node_mask; 857 u16 rx_buf_len; 858 u16 num_tx_desc; /* desc num of per tx queue */ 859 u16 num_rx_desc; /* desc num of per rx queue */ 860 u8 hw_tc_map; 861 enum hclge_fc_mode fc_mode_last_time; 862 u8 support_sfp_query; 863 864 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1 865 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2 866 u8 tx_sch_mode; 867 u8 tc_max; 868 u8 pfc_max; 869 870 u8 default_up; 871 u8 dcbx_cap; 872 struct hclge_tm_info tm_info; 873 874 u16 num_msi; 875 u16 num_msi_left; 876 u16 num_msi_used; 877 u32 base_msi_vector; 878 u16 *vector_status; 879 int *vector_irq; 880 u16 num_nic_msi; /* Num of nic vectors for this PF */ 881 u16 num_roce_msi; /* Num of roce vectors for this PF */ 882 int roce_base_vector; 883 884 unsigned long service_timer_period; 885 unsigned long service_timer_previous; 886 struct timer_list reset_timer; 887 struct delayed_work service_task; 888 889 bool cur_promisc; 890 int num_alloc_vfs; /* Actual number of VFs allocated */ 891 892 struct hclge_tqp *htqp; 893 struct hclge_vport *vport; 894 895 struct dentry *hclge_dbgfs; 896 897 struct hnae3_client *nic_client; 898 struct hnae3_client *roce_client; 899 900 #define HCLGE_FLAG_MAIN BIT(0) 901 #define HCLGE_FLAG_DCB_CAPABLE BIT(1) 902 #define HCLGE_FLAG_DCB_ENABLE BIT(2) 903 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3) 904 u32 flag; 905 906 u32 pkt_buf_size; /* Total pf buf size for tx/rx */ 907 u32 tx_buf_size; /* Tx buffer size for each TC */ 908 u32 dv_buf_size; /* Dv buffer size for each TC */ 909 910 u32 mps; /* Max packet size */ 911 /* vport_lock protect resource shared by vports */ 912 struct mutex vport_lock; 913 914 struct hclge_vlan_type_cfg vlan_type_cfg; 915 916 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 917 unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 918 919 unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 920 921 struct hclge_fd_cfg fd_cfg; 922 struct hlist_head fd_rule_list; 923 spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */ 924 u16 hclge_fd_rule_num; 925 unsigned long serv_processed_cnt; 926 unsigned long last_serv_processed; 927 unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)]; 928 enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type; 929 u8 fd_en; 930 931 u16 wanted_umv_size; 932 /* max available unicast mac vlan space */ 933 u16 max_umv_size; 934 /* private unicast mac vlan space, it's same for PF and its VFs */ 935 u16 priv_umv_size; 936 /* unicast mac vlan space shared by PF and its VFs */ 937 u16 share_umv_size; 938 939 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats, 940 HCLGE_MAC_TNL_LOG_SIZE); 941 942 /* affinity mask and notify for misc interrupt */ 943 cpumask_t affinity_mask; 944 struct irq_affinity_notify affinity_notify; 945 struct hclge_ptp *ptp; 946 }; 947 948 /* VPort level vlan tag configuration for TX direction */ 949 struct hclge_tx_vtag_cfg { 950 bool accept_tag1; /* Whether accept tag1 packet from host */ 951 bool accept_untag1; /* Whether accept untag1 packet from host */ 952 bool accept_tag2; 953 bool accept_untag2; 954 bool insert_tag1_en; /* Whether insert inner vlan tag */ 955 bool insert_tag2_en; /* Whether insert outer vlan tag */ 956 u16 default_tag1; /* The default inner vlan tag to insert */ 957 u16 default_tag2; /* The default outer vlan tag to insert */ 958 bool tag_shift_mode_en; 959 }; 960 961 /* VPort level vlan tag configuration for RX direction */ 962 struct hclge_rx_vtag_cfg { 963 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ 964 bool strip_tag1_en; /* Whether strip inner vlan tag */ 965 bool strip_tag2_en; /* Whether strip outer vlan tag */ 966 bool vlan1_vlan_prionly; /* Inner vlan tag up to descriptor enable */ 967 bool vlan2_vlan_prionly; /* Outer vlan tag up to descriptor enable */ 968 bool strip_tag1_discard_en; /* Inner vlan tag discard for BD enable */ 969 bool strip_tag2_discard_en; /* Outer vlan tag discard for BD enable */ 970 }; 971 972 struct hclge_rss_tuple_cfg { 973 u8 ipv4_tcp_en; 974 u8 ipv4_udp_en; 975 u8 ipv4_sctp_en; 976 u8 ipv4_fragment_en; 977 u8 ipv6_tcp_en; 978 u8 ipv6_udp_en; 979 u8 ipv6_sctp_en; 980 u8 ipv6_fragment_en; 981 }; 982 983 enum HCLGE_VPORT_STATE { 984 HCLGE_VPORT_STATE_ALIVE, 985 HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 986 HCLGE_VPORT_STATE_PROMISC_CHANGE, 987 HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 988 HCLGE_VPORT_STATE_MAX 989 }; 990 991 struct hclge_vlan_info { 992 u16 vlan_proto; /* so far support 802.1Q only */ 993 u16 qos; 994 u16 vlan_tag; 995 }; 996 997 struct hclge_port_base_vlan_config { 998 u16 state; 999 struct hclge_vlan_info vlan_info; 1000 }; 1001 1002 struct hclge_vf_info { 1003 int link_state; 1004 u8 mac[ETH_ALEN]; 1005 u32 spoofchk; 1006 u32 max_tx_rate; 1007 u32 trusted; 1008 u8 request_uc_en; 1009 u8 request_mc_en; 1010 u8 request_bc_en; 1011 }; 1012 1013 struct hclge_vport { 1014 u16 alloc_tqps; /* Allocated Tx/Rx queues */ 1015 1016 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */ 1017 /* User configured lookup table entries */ 1018 u16 *rss_indirection_tbl; 1019 int rss_algo; /* User configured hash algorithm */ 1020 /* User configured rss tuple sets */ 1021 struct hclge_rss_tuple_cfg rss_tuple_sets; 1022 1023 u16 alloc_rss_size; 1024 1025 u16 qs_offset; 1026 u32 bw_limit; /* VSI BW Limit (0 = disabled) */ 1027 u8 dwrr; 1028 1029 bool req_vlan_fltr_en; 1030 bool cur_vlan_fltr_en; 1031 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 1032 struct hclge_port_base_vlan_config port_base_vlan_cfg; 1033 struct hclge_tx_vtag_cfg txvlan_cfg; 1034 struct hclge_rx_vtag_cfg rxvlan_cfg; 1035 1036 u16 used_umv_num; 1037 1038 u16 vport_id; 1039 struct hclge_dev *back; /* Back reference to associated dev */ 1040 struct hnae3_handle nic; 1041 struct hnae3_handle roce; 1042 1043 unsigned long state; 1044 unsigned long last_active_jiffies; 1045 u32 mps; /* Max packet size */ 1046 struct hclge_vf_info vf_info; 1047 1048 u8 overflow_promisc_flags; 1049 u8 last_promisc_flags; 1050 1051 spinlock_t mac_list_lock; /* protect mac address need to add/detele */ 1052 struct list_head uc_mac_list; /* Store VF unicast table */ 1053 struct list_head mc_mac_list; /* Store VF multicast table */ 1054 struct list_head vlan_list; /* Store VF vlan table */ 1055 }; 1056 1057 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 1058 bool en_mc_pmc, bool en_bc_pmc); 1059 int hclge_add_uc_addr_common(struct hclge_vport *vport, 1060 const unsigned char *addr); 1061 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 1062 const unsigned char *addr); 1063 int hclge_add_mc_addr_common(struct hclge_vport *vport, 1064 const unsigned char *addr); 1065 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 1066 const unsigned char *addr); 1067 1068 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle); 1069 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 1070 int vector_id, bool en, 1071 struct hnae3_ring_chain_node *ring_chain); 1072 1073 static inline int hclge_get_queue_id(struct hnae3_queue *queue) 1074 { 1075 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q); 1076 1077 return tqp->index; 1078 } 1079 1080 static inline bool hclge_is_reset_pending(struct hclge_dev *hdev) 1081 { 1082 return !!hdev->reset_pending; 1083 } 1084 1085 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport); 1086 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex); 1087 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 1088 u16 vlan_id, bool is_kill); 1089 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable); 1090 1091 int hclge_buffer_alloc(struct hclge_dev *hdev); 1092 int hclge_rss_init_hw(struct hclge_dev *hdev); 1093 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev); 1094 1095 void hclge_mbx_handler(struct hclge_dev *hdev); 1096 int hclge_reset_tqp(struct hnae3_handle *handle); 1097 int hclge_cfg_flowctrl(struct hclge_dev *hdev); 1098 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id); 1099 int hclge_vport_start(struct hclge_vport *vport); 1100 void hclge_vport_stop(struct hclge_vport *vport); 1101 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu); 1102 int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, 1103 char *buf, int len); 1104 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id); 1105 int hclge_notify_client(struct hclge_dev *hdev, 1106 enum hnae3_reset_notify_type type); 1107 int hclge_update_mac_list(struct hclge_vport *vport, 1108 enum HCLGE_MAC_NODE_STATE state, 1109 enum HCLGE_MAC_ADDR_TYPE mac_type, 1110 const unsigned char *addr); 1111 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 1112 const u8 *old_addr, const u8 *new_addr); 1113 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 1114 enum HCLGE_MAC_ADDR_TYPE mac_type); 1115 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list); 1116 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev); 1117 void hclge_restore_mac_table_common(struct hclge_vport *vport); 1118 void hclge_restore_vport_vlan_table(struct hclge_vport *vport); 1119 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 1120 struct hclge_vlan_info *vlan_info); 1121 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid, 1122 u16 state, 1123 struct hclge_vlan_info *vlan_info); 1124 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time); 1125 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, 1126 struct hclge_desc *desc); 1127 void hclge_report_hw_error(struct hclge_dev *hdev, 1128 enum hnae3_hw_error_type type); 1129 void hclge_inform_vf_promisc_info(struct hclge_vport *vport); 1130 int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len); 1131 int hclge_push_vf_link_status(struct hclge_vport *vport); 1132 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en); 1133 #endif 1134