1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_MAIN_H 5 #define __HCLGE_MAIN_H 6 #include <linux/fs.h> 7 #include <linux/types.h> 8 #include <linux/phy.h> 9 #include <linux/if_vlan.h> 10 #include <linux/kfifo.h> 11 12 #include "hclge_cmd.h" 13 #include "hnae3.h" 14 15 #define HCLGE_MOD_VERSION "1.0" 16 #define HCLGE_DRIVER_NAME "hclge" 17 18 #define HCLGE_MAX_PF_NUM 8 19 20 #define HCLGE_VF_VPORT_START_NUM 1 21 22 #define HCLGE_RD_FIRST_STATS_NUM 2 23 #define HCLGE_RD_OTHER_STATS_NUM 4 24 25 #define HCLGE_INVALID_VPORT 0xffff 26 27 #define HCLGE_PF_CFG_BLOCK_SIZE 32 28 #define HCLGE_PF_CFG_DESC_NUM \ 29 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) 30 31 #define HCLGE_VECTOR_REG_BASE 0x20000 32 #define HCLGE_VECTOR_EXT_REG_BASE 0x30000 33 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400 34 35 #define HCLGE_VECTOR_REG_OFFSET 0x4 36 #define HCLGE_VECTOR_REG_OFFSET_H 0x1000 37 #define HCLGE_VECTOR_VF_OFFSET 0x100000 38 39 #define HCLGE_CMDQ_TX_ADDR_L_REG 0x27000 40 #define HCLGE_CMDQ_TX_ADDR_H_REG 0x27004 41 #define HCLGE_CMDQ_TX_DEPTH_REG 0x27008 42 #define HCLGE_CMDQ_TX_TAIL_REG 0x27010 43 #define HCLGE_CMDQ_TX_HEAD_REG 0x27014 44 #define HCLGE_CMDQ_RX_ADDR_L_REG 0x27018 45 #define HCLGE_CMDQ_RX_ADDR_H_REG 0x2701C 46 #define HCLGE_CMDQ_RX_DEPTH_REG 0x27020 47 #define HCLGE_CMDQ_RX_TAIL_REG 0x27024 48 #define HCLGE_CMDQ_RX_HEAD_REG 0x27028 49 #define HCLGE_CMDQ_INTR_STS_REG 0x27104 50 #define HCLGE_CMDQ_INTR_EN_REG 0x27108 51 #define HCLGE_CMDQ_INTR_GEN_REG 0x2710C 52 53 /* bar registers for common func */ 54 #define HCLGE_VECTOR0_OTER_EN_REG 0x20600 55 #define HCLGE_GRO_EN_REG 0x28000 56 #define HCLGE_RXD_ADV_LAYOUT_EN_REG 0x28008 57 58 /* bar registers for rcb */ 59 #define HCLGE_RING_RX_ADDR_L_REG 0x80000 60 #define HCLGE_RING_RX_ADDR_H_REG 0x80004 61 #define HCLGE_RING_RX_BD_NUM_REG 0x80008 62 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C 63 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014 64 #define HCLGE_RING_RX_TAIL_REG 0x80018 65 #define HCLGE_RING_RX_HEAD_REG 0x8001C 66 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020 67 #define HCLGE_RING_RX_OFFSET_REG 0x80024 68 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028 69 #define HCLGE_RING_RX_STASH_REG 0x80030 70 #define HCLGE_RING_RX_BD_ERR_REG 0x80034 71 #define HCLGE_RING_TX_ADDR_L_REG 0x80040 72 #define HCLGE_RING_TX_ADDR_H_REG 0x80044 73 #define HCLGE_RING_TX_BD_NUM_REG 0x80048 74 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C 75 #define HCLGE_RING_TX_TC_REG 0x80050 76 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054 77 #define HCLGE_RING_TX_TAIL_REG 0x80058 78 #define HCLGE_RING_TX_HEAD_REG 0x8005C 79 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060 80 #define HCLGE_RING_TX_OFFSET_REG 0x80064 81 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068 82 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070 83 #define HCLGE_RING_TX_BD_ERR_REG 0x80074 84 #define HCLGE_RING_EN_REG 0x80090 85 86 /* bar registers for tqp interrupt */ 87 #define HCLGE_TQP_INTR_CTRL_REG 0x20000 88 #define HCLGE_TQP_INTR_GL0_REG 0x20100 89 #define HCLGE_TQP_INTR_GL1_REG 0x20200 90 #define HCLGE_TQP_INTR_GL2_REG 0x20300 91 #define HCLGE_TQP_INTR_RL_REG 0x20900 92 93 #define HCLGE_RSS_IND_TBL_SIZE 512 94 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0) 95 #define HCLGE_RSS_KEY_SIZE 40 96 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0 97 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1 98 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2 99 #define HCLGE_RSS_HASH_ALGO_MASK GENMASK(3, 0) 100 101 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) 102 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) 103 #define HCLGE_D_PORT_BIT BIT(0) 104 #define HCLGE_S_PORT_BIT BIT(1) 105 #define HCLGE_D_IP_BIT BIT(2) 106 #define HCLGE_S_IP_BIT BIT(3) 107 #define HCLGE_V_TAG_BIT BIT(4) 108 #define HCLGE_RSS_INPUT_TUPLE_SCTP_NO_PORT \ 109 (HCLGE_D_IP_BIT | HCLGE_S_IP_BIT | HCLGE_V_TAG_BIT) 110 111 #define HCLGE_RSS_TC_SIZE_0 1 112 #define HCLGE_RSS_TC_SIZE_1 2 113 #define HCLGE_RSS_TC_SIZE_2 4 114 #define HCLGE_RSS_TC_SIZE_3 8 115 #define HCLGE_RSS_TC_SIZE_4 16 116 #define HCLGE_RSS_TC_SIZE_5 32 117 #define HCLGE_RSS_TC_SIZE_6 64 118 #define HCLGE_RSS_TC_SIZE_7 128 119 120 #define HCLGE_UMV_TBL_SIZE 3072 121 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \ 122 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM) 123 124 #define HCLGE_TQP_RESET_TRY_TIMES 200 125 126 #define HCLGE_PHY_PAGE_MDIX 0 127 #define HCLGE_PHY_PAGE_COPPER 0 128 129 /* Page Selection Reg. */ 130 #define HCLGE_PHY_PAGE_REG 22 131 132 /* Copper Specific Control Register */ 133 #define HCLGE_PHY_CSC_REG 16 134 135 /* Copper Specific Status Register */ 136 #define HCLGE_PHY_CSS_REG 17 137 138 #define HCLGE_PHY_MDIX_CTRL_S 5 139 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) 140 141 #define HCLGE_PHY_MDIX_STATUS_B 6 142 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11 143 144 #define HCLGE_GET_DFX_REG_TYPE_CNT 4 145 146 /* Factor used to calculate offset and bitmap of VF num */ 147 #define HCLGE_VF_NUM_PER_CMD 64 148 149 #define HCLGE_MAX_QSET_NUM 1024 150 151 #define HCLGE_DBG_RESET_INFO_LEN 1024 152 153 enum HLCGE_PORT_TYPE { 154 HOST_PORT, 155 NETWORK_PORT 156 }; 157 158 #define PF_VPORT_ID 0 159 160 #define HCLGE_PF_ID_S 0 161 #define HCLGE_PF_ID_M GENMASK(2, 0) 162 #define HCLGE_VF_ID_S 3 163 #define HCLGE_VF_ID_M GENMASK(10, 3) 164 #define HCLGE_PORT_TYPE_B 11 165 #define HCLGE_NETWORK_PORT_ID_S 0 166 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0) 167 168 /* Reset related Registers */ 169 #define HCLGE_PF_OTHER_INT_REG 0x20600 170 #define HCLGE_MISC_RESET_STS_REG 0x20700 171 #define HCLGE_MISC_VECTOR_INT_STS 0x20800 172 #define HCLGE_GLOBAL_RESET_REG 0x20A00 173 #define HCLGE_GLOBAL_RESET_BIT 0 174 #define HCLGE_CORE_RESET_BIT 1 175 #define HCLGE_IMP_RESET_BIT 2 176 #define HCLGE_RESET_INT_M GENMASK(7, 5) 177 #define HCLGE_FUN_RST_ING 0x20C00 178 #define HCLGE_FUN_RST_ING_B 0 179 180 /* Vector0 register bits define */ 181 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5 182 #define HCLGE_VECTOR0_CORERESET_INT_B 6 183 #define HCLGE_VECTOR0_IMPRESET_INT_B 7 184 185 /* Vector0 interrupt CMDQ event source register(RW) */ 186 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100 187 /* CMDQ register bits for RX event(=MBX event) */ 188 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 189 190 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1 191 #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U 192 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U 193 194 #define HCLGE_MAC_DEFAULT_FRAME \ 195 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN) 196 #define HCLGE_MAC_MIN_FRAME 64 197 #define HCLGE_MAC_MAX_FRAME 9728 198 199 #define HCLGE_SUPPORT_1G_BIT BIT(0) 200 #define HCLGE_SUPPORT_10G_BIT BIT(1) 201 #define HCLGE_SUPPORT_25G_BIT BIT(2) 202 #define HCLGE_SUPPORT_50G_BIT BIT(3) 203 #define HCLGE_SUPPORT_100G_BIT BIT(4) 204 /* to be compatible with exsit board */ 205 #define HCLGE_SUPPORT_40G_BIT BIT(5) 206 #define HCLGE_SUPPORT_100M_BIT BIT(6) 207 #define HCLGE_SUPPORT_10M_BIT BIT(7) 208 #define HCLGE_SUPPORT_200G_BIT BIT(8) 209 #define HCLGE_SUPPORT_GE \ 210 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT) 211 212 enum HCLGE_DEV_STATE { 213 HCLGE_STATE_REINITING, 214 HCLGE_STATE_DOWN, 215 HCLGE_STATE_DISABLED, 216 HCLGE_STATE_REMOVING, 217 HCLGE_STATE_NIC_REGISTERED, 218 HCLGE_STATE_ROCE_REGISTERED, 219 HCLGE_STATE_SERVICE_INITED, 220 HCLGE_STATE_RST_SERVICE_SCHED, 221 HCLGE_STATE_RST_HANDLING, 222 HCLGE_STATE_MBX_SERVICE_SCHED, 223 HCLGE_STATE_MBX_HANDLING, 224 HCLGE_STATE_STATISTICS_UPDATING, 225 HCLGE_STATE_CMD_DISABLE, 226 HCLGE_STATE_LINK_UPDATING, 227 HCLGE_STATE_RST_FAIL, 228 HCLGE_STATE_FD_TBL_CHANGED, 229 HCLGE_STATE_FD_CLEAR_ALL, 230 HCLGE_STATE_FD_USER_DEF_CHANGED, 231 HCLGE_STATE_MAX 232 }; 233 234 enum hclge_evt_cause { 235 HCLGE_VECTOR0_EVENT_RST, 236 HCLGE_VECTOR0_EVENT_MBX, 237 HCLGE_VECTOR0_EVENT_ERR, 238 HCLGE_VECTOR0_EVENT_OTHER, 239 }; 240 241 enum HCLGE_MAC_SPEED { 242 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */ 243 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */ 244 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */ 245 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ 246 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ 247 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ 248 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ 249 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ 250 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */ 251 HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */ 252 }; 253 254 enum HCLGE_MAC_DUPLEX { 255 HCLGE_MAC_HALF, 256 HCLGE_MAC_FULL 257 }; 258 259 #define QUERY_SFP_SPEED 0 260 #define QUERY_ACTIVE_SPEED 1 261 262 struct hclge_mac { 263 u8 mac_id; 264 u8 phy_addr; 265 u8 flag; 266 u8 media_type; /* port media type, e.g. fibre/copper/backplane */ 267 u8 mac_addr[ETH_ALEN]; 268 u8 autoneg; 269 u8 duplex; 270 u8 support_autoneg; 271 u8 speed_type; /* 0: sfp speed, 1: active speed */ 272 u32 speed; 273 u32 max_speed; 274 u32 speed_ability; /* speed ability supported by current media */ 275 u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */ 276 u32 fec_mode; /* active fec mode */ 277 u32 user_fec_mode; 278 u32 fec_ability; 279 int link; /* store the link status of mac & phy (if phy exists) */ 280 struct phy_device *phydev; 281 struct mii_bus *mdio_bus; 282 phy_interface_t phy_if; 283 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 284 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); 285 }; 286 287 struct hclge_hw { 288 void __iomem *io_base; 289 void __iomem *mem_base; 290 struct hclge_mac mac; 291 int num_vec; 292 struct hclge_cmq cmq; 293 }; 294 295 /* TQP stats */ 296 struct hlcge_tqp_stats { 297 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ 298 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ 299 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ 300 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ 301 }; 302 303 struct hclge_tqp { 304 /* copy of device pointer from pci_dev, 305 * used when perform DMA mapping 306 */ 307 struct device *dev; 308 struct hnae3_queue q; 309 struct hlcge_tqp_stats tqp_stats; 310 u16 index; /* Global index in a NIC controller */ 311 312 bool alloced; 313 }; 314 315 enum hclge_fc_mode { 316 HCLGE_FC_NONE, 317 HCLGE_FC_RX_PAUSE, 318 HCLGE_FC_TX_PAUSE, 319 HCLGE_FC_FULL, 320 HCLGE_FC_PFC, 321 HCLGE_FC_DEFAULT 322 }; 323 324 enum hclge_link_fail_code { 325 HCLGE_LF_NORMAL, 326 HCLGE_LF_REF_CLOCK_LOST, 327 HCLGE_LF_XSFP_TX_DISABLE, 328 HCLGE_LF_XSFP_ABSENT, 329 }; 330 331 #define HCLGE_LINK_STATUS_DOWN 0 332 #define HCLGE_LINK_STATUS_UP 1 333 334 #define HCLGE_PG_NUM 4 335 #define HCLGE_SCH_MODE_SP 0 336 #define HCLGE_SCH_MODE_DWRR 1 337 struct hclge_pg_info { 338 u8 pg_id; 339 u8 pg_sch_mode; /* 0: sp; 1: dwrr */ 340 u8 tc_bit_map; 341 u32 bw_limit; 342 u8 tc_dwrr[HNAE3_MAX_TC]; 343 }; 344 345 struct hclge_tc_info { 346 u8 tc_id; 347 u8 tc_sch_mode; /* 0: sp; 1: dwrr */ 348 u8 pgid; 349 u32 bw_limit; 350 }; 351 352 struct hclge_cfg { 353 u8 tc_num; 354 u16 tqp_desc_num; 355 u16 rx_buf_len; 356 u16 vf_rss_size_max; 357 u16 pf_rss_size_max; 358 u8 phy_addr; 359 u8 media_type; 360 u8 mac_addr[ETH_ALEN]; 361 u8 default_speed; 362 u32 numa_node_map; 363 u16 speed_ability; 364 u16 umv_space; 365 }; 366 367 struct hclge_tm_info { 368 u8 num_tc; 369 u8 num_pg; /* It must be 1 if vNET-Base schd */ 370 u8 pg_dwrr[HCLGE_PG_NUM]; 371 u8 prio_tc[HNAE3_MAX_USER_PRIO]; 372 struct hclge_pg_info pg_info[HCLGE_PG_NUM]; 373 struct hclge_tc_info tc_info[HNAE3_MAX_TC]; 374 enum hclge_fc_mode fc_mode; 375 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */ 376 u8 pfc_en; /* PFC enabled or not for user priority */ 377 }; 378 379 struct hclge_comm_stats_str { 380 char desc[ETH_GSTRING_LEN]; 381 unsigned long offset; 382 }; 383 384 /* mac stats ,opcode id: 0x0032 */ 385 struct hclge_mac_stats { 386 u64 mac_tx_mac_pause_num; 387 u64 mac_rx_mac_pause_num; 388 u64 mac_tx_pfc_pri0_pkt_num; 389 u64 mac_tx_pfc_pri1_pkt_num; 390 u64 mac_tx_pfc_pri2_pkt_num; 391 u64 mac_tx_pfc_pri3_pkt_num; 392 u64 mac_tx_pfc_pri4_pkt_num; 393 u64 mac_tx_pfc_pri5_pkt_num; 394 u64 mac_tx_pfc_pri6_pkt_num; 395 u64 mac_tx_pfc_pri7_pkt_num; 396 u64 mac_rx_pfc_pri0_pkt_num; 397 u64 mac_rx_pfc_pri1_pkt_num; 398 u64 mac_rx_pfc_pri2_pkt_num; 399 u64 mac_rx_pfc_pri3_pkt_num; 400 u64 mac_rx_pfc_pri4_pkt_num; 401 u64 mac_rx_pfc_pri5_pkt_num; 402 u64 mac_rx_pfc_pri6_pkt_num; 403 u64 mac_rx_pfc_pri7_pkt_num; 404 u64 mac_tx_total_pkt_num; 405 u64 mac_tx_total_oct_num; 406 u64 mac_tx_good_pkt_num; 407 u64 mac_tx_bad_pkt_num; 408 u64 mac_tx_good_oct_num; 409 u64 mac_tx_bad_oct_num; 410 u64 mac_tx_uni_pkt_num; 411 u64 mac_tx_multi_pkt_num; 412 u64 mac_tx_broad_pkt_num; 413 u64 mac_tx_undersize_pkt_num; 414 u64 mac_tx_oversize_pkt_num; 415 u64 mac_tx_64_oct_pkt_num; 416 u64 mac_tx_65_127_oct_pkt_num; 417 u64 mac_tx_128_255_oct_pkt_num; 418 u64 mac_tx_256_511_oct_pkt_num; 419 u64 mac_tx_512_1023_oct_pkt_num; 420 u64 mac_tx_1024_1518_oct_pkt_num; 421 u64 mac_tx_1519_2047_oct_pkt_num; 422 u64 mac_tx_2048_4095_oct_pkt_num; 423 u64 mac_tx_4096_8191_oct_pkt_num; 424 u64 rsv0; 425 u64 mac_tx_8192_9216_oct_pkt_num; 426 u64 mac_tx_9217_12287_oct_pkt_num; 427 u64 mac_tx_12288_16383_oct_pkt_num; 428 u64 mac_tx_1519_max_good_oct_pkt_num; 429 u64 mac_tx_1519_max_bad_oct_pkt_num; 430 431 u64 mac_rx_total_pkt_num; 432 u64 mac_rx_total_oct_num; 433 u64 mac_rx_good_pkt_num; 434 u64 mac_rx_bad_pkt_num; 435 u64 mac_rx_good_oct_num; 436 u64 mac_rx_bad_oct_num; 437 u64 mac_rx_uni_pkt_num; 438 u64 mac_rx_multi_pkt_num; 439 u64 mac_rx_broad_pkt_num; 440 u64 mac_rx_undersize_pkt_num; 441 u64 mac_rx_oversize_pkt_num; 442 u64 mac_rx_64_oct_pkt_num; 443 u64 mac_rx_65_127_oct_pkt_num; 444 u64 mac_rx_128_255_oct_pkt_num; 445 u64 mac_rx_256_511_oct_pkt_num; 446 u64 mac_rx_512_1023_oct_pkt_num; 447 u64 mac_rx_1024_1518_oct_pkt_num; 448 u64 mac_rx_1519_2047_oct_pkt_num; 449 u64 mac_rx_2048_4095_oct_pkt_num; 450 u64 mac_rx_4096_8191_oct_pkt_num; 451 u64 rsv1; 452 u64 mac_rx_8192_9216_oct_pkt_num; 453 u64 mac_rx_9217_12287_oct_pkt_num; 454 u64 mac_rx_12288_16383_oct_pkt_num; 455 u64 mac_rx_1519_max_good_oct_pkt_num; 456 u64 mac_rx_1519_max_bad_oct_pkt_num; 457 458 u64 mac_tx_fragment_pkt_num; 459 u64 mac_tx_undermin_pkt_num; 460 u64 mac_tx_jabber_pkt_num; 461 u64 mac_tx_err_all_pkt_num; 462 u64 mac_tx_from_app_good_pkt_num; 463 u64 mac_tx_from_app_bad_pkt_num; 464 u64 mac_rx_fragment_pkt_num; 465 u64 mac_rx_undermin_pkt_num; 466 u64 mac_rx_jabber_pkt_num; 467 u64 mac_rx_fcs_err_pkt_num; 468 u64 mac_rx_send_app_good_pkt_num; 469 u64 mac_rx_send_app_bad_pkt_num; 470 u64 mac_tx_pfc_pause_pkt_num; 471 u64 mac_rx_pfc_pause_pkt_num; 472 u64 mac_tx_ctrl_pkt_num; 473 u64 mac_rx_ctrl_pkt_num; 474 }; 475 476 #define HCLGE_STATS_TIMER_INTERVAL 300UL 477 478 struct hclge_vlan_type_cfg { 479 u16 rx_ot_fst_vlan_type; 480 u16 rx_ot_sec_vlan_type; 481 u16 rx_in_fst_vlan_type; 482 u16 rx_in_sec_vlan_type; 483 u16 tx_ot_vlan_type; 484 u16 tx_in_vlan_type; 485 }; 486 487 enum HCLGE_FD_MODE { 488 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1, 489 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2, 490 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1, 491 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2, 492 }; 493 494 enum HCLGE_FD_KEY_TYPE { 495 HCLGE_FD_KEY_BASE_ON_PTYPE, 496 HCLGE_FD_KEY_BASE_ON_TUPLE, 497 }; 498 499 enum HCLGE_FD_STAGE { 500 HCLGE_FD_STAGE_1, 501 HCLGE_FD_STAGE_2, 502 MAX_STAGE_NUM, 503 }; 504 505 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet 506 * INNER_XXX indicate tuples in tunneled header of tunnel packet or 507 * tuples of non-tunnel packet 508 */ 509 enum HCLGE_FD_TUPLE { 510 OUTER_DST_MAC, 511 OUTER_SRC_MAC, 512 OUTER_VLAN_TAG_FST, 513 OUTER_VLAN_TAG_SEC, 514 OUTER_ETH_TYPE, 515 OUTER_L2_RSV, 516 OUTER_IP_TOS, 517 OUTER_IP_PROTO, 518 OUTER_SRC_IP, 519 OUTER_DST_IP, 520 OUTER_L3_RSV, 521 OUTER_SRC_PORT, 522 OUTER_DST_PORT, 523 OUTER_L4_RSV, 524 OUTER_TUN_VNI, 525 OUTER_TUN_FLOW_ID, 526 INNER_DST_MAC, 527 INNER_SRC_MAC, 528 INNER_VLAN_TAG_FST, 529 INNER_VLAN_TAG_SEC, 530 INNER_ETH_TYPE, 531 INNER_L2_RSV, 532 INNER_IP_TOS, 533 INNER_IP_PROTO, 534 INNER_SRC_IP, 535 INNER_DST_IP, 536 INNER_L3_RSV, 537 INNER_SRC_PORT, 538 INNER_DST_PORT, 539 INNER_L4_RSV, 540 MAX_TUPLE, 541 }; 542 543 #define HCLGE_FD_TUPLE_USER_DEF_TUPLES \ 544 (BIT(INNER_L2_RSV) | BIT(INNER_L3_RSV) | BIT(INNER_L4_RSV)) 545 546 enum HCLGE_FD_META_DATA { 547 PACKET_TYPE_ID, 548 IP_FRAGEMENT, 549 ROCE_TYPE, 550 NEXT_KEY, 551 VLAN_NUMBER, 552 SRC_VPORT, 553 DST_VPORT, 554 TUNNEL_PACKET, 555 MAX_META_DATA, 556 }; 557 558 enum HCLGE_FD_KEY_OPT { 559 KEY_OPT_U8, 560 KEY_OPT_LE16, 561 KEY_OPT_LE32, 562 KEY_OPT_MAC, 563 KEY_OPT_IP, 564 KEY_OPT_VNI, 565 }; 566 567 struct key_info { 568 u8 key_type; 569 u8 key_length; /* use bit as unit */ 570 enum HCLGE_FD_KEY_OPT key_opt; 571 int offset; 572 int moffset; 573 }; 574 575 #define MAX_KEY_LENGTH 400 576 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4) 577 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4) 578 #define MAX_META_DATA_LENGTH 32 579 580 #define HCLGE_FD_MAX_USER_DEF_OFFSET 9000 581 #define HCLGE_FD_USER_DEF_DATA GENMASK(15, 0) 582 #define HCLGE_FD_USER_DEF_OFFSET GENMASK(15, 0) 583 #define HCLGE_FD_USER_DEF_OFFSET_UNMASK GENMASK(15, 0) 584 585 /* assigned by firmware, the real filter number for each pf may be less */ 586 #define MAX_FD_FILTER_NUM 4096 587 #define HCLGE_ARFS_EXPIRE_INTERVAL 5UL 588 589 enum HCLGE_FD_ACTIVE_RULE_TYPE { 590 HCLGE_FD_RULE_NONE, 591 HCLGE_FD_ARFS_ACTIVE, 592 HCLGE_FD_EP_ACTIVE, 593 HCLGE_FD_TC_FLOWER_ACTIVE, 594 }; 595 596 enum HCLGE_FD_PACKET_TYPE { 597 NIC_PACKET, 598 ROCE_PACKET, 599 }; 600 601 enum HCLGE_FD_ACTION { 602 HCLGE_FD_ACTION_SELECT_QUEUE, 603 HCLGE_FD_ACTION_DROP_PACKET, 604 HCLGE_FD_ACTION_SELECT_TC, 605 }; 606 607 enum HCLGE_FD_NODE_STATE { 608 HCLGE_FD_TO_ADD, 609 HCLGE_FD_TO_DEL, 610 HCLGE_FD_ACTIVE, 611 HCLGE_FD_DELETED, 612 }; 613 614 enum HCLGE_FD_USER_DEF_LAYER { 615 HCLGE_FD_USER_DEF_NONE, 616 HCLGE_FD_USER_DEF_L2, 617 HCLGE_FD_USER_DEF_L3, 618 HCLGE_FD_USER_DEF_L4, 619 }; 620 621 #define HCLGE_FD_USER_DEF_LAYER_NUM 3 622 struct hclge_fd_user_def_cfg { 623 u16 ref_cnt; 624 u16 offset; 625 }; 626 627 struct hclge_fd_user_def_info { 628 enum HCLGE_FD_USER_DEF_LAYER layer; 629 u16 data; 630 u16 data_mask; 631 u16 offset; 632 }; 633 634 struct hclge_fd_key_cfg { 635 u8 key_sel; 636 u8 inner_sipv6_word_en; 637 u8 inner_dipv6_word_en; 638 u8 outer_sipv6_word_en; 639 u8 outer_dipv6_word_en; 640 u32 tuple_active; 641 u32 meta_data_active; 642 }; 643 644 struct hclge_fd_cfg { 645 u8 fd_mode; 646 u16 max_key_length; /* use bit as unit */ 647 u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */ 648 u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */ 649 struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM]; 650 struct hclge_fd_user_def_cfg user_def_cfg[HCLGE_FD_USER_DEF_LAYER_NUM]; 651 }; 652 653 #define IPV4_INDEX 3 654 #define IPV6_SIZE 4 655 struct hclge_fd_rule_tuples { 656 u8 src_mac[ETH_ALEN]; 657 u8 dst_mac[ETH_ALEN]; 658 /* Be compatible for ip address of both ipv4 and ipv6. 659 * For ipv4 address, we store it in src/dst_ip[3]. 660 */ 661 u32 src_ip[IPV6_SIZE]; 662 u32 dst_ip[IPV6_SIZE]; 663 u16 src_port; 664 u16 dst_port; 665 u16 vlan_tag1; 666 u16 ether_proto; 667 u16 l2_user_def; 668 u16 l3_user_def; 669 u32 l4_user_def; 670 u8 ip_tos; 671 u8 ip_proto; 672 }; 673 674 struct hclge_fd_rule { 675 struct hlist_node rule_node; 676 struct hclge_fd_rule_tuples tuples; 677 struct hclge_fd_rule_tuples tuples_mask; 678 u32 unused_tuple; 679 u32 flow_type; 680 union { 681 struct { 682 unsigned long cookie; 683 u8 tc; 684 } cls_flower; 685 struct { 686 u16 flow_id; /* only used for arfs */ 687 } arfs; 688 struct { 689 struct hclge_fd_user_def_info user_def; 690 } ep; 691 }; 692 u16 queue_id; 693 u16 vf_id; 694 u16 location; 695 enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type; 696 enum HCLGE_FD_NODE_STATE state; 697 u8 action; 698 }; 699 700 struct hclge_fd_ad_data { 701 u16 ad_id; 702 u8 drop_packet; 703 u8 forward_to_direct_queue; 704 u16 queue_id; 705 u8 use_counter; 706 u8 counter_id; 707 u8 use_next_stage; 708 u8 write_rule_id_to_bd; 709 u8 next_input_key; 710 u16 rule_id; 711 u16 tc_size; 712 u8 override_tc; 713 }; 714 715 enum HCLGE_MAC_NODE_STATE { 716 HCLGE_MAC_TO_ADD, 717 HCLGE_MAC_TO_DEL, 718 HCLGE_MAC_ACTIVE 719 }; 720 721 struct hclge_mac_node { 722 struct list_head node; 723 enum HCLGE_MAC_NODE_STATE state; 724 u8 mac_addr[ETH_ALEN]; 725 }; 726 727 enum HCLGE_MAC_ADDR_TYPE { 728 HCLGE_MAC_ADDR_UC, 729 HCLGE_MAC_ADDR_MC 730 }; 731 732 struct hclge_vport_vlan_cfg { 733 struct list_head node; 734 int hd_tbl_status; 735 u16 vlan_id; 736 }; 737 738 struct hclge_rst_stats { 739 u32 reset_done_cnt; /* the number of reset has completed */ 740 u32 hw_reset_done_cnt; /* the number of HW reset has completed */ 741 u32 pf_rst_cnt; /* the number of PF reset */ 742 u32 flr_rst_cnt; /* the number of FLR */ 743 u32 global_rst_cnt; /* the number of GLOBAL */ 744 u32 imp_rst_cnt; /* the number of IMP reset */ 745 u32 reset_cnt; /* the number of reset */ 746 u32 reset_fail_cnt; /* the number of reset fail */ 747 }; 748 749 /* time and register status when mac tunnel interruption occur */ 750 struct hclge_mac_tnl_stats { 751 u64 time; 752 u32 status; 753 }; 754 755 #define HCLGE_RESET_INTERVAL (10 * HZ) 756 #define HCLGE_WAIT_RESET_DONE 100 757 758 #pragma pack(1) 759 struct hclge_vf_vlan_cfg { 760 u8 mbx_cmd; 761 u8 subcode; 762 u8 is_kill; 763 u16 vlan; 764 u16 proto; 765 }; 766 767 #pragma pack() 768 769 /* For each bit of TCAM entry, it uses a pair of 'x' and 770 * 'y' to indicate which value to match, like below: 771 * ---------------------------------- 772 * | bit x | bit y | search value | 773 * ---------------------------------- 774 * | 0 | 0 | always hit | 775 * ---------------------------------- 776 * | 1 | 0 | match '0' | 777 * ---------------------------------- 778 * | 0 | 1 | match '1' | 779 * ---------------------------------- 780 * | 1 | 1 | invalid | 781 * ---------------------------------- 782 * Then for input key(k) and mask(v), we can calculate the value by 783 * the formulae: 784 * x = (~k) & v 785 * y = (k ^ ~v) & k 786 */ 787 #define calc_x(x, k, v) (x = ~(k) & (v)) 788 #define calc_y(y, k, v) \ 789 do { \ 790 const typeof(k) _k_ = (k); \ 791 const typeof(v) _v_ = (v); \ 792 (y) = (_k_ ^ ~_v_) & (_k_); \ 793 } while (0) 794 795 #define HCLGE_MAC_TNL_LOG_SIZE 8 796 #define HCLGE_VPORT_NUM 256 797 struct hclge_dev { 798 struct pci_dev *pdev; 799 struct hnae3_ae_dev *ae_dev; 800 struct hclge_hw hw; 801 struct hclge_misc_vector misc_vector; 802 struct hclge_mac_stats mac_stats; 803 unsigned long state; 804 unsigned long flr_state; 805 unsigned long last_reset_time; 806 807 enum hnae3_reset_type reset_type; 808 enum hnae3_reset_type reset_level; 809 unsigned long default_reset_request; 810 unsigned long reset_request; /* reset has been requested */ 811 unsigned long reset_pending; /* client rst is pending to be served */ 812 struct hclge_rst_stats rst_stats; 813 struct semaphore reset_sem; /* protect reset process */ 814 u32 fw_version; 815 u16 num_tqps; /* Num task queue pairs of this PF */ 816 u16 num_req_vfs; /* Num VFs requested for this PF */ 817 818 u16 base_tqp_pid; /* Base task tqp physical id of this PF */ 819 u16 alloc_rss_size; /* Allocated RSS task queue */ 820 u16 vf_rss_size_max; /* HW defined VF max RSS task queue */ 821 u16 pf_rss_size_max; /* HW defined PF max RSS task queue */ 822 823 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */ 824 u16 num_alloc_vport; /* Num vports this driver supports */ 825 u32 numa_node_mask; 826 u16 rx_buf_len; 827 u16 num_tx_desc; /* desc num of per tx queue */ 828 u16 num_rx_desc; /* desc num of per rx queue */ 829 u8 hw_tc_map; 830 enum hclge_fc_mode fc_mode_last_time; 831 u8 support_sfp_query; 832 833 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1 834 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2 835 u8 tx_sch_mode; 836 u8 tc_max; 837 u8 pfc_max; 838 839 u8 default_up; 840 u8 dcbx_cap; 841 struct hclge_tm_info tm_info; 842 843 u16 num_msi; 844 u16 num_msi_left; 845 u16 num_msi_used; 846 u32 base_msi_vector; 847 u16 *vector_status; 848 int *vector_irq; 849 u16 num_nic_msi; /* Num of nic vectors for this PF */ 850 u16 num_roce_msi; /* Num of roce vectors for this PF */ 851 int roce_base_vector; 852 853 unsigned long service_timer_period; 854 unsigned long service_timer_previous; 855 struct timer_list reset_timer; 856 struct delayed_work service_task; 857 858 bool cur_promisc; 859 int num_alloc_vfs; /* Actual number of VFs allocated */ 860 861 struct hclge_tqp *htqp; 862 struct hclge_vport *vport; 863 864 struct dentry *hclge_dbgfs; 865 866 struct hnae3_client *nic_client; 867 struct hnae3_client *roce_client; 868 869 #define HCLGE_FLAG_MAIN BIT(0) 870 #define HCLGE_FLAG_DCB_CAPABLE BIT(1) 871 #define HCLGE_FLAG_DCB_ENABLE BIT(2) 872 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3) 873 u32 flag; 874 875 u32 pkt_buf_size; /* Total pf buf size for tx/rx */ 876 u32 tx_buf_size; /* Tx buffer size for each TC */ 877 u32 dv_buf_size; /* Dv buffer size for each TC */ 878 879 u32 mps; /* Max packet size */ 880 /* vport_lock protect resource shared by vports */ 881 struct mutex vport_lock; 882 883 struct hclge_vlan_type_cfg vlan_type_cfg; 884 885 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 886 unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 887 888 unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; 889 890 struct hclge_fd_cfg fd_cfg; 891 struct hlist_head fd_rule_list; 892 spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */ 893 u16 hclge_fd_rule_num; 894 unsigned long serv_processed_cnt; 895 unsigned long last_serv_processed; 896 unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)]; 897 enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type; 898 u8 fd_en; 899 900 u16 wanted_umv_size; 901 /* max available unicast mac vlan space */ 902 u16 max_umv_size; 903 /* private unicast mac vlan space, it's same for PF and its VFs */ 904 u16 priv_umv_size; 905 /* unicast mac vlan space shared by PF and its VFs */ 906 u16 share_umv_size; 907 908 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats, 909 HCLGE_MAC_TNL_LOG_SIZE); 910 911 /* affinity mask and notify for misc interrupt */ 912 cpumask_t affinity_mask; 913 struct irq_affinity_notify affinity_notify; 914 }; 915 916 /* VPort level vlan tag configuration for TX direction */ 917 struct hclge_tx_vtag_cfg { 918 bool accept_tag1; /* Whether accept tag1 packet from host */ 919 bool accept_untag1; /* Whether accept untag1 packet from host */ 920 bool accept_tag2; 921 bool accept_untag2; 922 bool insert_tag1_en; /* Whether insert inner vlan tag */ 923 bool insert_tag2_en; /* Whether insert outer vlan tag */ 924 u16 default_tag1; /* The default inner vlan tag to insert */ 925 u16 default_tag2; /* The default outer vlan tag to insert */ 926 bool tag_shift_mode_en; 927 }; 928 929 /* VPort level vlan tag configuration for RX direction */ 930 struct hclge_rx_vtag_cfg { 931 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */ 932 bool strip_tag1_en; /* Whether strip inner vlan tag */ 933 bool strip_tag2_en; /* Whether strip outer vlan tag */ 934 bool vlan1_vlan_prionly; /* Inner vlan tag up to descriptor enable */ 935 bool vlan2_vlan_prionly; /* Outer vlan tag up to descriptor enable */ 936 bool strip_tag1_discard_en; /* Inner vlan tag discard for BD enable */ 937 bool strip_tag2_discard_en; /* Outer vlan tag discard for BD enable */ 938 }; 939 940 struct hclge_rss_tuple_cfg { 941 u8 ipv4_tcp_en; 942 u8 ipv4_udp_en; 943 u8 ipv4_sctp_en; 944 u8 ipv4_fragment_en; 945 u8 ipv6_tcp_en; 946 u8 ipv6_udp_en; 947 u8 ipv6_sctp_en; 948 u8 ipv6_fragment_en; 949 }; 950 951 enum HCLGE_VPORT_STATE { 952 HCLGE_VPORT_STATE_ALIVE, 953 HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 954 HCLGE_VPORT_STATE_PROMISC_CHANGE, 955 HCLGE_VPORT_STATE_MAX 956 }; 957 958 struct hclge_vlan_info { 959 u16 vlan_proto; /* so far support 802.1Q only */ 960 u16 qos; 961 u16 vlan_tag; 962 }; 963 964 struct hclge_port_base_vlan_config { 965 u16 state; 966 struct hclge_vlan_info vlan_info; 967 }; 968 969 struct hclge_vf_info { 970 int link_state; 971 u8 mac[ETH_ALEN]; 972 u32 spoofchk; 973 u32 max_tx_rate; 974 u32 trusted; 975 u8 request_uc_en; 976 u8 request_mc_en; 977 u8 request_bc_en; 978 }; 979 980 struct hclge_vport { 981 u16 alloc_tqps; /* Allocated Tx/Rx queues */ 982 983 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */ 984 /* User configured lookup table entries */ 985 u16 *rss_indirection_tbl; 986 int rss_algo; /* User configured hash algorithm */ 987 /* User configured rss tuple sets */ 988 struct hclge_rss_tuple_cfg rss_tuple_sets; 989 990 u16 alloc_rss_size; 991 992 u16 qs_offset; 993 u32 bw_limit; /* VSI BW Limit (0 = disabled) */ 994 u8 dwrr; 995 996 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; 997 struct hclge_port_base_vlan_config port_base_vlan_cfg; 998 struct hclge_tx_vtag_cfg txvlan_cfg; 999 struct hclge_rx_vtag_cfg rxvlan_cfg; 1000 1001 u16 used_umv_num; 1002 1003 u16 vport_id; 1004 struct hclge_dev *back; /* Back reference to associated dev */ 1005 struct hnae3_handle nic; 1006 struct hnae3_handle roce; 1007 1008 unsigned long state; 1009 unsigned long last_active_jiffies; 1010 u32 mps; /* Max packet size */ 1011 struct hclge_vf_info vf_info; 1012 1013 u8 overflow_promisc_flags; 1014 u8 last_promisc_flags; 1015 1016 spinlock_t mac_list_lock; /* protect mac address need to add/detele */ 1017 struct list_head uc_mac_list; /* Store VF unicast table */ 1018 struct list_head mc_mac_list; /* Store VF multicast table */ 1019 struct list_head vlan_list; /* Store VF vlan table */ 1020 }; 1021 1022 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 1023 bool en_mc_pmc, bool en_bc_pmc); 1024 int hclge_add_uc_addr_common(struct hclge_vport *vport, 1025 const unsigned char *addr); 1026 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 1027 const unsigned char *addr); 1028 int hclge_add_mc_addr_common(struct hclge_vport *vport, 1029 const unsigned char *addr); 1030 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 1031 const unsigned char *addr); 1032 1033 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle); 1034 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 1035 int vector_id, bool en, 1036 struct hnae3_ring_chain_node *ring_chain); 1037 1038 static inline int hclge_get_queue_id(struct hnae3_queue *queue) 1039 { 1040 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q); 1041 1042 return tqp->index; 1043 } 1044 1045 static inline bool hclge_is_reset_pending(struct hclge_dev *hdev) 1046 { 1047 return !!hdev->reset_pending; 1048 } 1049 1050 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport); 1051 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex); 1052 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 1053 u16 vlan_id, bool is_kill); 1054 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable); 1055 1056 int hclge_buffer_alloc(struct hclge_dev *hdev); 1057 int hclge_rss_init_hw(struct hclge_dev *hdev); 1058 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev); 1059 1060 void hclge_mbx_handler(struct hclge_dev *hdev); 1061 int hclge_reset_tqp(struct hnae3_handle *handle); 1062 int hclge_cfg_flowctrl(struct hclge_dev *hdev); 1063 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id); 1064 int hclge_vport_start(struct hclge_vport *vport); 1065 void hclge_vport_stop(struct hclge_vport *vport); 1066 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu); 1067 int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, 1068 char *buf, int len); 1069 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id); 1070 int hclge_notify_client(struct hclge_dev *hdev, 1071 enum hnae3_reset_notify_type type); 1072 int hclge_update_mac_list(struct hclge_vport *vport, 1073 enum HCLGE_MAC_NODE_STATE state, 1074 enum HCLGE_MAC_ADDR_TYPE mac_type, 1075 const unsigned char *addr); 1076 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 1077 const u8 *old_addr, const u8 *new_addr); 1078 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 1079 enum HCLGE_MAC_ADDR_TYPE mac_type); 1080 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list); 1081 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev); 1082 void hclge_restore_mac_table_common(struct hclge_vport *vport); 1083 void hclge_restore_vport_vlan_table(struct hclge_vport *vport); 1084 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 1085 struct hclge_vlan_info *vlan_info); 1086 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid, 1087 u16 state, u16 vlan_tag, u16 qos, 1088 u16 vlan_proto); 1089 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time); 1090 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, 1091 struct hclge_desc *desc); 1092 void hclge_report_hw_error(struct hclge_dev *hdev, 1093 enum hnae3_hw_error_type type); 1094 void hclge_inform_vf_promisc_info(struct hclge_vport *vport); 1095 int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len); 1096 int hclge_push_vf_link_status(struct hclge_vport *vport); 1097 #endif 1098