1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/pci.h> 13 #include <linux/platform_device.h> 14 #include <linux/if_vlan.h> 15 #include <linux/crash_dump.h> 16 #include <net/ipv6.h> 17 #include <net/rtnetlink.h> 18 #include "hclge_cmd.h" 19 #include "hclge_dcb.h" 20 #include "hclge_main.h" 21 #include "hclge_mbx.h" 22 #include "hclge_mdio.h" 23 #include "hclge_tm.h" 24 #include "hclge_err.h" 25 #include "hnae3.h" 26 #include "hclge_devlink.h" 27 #include "hclge_comm_cmd.h" 28 29 #define HCLGE_NAME "hclge" 30 31 #define HCLGE_BUF_SIZE_UNIT 256U 32 #define HCLGE_BUF_MUL_BY 2 33 #define HCLGE_BUF_DIV_BY 2 34 #define NEED_RESERVE_TC_NUM 2 35 #define BUF_MAX_PERCENT 100 36 #define BUF_RESERVE_PERCENT 90 37 38 #define HCLGE_RESET_MAX_FAIL_CNT 5 39 #define HCLGE_RESET_SYNC_TIME 100 40 #define HCLGE_PF_RESET_SYNC_TIME 20 41 #define HCLGE_PF_RESET_SYNC_CNT 1500 42 43 /* Get DFX BD number offset */ 44 #define HCLGE_DFX_BIOS_BD_OFFSET 1 45 #define HCLGE_DFX_SSU_0_BD_OFFSET 2 46 #define HCLGE_DFX_SSU_1_BD_OFFSET 3 47 #define HCLGE_DFX_IGU_BD_OFFSET 4 48 #define HCLGE_DFX_RPU_0_BD_OFFSET 5 49 #define HCLGE_DFX_RPU_1_BD_OFFSET 6 50 #define HCLGE_DFX_NCSI_BD_OFFSET 7 51 #define HCLGE_DFX_RTC_BD_OFFSET 8 52 #define HCLGE_DFX_PPP_BD_OFFSET 9 53 #define HCLGE_DFX_RCB_BD_OFFSET 10 54 #define HCLGE_DFX_TQP_BD_OFFSET 11 55 #define HCLGE_DFX_SSU_2_BD_OFFSET 12 56 57 #define HCLGE_LINK_STATUS_MS 10 58 59 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps); 60 static int hclge_init_vlan_config(struct hclge_dev *hdev); 61 static void hclge_sync_vlan_filter(struct hclge_dev *hdev); 62 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 63 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle); 64 static void hclge_rfs_filter_expire(struct hclge_dev *hdev); 65 static int hclge_clear_arfs_rules(struct hclge_dev *hdev); 66 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 67 unsigned long *addr); 68 static int hclge_set_default_loopback(struct hclge_dev *hdev); 69 70 static void hclge_sync_mac_table(struct hclge_dev *hdev); 71 static void hclge_restore_hw_table(struct hclge_dev *hdev); 72 static void hclge_sync_promisc_mode(struct hclge_dev *hdev); 73 static void hclge_sync_fd_table(struct hclge_dev *hdev); 74 static void hclge_update_fec_stats(struct hclge_dev *hdev); 75 76 static struct hnae3_ae_algo ae_algo; 77 78 static struct workqueue_struct *hclge_wq; 79 80 static const struct pci_device_id ae_algo_pci_tbl[] = { 81 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 83 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 84 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 85 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 86 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 88 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 89 /* required last entry */ 90 {0, } 91 }; 92 93 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 94 95 static const u32 cmdq_reg_addr_list[] = {HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG, 96 HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG, 97 HCLGE_COMM_NIC_CSQ_DEPTH_REG, 98 HCLGE_COMM_NIC_CSQ_TAIL_REG, 99 HCLGE_COMM_NIC_CSQ_HEAD_REG, 100 HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG, 101 HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG, 102 HCLGE_COMM_NIC_CRQ_DEPTH_REG, 103 HCLGE_COMM_NIC_CRQ_TAIL_REG, 104 HCLGE_COMM_NIC_CRQ_HEAD_REG, 105 HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, 106 HCLGE_COMM_CMDQ_INTR_STS_REG, 107 HCLGE_COMM_CMDQ_INTR_EN_REG, 108 HCLGE_COMM_CMDQ_INTR_GEN_REG}; 109 110 static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE, 111 HCLGE_PF_OTHER_INT_REG, 112 HCLGE_MISC_RESET_STS_REG, 113 HCLGE_MISC_VECTOR_INT_STS, 114 HCLGE_GLOBAL_RESET_REG, 115 HCLGE_FUN_RST_ING, 116 HCLGE_GRO_EN_REG}; 117 118 static const u32 ring_reg_addr_list[] = {HCLGE_RING_RX_ADDR_L_REG, 119 HCLGE_RING_RX_ADDR_H_REG, 120 HCLGE_RING_RX_BD_NUM_REG, 121 HCLGE_RING_RX_BD_LENGTH_REG, 122 HCLGE_RING_RX_MERGE_EN_REG, 123 HCLGE_RING_RX_TAIL_REG, 124 HCLGE_RING_RX_HEAD_REG, 125 HCLGE_RING_RX_FBD_NUM_REG, 126 HCLGE_RING_RX_OFFSET_REG, 127 HCLGE_RING_RX_FBD_OFFSET_REG, 128 HCLGE_RING_RX_STASH_REG, 129 HCLGE_RING_RX_BD_ERR_REG, 130 HCLGE_RING_TX_ADDR_L_REG, 131 HCLGE_RING_TX_ADDR_H_REG, 132 HCLGE_RING_TX_BD_NUM_REG, 133 HCLGE_RING_TX_PRIORITY_REG, 134 HCLGE_RING_TX_TC_REG, 135 HCLGE_RING_TX_MERGE_EN_REG, 136 HCLGE_RING_TX_TAIL_REG, 137 HCLGE_RING_TX_HEAD_REG, 138 HCLGE_RING_TX_FBD_NUM_REG, 139 HCLGE_RING_TX_OFFSET_REG, 140 HCLGE_RING_TX_EBD_NUM_REG, 141 HCLGE_RING_TX_EBD_OFFSET_REG, 142 HCLGE_RING_TX_BD_ERR_REG, 143 HCLGE_RING_EN_REG}; 144 145 static const u32 tqp_intr_reg_addr_list[] = {HCLGE_TQP_INTR_CTRL_REG, 146 HCLGE_TQP_INTR_GL0_REG, 147 HCLGE_TQP_INTR_GL1_REG, 148 HCLGE_TQP_INTR_GL2_REG, 149 HCLGE_TQP_INTR_RL_REG}; 150 151 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 152 "External Loopback test", 153 "App Loopback test", 154 "Serdes serial Loopback test", 155 "Serdes parallel Loopback test", 156 "Phy Loopback test" 157 }; 158 159 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 160 {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 161 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 162 {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 163 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 164 {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 165 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)}, 166 {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 167 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)}, 168 {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 169 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)}, 170 {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 171 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)}, 172 {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 173 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)}, 174 {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 175 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 176 {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 177 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 178 {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 179 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 180 {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 181 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 182 {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 183 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 184 {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 185 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 186 {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 187 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 188 {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 189 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 190 {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 191 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)}, 192 {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 193 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)}, 194 {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 195 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)}, 196 {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 197 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)}, 198 {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 199 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)}, 200 {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 201 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)}, 202 {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 203 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)}, 204 {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 205 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)}, 206 {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 207 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)}, 208 {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 209 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 210 {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 211 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 212 {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 213 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 214 {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 215 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 216 {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 217 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 218 {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 219 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 220 {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 221 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 222 {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 223 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 224 {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 225 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)}, 226 {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)}, 228 {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)}, 230 {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 231 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)}, 232 {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)}, 234 {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 235 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)}, 236 {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 237 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)}, 238 {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 239 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)}, 240 {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 242 {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 244 {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 246 {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 247 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 248 {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 249 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 250 {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 251 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 252 {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 253 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 254 {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 255 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 256 {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 257 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 258 {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 259 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 260 {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 261 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 262 {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 264 {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 266 {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 268 {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 270 {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 272 {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 274 {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 276 {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 278 {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 280 {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 282 {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 284 {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 286 {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 288 {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 290 {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 291 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 292 {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 293 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 294 {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 295 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 296 {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 297 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 298 {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 300 {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 301 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 302 {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 303 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 304 {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 305 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 306 {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 307 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 308 {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 309 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 310 {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 312 {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 314 {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 316 {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 318 {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 320 {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 322 {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 324 {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 326 {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 328 {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 330 {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 332 {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 334 {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 336 {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 338 {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 340 341 {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 342 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 343 {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 344 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 345 {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 346 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 347 {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 348 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 349 {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 350 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 351 {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 352 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 353 {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 354 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 355 {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 356 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 357 {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 358 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 359 {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 360 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 361 {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 362 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 363 {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 364 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 365 }; 366 367 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 368 { 369 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 370 .ethter_type = cpu_to_le16(ETH_P_LLDP), 371 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e}, 372 .i_port_bitmap = 0x1, 373 }, 374 }; 375 376 static const u32 hclge_dfx_bd_offset_list[] = { 377 HCLGE_DFX_BIOS_BD_OFFSET, 378 HCLGE_DFX_SSU_0_BD_OFFSET, 379 HCLGE_DFX_SSU_1_BD_OFFSET, 380 HCLGE_DFX_IGU_BD_OFFSET, 381 HCLGE_DFX_RPU_0_BD_OFFSET, 382 HCLGE_DFX_RPU_1_BD_OFFSET, 383 HCLGE_DFX_NCSI_BD_OFFSET, 384 HCLGE_DFX_RTC_BD_OFFSET, 385 HCLGE_DFX_PPP_BD_OFFSET, 386 HCLGE_DFX_RCB_BD_OFFSET, 387 HCLGE_DFX_TQP_BD_OFFSET, 388 HCLGE_DFX_SSU_2_BD_OFFSET 389 }; 390 391 static const enum hclge_opcode_type hclge_dfx_reg_opcode_list[] = { 392 HCLGE_OPC_DFX_BIOS_COMMON_REG, 393 HCLGE_OPC_DFX_SSU_REG_0, 394 HCLGE_OPC_DFX_SSU_REG_1, 395 HCLGE_OPC_DFX_IGU_EGU_REG, 396 HCLGE_OPC_DFX_RPU_REG_0, 397 HCLGE_OPC_DFX_RPU_REG_1, 398 HCLGE_OPC_DFX_NCSI_REG, 399 HCLGE_OPC_DFX_RTC_REG, 400 HCLGE_OPC_DFX_PPP_REG, 401 HCLGE_OPC_DFX_RCB_REG, 402 HCLGE_OPC_DFX_TQP_REG, 403 HCLGE_OPC_DFX_SSU_REG_2 404 }; 405 406 static const struct key_info meta_data_key_info[] = { 407 { PACKET_TYPE_ID, 6 }, 408 { IP_FRAGEMENT, 1 }, 409 { ROCE_TYPE, 1 }, 410 { NEXT_KEY, 5 }, 411 { VLAN_NUMBER, 2 }, 412 { SRC_VPORT, 12 }, 413 { DST_VPORT, 12 }, 414 { TUNNEL_PACKET, 1 }, 415 }; 416 417 static const struct key_info tuple_key_info[] = { 418 { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 }, 419 { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 }, 420 { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 }, 421 { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 422 { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 }, 423 { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 }, 424 { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 }, 425 { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 }, 426 { OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 }, 427 { OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 }, 428 { OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 }, 429 { OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 }, 430 { OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 }, 431 { OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 }, 432 { OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 }, 433 { OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 }, 434 { INNER_DST_MAC, 48, KEY_OPT_MAC, 435 offsetof(struct hclge_fd_rule, tuples.dst_mac), 436 offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) }, 437 { INNER_SRC_MAC, 48, KEY_OPT_MAC, 438 offsetof(struct hclge_fd_rule, tuples.src_mac), 439 offsetof(struct hclge_fd_rule, tuples_mask.src_mac) }, 440 { INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16, 441 offsetof(struct hclge_fd_rule, tuples.vlan_tag1), 442 offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) }, 443 { INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 444 { INNER_ETH_TYPE, 16, KEY_OPT_LE16, 445 offsetof(struct hclge_fd_rule, tuples.ether_proto), 446 offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) }, 447 { INNER_L2_RSV, 16, KEY_OPT_LE16, 448 offsetof(struct hclge_fd_rule, tuples.l2_user_def), 449 offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) }, 450 { INNER_IP_TOS, 8, KEY_OPT_U8, 451 offsetof(struct hclge_fd_rule, tuples.ip_tos), 452 offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) }, 453 { INNER_IP_PROTO, 8, KEY_OPT_U8, 454 offsetof(struct hclge_fd_rule, tuples.ip_proto), 455 offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) }, 456 { INNER_SRC_IP, 32, KEY_OPT_IP, 457 offsetof(struct hclge_fd_rule, tuples.src_ip), 458 offsetof(struct hclge_fd_rule, tuples_mask.src_ip) }, 459 { INNER_DST_IP, 32, KEY_OPT_IP, 460 offsetof(struct hclge_fd_rule, tuples.dst_ip), 461 offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) }, 462 { INNER_L3_RSV, 16, KEY_OPT_LE16, 463 offsetof(struct hclge_fd_rule, tuples.l3_user_def), 464 offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) }, 465 { INNER_SRC_PORT, 16, KEY_OPT_LE16, 466 offsetof(struct hclge_fd_rule, tuples.src_port), 467 offsetof(struct hclge_fd_rule, tuples_mask.src_port) }, 468 { INNER_DST_PORT, 16, KEY_OPT_LE16, 469 offsetof(struct hclge_fd_rule, tuples.dst_port), 470 offsetof(struct hclge_fd_rule, tuples_mask.dst_port) }, 471 { INNER_L4_RSV, 32, KEY_OPT_LE32, 472 offsetof(struct hclge_fd_rule, tuples.l4_user_def), 473 offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) }, 474 }; 475 476 /** 477 * hclge_cmd_send - send command to command queue 478 * @hw: pointer to the hw struct 479 * @desc: prefilled descriptor for describing the command 480 * @num : the number of descriptors to be sent 481 * 482 * This is the main send command for command queue, it 483 * sends the queue, cleans the queue, etc 484 **/ 485 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 486 { 487 return hclge_comm_cmd_send(&hw->hw, desc, num); 488 } 489 490 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev) 491 { 492 #define HCLGE_MAC_CMD_NUM 21 493 494 u64 *data = (u64 *)(&hdev->mac_stats); 495 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 496 __le64 *desc_data; 497 u32 data_size; 498 int ret; 499 u32 i; 500 501 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 502 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 503 if (ret) { 504 dev_err(&hdev->pdev->dev, 505 "Get MAC pkt stats fail, status = %d.\n", ret); 506 507 return ret; 508 } 509 510 /* The first desc has a 64-bit header, so data size need to minus 1 */ 511 data_size = sizeof(desc) / (sizeof(u64)) - 1; 512 513 desc_data = (__le64 *)(&desc[0].data[0]); 514 for (i = 0; i < data_size; i++) { 515 /* data memory is continuous becase only the first desc has a 516 * header in this command 517 */ 518 *data += le64_to_cpu(*desc_data); 519 data++; 520 desc_data++; 521 } 522 523 return 0; 524 } 525 526 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev) 527 { 528 #define HCLGE_REG_NUM_PER_DESC 4 529 530 u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num; 531 u64 *data = (u64 *)(&hdev->mac_stats); 532 struct hclge_desc *desc; 533 __le64 *desc_data; 534 u32 data_size; 535 u32 desc_num; 536 int ret; 537 u32 i; 538 539 /* The first desc has a 64-bit header, so need to consider it */ 540 desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1; 541 542 /* This may be called inside atomic sections, 543 * so GFP_ATOMIC is more suitalbe here 544 */ 545 desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC); 546 if (!desc) 547 return -ENOMEM; 548 549 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true); 550 ret = hclge_cmd_send(&hdev->hw, desc, desc_num); 551 if (ret) { 552 kfree(desc); 553 return ret; 554 } 555 556 data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num); 557 558 desc_data = (__le64 *)(&desc[0].data[0]); 559 for (i = 0; i < data_size; i++) { 560 /* data memory is continuous becase only the first desc has a 561 * header in this command 562 */ 563 *data += le64_to_cpu(*desc_data); 564 data++; 565 desc_data++; 566 } 567 568 kfree(desc); 569 570 return 0; 571 } 572 573 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num) 574 { 575 struct hclge_desc desc; 576 int ret; 577 578 /* Driver needs total register number of both valid registers and 579 * reserved registers, but the old firmware only returns number 580 * of valid registers in device V2. To be compatible with these 581 * devices, driver uses a fixed value. 582 */ 583 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) { 584 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1; 585 return 0; 586 } 587 588 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true); 589 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 590 if (ret) { 591 dev_err(&hdev->pdev->dev, 592 "failed to query mac statistic reg number, ret = %d\n", 593 ret); 594 return ret; 595 } 596 597 *reg_num = le32_to_cpu(desc.data[0]); 598 if (*reg_num == 0) { 599 dev_err(&hdev->pdev->dev, 600 "mac statistic reg number is invalid!\n"); 601 return -ENODATA; 602 } 603 604 return 0; 605 } 606 607 int hclge_mac_update_stats(struct hclge_dev *hdev) 608 { 609 /* The firmware supports the new statistics acquisition method */ 610 if (hdev->ae_dev->dev_specs.mac_stats_num) 611 return hclge_mac_update_stats_complete(hdev); 612 else 613 return hclge_mac_update_stats_defective(hdev); 614 } 615 616 static int hclge_comm_get_count(struct hclge_dev *hdev, 617 const struct hclge_comm_stats_str strs[], 618 u32 size) 619 { 620 int count = 0; 621 u32 i; 622 623 for (i = 0; i < size; i++) 624 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num) 625 count++; 626 627 return count; 628 } 629 630 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, 631 const struct hclge_comm_stats_str strs[], 632 int size, u64 *data) 633 { 634 u64 *buf = data; 635 u32 i; 636 637 for (i = 0; i < size; i++) { 638 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 639 continue; 640 641 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset); 642 buf++; 643 } 644 645 return buf; 646 } 647 648 static u8 *hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, 649 const struct hclge_comm_stats_str strs[], 650 int size, u8 *data) 651 { 652 char *buff = (char *)data; 653 u32 i; 654 655 if (stringset != ETH_SS_STATS) 656 return buff; 657 658 for (i = 0; i < size; i++) { 659 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 660 continue; 661 662 snprintf(buff, ETH_GSTRING_LEN, "%s", strs[i].desc); 663 buff = buff + ETH_GSTRING_LEN; 664 } 665 666 return (u8 *)buff; 667 } 668 669 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 670 { 671 struct hnae3_handle *handle; 672 int status; 673 674 handle = &hdev->vport[0].nic; 675 if (handle->client) { 676 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 677 if (status) { 678 dev_err(&hdev->pdev->dev, 679 "Update TQPS stats fail, status = %d.\n", 680 status); 681 } 682 } 683 684 hclge_update_fec_stats(hdev); 685 686 status = hclge_mac_update_stats(hdev); 687 if (status) 688 dev_err(&hdev->pdev->dev, 689 "Update MAC stats fail, status = %d.\n", status); 690 } 691 692 static void hclge_update_stats(struct hnae3_handle *handle, 693 struct net_device_stats *net_stats) 694 { 695 struct hclge_vport *vport = hclge_get_vport(handle); 696 struct hclge_dev *hdev = vport->back; 697 int status; 698 699 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 700 return; 701 702 status = hclge_mac_update_stats(hdev); 703 if (status) 704 dev_err(&hdev->pdev->dev, 705 "Update MAC stats fail, status = %d.\n", 706 status); 707 708 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 709 if (status) 710 dev_err(&hdev->pdev->dev, 711 "Update TQPS stats fail, status = %d.\n", 712 status); 713 714 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 715 } 716 717 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 718 { 719 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \ 720 HNAE3_SUPPORT_PHY_LOOPBACK | \ 721 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \ 722 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \ 723 HNAE3_SUPPORT_EXTERNAL_LOOPBACK) 724 725 struct hclge_vport *vport = hclge_get_vport(handle); 726 struct hclge_dev *hdev = vport->back; 727 int count = 0; 728 729 /* Loopback test support rules: 730 * mac: only GE mode support 731 * serdes: all mac mode will support include GE/XGE/LGE/CGE 732 * phy: only support when phy device exist on board 733 */ 734 if (stringset == ETH_SS_TEST) { 735 /* clear loopback bit flags at first */ 736 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 737 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 || 738 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 739 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 740 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 741 count += 1; 742 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; 743 } 744 745 count += 1; 746 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; 747 count += 1; 748 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; 749 count += 1; 750 handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK; 751 752 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv && 753 hdev->hw.mac.phydev->drv->set_loopback) || 754 hnae3_dev_phy_imp_supported(hdev)) { 755 count += 1; 756 handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK; 757 } 758 } else if (stringset == ETH_SS_STATS) { 759 count = hclge_comm_get_count(hdev, g_mac_stats_string, 760 ARRAY_SIZE(g_mac_stats_string)) + 761 hclge_comm_tqps_get_sset_count(handle); 762 } 763 764 return count; 765 } 766 767 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset, 768 u8 *data) 769 { 770 struct hclge_vport *vport = hclge_get_vport(handle); 771 struct hclge_dev *hdev = vport->back; 772 u8 *p = (char *)data; 773 int size; 774 775 if (stringset == ETH_SS_STATS) { 776 size = ARRAY_SIZE(g_mac_stats_string); 777 p = hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, 778 size, p); 779 p = hclge_comm_tqps_get_strings(handle, p); 780 } else if (stringset == ETH_SS_TEST) { 781 if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) { 782 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL], 783 ETH_GSTRING_LEN); 784 p += ETH_GSTRING_LEN; 785 } 786 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { 787 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_APP], 788 ETH_GSTRING_LEN); 789 p += ETH_GSTRING_LEN; 790 } 791 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { 792 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES], 793 ETH_GSTRING_LEN); 794 p += ETH_GSTRING_LEN; 795 } 796 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { 797 memcpy(p, 798 hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES], 799 ETH_GSTRING_LEN); 800 p += ETH_GSTRING_LEN; 801 } 802 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 803 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_PHY], 804 ETH_GSTRING_LEN); 805 p += ETH_GSTRING_LEN; 806 } 807 } 808 } 809 810 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 811 { 812 struct hclge_vport *vport = hclge_get_vport(handle); 813 struct hclge_dev *hdev = vport->back; 814 u64 *p; 815 816 p = hclge_comm_get_stats(hdev, g_mac_stats_string, 817 ARRAY_SIZE(g_mac_stats_string), data); 818 p = hclge_comm_tqps_get_stats(handle, p); 819 } 820 821 static void hclge_get_mac_stat(struct hnae3_handle *handle, 822 struct hns3_mac_stats *mac_stats) 823 { 824 struct hclge_vport *vport = hclge_get_vport(handle); 825 struct hclge_dev *hdev = vport->back; 826 827 hclge_update_stats(handle, NULL); 828 829 mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num; 830 mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num; 831 } 832 833 static int hclge_parse_func_status(struct hclge_dev *hdev, 834 struct hclge_func_status_cmd *status) 835 { 836 #define HCLGE_MAC_ID_MASK 0xF 837 838 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 839 return -EINVAL; 840 841 /* Set the pf to main pf */ 842 if (status->pf_state & HCLGE_PF_STATE_MAIN) 843 hdev->flag |= HCLGE_FLAG_MAIN; 844 else 845 hdev->flag &= ~HCLGE_FLAG_MAIN; 846 847 hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK; 848 return 0; 849 } 850 851 static int hclge_query_function_status(struct hclge_dev *hdev) 852 { 853 #define HCLGE_QUERY_MAX_CNT 5 854 855 struct hclge_func_status_cmd *req; 856 struct hclge_desc desc; 857 int timeout = 0; 858 int ret; 859 860 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 861 req = (struct hclge_func_status_cmd *)desc.data; 862 863 do { 864 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 865 if (ret) { 866 dev_err(&hdev->pdev->dev, 867 "query function status failed %d.\n", ret); 868 return ret; 869 } 870 871 /* Check pf reset is done */ 872 if (req->pf_state) 873 break; 874 usleep_range(1000, 2000); 875 } while (timeout++ < HCLGE_QUERY_MAX_CNT); 876 877 return hclge_parse_func_status(hdev, req); 878 } 879 880 static int hclge_query_pf_resource(struct hclge_dev *hdev) 881 { 882 struct hclge_pf_res_cmd *req; 883 struct hclge_desc desc; 884 int ret; 885 886 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 887 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 888 if (ret) { 889 dev_err(&hdev->pdev->dev, 890 "query pf resource failed %d.\n", ret); 891 return ret; 892 } 893 894 req = (struct hclge_pf_res_cmd *)desc.data; 895 hdev->num_tqps = le16_to_cpu(req->tqp_num) + 896 le16_to_cpu(req->ext_tqp_num); 897 hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 898 899 if (req->tx_buf_size) 900 hdev->tx_buf_size = 901 le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S; 902 else 903 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 904 905 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT); 906 907 if (req->dv_buf_size) 908 hdev->dv_buf_size = 909 le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S; 910 else 911 hdev->dv_buf_size = HCLGE_DEFAULT_DV; 912 913 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT); 914 915 hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic); 916 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) { 917 dev_err(&hdev->pdev->dev, 918 "only %u msi resources available, not enough for pf(min:2).\n", 919 hdev->num_nic_msi); 920 return -EINVAL; 921 } 922 923 if (hnae3_dev_roce_supported(hdev)) { 924 hdev->num_roce_msi = 925 le16_to_cpu(req->pf_intr_vector_number_roce); 926 927 /* PF should have NIC vectors and Roce vectors, 928 * NIC vectors are queued before Roce vectors. 929 */ 930 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi; 931 } else { 932 hdev->num_msi = hdev->num_nic_msi; 933 } 934 935 return 0; 936 } 937 938 static int hclge_parse_speed(u8 speed_cmd, u32 *speed) 939 { 940 switch (speed_cmd) { 941 case HCLGE_FW_MAC_SPEED_10M: 942 *speed = HCLGE_MAC_SPEED_10M; 943 break; 944 case HCLGE_FW_MAC_SPEED_100M: 945 *speed = HCLGE_MAC_SPEED_100M; 946 break; 947 case HCLGE_FW_MAC_SPEED_1G: 948 *speed = HCLGE_MAC_SPEED_1G; 949 break; 950 case HCLGE_FW_MAC_SPEED_10G: 951 *speed = HCLGE_MAC_SPEED_10G; 952 break; 953 case HCLGE_FW_MAC_SPEED_25G: 954 *speed = HCLGE_MAC_SPEED_25G; 955 break; 956 case HCLGE_FW_MAC_SPEED_40G: 957 *speed = HCLGE_MAC_SPEED_40G; 958 break; 959 case HCLGE_FW_MAC_SPEED_50G: 960 *speed = HCLGE_MAC_SPEED_50G; 961 break; 962 case HCLGE_FW_MAC_SPEED_100G: 963 *speed = HCLGE_MAC_SPEED_100G; 964 break; 965 case HCLGE_FW_MAC_SPEED_200G: 966 *speed = HCLGE_MAC_SPEED_200G; 967 break; 968 default: 969 return -EINVAL; 970 } 971 972 return 0; 973 } 974 975 static const struct hclge_speed_bit_map speed_bit_map[] = { 976 {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT}, 977 {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT}, 978 {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT}, 979 {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT}, 980 {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT}, 981 {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT}, 982 {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BIT}, 983 {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BIT}, 984 {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT}, 985 }; 986 987 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit) 988 { 989 u16 i; 990 991 for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) { 992 if (speed == speed_bit_map[i].speed) { 993 *speed_bit = speed_bit_map[i].speed_bit; 994 return 0; 995 } 996 } 997 998 return -EINVAL; 999 } 1000 1001 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed) 1002 { 1003 struct hclge_vport *vport = hclge_get_vport(handle); 1004 struct hclge_dev *hdev = vport->back; 1005 u32 speed_ability = hdev->hw.mac.speed_ability; 1006 u32 speed_bit = 0; 1007 int ret; 1008 1009 ret = hclge_get_speed_bit(speed, &speed_bit); 1010 if (ret) 1011 return ret; 1012 1013 if (speed_bit & speed_ability) 1014 return 0; 1015 1016 return -EINVAL; 1017 } 1018 1019 static void hclge_update_fec_support(struct hclge_mac *mac) 1020 { 1021 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported); 1022 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported); 1023 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported); 1024 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1025 1026 if (mac->fec_ability & BIT(HNAE3_FEC_BASER)) 1027 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1028 mac->supported); 1029 if (mac->fec_ability & BIT(HNAE3_FEC_RS)) 1030 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1031 mac->supported); 1032 if (mac->fec_ability & BIT(HNAE3_FEC_LLRS)) 1033 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1034 mac->supported); 1035 if (mac->fec_ability & BIT(HNAE3_FEC_NONE)) 1036 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1037 mac->supported); 1038 } 1039 1040 static void hclge_convert_setting_sr(u16 speed_ability, 1041 unsigned long *link_mode) 1042 { 1043 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1044 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1045 link_mode); 1046 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1047 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1048 link_mode); 1049 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1050 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 1051 link_mode); 1052 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1053 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 1054 link_mode); 1055 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1056 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 1057 link_mode); 1058 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1059 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 1060 link_mode); 1061 } 1062 1063 static void hclge_convert_setting_lr(u16 speed_ability, 1064 unsigned long *link_mode) 1065 { 1066 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1067 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 1068 link_mode); 1069 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1070 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1071 link_mode); 1072 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1073 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 1074 link_mode); 1075 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1076 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 1077 link_mode); 1078 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1079 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 1080 link_mode); 1081 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1082 linkmode_set_bit( 1083 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 1084 link_mode); 1085 } 1086 1087 static void hclge_convert_setting_cr(u16 speed_ability, 1088 unsigned long *link_mode) 1089 { 1090 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1091 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 1092 link_mode); 1093 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1094 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 1095 link_mode); 1096 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1097 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 1098 link_mode); 1099 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1100 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 1101 link_mode); 1102 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1103 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 1104 link_mode); 1105 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1106 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 1107 link_mode); 1108 } 1109 1110 static void hclge_convert_setting_kr(u16 speed_ability, 1111 unsigned long *link_mode) 1112 { 1113 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1114 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1115 link_mode); 1116 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1117 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1118 link_mode); 1119 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1120 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 1121 link_mode); 1122 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1123 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 1124 link_mode); 1125 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1126 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 1127 link_mode); 1128 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1129 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 1130 link_mode); 1131 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1132 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 1133 link_mode); 1134 } 1135 1136 static void hclge_convert_setting_fec(struct hclge_mac *mac) 1137 { 1138 /* If firmware has reported fec_ability, don't need to convert by speed */ 1139 if (mac->fec_ability) 1140 goto out; 1141 1142 switch (mac->speed) { 1143 case HCLGE_MAC_SPEED_10G: 1144 case HCLGE_MAC_SPEED_40G: 1145 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) | 1146 BIT(HNAE3_FEC_NONE); 1147 break; 1148 case HCLGE_MAC_SPEED_25G: 1149 case HCLGE_MAC_SPEED_50G: 1150 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) | 1151 BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE); 1152 break; 1153 case HCLGE_MAC_SPEED_100G: 1154 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1155 BIT(HNAE3_FEC_NONE); 1156 break; 1157 case HCLGE_MAC_SPEED_200G: 1158 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1159 BIT(HNAE3_FEC_LLRS); 1160 break; 1161 default: 1162 mac->fec_ability = 0; 1163 break; 1164 } 1165 1166 out: 1167 hclge_update_fec_support(mac); 1168 } 1169 1170 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 1171 u16 speed_ability) 1172 { 1173 struct hclge_mac *mac = &hdev->hw.mac; 1174 1175 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1176 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1177 mac->supported); 1178 1179 hclge_convert_setting_sr(speed_ability, mac->supported); 1180 hclge_convert_setting_lr(speed_ability, mac->supported); 1181 hclge_convert_setting_cr(speed_ability, mac->supported); 1182 if (hnae3_dev_fec_supported(hdev)) 1183 hclge_convert_setting_fec(mac); 1184 1185 if (hnae3_dev_pause_supported(hdev)) 1186 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1187 1188 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported); 1189 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1190 } 1191 1192 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev, 1193 u16 speed_ability) 1194 { 1195 struct hclge_mac *mac = &hdev->hw.mac; 1196 1197 hclge_convert_setting_kr(speed_ability, mac->supported); 1198 if (hnae3_dev_fec_supported(hdev)) 1199 hclge_convert_setting_fec(mac); 1200 1201 if (hnae3_dev_pause_supported(hdev)) 1202 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1203 1204 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported); 1205 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1206 } 1207 1208 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev, 1209 u16 speed_ability) 1210 { 1211 unsigned long *supported = hdev->hw.mac.supported; 1212 1213 /* default to support all speed for GE port */ 1214 if (!speed_ability) 1215 speed_ability = HCLGE_SUPPORT_GE; 1216 1217 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1218 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1219 supported); 1220 1221 if (speed_ability & HCLGE_SUPPORT_100M_BIT) { 1222 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1223 supported); 1224 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1225 supported); 1226 } 1227 1228 if (speed_ability & HCLGE_SUPPORT_10M_BIT) { 1229 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported); 1230 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported); 1231 } 1232 1233 if (hnae3_dev_pause_supported(hdev)) { 1234 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1235 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 1236 } 1237 1238 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 1239 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 1240 } 1241 1242 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 1243 { 1244 u8 media_type = hdev->hw.mac.media_type; 1245 1246 if (media_type == HNAE3_MEDIA_TYPE_FIBER) 1247 hclge_parse_fiber_link_mode(hdev, speed_ability); 1248 else if (media_type == HNAE3_MEDIA_TYPE_COPPER) 1249 hclge_parse_copper_link_mode(hdev, speed_ability); 1250 else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE) 1251 hclge_parse_backplane_link_mode(hdev, speed_ability); 1252 } 1253 1254 static u32 hclge_get_max_speed(u16 speed_ability) 1255 { 1256 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1257 return HCLGE_MAC_SPEED_200G; 1258 1259 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1260 return HCLGE_MAC_SPEED_100G; 1261 1262 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1263 return HCLGE_MAC_SPEED_50G; 1264 1265 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1266 return HCLGE_MAC_SPEED_40G; 1267 1268 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1269 return HCLGE_MAC_SPEED_25G; 1270 1271 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1272 return HCLGE_MAC_SPEED_10G; 1273 1274 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1275 return HCLGE_MAC_SPEED_1G; 1276 1277 if (speed_ability & HCLGE_SUPPORT_100M_BIT) 1278 return HCLGE_MAC_SPEED_100M; 1279 1280 if (speed_ability & HCLGE_SUPPORT_10M_BIT) 1281 return HCLGE_MAC_SPEED_10M; 1282 1283 return HCLGE_MAC_SPEED_1G; 1284 } 1285 1286 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1287 { 1288 #define HCLGE_TX_SPARE_SIZE_UNIT 4096 1289 #define SPEED_ABILITY_EXT_SHIFT 8 1290 1291 struct hclge_cfg_param_cmd *req; 1292 u64 mac_addr_tmp_high; 1293 u16 speed_ability_ext; 1294 u64 mac_addr_tmp; 1295 unsigned int i; 1296 1297 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1298 1299 /* get the configuration */ 1300 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1301 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1302 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1303 HCLGE_CFG_TQP_DESC_N_M, 1304 HCLGE_CFG_TQP_DESC_N_S); 1305 1306 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1307 HCLGE_CFG_PHY_ADDR_M, 1308 HCLGE_CFG_PHY_ADDR_S); 1309 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1310 HCLGE_CFG_MEDIA_TP_M, 1311 HCLGE_CFG_MEDIA_TP_S); 1312 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1313 HCLGE_CFG_RX_BUF_LEN_M, 1314 HCLGE_CFG_RX_BUF_LEN_S); 1315 /* get mac_address */ 1316 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1317 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1318 HCLGE_CFG_MAC_ADDR_H_M, 1319 HCLGE_CFG_MAC_ADDR_H_S); 1320 1321 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1322 1323 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1324 HCLGE_CFG_DEFAULT_SPEED_M, 1325 HCLGE_CFG_DEFAULT_SPEED_S); 1326 cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1327 HCLGE_CFG_RSS_SIZE_M, 1328 HCLGE_CFG_RSS_SIZE_S); 1329 1330 for (i = 0; i < ETH_ALEN; i++) 1331 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1332 1333 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1334 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1335 1336 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1337 HCLGE_CFG_SPEED_ABILITY_M, 1338 HCLGE_CFG_SPEED_ABILITY_S); 1339 speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]), 1340 HCLGE_CFG_SPEED_ABILITY_EXT_M, 1341 HCLGE_CFG_SPEED_ABILITY_EXT_S); 1342 cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT; 1343 1344 cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]), 1345 HCLGE_CFG_VLAN_FLTR_CAP_M, 1346 HCLGE_CFG_VLAN_FLTR_CAP_S); 1347 1348 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]), 1349 HCLGE_CFG_UMV_TBL_SPACE_M, 1350 HCLGE_CFG_UMV_TBL_SPACE_S); 1351 1352 cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]), 1353 HCLGE_CFG_PF_RSS_SIZE_M, 1354 HCLGE_CFG_PF_RSS_SIZE_S); 1355 1356 /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a 1357 * power of 2, instead of reading out directly. This would 1358 * be more flexible for future changes and expansions. 1359 * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S, 1360 * it does not make sense if PF's field is 0. In this case, PF and VF 1361 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S. 1362 */ 1363 cfg->pf_rss_size_max = cfg->pf_rss_size_max ? 1364 1U << cfg->pf_rss_size_max : 1365 cfg->vf_rss_size_max; 1366 1367 /* The unit of the tx spare buffer size queried from configuration 1368 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is 1369 * needed here. 1370 */ 1371 cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]), 1372 HCLGE_CFG_TX_SPARE_BUF_SIZE_M, 1373 HCLGE_CFG_TX_SPARE_BUF_SIZE_S); 1374 cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT; 1375 } 1376 1377 /* hclge_get_cfg: query the static parameter from flash 1378 * @hdev: pointer to struct hclge_dev 1379 * @hcfg: the config structure to be getted 1380 */ 1381 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1382 { 1383 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1384 struct hclge_cfg_param_cmd *req; 1385 unsigned int i; 1386 int ret; 1387 1388 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1389 u32 offset = 0; 1390 1391 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1392 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1393 true); 1394 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1395 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1396 /* Len should be united by 4 bytes when send to hardware */ 1397 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1398 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1399 req->offset = cpu_to_le32(offset); 1400 } 1401 1402 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1403 if (ret) { 1404 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1405 return ret; 1406 } 1407 1408 hclge_parse_cfg(hcfg, desc); 1409 1410 return 0; 1411 } 1412 1413 static void hclge_set_default_dev_specs(struct hclge_dev *hdev) 1414 { 1415 #define HCLGE_MAX_NON_TSO_BD_NUM 8U 1416 1417 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1418 1419 ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1420 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1421 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1422 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE; 1423 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL; 1424 ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME; 1425 ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM; 1426 ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1427 } 1428 1429 static void hclge_parse_dev_specs(struct hclge_dev *hdev, 1430 struct hclge_desc *desc) 1431 { 1432 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1433 struct hclge_dev_specs_0_cmd *req0; 1434 struct hclge_dev_specs_1_cmd *req1; 1435 1436 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data; 1437 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data; 1438 1439 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 1440 ae_dev->dev_specs.rss_ind_tbl_size = 1441 le16_to_cpu(req0->rss_ind_tbl_size); 1442 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 1443 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 1444 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate); 1445 ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num); 1446 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 1447 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 1448 ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size); 1449 ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size); 1450 } 1451 1452 static void hclge_check_dev_specs(struct hclge_dev *hdev) 1453 { 1454 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 1455 1456 if (!dev_specs->max_non_tso_bd_num) 1457 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1458 if (!dev_specs->rss_ind_tbl_size) 1459 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1460 if (!dev_specs->rss_key_size) 1461 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1462 if (!dev_specs->max_tm_rate) 1463 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE; 1464 if (!dev_specs->max_qset_num) 1465 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM; 1466 if (!dev_specs->max_int_gl) 1467 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL; 1468 if (!dev_specs->max_frm_size) 1469 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME; 1470 if (!dev_specs->umv_size) 1471 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1472 } 1473 1474 static int hclge_query_mac_stats_num(struct hclge_dev *hdev) 1475 { 1476 u32 reg_num = 0; 1477 int ret; 1478 1479 ret = hclge_mac_query_reg_num(hdev, ®_num); 1480 if (ret && ret != -EOPNOTSUPP) 1481 return ret; 1482 1483 hdev->ae_dev->dev_specs.mac_stats_num = reg_num; 1484 return 0; 1485 } 1486 1487 static int hclge_query_dev_specs(struct hclge_dev *hdev) 1488 { 1489 struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM]; 1490 int ret; 1491 int i; 1492 1493 ret = hclge_query_mac_stats_num(hdev); 1494 if (ret) 1495 return ret; 1496 1497 /* set default specifications as devices lower than version V3 do not 1498 * support querying specifications from firmware. 1499 */ 1500 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 1501 hclge_set_default_dev_specs(hdev); 1502 return 0; 1503 } 1504 1505 for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1506 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, 1507 true); 1508 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 1509 } 1510 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 1511 1512 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM); 1513 if (ret) 1514 return ret; 1515 1516 hclge_parse_dev_specs(hdev, desc); 1517 hclge_check_dev_specs(hdev); 1518 1519 return 0; 1520 } 1521 1522 static int hclge_get_cap(struct hclge_dev *hdev) 1523 { 1524 int ret; 1525 1526 ret = hclge_query_function_status(hdev); 1527 if (ret) { 1528 dev_err(&hdev->pdev->dev, 1529 "query function status error %d.\n", ret); 1530 return ret; 1531 } 1532 1533 /* get pf resource */ 1534 return hclge_query_pf_resource(hdev); 1535 } 1536 1537 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev) 1538 { 1539 #define HCLGE_MIN_TX_DESC 64 1540 #define HCLGE_MIN_RX_DESC 64 1541 1542 if (!is_kdump_kernel()) 1543 return; 1544 1545 dev_info(&hdev->pdev->dev, 1546 "Running kdump kernel. Using minimal resources\n"); 1547 1548 /* minimal queue pairs equals to the number of vports */ 1549 hdev->num_tqps = hdev->num_req_vfs + 1; 1550 hdev->num_tx_desc = HCLGE_MIN_TX_DESC; 1551 hdev->num_rx_desc = HCLGE_MIN_RX_DESC; 1552 } 1553 1554 static void hclge_init_tc_config(struct hclge_dev *hdev) 1555 { 1556 unsigned int i; 1557 1558 if (hdev->tc_max > HNAE3_MAX_TC || 1559 hdev->tc_max < 1) { 1560 dev_warn(&hdev->pdev->dev, "TC num = %u.\n", 1561 hdev->tc_max); 1562 hdev->tc_max = 1; 1563 } 1564 1565 /* Dev does not support DCB */ 1566 if (!hnae3_dev_dcb_supported(hdev)) { 1567 hdev->tc_max = 1; 1568 hdev->pfc_max = 0; 1569 } else { 1570 hdev->pfc_max = hdev->tc_max; 1571 } 1572 1573 hdev->tm_info.num_tc = 1; 1574 1575 /* Currently not support uncontiuous tc */ 1576 for (i = 0; i < hdev->tm_info.num_tc; i++) 1577 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1578 1579 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1580 } 1581 1582 static int hclge_configure(struct hclge_dev *hdev) 1583 { 1584 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1585 struct hclge_cfg cfg; 1586 int ret; 1587 1588 ret = hclge_get_cfg(hdev, &cfg); 1589 if (ret) 1590 return ret; 1591 1592 hdev->base_tqp_pid = 0; 1593 hdev->vf_rss_size_max = cfg.vf_rss_size_max; 1594 hdev->pf_rss_size_max = cfg.pf_rss_size_max; 1595 hdev->rx_buf_len = cfg.rx_buf_len; 1596 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1597 hdev->hw.mac.media_type = cfg.media_type; 1598 hdev->hw.mac.phy_addr = cfg.phy_addr; 1599 hdev->num_tx_desc = cfg.tqp_desc_num; 1600 hdev->num_rx_desc = cfg.tqp_desc_num; 1601 hdev->tm_info.num_pg = 1; 1602 hdev->tc_max = cfg.tc_num; 1603 hdev->tm_info.hw_pfc_map = 0; 1604 if (cfg.umv_space) 1605 hdev->wanted_umv_size = cfg.umv_space; 1606 else 1607 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size; 1608 hdev->tx_spare_buf_size = cfg.tx_spare_buf_size; 1609 hdev->gro_en = true; 1610 if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF) 1611 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 1612 1613 if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 1614 hdev->fd_en = true; 1615 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 1616 } 1617 1618 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1619 if (ret) { 1620 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n", 1621 cfg.default_speed, ret); 1622 return ret; 1623 } 1624 1625 hclge_parse_link_mode(hdev, cfg.speed_ability); 1626 1627 hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability); 1628 1629 hclge_init_tc_config(hdev); 1630 hclge_init_kdump_kernel_config(hdev); 1631 1632 return ret; 1633 } 1634 1635 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min, 1636 u16 tso_mss_max) 1637 { 1638 struct hclge_cfg_tso_status_cmd *req; 1639 struct hclge_desc desc; 1640 1641 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1642 1643 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1644 req->tso_mss_min = cpu_to_le16(tso_mss_min); 1645 req->tso_mss_max = cpu_to_le16(tso_mss_max); 1646 1647 return hclge_cmd_send(&hdev->hw, &desc, 1); 1648 } 1649 1650 static int hclge_config_gro(struct hclge_dev *hdev) 1651 { 1652 struct hclge_cfg_gro_status_cmd *req; 1653 struct hclge_desc desc; 1654 int ret; 1655 1656 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 1657 return 0; 1658 1659 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false); 1660 req = (struct hclge_cfg_gro_status_cmd *)desc.data; 1661 1662 req->gro_en = hdev->gro_en ? 1 : 0; 1663 1664 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1665 if (ret) 1666 dev_err(&hdev->pdev->dev, 1667 "GRO hardware config cmd failed, ret = %d\n", ret); 1668 1669 return ret; 1670 } 1671 1672 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1673 { 1674 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1675 struct hclge_comm_tqp *tqp; 1676 int i; 1677 1678 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1679 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 1680 if (!hdev->htqp) 1681 return -ENOMEM; 1682 1683 tqp = hdev->htqp; 1684 1685 for (i = 0; i < hdev->num_tqps; i++) { 1686 tqp->dev = &hdev->pdev->dev; 1687 tqp->index = i; 1688 1689 tqp->q.ae_algo = &ae_algo; 1690 tqp->q.buf_size = hdev->rx_buf_len; 1691 tqp->q.tx_desc_num = hdev->num_tx_desc; 1692 tqp->q.rx_desc_num = hdev->num_rx_desc; 1693 1694 /* need an extended offset to configure queues >= 1695 * HCLGE_TQP_MAX_SIZE_DEV_V2 1696 */ 1697 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2) 1698 tqp->q.io_base = hdev->hw.hw.io_base + 1699 HCLGE_TQP_REG_OFFSET + 1700 i * HCLGE_TQP_REG_SIZE; 1701 else 1702 tqp->q.io_base = hdev->hw.hw.io_base + 1703 HCLGE_TQP_REG_OFFSET + 1704 HCLGE_TQP_EXT_REG_OFFSET + 1705 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) * 1706 HCLGE_TQP_REG_SIZE; 1707 1708 /* when device supports tx push and has device memory, 1709 * the queue can execute push mode or doorbell mode on 1710 * device memory. 1711 */ 1712 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 1713 tqp->q.mem_base = hdev->hw.hw.mem_base + 1714 HCLGE_TQP_MEM_OFFSET(hdev, i); 1715 1716 tqp++; 1717 } 1718 1719 return 0; 1720 } 1721 1722 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1723 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1724 { 1725 struct hclge_tqp_map_cmd *req; 1726 struct hclge_desc desc; 1727 int ret; 1728 1729 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1730 1731 req = (struct hclge_tqp_map_cmd *)desc.data; 1732 req->tqp_id = cpu_to_le16(tqp_pid); 1733 req->tqp_vf = func_id; 1734 req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B; 1735 if (!is_pf) 1736 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B; 1737 req->tqp_vid = cpu_to_le16(tqp_vid); 1738 1739 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1740 if (ret) 1741 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1742 1743 return ret; 1744 } 1745 1746 static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) 1747 { 1748 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1749 struct hclge_dev *hdev = vport->back; 1750 int i, alloced; 1751 1752 for (i = 0, alloced = 0; i < hdev->num_tqps && 1753 alloced < num_tqps; i++) { 1754 if (!hdev->htqp[i].alloced) { 1755 hdev->htqp[i].q.handle = &vport->nic; 1756 hdev->htqp[i].q.tqp_index = alloced; 1757 hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc; 1758 hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc; 1759 kinfo->tqp[alloced] = &hdev->htqp[i].q; 1760 hdev->htqp[i].alloced = true; 1761 alloced++; 1762 } 1763 } 1764 vport->alloc_tqps = alloced; 1765 kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max, 1766 vport->alloc_tqps / hdev->tm_info.num_tc); 1767 1768 /* ensure one to one mapping between irq and queue at default */ 1769 kinfo->rss_size = min_t(u16, kinfo->rss_size, 1770 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc); 1771 1772 return 0; 1773 } 1774 1775 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps, 1776 u16 num_tx_desc, u16 num_rx_desc) 1777 1778 { 1779 struct hnae3_handle *nic = &vport->nic; 1780 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1781 struct hclge_dev *hdev = vport->back; 1782 int ret; 1783 1784 kinfo->num_tx_desc = num_tx_desc; 1785 kinfo->num_rx_desc = num_rx_desc; 1786 1787 kinfo->rx_buf_len = hdev->rx_buf_len; 1788 kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size; 1789 1790 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps, 1791 sizeof(struct hnae3_queue *), GFP_KERNEL); 1792 if (!kinfo->tqp) 1793 return -ENOMEM; 1794 1795 ret = hclge_assign_tqp(vport, num_tqps); 1796 if (ret) 1797 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1798 1799 return ret; 1800 } 1801 1802 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1803 struct hclge_vport *vport) 1804 { 1805 struct hnae3_handle *nic = &vport->nic; 1806 struct hnae3_knic_private_info *kinfo; 1807 u16 i; 1808 1809 kinfo = &nic->kinfo; 1810 for (i = 0; i < vport->alloc_tqps; i++) { 1811 struct hclge_comm_tqp *q = 1812 container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); 1813 bool is_pf; 1814 int ret; 1815 1816 is_pf = !(vport->vport_id); 1817 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1818 i, is_pf); 1819 if (ret) 1820 return ret; 1821 } 1822 1823 return 0; 1824 } 1825 1826 static int hclge_map_tqp(struct hclge_dev *hdev) 1827 { 1828 struct hclge_vport *vport = hdev->vport; 1829 u16 i, num_vport; 1830 1831 num_vport = hdev->num_req_vfs + 1; 1832 for (i = 0; i < num_vport; i++) { 1833 int ret; 1834 1835 ret = hclge_map_tqp_to_vport(hdev, vport); 1836 if (ret) 1837 return ret; 1838 1839 vport++; 1840 } 1841 1842 return 0; 1843 } 1844 1845 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1846 { 1847 struct hnae3_handle *nic = &vport->nic; 1848 struct hclge_dev *hdev = vport->back; 1849 int ret; 1850 1851 nic->pdev = hdev->pdev; 1852 nic->ae_algo = &ae_algo; 1853 nic->numa_node_mask = hdev->numa_node_mask; 1854 nic->kinfo.io_base = hdev->hw.hw.io_base; 1855 1856 ret = hclge_knic_setup(vport, num_tqps, 1857 hdev->num_tx_desc, hdev->num_rx_desc); 1858 if (ret) 1859 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret); 1860 1861 return ret; 1862 } 1863 1864 static int hclge_alloc_vport(struct hclge_dev *hdev) 1865 { 1866 struct pci_dev *pdev = hdev->pdev; 1867 struct hclge_vport *vport; 1868 u32 tqp_main_vport; 1869 u32 tqp_per_vport; 1870 int num_vport, i; 1871 int ret; 1872 1873 /* We need to alloc a vport for main NIC of PF */ 1874 num_vport = hdev->num_req_vfs + 1; 1875 1876 if (hdev->num_tqps < num_vport) { 1877 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)", 1878 hdev->num_tqps, num_vport); 1879 return -EINVAL; 1880 } 1881 1882 /* Alloc the same number of TQPs for every vport */ 1883 tqp_per_vport = hdev->num_tqps / num_vport; 1884 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1885 1886 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1887 GFP_KERNEL); 1888 if (!vport) 1889 return -ENOMEM; 1890 1891 hdev->vport = vport; 1892 hdev->num_alloc_vport = num_vport; 1893 1894 if (IS_ENABLED(CONFIG_PCI_IOV)) 1895 hdev->num_alloc_vfs = hdev->num_req_vfs; 1896 1897 for (i = 0; i < num_vport; i++) { 1898 vport->back = hdev; 1899 vport->vport_id = i; 1900 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO; 1901 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 1902 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE; 1903 vport->port_base_vlan_cfg.tbl_sta = true; 1904 vport->rxvlan_cfg.rx_vlan_offload_en = true; 1905 vport->req_vlan_fltr_en = true; 1906 INIT_LIST_HEAD(&vport->vlan_list); 1907 INIT_LIST_HEAD(&vport->uc_mac_list); 1908 INIT_LIST_HEAD(&vport->mc_mac_list); 1909 spin_lock_init(&vport->mac_list_lock); 1910 1911 if (i == 0) 1912 ret = hclge_vport_setup(vport, tqp_main_vport); 1913 else 1914 ret = hclge_vport_setup(vport, tqp_per_vport); 1915 if (ret) { 1916 dev_err(&pdev->dev, 1917 "vport setup failed for vport %d, %d\n", 1918 i, ret); 1919 return ret; 1920 } 1921 1922 vport++; 1923 } 1924 1925 return 0; 1926 } 1927 1928 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1929 struct hclge_pkt_buf_alloc *buf_alloc) 1930 { 1931 /* TX buffer size is unit by 128 byte */ 1932 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1933 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1934 struct hclge_tx_buff_alloc_cmd *req; 1935 struct hclge_desc desc; 1936 int ret; 1937 u8 i; 1938 1939 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1940 1941 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1942 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1943 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1944 1945 req->tx_pkt_buff[i] = 1946 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1947 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1948 } 1949 1950 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1951 if (ret) 1952 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1953 ret); 1954 1955 return ret; 1956 } 1957 1958 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1959 struct hclge_pkt_buf_alloc *buf_alloc) 1960 { 1961 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1962 1963 if (ret) 1964 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1965 1966 return ret; 1967 } 1968 1969 static u32 hclge_get_tc_num(struct hclge_dev *hdev) 1970 { 1971 unsigned int i; 1972 u32 cnt = 0; 1973 1974 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1975 if (hdev->hw_tc_map & BIT(i)) 1976 cnt++; 1977 return cnt; 1978 } 1979 1980 /* Get the number of pfc enabled TCs, which have private buffer */ 1981 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1982 struct hclge_pkt_buf_alloc *buf_alloc) 1983 { 1984 struct hclge_priv_buf *priv; 1985 unsigned int i; 1986 int cnt = 0; 1987 1988 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1989 priv = &buf_alloc->priv_buf[i]; 1990 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1991 priv->enable) 1992 cnt++; 1993 } 1994 1995 return cnt; 1996 } 1997 1998 /* Get the number of pfc disabled TCs, which have private buffer */ 1999 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 2000 struct hclge_pkt_buf_alloc *buf_alloc) 2001 { 2002 struct hclge_priv_buf *priv; 2003 unsigned int i; 2004 int cnt = 0; 2005 2006 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2007 priv = &buf_alloc->priv_buf[i]; 2008 if (hdev->hw_tc_map & BIT(i) && 2009 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 2010 priv->enable) 2011 cnt++; 2012 } 2013 2014 return cnt; 2015 } 2016 2017 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 2018 { 2019 struct hclge_priv_buf *priv; 2020 u32 rx_priv = 0; 2021 int i; 2022 2023 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2024 priv = &buf_alloc->priv_buf[i]; 2025 if (priv->enable) 2026 rx_priv += priv->buf_size; 2027 } 2028 return rx_priv; 2029 } 2030 2031 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 2032 { 2033 u32 i, total_tx_size = 0; 2034 2035 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 2036 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 2037 2038 return total_tx_size; 2039 } 2040 2041 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 2042 struct hclge_pkt_buf_alloc *buf_alloc, 2043 u32 rx_all) 2044 { 2045 u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 2046 u32 tc_num = hclge_get_tc_num(hdev); 2047 u32 shared_buf, aligned_mps; 2048 u32 rx_priv; 2049 int i; 2050 2051 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2052 2053 if (hnae3_dev_dcb_supported(hdev)) 2054 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps + 2055 hdev->dv_buf_size; 2056 else 2057 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF 2058 + hdev->dv_buf_size; 2059 2060 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 2061 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc), 2062 HCLGE_BUF_SIZE_UNIT); 2063 2064 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 2065 if (rx_all < rx_priv + shared_std) 2066 return false; 2067 2068 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT); 2069 buf_alloc->s_buf.buf_size = shared_buf; 2070 if (hnae3_dev_dcb_supported(hdev)) { 2071 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size; 2072 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 2073 - roundup(aligned_mps / HCLGE_BUF_DIV_BY, 2074 HCLGE_BUF_SIZE_UNIT); 2075 } else { 2076 buf_alloc->s_buf.self.high = aligned_mps + 2077 HCLGE_NON_DCB_ADDITIONAL_BUF; 2078 buf_alloc->s_buf.self.low = aligned_mps; 2079 } 2080 2081 if (hnae3_dev_dcb_supported(hdev)) { 2082 hi_thrd = shared_buf - hdev->dv_buf_size; 2083 2084 if (tc_num <= NEED_RESERVE_TC_NUM) 2085 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 2086 / BUF_MAX_PERCENT; 2087 2088 if (tc_num) 2089 hi_thrd = hi_thrd / tc_num; 2090 2091 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps); 2092 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT); 2093 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY; 2094 } else { 2095 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF; 2096 lo_thrd = aligned_mps; 2097 } 2098 2099 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2100 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 2101 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 2102 } 2103 2104 return true; 2105 } 2106 2107 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 2108 struct hclge_pkt_buf_alloc *buf_alloc) 2109 { 2110 u32 i, total_size; 2111 2112 total_size = hdev->pkt_buf_size; 2113 2114 /* alloc tx buffer for all enabled tc */ 2115 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2116 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2117 2118 if (hdev->hw_tc_map & BIT(i)) { 2119 if (total_size < hdev->tx_buf_size) 2120 return -ENOMEM; 2121 2122 priv->tx_buf_size = hdev->tx_buf_size; 2123 } else { 2124 priv->tx_buf_size = 0; 2125 } 2126 2127 total_size -= priv->tx_buf_size; 2128 } 2129 2130 return 0; 2131 } 2132 2133 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max, 2134 struct hclge_pkt_buf_alloc *buf_alloc) 2135 { 2136 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2137 u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2138 unsigned int i; 2139 2140 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2141 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2142 2143 priv->enable = 0; 2144 priv->wl.low = 0; 2145 priv->wl.high = 0; 2146 priv->buf_size = 0; 2147 2148 if (!(hdev->hw_tc_map & BIT(i))) 2149 continue; 2150 2151 priv->enable = 1; 2152 2153 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 2154 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT; 2155 priv->wl.high = roundup(priv->wl.low + aligned_mps, 2156 HCLGE_BUF_SIZE_UNIT); 2157 } else { 2158 priv->wl.low = 0; 2159 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) : 2160 aligned_mps; 2161 } 2162 2163 priv->buf_size = priv->wl.high + hdev->dv_buf_size; 2164 } 2165 2166 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2167 } 2168 2169 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev, 2170 struct hclge_pkt_buf_alloc *buf_alloc) 2171 { 2172 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2173 int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 2174 int i; 2175 2176 /* let the last to be cleared first */ 2177 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2178 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2179 unsigned int mask = BIT((unsigned int)i); 2180 2181 if (hdev->hw_tc_map & mask && 2182 !(hdev->tm_info.hw_pfc_map & mask)) { 2183 /* Clear the no pfc TC private buffer */ 2184 priv->wl.low = 0; 2185 priv->wl.high = 0; 2186 priv->buf_size = 0; 2187 priv->enable = 0; 2188 no_pfc_priv_num--; 2189 } 2190 2191 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2192 no_pfc_priv_num == 0) 2193 break; 2194 } 2195 2196 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2197 } 2198 2199 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev, 2200 struct hclge_pkt_buf_alloc *buf_alloc) 2201 { 2202 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2203 int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 2204 int i; 2205 2206 /* let the last to be cleared first */ 2207 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2208 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2209 unsigned int mask = BIT((unsigned int)i); 2210 2211 if (hdev->hw_tc_map & mask && 2212 hdev->tm_info.hw_pfc_map & mask) { 2213 /* Reduce the number of pfc TC with private buffer */ 2214 priv->wl.low = 0; 2215 priv->enable = 0; 2216 priv->wl.high = 0; 2217 priv->buf_size = 0; 2218 pfc_priv_num--; 2219 } 2220 2221 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2222 pfc_priv_num == 0) 2223 break; 2224 } 2225 2226 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2227 } 2228 2229 static int hclge_only_alloc_priv_buff(struct hclge_dev *hdev, 2230 struct hclge_pkt_buf_alloc *buf_alloc) 2231 { 2232 #define COMPENSATE_BUFFER 0x3C00 2233 #define COMPENSATE_HALF_MPS_NUM 5 2234 #define PRIV_WL_GAP 0x1800 2235 2236 u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2237 u32 tc_num = hclge_get_tc_num(hdev); 2238 u32 half_mps = hdev->mps >> 1; 2239 u32 min_rx_priv; 2240 unsigned int i; 2241 2242 if (tc_num) 2243 rx_priv = rx_priv / tc_num; 2244 2245 if (tc_num <= NEED_RESERVE_TC_NUM) 2246 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 2247 2248 min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER + 2249 COMPENSATE_HALF_MPS_NUM * half_mps; 2250 min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT); 2251 rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT); 2252 if (rx_priv < min_rx_priv) 2253 return false; 2254 2255 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2256 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2257 2258 priv->enable = 0; 2259 priv->wl.low = 0; 2260 priv->wl.high = 0; 2261 priv->buf_size = 0; 2262 2263 if (!(hdev->hw_tc_map & BIT(i))) 2264 continue; 2265 2266 priv->enable = 1; 2267 priv->buf_size = rx_priv; 2268 priv->wl.high = rx_priv - hdev->dv_buf_size; 2269 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 2270 } 2271 2272 buf_alloc->s_buf.buf_size = 0; 2273 2274 return true; 2275 } 2276 2277 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 2278 * @hdev: pointer to struct hclge_dev 2279 * @buf_alloc: pointer to buffer calculation data 2280 * @return: 0: calculate successful, negative: fail 2281 */ 2282 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 2283 struct hclge_pkt_buf_alloc *buf_alloc) 2284 { 2285 /* When DCB is not supported, rx private buffer is not allocated. */ 2286 if (!hnae3_dev_dcb_supported(hdev)) { 2287 u32 rx_all = hdev->pkt_buf_size; 2288 2289 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 2290 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 2291 return -ENOMEM; 2292 2293 return 0; 2294 } 2295 2296 if (hclge_only_alloc_priv_buff(hdev, buf_alloc)) 2297 return 0; 2298 2299 if (hclge_rx_buf_calc_all(hdev, true, buf_alloc)) 2300 return 0; 2301 2302 /* try to decrease the buffer size */ 2303 if (hclge_rx_buf_calc_all(hdev, false, buf_alloc)) 2304 return 0; 2305 2306 if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc)) 2307 return 0; 2308 2309 if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc)) 2310 return 0; 2311 2312 return -ENOMEM; 2313 } 2314 2315 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 2316 struct hclge_pkt_buf_alloc *buf_alloc) 2317 { 2318 struct hclge_rx_priv_buff_cmd *req; 2319 struct hclge_desc desc; 2320 int ret; 2321 int i; 2322 2323 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 2324 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 2325 2326 /* Alloc private buffer TCs */ 2327 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2328 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2329 2330 req->buf_num[i] = 2331 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 2332 req->buf_num[i] |= 2333 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 2334 } 2335 2336 req->shared_buf = 2337 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 2338 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 2339 2340 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2341 if (ret) 2342 dev_err(&hdev->pdev->dev, 2343 "rx private buffer alloc cmd failed %d\n", ret); 2344 2345 return ret; 2346 } 2347 2348 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 2349 struct hclge_pkt_buf_alloc *buf_alloc) 2350 { 2351 struct hclge_rx_priv_wl_buf *req; 2352 struct hclge_priv_buf *priv; 2353 struct hclge_desc desc[2]; 2354 int i, j; 2355 int ret; 2356 2357 for (i = 0; i < 2; i++) { 2358 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 2359 false); 2360 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 2361 2362 /* The first descriptor set the NEXT bit to 1 */ 2363 if (i == 0) 2364 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2365 else 2366 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2367 2368 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2369 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 2370 2371 priv = &buf_alloc->priv_buf[idx]; 2372 req->tc_wl[j].high = 2373 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 2374 req->tc_wl[j].high |= 2375 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2376 req->tc_wl[j].low = 2377 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 2378 req->tc_wl[j].low |= 2379 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2380 } 2381 } 2382 2383 /* Send 2 descriptor at one time */ 2384 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2385 if (ret) 2386 dev_err(&hdev->pdev->dev, 2387 "rx private waterline config cmd failed %d\n", 2388 ret); 2389 return ret; 2390 } 2391 2392 static int hclge_common_thrd_config(struct hclge_dev *hdev, 2393 struct hclge_pkt_buf_alloc *buf_alloc) 2394 { 2395 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 2396 struct hclge_rx_com_thrd *req; 2397 struct hclge_desc desc[2]; 2398 struct hclge_tc_thrd *tc; 2399 int i, j; 2400 int ret; 2401 2402 for (i = 0; i < 2; i++) { 2403 hclge_cmd_setup_basic_desc(&desc[i], 2404 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 2405 req = (struct hclge_rx_com_thrd *)&desc[i].data; 2406 2407 /* The first descriptor set the NEXT bit to 1 */ 2408 if (i == 0) 2409 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2410 else 2411 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2412 2413 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2414 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 2415 2416 req->com_thrd[j].high = 2417 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 2418 req->com_thrd[j].high |= 2419 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2420 req->com_thrd[j].low = 2421 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 2422 req->com_thrd[j].low |= 2423 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2424 } 2425 } 2426 2427 /* Send 2 descriptors at one time */ 2428 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2429 if (ret) 2430 dev_err(&hdev->pdev->dev, 2431 "common threshold config cmd failed %d\n", ret); 2432 return ret; 2433 } 2434 2435 static int hclge_common_wl_config(struct hclge_dev *hdev, 2436 struct hclge_pkt_buf_alloc *buf_alloc) 2437 { 2438 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 2439 struct hclge_rx_com_wl *req; 2440 struct hclge_desc desc; 2441 int ret; 2442 2443 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 2444 2445 req = (struct hclge_rx_com_wl *)desc.data; 2446 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 2447 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2448 2449 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 2450 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2451 2452 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2453 if (ret) 2454 dev_err(&hdev->pdev->dev, 2455 "common waterline config cmd failed %d\n", ret); 2456 2457 return ret; 2458 } 2459 2460 int hclge_buffer_alloc(struct hclge_dev *hdev) 2461 { 2462 struct hclge_pkt_buf_alloc *pkt_buf; 2463 int ret; 2464 2465 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 2466 if (!pkt_buf) 2467 return -ENOMEM; 2468 2469 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 2470 if (ret) { 2471 dev_err(&hdev->pdev->dev, 2472 "could not calc tx buffer size for all TCs %d\n", ret); 2473 goto out; 2474 } 2475 2476 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 2477 if (ret) { 2478 dev_err(&hdev->pdev->dev, 2479 "could not alloc tx buffers %d\n", ret); 2480 goto out; 2481 } 2482 2483 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 2484 if (ret) { 2485 dev_err(&hdev->pdev->dev, 2486 "could not calc rx priv buffer size for all TCs %d\n", 2487 ret); 2488 goto out; 2489 } 2490 2491 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 2492 if (ret) { 2493 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 2494 ret); 2495 goto out; 2496 } 2497 2498 if (hnae3_dev_dcb_supported(hdev)) { 2499 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2500 if (ret) { 2501 dev_err(&hdev->pdev->dev, 2502 "could not configure rx private waterline %d\n", 2503 ret); 2504 goto out; 2505 } 2506 2507 ret = hclge_common_thrd_config(hdev, pkt_buf); 2508 if (ret) { 2509 dev_err(&hdev->pdev->dev, 2510 "could not configure common threshold %d\n", 2511 ret); 2512 goto out; 2513 } 2514 } 2515 2516 ret = hclge_common_wl_config(hdev, pkt_buf); 2517 if (ret) 2518 dev_err(&hdev->pdev->dev, 2519 "could not configure common waterline %d\n", ret); 2520 2521 out: 2522 kfree(pkt_buf); 2523 return ret; 2524 } 2525 2526 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2527 { 2528 struct hnae3_handle *roce = &vport->roce; 2529 struct hnae3_handle *nic = &vport->nic; 2530 struct hclge_dev *hdev = vport->back; 2531 2532 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2533 2534 if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi) 2535 return -EINVAL; 2536 2537 roce->rinfo.base_vector = hdev->num_nic_msi; 2538 2539 roce->rinfo.netdev = nic->kinfo.netdev; 2540 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2541 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2542 2543 roce->pdev = nic->pdev; 2544 roce->ae_algo = nic->ae_algo; 2545 roce->numa_node_mask = nic->numa_node_mask; 2546 2547 return 0; 2548 } 2549 2550 static int hclge_init_msi(struct hclge_dev *hdev) 2551 { 2552 struct pci_dev *pdev = hdev->pdev; 2553 int vectors; 2554 int i; 2555 2556 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2557 hdev->num_msi, 2558 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2559 if (vectors < 0) { 2560 dev_err(&pdev->dev, 2561 "failed(%d) to allocate MSI/MSI-X vectors\n", 2562 vectors); 2563 return vectors; 2564 } 2565 if (vectors < hdev->num_msi) 2566 dev_warn(&hdev->pdev->dev, 2567 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2568 hdev->num_msi, vectors); 2569 2570 hdev->num_msi = vectors; 2571 hdev->num_msi_left = vectors; 2572 2573 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2574 sizeof(u16), GFP_KERNEL); 2575 if (!hdev->vector_status) { 2576 pci_free_irq_vectors(pdev); 2577 return -ENOMEM; 2578 } 2579 2580 for (i = 0; i < hdev->num_msi; i++) 2581 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2582 2583 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2584 sizeof(int), GFP_KERNEL); 2585 if (!hdev->vector_irq) { 2586 pci_free_irq_vectors(pdev); 2587 return -ENOMEM; 2588 } 2589 2590 return 0; 2591 } 2592 2593 static u8 hclge_check_speed_dup(u8 duplex, int speed) 2594 { 2595 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 2596 duplex = HCLGE_MAC_FULL; 2597 2598 return duplex; 2599 } 2600 2601 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = { 2602 {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M}, 2603 {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M}, 2604 {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G}, 2605 {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G}, 2606 {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G}, 2607 {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G}, 2608 {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G}, 2609 {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G}, 2610 {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G}, 2611 }; 2612 2613 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw) 2614 { 2615 u16 i; 2616 2617 for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) { 2618 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) { 2619 *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw; 2620 return 0; 2621 } 2622 } 2623 2624 return -EINVAL; 2625 } 2626 2627 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 2628 u8 duplex, u8 lane_num) 2629 { 2630 struct hclge_config_mac_speed_dup_cmd *req; 2631 struct hclge_desc desc; 2632 u32 speed_fw; 2633 int ret; 2634 2635 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2636 2637 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2638 2639 if (duplex) 2640 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1); 2641 2642 ret = hclge_convert_to_fw_speed(speed, &speed_fw); 2643 if (ret) { 2644 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2645 return ret; 2646 } 2647 2648 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S, 2649 speed_fw); 2650 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2651 1); 2652 req->lane_num = lane_num; 2653 2654 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2655 if (ret) { 2656 dev_err(&hdev->pdev->dev, 2657 "mac speed/duplex config cmd failed %d.\n", ret); 2658 return ret; 2659 } 2660 2661 return 0; 2662 } 2663 2664 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num) 2665 { 2666 struct hclge_mac *mac = &hdev->hw.mac; 2667 int ret; 2668 2669 duplex = hclge_check_speed_dup(duplex, speed); 2670 if (!mac->support_autoneg && mac->speed == speed && 2671 mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0)) 2672 return 0; 2673 2674 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num); 2675 if (ret) 2676 return ret; 2677 2678 hdev->hw.mac.speed = speed; 2679 hdev->hw.mac.duplex = duplex; 2680 if (!lane_num) 2681 hdev->hw.mac.lane_num = lane_num; 2682 2683 return 0; 2684 } 2685 2686 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2687 u8 duplex, u8 lane_num) 2688 { 2689 struct hclge_vport *vport = hclge_get_vport(handle); 2690 struct hclge_dev *hdev = vport->back; 2691 2692 return hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num); 2693 } 2694 2695 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2696 { 2697 struct hclge_config_auto_neg_cmd *req; 2698 struct hclge_desc desc; 2699 u32 flag = 0; 2700 int ret; 2701 2702 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2703 2704 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2705 if (enable) 2706 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U); 2707 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2708 2709 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2710 if (ret) 2711 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2712 ret); 2713 2714 return ret; 2715 } 2716 2717 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2718 { 2719 struct hclge_vport *vport = hclge_get_vport(handle); 2720 struct hclge_dev *hdev = vport->back; 2721 2722 if (!hdev->hw.mac.support_autoneg) { 2723 if (enable) { 2724 dev_err(&hdev->pdev->dev, 2725 "autoneg is not supported by current port\n"); 2726 return -EOPNOTSUPP; 2727 } else { 2728 return 0; 2729 } 2730 } 2731 2732 return hclge_set_autoneg_en(hdev, enable); 2733 } 2734 2735 static int hclge_get_autoneg(struct hnae3_handle *handle) 2736 { 2737 struct hclge_vport *vport = hclge_get_vport(handle); 2738 struct hclge_dev *hdev = vport->back; 2739 struct phy_device *phydev = hdev->hw.mac.phydev; 2740 2741 if (phydev) 2742 return phydev->autoneg; 2743 2744 return hdev->hw.mac.autoneg; 2745 } 2746 2747 static int hclge_restart_autoneg(struct hnae3_handle *handle) 2748 { 2749 struct hclge_vport *vport = hclge_get_vport(handle); 2750 struct hclge_dev *hdev = vport->back; 2751 int ret; 2752 2753 dev_dbg(&hdev->pdev->dev, "restart autoneg\n"); 2754 2755 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2756 if (ret) 2757 return ret; 2758 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2759 } 2760 2761 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt) 2762 { 2763 struct hclge_vport *vport = hclge_get_vport(handle); 2764 struct hclge_dev *hdev = vport->back; 2765 2766 if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) 2767 return hclge_set_autoneg_en(hdev, !halt); 2768 2769 return 0; 2770 } 2771 2772 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev, 2773 struct hclge_desc *desc, u32 desc_len) 2774 { 2775 u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2; 2776 u32 desc_index = 0; 2777 u32 data_index = 0; 2778 u32 i; 2779 2780 for (i = 0; i < lane_size; i++) { 2781 if (data_index >= HCLGE_DESC_DATA_LEN) { 2782 desc_index++; 2783 data_index = 0; 2784 } 2785 2786 if (desc_index >= desc_len) 2787 return; 2788 2789 hdev->fec_stats.per_lanes[i] += 2790 le32_to_cpu(desc[desc_index].data[data_index]); 2791 data_index++; 2792 } 2793 } 2794 2795 static void hclge_parse_fec_stats(struct hclge_dev *hdev, 2796 struct hclge_desc *desc, u32 desc_len) 2797 { 2798 struct hclge_query_fec_stats_cmd *req; 2799 2800 req = (struct hclge_query_fec_stats_cmd *)desc[0].data; 2801 2802 hdev->fec_stats.base_r_lane_num = req->base_r_lane_num; 2803 hdev->fec_stats.rs_corr_blocks += 2804 le32_to_cpu(req->rs_fec_corr_blocks); 2805 hdev->fec_stats.rs_uncorr_blocks += 2806 le32_to_cpu(req->rs_fec_uncorr_blocks); 2807 hdev->fec_stats.rs_error_blocks += 2808 le32_to_cpu(req->rs_fec_error_blocks); 2809 hdev->fec_stats.base_r_corr_blocks += 2810 le32_to_cpu(req->base_r_fec_corr_blocks); 2811 hdev->fec_stats.base_r_uncorr_blocks += 2812 le32_to_cpu(req->base_r_fec_uncorr_blocks); 2813 2814 hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1); 2815 } 2816 2817 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev) 2818 { 2819 struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM]; 2820 int ret; 2821 u32 i; 2822 2823 for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) { 2824 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS, 2825 true); 2826 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1)) 2827 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2828 } 2829 2830 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM); 2831 if (ret) 2832 return ret; 2833 2834 hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM); 2835 2836 return 0; 2837 } 2838 2839 static void hclge_update_fec_stats(struct hclge_dev *hdev) 2840 { 2841 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2842 int ret; 2843 2844 if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || 2845 test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state)) 2846 return; 2847 2848 ret = hclge_update_fec_stats_hw(hdev); 2849 if (ret) 2850 dev_err(&hdev->pdev->dev, 2851 "failed to update fec stats, ret = %d\n", ret); 2852 2853 clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state); 2854 } 2855 2856 static void hclge_get_fec_stats_total(struct hclge_dev *hdev, 2857 struct ethtool_fec_stats *fec_stats) 2858 { 2859 fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks; 2860 fec_stats->uncorrectable_blocks.total = 2861 hdev->fec_stats.rs_uncorr_blocks; 2862 } 2863 2864 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev, 2865 struct ethtool_fec_stats *fec_stats) 2866 { 2867 u32 i; 2868 2869 if (hdev->fec_stats.base_r_lane_num == 0 || 2870 hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) { 2871 dev_err(&hdev->pdev->dev, 2872 "fec stats lane number(%llu) is invalid\n", 2873 hdev->fec_stats.base_r_lane_num); 2874 return; 2875 } 2876 2877 for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) { 2878 fec_stats->corrected_blocks.lanes[i] = 2879 hdev->fec_stats.base_r_corr_per_lanes[i]; 2880 fec_stats->uncorrectable_blocks.lanes[i] = 2881 hdev->fec_stats.base_r_uncorr_per_lanes[i]; 2882 } 2883 } 2884 2885 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev, 2886 struct ethtool_fec_stats *fec_stats) 2887 { 2888 u32 fec_mode = hdev->hw.mac.fec_mode; 2889 2890 switch (fec_mode) { 2891 case BIT(HNAE3_FEC_RS): 2892 case BIT(HNAE3_FEC_LLRS): 2893 hclge_get_fec_stats_total(hdev, fec_stats); 2894 break; 2895 case BIT(HNAE3_FEC_BASER): 2896 hclge_get_fec_stats_lanes(hdev, fec_stats); 2897 break; 2898 default: 2899 dev_err(&hdev->pdev->dev, 2900 "fec stats is not supported by current fec mode(0x%x)\n", 2901 fec_mode); 2902 break; 2903 } 2904 } 2905 2906 static void hclge_get_fec_stats(struct hnae3_handle *handle, 2907 struct ethtool_fec_stats *fec_stats) 2908 { 2909 struct hclge_vport *vport = hclge_get_vport(handle); 2910 struct hclge_dev *hdev = vport->back; 2911 u32 fec_mode = hdev->hw.mac.fec_mode; 2912 2913 if (fec_mode == BIT(HNAE3_FEC_NONE) || 2914 fec_mode == BIT(HNAE3_FEC_AUTO) || 2915 fec_mode == BIT(HNAE3_FEC_USER_DEF)) 2916 return; 2917 2918 hclge_update_fec_stats(hdev); 2919 2920 hclge_comm_get_fec_stats(hdev, fec_stats); 2921 } 2922 2923 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode) 2924 { 2925 struct hclge_config_fec_cmd *req; 2926 struct hclge_desc desc; 2927 int ret; 2928 2929 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false); 2930 2931 req = (struct hclge_config_fec_cmd *)desc.data; 2932 if (fec_mode & BIT(HNAE3_FEC_AUTO)) 2933 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1); 2934 if (fec_mode & BIT(HNAE3_FEC_RS)) 2935 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2936 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS); 2937 if (fec_mode & BIT(HNAE3_FEC_LLRS)) 2938 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2939 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS); 2940 if (fec_mode & BIT(HNAE3_FEC_BASER)) 2941 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2942 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER); 2943 2944 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2945 if (ret) 2946 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret); 2947 2948 return ret; 2949 } 2950 2951 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode) 2952 { 2953 struct hclge_vport *vport = hclge_get_vport(handle); 2954 struct hclge_dev *hdev = vport->back; 2955 struct hclge_mac *mac = &hdev->hw.mac; 2956 int ret; 2957 2958 if (fec_mode && !(mac->fec_ability & fec_mode)) { 2959 dev_err(&hdev->pdev->dev, "unsupported fec mode\n"); 2960 return -EINVAL; 2961 } 2962 2963 ret = hclge_set_fec_hw(hdev, fec_mode); 2964 if (ret) 2965 return ret; 2966 2967 mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF); 2968 return 0; 2969 } 2970 2971 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability, 2972 u8 *fec_mode) 2973 { 2974 struct hclge_vport *vport = hclge_get_vport(handle); 2975 struct hclge_dev *hdev = vport->back; 2976 struct hclge_mac *mac = &hdev->hw.mac; 2977 2978 if (fec_ability) 2979 *fec_ability = mac->fec_ability; 2980 if (fec_mode) 2981 *fec_mode = mac->fec_mode; 2982 } 2983 2984 static int hclge_mac_init(struct hclge_dev *hdev) 2985 { 2986 struct hclge_mac *mac = &hdev->hw.mac; 2987 int ret; 2988 2989 hdev->support_sfp_query = true; 2990 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 2991 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed, 2992 hdev->hw.mac.duplex, hdev->hw.mac.lane_num); 2993 if (ret) 2994 return ret; 2995 2996 if (hdev->hw.mac.support_autoneg) { 2997 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg); 2998 if (ret) 2999 return ret; 3000 } 3001 3002 mac->link = 0; 3003 3004 if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { 3005 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode); 3006 if (ret) 3007 return ret; 3008 } 3009 3010 ret = hclge_set_mac_mtu(hdev, hdev->mps); 3011 if (ret) { 3012 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret); 3013 return ret; 3014 } 3015 3016 ret = hclge_set_default_loopback(hdev); 3017 if (ret) 3018 return ret; 3019 3020 ret = hclge_buffer_alloc(hdev); 3021 if (ret) 3022 dev_err(&hdev->pdev->dev, 3023 "allocate buffer fail, ret=%d\n", ret); 3024 3025 return ret; 3026 } 3027 3028 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 3029 { 3030 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3031 !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) { 3032 hdev->last_mbx_scheduled = jiffies; 3033 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3034 } 3035 } 3036 3037 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 3038 { 3039 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3040 test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) && 3041 !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) { 3042 hdev->last_rst_scheduled = jiffies; 3043 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3044 } 3045 } 3046 3047 static void hclge_errhand_task_schedule(struct hclge_dev *hdev) 3048 { 3049 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3050 !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 3051 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3052 } 3053 3054 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time) 3055 { 3056 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3057 !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 3058 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time); 3059 } 3060 3061 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status) 3062 { 3063 struct hclge_link_status_cmd *req; 3064 struct hclge_desc desc; 3065 int ret; 3066 3067 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 3068 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3069 if (ret) { 3070 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 3071 ret); 3072 return ret; 3073 } 3074 3075 req = (struct hclge_link_status_cmd *)desc.data; 3076 *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ? 3077 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 3078 3079 return 0; 3080 } 3081 3082 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status) 3083 { 3084 struct phy_device *phydev = hdev->hw.mac.phydev; 3085 3086 *link_status = HCLGE_LINK_STATUS_DOWN; 3087 3088 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) 3089 return 0; 3090 3091 if (phydev && (phydev->state != PHY_RUNNING || !phydev->link)) 3092 return 0; 3093 3094 return hclge_get_mac_link_status(hdev, link_status); 3095 } 3096 3097 static void hclge_push_link_status(struct hclge_dev *hdev) 3098 { 3099 struct hclge_vport *vport; 3100 int ret; 3101 u16 i; 3102 3103 for (i = 0; i < pci_num_vf(hdev->pdev); i++) { 3104 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 3105 3106 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) || 3107 vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO) 3108 continue; 3109 3110 ret = hclge_push_vf_link_status(vport); 3111 if (ret) { 3112 dev_err(&hdev->pdev->dev, 3113 "failed to push link status to vf%u, ret = %d\n", 3114 i, ret); 3115 } 3116 } 3117 } 3118 3119 static void hclge_update_link_status(struct hclge_dev *hdev) 3120 { 3121 struct hnae3_handle *rhandle = &hdev->vport[0].roce; 3122 struct hnae3_handle *handle = &hdev->vport[0].nic; 3123 struct hnae3_client *rclient = hdev->roce_client; 3124 struct hnae3_client *client = hdev->nic_client; 3125 int state; 3126 int ret; 3127 3128 if (!client) 3129 return; 3130 3131 if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state)) 3132 return; 3133 3134 ret = hclge_get_mac_phy_link(hdev, &state); 3135 if (ret) { 3136 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3137 return; 3138 } 3139 3140 if (state != hdev->hw.mac.link) { 3141 hdev->hw.mac.link = state; 3142 client->ops->link_status_change(handle, state); 3143 hclge_config_mac_tnl_int(hdev, state); 3144 if (rclient && rclient->ops->link_status_change) 3145 rclient->ops->link_status_change(rhandle, state); 3146 3147 hclge_push_link_status(hdev); 3148 } 3149 3150 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3151 } 3152 3153 static void hclge_update_speed_advertising(struct hclge_mac *mac) 3154 { 3155 u32 speed_ability; 3156 3157 if (hclge_get_speed_bit(mac->speed, &speed_ability)) 3158 return; 3159 3160 switch (mac->module_type) { 3161 case HNAE3_MODULE_TYPE_FIBRE_LR: 3162 hclge_convert_setting_lr(speed_ability, mac->advertising); 3163 break; 3164 case HNAE3_MODULE_TYPE_FIBRE_SR: 3165 case HNAE3_MODULE_TYPE_AOC: 3166 hclge_convert_setting_sr(speed_ability, mac->advertising); 3167 break; 3168 case HNAE3_MODULE_TYPE_CR: 3169 hclge_convert_setting_cr(speed_ability, mac->advertising); 3170 break; 3171 case HNAE3_MODULE_TYPE_KR: 3172 hclge_convert_setting_kr(speed_ability, mac->advertising); 3173 break; 3174 default: 3175 break; 3176 } 3177 } 3178 3179 static void hclge_update_fec_advertising(struct hclge_mac *mac) 3180 { 3181 if (mac->fec_mode & BIT(HNAE3_FEC_RS)) 3182 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 3183 mac->advertising); 3184 else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS)) 3185 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 3186 mac->advertising); 3187 else if (mac->fec_mode & BIT(HNAE3_FEC_BASER)) 3188 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 3189 mac->advertising); 3190 else 3191 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 3192 mac->advertising); 3193 } 3194 3195 static void hclge_update_pause_advertising(struct hclge_dev *hdev) 3196 { 3197 struct hclge_mac *mac = &hdev->hw.mac; 3198 bool rx_en, tx_en; 3199 3200 switch (hdev->fc_mode_last_time) { 3201 case HCLGE_FC_RX_PAUSE: 3202 rx_en = true; 3203 tx_en = false; 3204 break; 3205 case HCLGE_FC_TX_PAUSE: 3206 rx_en = false; 3207 tx_en = true; 3208 break; 3209 case HCLGE_FC_FULL: 3210 rx_en = true; 3211 tx_en = true; 3212 break; 3213 default: 3214 rx_en = false; 3215 tx_en = false; 3216 break; 3217 } 3218 3219 linkmode_set_pause(mac->advertising, tx_en, rx_en); 3220 } 3221 3222 static void hclge_update_advertising(struct hclge_dev *hdev) 3223 { 3224 struct hclge_mac *mac = &hdev->hw.mac; 3225 3226 linkmode_zero(mac->advertising); 3227 hclge_update_speed_advertising(mac); 3228 hclge_update_fec_advertising(mac); 3229 hclge_update_pause_advertising(hdev); 3230 } 3231 3232 static void hclge_update_port_capability(struct hclge_dev *hdev, 3233 struct hclge_mac *mac) 3234 { 3235 if (hnae3_dev_fec_supported(hdev)) 3236 hclge_convert_setting_fec(mac); 3237 3238 /* firmware can not identify back plane type, the media type 3239 * read from configuration can help deal it 3240 */ 3241 if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE && 3242 mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN) 3243 mac->module_type = HNAE3_MODULE_TYPE_KR; 3244 else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3245 mac->module_type = HNAE3_MODULE_TYPE_TP; 3246 3247 if (mac->support_autoneg) { 3248 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported); 3249 linkmode_copy(mac->advertising, mac->supported); 3250 } else { 3251 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3252 mac->supported); 3253 hclge_update_advertising(hdev); 3254 } 3255 } 3256 3257 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed) 3258 { 3259 struct hclge_sfp_info_cmd *resp; 3260 struct hclge_desc desc; 3261 int ret; 3262 3263 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3264 resp = (struct hclge_sfp_info_cmd *)desc.data; 3265 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3266 if (ret == -EOPNOTSUPP) { 3267 dev_warn(&hdev->pdev->dev, 3268 "IMP do not support get SFP speed %d\n", ret); 3269 return ret; 3270 } else if (ret) { 3271 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret); 3272 return ret; 3273 } 3274 3275 *speed = le32_to_cpu(resp->speed); 3276 3277 return 0; 3278 } 3279 3280 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac) 3281 { 3282 struct hclge_sfp_info_cmd *resp; 3283 struct hclge_desc desc; 3284 int ret; 3285 3286 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3287 resp = (struct hclge_sfp_info_cmd *)desc.data; 3288 3289 resp->query_type = QUERY_ACTIVE_SPEED; 3290 3291 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3292 if (ret == -EOPNOTSUPP) { 3293 dev_warn(&hdev->pdev->dev, 3294 "IMP does not support get SFP info %d\n", ret); 3295 return ret; 3296 } else if (ret) { 3297 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret); 3298 return ret; 3299 } 3300 3301 /* In some case, mac speed get from IMP may be 0, it shouldn't be 3302 * set to mac->speed. 3303 */ 3304 if (!le32_to_cpu(resp->speed)) 3305 return 0; 3306 3307 mac->speed = le32_to_cpu(resp->speed); 3308 /* if resp->speed_ability is 0, it means it's an old version 3309 * firmware, do not update these params 3310 */ 3311 if (resp->speed_ability) { 3312 mac->module_type = le32_to_cpu(resp->module_type); 3313 mac->speed_ability = le32_to_cpu(resp->speed_ability); 3314 mac->autoneg = resp->autoneg; 3315 mac->support_autoneg = resp->autoneg_ability; 3316 mac->speed_type = QUERY_ACTIVE_SPEED; 3317 mac->lane_num = resp->lane_num; 3318 if (!resp->active_fec) 3319 mac->fec_mode = 0; 3320 else 3321 mac->fec_mode = BIT(resp->active_fec); 3322 mac->fec_ability = resp->fec_ability; 3323 } else { 3324 mac->speed_type = QUERY_SFP_SPEED; 3325 } 3326 3327 return 0; 3328 } 3329 3330 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle, 3331 struct ethtool_link_ksettings *cmd) 3332 { 3333 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3334 struct hclge_vport *vport = hclge_get_vport(handle); 3335 struct hclge_phy_link_ksetting_0_cmd *req0; 3336 struct hclge_phy_link_ksetting_1_cmd *req1; 3337 u32 supported, advertising, lp_advertising; 3338 struct hclge_dev *hdev = vport->back; 3339 int ret; 3340 3341 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3342 true); 3343 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3344 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3345 true); 3346 3347 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3348 if (ret) { 3349 dev_err(&hdev->pdev->dev, 3350 "failed to get phy link ksetting, ret = %d.\n", ret); 3351 return ret; 3352 } 3353 3354 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3355 cmd->base.autoneg = req0->autoneg; 3356 cmd->base.speed = le32_to_cpu(req0->speed); 3357 cmd->base.duplex = req0->duplex; 3358 cmd->base.port = req0->port; 3359 cmd->base.transceiver = req0->transceiver; 3360 cmd->base.phy_address = req0->phy_address; 3361 cmd->base.eth_tp_mdix = req0->eth_tp_mdix; 3362 cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl; 3363 supported = le32_to_cpu(req0->supported); 3364 advertising = le32_to_cpu(req0->advertising); 3365 lp_advertising = le32_to_cpu(req0->lp_advertising); 3366 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3367 supported); 3368 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3369 advertising); 3370 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 3371 lp_advertising); 3372 3373 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3374 cmd->base.master_slave_cfg = req1->master_slave_cfg; 3375 cmd->base.master_slave_state = req1->master_slave_state; 3376 3377 return 0; 3378 } 3379 3380 static int 3381 hclge_set_phy_link_ksettings(struct hnae3_handle *handle, 3382 const struct ethtool_link_ksettings *cmd) 3383 { 3384 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3385 struct hclge_vport *vport = hclge_get_vport(handle); 3386 struct hclge_phy_link_ksetting_0_cmd *req0; 3387 struct hclge_phy_link_ksetting_1_cmd *req1; 3388 struct hclge_dev *hdev = vport->back; 3389 u32 advertising; 3390 int ret; 3391 3392 if (cmd->base.autoneg == AUTONEG_DISABLE && 3393 ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) || 3394 (cmd->base.duplex != DUPLEX_HALF && 3395 cmd->base.duplex != DUPLEX_FULL))) 3396 return -EINVAL; 3397 3398 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3399 false); 3400 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3401 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3402 false); 3403 3404 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3405 req0->autoneg = cmd->base.autoneg; 3406 req0->speed = cpu_to_le32(cmd->base.speed); 3407 req0->duplex = cmd->base.duplex; 3408 ethtool_convert_link_mode_to_legacy_u32(&advertising, 3409 cmd->link_modes.advertising); 3410 req0->advertising = cpu_to_le32(advertising); 3411 req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; 3412 3413 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3414 req1->master_slave_cfg = cmd->base.master_slave_cfg; 3415 3416 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3417 if (ret) { 3418 dev_err(&hdev->pdev->dev, 3419 "failed to set phy link ksettings, ret = %d.\n", ret); 3420 return ret; 3421 } 3422 3423 hdev->hw.mac.autoneg = cmd->base.autoneg; 3424 hdev->hw.mac.speed = cmd->base.speed; 3425 hdev->hw.mac.duplex = cmd->base.duplex; 3426 linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising); 3427 3428 return 0; 3429 } 3430 3431 static int hclge_update_tp_port_info(struct hclge_dev *hdev) 3432 { 3433 struct ethtool_link_ksettings cmd; 3434 int ret; 3435 3436 if (!hnae3_dev_phy_imp_supported(hdev)) 3437 return 0; 3438 3439 ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd); 3440 if (ret) 3441 return ret; 3442 3443 hdev->hw.mac.autoneg = cmd.base.autoneg; 3444 hdev->hw.mac.speed = cmd.base.speed; 3445 hdev->hw.mac.duplex = cmd.base.duplex; 3446 linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising); 3447 3448 return 0; 3449 } 3450 3451 static int hclge_tp_port_init(struct hclge_dev *hdev) 3452 { 3453 struct ethtool_link_ksettings cmd; 3454 3455 if (!hnae3_dev_phy_imp_supported(hdev)) 3456 return 0; 3457 3458 cmd.base.autoneg = hdev->hw.mac.autoneg; 3459 cmd.base.speed = hdev->hw.mac.speed; 3460 cmd.base.duplex = hdev->hw.mac.duplex; 3461 linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising); 3462 3463 return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd); 3464 } 3465 3466 static int hclge_update_port_info(struct hclge_dev *hdev) 3467 { 3468 struct hclge_mac *mac = &hdev->hw.mac; 3469 int speed; 3470 int ret; 3471 3472 /* get the port info from SFP cmd if not copper port */ 3473 if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3474 return hclge_update_tp_port_info(hdev); 3475 3476 /* if IMP does not support get SFP/qSFP info, return directly */ 3477 if (!hdev->support_sfp_query) 3478 return 0; 3479 3480 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3481 speed = mac->speed; 3482 ret = hclge_get_sfp_info(hdev, mac); 3483 } else { 3484 speed = HCLGE_MAC_SPEED_UNKNOWN; 3485 ret = hclge_get_sfp_speed(hdev, &speed); 3486 } 3487 3488 if (ret == -EOPNOTSUPP) { 3489 hdev->support_sfp_query = false; 3490 return ret; 3491 } else if (ret) { 3492 return ret; 3493 } 3494 3495 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3496 if (mac->speed_type == QUERY_ACTIVE_SPEED) { 3497 hclge_update_port_capability(hdev, mac); 3498 if (mac->speed != speed) 3499 (void)hclge_tm_port_shaper_cfg(hdev); 3500 return 0; 3501 } 3502 return hclge_cfg_mac_speed_dup(hdev, mac->speed, 3503 HCLGE_MAC_FULL, mac->lane_num); 3504 } else { 3505 if (speed == HCLGE_MAC_SPEED_UNKNOWN) 3506 return 0; /* do nothing if no SFP */ 3507 3508 /* must config full duplex for SFP */ 3509 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0); 3510 } 3511 } 3512 3513 static int hclge_get_status(struct hnae3_handle *handle) 3514 { 3515 struct hclge_vport *vport = hclge_get_vport(handle); 3516 struct hclge_dev *hdev = vport->back; 3517 3518 hclge_update_link_status(hdev); 3519 3520 return hdev->hw.mac.link; 3521 } 3522 3523 static struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf) 3524 { 3525 if (!pci_num_vf(hdev->pdev)) { 3526 dev_err(&hdev->pdev->dev, 3527 "SRIOV is disabled, can not get vport(%d) info.\n", vf); 3528 return NULL; 3529 } 3530 3531 if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) { 3532 dev_err(&hdev->pdev->dev, 3533 "vf id(%d) is out of range(0 <= vfid < %d)\n", 3534 vf, pci_num_vf(hdev->pdev)); 3535 return NULL; 3536 } 3537 3538 /* VF start from 1 in vport */ 3539 vf += HCLGE_VF_VPORT_START_NUM; 3540 return &hdev->vport[vf]; 3541 } 3542 3543 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf, 3544 struct ifla_vf_info *ivf) 3545 { 3546 struct hclge_vport *vport = hclge_get_vport(handle); 3547 struct hclge_dev *hdev = vport->back; 3548 3549 vport = hclge_get_vf_vport(hdev, vf); 3550 if (!vport) 3551 return -EINVAL; 3552 3553 ivf->vf = vf; 3554 ivf->linkstate = vport->vf_info.link_state; 3555 ivf->spoofchk = vport->vf_info.spoofchk; 3556 ivf->trusted = vport->vf_info.trusted; 3557 ivf->min_tx_rate = 0; 3558 ivf->max_tx_rate = vport->vf_info.max_tx_rate; 3559 ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag; 3560 ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto); 3561 ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos; 3562 ether_addr_copy(ivf->mac, vport->vf_info.mac); 3563 3564 return 0; 3565 } 3566 3567 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, 3568 int link_state) 3569 { 3570 struct hclge_vport *vport = hclge_get_vport(handle); 3571 struct hclge_dev *hdev = vport->back; 3572 int link_state_old; 3573 int ret; 3574 3575 vport = hclge_get_vf_vport(hdev, vf); 3576 if (!vport) 3577 return -EINVAL; 3578 3579 link_state_old = vport->vf_info.link_state; 3580 vport->vf_info.link_state = link_state; 3581 3582 /* return success directly if the VF is unalive, VF will 3583 * query link state itself when it starts work. 3584 */ 3585 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3586 return 0; 3587 3588 ret = hclge_push_vf_link_status(vport); 3589 if (ret) { 3590 vport->vf_info.link_state = link_state_old; 3591 dev_err(&hdev->pdev->dev, 3592 "failed to push vf%d link status, ret = %d\n", vf, ret); 3593 } 3594 3595 return ret; 3596 } 3597 3598 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 3599 { 3600 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; 3601 3602 /* fetch the events from their corresponding regs */ 3603 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 3604 msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 3605 hw_err_src_reg = hclge_read_dev(&hdev->hw, 3606 HCLGE_RAS_PF_OTHER_INT_STS_REG); 3607 3608 /* Assumption: If by any chance reset and mailbox events are reported 3609 * together then we will only process reset event in this go and will 3610 * defer the processing of the mailbox events. Since, we would have not 3611 * cleared RX CMDQ event this time we would receive again another 3612 * interrupt from H/W just for the mailbox. 3613 * 3614 * check for vector0 reset event sources 3615 */ 3616 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { 3617 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); 3618 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); 3619 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3620 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3621 hdev->rst_stats.imp_rst_cnt++; 3622 return HCLGE_VECTOR0_EVENT_RST; 3623 } 3624 3625 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { 3626 dev_info(&hdev->pdev->dev, "global reset interrupt\n"); 3627 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3628 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 3629 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3630 hdev->rst_stats.global_rst_cnt++; 3631 return HCLGE_VECTOR0_EVENT_RST; 3632 } 3633 3634 /* check for vector0 msix event and hardware error event source */ 3635 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK || 3636 hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK) 3637 return HCLGE_VECTOR0_EVENT_ERR; 3638 3639 /* check for vector0 ptp event source */ 3640 if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) { 3641 *clearval = msix_src_reg; 3642 return HCLGE_VECTOR0_EVENT_PTP; 3643 } 3644 3645 /* check for vector0 mailbox(=CMDQ RX) event source */ 3646 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 3647 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 3648 *clearval = cmdq_src_reg; 3649 return HCLGE_VECTOR0_EVENT_MBX; 3650 } 3651 3652 /* print other vector0 event source */ 3653 dev_info(&hdev->pdev->dev, 3654 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n", 3655 cmdq_src_reg, hw_err_src_reg, msix_src_reg); 3656 3657 return HCLGE_VECTOR0_EVENT_OTHER; 3658 } 3659 3660 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 3661 u32 regclr) 3662 { 3663 switch (event_type) { 3664 case HCLGE_VECTOR0_EVENT_PTP: 3665 case HCLGE_VECTOR0_EVENT_RST: 3666 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 3667 break; 3668 case HCLGE_VECTOR0_EVENT_MBX: 3669 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 3670 break; 3671 default: 3672 break; 3673 } 3674 } 3675 3676 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 3677 { 3678 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 3679 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 3680 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 3681 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 3682 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 3683 } 3684 3685 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 3686 { 3687 writel(enable ? 1 : 0, vector->addr); 3688 } 3689 3690 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 3691 { 3692 struct hclge_dev *hdev = data; 3693 unsigned long flags; 3694 u32 clearval = 0; 3695 u32 event_cause; 3696 3697 hclge_enable_vector(&hdev->misc_vector, false); 3698 event_cause = hclge_check_event_cause(hdev, &clearval); 3699 3700 /* vector 0 interrupt is shared with reset and mailbox source events. */ 3701 switch (event_cause) { 3702 case HCLGE_VECTOR0_EVENT_ERR: 3703 hclge_errhand_task_schedule(hdev); 3704 break; 3705 case HCLGE_VECTOR0_EVENT_RST: 3706 hclge_reset_task_schedule(hdev); 3707 break; 3708 case HCLGE_VECTOR0_EVENT_PTP: 3709 spin_lock_irqsave(&hdev->ptp->lock, flags); 3710 hclge_ptp_clean_tx_hwts(hdev); 3711 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 3712 break; 3713 case HCLGE_VECTOR0_EVENT_MBX: 3714 /* If we are here then, 3715 * 1. Either we are not handling any mbx task and we are not 3716 * scheduled as well 3717 * OR 3718 * 2. We could be handling a mbx task but nothing more is 3719 * scheduled. 3720 * In both cases, we should schedule mbx task as there are more 3721 * mbx messages reported by this interrupt. 3722 */ 3723 hclge_mbx_task_schedule(hdev); 3724 break; 3725 default: 3726 dev_warn(&hdev->pdev->dev, 3727 "received unknown or unhandled event of vector0\n"); 3728 break; 3729 } 3730 3731 hclge_clear_event_cause(hdev, event_cause, clearval); 3732 3733 /* Enable interrupt if it is not caused by reset event or error event */ 3734 if (event_cause == HCLGE_VECTOR0_EVENT_PTP || 3735 event_cause == HCLGE_VECTOR0_EVENT_MBX || 3736 event_cause == HCLGE_VECTOR0_EVENT_OTHER) 3737 hclge_enable_vector(&hdev->misc_vector, true); 3738 3739 return IRQ_HANDLED; 3740 } 3741 3742 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 3743 { 3744 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 3745 dev_warn(&hdev->pdev->dev, 3746 "vector(vector_id %d) has been freed.\n", vector_id); 3747 return; 3748 } 3749 3750 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 3751 hdev->num_msi_left += 1; 3752 hdev->num_msi_used -= 1; 3753 } 3754 3755 static void hclge_get_misc_vector(struct hclge_dev *hdev) 3756 { 3757 struct hclge_misc_vector *vector = &hdev->misc_vector; 3758 3759 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 3760 3761 vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 3762 hdev->vector_status[0] = 0; 3763 3764 hdev->num_msi_left -= 1; 3765 hdev->num_msi_used += 1; 3766 } 3767 3768 static int hclge_misc_irq_init(struct hclge_dev *hdev) 3769 { 3770 int ret; 3771 3772 hclge_get_misc_vector(hdev); 3773 3774 /* this would be explicitly freed in the end */ 3775 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 3776 HCLGE_NAME, pci_name(hdev->pdev)); 3777 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 3778 0, hdev->misc_vector.name, hdev); 3779 if (ret) { 3780 hclge_free_vector(hdev, 0); 3781 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 3782 hdev->misc_vector.vector_irq); 3783 } 3784 3785 return ret; 3786 } 3787 3788 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 3789 { 3790 free_irq(hdev->misc_vector.vector_irq, hdev); 3791 hclge_free_vector(hdev, 0); 3792 } 3793 3794 int hclge_notify_client(struct hclge_dev *hdev, 3795 enum hnae3_reset_notify_type type) 3796 { 3797 struct hnae3_handle *handle = &hdev->vport[0].nic; 3798 struct hnae3_client *client = hdev->nic_client; 3799 int ret; 3800 3801 if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client) 3802 return 0; 3803 3804 if (!client->ops->reset_notify) 3805 return -EOPNOTSUPP; 3806 3807 ret = client->ops->reset_notify(handle, type); 3808 if (ret) 3809 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 3810 type, ret); 3811 3812 return ret; 3813 } 3814 3815 static int hclge_notify_roce_client(struct hclge_dev *hdev, 3816 enum hnae3_reset_notify_type type) 3817 { 3818 struct hnae3_handle *handle = &hdev->vport[0].roce; 3819 struct hnae3_client *client = hdev->roce_client; 3820 int ret; 3821 3822 if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client) 3823 return 0; 3824 3825 if (!client->ops->reset_notify) 3826 return -EOPNOTSUPP; 3827 3828 ret = client->ops->reset_notify(handle, type); 3829 if (ret) 3830 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 3831 type, ret); 3832 3833 return ret; 3834 } 3835 3836 static int hclge_reset_wait(struct hclge_dev *hdev) 3837 { 3838 #define HCLGE_RESET_WATI_MS 100 3839 #define HCLGE_RESET_WAIT_CNT 350 3840 3841 u32 val, reg, reg_bit; 3842 u32 cnt = 0; 3843 3844 switch (hdev->reset_type) { 3845 case HNAE3_IMP_RESET: 3846 reg = HCLGE_GLOBAL_RESET_REG; 3847 reg_bit = HCLGE_IMP_RESET_BIT; 3848 break; 3849 case HNAE3_GLOBAL_RESET: 3850 reg = HCLGE_GLOBAL_RESET_REG; 3851 reg_bit = HCLGE_GLOBAL_RESET_BIT; 3852 break; 3853 case HNAE3_FUNC_RESET: 3854 reg = HCLGE_FUN_RST_ING; 3855 reg_bit = HCLGE_FUN_RST_ING_B; 3856 break; 3857 default: 3858 dev_err(&hdev->pdev->dev, 3859 "Wait for unsupported reset type: %d\n", 3860 hdev->reset_type); 3861 return -EINVAL; 3862 } 3863 3864 val = hclge_read_dev(&hdev->hw, reg); 3865 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 3866 msleep(HCLGE_RESET_WATI_MS); 3867 val = hclge_read_dev(&hdev->hw, reg); 3868 cnt++; 3869 } 3870 3871 if (cnt >= HCLGE_RESET_WAIT_CNT) { 3872 dev_warn(&hdev->pdev->dev, 3873 "Wait for reset timeout: %d\n", hdev->reset_type); 3874 return -EBUSY; 3875 } 3876 3877 return 0; 3878 } 3879 3880 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset) 3881 { 3882 struct hclge_vf_rst_cmd *req; 3883 struct hclge_desc desc; 3884 3885 req = (struct hclge_vf_rst_cmd *)desc.data; 3886 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false); 3887 req->dest_vfid = func_id; 3888 3889 if (reset) 3890 req->vf_rst = 0x1; 3891 3892 return hclge_cmd_send(&hdev->hw, &desc, 1); 3893 } 3894 3895 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset) 3896 { 3897 int i; 3898 3899 for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) { 3900 struct hclge_vport *vport = &hdev->vport[i]; 3901 int ret; 3902 3903 /* Send cmd to set/clear VF's FUNC_RST_ING */ 3904 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset); 3905 if (ret) { 3906 dev_err(&hdev->pdev->dev, 3907 "set vf(%u) rst failed %d!\n", 3908 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3909 ret); 3910 return ret; 3911 } 3912 3913 if (!reset || !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3914 continue; 3915 3916 /* Inform VF to process the reset. 3917 * hclge_inform_reset_assert_to_vf may fail if VF 3918 * driver is not loaded. 3919 */ 3920 ret = hclge_inform_reset_assert_to_vf(vport); 3921 if (ret) 3922 dev_warn(&hdev->pdev->dev, 3923 "inform reset to vf(%u) failed %d!\n", 3924 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3925 ret); 3926 } 3927 3928 return 0; 3929 } 3930 3931 static void hclge_mailbox_service_task(struct hclge_dev *hdev) 3932 { 3933 if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) || 3934 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) || 3935 test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 3936 return; 3937 3938 if (time_is_before_jiffies(hdev->last_mbx_scheduled + 3939 HCLGE_MBX_SCHED_TIMEOUT)) 3940 dev_warn(&hdev->pdev->dev, 3941 "mbx service task is scheduled after %ums on cpu%u!\n", 3942 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled), 3943 smp_processor_id()); 3944 3945 hclge_mbx_handler(hdev); 3946 3947 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 3948 } 3949 3950 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev) 3951 { 3952 struct hclge_pf_rst_sync_cmd *req; 3953 struct hclge_desc desc; 3954 int cnt = 0; 3955 int ret; 3956 3957 req = (struct hclge_pf_rst_sync_cmd *)desc.data; 3958 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true); 3959 3960 do { 3961 /* vf need to down netdev by mbx during PF or FLR reset */ 3962 hclge_mailbox_service_task(hdev); 3963 3964 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3965 /* for compatible with old firmware, wait 3966 * 100 ms for VF to stop IO 3967 */ 3968 if (ret == -EOPNOTSUPP) { 3969 msleep(HCLGE_RESET_SYNC_TIME); 3970 return; 3971 } else if (ret) { 3972 dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n", 3973 ret); 3974 return; 3975 } else if (req->all_vf_ready) { 3976 return; 3977 } 3978 msleep(HCLGE_PF_RESET_SYNC_TIME); 3979 hclge_comm_cmd_reuse_desc(&desc, true); 3980 } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT); 3981 3982 dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n"); 3983 } 3984 3985 void hclge_report_hw_error(struct hclge_dev *hdev, 3986 enum hnae3_hw_error_type type) 3987 { 3988 struct hnae3_client *client = hdev->nic_client; 3989 3990 if (!client || !client->ops->process_hw_error || 3991 !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) 3992 return; 3993 3994 client->ops->process_hw_error(&hdev->vport[0].nic, type); 3995 } 3996 3997 static void hclge_handle_imp_error(struct hclge_dev *hdev) 3998 { 3999 u32 reg_val; 4000 4001 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4002 if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { 4003 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); 4004 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); 4005 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 4006 } 4007 4008 if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { 4009 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); 4010 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); 4011 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 4012 } 4013 } 4014 4015 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 4016 { 4017 struct hclge_desc desc; 4018 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 4019 int ret; 4020 4021 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 4022 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 4023 req->fun_reset_vfid = func_id; 4024 4025 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4026 if (ret) 4027 dev_err(&hdev->pdev->dev, 4028 "send function reset cmd fail, status =%d\n", ret); 4029 4030 return ret; 4031 } 4032 4033 static void hclge_do_reset(struct hclge_dev *hdev) 4034 { 4035 struct hnae3_handle *handle = &hdev->vport[0].nic; 4036 struct pci_dev *pdev = hdev->pdev; 4037 u32 val; 4038 4039 if (hclge_get_hw_reset_stat(handle)) { 4040 dev_info(&pdev->dev, "hardware reset not finish\n"); 4041 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n", 4042 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING), 4043 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 4044 return; 4045 } 4046 4047 switch (hdev->reset_type) { 4048 case HNAE3_IMP_RESET: 4049 dev_info(&pdev->dev, "IMP reset requested\n"); 4050 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4051 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1); 4052 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val); 4053 break; 4054 case HNAE3_GLOBAL_RESET: 4055 dev_info(&pdev->dev, "global reset requested\n"); 4056 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 4057 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 4058 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 4059 break; 4060 case HNAE3_FUNC_RESET: 4061 dev_info(&pdev->dev, "PF reset requested\n"); 4062 /* schedule again to check later */ 4063 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); 4064 hclge_reset_task_schedule(hdev); 4065 break; 4066 default: 4067 dev_warn(&pdev->dev, 4068 "unsupported reset type: %d\n", hdev->reset_type); 4069 break; 4070 } 4071 } 4072 4073 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 4074 unsigned long *addr) 4075 { 4076 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 4077 struct hclge_dev *hdev = ae_dev->priv; 4078 4079 /* return the highest priority reset level amongst all */ 4080 if (test_bit(HNAE3_IMP_RESET, addr)) { 4081 rst_level = HNAE3_IMP_RESET; 4082 clear_bit(HNAE3_IMP_RESET, addr); 4083 clear_bit(HNAE3_GLOBAL_RESET, addr); 4084 clear_bit(HNAE3_FUNC_RESET, addr); 4085 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) { 4086 rst_level = HNAE3_GLOBAL_RESET; 4087 clear_bit(HNAE3_GLOBAL_RESET, addr); 4088 clear_bit(HNAE3_FUNC_RESET, addr); 4089 } else if (test_bit(HNAE3_FUNC_RESET, addr)) { 4090 rst_level = HNAE3_FUNC_RESET; 4091 clear_bit(HNAE3_FUNC_RESET, addr); 4092 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 4093 rst_level = HNAE3_FLR_RESET; 4094 clear_bit(HNAE3_FLR_RESET, addr); 4095 } 4096 4097 if (hdev->reset_type != HNAE3_NONE_RESET && 4098 rst_level < hdev->reset_type) 4099 return HNAE3_NONE_RESET; 4100 4101 return rst_level; 4102 } 4103 4104 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 4105 { 4106 u32 clearval = 0; 4107 4108 switch (hdev->reset_type) { 4109 case HNAE3_IMP_RESET: 4110 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 4111 break; 4112 case HNAE3_GLOBAL_RESET: 4113 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 4114 break; 4115 default: 4116 break; 4117 } 4118 4119 if (!clearval) 4120 return; 4121 4122 /* For revision 0x20, the reset interrupt source 4123 * can only be cleared after hardware reset done 4124 */ 4125 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 4126 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, 4127 clearval); 4128 4129 hclge_enable_vector(&hdev->misc_vector, true); 4130 } 4131 4132 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable) 4133 { 4134 u32 reg_val; 4135 4136 reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 4137 if (enable) 4138 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY; 4139 else 4140 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY; 4141 4142 hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val); 4143 } 4144 4145 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev) 4146 { 4147 int ret; 4148 4149 ret = hclge_set_all_vf_rst(hdev, true); 4150 if (ret) 4151 return ret; 4152 4153 hclge_func_reset_sync_vf(hdev); 4154 4155 return 0; 4156 } 4157 4158 static int hclge_reset_prepare_wait(struct hclge_dev *hdev) 4159 { 4160 u32 reg_val; 4161 int ret = 0; 4162 4163 switch (hdev->reset_type) { 4164 case HNAE3_FUNC_RESET: 4165 ret = hclge_func_reset_notify_vf(hdev); 4166 if (ret) 4167 return ret; 4168 4169 ret = hclge_func_reset_cmd(hdev, 0); 4170 if (ret) { 4171 dev_err(&hdev->pdev->dev, 4172 "asserting function reset fail %d!\n", ret); 4173 return ret; 4174 } 4175 4176 /* After performaning pf reset, it is not necessary to do the 4177 * mailbox handling or send any command to firmware, because 4178 * any mailbox handling or command to firmware is only valid 4179 * after hclge_comm_cmd_init is called. 4180 */ 4181 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 4182 hdev->rst_stats.pf_rst_cnt++; 4183 break; 4184 case HNAE3_FLR_RESET: 4185 ret = hclge_func_reset_notify_vf(hdev); 4186 if (ret) 4187 return ret; 4188 break; 4189 case HNAE3_IMP_RESET: 4190 hclge_handle_imp_error(hdev); 4191 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4192 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, 4193 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); 4194 break; 4195 default: 4196 break; 4197 } 4198 4199 /* inform hardware that preparatory work is done */ 4200 msleep(HCLGE_RESET_SYNC_TIME); 4201 hclge_reset_handshake(hdev, true); 4202 dev_info(&hdev->pdev->dev, "prepare wait ok\n"); 4203 4204 return ret; 4205 } 4206 4207 static void hclge_show_rst_info(struct hclge_dev *hdev) 4208 { 4209 char *buf; 4210 4211 buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL); 4212 if (!buf) 4213 return; 4214 4215 hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN); 4216 4217 dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf); 4218 4219 kfree(buf); 4220 } 4221 4222 static bool hclge_reset_err_handle(struct hclge_dev *hdev) 4223 { 4224 #define MAX_RESET_FAIL_CNT 5 4225 4226 if (hdev->reset_pending) { 4227 dev_info(&hdev->pdev->dev, "Reset pending %lu\n", 4228 hdev->reset_pending); 4229 return true; 4230 } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) & 4231 HCLGE_RESET_INT_M) { 4232 dev_info(&hdev->pdev->dev, 4233 "reset failed because new reset interrupt\n"); 4234 hclge_clear_reset_cause(hdev); 4235 return false; 4236 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { 4237 hdev->rst_stats.reset_fail_cnt++; 4238 set_bit(hdev->reset_type, &hdev->reset_pending); 4239 dev_info(&hdev->pdev->dev, 4240 "re-schedule reset task(%u)\n", 4241 hdev->rst_stats.reset_fail_cnt); 4242 return true; 4243 } 4244 4245 hclge_clear_reset_cause(hdev); 4246 4247 /* recover the handshake status when reset fail */ 4248 hclge_reset_handshake(hdev, true); 4249 4250 dev_err(&hdev->pdev->dev, "Reset fail!\n"); 4251 4252 hclge_show_rst_info(hdev); 4253 4254 set_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4255 4256 return false; 4257 } 4258 4259 static void hclge_update_reset_level(struct hclge_dev *hdev) 4260 { 4261 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4262 enum hnae3_reset_type reset_level; 4263 4264 /* reset request will not be set during reset, so clear 4265 * pending reset request to avoid unnecessary reset 4266 * caused by the same reason. 4267 */ 4268 hclge_get_reset_level(ae_dev, &hdev->reset_request); 4269 4270 /* if default_reset_request has a higher level reset request, 4271 * it should be handled as soon as possible. since some errors 4272 * need this kind of reset to fix. 4273 */ 4274 reset_level = hclge_get_reset_level(ae_dev, 4275 &hdev->default_reset_request); 4276 if (reset_level != HNAE3_NONE_RESET) 4277 set_bit(reset_level, &hdev->reset_request); 4278 } 4279 4280 static int hclge_set_rst_done(struct hclge_dev *hdev) 4281 { 4282 struct hclge_pf_rst_done_cmd *req; 4283 struct hclge_desc desc; 4284 int ret; 4285 4286 req = (struct hclge_pf_rst_done_cmd *)desc.data; 4287 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false); 4288 req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT; 4289 4290 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4291 /* To be compatible with the old firmware, which does not support 4292 * command HCLGE_OPC_PF_RST_DONE, just print a warning and 4293 * return success 4294 */ 4295 if (ret == -EOPNOTSUPP) { 4296 dev_warn(&hdev->pdev->dev, 4297 "current firmware does not support command(0x%x)!\n", 4298 HCLGE_OPC_PF_RST_DONE); 4299 return 0; 4300 } else if (ret) { 4301 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n", 4302 ret); 4303 } 4304 4305 return ret; 4306 } 4307 4308 static int hclge_reset_prepare_up(struct hclge_dev *hdev) 4309 { 4310 int ret = 0; 4311 4312 switch (hdev->reset_type) { 4313 case HNAE3_FUNC_RESET: 4314 case HNAE3_FLR_RESET: 4315 ret = hclge_set_all_vf_rst(hdev, false); 4316 break; 4317 case HNAE3_GLOBAL_RESET: 4318 case HNAE3_IMP_RESET: 4319 ret = hclge_set_rst_done(hdev); 4320 break; 4321 default: 4322 break; 4323 } 4324 4325 /* clear up the handshake status after re-initialize done */ 4326 hclge_reset_handshake(hdev, false); 4327 4328 return ret; 4329 } 4330 4331 static int hclge_reset_stack(struct hclge_dev *hdev) 4332 { 4333 int ret; 4334 4335 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 4336 if (ret) 4337 return ret; 4338 4339 ret = hclge_reset_ae_dev(hdev->ae_dev); 4340 if (ret) 4341 return ret; 4342 4343 return hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 4344 } 4345 4346 static int hclge_reset_prepare(struct hclge_dev *hdev) 4347 { 4348 int ret; 4349 4350 hdev->rst_stats.reset_cnt++; 4351 /* perform reset of the stack & ae device for a client */ 4352 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 4353 if (ret) 4354 return ret; 4355 4356 rtnl_lock(); 4357 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 4358 rtnl_unlock(); 4359 if (ret) 4360 return ret; 4361 4362 return hclge_reset_prepare_wait(hdev); 4363 } 4364 4365 static int hclge_reset_rebuild(struct hclge_dev *hdev) 4366 { 4367 int ret; 4368 4369 hdev->rst_stats.hw_reset_done_cnt++; 4370 4371 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 4372 if (ret) 4373 return ret; 4374 4375 rtnl_lock(); 4376 ret = hclge_reset_stack(hdev); 4377 rtnl_unlock(); 4378 if (ret) 4379 return ret; 4380 4381 hclge_clear_reset_cause(hdev); 4382 4383 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 4384 /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1 4385 * times 4386 */ 4387 if (ret && 4388 hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1) 4389 return ret; 4390 4391 ret = hclge_reset_prepare_up(hdev); 4392 if (ret) 4393 return ret; 4394 4395 rtnl_lock(); 4396 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT); 4397 rtnl_unlock(); 4398 if (ret) 4399 return ret; 4400 4401 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT); 4402 if (ret) 4403 return ret; 4404 4405 hdev->last_reset_time = jiffies; 4406 hdev->rst_stats.reset_fail_cnt = 0; 4407 hdev->rst_stats.reset_done_cnt++; 4408 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4409 4410 hclge_update_reset_level(hdev); 4411 4412 return 0; 4413 } 4414 4415 static void hclge_reset(struct hclge_dev *hdev) 4416 { 4417 if (hclge_reset_prepare(hdev)) 4418 goto err_reset; 4419 4420 if (hclge_reset_wait(hdev)) 4421 goto err_reset; 4422 4423 if (hclge_reset_rebuild(hdev)) 4424 goto err_reset; 4425 4426 return; 4427 4428 err_reset: 4429 if (hclge_reset_err_handle(hdev)) 4430 hclge_reset_task_schedule(hdev); 4431 } 4432 4433 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) 4434 { 4435 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4436 struct hclge_dev *hdev = ae_dev->priv; 4437 4438 /* We might end up getting called broadly because of 2 below cases: 4439 * 1. Recoverable error was conveyed through APEI and only way to bring 4440 * normalcy is to reset. 4441 * 2. A new reset request from the stack due to timeout 4442 * 4443 * check if this is a new reset request and we are not here just because 4444 * last reset attempt did not succeed and watchdog hit us again. We will 4445 * know this if last reset request did not occur very recently (watchdog 4446 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 4447 * In case of new request we reset the "reset level" to PF reset. 4448 * And if it is a repeat reset request of the most recent one then we 4449 * want to make sure we throttle the reset request. Therefore, we will 4450 * not allow it again before 3*HZ times. 4451 */ 4452 4453 if (time_before(jiffies, (hdev->last_reset_time + 4454 HCLGE_RESET_INTERVAL))) { 4455 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 4456 return; 4457 } 4458 4459 if (hdev->default_reset_request) { 4460 hdev->reset_level = 4461 hclge_get_reset_level(ae_dev, 4462 &hdev->default_reset_request); 4463 } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) { 4464 hdev->reset_level = HNAE3_FUNC_RESET; 4465 } 4466 4467 dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n", 4468 hdev->reset_level); 4469 4470 /* request reset & schedule reset task */ 4471 set_bit(hdev->reset_level, &hdev->reset_request); 4472 hclge_reset_task_schedule(hdev); 4473 4474 if (hdev->reset_level < HNAE3_GLOBAL_RESET) 4475 hdev->reset_level++; 4476 } 4477 4478 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 4479 enum hnae3_reset_type rst_type) 4480 { 4481 struct hclge_dev *hdev = ae_dev->priv; 4482 4483 set_bit(rst_type, &hdev->default_reset_request); 4484 } 4485 4486 static void hclge_reset_timer(struct timer_list *t) 4487 { 4488 struct hclge_dev *hdev = from_timer(hdev, t, reset_timer); 4489 4490 /* if default_reset_request has no value, it means that this reset 4491 * request has already be handled, so just return here 4492 */ 4493 if (!hdev->default_reset_request) 4494 return; 4495 4496 dev_info(&hdev->pdev->dev, 4497 "triggering reset in reset timer\n"); 4498 hclge_reset_event(hdev->pdev, NULL); 4499 } 4500 4501 static void hclge_reset_subtask(struct hclge_dev *hdev) 4502 { 4503 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4504 4505 /* check if there is any ongoing reset in the hardware. This status can 4506 * be checked from reset_pending. If there is then, we need to wait for 4507 * hardware to complete reset. 4508 * a. If we are able to figure out in reasonable time that hardware 4509 * has fully resetted then, we can proceed with driver, client 4510 * reset. 4511 * b. else, we can come back later to check this status so re-sched 4512 * now. 4513 */ 4514 hdev->last_reset_time = jiffies; 4515 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending); 4516 if (hdev->reset_type != HNAE3_NONE_RESET) 4517 hclge_reset(hdev); 4518 4519 /* check if we got any *new* reset requests to be honored */ 4520 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request); 4521 if (hdev->reset_type != HNAE3_NONE_RESET) 4522 hclge_do_reset(hdev); 4523 4524 hdev->reset_type = HNAE3_NONE_RESET; 4525 } 4526 4527 static void hclge_handle_err_reset_request(struct hclge_dev *hdev) 4528 { 4529 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4530 enum hnae3_reset_type reset_type; 4531 4532 if (ae_dev->hw_err_reset_req) { 4533 reset_type = hclge_get_reset_level(ae_dev, 4534 &ae_dev->hw_err_reset_req); 4535 hclge_set_def_reset_request(ae_dev, reset_type); 4536 } 4537 4538 if (hdev->default_reset_request && ae_dev->ops->reset_event) 4539 ae_dev->ops->reset_event(hdev->pdev, NULL); 4540 4541 /* enable interrupt after error handling complete */ 4542 hclge_enable_vector(&hdev->misc_vector, true); 4543 } 4544 4545 static void hclge_handle_err_recovery(struct hclge_dev *hdev) 4546 { 4547 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4548 4549 ae_dev->hw_err_reset_req = 0; 4550 4551 if (hclge_find_error_source(hdev)) { 4552 hclge_handle_error_info_log(ae_dev); 4553 hclge_handle_mac_tnl(hdev); 4554 } 4555 4556 hclge_handle_err_reset_request(hdev); 4557 } 4558 4559 static void hclge_misc_err_recovery(struct hclge_dev *hdev) 4560 { 4561 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4562 struct device *dev = &hdev->pdev->dev; 4563 u32 msix_sts_reg; 4564 4565 msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 4566 if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) { 4567 if (hclge_handle_hw_msix_error 4568 (hdev, &hdev->default_reset_request)) 4569 dev_info(dev, "received msix interrupt 0x%x\n", 4570 msix_sts_reg); 4571 } 4572 4573 hclge_handle_hw_ras_error(ae_dev); 4574 4575 hclge_handle_err_reset_request(hdev); 4576 } 4577 4578 static void hclge_errhand_service_task(struct hclge_dev *hdev) 4579 { 4580 if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 4581 return; 4582 4583 if (hnae3_dev_ras_imp_supported(hdev)) 4584 hclge_handle_err_recovery(hdev); 4585 else 4586 hclge_misc_err_recovery(hdev); 4587 } 4588 4589 static void hclge_reset_service_task(struct hclge_dev *hdev) 4590 { 4591 if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 4592 return; 4593 4594 if (time_is_before_jiffies(hdev->last_rst_scheduled + 4595 HCLGE_RESET_SCHED_TIMEOUT)) 4596 dev_warn(&hdev->pdev->dev, 4597 "reset service task is scheduled after %ums on cpu%u!\n", 4598 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled), 4599 smp_processor_id()); 4600 4601 down(&hdev->reset_sem); 4602 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4603 4604 hclge_reset_subtask(hdev); 4605 4606 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4607 up(&hdev->reset_sem); 4608 } 4609 4610 static void hclge_update_vport_alive(struct hclge_dev *hdev) 4611 { 4612 int i; 4613 4614 /* start from vport 1 for PF is always alive */ 4615 for (i = 1; i < hdev->num_alloc_vport; i++) { 4616 struct hclge_vport *vport = &hdev->vport[i]; 4617 4618 if (time_after(jiffies, vport->last_active_jiffies + 8 * HZ)) 4619 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 4620 4621 /* If vf is not alive, set to default value */ 4622 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 4623 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 4624 } 4625 } 4626 4627 static void hclge_periodic_service_task(struct hclge_dev *hdev) 4628 { 4629 unsigned long delta = round_jiffies_relative(HZ); 4630 4631 if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 4632 return; 4633 4634 /* Always handle the link updating to make sure link state is 4635 * updated when it is triggered by mbx. 4636 */ 4637 hclge_update_link_status(hdev); 4638 hclge_sync_mac_table(hdev); 4639 hclge_sync_promisc_mode(hdev); 4640 hclge_sync_fd_table(hdev); 4641 4642 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 4643 delta = jiffies - hdev->last_serv_processed; 4644 4645 if (delta < round_jiffies_relative(HZ)) { 4646 delta = round_jiffies_relative(HZ) - delta; 4647 goto out; 4648 } 4649 } 4650 4651 hdev->serv_processed_cnt++; 4652 hclge_update_vport_alive(hdev); 4653 4654 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) { 4655 hdev->last_serv_processed = jiffies; 4656 goto out; 4657 } 4658 4659 if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL)) 4660 hclge_update_stats_for_all(hdev); 4661 4662 hclge_update_port_info(hdev); 4663 hclge_sync_vlan_filter(hdev); 4664 4665 if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL)) 4666 hclge_rfs_filter_expire(hdev); 4667 4668 hdev->last_serv_processed = jiffies; 4669 4670 out: 4671 hclge_task_schedule(hdev, delta); 4672 } 4673 4674 static void hclge_ptp_service_task(struct hclge_dev *hdev) 4675 { 4676 unsigned long flags; 4677 4678 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) || 4679 !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) || 4680 !time_is_before_jiffies(hdev->ptp->tx_start + HZ)) 4681 return; 4682 4683 /* to prevent concurrence with the irq handler */ 4684 spin_lock_irqsave(&hdev->ptp->lock, flags); 4685 4686 /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq 4687 * handler may handle it just before spin_lock_irqsave(). 4688 */ 4689 if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) 4690 hclge_ptp_clean_tx_hwts(hdev); 4691 4692 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 4693 } 4694 4695 static void hclge_service_task(struct work_struct *work) 4696 { 4697 struct hclge_dev *hdev = 4698 container_of(work, struct hclge_dev, service_task.work); 4699 4700 hclge_errhand_service_task(hdev); 4701 hclge_reset_service_task(hdev); 4702 hclge_ptp_service_task(hdev); 4703 hclge_mailbox_service_task(hdev); 4704 hclge_periodic_service_task(hdev); 4705 4706 /* Handle error recovery, reset and mbx again in case periodical task 4707 * delays the handling by calling hclge_task_schedule() in 4708 * hclge_periodic_service_task(). 4709 */ 4710 hclge_errhand_service_task(hdev); 4711 hclge_reset_service_task(hdev); 4712 hclge_mailbox_service_task(hdev); 4713 } 4714 4715 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 4716 { 4717 /* VF handle has no client */ 4718 if (!handle->client) 4719 return container_of(handle, struct hclge_vport, nic); 4720 else if (handle->client->type == HNAE3_CLIENT_ROCE) 4721 return container_of(handle, struct hclge_vport, roce); 4722 else 4723 return container_of(handle, struct hclge_vport, nic); 4724 } 4725 4726 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx, 4727 struct hnae3_vector_info *vector_info) 4728 { 4729 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 64 4730 4731 vector_info->vector = pci_irq_vector(hdev->pdev, idx); 4732 4733 /* need an extend offset to config vector >= 64 */ 4734 if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2) 4735 vector_info->io_addr = hdev->hw.hw.io_base + 4736 HCLGE_VECTOR_REG_BASE + 4737 (idx - 1) * HCLGE_VECTOR_REG_OFFSET; 4738 else 4739 vector_info->io_addr = hdev->hw.hw.io_base + 4740 HCLGE_VECTOR_EXT_REG_BASE + 4741 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4742 HCLGE_VECTOR_REG_OFFSET_H + 4743 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4744 HCLGE_VECTOR_REG_OFFSET; 4745 4746 hdev->vector_status[idx] = hdev->vport[0].vport_id; 4747 hdev->vector_irq[idx] = vector_info->vector; 4748 } 4749 4750 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 4751 struct hnae3_vector_info *vector_info) 4752 { 4753 struct hclge_vport *vport = hclge_get_vport(handle); 4754 struct hnae3_vector_info *vector = vector_info; 4755 struct hclge_dev *hdev = vport->back; 4756 int alloc = 0; 4757 u16 i = 0; 4758 u16 j; 4759 4760 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num); 4761 vector_num = min(hdev->num_msi_left, vector_num); 4762 4763 for (j = 0; j < vector_num; j++) { 4764 while (++i < hdev->num_nic_msi) { 4765 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 4766 hclge_get_vector_info(hdev, i, vector); 4767 vector++; 4768 alloc++; 4769 4770 break; 4771 } 4772 } 4773 } 4774 hdev->num_msi_left -= alloc; 4775 hdev->num_msi_used += alloc; 4776 4777 return alloc; 4778 } 4779 4780 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 4781 { 4782 int i; 4783 4784 for (i = 0; i < hdev->num_msi; i++) 4785 if (vector == hdev->vector_irq[i]) 4786 return i; 4787 4788 return -EINVAL; 4789 } 4790 4791 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 4792 { 4793 struct hclge_vport *vport = hclge_get_vport(handle); 4794 struct hclge_dev *hdev = vport->back; 4795 int vector_id; 4796 4797 vector_id = hclge_get_vector_index(hdev, vector); 4798 if (vector_id < 0) { 4799 dev_err(&hdev->pdev->dev, 4800 "Get vector index fail. vector = %d\n", vector); 4801 return vector_id; 4802 } 4803 4804 hclge_free_vector(hdev, vector_id); 4805 4806 return 0; 4807 } 4808 4809 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 4810 u8 *key, u8 *hfunc) 4811 { 4812 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4813 struct hclge_vport *vport = hclge_get_vport(handle); 4814 struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg; 4815 4816 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 4817 4818 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 4819 ae_dev->dev_specs.rss_ind_tbl_size); 4820 4821 return 0; 4822 } 4823 4824 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 4825 const u8 *key, const u8 hfunc) 4826 { 4827 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4828 struct hclge_vport *vport = hclge_get_vport(handle); 4829 struct hclge_dev *hdev = vport->back; 4830 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 4831 int ret, i; 4832 4833 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc); 4834 if (ret) { 4835 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc); 4836 return ret; 4837 } 4838 4839 /* Update the shadow RSS table with user specified qids */ 4840 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 4841 rss_cfg->rss_indirection_tbl[i] = indir[i]; 4842 4843 /* Update the hardware */ 4844 return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw, 4845 rss_cfg->rss_indirection_tbl); 4846 } 4847 4848 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 4849 struct ethtool_rxnfc *nfc) 4850 { 4851 struct hclge_vport *vport = hclge_get_vport(handle); 4852 struct hclge_dev *hdev = vport->back; 4853 int ret; 4854 4855 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 4856 &hdev->rss_cfg, nfc); 4857 if (ret) { 4858 dev_err(&hdev->pdev->dev, 4859 "failed to set rss tuple, ret = %d.\n", ret); 4860 return ret; 4861 } 4862 4863 return 0; 4864 } 4865 4866 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 4867 struct ethtool_rxnfc *nfc) 4868 { 4869 struct hclge_vport *vport = hclge_get_vport(handle); 4870 u8 tuple_sets; 4871 int ret; 4872 4873 nfc->data = 0; 4874 4875 ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type, 4876 &tuple_sets); 4877 if (ret || !tuple_sets) 4878 return ret; 4879 4880 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 4881 4882 return 0; 4883 } 4884 4885 static int hclge_get_tc_size(struct hnae3_handle *handle) 4886 { 4887 struct hclge_vport *vport = hclge_get_vport(handle); 4888 struct hclge_dev *hdev = vport->back; 4889 4890 return hdev->pf_rss_size_max; 4891 } 4892 4893 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev) 4894 { 4895 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 4896 struct hclge_vport *vport = hdev->vport; 4897 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 4898 u16 tc_valid[HCLGE_MAX_TC_NUM] = {0}; 4899 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 4900 struct hnae3_tc_info *tc_info; 4901 u16 roundup_size; 4902 u16 rss_size; 4903 int i; 4904 4905 tc_info = &vport->nic.kinfo.tc_info; 4906 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 4907 rss_size = tc_info->tqp_count[i]; 4908 tc_valid[i] = 0; 4909 4910 if (!(hdev->hw_tc_map & BIT(i))) 4911 continue; 4912 4913 /* tc_size set to hardware is the log2 of roundup power of two 4914 * of rss_size, the acutal queue size is limited by indirection 4915 * table. 4916 */ 4917 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size || 4918 rss_size == 0) { 4919 dev_err(&hdev->pdev->dev, 4920 "Configure rss tc size failed, invalid TC_SIZE = %u\n", 4921 rss_size); 4922 return -EINVAL; 4923 } 4924 4925 roundup_size = roundup_pow_of_two(rss_size); 4926 roundup_size = ilog2(roundup_size); 4927 4928 tc_valid[i] = 1; 4929 tc_size[i] = roundup_size; 4930 tc_offset[i] = tc_info->tqp_offset[i]; 4931 } 4932 4933 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 4934 tc_size); 4935 } 4936 4937 int hclge_rss_init_hw(struct hclge_dev *hdev) 4938 { 4939 u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl; 4940 u8 *key = hdev->rss_cfg.rss_hash_key; 4941 u8 hfunc = hdev->rss_cfg.rss_algo; 4942 int ret; 4943 4944 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 4945 rss_indir); 4946 if (ret) 4947 return ret; 4948 4949 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key); 4950 if (ret) 4951 return ret; 4952 4953 ret = hclge_comm_set_rss_input_tuple(&hdev->vport[0].nic, 4954 &hdev->hw.hw, true, 4955 &hdev->rss_cfg); 4956 if (ret) 4957 return ret; 4958 4959 return hclge_init_rss_tc_mode(hdev); 4960 } 4961 4962 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 4963 int vector_id, bool en, 4964 struct hnae3_ring_chain_node *ring_chain) 4965 { 4966 struct hclge_dev *hdev = vport->back; 4967 struct hnae3_ring_chain_node *node; 4968 struct hclge_desc desc; 4969 struct hclge_ctrl_vector_chain_cmd *req = 4970 (struct hclge_ctrl_vector_chain_cmd *)desc.data; 4971 enum hclge_comm_cmd_status status; 4972 enum hclge_opcode_type op; 4973 u16 tqp_type_and_id; 4974 int i; 4975 4976 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 4977 hclge_cmd_setup_basic_desc(&desc, op, false); 4978 req->int_vector_id_l = hnae3_get_field(vector_id, 4979 HCLGE_VECTOR_ID_L_M, 4980 HCLGE_VECTOR_ID_L_S); 4981 req->int_vector_id_h = hnae3_get_field(vector_id, 4982 HCLGE_VECTOR_ID_H_M, 4983 HCLGE_VECTOR_ID_H_S); 4984 4985 i = 0; 4986 for (node = ring_chain; node; node = node->next) { 4987 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 4988 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 4989 HCLGE_INT_TYPE_S, 4990 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 4991 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 4992 HCLGE_TQP_ID_S, node->tqp_index); 4993 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 4994 HCLGE_INT_GL_IDX_S, 4995 hnae3_get_field(node->int_gl_idx, 4996 HNAE3_RING_GL_IDX_M, 4997 HNAE3_RING_GL_IDX_S)); 4998 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 4999 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 5000 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 5001 req->vfid = vport->vport_id; 5002 5003 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5004 if (status) { 5005 dev_err(&hdev->pdev->dev, 5006 "Map TQP fail, status is %d.\n", 5007 status); 5008 return -EIO; 5009 } 5010 i = 0; 5011 5012 hclge_cmd_setup_basic_desc(&desc, 5013 op, 5014 false); 5015 req->int_vector_id_l = 5016 hnae3_get_field(vector_id, 5017 HCLGE_VECTOR_ID_L_M, 5018 HCLGE_VECTOR_ID_L_S); 5019 req->int_vector_id_h = 5020 hnae3_get_field(vector_id, 5021 HCLGE_VECTOR_ID_H_M, 5022 HCLGE_VECTOR_ID_H_S); 5023 } 5024 } 5025 5026 if (i > 0) { 5027 req->int_cause_num = i; 5028 req->vfid = vport->vport_id; 5029 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5030 if (status) { 5031 dev_err(&hdev->pdev->dev, 5032 "Map TQP fail, status is %d.\n", status); 5033 return -EIO; 5034 } 5035 } 5036 5037 return 0; 5038 } 5039 5040 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector, 5041 struct hnae3_ring_chain_node *ring_chain) 5042 { 5043 struct hclge_vport *vport = hclge_get_vport(handle); 5044 struct hclge_dev *hdev = vport->back; 5045 int vector_id; 5046 5047 vector_id = hclge_get_vector_index(hdev, vector); 5048 if (vector_id < 0) { 5049 dev_err(&hdev->pdev->dev, 5050 "failed to get vector index. vector=%d\n", vector); 5051 return vector_id; 5052 } 5053 5054 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 5055 } 5056 5057 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector, 5058 struct hnae3_ring_chain_node *ring_chain) 5059 { 5060 struct hclge_vport *vport = hclge_get_vport(handle); 5061 struct hclge_dev *hdev = vport->back; 5062 int vector_id, ret; 5063 5064 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 5065 return 0; 5066 5067 vector_id = hclge_get_vector_index(hdev, vector); 5068 if (vector_id < 0) { 5069 dev_err(&handle->pdev->dev, 5070 "Get vector index fail. ret =%d\n", vector_id); 5071 return vector_id; 5072 } 5073 5074 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 5075 if (ret) 5076 dev_err(&handle->pdev->dev, 5077 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 5078 vector_id, ret); 5079 5080 return ret; 5081 } 5082 5083 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id, 5084 bool en_uc, bool en_mc, bool en_bc) 5085 { 5086 struct hclge_vport *vport = &hdev->vport[vf_id]; 5087 struct hnae3_handle *handle = &vport->nic; 5088 struct hclge_promisc_cfg_cmd *req; 5089 struct hclge_desc desc; 5090 bool uc_tx_en = en_uc; 5091 u8 promisc_cfg = 0; 5092 int ret; 5093 5094 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 5095 5096 req = (struct hclge_promisc_cfg_cmd *)desc.data; 5097 req->vf_id = vf_id; 5098 5099 if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags)) 5100 uc_tx_en = false; 5101 5102 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0); 5103 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0); 5104 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0); 5105 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0); 5106 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0); 5107 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0); 5108 req->extend_promisc = promisc_cfg; 5109 5110 /* to be compatible with DEVICE_VERSION_V1/2 */ 5111 promisc_cfg = 0; 5112 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0); 5113 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0); 5114 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0); 5115 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1); 5116 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1); 5117 req->promisc = promisc_cfg; 5118 5119 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5120 if (ret) 5121 dev_err(&hdev->pdev->dev, 5122 "failed to set vport %u promisc mode, ret = %d.\n", 5123 vf_id, ret); 5124 5125 return ret; 5126 } 5127 5128 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 5129 bool en_mc_pmc, bool en_bc_pmc) 5130 { 5131 return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id, 5132 en_uc_pmc, en_mc_pmc, en_bc_pmc); 5133 } 5134 5135 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 5136 bool en_mc_pmc) 5137 { 5138 struct hclge_vport *vport = hclge_get_vport(handle); 5139 struct hclge_dev *hdev = vport->back; 5140 bool en_bc_pmc = true; 5141 5142 /* For device whose version below V2, if broadcast promisc enabled, 5143 * vlan filter is always bypassed. So broadcast promisc should be 5144 * disabled until user enable promisc mode 5145 */ 5146 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 5147 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false; 5148 5149 return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc, 5150 en_bc_pmc); 5151 } 5152 5153 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle) 5154 { 5155 struct hclge_vport *vport = hclge_get_vport(handle); 5156 5157 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5158 } 5159 5160 static void hclge_sync_fd_state(struct hclge_dev *hdev) 5161 { 5162 if (hlist_empty(&hdev->fd_rule_list)) 5163 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 5164 } 5165 5166 static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location) 5167 { 5168 if (!test_bit(location, hdev->fd_bmap)) { 5169 set_bit(location, hdev->fd_bmap); 5170 hdev->hclge_fd_rule_num++; 5171 } 5172 } 5173 5174 static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location) 5175 { 5176 if (test_bit(location, hdev->fd_bmap)) { 5177 clear_bit(location, hdev->fd_bmap); 5178 hdev->hclge_fd_rule_num--; 5179 } 5180 } 5181 5182 static void hclge_fd_free_node(struct hclge_dev *hdev, 5183 struct hclge_fd_rule *rule) 5184 { 5185 hlist_del(&rule->rule_node); 5186 kfree(rule); 5187 hclge_sync_fd_state(hdev); 5188 } 5189 5190 static void hclge_update_fd_rule_node(struct hclge_dev *hdev, 5191 struct hclge_fd_rule *old_rule, 5192 struct hclge_fd_rule *new_rule, 5193 enum HCLGE_FD_NODE_STATE state) 5194 { 5195 switch (state) { 5196 case HCLGE_FD_TO_ADD: 5197 case HCLGE_FD_ACTIVE: 5198 /* 1) if the new state is TO_ADD, just replace the old rule 5199 * with the same location, no matter its state, because the 5200 * new rule will be configured to the hardware. 5201 * 2) if the new state is ACTIVE, it means the new rule 5202 * has been configured to the hardware, so just replace 5203 * the old rule node with the same location. 5204 * 3) for it doesn't add a new node to the list, so it's 5205 * unnecessary to update the rule number and fd_bmap. 5206 */ 5207 new_rule->rule_node.next = old_rule->rule_node.next; 5208 new_rule->rule_node.pprev = old_rule->rule_node.pprev; 5209 memcpy(old_rule, new_rule, sizeof(*old_rule)); 5210 kfree(new_rule); 5211 break; 5212 case HCLGE_FD_DELETED: 5213 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5214 hclge_fd_free_node(hdev, old_rule); 5215 break; 5216 case HCLGE_FD_TO_DEL: 5217 /* if new request is TO_DEL, and old rule is existent 5218 * 1) the state of old rule is TO_DEL, we need do nothing, 5219 * because we delete rule by location, other rule content 5220 * is unncessary. 5221 * 2) the state of old rule is ACTIVE, we need to change its 5222 * state to TO_DEL, so the rule will be deleted when periodic 5223 * task being scheduled. 5224 * 3) the state of old rule is TO_ADD, it means the rule hasn't 5225 * been added to hardware, so we just delete the rule node from 5226 * fd_rule_list directly. 5227 */ 5228 if (old_rule->state == HCLGE_FD_TO_ADD) { 5229 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5230 hclge_fd_free_node(hdev, old_rule); 5231 return; 5232 } 5233 old_rule->state = HCLGE_FD_TO_DEL; 5234 break; 5235 } 5236 } 5237 5238 static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist, 5239 u16 location, 5240 struct hclge_fd_rule **parent) 5241 { 5242 struct hclge_fd_rule *rule; 5243 struct hlist_node *node; 5244 5245 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 5246 if (rule->location == location) 5247 return rule; 5248 else if (rule->location > location) 5249 return NULL; 5250 /* record the parent node, use to keep the nodes in fd_rule_list 5251 * in ascend order. 5252 */ 5253 *parent = rule; 5254 } 5255 5256 return NULL; 5257 } 5258 5259 /* insert fd rule node in ascend order according to rule->location */ 5260 static void hclge_fd_insert_rule_node(struct hlist_head *hlist, 5261 struct hclge_fd_rule *rule, 5262 struct hclge_fd_rule *parent) 5263 { 5264 INIT_HLIST_NODE(&rule->rule_node); 5265 5266 if (parent) 5267 hlist_add_behind(&rule->rule_node, &parent->rule_node); 5268 else 5269 hlist_add_head(&rule->rule_node, hlist); 5270 } 5271 5272 static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev, 5273 struct hclge_fd_user_def_cfg *cfg) 5274 { 5275 struct hclge_fd_user_def_cfg_cmd *req; 5276 struct hclge_desc desc; 5277 u16 data = 0; 5278 int ret; 5279 5280 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false); 5281 5282 req = (struct hclge_fd_user_def_cfg_cmd *)desc.data; 5283 5284 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0); 5285 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5286 HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset); 5287 req->ol2_cfg = cpu_to_le16(data); 5288 5289 data = 0; 5290 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0); 5291 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5292 HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset); 5293 req->ol3_cfg = cpu_to_le16(data); 5294 5295 data = 0; 5296 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0); 5297 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5298 HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset); 5299 req->ol4_cfg = cpu_to_le16(data); 5300 5301 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5302 if (ret) 5303 dev_err(&hdev->pdev->dev, 5304 "failed to set fd user def data, ret= %d\n", ret); 5305 return ret; 5306 } 5307 5308 static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked) 5309 { 5310 int ret; 5311 5312 if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state)) 5313 return; 5314 5315 if (!locked) 5316 spin_lock_bh(&hdev->fd_rule_lock); 5317 5318 ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg); 5319 if (ret) 5320 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5321 5322 if (!locked) 5323 spin_unlock_bh(&hdev->fd_rule_lock); 5324 } 5325 5326 static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev, 5327 struct hclge_fd_rule *rule) 5328 { 5329 struct hlist_head *hlist = &hdev->fd_rule_list; 5330 struct hclge_fd_rule *fd_rule, *parent = NULL; 5331 struct hclge_fd_user_def_info *info, *old_info; 5332 struct hclge_fd_user_def_cfg *cfg; 5333 5334 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5335 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5336 return 0; 5337 5338 /* for valid layer is start from 1, so need minus 1 to get the cfg */ 5339 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5340 info = &rule->ep.user_def; 5341 5342 if (!cfg->ref_cnt || cfg->offset == info->offset) 5343 return 0; 5344 5345 if (cfg->ref_cnt > 1) 5346 goto error; 5347 5348 fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent); 5349 if (fd_rule) { 5350 old_info = &fd_rule->ep.user_def; 5351 if (info->layer == old_info->layer) 5352 return 0; 5353 } 5354 5355 error: 5356 dev_err(&hdev->pdev->dev, 5357 "No available offset for layer%d fd rule, each layer only support one user def offset.\n", 5358 info->layer + 1); 5359 return -ENOSPC; 5360 } 5361 5362 static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev, 5363 struct hclge_fd_rule *rule) 5364 { 5365 struct hclge_fd_user_def_cfg *cfg; 5366 5367 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5368 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5369 return; 5370 5371 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5372 if (!cfg->ref_cnt) { 5373 cfg->offset = rule->ep.user_def.offset; 5374 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5375 } 5376 cfg->ref_cnt++; 5377 } 5378 5379 static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev, 5380 struct hclge_fd_rule *rule) 5381 { 5382 struct hclge_fd_user_def_cfg *cfg; 5383 5384 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5385 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5386 return; 5387 5388 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5389 if (!cfg->ref_cnt) 5390 return; 5391 5392 cfg->ref_cnt--; 5393 if (!cfg->ref_cnt) { 5394 cfg->offset = 0; 5395 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5396 } 5397 } 5398 5399 static void hclge_update_fd_list(struct hclge_dev *hdev, 5400 enum HCLGE_FD_NODE_STATE state, u16 location, 5401 struct hclge_fd_rule *new_rule) 5402 { 5403 struct hlist_head *hlist = &hdev->fd_rule_list; 5404 struct hclge_fd_rule *fd_rule, *parent = NULL; 5405 5406 fd_rule = hclge_find_fd_rule(hlist, location, &parent); 5407 if (fd_rule) { 5408 hclge_fd_dec_user_def_refcnt(hdev, fd_rule); 5409 if (state == HCLGE_FD_ACTIVE) 5410 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5411 hclge_sync_fd_user_def_cfg(hdev, true); 5412 5413 hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state); 5414 return; 5415 } 5416 5417 /* it's unlikely to fail here, because we have checked the rule 5418 * exist before. 5419 */ 5420 if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) { 5421 dev_warn(&hdev->pdev->dev, 5422 "failed to delete fd rule %u, it's inexistent\n", 5423 location); 5424 return; 5425 } 5426 5427 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5428 hclge_sync_fd_user_def_cfg(hdev, true); 5429 5430 hclge_fd_insert_rule_node(hlist, new_rule, parent); 5431 hclge_fd_inc_rule_cnt(hdev, new_rule->location); 5432 5433 if (state == HCLGE_FD_TO_ADD) { 5434 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 5435 hclge_task_schedule(hdev, 0); 5436 } 5437 } 5438 5439 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode) 5440 { 5441 struct hclge_get_fd_mode_cmd *req; 5442 struct hclge_desc desc; 5443 int ret; 5444 5445 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true); 5446 5447 req = (struct hclge_get_fd_mode_cmd *)desc.data; 5448 5449 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5450 if (ret) { 5451 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret); 5452 return ret; 5453 } 5454 5455 *fd_mode = req->mode; 5456 5457 return ret; 5458 } 5459 5460 static int hclge_get_fd_allocation(struct hclge_dev *hdev, 5461 u32 *stage1_entry_num, 5462 u32 *stage2_entry_num, 5463 u16 *stage1_counter_num, 5464 u16 *stage2_counter_num) 5465 { 5466 struct hclge_get_fd_allocation_cmd *req; 5467 struct hclge_desc desc; 5468 int ret; 5469 5470 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true); 5471 5472 req = (struct hclge_get_fd_allocation_cmd *)desc.data; 5473 5474 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5475 if (ret) { 5476 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n", 5477 ret); 5478 return ret; 5479 } 5480 5481 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num); 5482 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num); 5483 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num); 5484 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num); 5485 5486 return ret; 5487 } 5488 5489 static int hclge_set_fd_key_config(struct hclge_dev *hdev, 5490 enum HCLGE_FD_STAGE stage_num) 5491 { 5492 struct hclge_set_fd_key_config_cmd *req; 5493 struct hclge_fd_key_cfg *stage; 5494 struct hclge_desc desc; 5495 int ret; 5496 5497 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false); 5498 5499 req = (struct hclge_set_fd_key_config_cmd *)desc.data; 5500 stage = &hdev->fd_cfg.key_cfg[stage_num]; 5501 req->stage = stage_num; 5502 req->key_select = stage->key_sel; 5503 req->inner_sipv6_word_en = stage->inner_sipv6_word_en; 5504 req->inner_dipv6_word_en = stage->inner_dipv6_word_en; 5505 req->outer_sipv6_word_en = stage->outer_sipv6_word_en; 5506 req->outer_dipv6_word_en = stage->outer_dipv6_word_en; 5507 req->tuple_mask = cpu_to_le32(~stage->tuple_active); 5508 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active); 5509 5510 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5511 if (ret) 5512 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret); 5513 5514 return ret; 5515 } 5516 5517 static void hclge_fd_disable_user_def(struct hclge_dev *hdev) 5518 { 5519 struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg; 5520 5521 spin_lock_bh(&hdev->fd_rule_lock); 5522 memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg)); 5523 spin_unlock_bh(&hdev->fd_rule_lock); 5524 5525 hclge_fd_set_user_def_cmd(hdev, cfg); 5526 } 5527 5528 static int hclge_init_fd_config(struct hclge_dev *hdev) 5529 { 5530 #define LOW_2_WORDS 0x03 5531 struct hclge_fd_key_cfg *key_cfg; 5532 int ret; 5533 5534 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 5535 return 0; 5536 5537 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode); 5538 if (ret) 5539 return ret; 5540 5541 switch (hdev->fd_cfg.fd_mode) { 5542 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1: 5543 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH; 5544 break; 5545 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1: 5546 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2; 5547 break; 5548 default: 5549 dev_err(&hdev->pdev->dev, 5550 "Unsupported flow director mode %u\n", 5551 hdev->fd_cfg.fd_mode); 5552 return -EOPNOTSUPP; 5553 } 5554 5555 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1]; 5556 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE; 5557 key_cfg->inner_sipv6_word_en = LOW_2_WORDS; 5558 key_cfg->inner_dipv6_word_en = LOW_2_WORDS; 5559 key_cfg->outer_sipv6_word_en = 0; 5560 key_cfg->outer_dipv6_word_en = 0; 5561 5562 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) | 5563 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) | 5564 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5565 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5566 5567 /* If use max 400bit key, we can support tuples for ether type */ 5568 if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 5569 key_cfg->tuple_active |= 5570 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC); 5571 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5572 key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 5573 } 5574 5575 /* roce_type is used to filter roce frames 5576 * dst_vport is used to specify the rule 5577 */ 5578 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT); 5579 5580 ret = hclge_get_fd_allocation(hdev, 5581 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1], 5582 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2], 5583 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1], 5584 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]); 5585 if (ret) 5586 return ret; 5587 5588 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1); 5589 } 5590 5591 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x, 5592 int loc, u8 *key, bool is_add) 5593 { 5594 struct hclge_fd_tcam_config_1_cmd *req1; 5595 struct hclge_fd_tcam_config_2_cmd *req2; 5596 struct hclge_fd_tcam_config_3_cmd *req3; 5597 struct hclge_desc desc[3]; 5598 int ret; 5599 5600 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false); 5601 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5602 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false); 5603 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5604 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false); 5605 5606 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 5607 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 5608 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 5609 5610 req1->stage = stage; 5611 req1->xy_sel = sel_x ? 1 : 0; 5612 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0); 5613 req1->index = cpu_to_le32(loc); 5614 req1->entry_vld = sel_x ? is_add : 0; 5615 5616 if (key) { 5617 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data)); 5618 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)], 5619 sizeof(req2->tcam_data)); 5620 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) + 5621 sizeof(req2->tcam_data)], sizeof(req3->tcam_data)); 5622 } 5623 5624 ret = hclge_cmd_send(&hdev->hw, desc, 3); 5625 if (ret) 5626 dev_err(&hdev->pdev->dev, 5627 "config tcam key fail, ret=%d\n", 5628 ret); 5629 5630 return ret; 5631 } 5632 5633 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc, 5634 struct hclge_fd_ad_data *action) 5635 { 5636 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 5637 struct hclge_fd_ad_config_cmd *req; 5638 struct hclge_desc desc; 5639 u64 ad_data = 0; 5640 int ret; 5641 5642 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false); 5643 5644 req = (struct hclge_fd_ad_config_cmd *)desc.data; 5645 req->index = cpu_to_le32(loc); 5646 req->stage = stage; 5647 5648 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B, 5649 action->write_rule_id_to_bd); 5650 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S, 5651 action->rule_id); 5652 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) { 5653 hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B, 5654 action->override_tc); 5655 hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M, 5656 HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size); 5657 } 5658 ad_data <<= 32; 5659 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet); 5660 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B, 5661 action->forward_to_direct_queue); 5662 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S, 5663 action->queue_id); 5664 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter); 5665 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M, 5666 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id); 5667 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage); 5668 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S, 5669 action->counter_id); 5670 5671 req->ad_data = cpu_to_le64(ad_data); 5672 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5673 if (ret) 5674 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret); 5675 5676 return ret; 5677 } 5678 5679 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y, 5680 struct hclge_fd_rule *rule) 5681 { 5682 int offset, moffset, ip_offset; 5683 enum HCLGE_FD_KEY_OPT key_opt; 5684 u16 tmp_x_s, tmp_y_s; 5685 u32 tmp_x_l, tmp_y_l; 5686 u8 *p = (u8 *)rule; 5687 int i; 5688 5689 if (rule->unused_tuple & BIT(tuple_bit)) 5690 return true; 5691 5692 key_opt = tuple_key_info[tuple_bit].key_opt; 5693 offset = tuple_key_info[tuple_bit].offset; 5694 moffset = tuple_key_info[tuple_bit].moffset; 5695 5696 switch (key_opt) { 5697 case KEY_OPT_U8: 5698 calc_x(*key_x, p[offset], p[moffset]); 5699 calc_y(*key_y, p[offset], p[moffset]); 5700 5701 return true; 5702 case KEY_OPT_LE16: 5703 calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5704 calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5705 *(__le16 *)key_x = cpu_to_le16(tmp_x_s); 5706 *(__le16 *)key_y = cpu_to_le16(tmp_y_s); 5707 5708 return true; 5709 case KEY_OPT_LE32: 5710 calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5711 calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5712 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5713 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5714 5715 return true; 5716 case KEY_OPT_MAC: 5717 for (i = 0; i < ETH_ALEN; i++) { 5718 calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i], 5719 p[moffset + i]); 5720 calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i], 5721 p[moffset + i]); 5722 } 5723 5724 return true; 5725 case KEY_OPT_IP: 5726 ip_offset = IPV4_INDEX * sizeof(u32); 5727 calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]), 5728 *(u32 *)(&p[moffset + ip_offset])); 5729 calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]), 5730 *(u32 *)(&p[moffset + ip_offset])); 5731 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5732 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5733 5734 return true; 5735 default: 5736 return false; 5737 } 5738 } 5739 5740 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 5741 u8 vf_id, u8 network_port_id) 5742 { 5743 u32 port_number = 0; 5744 5745 if (port_type == HOST_PORT) { 5746 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S, 5747 pf_id); 5748 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S, 5749 vf_id); 5750 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT); 5751 } else { 5752 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M, 5753 HCLGE_NETWORK_PORT_ID_S, network_port_id); 5754 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT); 5755 } 5756 5757 return port_number; 5758 } 5759 5760 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg, 5761 __le32 *key_x, __le32 *key_y, 5762 struct hclge_fd_rule *rule) 5763 { 5764 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number; 5765 u8 cur_pos = 0, tuple_size, shift_bits; 5766 unsigned int i; 5767 5768 for (i = 0; i < MAX_META_DATA; i++) { 5769 tuple_size = meta_data_key_info[i].key_length; 5770 tuple_bit = key_cfg->meta_data_active & BIT(i); 5771 5772 switch (tuple_bit) { 5773 case BIT(ROCE_TYPE): 5774 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET); 5775 cur_pos += tuple_size; 5776 break; 5777 case BIT(DST_VPORT): 5778 port_number = hclge_get_port_number(HOST_PORT, 0, 5779 rule->vf_id, 0); 5780 hnae3_set_field(meta_data, 5781 GENMASK(cur_pos + tuple_size, cur_pos), 5782 cur_pos, port_number); 5783 cur_pos += tuple_size; 5784 break; 5785 default: 5786 break; 5787 } 5788 } 5789 5790 calc_x(tmp_x, meta_data, 0xFFFFFFFF); 5791 calc_y(tmp_y, meta_data, 0xFFFFFFFF); 5792 shift_bits = sizeof(meta_data) * 8 - cur_pos; 5793 5794 *key_x = cpu_to_le32(tmp_x << shift_bits); 5795 *key_y = cpu_to_le32(tmp_y << shift_bits); 5796 } 5797 5798 /* A complete key is combined with meta data key and tuple key. 5799 * Meta data key is stored at the MSB region, and tuple key is stored at 5800 * the LSB region, unused bits will be filled 0. 5801 */ 5802 static int hclge_config_key(struct hclge_dev *hdev, u8 stage, 5803 struct hclge_fd_rule *rule) 5804 { 5805 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage]; 5806 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES]; 5807 u8 *cur_key_x, *cur_key_y; 5808 u8 meta_data_region; 5809 u8 tuple_size; 5810 int ret; 5811 u32 i; 5812 5813 memset(key_x, 0, sizeof(key_x)); 5814 memset(key_y, 0, sizeof(key_y)); 5815 cur_key_x = key_x; 5816 cur_key_y = key_y; 5817 5818 for (i = 0; i < MAX_TUPLE; i++) { 5819 bool tuple_valid; 5820 5821 tuple_size = tuple_key_info[i].key_length / 8; 5822 if (!(key_cfg->tuple_active & BIT(i))) 5823 continue; 5824 5825 tuple_valid = hclge_fd_convert_tuple(i, cur_key_x, 5826 cur_key_y, rule); 5827 if (tuple_valid) { 5828 cur_key_x += tuple_size; 5829 cur_key_y += tuple_size; 5830 } 5831 } 5832 5833 meta_data_region = hdev->fd_cfg.max_key_length / 8 - 5834 MAX_META_DATA_LENGTH / 8; 5835 5836 hclge_fd_convert_meta_data(key_cfg, 5837 (__le32 *)(key_x + meta_data_region), 5838 (__le32 *)(key_y + meta_data_region), 5839 rule); 5840 5841 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y, 5842 true); 5843 if (ret) { 5844 dev_err(&hdev->pdev->dev, 5845 "fd key_y config fail, loc=%u, ret=%d\n", 5846 rule->queue_id, ret); 5847 return ret; 5848 } 5849 5850 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x, 5851 true); 5852 if (ret) 5853 dev_err(&hdev->pdev->dev, 5854 "fd key_x config fail, loc=%u, ret=%d\n", 5855 rule->queue_id, ret); 5856 return ret; 5857 } 5858 5859 static int hclge_config_action(struct hclge_dev *hdev, u8 stage, 5860 struct hclge_fd_rule *rule) 5861 { 5862 struct hclge_vport *vport = hdev->vport; 5863 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5864 struct hclge_fd_ad_data ad_data; 5865 5866 memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data)); 5867 ad_data.ad_id = rule->location; 5868 5869 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 5870 ad_data.drop_packet = true; 5871 } else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) { 5872 ad_data.override_tc = true; 5873 ad_data.queue_id = 5874 kinfo->tc_info.tqp_offset[rule->cls_flower.tc]; 5875 ad_data.tc_size = 5876 ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]); 5877 } else { 5878 ad_data.forward_to_direct_queue = true; 5879 ad_data.queue_id = rule->queue_id; 5880 } 5881 5882 if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) { 5883 ad_data.use_counter = true; 5884 ad_data.counter_id = rule->vf_id % 5885 hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]; 5886 } else { 5887 ad_data.use_counter = false; 5888 ad_data.counter_id = 0; 5889 } 5890 5891 ad_data.use_next_stage = false; 5892 ad_data.next_input_key = 0; 5893 5894 ad_data.write_rule_id_to_bd = true; 5895 ad_data.rule_id = rule->location; 5896 5897 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data); 5898 } 5899 5900 static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec, 5901 u32 *unused_tuple) 5902 { 5903 if (!spec || !unused_tuple) 5904 return -EINVAL; 5905 5906 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5907 5908 if (!spec->ip4src) 5909 *unused_tuple |= BIT(INNER_SRC_IP); 5910 5911 if (!spec->ip4dst) 5912 *unused_tuple |= BIT(INNER_DST_IP); 5913 5914 if (!spec->psrc) 5915 *unused_tuple |= BIT(INNER_SRC_PORT); 5916 5917 if (!spec->pdst) 5918 *unused_tuple |= BIT(INNER_DST_PORT); 5919 5920 if (!spec->tos) 5921 *unused_tuple |= BIT(INNER_IP_TOS); 5922 5923 return 0; 5924 } 5925 5926 static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec, 5927 u32 *unused_tuple) 5928 { 5929 if (!spec || !unused_tuple) 5930 return -EINVAL; 5931 5932 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5933 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5934 5935 if (!spec->ip4src) 5936 *unused_tuple |= BIT(INNER_SRC_IP); 5937 5938 if (!spec->ip4dst) 5939 *unused_tuple |= BIT(INNER_DST_IP); 5940 5941 if (!spec->tos) 5942 *unused_tuple |= BIT(INNER_IP_TOS); 5943 5944 if (!spec->proto) 5945 *unused_tuple |= BIT(INNER_IP_PROTO); 5946 5947 if (spec->l4_4_bytes) 5948 return -EOPNOTSUPP; 5949 5950 if (spec->ip_ver != ETH_RX_NFC_IP4) 5951 return -EOPNOTSUPP; 5952 5953 return 0; 5954 } 5955 5956 static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec, 5957 u32 *unused_tuple) 5958 { 5959 if (!spec || !unused_tuple) 5960 return -EINVAL; 5961 5962 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5963 5964 /* check whether src/dst ip address used */ 5965 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5966 *unused_tuple |= BIT(INNER_SRC_IP); 5967 5968 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5969 *unused_tuple |= BIT(INNER_DST_IP); 5970 5971 if (!spec->psrc) 5972 *unused_tuple |= BIT(INNER_SRC_PORT); 5973 5974 if (!spec->pdst) 5975 *unused_tuple |= BIT(INNER_DST_PORT); 5976 5977 if (!spec->tclass) 5978 *unused_tuple |= BIT(INNER_IP_TOS); 5979 5980 return 0; 5981 } 5982 5983 static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec, 5984 u32 *unused_tuple) 5985 { 5986 if (!spec || !unused_tuple) 5987 return -EINVAL; 5988 5989 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5990 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5991 5992 /* check whether src/dst ip address used */ 5993 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5994 *unused_tuple |= BIT(INNER_SRC_IP); 5995 5996 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5997 *unused_tuple |= BIT(INNER_DST_IP); 5998 5999 if (!spec->l4_proto) 6000 *unused_tuple |= BIT(INNER_IP_PROTO); 6001 6002 if (!spec->tclass) 6003 *unused_tuple |= BIT(INNER_IP_TOS); 6004 6005 if (spec->l4_4_bytes) 6006 return -EOPNOTSUPP; 6007 6008 return 0; 6009 } 6010 6011 static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple) 6012 { 6013 if (!spec || !unused_tuple) 6014 return -EINVAL; 6015 6016 *unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 6017 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) | 6018 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO); 6019 6020 if (is_zero_ether_addr(spec->h_source)) 6021 *unused_tuple |= BIT(INNER_SRC_MAC); 6022 6023 if (is_zero_ether_addr(spec->h_dest)) 6024 *unused_tuple |= BIT(INNER_DST_MAC); 6025 6026 if (!spec->h_proto) 6027 *unused_tuple |= BIT(INNER_ETH_TYPE); 6028 6029 return 0; 6030 } 6031 6032 static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev, 6033 struct ethtool_rx_flow_spec *fs, 6034 u32 *unused_tuple) 6035 { 6036 if (fs->flow_type & FLOW_EXT) { 6037 if (fs->h_ext.vlan_etype) { 6038 dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n"); 6039 return -EOPNOTSUPP; 6040 } 6041 6042 if (!fs->h_ext.vlan_tci) 6043 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6044 6045 if (fs->m_ext.vlan_tci && 6046 be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) { 6047 dev_err(&hdev->pdev->dev, 6048 "failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n", 6049 ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1); 6050 return -EINVAL; 6051 } 6052 } else { 6053 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6054 } 6055 6056 if (fs->flow_type & FLOW_MAC_EXT) { 6057 if (hdev->fd_cfg.fd_mode != 6058 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6059 dev_err(&hdev->pdev->dev, 6060 "FLOW_MAC_EXT is not supported in current fd mode!\n"); 6061 return -EOPNOTSUPP; 6062 } 6063 6064 if (is_zero_ether_addr(fs->h_ext.h_dest)) 6065 *unused_tuple |= BIT(INNER_DST_MAC); 6066 else 6067 *unused_tuple &= ~BIT(INNER_DST_MAC); 6068 } 6069 6070 return 0; 6071 } 6072 6073 static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple, 6074 struct hclge_fd_user_def_info *info) 6075 { 6076 switch (flow_type) { 6077 case ETHER_FLOW: 6078 info->layer = HCLGE_FD_USER_DEF_L2; 6079 *unused_tuple &= ~BIT(INNER_L2_RSV); 6080 break; 6081 case IP_USER_FLOW: 6082 case IPV6_USER_FLOW: 6083 info->layer = HCLGE_FD_USER_DEF_L3; 6084 *unused_tuple &= ~BIT(INNER_L3_RSV); 6085 break; 6086 case TCP_V4_FLOW: 6087 case UDP_V4_FLOW: 6088 case TCP_V6_FLOW: 6089 case UDP_V6_FLOW: 6090 info->layer = HCLGE_FD_USER_DEF_L4; 6091 *unused_tuple &= ~BIT(INNER_L4_RSV); 6092 break; 6093 default: 6094 return -EOPNOTSUPP; 6095 } 6096 6097 return 0; 6098 } 6099 6100 static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs) 6101 { 6102 return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0; 6103 } 6104 6105 static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev, 6106 struct ethtool_rx_flow_spec *fs, 6107 u32 *unused_tuple, 6108 struct hclge_fd_user_def_info *info) 6109 { 6110 u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active; 6111 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6112 u16 data, offset, data_mask, offset_mask; 6113 int ret; 6114 6115 info->layer = HCLGE_FD_USER_DEF_NONE; 6116 *unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 6117 6118 if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs)) 6119 return 0; 6120 6121 /* user-def data from ethtool is 64 bit value, the bit0~15 is used 6122 * for data, and bit32~47 is used for offset. 6123 */ 6124 data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6125 data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6126 offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6127 offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6128 6129 if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) { 6130 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n"); 6131 return -EOPNOTSUPP; 6132 } 6133 6134 if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) { 6135 dev_err(&hdev->pdev->dev, 6136 "user-def offset[%u] should be no more than %u\n", 6137 offset, HCLGE_FD_MAX_USER_DEF_OFFSET); 6138 return -EINVAL; 6139 } 6140 6141 if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) { 6142 dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n"); 6143 return -EINVAL; 6144 } 6145 6146 ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info); 6147 if (ret) { 6148 dev_err(&hdev->pdev->dev, 6149 "unsupported flow type for user-def bytes, ret = %d\n", 6150 ret); 6151 return ret; 6152 } 6153 6154 info->data = data; 6155 info->data_mask = data_mask; 6156 info->offset = offset; 6157 6158 return 0; 6159 } 6160 6161 static int hclge_fd_check_spec(struct hclge_dev *hdev, 6162 struct ethtool_rx_flow_spec *fs, 6163 u32 *unused_tuple, 6164 struct hclge_fd_user_def_info *info) 6165 { 6166 u32 flow_type; 6167 int ret; 6168 6169 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 6170 dev_err(&hdev->pdev->dev, 6171 "failed to config fd rules, invalid rule location: %u, max is %u\n.", 6172 fs->location, 6173 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1); 6174 return -EINVAL; 6175 } 6176 6177 ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info); 6178 if (ret) 6179 return ret; 6180 6181 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6182 switch (flow_type) { 6183 case SCTP_V4_FLOW: 6184 case TCP_V4_FLOW: 6185 case UDP_V4_FLOW: 6186 ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec, 6187 unused_tuple); 6188 break; 6189 case IP_USER_FLOW: 6190 ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec, 6191 unused_tuple); 6192 break; 6193 case SCTP_V6_FLOW: 6194 case TCP_V6_FLOW: 6195 case UDP_V6_FLOW: 6196 ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec, 6197 unused_tuple); 6198 break; 6199 case IPV6_USER_FLOW: 6200 ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec, 6201 unused_tuple); 6202 break; 6203 case ETHER_FLOW: 6204 if (hdev->fd_cfg.fd_mode != 6205 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6206 dev_err(&hdev->pdev->dev, 6207 "ETHER_FLOW is not supported in current fd mode!\n"); 6208 return -EOPNOTSUPP; 6209 } 6210 6211 ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec, 6212 unused_tuple); 6213 break; 6214 default: 6215 dev_err(&hdev->pdev->dev, 6216 "unsupported protocol type, protocol type = %#x\n", 6217 flow_type); 6218 return -EOPNOTSUPP; 6219 } 6220 6221 if (ret) { 6222 dev_err(&hdev->pdev->dev, 6223 "failed to check flow union tuple, ret = %d\n", 6224 ret); 6225 return ret; 6226 } 6227 6228 return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple); 6229 } 6230 6231 static void hclge_fd_get_tcpip4_tuple(struct hclge_dev *hdev, 6232 struct ethtool_rx_flow_spec *fs, 6233 struct hclge_fd_rule *rule, u8 ip_proto) 6234 { 6235 rule->tuples.src_ip[IPV4_INDEX] = 6236 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src); 6237 rule->tuples_mask.src_ip[IPV4_INDEX] = 6238 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src); 6239 6240 rule->tuples.dst_ip[IPV4_INDEX] = 6241 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst); 6242 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6243 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst); 6244 6245 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc); 6246 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc); 6247 6248 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst); 6249 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst); 6250 6251 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos; 6252 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos; 6253 6254 rule->tuples.ether_proto = ETH_P_IP; 6255 rule->tuples_mask.ether_proto = 0xFFFF; 6256 6257 rule->tuples.ip_proto = ip_proto; 6258 rule->tuples_mask.ip_proto = 0xFF; 6259 } 6260 6261 static void hclge_fd_get_ip4_tuple(struct hclge_dev *hdev, 6262 struct ethtool_rx_flow_spec *fs, 6263 struct hclge_fd_rule *rule) 6264 { 6265 rule->tuples.src_ip[IPV4_INDEX] = 6266 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src); 6267 rule->tuples_mask.src_ip[IPV4_INDEX] = 6268 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src); 6269 6270 rule->tuples.dst_ip[IPV4_INDEX] = 6271 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst); 6272 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6273 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst); 6274 6275 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos; 6276 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos; 6277 6278 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto; 6279 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto; 6280 6281 rule->tuples.ether_proto = ETH_P_IP; 6282 rule->tuples_mask.ether_proto = 0xFFFF; 6283 } 6284 6285 static void hclge_fd_get_tcpip6_tuple(struct hclge_dev *hdev, 6286 struct ethtool_rx_flow_spec *fs, 6287 struct hclge_fd_rule *rule, u8 ip_proto) 6288 { 6289 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.tcp_ip6_spec.ip6src, 6290 IPV6_SIZE); 6291 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.tcp_ip6_spec.ip6src, 6292 IPV6_SIZE); 6293 6294 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.tcp_ip6_spec.ip6dst, 6295 IPV6_SIZE); 6296 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.tcp_ip6_spec.ip6dst, 6297 IPV6_SIZE); 6298 6299 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc); 6300 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc); 6301 6302 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst); 6303 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst); 6304 6305 rule->tuples.ether_proto = ETH_P_IPV6; 6306 rule->tuples_mask.ether_proto = 0xFFFF; 6307 6308 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6309 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6310 6311 rule->tuples.ip_proto = ip_proto; 6312 rule->tuples_mask.ip_proto = 0xFF; 6313 } 6314 6315 static void hclge_fd_get_ip6_tuple(struct hclge_dev *hdev, 6316 struct ethtool_rx_flow_spec *fs, 6317 struct hclge_fd_rule *rule) 6318 { 6319 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.usr_ip6_spec.ip6src, 6320 IPV6_SIZE); 6321 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.usr_ip6_spec.ip6src, 6322 IPV6_SIZE); 6323 6324 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.usr_ip6_spec.ip6dst, 6325 IPV6_SIZE); 6326 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.usr_ip6_spec.ip6dst, 6327 IPV6_SIZE); 6328 6329 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto; 6330 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto; 6331 6332 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6333 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6334 6335 rule->tuples.ether_proto = ETH_P_IPV6; 6336 rule->tuples_mask.ether_proto = 0xFFFF; 6337 } 6338 6339 static void hclge_fd_get_ether_tuple(struct hclge_dev *hdev, 6340 struct ethtool_rx_flow_spec *fs, 6341 struct hclge_fd_rule *rule) 6342 { 6343 ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source); 6344 ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source); 6345 6346 ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest); 6347 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest); 6348 6349 rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto); 6350 rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto); 6351 } 6352 6353 static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info, 6354 struct hclge_fd_rule *rule) 6355 { 6356 switch (info->layer) { 6357 case HCLGE_FD_USER_DEF_L2: 6358 rule->tuples.l2_user_def = info->data; 6359 rule->tuples_mask.l2_user_def = info->data_mask; 6360 break; 6361 case HCLGE_FD_USER_DEF_L3: 6362 rule->tuples.l3_user_def = info->data; 6363 rule->tuples_mask.l3_user_def = info->data_mask; 6364 break; 6365 case HCLGE_FD_USER_DEF_L4: 6366 rule->tuples.l4_user_def = (u32)info->data << 16; 6367 rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16; 6368 break; 6369 default: 6370 break; 6371 } 6372 6373 rule->ep.user_def = *info; 6374 } 6375 6376 static int hclge_fd_get_tuple(struct hclge_dev *hdev, 6377 struct ethtool_rx_flow_spec *fs, 6378 struct hclge_fd_rule *rule, 6379 struct hclge_fd_user_def_info *info) 6380 { 6381 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6382 6383 switch (flow_type) { 6384 case SCTP_V4_FLOW: 6385 hclge_fd_get_tcpip4_tuple(hdev, fs, rule, IPPROTO_SCTP); 6386 break; 6387 case TCP_V4_FLOW: 6388 hclge_fd_get_tcpip4_tuple(hdev, fs, rule, IPPROTO_TCP); 6389 break; 6390 case UDP_V4_FLOW: 6391 hclge_fd_get_tcpip4_tuple(hdev, fs, rule, IPPROTO_UDP); 6392 break; 6393 case IP_USER_FLOW: 6394 hclge_fd_get_ip4_tuple(hdev, fs, rule); 6395 break; 6396 case SCTP_V6_FLOW: 6397 hclge_fd_get_tcpip6_tuple(hdev, fs, rule, IPPROTO_SCTP); 6398 break; 6399 case TCP_V6_FLOW: 6400 hclge_fd_get_tcpip6_tuple(hdev, fs, rule, IPPROTO_TCP); 6401 break; 6402 case UDP_V6_FLOW: 6403 hclge_fd_get_tcpip6_tuple(hdev, fs, rule, IPPROTO_UDP); 6404 break; 6405 case IPV6_USER_FLOW: 6406 hclge_fd_get_ip6_tuple(hdev, fs, rule); 6407 break; 6408 case ETHER_FLOW: 6409 hclge_fd_get_ether_tuple(hdev, fs, rule); 6410 break; 6411 default: 6412 return -EOPNOTSUPP; 6413 } 6414 6415 if (fs->flow_type & FLOW_EXT) { 6416 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci); 6417 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci); 6418 hclge_fd_get_user_def_tuple(info, rule); 6419 } 6420 6421 if (fs->flow_type & FLOW_MAC_EXT) { 6422 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest); 6423 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest); 6424 } 6425 6426 return 0; 6427 } 6428 6429 static int hclge_fd_config_rule(struct hclge_dev *hdev, 6430 struct hclge_fd_rule *rule) 6431 { 6432 int ret; 6433 6434 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule); 6435 if (ret) 6436 return ret; 6437 6438 return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule); 6439 } 6440 6441 static int hclge_add_fd_entry_common(struct hclge_dev *hdev, 6442 struct hclge_fd_rule *rule) 6443 { 6444 int ret; 6445 6446 spin_lock_bh(&hdev->fd_rule_lock); 6447 6448 if (hdev->fd_active_type != rule->rule_type && 6449 (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6450 hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) { 6451 dev_err(&hdev->pdev->dev, 6452 "mode conflict(new type %d, active type %d), please delete existent rules first\n", 6453 rule->rule_type, hdev->fd_active_type); 6454 spin_unlock_bh(&hdev->fd_rule_lock); 6455 return -EINVAL; 6456 } 6457 6458 ret = hclge_fd_check_user_def_refcnt(hdev, rule); 6459 if (ret) 6460 goto out; 6461 6462 ret = hclge_clear_arfs_rules(hdev); 6463 if (ret) 6464 goto out; 6465 6466 ret = hclge_fd_config_rule(hdev, rule); 6467 if (ret) 6468 goto out; 6469 6470 rule->state = HCLGE_FD_ACTIVE; 6471 hdev->fd_active_type = rule->rule_type; 6472 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 6473 6474 out: 6475 spin_unlock_bh(&hdev->fd_rule_lock); 6476 return ret; 6477 } 6478 6479 static bool hclge_is_cls_flower_active(struct hnae3_handle *handle) 6480 { 6481 struct hclge_vport *vport = hclge_get_vport(handle); 6482 struct hclge_dev *hdev = vport->back; 6483 6484 return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE; 6485 } 6486 6487 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie, 6488 u16 *vport_id, u8 *action, u16 *queue_id) 6489 { 6490 struct hclge_vport *vport = hdev->vport; 6491 6492 if (ring_cookie == RX_CLS_FLOW_DISC) { 6493 *action = HCLGE_FD_ACTION_DROP_PACKET; 6494 } else { 6495 u32 ring = ethtool_get_flow_spec_ring(ring_cookie); 6496 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie); 6497 u16 tqps; 6498 6499 /* To keep consistent with user's configuration, minus 1 when 6500 * printing 'vf', because vf id from ethtool is added 1 for vf. 6501 */ 6502 if (vf > hdev->num_req_vfs) { 6503 dev_err(&hdev->pdev->dev, 6504 "Error: vf id (%u) should be less than %u\n", 6505 vf - 1U, hdev->num_req_vfs); 6506 return -EINVAL; 6507 } 6508 6509 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id; 6510 tqps = hdev->vport[vf].nic.kinfo.num_tqps; 6511 6512 if (ring >= tqps) { 6513 dev_err(&hdev->pdev->dev, 6514 "Error: queue id (%u) > max tqp num (%u)\n", 6515 ring, tqps - 1U); 6516 return -EINVAL; 6517 } 6518 6519 *action = HCLGE_FD_ACTION_SELECT_QUEUE; 6520 *queue_id = ring; 6521 } 6522 6523 return 0; 6524 } 6525 6526 static int hclge_add_fd_entry(struct hnae3_handle *handle, 6527 struct ethtool_rxnfc *cmd) 6528 { 6529 struct hclge_vport *vport = hclge_get_vport(handle); 6530 struct hclge_dev *hdev = vport->back; 6531 struct hclge_fd_user_def_info info; 6532 u16 dst_vport_id = 0, q_index = 0; 6533 struct ethtool_rx_flow_spec *fs; 6534 struct hclge_fd_rule *rule; 6535 u32 unused = 0; 6536 u8 action; 6537 int ret; 6538 6539 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 6540 dev_err(&hdev->pdev->dev, 6541 "flow table director is not supported\n"); 6542 return -EOPNOTSUPP; 6543 } 6544 6545 if (!hdev->fd_en) { 6546 dev_err(&hdev->pdev->dev, 6547 "please enable flow director first\n"); 6548 return -EOPNOTSUPP; 6549 } 6550 6551 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6552 6553 ret = hclge_fd_check_spec(hdev, fs, &unused, &info); 6554 if (ret) 6555 return ret; 6556 6557 ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id, 6558 &action, &q_index); 6559 if (ret) 6560 return ret; 6561 6562 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 6563 if (!rule) 6564 return -ENOMEM; 6565 6566 ret = hclge_fd_get_tuple(hdev, fs, rule, &info); 6567 if (ret) { 6568 kfree(rule); 6569 return ret; 6570 } 6571 6572 rule->flow_type = fs->flow_type; 6573 rule->location = fs->location; 6574 rule->unused_tuple = unused; 6575 rule->vf_id = dst_vport_id; 6576 rule->queue_id = q_index; 6577 rule->action = action; 6578 rule->rule_type = HCLGE_FD_EP_ACTIVE; 6579 6580 ret = hclge_add_fd_entry_common(hdev, rule); 6581 if (ret) 6582 kfree(rule); 6583 6584 return ret; 6585 } 6586 6587 static int hclge_del_fd_entry(struct hnae3_handle *handle, 6588 struct ethtool_rxnfc *cmd) 6589 { 6590 struct hclge_vport *vport = hclge_get_vport(handle); 6591 struct hclge_dev *hdev = vport->back; 6592 struct ethtool_rx_flow_spec *fs; 6593 int ret; 6594 6595 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6596 return -EOPNOTSUPP; 6597 6598 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6599 6600 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6601 return -EINVAL; 6602 6603 spin_lock_bh(&hdev->fd_rule_lock); 6604 if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6605 !test_bit(fs->location, hdev->fd_bmap)) { 6606 dev_err(&hdev->pdev->dev, 6607 "Delete fail, rule %u is inexistent\n", fs->location); 6608 spin_unlock_bh(&hdev->fd_rule_lock); 6609 return -ENOENT; 6610 } 6611 6612 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location, 6613 NULL, false); 6614 if (ret) 6615 goto out; 6616 6617 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL); 6618 6619 out: 6620 spin_unlock_bh(&hdev->fd_rule_lock); 6621 return ret; 6622 } 6623 6624 static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev, 6625 bool clear_list) 6626 { 6627 struct hclge_fd_rule *rule; 6628 struct hlist_node *node; 6629 u16 location; 6630 6631 spin_lock_bh(&hdev->fd_rule_lock); 6632 6633 for_each_set_bit(location, hdev->fd_bmap, 6634 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6635 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location, 6636 NULL, false); 6637 6638 if (clear_list) { 6639 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, 6640 rule_node) { 6641 hlist_del(&rule->rule_node); 6642 kfree(rule); 6643 } 6644 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 6645 hdev->hclge_fd_rule_num = 0; 6646 bitmap_zero(hdev->fd_bmap, 6647 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 6648 } 6649 6650 spin_unlock_bh(&hdev->fd_rule_lock); 6651 } 6652 6653 static void hclge_del_all_fd_entries(struct hclge_dev *hdev) 6654 { 6655 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6656 return; 6657 6658 hclge_clear_fd_rules_in_list(hdev, true); 6659 hclge_fd_disable_user_def(hdev); 6660 } 6661 6662 static int hclge_restore_fd_entries(struct hnae3_handle *handle) 6663 { 6664 struct hclge_vport *vport = hclge_get_vport(handle); 6665 struct hclge_dev *hdev = vport->back; 6666 struct hclge_fd_rule *rule; 6667 struct hlist_node *node; 6668 6669 /* Return ok here, because reset error handling will check this 6670 * return value. If error is returned here, the reset process will 6671 * fail. 6672 */ 6673 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6674 return 0; 6675 6676 /* if fd is disabled, should not restore it when reset */ 6677 if (!hdev->fd_en) 6678 return 0; 6679 6680 spin_lock_bh(&hdev->fd_rule_lock); 6681 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6682 if (rule->state == HCLGE_FD_ACTIVE) 6683 rule->state = HCLGE_FD_TO_ADD; 6684 } 6685 spin_unlock_bh(&hdev->fd_rule_lock); 6686 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 6687 6688 return 0; 6689 } 6690 6691 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle, 6692 struct ethtool_rxnfc *cmd) 6693 { 6694 struct hclge_vport *vport = hclge_get_vport(handle); 6695 struct hclge_dev *hdev = vport->back; 6696 6697 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev) || hclge_is_cls_flower_active(handle)) 6698 return -EOPNOTSUPP; 6699 6700 cmd->rule_cnt = hdev->hclge_fd_rule_num; 6701 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6702 6703 return 0; 6704 } 6705 6706 static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule, 6707 struct ethtool_tcpip4_spec *spec, 6708 struct ethtool_tcpip4_spec *spec_mask) 6709 { 6710 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6711 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6712 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6713 6714 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6715 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6716 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6717 6718 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6719 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6720 0 : cpu_to_be16(rule->tuples_mask.src_port); 6721 6722 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6723 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6724 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6725 6726 spec->tos = rule->tuples.ip_tos; 6727 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6728 0 : rule->tuples_mask.ip_tos; 6729 } 6730 6731 static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule, 6732 struct ethtool_usrip4_spec *spec, 6733 struct ethtool_usrip4_spec *spec_mask) 6734 { 6735 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6736 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6737 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6738 6739 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6740 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6741 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6742 6743 spec->tos = rule->tuples.ip_tos; 6744 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6745 0 : rule->tuples_mask.ip_tos; 6746 6747 spec->proto = rule->tuples.ip_proto; 6748 spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6749 0 : rule->tuples_mask.ip_proto; 6750 6751 spec->ip_ver = ETH_RX_NFC_IP4; 6752 } 6753 6754 static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule, 6755 struct ethtool_tcpip6_spec *spec, 6756 struct ethtool_tcpip6_spec *spec_mask) 6757 { 6758 cpu_to_be32_array(spec->ip6src, 6759 rule->tuples.src_ip, IPV6_SIZE); 6760 cpu_to_be32_array(spec->ip6dst, 6761 rule->tuples.dst_ip, IPV6_SIZE); 6762 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6763 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6764 else 6765 cpu_to_be32_array(spec_mask->ip6src, rule->tuples_mask.src_ip, 6766 IPV6_SIZE); 6767 6768 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6769 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6770 else 6771 cpu_to_be32_array(spec_mask->ip6dst, rule->tuples_mask.dst_ip, 6772 IPV6_SIZE); 6773 6774 spec->tclass = rule->tuples.ip_tos; 6775 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6776 0 : rule->tuples_mask.ip_tos; 6777 6778 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6779 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6780 0 : cpu_to_be16(rule->tuples_mask.src_port); 6781 6782 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6783 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6784 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6785 } 6786 6787 static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule, 6788 struct ethtool_usrip6_spec *spec, 6789 struct ethtool_usrip6_spec *spec_mask) 6790 { 6791 cpu_to_be32_array(spec->ip6src, rule->tuples.src_ip, IPV6_SIZE); 6792 cpu_to_be32_array(spec->ip6dst, rule->tuples.dst_ip, IPV6_SIZE); 6793 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6794 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6795 else 6796 cpu_to_be32_array(spec_mask->ip6src, 6797 rule->tuples_mask.src_ip, IPV6_SIZE); 6798 6799 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6800 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6801 else 6802 cpu_to_be32_array(spec_mask->ip6dst, 6803 rule->tuples_mask.dst_ip, IPV6_SIZE); 6804 6805 spec->tclass = rule->tuples.ip_tos; 6806 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6807 0 : rule->tuples_mask.ip_tos; 6808 6809 spec->l4_proto = rule->tuples.ip_proto; 6810 spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6811 0 : rule->tuples_mask.ip_proto; 6812 } 6813 6814 static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule, 6815 struct ethhdr *spec, 6816 struct ethhdr *spec_mask) 6817 { 6818 ether_addr_copy(spec->h_source, rule->tuples.src_mac); 6819 ether_addr_copy(spec->h_dest, rule->tuples.dst_mac); 6820 6821 if (rule->unused_tuple & BIT(INNER_SRC_MAC)) 6822 eth_zero_addr(spec_mask->h_source); 6823 else 6824 ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac); 6825 6826 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6827 eth_zero_addr(spec_mask->h_dest); 6828 else 6829 ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac); 6830 6831 spec->h_proto = cpu_to_be16(rule->tuples.ether_proto); 6832 spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ? 6833 0 : cpu_to_be16(rule->tuples_mask.ether_proto); 6834 } 6835 6836 static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs, 6837 struct hclge_fd_rule *rule) 6838 { 6839 if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) == 6840 HCLGE_FD_TUPLE_USER_DEF_TUPLES) { 6841 fs->h_ext.data[0] = 0; 6842 fs->h_ext.data[1] = 0; 6843 fs->m_ext.data[0] = 0; 6844 fs->m_ext.data[1] = 0; 6845 } else { 6846 fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset); 6847 fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data); 6848 fs->m_ext.data[0] = 6849 cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK); 6850 fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask); 6851 } 6852 } 6853 6854 static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs, 6855 struct hclge_fd_rule *rule) 6856 { 6857 if (fs->flow_type & FLOW_EXT) { 6858 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1); 6859 fs->m_ext.vlan_tci = 6860 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ? 6861 0 : cpu_to_be16(rule->tuples_mask.vlan_tag1); 6862 6863 hclge_fd_get_user_def_info(fs, rule); 6864 } 6865 6866 if (fs->flow_type & FLOW_MAC_EXT) { 6867 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac); 6868 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6869 eth_zero_addr(fs->m_u.ether_spec.h_dest); 6870 else 6871 ether_addr_copy(fs->m_u.ether_spec.h_dest, 6872 rule->tuples_mask.dst_mac); 6873 } 6874 } 6875 6876 static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev, 6877 u16 location) 6878 { 6879 struct hclge_fd_rule *rule = NULL; 6880 struct hlist_node *node2; 6881 6882 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) { 6883 if (rule->location == location) 6884 return rule; 6885 else if (rule->location > location) 6886 return NULL; 6887 } 6888 6889 return NULL; 6890 } 6891 6892 static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs, 6893 struct hclge_fd_rule *rule) 6894 { 6895 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 6896 fs->ring_cookie = RX_CLS_FLOW_DISC; 6897 } else { 6898 u64 vf_id; 6899 6900 fs->ring_cookie = rule->queue_id; 6901 vf_id = rule->vf_id; 6902 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 6903 fs->ring_cookie |= vf_id; 6904 } 6905 } 6906 6907 static int hclge_get_fd_rule_info(struct hnae3_handle *handle, 6908 struct ethtool_rxnfc *cmd) 6909 { 6910 struct hclge_vport *vport = hclge_get_vport(handle); 6911 struct hclge_fd_rule *rule = NULL; 6912 struct hclge_dev *hdev = vport->back; 6913 struct ethtool_rx_flow_spec *fs; 6914 6915 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6916 return -EOPNOTSUPP; 6917 6918 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6919 6920 spin_lock_bh(&hdev->fd_rule_lock); 6921 6922 rule = hclge_get_fd_rule(hdev, fs->location); 6923 if (!rule) { 6924 spin_unlock_bh(&hdev->fd_rule_lock); 6925 return -ENOENT; 6926 } 6927 6928 fs->flow_type = rule->flow_type; 6929 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 6930 case SCTP_V4_FLOW: 6931 case TCP_V4_FLOW: 6932 case UDP_V4_FLOW: 6933 hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec, 6934 &fs->m_u.tcp_ip4_spec); 6935 break; 6936 case IP_USER_FLOW: 6937 hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec, 6938 &fs->m_u.usr_ip4_spec); 6939 break; 6940 case SCTP_V6_FLOW: 6941 case TCP_V6_FLOW: 6942 case UDP_V6_FLOW: 6943 hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec, 6944 &fs->m_u.tcp_ip6_spec); 6945 break; 6946 case IPV6_USER_FLOW: 6947 hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec, 6948 &fs->m_u.usr_ip6_spec); 6949 break; 6950 /* The flow type of fd rule has been checked before adding in to rule 6951 * list. As other flow types have been handled, it must be ETHER_FLOW 6952 * for the default case 6953 */ 6954 default: 6955 hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec, 6956 &fs->m_u.ether_spec); 6957 break; 6958 } 6959 6960 hclge_fd_get_ext_info(fs, rule); 6961 6962 hclge_fd_get_ring_cookie(fs, rule); 6963 6964 spin_unlock_bh(&hdev->fd_rule_lock); 6965 6966 return 0; 6967 } 6968 6969 static int hclge_get_all_rules(struct hnae3_handle *handle, 6970 struct ethtool_rxnfc *cmd, u32 *rule_locs) 6971 { 6972 struct hclge_vport *vport = hclge_get_vport(handle); 6973 struct hclge_dev *hdev = vport->back; 6974 struct hclge_fd_rule *rule; 6975 struct hlist_node *node2; 6976 int cnt = 0; 6977 6978 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6979 return -EOPNOTSUPP; 6980 6981 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6982 6983 spin_lock_bh(&hdev->fd_rule_lock); 6984 hlist_for_each_entry_safe(rule, node2, 6985 &hdev->fd_rule_list, rule_node) { 6986 if (cnt == cmd->rule_cnt) { 6987 spin_unlock_bh(&hdev->fd_rule_lock); 6988 return -EMSGSIZE; 6989 } 6990 6991 if (rule->state == HCLGE_FD_TO_DEL) 6992 continue; 6993 6994 rule_locs[cnt] = rule->location; 6995 cnt++; 6996 } 6997 6998 spin_unlock_bh(&hdev->fd_rule_lock); 6999 7000 cmd->rule_cnt = cnt; 7001 7002 return 0; 7003 } 7004 7005 static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys, 7006 struct hclge_fd_rule_tuples *tuples) 7007 { 7008 #define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32 7009 #define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32 7010 7011 tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto); 7012 tuples->ip_proto = fkeys->basic.ip_proto; 7013 tuples->dst_port = be16_to_cpu(fkeys->ports.dst); 7014 7015 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 7016 tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src); 7017 tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst); 7018 } else { 7019 int i; 7020 7021 for (i = 0; i < IPV6_SIZE; i++) { 7022 tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]); 7023 tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]); 7024 } 7025 } 7026 } 7027 7028 /* traverse all rules, check whether an existed rule has the same tuples */ 7029 static struct hclge_fd_rule * 7030 hclge_fd_search_flow_keys(struct hclge_dev *hdev, 7031 const struct hclge_fd_rule_tuples *tuples) 7032 { 7033 struct hclge_fd_rule *rule = NULL; 7034 struct hlist_node *node; 7035 7036 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7037 if (!memcmp(tuples, &rule->tuples, sizeof(*tuples))) 7038 return rule; 7039 } 7040 7041 return NULL; 7042 } 7043 7044 static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples, 7045 struct hclge_fd_rule *rule) 7046 { 7047 rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 7048 BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) | 7049 BIT(INNER_SRC_PORT); 7050 rule->action = 0; 7051 rule->vf_id = 0; 7052 rule->rule_type = HCLGE_FD_ARFS_ACTIVE; 7053 rule->state = HCLGE_FD_TO_ADD; 7054 if (tuples->ether_proto == ETH_P_IP) { 7055 if (tuples->ip_proto == IPPROTO_TCP) 7056 rule->flow_type = TCP_V4_FLOW; 7057 else 7058 rule->flow_type = UDP_V4_FLOW; 7059 } else { 7060 if (tuples->ip_proto == IPPROTO_TCP) 7061 rule->flow_type = TCP_V6_FLOW; 7062 else 7063 rule->flow_type = UDP_V6_FLOW; 7064 } 7065 memcpy(&rule->tuples, tuples, sizeof(rule->tuples)); 7066 memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask)); 7067 } 7068 7069 static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id, 7070 u16 flow_id, struct flow_keys *fkeys) 7071 { 7072 struct hclge_vport *vport = hclge_get_vport(handle); 7073 struct hclge_fd_rule_tuples new_tuples = {}; 7074 struct hclge_dev *hdev = vport->back; 7075 struct hclge_fd_rule *rule; 7076 u16 bit_id; 7077 7078 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7079 return -EOPNOTSUPP; 7080 7081 /* when there is already fd rule existed add by user, 7082 * arfs should not work 7083 */ 7084 spin_lock_bh(&hdev->fd_rule_lock); 7085 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE && 7086 hdev->fd_active_type != HCLGE_FD_RULE_NONE) { 7087 spin_unlock_bh(&hdev->fd_rule_lock); 7088 return -EOPNOTSUPP; 7089 } 7090 7091 hclge_fd_get_flow_tuples(fkeys, &new_tuples); 7092 7093 /* check is there flow director filter existed for this flow, 7094 * if not, create a new filter for it; 7095 * if filter exist with different queue id, modify the filter; 7096 * if filter exist with same queue id, do nothing 7097 */ 7098 rule = hclge_fd_search_flow_keys(hdev, &new_tuples); 7099 if (!rule) { 7100 bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM); 7101 if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7102 spin_unlock_bh(&hdev->fd_rule_lock); 7103 return -ENOSPC; 7104 } 7105 7106 rule = kzalloc(sizeof(*rule), GFP_ATOMIC); 7107 if (!rule) { 7108 spin_unlock_bh(&hdev->fd_rule_lock); 7109 return -ENOMEM; 7110 } 7111 7112 rule->location = bit_id; 7113 rule->arfs.flow_id = flow_id; 7114 rule->queue_id = queue_id; 7115 hclge_fd_build_arfs_rule(&new_tuples, rule); 7116 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 7117 hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE; 7118 } else if (rule->queue_id != queue_id) { 7119 rule->queue_id = queue_id; 7120 rule->state = HCLGE_FD_TO_ADD; 7121 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7122 hclge_task_schedule(hdev, 0); 7123 } 7124 spin_unlock_bh(&hdev->fd_rule_lock); 7125 return rule->location; 7126 } 7127 7128 static void hclge_rfs_filter_expire(struct hclge_dev *hdev) 7129 { 7130 #ifdef CONFIG_RFS_ACCEL 7131 struct hnae3_handle *handle = &hdev->vport[0].nic; 7132 struct hclge_fd_rule *rule; 7133 struct hlist_node *node; 7134 7135 spin_lock_bh(&hdev->fd_rule_lock); 7136 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) { 7137 spin_unlock_bh(&hdev->fd_rule_lock); 7138 return; 7139 } 7140 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7141 if (rule->state != HCLGE_FD_ACTIVE) 7142 continue; 7143 if (rps_may_expire_flow(handle->netdev, rule->queue_id, 7144 rule->arfs.flow_id, rule->location)) { 7145 rule->state = HCLGE_FD_TO_DEL; 7146 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7147 } 7148 } 7149 spin_unlock_bh(&hdev->fd_rule_lock); 7150 #endif 7151 } 7152 7153 /* make sure being called after lock up with fd_rule_lock */ 7154 static int hclge_clear_arfs_rules(struct hclge_dev *hdev) 7155 { 7156 #ifdef CONFIG_RFS_ACCEL 7157 struct hclge_fd_rule *rule; 7158 struct hlist_node *node; 7159 int ret; 7160 7161 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) 7162 return 0; 7163 7164 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7165 switch (rule->state) { 7166 case HCLGE_FD_TO_DEL: 7167 case HCLGE_FD_ACTIVE: 7168 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7169 rule->location, NULL, false); 7170 if (ret) 7171 return ret; 7172 fallthrough; 7173 case HCLGE_FD_TO_ADD: 7174 hclge_fd_dec_rule_cnt(hdev, rule->location); 7175 hlist_del(&rule->rule_node); 7176 kfree(rule); 7177 break; 7178 default: 7179 break; 7180 } 7181 } 7182 hclge_sync_fd_state(hdev); 7183 7184 #endif 7185 return 0; 7186 } 7187 7188 static void hclge_get_cls_key_basic(const struct flow_rule *flow, 7189 struct hclge_fd_rule *rule) 7190 { 7191 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) { 7192 struct flow_match_basic match; 7193 u16 ethtype_key, ethtype_mask; 7194 7195 flow_rule_match_basic(flow, &match); 7196 ethtype_key = ntohs(match.key->n_proto); 7197 ethtype_mask = ntohs(match.mask->n_proto); 7198 7199 if (ethtype_key == ETH_P_ALL) { 7200 ethtype_key = 0; 7201 ethtype_mask = 0; 7202 } 7203 rule->tuples.ether_proto = ethtype_key; 7204 rule->tuples_mask.ether_proto = ethtype_mask; 7205 rule->tuples.ip_proto = match.key->ip_proto; 7206 rule->tuples_mask.ip_proto = match.mask->ip_proto; 7207 } else { 7208 rule->unused_tuple |= BIT(INNER_IP_PROTO); 7209 rule->unused_tuple |= BIT(INNER_ETH_TYPE); 7210 } 7211 } 7212 7213 static void hclge_get_cls_key_mac(const struct flow_rule *flow, 7214 struct hclge_fd_rule *rule) 7215 { 7216 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 7217 struct flow_match_eth_addrs match; 7218 7219 flow_rule_match_eth_addrs(flow, &match); 7220 ether_addr_copy(rule->tuples.dst_mac, match.key->dst); 7221 ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst); 7222 ether_addr_copy(rule->tuples.src_mac, match.key->src); 7223 ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src); 7224 } else { 7225 rule->unused_tuple |= BIT(INNER_DST_MAC); 7226 rule->unused_tuple |= BIT(INNER_SRC_MAC); 7227 } 7228 } 7229 7230 static void hclge_get_cls_key_vlan(const struct flow_rule *flow, 7231 struct hclge_fd_rule *rule) 7232 { 7233 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) { 7234 struct flow_match_vlan match; 7235 7236 flow_rule_match_vlan(flow, &match); 7237 rule->tuples.vlan_tag1 = match.key->vlan_id | 7238 (match.key->vlan_priority << VLAN_PRIO_SHIFT); 7239 rule->tuples_mask.vlan_tag1 = match.mask->vlan_id | 7240 (match.mask->vlan_priority << VLAN_PRIO_SHIFT); 7241 } else { 7242 rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST); 7243 } 7244 } 7245 7246 static void hclge_get_cls_key_ip(const struct flow_rule *flow, 7247 struct hclge_fd_rule *rule) 7248 { 7249 u16 addr_type = 0; 7250 7251 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) { 7252 struct flow_match_control match; 7253 7254 flow_rule_match_control(flow, &match); 7255 addr_type = match.key->addr_type; 7256 } 7257 7258 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { 7259 struct flow_match_ipv4_addrs match; 7260 7261 flow_rule_match_ipv4_addrs(flow, &match); 7262 rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src); 7263 rule->tuples_mask.src_ip[IPV4_INDEX] = 7264 be32_to_cpu(match.mask->src); 7265 rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst); 7266 rule->tuples_mask.dst_ip[IPV4_INDEX] = 7267 be32_to_cpu(match.mask->dst); 7268 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { 7269 struct flow_match_ipv6_addrs match; 7270 7271 flow_rule_match_ipv6_addrs(flow, &match); 7272 be32_to_cpu_array(rule->tuples.src_ip, match.key->src.s6_addr32, 7273 IPV6_SIZE); 7274 be32_to_cpu_array(rule->tuples_mask.src_ip, 7275 match.mask->src.s6_addr32, IPV6_SIZE); 7276 be32_to_cpu_array(rule->tuples.dst_ip, match.key->dst.s6_addr32, 7277 IPV6_SIZE); 7278 be32_to_cpu_array(rule->tuples_mask.dst_ip, 7279 match.mask->dst.s6_addr32, IPV6_SIZE); 7280 } else { 7281 rule->unused_tuple |= BIT(INNER_SRC_IP); 7282 rule->unused_tuple |= BIT(INNER_DST_IP); 7283 } 7284 } 7285 7286 static void hclge_get_cls_key_port(const struct flow_rule *flow, 7287 struct hclge_fd_rule *rule) 7288 { 7289 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) { 7290 struct flow_match_ports match; 7291 7292 flow_rule_match_ports(flow, &match); 7293 7294 rule->tuples.src_port = be16_to_cpu(match.key->src); 7295 rule->tuples_mask.src_port = be16_to_cpu(match.mask->src); 7296 rule->tuples.dst_port = be16_to_cpu(match.key->dst); 7297 rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst); 7298 } else { 7299 rule->unused_tuple |= BIT(INNER_SRC_PORT); 7300 rule->unused_tuple |= BIT(INNER_DST_PORT); 7301 } 7302 } 7303 7304 static int hclge_parse_cls_flower(struct hclge_dev *hdev, 7305 struct flow_cls_offload *cls_flower, 7306 struct hclge_fd_rule *rule) 7307 { 7308 struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower); 7309 struct flow_dissector *dissector = flow->match.dissector; 7310 7311 if (dissector->used_keys & 7312 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | 7313 BIT(FLOW_DISSECTOR_KEY_BASIC) | 7314 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 7315 BIT(FLOW_DISSECTOR_KEY_VLAN) | 7316 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | 7317 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | 7318 BIT(FLOW_DISSECTOR_KEY_PORTS))) { 7319 dev_err(&hdev->pdev->dev, "unsupported key set: %#x\n", 7320 dissector->used_keys); 7321 return -EOPNOTSUPP; 7322 } 7323 7324 hclge_get_cls_key_basic(flow, rule); 7325 hclge_get_cls_key_mac(flow, rule); 7326 hclge_get_cls_key_vlan(flow, rule); 7327 hclge_get_cls_key_ip(flow, rule); 7328 hclge_get_cls_key_port(flow, rule); 7329 7330 return 0; 7331 } 7332 7333 static int hclge_check_cls_flower(struct hclge_dev *hdev, 7334 struct flow_cls_offload *cls_flower, int tc) 7335 { 7336 u32 prio = cls_flower->common.prio; 7337 7338 if (tc < 0 || tc > hdev->tc_max) { 7339 dev_err(&hdev->pdev->dev, "invalid traffic class\n"); 7340 return -EINVAL; 7341 } 7342 7343 if (prio == 0 || 7344 prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7345 dev_err(&hdev->pdev->dev, 7346 "prio %u should be in range[1, %u]\n", 7347 prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 7348 return -EINVAL; 7349 } 7350 7351 if (test_bit(prio - 1, hdev->fd_bmap)) { 7352 dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio); 7353 return -EINVAL; 7354 } 7355 return 0; 7356 } 7357 7358 static int hclge_add_cls_flower(struct hnae3_handle *handle, 7359 struct flow_cls_offload *cls_flower, 7360 int tc) 7361 { 7362 struct hclge_vport *vport = hclge_get_vport(handle); 7363 struct hclge_dev *hdev = vport->back; 7364 struct hclge_fd_rule *rule; 7365 int ret; 7366 7367 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 7368 dev_err(&hdev->pdev->dev, 7369 "cls flower is not supported\n"); 7370 return -EOPNOTSUPP; 7371 } 7372 7373 ret = hclge_check_cls_flower(hdev, cls_flower, tc); 7374 if (ret) { 7375 dev_err(&hdev->pdev->dev, 7376 "failed to check cls flower params, ret = %d\n", ret); 7377 return ret; 7378 } 7379 7380 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 7381 if (!rule) 7382 return -ENOMEM; 7383 7384 ret = hclge_parse_cls_flower(hdev, cls_flower, rule); 7385 if (ret) { 7386 kfree(rule); 7387 return ret; 7388 } 7389 7390 rule->action = HCLGE_FD_ACTION_SELECT_TC; 7391 rule->cls_flower.tc = tc; 7392 rule->location = cls_flower->common.prio - 1; 7393 rule->vf_id = 0; 7394 rule->cls_flower.cookie = cls_flower->cookie; 7395 rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE; 7396 7397 ret = hclge_add_fd_entry_common(hdev, rule); 7398 if (ret) 7399 kfree(rule); 7400 7401 return ret; 7402 } 7403 7404 static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev, 7405 unsigned long cookie) 7406 { 7407 struct hclge_fd_rule *rule; 7408 struct hlist_node *node; 7409 7410 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7411 if (rule->cls_flower.cookie == cookie) 7412 return rule; 7413 } 7414 7415 return NULL; 7416 } 7417 7418 static int hclge_del_cls_flower(struct hnae3_handle *handle, 7419 struct flow_cls_offload *cls_flower) 7420 { 7421 struct hclge_vport *vport = hclge_get_vport(handle); 7422 struct hclge_dev *hdev = vport->back; 7423 struct hclge_fd_rule *rule; 7424 int ret; 7425 7426 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7427 return -EOPNOTSUPP; 7428 7429 spin_lock_bh(&hdev->fd_rule_lock); 7430 7431 rule = hclge_find_cls_flower(hdev, cls_flower->cookie); 7432 if (!rule) { 7433 spin_unlock_bh(&hdev->fd_rule_lock); 7434 return -EINVAL; 7435 } 7436 7437 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location, 7438 NULL, false); 7439 if (ret) { 7440 spin_unlock_bh(&hdev->fd_rule_lock); 7441 return ret; 7442 } 7443 7444 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL); 7445 spin_unlock_bh(&hdev->fd_rule_lock); 7446 7447 return 0; 7448 } 7449 7450 static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist) 7451 { 7452 struct hclge_fd_rule *rule; 7453 struct hlist_node *node; 7454 int ret = 0; 7455 7456 if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state)) 7457 return; 7458 7459 spin_lock_bh(&hdev->fd_rule_lock); 7460 7461 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 7462 switch (rule->state) { 7463 case HCLGE_FD_TO_ADD: 7464 ret = hclge_fd_config_rule(hdev, rule); 7465 if (ret) 7466 goto out; 7467 rule->state = HCLGE_FD_ACTIVE; 7468 break; 7469 case HCLGE_FD_TO_DEL: 7470 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7471 rule->location, NULL, false); 7472 if (ret) 7473 goto out; 7474 hclge_fd_dec_rule_cnt(hdev, rule->location); 7475 hclge_fd_free_node(hdev, rule); 7476 break; 7477 default: 7478 break; 7479 } 7480 } 7481 7482 out: 7483 if (ret) 7484 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7485 7486 spin_unlock_bh(&hdev->fd_rule_lock); 7487 } 7488 7489 static void hclge_sync_fd_table(struct hclge_dev *hdev) 7490 { 7491 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7492 return; 7493 7494 if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) { 7495 bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE; 7496 7497 hclge_clear_fd_rules_in_list(hdev, clear_list); 7498 } 7499 7500 hclge_sync_fd_user_def_cfg(hdev, false); 7501 7502 hclge_sync_fd_list(hdev, &hdev->fd_rule_list); 7503 } 7504 7505 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle) 7506 { 7507 struct hclge_vport *vport = hclge_get_vport(handle); 7508 struct hclge_dev *hdev = vport->back; 7509 7510 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) || 7511 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING); 7512 } 7513 7514 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle) 7515 { 7516 struct hclge_vport *vport = hclge_get_vport(handle); 7517 struct hclge_dev *hdev = vport->back; 7518 7519 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 7520 } 7521 7522 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle) 7523 { 7524 struct hclge_vport *vport = hclge_get_vport(handle); 7525 struct hclge_dev *hdev = vport->back; 7526 7527 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 7528 } 7529 7530 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle) 7531 { 7532 struct hclge_vport *vport = hclge_get_vport(handle); 7533 struct hclge_dev *hdev = vport->back; 7534 7535 return hdev->rst_stats.hw_reset_done_cnt; 7536 } 7537 7538 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable) 7539 { 7540 struct hclge_vport *vport = hclge_get_vport(handle); 7541 struct hclge_dev *hdev = vport->back; 7542 7543 hdev->fd_en = enable; 7544 7545 if (!enable) 7546 set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state); 7547 else 7548 hclge_restore_fd_entries(handle); 7549 7550 hclge_task_schedule(hdev, 0); 7551 } 7552 7553 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 7554 { 7555 struct hclge_desc desc; 7556 struct hclge_config_mac_mode_cmd *req = 7557 (struct hclge_config_mac_mode_cmd *)desc.data; 7558 u32 loop_en = 0; 7559 int ret; 7560 7561 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 7562 7563 if (enable) { 7564 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U); 7565 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U); 7566 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U); 7567 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U); 7568 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U); 7569 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U); 7570 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U); 7571 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U); 7572 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U); 7573 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U); 7574 } 7575 7576 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7577 7578 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7579 if (ret) 7580 dev_err(&hdev->pdev->dev, 7581 "mac enable fail, ret =%d.\n", ret); 7582 } 7583 7584 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid, 7585 u8 switch_param, u8 param_mask) 7586 { 7587 struct hclge_mac_vlan_switch_cmd *req; 7588 struct hclge_desc desc; 7589 u32 func_id; 7590 int ret; 7591 7592 func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0); 7593 req = (struct hclge_mac_vlan_switch_cmd *)desc.data; 7594 7595 /* read current config parameter */ 7596 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM, 7597 true); 7598 req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL; 7599 req->func_id = cpu_to_le32(func_id); 7600 7601 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7602 if (ret) { 7603 dev_err(&hdev->pdev->dev, 7604 "read mac vlan switch parameter fail, ret = %d\n", ret); 7605 return ret; 7606 } 7607 7608 /* modify and write new config parameter */ 7609 hclge_comm_cmd_reuse_desc(&desc, false); 7610 req->switch_param = (req->switch_param & param_mask) | switch_param; 7611 req->param_mask = param_mask; 7612 7613 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7614 if (ret) 7615 dev_err(&hdev->pdev->dev, 7616 "set mac vlan switch parameter fail, ret = %d\n", ret); 7617 return ret; 7618 } 7619 7620 static void hclge_phy_link_status_wait(struct hclge_dev *hdev, 7621 int link_ret) 7622 { 7623 #define HCLGE_PHY_LINK_STATUS_NUM 200 7624 7625 struct phy_device *phydev = hdev->hw.mac.phydev; 7626 int i = 0; 7627 int ret; 7628 7629 do { 7630 ret = phy_read_status(phydev); 7631 if (ret) { 7632 dev_err(&hdev->pdev->dev, 7633 "phy update link status fail, ret = %d\n", ret); 7634 return; 7635 } 7636 7637 if (phydev->link == link_ret) 7638 break; 7639 7640 msleep(HCLGE_LINK_STATUS_MS); 7641 } while (++i < HCLGE_PHY_LINK_STATUS_NUM); 7642 } 7643 7644 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret) 7645 { 7646 #define HCLGE_MAC_LINK_STATUS_NUM 100 7647 7648 int link_status; 7649 int i = 0; 7650 int ret; 7651 7652 do { 7653 ret = hclge_get_mac_link_status(hdev, &link_status); 7654 if (ret) 7655 return ret; 7656 if (link_status == link_ret) 7657 return 0; 7658 7659 msleep(HCLGE_LINK_STATUS_MS); 7660 } while (++i < HCLGE_MAC_LINK_STATUS_NUM); 7661 return -EBUSY; 7662 } 7663 7664 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en, 7665 bool is_phy) 7666 { 7667 int link_ret; 7668 7669 link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 7670 7671 if (is_phy) 7672 hclge_phy_link_status_wait(hdev, link_ret); 7673 7674 return hclge_mac_link_status_wait(hdev, link_ret); 7675 } 7676 7677 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) 7678 { 7679 struct hclge_config_mac_mode_cmd *req; 7680 struct hclge_desc desc; 7681 u32 loop_en; 7682 int ret; 7683 7684 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 7685 /* 1 Read out the MAC mode config at first */ 7686 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 7687 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7688 if (ret) { 7689 dev_err(&hdev->pdev->dev, 7690 "mac loopback get fail, ret =%d.\n", ret); 7691 return ret; 7692 } 7693 7694 /* 2 Then setup the loopback flag */ 7695 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 7696 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 7697 7698 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7699 7700 /* 3 Config mac work mode with loopback flag 7701 * and its original configure parameters 7702 */ 7703 hclge_comm_cmd_reuse_desc(&desc, false); 7704 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7705 if (ret) 7706 dev_err(&hdev->pdev->dev, 7707 "mac loopback set fail, ret =%d.\n", ret); 7708 return ret; 7709 } 7710 7711 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en, 7712 enum hnae3_loop loop_mode) 7713 { 7714 struct hclge_common_lb_cmd *req; 7715 struct hclge_desc desc; 7716 u8 loop_mode_b; 7717 int ret; 7718 7719 req = (struct hclge_common_lb_cmd *)desc.data; 7720 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false); 7721 7722 switch (loop_mode) { 7723 case HNAE3_LOOP_SERIAL_SERDES: 7724 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 7725 break; 7726 case HNAE3_LOOP_PARALLEL_SERDES: 7727 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B; 7728 break; 7729 case HNAE3_LOOP_PHY: 7730 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B; 7731 break; 7732 default: 7733 dev_err(&hdev->pdev->dev, 7734 "unsupported loopback mode %d\n", loop_mode); 7735 return -ENOTSUPP; 7736 } 7737 7738 req->mask = loop_mode_b; 7739 if (en) 7740 req->enable = loop_mode_b; 7741 7742 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7743 if (ret) 7744 dev_err(&hdev->pdev->dev, 7745 "failed to send loopback cmd, loop_mode = %d, ret = %d\n", 7746 loop_mode, ret); 7747 7748 return ret; 7749 } 7750 7751 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev) 7752 { 7753 #define HCLGE_COMMON_LB_RETRY_MS 10 7754 #define HCLGE_COMMON_LB_RETRY_NUM 100 7755 7756 struct hclge_common_lb_cmd *req; 7757 struct hclge_desc desc; 7758 u32 i = 0; 7759 int ret; 7760 7761 req = (struct hclge_common_lb_cmd *)desc.data; 7762 7763 do { 7764 msleep(HCLGE_COMMON_LB_RETRY_MS); 7765 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, 7766 true); 7767 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7768 if (ret) { 7769 dev_err(&hdev->pdev->dev, 7770 "failed to get loopback done status, ret = %d\n", 7771 ret); 7772 return ret; 7773 } 7774 } while (++i < HCLGE_COMMON_LB_RETRY_NUM && 7775 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B)); 7776 7777 if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) { 7778 dev_err(&hdev->pdev->dev, "wait loopback timeout\n"); 7779 return -EBUSY; 7780 } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) { 7781 dev_err(&hdev->pdev->dev, "failed to do loopback test\n"); 7782 return -EIO; 7783 } 7784 7785 return 0; 7786 } 7787 7788 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en, 7789 enum hnae3_loop loop_mode) 7790 { 7791 int ret; 7792 7793 ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode); 7794 if (ret) 7795 return ret; 7796 7797 return hclge_cfg_common_loopback_wait(hdev); 7798 } 7799 7800 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en, 7801 enum hnae3_loop loop_mode) 7802 { 7803 int ret; 7804 7805 ret = hclge_cfg_common_loopback(hdev, en, loop_mode); 7806 if (ret) 7807 return ret; 7808 7809 hclge_cfg_mac_mode(hdev, en); 7810 7811 ret = hclge_mac_phy_link_status_wait(hdev, en, false); 7812 if (ret) 7813 dev_err(&hdev->pdev->dev, 7814 "serdes loopback config mac mode timeout\n"); 7815 7816 return ret; 7817 } 7818 7819 static int hclge_enable_phy_loopback(struct hclge_dev *hdev, 7820 struct phy_device *phydev) 7821 { 7822 int ret; 7823 7824 if (!phydev->suspended) { 7825 ret = phy_suspend(phydev); 7826 if (ret) 7827 return ret; 7828 } 7829 7830 ret = phy_resume(phydev); 7831 if (ret) 7832 return ret; 7833 7834 return phy_loopback(phydev, true); 7835 } 7836 7837 static int hclge_disable_phy_loopback(struct hclge_dev *hdev, 7838 struct phy_device *phydev) 7839 { 7840 int ret; 7841 7842 ret = phy_loopback(phydev, false); 7843 if (ret) 7844 return ret; 7845 7846 return phy_suspend(phydev); 7847 } 7848 7849 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en) 7850 { 7851 struct phy_device *phydev = hdev->hw.mac.phydev; 7852 int ret; 7853 7854 if (!phydev) { 7855 if (hnae3_dev_phy_imp_supported(hdev)) 7856 return hclge_set_common_loopback(hdev, en, 7857 HNAE3_LOOP_PHY); 7858 return -ENOTSUPP; 7859 } 7860 7861 if (en) 7862 ret = hclge_enable_phy_loopback(hdev, phydev); 7863 else 7864 ret = hclge_disable_phy_loopback(hdev, phydev); 7865 if (ret) { 7866 dev_err(&hdev->pdev->dev, 7867 "set phy loopback fail, ret = %d\n", ret); 7868 return ret; 7869 } 7870 7871 hclge_cfg_mac_mode(hdev, en); 7872 7873 ret = hclge_mac_phy_link_status_wait(hdev, en, true); 7874 if (ret) 7875 dev_err(&hdev->pdev->dev, 7876 "phy loopback config mac mode timeout\n"); 7877 7878 return ret; 7879 } 7880 7881 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id, 7882 u16 stream_id, bool enable) 7883 { 7884 struct hclge_desc desc; 7885 struct hclge_cfg_com_tqp_queue_cmd *req = 7886 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 7887 7888 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 7889 req->tqp_id = cpu_to_le16(tqp_id); 7890 req->stream_id = cpu_to_le16(stream_id); 7891 if (enable) 7892 req->enable |= 1U << HCLGE_TQP_ENABLE_B; 7893 7894 return hclge_cmd_send(&hdev->hw, &desc, 1); 7895 } 7896 7897 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable) 7898 { 7899 struct hclge_vport *vport = hclge_get_vport(handle); 7900 struct hclge_dev *hdev = vport->back; 7901 int ret; 7902 u16 i; 7903 7904 for (i = 0; i < handle->kinfo.num_tqps; i++) { 7905 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable); 7906 if (ret) 7907 return ret; 7908 } 7909 return 0; 7910 } 7911 7912 static int hclge_set_loopback(struct hnae3_handle *handle, 7913 enum hnae3_loop loop_mode, bool en) 7914 { 7915 struct hclge_vport *vport = hclge_get_vport(handle); 7916 struct hclge_dev *hdev = vport->back; 7917 int ret = 0; 7918 7919 /* Loopback can be enabled in three places: SSU, MAC, and serdes. By 7920 * default, SSU loopback is enabled, so if the SMAC and the DMAC are 7921 * the same, the packets are looped back in the SSU. If SSU loopback 7922 * is disabled, packets can reach MAC even if SMAC is the same as DMAC. 7923 */ 7924 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 7925 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B); 7926 7927 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param, 7928 HCLGE_SWITCH_ALW_LPBK_MASK); 7929 if (ret) 7930 return ret; 7931 } 7932 7933 switch (loop_mode) { 7934 case HNAE3_LOOP_APP: 7935 ret = hclge_set_app_loopback(hdev, en); 7936 break; 7937 case HNAE3_LOOP_SERIAL_SERDES: 7938 case HNAE3_LOOP_PARALLEL_SERDES: 7939 ret = hclge_set_common_loopback(hdev, en, loop_mode); 7940 break; 7941 case HNAE3_LOOP_PHY: 7942 ret = hclge_set_phy_loopback(hdev, en); 7943 break; 7944 case HNAE3_LOOP_EXTERNAL: 7945 break; 7946 default: 7947 ret = -ENOTSUPP; 7948 dev_err(&hdev->pdev->dev, 7949 "loop_mode %d is not supported\n", loop_mode); 7950 break; 7951 } 7952 7953 if (ret) 7954 return ret; 7955 7956 ret = hclge_tqp_enable(handle, en); 7957 if (ret) 7958 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n", 7959 en ? "enable" : "disable", ret); 7960 7961 return ret; 7962 } 7963 7964 static int hclge_set_default_loopback(struct hclge_dev *hdev) 7965 { 7966 int ret; 7967 7968 ret = hclge_set_app_loopback(hdev, false); 7969 if (ret) 7970 return ret; 7971 7972 ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES); 7973 if (ret) 7974 return ret; 7975 7976 return hclge_cfg_common_loopback(hdev, false, 7977 HNAE3_LOOP_PARALLEL_SERDES); 7978 } 7979 7980 static void hclge_flush_link_update(struct hclge_dev *hdev) 7981 { 7982 #define HCLGE_FLUSH_LINK_TIMEOUT 100000 7983 7984 unsigned long last = hdev->serv_processed_cnt; 7985 int i = 0; 7986 7987 while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) && 7988 i++ < HCLGE_FLUSH_LINK_TIMEOUT && 7989 last == hdev->serv_processed_cnt) 7990 usleep_range(1, 1); 7991 } 7992 7993 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable) 7994 { 7995 struct hclge_vport *vport = hclge_get_vport(handle); 7996 struct hclge_dev *hdev = vport->back; 7997 7998 if (enable) { 7999 hclge_task_schedule(hdev, 0); 8000 } else { 8001 /* Set the DOWN flag here to disable link updating */ 8002 set_bit(HCLGE_STATE_DOWN, &hdev->state); 8003 8004 /* flush memory to make sure DOWN is seen by service task */ 8005 smp_mb__before_atomic(); 8006 hclge_flush_link_update(hdev); 8007 } 8008 } 8009 8010 static int hclge_ae_start(struct hnae3_handle *handle) 8011 { 8012 struct hclge_vport *vport = hclge_get_vport(handle); 8013 struct hclge_dev *hdev = vport->back; 8014 8015 /* mac enable */ 8016 hclge_cfg_mac_mode(hdev, true); 8017 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 8018 hdev->hw.mac.link = 0; 8019 8020 /* reset tqp stats */ 8021 hclge_comm_reset_tqp_stats(handle); 8022 8023 hclge_mac_start_phy(hdev); 8024 8025 return 0; 8026 } 8027 8028 static void hclge_ae_stop(struct hnae3_handle *handle) 8029 { 8030 struct hclge_vport *vport = hclge_get_vport(handle); 8031 struct hclge_dev *hdev = vport->back; 8032 8033 set_bit(HCLGE_STATE_DOWN, &hdev->state); 8034 spin_lock_bh(&hdev->fd_rule_lock); 8035 hclge_clear_arfs_rules(hdev); 8036 spin_unlock_bh(&hdev->fd_rule_lock); 8037 8038 /* If it is not PF reset or FLR, the firmware will disable the MAC, 8039 * so it only need to stop phy here. 8040 */ 8041 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) && 8042 hdev->reset_type != HNAE3_FUNC_RESET && 8043 hdev->reset_type != HNAE3_FLR_RESET) { 8044 hclge_mac_stop_phy(hdev); 8045 hclge_update_link_status(hdev); 8046 return; 8047 } 8048 8049 hclge_reset_tqp(handle); 8050 8051 hclge_config_mac_tnl_int(hdev, false); 8052 8053 /* Mac disable */ 8054 hclge_cfg_mac_mode(hdev, false); 8055 8056 hclge_mac_stop_phy(hdev); 8057 8058 /* reset tqp stats */ 8059 hclge_comm_reset_tqp_stats(handle); 8060 hclge_update_link_status(hdev); 8061 } 8062 8063 int hclge_vport_start(struct hclge_vport *vport) 8064 { 8065 struct hclge_dev *hdev = vport->back; 8066 8067 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8068 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 8069 vport->last_active_jiffies = jiffies; 8070 8071 if (test_bit(vport->vport_id, hdev->vport_config_block)) { 8072 if (vport->vport_id) { 8073 hclge_restore_mac_table_common(vport); 8074 hclge_restore_vport_vlan_table(vport); 8075 } else { 8076 hclge_restore_hw_table(hdev); 8077 } 8078 } 8079 8080 clear_bit(vport->vport_id, hdev->vport_config_block); 8081 8082 return 0; 8083 } 8084 8085 void hclge_vport_stop(struct hclge_vport *vport) 8086 { 8087 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8088 } 8089 8090 static int hclge_client_start(struct hnae3_handle *handle) 8091 { 8092 struct hclge_vport *vport = hclge_get_vport(handle); 8093 8094 return hclge_vport_start(vport); 8095 } 8096 8097 static void hclge_client_stop(struct hnae3_handle *handle) 8098 { 8099 struct hclge_vport *vport = hclge_get_vport(handle); 8100 8101 hclge_vport_stop(vport); 8102 } 8103 8104 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 8105 u16 cmdq_resp, u8 resp_code, 8106 enum hclge_mac_vlan_tbl_opcode op) 8107 { 8108 struct hclge_dev *hdev = vport->back; 8109 8110 if (cmdq_resp) { 8111 dev_err(&hdev->pdev->dev, 8112 "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n", 8113 cmdq_resp); 8114 return -EIO; 8115 } 8116 8117 if (op == HCLGE_MAC_VLAN_ADD) { 8118 if (!resp_code || resp_code == 1) 8119 return 0; 8120 else if (resp_code == HCLGE_ADD_UC_OVERFLOW || 8121 resp_code == HCLGE_ADD_MC_OVERFLOW) 8122 return -ENOSPC; 8123 8124 dev_err(&hdev->pdev->dev, 8125 "add mac addr failed for undefined, code=%u.\n", 8126 resp_code); 8127 return -EIO; 8128 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 8129 if (!resp_code) { 8130 return 0; 8131 } else if (resp_code == 1) { 8132 dev_dbg(&hdev->pdev->dev, 8133 "remove mac addr failed for miss.\n"); 8134 return -ENOENT; 8135 } 8136 8137 dev_err(&hdev->pdev->dev, 8138 "remove mac addr failed for undefined, code=%u.\n", 8139 resp_code); 8140 return -EIO; 8141 } else if (op == HCLGE_MAC_VLAN_LKUP) { 8142 if (!resp_code) { 8143 return 0; 8144 } else if (resp_code == 1) { 8145 dev_dbg(&hdev->pdev->dev, 8146 "lookup mac addr failed for miss.\n"); 8147 return -ENOENT; 8148 } 8149 8150 dev_err(&hdev->pdev->dev, 8151 "lookup mac addr failed for undefined, code=%u.\n", 8152 resp_code); 8153 return -EIO; 8154 } 8155 8156 dev_err(&hdev->pdev->dev, 8157 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op); 8158 8159 return -EINVAL; 8160 } 8161 8162 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 8163 { 8164 #define HCLGE_VF_NUM_IN_FIRST_DESC 192 8165 8166 unsigned int word_num; 8167 unsigned int bit_num; 8168 8169 if (vfid > 255 || vfid < 0) 8170 return -EIO; 8171 8172 if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) { 8173 word_num = vfid / 32; 8174 bit_num = vfid % 32; 8175 if (clr) 8176 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8177 else 8178 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 8179 } else { 8180 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32; 8181 bit_num = vfid % 32; 8182 if (clr) 8183 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8184 else 8185 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 8186 } 8187 8188 return 0; 8189 } 8190 8191 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 8192 { 8193 #define HCLGE_DESC_NUMBER 3 8194 #define HCLGE_FUNC_NUMBER_PER_DESC 6 8195 int i, j; 8196 8197 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 8198 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 8199 if (desc[i].data[j]) 8200 return false; 8201 8202 return true; 8203 } 8204 8205 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 8206 const u8 *addr, bool is_mc) 8207 { 8208 const unsigned char *mac_addr = addr; 8209 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 8210 (mac_addr[0]) | (mac_addr[1] << 8); 8211 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 8212 8213 hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8214 if (is_mc) { 8215 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 8216 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8217 } 8218 8219 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 8220 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 8221 } 8222 8223 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 8224 struct hclge_mac_vlan_tbl_entry_cmd *req) 8225 { 8226 struct hclge_dev *hdev = vport->back; 8227 struct hclge_desc desc; 8228 u8 resp_code; 8229 u16 retval; 8230 int ret; 8231 8232 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 8233 8234 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8235 8236 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8237 if (ret) { 8238 dev_err(&hdev->pdev->dev, 8239 "del mac addr failed for cmd_send, ret =%d.\n", 8240 ret); 8241 return ret; 8242 } 8243 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8244 retval = le16_to_cpu(desc.retval); 8245 8246 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8247 HCLGE_MAC_VLAN_REMOVE); 8248 } 8249 8250 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 8251 struct hclge_mac_vlan_tbl_entry_cmd *req, 8252 struct hclge_desc *desc, 8253 bool is_mc) 8254 { 8255 struct hclge_dev *hdev = vport->back; 8256 u8 resp_code; 8257 u16 retval; 8258 int ret; 8259 8260 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 8261 if (is_mc) { 8262 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8263 memcpy(desc[0].data, 8264 req, 8265 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8266 hclge_cmd_setup_basic_desc(&desc[1], 8267 HCLGE_OPC_MAC_VLAN_ADD, 8268 true); 8269 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8270 hclge_cmd_setup_basic_desc(&desc[2], 8271 HCLGE_OPC_MAC_VLAN_ADD, 8272 true); 8273 ret = hclge_cmd_send(&hdev->hw, desc, 3); 8274 } else { 8275 memcpy(desc[0].data, 8276 req, 8277 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8278 ret = hclge_cmd_send(&hdev->hw, desc, 1); 8279 } 8280 if (ret) { 8281 dev_err(&hdev->pdev->dev, 8282 "lookup mac addr failed for cmd_send, ret =%d.\n", 8283 ret); 8284 return ret; 8285 } 8286 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 8287 retval = le16_to_cpu(desc[0].retval); 8288 8289 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8290 HCLGE_MAC_VLAN_LKUP); 8291 } 8292 8293 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 8294 struct hclge_mac_vlan_tbl_entry_cmd *req, 8295 struct hclge_desc *mc_desc) 8296 { 8297 struct hclge_dev *hdev = vport->back; 8298 int cfg_status; 8299 u8 resp_code; 8300 u16 retval; 8301 int ret; 8302 8303 if (!mc_desc) { 8304 struct hclge_desc desc; 8305 8306 hclge_cmd_setup_basic_desc(&desc, 8307 HCLGE_OPC_MAC_VLAN_ADD, 8308 false); 8309 memcpy(desc.data, req, 8310 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8311 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8312 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8313 retval = le16_to_cpu(desc.retval); 8314 8315 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8316 resp_code, 8317 HCLGE_MAC_VLAN_ADD); 8318 } else { 8319 hclge_comm_cmd_reuse_desc(&mc_desc[0], false); 8320 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8321 hclge_comm_cmd_reuse_desc(&mc_desc[1], false); 8322 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8323 hclge_comm_cmd_reuse_desc(&mc_desc[2], false); 8324 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT); 8325 memcpy(mc_desc[0].data, req, 8326 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8327 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 8328 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 8329 retval = le16_to_cpu(mc_desc[0].retval); 8330 8331 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8332 resp_code, 8333 HCLGE_MAC_VLAN_ADD); 8334 } 8335 8336 if (ret) { 8337 dev_err(&hdev->pdev->dev, 8338 "add mac addr failed for cmd_send, ret =%d.\n", 8339 ret); 8340 return ret; 8341 } 8342 8343 return cfg_status; 8344 } 8345 8346 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 8347 u16 *allocated_size) 8348 { 8349 struct hclge_umv_spc_alc_cmd *req; 8350 struct hclge_desc desc; 8351 int ret; 8352 8353 req = (struct hclge_umv_spc_alc_cmd *)desc.data; 8354 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false); 8355 8356 req->space_size = cpu_to_le32(space_size); 8357 8358 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8359 if (ret) { 8360 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n", 8361 ret); 8362 return ret; 8363 } 8364 8365 *allocated_size = le32_to_cpu(desc.data[1]); 8366 8367 return 0; 8368 } 8369 8370 static int hclge_init_umv_space(struct hclge_dev *hdev) 8371 { 8372 u16 allocated_size = 0; 8373 int ret; 8374 8375 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size); 8376 if (ret) 8377 return ret; 8378 8379 if (allocated_size < hdev->wanted_umv_size) 8380 dev_warn(&hdev->pdev->dev, 8381 "failed to alloc umv space, want %u, get %u\n", 8382 hdev->wanted_umv_size, allocated_size); 8383 8384 hdev->max_umv_size = allocated_size; 8385 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1); 8386 hdev->share_umv_size = hdev->priv_umv_size + 8387 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8388 8389 if (hdev->ae_dev->dev_specs.mc_mac_size) 8390 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps); 8391 8392 return 0; 8393 } 8394 8395 static void hclge_reset_umv_space(struct hclge_dev *hdev) 8396 { 8397 struct hclge_vport *vport; 8398 int i; 8399 8400 for (i = 0; i < hdev->num_alloc_vport; i++) { 8401 vport = &hdev->vport[i]; 8402 vport->used_umv_num = 0; 8403 } 8404 8405 mutex_lock(&hdev->vport_lock); 8406 hdev->share_umv_size = hdev->priv_umv_size + 8407 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8408 mutex_unlock(&hdev->vport_lock); 8409 8410 hdev->used_mc_mac_num = 0; 8411 } 8412 8413 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock) 8414 { 8415 struct hclge_dev *hdev = vport->back; 8416 bool is_full; 8417 8418 if (need_lock) 8419 mutex_lock(&hdev->vport_lock); 8420 8421 is_full = (vport->used_umv_num >= hdev->priv_umv_size && 8422 hdev->share_umv_size == 0); 8423 8424 if (need_lock) 8425 mutex_unlock(&hdev->vport_lock); 8426 8427 return is_full; 8428 } 8429 8430 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free) 8431 { 8432 struct hclge_dev *hdev = vport->back; 8433 8434 if (is_free) { 8435 if (vport->used_umv_num > hdev->priv_umv_size) 8436 hdev->share_umv_size++; 8437 8438 if (vport->used_umv_num > 0) 8439 vport->used_umv_num--; 8440 } else { 8441 if (vport->used_umv_num >= hdev->priv_umv_size && 8442 hdev->share_umv_size > 0) 8443 hdev->share_umv_size--; 8444 vport->used_umv_num++; 8445 } 8446 } 8447 8448 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list, 8449 const u8 *mac_addr) 8450 { 8451 struct hclge_mac_node *mac_node, *tmp; 8452 8453 list_for_each_entry_safe(mac_node, tmp, list, node) 8454 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 8455 return mac_node; 8456 8457 return NULL; 8458 } 8459 8460 static void hclge_update_mac_node(struct hclge_mac_node *mac_node, 8461 enum HCLGE_MAC_NODE_STATE state) 8462 { 8463 switch (state) { 8464 /* from set_rx_mode or tmp_add_list */ 8465 case HCLGE_MAC_TO_ADD: 8466 if (mac_node->state == HCLGE_MAC_TO_DEL) 8467 mac_node->state = HCLGE_MAC_ACTIVE; 8468 break; 8469 /* only from set_rx_mode */ 8470 case HCLGE_MAC_TO_DEL: 8471 if (mac_node->state == HCLGE_MAC_TO_ADD) { 8472 list_del(&mac_node->node); 8473 kfree(mac_node); 8474 } else { 8475 mac_node->state = HCLGE_MAC_TO_DEL; 8476 } 8477 break; 8478 /* only from tmp_add_list, the mac_node->state won't be 8479 * ACTIVE. 8480 */ 8481 case HCLGE_MAC_ACTIVE: 8482 if (mac_node->state == HCLGE_MAC_TO_ADD) 8483 mac_node->state = HCLGE_MAC_ACTIVE; 8484 8485 break; 8486 } 8487 } 8488 8489 int hclge_update_mac_list(struct hclge_vport *vport, 8490 enum HCLGE_MAC_NODE_STATE state, 8491 enum HCLGE_MAC_ADDR_TYPE mac_type, 8492 const unsigned char *addr) 8493 { 8494 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8495 struct hclge_dev *hdev = vport->back; 8496 struct hclge_mac_node *mac_node; 8497 struct list_head *list; 8498 8499 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8500 &vport->uc_mac_list : &vport->mc_mac_list; 8501 8502 spin_lock_bh(&vport->mac_list_lock); 8503 8504 /* if the mac addr is already in the mac list, no need to add a new 8505 * one into it, just check the mac addr state, convert it to a new 8506 * state, or just remove it, or do nothing. 8507 */ 8508 mac_node = hclge_find_mac_node(list, addr); 8509 if (mac_node) { 8510 hclge_update_mac_node(mac_node, state); 8511 spin_unlock_bh(&vport->mac_list_lock); 8512 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8513 return 0; 8514 } 8515 8516 /* if this address is never added, unnecessary to delete */ 8517 if (state == HCLGE_MAC_TO_DEL) { 8518 spin_unlock_bh(&vport->mac_list_lock); 8519 hnae3_format_mac_addr(format_mac_addr, addr); 8520 dev_err(&hdev->pdev->dev, 8521 "failed to delete address %s from mac list\n", 8522 format_mac_addr); 8523 return -ENOENT; 8524 } 8525 8526 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 8527 if (!mac_node) { 8528 spin_unlock_bh(&vport->mac_list_lock); 8529 return -ENOMEM; 8530 } 8531 8532 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8533 8534 mac_node->state = state; 8535 ether_addr_copy(mac_node->mac_addr, addr); 8536 list_add_tail(&mac_node->node, list); 8537 8538 spin_unlock_bh(&vport->mac_list_lock); 8539 8540 return 0; 8541 } 8542 8543 static int hclge_add_uc_addr(struct hnae3_handle *handle, 8544 const unsigned char *addr) 8545 { 8546 struct hclge_vport *vport = hclge_get_vport(handle); 8547 8548 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC, 8549 addr); 8550 } 8551 8552 int hclge_add_uc_addr_common(struct hclge_vport *vport, 8553 const unsigned char *addr) 8554 { 8555 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8556 struct hclge_dev *hdev = vport->back; 8557 struct hclge_mac_vlan_tbl_entry_cmd req; 8558 struct hclge_desc desc; 8559 u16 egress_port = 0; 8560 int ret; 8561 8562 /* mac addr check */ 8563 if (is_zero_ether_addr(addr) || 8564 is_broadcast_ether_addr(addr) || 8565 is_multicast_ether_addr(addr)) { 8566 hnae3_format_mac_addr(format_mac_addr, addr); 8567 dev_err(&hdev->pdev->dev, 8568 "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n", 8569 format_mac_addr, is_zero_ether_addr(addr), 8570 is_broadcast_ether_addr(addr), 8571 is_multicast_ether_addr(addr)); 8572 return -EINVAL; 8573 } 8574 8575 memset(&req, 0, sizeof(req)); 8576 8577 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 8578 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 8579 8580 req.egress_port = cpu_to_le16(egress_port); 8581 8582 hclge_prepare_mac_addr(&req, addr, false); 8583 8584 /* Lookup the mac address in the mac_vlan table, and add 8585 * it if the entry is inexistent. Repeated unicast entry 8586 * is not allowed in the mac vlan table. 8587 */ 8588 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 8589 if (ret == -ENOENT) { 8590 mutex_lock(&hdev->vport_lock); 8591 if (!hclge_is_umv_space_full(vport, false)) { 8592 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL); 8593 if (!ret) 8594 hclge_update_umv_space(vport, false); 8595 mutex_unlock(&hdev->vport_lock); 8596 return ret; 8597 } 8598 mutex_unlock(&hdev->vport_lock); 8599 8600 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE)) 8601 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n", 8602 hdev->priv_umv_size); 8603 8604 return -ENOSPC; 8605 } 8606 8607 /* check if we just hit the duplicate */ 8608 if (!ret) 8609 return -EEXIST; 8610 8611 return ret; 8612 } 8613 8614 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 8615 const unsigned char *addr) 8616 { 8617 struct hclge_vport *vport = hclge_get_vport(handle); 8618 8619 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC, 8620 addr); 8621 } 8622 8623 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 8624 const unsigned char *addr) 8625 { 8626 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8627 struct hclge_dev *hdev = vport->back; 8628 struct hclge_mac_vlan_tbl_entry_cmd req; 8629 int ret; 8630 8631 /* mac addr check */ 8632 if (is_zero_ether_addr(addr) || 8633 is_broadcast_ether_addr(addr) || 8634 is_multicast_ether_addr(addr)) { 8635 hnae3_format_mac_addr(format_mac_addr, addr); 8636 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n", 8637 format_mac_addr); 8638 return -EINVAL; 8639 } 8640 8641 memset(&req, 0, sizeof(req)); 8642 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 8643 hclge_prepare_mac_addr(&req, addr, false); 8644 ret = hclge_remove_mac_vlan_tbl(vport, &req); 8645 if (!ret || ret == -ENOENT) { 8646 mutex_lock(&hdev->vport_lock); 8647 hclge_update_umv_space(vport, true); 8648 mutex_unlock(&hdev->vport_lock); 8649 return 0; 8650 } 8651 8652 return ret; 8653 } 8654 8655 static int hclge_add_mc_addr(struct hnae3_handle *handle, 8656 const unsigned char *addr) 8657 { 8658 struct hclge_vport *vport = hclge_get_vport(handle); 8659 8660 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC, 8661 addr); 8662 } 8663 8664 int hclge_add_mc_addr_common(struct hclge_vport *vport, 8665 const unsigned char *addr) 8666 { 8667 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8668 struct hclge_dev *hdev = vport->back; 8669 struct hclge_mac_vlan_tbl_entry_cmd req; 8670 struct hclge_desc desc[3]; 8671 bool is_new_addr = false; 8672 int status; 8673 8674 /* mac addr check */ 8675 if (!is_multicast_ether_addr(addr)) { 8676 hnae3_format_mac_addr(format_mac_addr, addr); 8677 dev_err(&hdev->pdev->dev, 8678 "Add mc mac err! invalid mac:%s.\n", 8679 format_mac_addr); 8680 return -EINVAL; 8681 } 8682 memset(&req, 0, sizeof(req)); 8683 hclge_prepare_mac_addr(&req, addr, true); 8684 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8685 if (status) { 8686 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) && 8687 hdev->used_mc_mac_num >= 8688 hdev->ae_dev->dev_specs.mc_mac_size) 8689 goto err_no_space; 8690 8691 is_new_addr = true; 8692 8693 /* This mac addr do not exist, add new entry for it */ 8694 memset(desc[0].data, 0, sizeof(desc[0].data)); 8695 memset(desc[1].data, 0, sizeof(desc[0].data)); 8696 memset(desc[2].data, 0, sizeof(desc[0].data)); 8697 } 8698 status = hclge_update_desc_vfid(desc, vport->vport_id, false); 8699 if (status) 8700 return status; 8701 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8702 if (status == -ENOSPC) 8703 goto err_no_space; 8704 else if (!status && is_new_addr) 8705 hdev->used_mc_mac_num++; 8706 8707 return status; 8708 8709 err_no_space: 8710 /* if already overflow, not to print each time */ 8711 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) { 8712 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8713 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n"); 8714 } 8715 8716 return -ENOSPC; 8717 } 8718 8719 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 8720 const unsigned char *addr) 8721 { 8722 struct hclge_vport *vport = hclge_get_vport(handle); 8723 8724 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC, 8725 addr); 8726 } 8727 8728 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 8729 const unsigned char *addr) 8730 { 8731 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8732 struct hclge_dev *hdev = vport->back; 8733 struct hclge_mac_vlan_tbl_entry_cmd req; 8734 enum hclge_comm_cmd_status status; 8735 struct hclge_desc desc[3]; 8736 8737 /* mac addr check */ 8738 if (!is_multicast_ether_addr(addr)) { 8739 hnae3_format_mac_addr(format_mac_addr, addr); 8740 dev_dbg(&hdev->pdev->dev, 8741 "Remove mc mac err! invalid mac:%s.\n", 8742 format_mac_addr); 8743 return -EINVAL; 8744 } 8745 8746 memset(&req, 0, sizeof(req)); 8747 hclge_prepare_mac_addr(&req, addr, true); 8748 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8749 if (!status) { 8750 /* This mac addr exist, remove this handle's VFID for it */ 8751 status = hclge_update_desc_vfid(desc, vport->vport_id, true); 8752 if (status) 8753 return status; 8754 8755 if (hclge_is_all_function_id_zero(desc)) { 8756 /* All the vfid is zero, so need to delete this entry */ 8757 status = hclge_remove_mac_vlan_tbl(vport, &req); 8758 if (!status) 8759 hdev->used_mc_mac_num--; 8760 } else { 8761 /* Not all the vfid is zero, update the vfid */ 8762 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8763 } 8764 } else if (status == -ENOENT) { 8765 status = 0; 8766 } 8767 8768 return status; 8769 } 8770 8771 static void hclge_sync_vport_mac_list(struct hclge_vport *vport, 8772 struct list_head *list, 8773 enum HCLGE_MAC_ADDR_TYPE mac_type) 8774 { 8775 int (*sync)(struct hclge_vport *vport, const unsigned char *addr); 8776 struct hclge_mac_node *mac_node, *tmp; 8777 int ret; 8778 8779 if (mac_type == HCLGE_MAC_ADDR_UC) 8780 sync = hclge_add_uc_addr_common; 8781 else 8782 sync = hclge_add_mc_addr_common; 8783 8784 list_for_each_entry_safe(mac_node, tmp, list, node) { 8785 ret = sync(vport, mac_node->mac_addr); 8786 if (!ret) { 8787 mac_node->state = HCLGE_MAC_ACTIVE; 8788 } else { 8789 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8790 &vport->state); 8791 8792 /* If one unicast mac address is existing in hardware, 8793 * we need to try whether other unicast mac addresses 8794 * are new addresses that can be added. 8795 * Multicast mac address can be reusable, even though 8796 * there is no space to add new multicast mac address, 8797 * we should check whether other mac addresses are 8798 * existing in hardware for reuse. 8799 */ 8800 if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) || 8801 (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC)) 8802 break; 8803 } 8804 } 8805 } 8806 8807 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport, 8808 struct list_head *list, 8809 enum HCLGE_MAC_ADDR_TYPE mac_type) 8810 { 8811 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 8812 struct hclge_mac_node *mac_node, *tmp; 8813 int ret; 8814 8815 if (mac_type == HCLGE_MAC_ADDR_UC) 8816 unsync = hclge_rm_uc_addr_common; 8817 else 8818 unsync = hclge_rm_mc_addr_common; 8819 8820 list_for_each_entry_safe(mac_node, tmp, list, node) { 8821 ret = unsync(vport, mac_node->mac_addr); 8822 if (!ret || ret == -ENOENT) { 8823 list_del(&mac_node->node); 8824 kfree(mac_node); 8825 } else { 8826 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8827 &vport->state); 8828 break; 8829 } 8830 } 8831 } 8832 8833 static bool hclge_sync_from_add_list(struct list_head *add_list, 8834 struct list_head *mac_list) 8835 { 8836 struct hclge_mac_node *mac_node, *tmp, *new_node; 8837 bool all_added = true; 8838 8839 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 8840 if (mac_node->state == HCLGE_MAC_TO_ADD) 8841 all_added = false; 8842 8843 /* if the mac address from tmp_add_list is not in the 8844 * uc/mc_mac_list, it means have received a TO_DEL request 8845 * during the time window of adding the mac address into mac 8846 * table. if mac_node state is ACTIVE, then change it to TO_DEL, 8847 * then it will be removed at next time. else it must be TO_ADD, 8848 * this address hasn't been added into mac table, 8849 * so just remove the mac node. 8850 */ 8851 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8852 if (new_node) { 8853 hclge_update_mac_node(new_node, mac_node->state); 8854 list_del(&mac_node->node); 8855 kfree(mac_node); 8856 } else if (mac_node->state == HCLGE_MAC_ACTIVE) { 8857 mac_node->state = HCLGE_MAC_TO_DEL; 8858 list_move_tail(&mac_node->node, mac_list); 8859 } else { 8860 list_del(&mac_node->node); 8861 kfree(mac_node); 8862 } 8863 } 8864 8865 return all_added; 8866 } 8867 8868 static void hclge_sync_from_del_list(struct list_head *del_list, 8869 struct list_head *mac_list) 8870 { 8871 struct hclge_mac_node *mac_node, *tmp, *new_node; 8872 8873 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 8874 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8875 if (new_node) { 8876 /* If the mac addr exists in the mac list, it means 8877 * received a new TO_ADD request during the time window 8878 * of configuring the mac address. For the mac node 8879 * state is TO_ADD, and the address is already in the 8880 * in the hardware(due to delete fail), so we just need 8881 * to change the mac node state to ACTIVE. 8882 */ 8883 new_node->state = HCLGE_MAC_ACTIVE; 8884 list_del(&mac_node->node); 8885 kfree(mac_node); 8886 } else { 8887 list_move_tail(&mac_node->node, mac_list); 8888 } 8889 } 8890 } 8891 8892 static void hclge_update_overflow_flags(struct hclge_vport *vport, 8893 enum HCLGE_MAC_ADDR_TYPE mac_type, 8894 bool is_all_added) 8895 { 8896 if (mac_type == HCLGE_MAC_ADDR_UC) { 8897 if (is_all_added) 8898 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE; 8899 else 8900 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE; 8901 } else { 8902 if (is_all_added) 8903 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE; 8904 else 8905 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8906 } 8907 } 8908 8909 static void hclge_sync_vport_mac_table(struct hclge_vport *vport, 8910 enum HCLGE_MAC_ADDR_TYPE mac_type) 8911 { 8912 struct hclge_mac_node *mac_node, *tmp, *new_node; 8913 struct list_head tmp_add_list, tmp_del_list; 8914 struct list_head *list; 8915 bool all_added; 8916 8917 INIT_LIST_HEAD(&tmp_add_list); 8918 INIT_LIST_HEAD(&tmp_del_list); 8919 8920 /* move the mac addr to the tmp_add_list and tmp_del_list, then 8921 * we can add/delete these mac addr outside the spin lock 8922 */ 8923 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8924 &vport->uc_mac_list : &vport->mc_mac_list; 8925 8926 spin_lock_bh(&vport->mac_list_lock); 8927 8928 list_for_each_entry_safe(mac_node, tmp, list, node) { 8929 switch (mac_node->state) { 8930 case HCLGE_MAC_TO_DEL: 8931 list_move_tail(&mac_node->node, &tmp_del_list); 8932 break; 8933 case HCLGE_MAC_TO_ADD: 8934 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 8935 if (!new_node) 8936 goto stop_traverse; 8937 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 8938 new_node->state = mac_node->state; 8939 list_add_tail(&new_node->node, &tmp_add_list); 8940 break; 8941 default: 8942 break; 8943 } 8944 } 8945 8946 stop_traverse: 8947 spin_unlock_bh(&vport->mac_list_lock); 8948 8949 /* delete first, in order to get max mac table space for adding */ 8950 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 8951 hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type); 8952 8953 /* if some mac addresses were added/deleted fail, move back to the 8954 * mac_list, and retry at next time. 8955 */ 8956 spin_lock_bh(&vport->mac_list_lock); 8957 8958 hclge_sync_from_del_list(&tmp_del_list, list); 8959 all_added = hclge_sync_from_add_list(&tmp_add_list, list); 8960 8961 spin_unlock_bh(&vport->mac_list_lock); 8962 8963 hclge_update_overflow_flags(vport, mac_type, all_added); 8964 } 8965 8966 static bool hclge_need_sync_mac_table(struct hclge_vport *vport) 8967 { 8968 struct hclge_dev *hdev = vport->back; 8969 8970 if (test_bit(vport->vport_id, hdev->vport_config_block)) 8971 return false; 8972 8973 if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state)) 8974 return true; 8975 8976 return false; 8977 } 8978 8979 static void hclge_sync_mac_table(struct hclge_dev *hdev) 8980 { 8981 int i; 8982 8983 for (i = 0; i < hdev->num_alloc_vport; i++) { 8984 struct hclge_vport *vport = &hdev->vport[i]; 8985 8986 if (!hclge_need_sync_mac_table(vport)) 8987 continue; 8988 8989 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC); 8990 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC); 8991 } 8992 } 8993 8994 static void hclge_build_del_list(struct list_head *list, 8995 bool is_del_list, 8996 struct list_head *tmp_del_list) 8997 { 8998 struct hclge_mac_node *mac_cfg, *tmp; 8999 9000 list_for_each_entry_safe(mac_cfg, tmp, list, node) { 9001 switch (mac_cfg->state) { 9002 case HCLGE_MAC_TO_DEL: 9003 case HCLGE_MAC_ACTIVE: 9004 list_move_tail(&mac_cfg->node, tmp_del_list); 9005 break; 9006 case HCLGE_MAC_TO_ADD: 9007 if (is_del_list) { 9008 list_del(&mac_cfg->node); 9009 kfree(mac_cfg); 9010 } 9011 break; 9012 } 9013 } 9014 } 9015 9016 static void hclge_unsync_del_list(struct hclge_vport *vport, 9017 int (*unsync)(struct hclge_vport *vport, 9018 const unsigned char *addr), 9019 bool is_del_list, 9020 struct list_head *tmp_del_list) 9021 { 9022 struct hclge_mac_node *mac_cfg, *tmp; 9023 int ret; 9024 9025 list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) { 9026 ret = unsync(vport, mac_cfg->mac_addr); 9027 if (!ret || ret == -ENOENT) { 9028 /* clear all mac addr from hardware, but remain these 9029 * mac addr in the mac list, and restore them after 9030 * vf reset finished. 9031 */ 9032 if (!is_del_list && 9033 mac_cfg->state == HCLGE_MAC_ACTIVE) { 9034 mac_cfg->state = HCLGE_MAC_TO_ADD; 9035 } else { 9036 list_del(&mac_cfg->node); 9037 kfree(mac_cfg); 9038 } 9039 } else if (is_del_list) { 9040 mac_cfg->state = HCLGE_MAC_TO_DEL; 9041 } 9042 } 9043 } 9044 9045 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 9046 enum HCLGE_MAC_ADDR_TYPE mac_type) 9047 { 9048 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 9049 struct hclge_dev *hdev = vport->back; 9050 struct list_head tmp_del_list, *list; 9051 9052 if (mac_type == HCLGE_MAC_ADDR_UC) { 9053 list = &vport->uc_mac_list; 9054 unsync = hclge_rm_uc_addr_common; 9055 } else { 9056 list = &vport->mc_mac_list; 9057 unsync = hclge_rm_mc_addr_common; 9058 } 9059 9060 INIT_LIST_HEAD(&tmp_del_list); 9061 9062 if (!is_del_list) 9063 set_bit(vport->vport_id, hdev->vport_config_block); 9064 9065 spin_lock_bh(&vport->mac_list_lock); 9066 9067 hclge_build_del_list(list, is_del_list, &tmp_del_list); 9068 9069 spin_unlock_bh(&vport->mac_list_lock); 9070 9071 hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list); 9072 9073 spin_lock_bh(&vport->mac_list_lock); 9074 9075 hclge_sync_from_del_list(&tmp_del_list, list); 9076 9077 spin_unlock_bh(&vport->mac_list_lock); 9078 } 9079 9080 /* remove all mac address when uninitailize */ 9081 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport, 9082 enum HCLGE_MAC_ADDR_TYPE mac_type) 9083 { 9084 struct hclge_mac_node *mac_node, *tmp; 9085 struct hclge_dev *hdev = vport->back; 9086 struct list_head tmp_del_list, *list; 9087 9088 INIT_LIST_HEAD(&tmp_del_list); 9089 9090 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 9091 &vport->uc_mac_list : &vport->mc_mac_list; 9092 9093 spin_lock_bh(&vport->mac_list_lock); 9094 9095 list_for_each_entry_safe(mac_node, tmp, list, node) { 9096 switch (mac_node->state) { 9097 case HCLGE_MAC_TO_DEL: 9098 case HCLGE_MAC_ACTIVE: 9099 list_move_tail(&mac_node->node, &tmp_del_list); 9100 break; 9101 case HCLGE_MAC_TO_ADD: 9102 list_del(&mac_node->node); 9103 kfree(mac_node); 9104 break; 9105 } 9106 } 9107 9108 spin_unlock_bh(&vport->mac_list_lock); 9109 9110 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 9111 9112 if (!list_empty(&tmp_del_list)) 9113 dev_warn(&hdev->pdev->dev, 9114 "uninit %s mac list for vport %u not completely.\n", 9115 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc", 9116 vport->vport_id); 9117 9118 list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) { 9119 list_del(&mac_node->node); 9120 kfree(mac_node); 9121 } 9122 } 9123 9124 static void hclge_uninit_mac_table(struct hclge_dev *hdev) 9125 { 9126 struct hclge_vport *vport; 9127 int i; 9128 9129 for (i = 0; i < hdev->num_alloc_vport; i++) { 9130 vport = &hdev->vport[i]; 9131 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC); 9132 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC); 9133 } 9134 } 9135 9136 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 9137 u16 cmdq_resp, u8 resp_code) 9138 { 9139 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 9140 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 9141 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 9142 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 9143 9144 int return_status; 9145 9146 if (cmdq_resp) { 9147 dev_err(&hdev->pdev->dev, 9148 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 9149 cmdq_resp); 9150 return -EIO; 9151 } 9152 9153 switch (resp_code) { 9154 case HCLGE_ETHERTYPE_SUCCESS_ADD: 9155 case HCLGE_ETHERTYPE_ALREADY_ADD: 9156 return_status = 0; 9157 break; 9158 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 9159 dev_err(&hdev->pdev->dev, 9160 "add mac ethertype failed for manager table overflow.\n"); 9161 return_status = -EIO; 9162 break; 9163 case HCLGE_ETHERTYPE_KEY_CONFLICT: 9164 dev_err(&hdev->pdev->dev, 9165 "add mac ethertype failed for key conflict.\n"); 9166 return_status = -EIO; 9167 break; 9168 default: 9169 dev_err(&hdev->pdev->dev, 9170 "add mac ethertype failed for undefined, code=%u.\n", 9171 resp_code); 9172 return_status = -EIO; 9173 } 9174 9175 return return_status; 9176 } 9177 9178 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf, 9179 u8 *mac_addr) 9180 { 9181 struct hclge_vport *vport = hclge_get_vport(handle); 9182 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9183 struct hclge_dev *hdev = vport->back; 9184 9185 vport = hclge_get_vf_vport(hdev, vf); 9186 if (!vport) 9187 return -EINVAL; 9188 9189 hnae3_format_mac_addr(format_mac_addr, mac_addr); 9190 if (ether_addr_equal(mac_addr, vport->vf_info.mac)) { 9191 dev_info(&hdev->pdev->dev, 9192 "Specified MAC(=%s) is same as before, no change committed!\n", 9193 format_mac_addr); 9194 return 0; 9195 } 9196 9197 ether_addr_copy(vport->vf_info.mac, mac_addr); 9198 9199 /* there is a timewindow for PF to know VF unalive, it may 9200 * cause send mailbox fail, but it doesn't matter, VF will 9201 * query it when reinit. 9202 */ 9203 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) { 9204 dev_info(&hdev->pdev->dev, 9205 "MAC of VF %d has been set to %s, and it will be reinitialized!\n", 9206 vf, format_mac_addr); 9207 (void)hclge_inform_reset_assert_to_vf(vport); 9208 return 0; 9209 } 9210 9211 dev_info(&hdev->pdev->dev, "MAC of VF %d has been set to %s\n", 9212 vf, format_mac_addr); 9213 return 0; 9214 } 9215 9216 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 9217 const struct hclge_mac_mgr_tbl_entry_cmd *req) 9218 { 9219 struct hclge_desc desc; 9220 u8 resp_code; 9221 u16 retval; 9222 int ret; 9223 9224 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 9225 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 9226 9227 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9228 if (ret) { 9229 dev_err(&hdev->pdev->dev, 9230 "add mac ethertype failed for cmd_send, ret =%d.\n", 9231 ret); 9232 return ret; 9233 } 9234 9235 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 9236 retval = le16_to_cpu(desc.retval); 9237 9238 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 9239 } 9240 9241 static int init_mgr_tbl(struct hclge_dev *hdev) 9242 { 9243 int ret; 9244 int i; 9245 9246 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 9247 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 9248 if (ret) { 9249 dev_err(&hdev->pdev->dev, 9250 "add mac ethertype failed, ret =%d.\n", 9251 ret); 9252 return ret; 9253 } 9254 } 9255 9256 return 0; 9257 } 9258 9259 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 9260 { 9261 struct hclge_vport *vport = hclge_get_vport(handle); 9262 struct hclge_dev *hdev = vport->back; 9263 9264 ether_addr_copy(p, hdev->hw.mac.mac_addr); 9265 } 9266 9267 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 9268 const u8 *old_addr, const u8 *new_addr) 9269 { 9270 struct list_head *list = &vport->uc_mac_list; 9271 struct hclge_mac_node *old_node, *new_node; 9272 9273 new_node = hclge_find_mac_node(list, new_addr); 9274 if (!new_node) { 9275 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 9276 if (!new_node) 9277 return -ENOMEM; 9278 9279 new_node->state = HCLGE_MAC_TO_ADD; 9280 ether_addr_copy(new_node->mac_addr, new_addr); 9281 list_add(&new_node->node, list); 9282 } else { 9283 if (new_node->state == HCLGE_MAC_TO_DEL) 9284 new_node->state = HCLGE_MAC_ACTIVE; 9285 9286 /* make sure the new addr is in the list head, avoid dev 9287 * addr may be not re-added into mac table for the umv space 9288 * limitation after global/imp reset which will clear mac 9289 * table by hardware. 9290 */ 9291 list_move(&new_node->node, list); 9292 } 9293 9294 if (old_addr && !ether_addr_equal(old_addr, new_addr)) { 9295 old_node = hclge_find_mac_node(list, old_addr); 9296 if (old_node) { 9297 if (old_node->state == HCLGE_MAC_TO_ADD) { 9298 list_del(&old_node->node); 9299 kfree(old_node); 9300 } else { 9301 old_node->state = HCLGE_MAC_TO_DEL; 9302 } 9303 } 9304 } 9305 9306 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 9307 9308 return 0; 9309 } 9310 9311 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p, 9312 bool is_first) 9313 { 9314 const unsigned char *new_addr = (const unsigned char *)p; 9315 struct hclge_vport *vport = hclge_get_vport(handle); 9316 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9317 struct hclge_dev *hdev = vport->back; 9318 unsigned char *old_addr = NULL; 9319 int ret; 9320 9321 /* mac addr check */ 9322 if (is_zero_ether_addr(new_addr) || 9323 is_broadcast_ether_addr(new_addr) || 9324 is_multicast_ether_addr(new_addr)) { 9325 hnae3_format_mac_addr(format_mac_addr, new_addr); 9326 dev_err(&hdev->pdev->dev, 9327 "change uc mac err! invalid mac: %s.\n", 9328 format_mac_addr); 9329 return -EINVAL; 9330 } 9331 9332 ret = hclge_pause_addr_cfg(hdev, new_addr); 9333 if (ret) { 9334 dev_err(&hdev->pdev->dev, 9335 "failed to configure mac pause address, ret = %d\n", 9336 ret); 9337 return ret; 9338 } 9339 9340 if (!is_first) 9341 old_addr = hdev->hw.mac.mac_addr; 9342 9343 spin_lock_bh(&vport->mac_list_lock); 9344 ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr); 9345 if (ret) { 9346 hnae3_format_mac_addr(format_mac_addr, new_addr); 9347 dev_err(&hdev->pdev->dev, 9348 "failed to change the mac addr:%s, ret = %d\n", 9349 format_mac_addr, ret); 9350 spin_unlock_bh(&vport->mac_list_lock); 9351 9352 if (!is_first) 9353 hclge_pause_addr_cfg(hdev, old_addr); 9354 9355 return ret; 9356 } 9357 /* we must update dev addr with spin lock protect, preventing dev addr 9358 * being removed by set_rx_mode path. 9359 */ 9360 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 9361 spin_unlock_bh(&vport->mac_list_lock); 9362 9363 hclge_task_schedule(hdev, 0); 9364 9365 return 0; 9366 } 9367 9368 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd) 9369 { 9370 struct mii_ioctl_data *data = if_mii(ifr); 9371 9372 if (!hnae3_dev_phy_imp_supported(hdev)) 9373 return -EOPNOTSUPP; 9374 9375 switch (cmd) { 9376 case SIOCGMIIPHY: 9377 data->phy_id = hdev->hw.mac.phy_addr; 9378 /* this command reads phy id and register at the same time */ 9379 fallthrough; 9380 case SIOCGMIIREG: 9381 data->val_out = hclge_read_phy_reg(hdev, data->reg_num); 9382 return 0; 9383 9384 case SIOCSMIIREG: 9385 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in); 9386 default: 9387 return -EOPNOTSUPP; 9388 } 9389 } 9390 9391 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr, 9392 int cmd) 9393 { 9394 struct hclge_vport *vport = hclge_get_vport(handle); 9395 struct hclge_dev *hdev = vport->back; 9396 9397 switch (cmd) { 9398 case SIOCGHWTSTAMP: 9399 return hclge_ptp_get_cfg(hdev, ifr); 9400 case SIOCSHWTSTAMP: 9401 return hclge_ptp_set_cfg(hdev, ifr); 9402 default: 9403 if (!hdev->hw.mac.phydev) 9404 return hclge_mii_ioctl(hdev, ifr, cmd); 9405 } 9406 9407 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd); 9408 } 9409 9410 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id, 9411 bool bypass_en) 9412 { 9413 struct hclge_port_vlan_filter_bypass_cmd *req; 9414 struct hclge_desc desc; 9415 int ret; 9416 9417 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false); 9418 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 9419 req->vf_id = vf_id; 9420 hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B, 9421 bypass_en ? 1 : 0); 9422 9423 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9424 if (ret) 9425 dev_err(&hdev->pdev->dev, 9426 "failed to set vport%u port vlan filter bypass state, ret = %d.\n", 9427 vf_id, ret); 9428 9429 return ret; 9430 } 9431 9432 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 9433 u8 fe_type, bool filter_en, u8 vf_id) 9434 { 9435 struct hclge_vlan_filter_ctrl_cmd *req; 9436 struct hclge_desc desc; 9437 int ret; 9438 9439 /* read current vlan filter parameter */ 9440 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 9441 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 9442 req->vlan_type = vlan_type; 9443 req->vf_id = vf_id; 9444 9445 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9446 if (ret) { 9447 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n", 9448 vf_id, ret); 9449 return ret; 9450 } 9451 9452 /* modify and write new config parameter */ 9453 hclge_comm_cmd_reuse_desc(&desc, false); 9454 req->vlan_fe = filter_en ? 9455 (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type); 9456 9457 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9458 if (ret) 9459 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n", 9460 vf_id, ret); 9461 9462 return ret; 9463 } 9464 9465 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable) 9466 { 9467 struct hclge_dev *hdev = vport->back; 9468 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 9469 int ret; 9470 9471 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9472 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9473 HCLGE_FILTER_FE_EGRESS_V1_B, 9474 enable, vport->vport_id); 9475 9476 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9477 HCLGE_FILTER_FE_EGRESS, enable, 9478 vport->vport_id); 9479 if (ret) 9480 return ret; 9481 9482 if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) { 9483 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id, 9484 !enable); 9485 } else if (!vport->vport_id) { 9486 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 9487 enable = false; 9488 9489 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9490 HCLGE_FILTER_FE_INGRESS, 9491 enable, 0); 9492 } 9493 9494 return ret; 9495 } 9496 9497 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport) 9498 { 9499 struct hnae3_handle *handle = &vport->nic; 9500 struct hclge_vport_vlan_cfg *vlan, *tmp; 9501 struct hclge_dev *hdev = vport->back; 9502 9503 if (vport->vport_id) { 9504 if (vport->port_base_vlan_cfg.state != 9505 HNAE3_PORT_BASE_VLAN_DISABLE) 9506 return true; 9507 9508 if (vport->vf_info.trusted && vport->vf_info.request_uc_en) 9509 return false; 9510 } else if (handle->netdev_flags & HNAE3_USER_UPE) { 9511 return false; 9512 } 9513 9514 if (!vport->req_vlan_fltr_en) 9515 return false; 9516 9517 /* compatible with former device, always enable vlan filter */ 9518 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 9519 return true; 9520 9521 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) 9522 if (vlan->vlan_id != 0) 9523 return true; 9524 9525 return false; 9526 } 9527 9528 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) 9529 { 9530 struct hclge_dev *hdev = vport->back; 9531 bool need_en; 9532 int ret; 9533 9534 mutex_lock(&hdev->vport_lock); 9535 9536 vport->req_vlan_fltr_en = request_en; 9537 9538 need_en = hclge_need_enable_vport_vlan_filter(vport); 9539 if (need_en == vport->cur_vlan_fltr_en) { 9540 mutex_unlock(&hdev->vport_lock); 9541 return 0; 9542 } 9543 9544 ret = hclge_set_vport_vlan_filter(vport, need_en); 9545 if (ret) { 9546 mutex_unlock(&hdev->vport_lock); 9547 return ret; 9548 } 9549 9550 vport->cur_vlan_fltr_en = need_en; 9551 9552 mutex_unlock(&hdev->vport_lock); 9553 9554 return 0; 9555 } 9556 9557 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 9558 { 9559 struct hclge_vport *vport = hclge_get_vport(handle); 9560 9561 return hclge_enable_vport_vlan_filter(vport, enable); 9562 } 9563 9564 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid, 9565 bool is_kill, u16 vlan, 9566 struct hclge_desc *desc) 9567 { 9568 struct hclge_vlan_filter_vf_cfg_cmd *req0; 9569 struct hclge_vlan_filter_vf_cfg_cmd *req1; 9570 u8 vf_byte_val; 9571 u8 vf_byte_off; 9572 int ret; 9573 9574 hclge_cmd_setup_basic_desc(&desc[0], 9575 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9576 hclge_cmd_setup_basic_desc(&desc[1], 9577 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9578 9579 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 9580 9581 vf_byte_off = vfid / 8; 9582 vf_byte_val = 1 << (vfid % 8); 9583 9584 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9585 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 9586 9587 req0->vlan_id = cpu_to_le16(vlan); 9588 req0->vlan_cfg = is_kill; 9589 9590 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 9591 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 9592 else 9593 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 9594 9595 ret = hclge_cmd_send(&hdev->hw, desc, 2); 9596 if (ret) { 9597 dev_err(&hdev->pdev->dev, 9598 "Send vf vlan command fail, ret =%d.\n", 9599 ret); 9600 return ret; 9601 } 9602 9603 return 0; 9604 } 9605 9606 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid, 9607 bool is_kill, struct hclge_desc *desc) 9608 { 9609 struct hclge_vlan_filter_vf_cfg_cmd *req; 9610 9611 req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9612 9613 if (!is_kill) { 9614 #define HCLGE_VF_VLAN_NO_ENTRY 2 9615 if (!req->resp_code || req->resp_code == 1) 9616 return 0; 9617 9618 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 9619 set_bit(vfid, hdev->vf_vlan_full); 9620 dev_warn(&hdev->pdev->dev, 9621 "vf vlan table is full, vf vlan filter is disabled\n"); 9622 return 0; 9623 } 9624 9625 dev_err(&hdev->pdev->dev, 9626 "Add vf vlan filter fail, ret =%u.\n", 9627 req->resp_code); 9628 } else { 9629 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 9630 if (!req->resp_code) 9631 return 0; 9632 9633 /* vf vlan filter is disabled when vf vlan table is full, 9634 * then new vlan id will not be added into vf vlan table. 9635 * Just return 0 without warning, avoid massive verbose 9636 * print logs when unload. 9637 */ 9638 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) 9639 return 0; 9640 9641 dev_err(&hdev->pdev->dev, 9642 "Kill vf vlan filter fail, ret =%u.\n", 9643 req->resp_code); 9644 } 9645 9646 return -EIO; 9647 } 9648 9649 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid, 9650 bool is_kill, u16 vlan) 9651 { 9652 struct hclge_vport *vport = &hdev->vport[vfid]; 9653 struct hclge_desc desc[2]; 9654 int ret; 9655 9656 /* if vf vlan table is full, firmware will close vf vlan filter, it 9657 * is unable and unnecessary to add new vlan id to vf vlan filter. 9658 * If spoof check is enable, and vf vlan is full, it shouldn't add 9659 * new vlan, because tx packets with these vlan id will be dropped. 9660 */ 9661 if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) { 9662 if (vport->vf_info.spoofchk && vlan) { 9663 dev_err(&hdev->pdev->dev, 9664 "Can't add vlan due to spoof check is on and vf vlan table is full\n"); 9665 return -EPERM; 9666 } 9667 return 0; 9668 } 9669 9670 ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc); 9671 if (ret) 9672 return ret; 9673 9674 return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc); 9675 } 9676 9677 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 9678 u16 vlan_id, bool is_kill) 9679 { 9680 struct hclge_vlan_filter_pf_cfg_cmd *req; 9681 struct hclge_desc desc; 9682 u8 vlan_offset_byte_val; 9683 u8 vlan_offset_byte; 9684 u8 vlan_offset_160; 9685 int ret; 9686 9687 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 9688 9689 vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP; 9690 vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) / 9691 HCLGE_VLAN_BYTE_SIZE; 9692 vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE); 9693 9694 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 9695 req->vlan_offset = vlan_offset_160; 9696 req->vlan_cfg = is_kill; 9697 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 9698 9699 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9700 if (ret) 9701 dev_err(&hdev->pdev->dev, 9702 "port vlan command, send fail, ret =%d.\n", ret); 9703 return ret; 9704 } 9705 9706 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id, 9707 u16 vlan_id, bool is_kill) 9708 { 9709 /* vlan 0 may be added twice when 8021q module is enabled */ 9710 if (!is_kill && !vlan_id && 9711 test_bit(vport_id, hdev->vlan_table[vlan_id])) 9712 return false; 9713 9714 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 9715 dev_warn(&hdev->pdev->dev, 9716 "Add port vlan failed, vport %u is already in vlan %u\n", 9717 vport_id, vlan_id); 9718 return false; 9719 } 9720 9721 if (is_kill && 9722 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 9723 dev_warn(&hdev->pdev->dev, 9724 "Delete port vlan failed, vport %u is not in vlan %u\n", 9725 vport_id, vlan_id); 9726 return false; 9727 } 9728 9729 return true; 9730 } 9731 9732 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 9733 u16 vport_id, u16 vlan_id, 9734 bool is_kill) 9735 { 9736 u16 vport_idx, vport_num = 0; 9737 int ret; 9738 9739 if (is_kill && !vlan_id) 9740 return 0; 9741 9742 if (vlan_id >= VLAN_N_VID) 9743 return -EINVAL; 9744 9745 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id); 9746 if (ret) { 9747 dev_err(&hdev->pdev->dev, 9748 "Set %u vport vlan filter config fail, ret =%d.\n", 9749 vport_id, ret); 9750 return ret; 9751 } 9752 9753 if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill)) 9754 return 0; 9755 9756 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 9757 vport_num++; 9758 9759 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 9760 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 9761 is_kill); 9762 9763 return ret; 9764 } 9765 9766 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 9767 { 9768 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 9769 struct hclge_vport_vtag_tx_cfg_cmd *req; 9770 struct hclge_dev *hdev = vport->back; 9771 struct hclge_desc desc; 9772 u16 bmap_index; 9773 int status; 9774 9775 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 9776 9777 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 9778 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 9779 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 9780 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 9781 vcfg->accept_tag1 ? 1 : 0); 9782 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 9783 vcfg->accept_untag1 ? 1 : 0); 9784 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 9785 vcfg->accept_tag2 ? 1 : 0); 9786 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 9787 vcfg->accept_untag2 ? 1 : 0); 9788 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 9789 vcfg->insert_tag1_en ? 1 : 0); 9790 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 9791 vcfg->insert_tag2_en ? 1 : 0); 9792 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B, 9793 vcfg->tag_shift_mode_en ? 1 : 0); 9794 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 9795 9796 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9797 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9798 HCLGE_VF_NUM_PER_BYTE; 9799 req->vf_bitmap[bmap_index] = 9800 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9801 9802 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9803 if (status) 9804 dev_err(&hdev->pdev->dev, 9805 "Send port txvlan cfg command fail, ret =%d\n", 9806 status); 9807 9808 return status; 9809 } 9810 9811 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 9812 { 9813 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 9814 struct hclge_vport_vtag_rx_cfg_cmd *req; 9815 struct hclge_dev *hdev = vport->back; 9816 struct hclge_desc desc; 9817 u16 bmap_index; 9818 int status; 9819 9820 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 9821 9822 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 9823 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 9824 vcfg->strip_tag1_en ? 1 : 0); 9825 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 9826 vcfg->strip_tag2_en ? 1 : 0); 9827 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 9828 vcfg->vlan1_vlan_prionly ? 1 : 0); 9829 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 9830 vcfg->vlan2_vlan_prionly ? 1 : 0); 9831 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B, 9832 vcfg->strip_tag1_discard_en ? 1 : 0); 9833 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B, 9834 vcfg->strip_tag2_discard_en ? 1 : 0); 9835 9836 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9837 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9838 HCLGE_VF_NUM_PER_BYTE; 9839 req->vf_bitmap[bmap_index] = 9840 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9841 9842 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9843 if (status) 9844 dev_err(&hdev->pdev->dev, 9845 "Send port rxvlan cfg command fail, ret =%d\n", 9846 status); 9847 9848 return status; 9849 } 9850 9851 static int hclge_vlan_offload_cfg(struct hclge_vport *vport, 9852 u16 port_base_vlan_state, 9853 u16 vlan_tag, u8 qos) 9854 { 9855 int ret; 9856 9857 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9858 vport->txvlan_cfg.accept_tag1 = true; 9859 vport->txvlan_cfg.insert_tag1_en = false; 9860 vport->txvlan_cfg.default_tag1 = 0; 9861 } else { 9862 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev); 9863 9864 vport->txvlan_cfg.accept_tag1 = 9865 ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3; 9866 vport->txvlan_cfg.insert_tag1_en = true; 9867 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) | 9868 vlan_tag; 9869 } 9870 9871 vport->txvlan_cfg.accept_untag1 = true; 9872 9873 /* accept_tag2 and accept_untag2 are not supported on 9874 * pdev revision(0x20), new revision support them, 9875 * this two fields can not be configured by user. 9876 */ 9877 vport->txvlan_cfg.accept_tag2 = true; 9878 vport->txvlan_cfg.accept_untag2 = true; 9879 vport->txvlan_cfg.insert_tag2_en = false; 9880 vport->txvlan_cfg.default_tag2 = 0; 9881 vport->txvlan_cfg.tag_shift_mode_en = true; 9882 9883 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9884 vport->rxvlan_cfg.strip_tag1_en = false; 9885 vport->rxvlan_cfg.strip_tag2_en = 9886 vport->rxvlan_cfg.rx_vlan_offload_en; 9887 vport->rxvlan_cfg.strip_tag2_discard_en = false; 9888 } else { 9889 vport->rxvlan_cfg.strip_tag1_en = 9890 vport->rxvlan_cfg.rx_vlan_offload_en; 9891 vport->rxvlan_cfg.strip_tag2_en = true; 9892 vport->rxvlan_cfg.strip_tag2_discard_en = true; 9893 } 9894 9895 vport->rxvlan_cfg.strip_tag1_discard_en = false; 9896 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 9897 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 9898 9899 ret = hclge_set_vlan_tx_offload_cfg(vport); 9900 if (ret) 9901 return ret; 9902 9903 return hclge_set_vlan_rx_offload_cfg(vport); 9904 } 9905 9906 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 9907 { 9908 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 9909 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 9910 struct hclge_desc desc; 9911 int status; 9912 9913 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 9914 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 9915 rx_req->ot_fst_vlan_type = 9916 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 9917 rx_req->ot_sec_vlan_type = 9918 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 9919 rx_req->in_fst_vlan_type = 9920 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 9921 rx_req->in_sec_vlan_type = 9922 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 9923 9924 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9925 if (status) { 9926 dev_err(&hdev->pdev->dev, 9927 "Send rxvlan protocol type command fail, ret =%d\n", 9928 status); 9929 return status; 9930 } 9931 9932 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 9933 9934 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data; 9935 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 9936 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 9937 9938 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9939 if (status) 9940 dev_err(&hdev->pdev->dev, 9941 "Send txvlan protocol type command fail, ret =%d\n", 9942 status); 9943 9944 return status; 9945 } 9946 9947 static int hclge_init_vlan_filter(struct hclge_dev *hdev) 9948 { 9949 struct hclge_vport *vport; 9950 int ret; 9951 int i; 9952 9953 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9954 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9955 HCLGE_FILTER_FE_EGRESS_V1_B, 9956 true, 0); 9957 9958 /* for revision 0x21, vf vlan filter is per function */ 9959 for (i = 0; i < hdev->num_alloc_vport; i++) { 9960 vport = &hdev->vport[i]; 9961 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9962 HCLGE_FILTER_FE_EGRESS, true, 9963 vport->vport_id); 9964 if (ret) 9965 return ret; 9966 vport->cur_vlan_fltr_en = true; 9967 } 9968 9969 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9970 HCLGE_FILTER_FE_INGRESS, true, 0); 9971 } 9972 9973 static int hclge_init_vlan_type(struct hclge_dev *hdev) 9974 { 9975 hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q; 9976 hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q; 9977 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q; 9978 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q; 9979 hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q; 9980 hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q; 9981 9982 return hclge_set_vlan_protocol_type(hdev); 9983 } 9984 9985 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev) 9986 { 9987 struct hclge_port_base_vlan_config *cfg; 9988 struct hclge_vport *vport; 9989 int ret; 9990 int i; 9991 9992 for (i = 0; i < hdev->num_alloc_vport; i++) { 9993 vport = &hdev->vport[i]; 9994 cfg = &vport->port_base_vlan_cfg; 9995 9996 ret = hclge_vlan_offload_cfg(vport, cfg->state, 9997 cfg->vlan_info.vlan_tag, 9998 cfg->vlan_info.qos); 9999 if (ret) 10000 return ret; 10001 } 10002 return 0; 10003 } 10004 10005 static int hclge_init_vlan_config(struct hclge_dev *hdev) 10006 { 10007 struct hnae3_handle *handle = &hdev->vport[0].nic; 10008 int ret; 10009 10010 ret = hclge_init_vlan_filter(hdev); 10011 if (ret) 10012 return ret; 10013 10014 ret = hclge_init_vlan_type(hdev); 10015 if (ret) 10016 return ret; 10017 10018 ret = hclge_init_vport_vlan_offload(hdev); 10019 if (ret) 10020 return ret; 10021 10022 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 10023 } 10024 10025 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10026 bool writen_to_tbl) 10027 { 10028 struct hclge_vport_vlan_cfg *vlan, *tmp; 10029 struct hclge_dev *hdev = vport->back; 10030 10031 mutex_lock(&hdev->vport_lock); 10032 10033 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10034 if (vlan->vlan_id == vlan_id) { 10035 mutex_unlock(&hdev->vport_lock); 10036 return; 10037 } 10038 } 10039 10040 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 10041 if (!vlan) { 10042 mutex_unlock(&hdev->vport_lock); 10043 return; 10044 } 10045 10046 vlan->hd_tbl_status = writen_to_tbl; 10047 vlan->vlan_id = vlan_id; 10048 10049 list_add_tail(&vlan->node, &vport->vlan_list); 10050 mutex_unlock(&hdev->vport_lock); 10051 } 10052 10053 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport) 10054 { 10055 struct hclge_vport_vlan_cfg *vlan, *tmp; 10056 struct hclge_dev *hdev = vport->back; 10057 int ret; 10058 10059 mutex_lock(&hdev->vport_lock); 10060 10061 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10062 if (!vlan->hd_tbl_status) { 10063 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10064 vport->vport_id, 10065 vlan->vlan_id, false); 10066 if (ret) { 10067 dev_err(&hdev->pdev->dev, 10068 "restore vport vlan list failed, ret=%d\n", 10069 ret); 10070 10071 mutex_unlock(&hdev->vport_lock); 10072 return ret; 10073 } 10074 } 10075 vlan->hd_tbl_status = true; 10076 } 10077 10078 mutex_unlock(&hdev->vport_lock); 10079 10080 return 0; 10081 } 10082 10083 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10084 bool is_write_tbl) 10085 { 10086 struct hclge_vport_vlan_cfg *vlan, *tmp; 10087 struct hclge_dev *hdev = vport->back; 10088 10089 mutex_lock(&hdev->vport_lock); 10090 10091 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10092 if (vlan->vlan_id == vlan_id) { 10093 if (is_write_tbl && vlan->hd_tbl_status) 10094 hclge_set_vlan_filter_hw(hdev, 10095 htons(ETH_P_8021Q), 10096 vport->vport_id, 10097 vlan_id, 10098 true); 10099 10100 list_del(&vlan->node); 10101 kfree(vlan); 10102 break; 10103 } 10104 } 10105 10106 mutex_unlock(&hdev->vport_lock); 10107 } 10108 10109 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list) 10110 { 10111 struct hclge_vport_vlan_cfg *vlan, *tmp; 10112 struct hclge_dev *hdev = vport->back; 10113 10114 mutex_lock(&hdev->vport_lock); 10115 10116 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10117 if (vlan->hd_tbl_status) 10118 hclge_set_vlan_filter_hw(hdev, 10119 htons(ETH_P_8021Q), 10120 vport->vport_id, 10121 vlan->vlan_id, 10122 true); 10123 10124 vlan->hd_tbl_status = false; 10125 if (is_del_list) { 10126 list_del(&vlan->node); 10127 kfree(vlan); 10128 } 10129 } 10130 clear_bit(vport->vport_id, hdev->vf_vlan_full); 10131 mutex_unlock(&hdev->vport_lock); 10132 } 10133 10134 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev) 10135 { 10136 struct hclge_vport_vlan_cfg *vlan, *tmp; 10137 struct hclge_vport *vport; 10138 int i; 10139 10140 mutex_lock(&hdev->vport_lock); 10141 10142 for (i = 0; i < hdev->num_alloc_vport; i++) { 10143 vport = &hdev->vport[i]; 10144 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10145 list_del(&vlan->node); 10146 kfree(vlan); 10147 } 10148 } 10149 10150 mutex_unlock(&hdev->vport_lock); 10151 } 10152 10153 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev) 10154 { 10155 struct hclge_vlan_info *vlan_info; 10156 struct hclge_vport *vport; 10157 u16 vlan_proto; 10158 u16 vlan_id; 10159 u16 state; 10160 int vf_id; 10161 int ret; 10162 10163 /* PF should restore all vfs port base vlan */ 10164 for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) { 10165 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM]; 10166 vlan_info = vport->port_base_vlan_cfg.tbl_sta ? 10167 &vport->port_base_vlan_cfg.vlan_info : 10168 &vport->port_base_vlan_cfg.old_vlan_info; 10169 10170 vlan_id = vlan_info->vlan_tag; 10171 vlan_proto = vlan_info->vlan_proto; 10172 state = vport->port_base_vlan_cfg.state; 10173 10174 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) { 10175 clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]); 10176 ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto), 10177 vport->vport_id, 10178 vlan_id, false); 10179 vport->port_base_vlan_cfg.tbl_sta = ret == 0; 10180 } 10181 } 10182 } 10183 10184 void hclge_restore_vport_vlan_table(struct hclge_vport *vport) 10185 { 10186 struct hclge_vport_vlan_cfg *vlan, *tmp; 10187 struct hclge_dev *hdev = vport->back; 10188 int ret; 10189 10190 mutex_lock(&hdev->vport_lock); 10191 10192 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10193 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10194 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10195 vport->vport_id, 10196 vlan->vlan_id, false); 10197 if (ret) 10198 break; 10199 vlan->hd_tbl_status = true; 10200 } 10201 } 10202 10203 mutex_unlock(&hdev->vport_lock); 10204 } 10205 10206 /* For global reset and imp reset, hardware will clear the mac table, 10207 * so we change the mac address state from ACTIVE to TO_ADD, then they 10208 * can be restored in the service task after reset complete. Furtherly, 10209 * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to 10210 * be restored after reset, so just remove these mac nodes from mac_list. 10211 */ 10212 static void hclge_mac_node_convert_for_reset(struct list_head *list) 10213 { 10214 struct hclge_mac_node *mac_node, *tmp; 10215 10216 list_for_each_entry_safe(mac_node, tmp, list, node) { 10217 if (mac_node->state == HCLGE_MAC_ACTIVE) { 10218 mac_node->state = HCLGE_MAC_TO_ADD; 10219 } else if (mac_node->state == HCLGE_MAC_TO_DEL) { 10220 list_del(&mac_node->node); 10221 kfree(mac_node); 10222 } 10223 } 10224 } 10225 10226 void hclge_restore_mac_table_common(struct hclge_vport *vport) 10227 { 10228 spin_lock_bh(&vport->mac_list_lock); 10229 10230 hclge_mac_node_convert_for_reset(&vport->uc_mac_list); 10231 hclge_mac_node_convert_for_reset(&vport->mc_mac_list); 10232 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 10233 10234 spin_unlock_bh(&vport->mac_list_lock); 10235 } 10236 10237 static void hclge_restore_hw_table(struct hclge_dev *hdev) 10238 { 10239 struct hclge_vport *vport = &hdev->vport[0]; 10240 struct hnae3_handle *handle = &vport->nic; 10241 10242 hclge_restore_mac_table_common(vport); 10243 hclge_restore_vport_port_base_vlan_config(hdev); 10244 hclge_restore_vport_vlan_table(vport); 10245 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 10246 hclge_restore_fd_entries(handle); 10247 } 10248 10249 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 10250 { 10251 struct hclge_vport *vport = hclge_get_vport(handle); 10252 10253 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10254 vport->rxvlan_cfg.strip_tag1_en = false; 10255 vport->rxvlan_cfg.strip_tag2_en = enable; 10256 vport->rxvlan_cfg.strip_tag2_discard_en = false; 10257 } else { 10258 vport->rxvlan_cfg.strip_tag1_en = enable; 10259 vport->rxvlan_cfg.strip_tag2_en = true; 10260 vport->rxvlan_cfg.strip_tag2_discard_en = true; 10261 } 10262 10263 vport->rxvlan_cfg.strip_tag1_discard_en = false; 10264 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 10265 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 10266 vport->rxvlan_cfg.rx_vlan_offload_en = enable; 10267 10268 return hclge_set_vlan_rx_offload_cfg(vport); 10269 } 10270 10271 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport) 10272 { 10273 struct hclge_dev *hdev = vport->back; 10274 10275 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 10276 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state); 10277 } 10278 10279 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport, 10280 u16 port_base_vlan_state, 10281 struct hclge_vlan_info *new_info, 10282 struct hclge_vlan_info *old_info) 10283 { 10284 struct hclge_dev *hdev = vport->back; 10285 int ret; 10286 10287 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) { 10288 hclge_rm_vport_all_vlan_table(vport, false); 10289 /* force clear VLAN 0 */ 10290 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0); 10291 if (ret) 10292 return ret; 10293 return hclge_set_vlan_filter_hw(hdev, 10294 htons(new_info->vlan_proto), 10295 vport->vport_id, 10296 new_info->vlan_tag, 10297 false); 10298 } 10299 10300 vport->port_base_vlan_cfg.tbl_sta = false; 10301 10302 /* force add VLAN 0 */ 10303 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0); 10304 if (ret) 10305 return ret; 10306 10307 ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto), 10308 vport->vport_id, old_info->vlan_tag, 10309 true); 10310 if (ret) 10311 return ret; 10312 10313 return hclge_add_vport_all_vlan_table(vport); 10314 } 10315 10316 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg, 10317 const struct hclge_vlan_info *old_cfg) 10318 { 10319 if (new_cfg->vlan_tag != old_cfg->vlan_tag) 10320 return true; 10321 10322 if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0)) 10323 return true; 10324 10325 return false; 10326 } 10327 10328 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport, 10329 struct hclge_vlan_info *new_info, 10330 struct hclge_vlan_info *old_info) 10331 { 10332 struct hclge_dev *hdev = vport->back; 10333 int ret; 10334 10335 /* add new VLAN tag */ 10336 ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto), 10337 vport->vport_id, new_info->vlan_tag, 10338 false); 10339 if (ret) 10340 return ret; 10341 10342 vport->port_base_vlan_cfg.tbl_sta = false; 10343 /* remove old VLAN tag */ 10344 if (old_info->vlan_tag == 0) 10345 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, 10346 true, 0); 10347 else 10348 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10349 vport->vport_id, 10350 old_info->vlan_tag, true); 10351 if (ret) 10352 dev_err(&hdev->pdev->dev, 10353 "failed to clear vport%u port base vlan %u, ret = %d.\n", 10354 vport->vport_id, old_info->vlan_tag, ret); 10355 10356 return ret; 10357 } 10358 10359 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 10360 struct hclge_vlan_info *vlan_info) 10361 { 10362 struct hnae3_handle *nic = &vport->nic; 10363 struct hclge_vlan_info *old_vlan_info; 10364 int ret; 10365 10366 old_vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10367 10368 ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag, 10369 vlan_info->qos); 10370 if (ret) 10371 return ret; 10372 10373 if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info)) 10374 goto out; 10375 10376 if (state == HNAE3_PORT_BASE_VLAN_MODIFY) 10377 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info, 10378 old_vlan_info); 10379 else 10380 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info, 10381 old_vlan_info); 10382 if (ret) 10383 return ret; 10384 10385 out: 10386 vport->port_base_vlan_cfg.state = state; 10387 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 10388 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 10389 else 10390 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 10391 10392 vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info; 10393 vport->port_base_vlan_cfg.vlan_info = *vlan_info; 10394 vport->port_base_vlan_cfg.tbl_sta = true; 10395 hclge_set_vport_vlan_fltr_change(vport); 10396 10397 return 0; 10398 } 10399 10400 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport, 10401 enum hnae3_port_base_vlan_state state, 10402 u16 vlan, u8 qos) 10403 { 10404 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10405 if (!vlan && !qos) 10406 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10407 10408 return HNAE3_PORT_BASE_VLAN_ENABLE; 10409 } 10410 10411 if (!vlan && !qos) 10412 return HNAE3_PORT_BASE_VLAN_DISABLE; 10413 10414 if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan && 10415 vport->port_base_vlan_cfg.vlan_info.qos == qos) 10416 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10417 10418 return HNAE3_PORT_BASE_VLAN_MODIFY; 10419 } 10420 10421 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 10422 u16 vlan, u8 qos, __be16 proto) 10423 { 10424 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 10425 struct hclge_vport *vport = hclge_get_vport(handle); 10426 struct hclge_dev *hdev = vport->back; 10427 struct hclge_vlan_info vlan_info; 10428 u16 state; 10429 int ret; 10430 10431 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 10432 return -EOPNOTSUPP; 10433 10434 vport = hclge_get_vf_vport(hdev, vfid); 10435 if (!vport) 10436 return -EINVAL; 10437 10438 /* qos is a 3 bits value, so can not be bigger than 7 */ 10439 if (vlan > VLAN_N_VID - 1 || qos > 7) 10440 return -EINVAL; 10441 if (proto != htons(ETH_P_8021Q)) 10442 return -EPROTONOSUPPORT; 10443 10444 state = hclge_get_port_base_vlan_state(vport, 10445 vport->port_base_vlan_cfg.state, 10446 vlan, qos); 10447 if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE) 10448 return 0; 10449 10450 vlan_info.vlan_tag = vlan; 10451 vlan_info.qos = qos; 10452 vlan_info.vlan_proto = ntohs(proto); 10453 10454 ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info); 10455 if (ret) { 10456 dev_err(&hdev->pdev->dev, 10457 "failed to update port base vlan for vf %d, ret = %d\n", 10458 vfid, ret); 10459 return ret; 10460 } 10461 10462 /* there is a timewindow for PF to know VF unalive, it may 10463 * cause send mailbox fail, but it doesn't matter, VF will 10464 * query it when reinit. 10465 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based 10466 * VLAN state. 10467 */ 10468 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3 && 10469 test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 10470 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0], 10471 vport->vport_id, 10472 state, &vlan_info); 10473 10474 return 0; 10475 } 10476 10477 static void hclge_clear_vf_vlan(struct hclge_dev *hdev) 10478 { 10479 struct hclge_vlan_info *vlan_info; 10480 struct hclge_vport *vport; 10481 int ret; 10482 int vf; 10483 10484 /* clear port base vlan for all vf */ 10485 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 10486 vport = &hdev->vport[vf]; 10487 vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10488 10489 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10490 vport->vport_id, 10491 vlan_info->vlan_tag, true); 10492 if (ret) 10493 dev_err(&hdev->pdev->dev, 10494 "failed to clear vf vlan for vf%d, ret = %d\n", 10495 vf - HCLGE_VF_VPORT_START_NUM, ret); 10496 } 10497 } 10498 10499 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 10500 u16 vlan_id, bool is_kill) 10501 { 10502 struct hclge_vport *vport = hclge_get_vport(handle); 10503 struct hclge_dev *hdev = vport->back; 10504 bool writen_to_tbl = false; 10505 int ret = 0; 10506 10507 /* When device is resetting or reset failed, firmware is unable to 10508 * handle mailbox. Just record the vlan id, and remove it after 10509 * reset finished. 10510 */ 10511 if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 10512 test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) { 10513 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10514 return -EBUSY; 10515 } 10516 10517 /* when port base vlan enabled, we use port base vlan as the vlan 10518 * filter entry. In this case, we don't update vlan filter table 10519 * when user add new vlan or remove exist vlan, just update the vport 10520 * vlan list. The vlan id in vlan list will be writen in vlan filter 10521 * table until port base vlan disabled 10522 */ 10523 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10524 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, 10525 vlan_id, is_kill); 10526 writen_to_tbl = true; 10527 } 10528 10529 if (!ret) { 10530 if (!is_kill) 10531 hclge_add_vport_vlan_table(vport, vlan_id, 10532 writen_to_tbl); 10533 else if (is_kill && vlan_id != 0) 10534 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10535 } else if (is_kill) { 10536 /* when remove hw vlan filter failed, record the vlan id, 10537 * and try to remove it from hw later, to be consistence 10538 * with stack 10539 */ 10540 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10541 } 10542 10543 hclge_set_vport_vlan_fltr_change(vport); 10544 10545 return ret; 10546 } 10547 10548 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev) 10549 { 10550 struct hclge_vport *vport; 10551 int ret; 10552 u16 i; 10553 10554 for (i = 0; i < hdev->num_alloc_vport; i++) { 10555 vport = &hdev->vport[i]; 10556 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10557 &vport->state)) 10558 continue; 10559 10560 ret = hclge_enable_vport_vlan_filter(vport, 10561 vport->req_vlan_fltr_en); 10562 if (ret) { 10563 dev_err(&hdev->pdev->dev, 10564 "failed to sync vlan filter state for vport%u, ret = %d\n", 10565 vport->vport_id, ret); 10566 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10567 &vport->state); 10568 return; 10569 } 10570 } 10571 } 10572 10573 static void hclge_sync_vlan_filter(struct hclge_dev *hdev) 10574 { 10575 #define HCLGE_MAX_SYNC_COUNT 60 10576 10577 int i, ret, sync_cnt = 0; 10578 u16 vlan_id; 10579 10580 /* start from vport 1 for PF is always alive */ 10581 for (i = 0; i < hdev->num_alloc_vport; i++) { 10582 struct hclge_vport *vport = &hdev->vport[i]; 10583 10584 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10585 VLAN_N_VID); 10586 while (vlan_id != VLAN_N_VID) { 10587 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10588 vport->vport_id, vlan_id, 10589 true); 10590 if (ret && ret != -EINVAL) 10591 return; 10592 10593 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10594 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10595 hclge_set_vport_vlan_fltr_change(vport); 10596 10597 sync_cnt++; 10598 if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) 10599 return; 10600 10601 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10602 VLAN_N_VID); 10603 } 10604 } 10605 10606 hclge_sync_vlan_fltr_state(hdev); 10607 } 10608 10609 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps) 10610 { 10611 struct hclge_config_max_frm_size_cmd *req; 10612 struct hclge_desc desc; 10613 10614 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 10615 10616 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 10617 req->max_frm_size = cpu_to_le16(new_mps); 10618 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 10619 10620 return hclge_cmd_send(&hdev->hw, &desc, 1); 10621 } 10622 10623 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 10624 { 10625 struct hclge_vport *vport = hclge_get_vport(handle); 10626 10627 return hclge_set_vport_mtu(vport, new_mtu); 10628 } 10629 10630 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) 10631 { 10632 struct hclge_dev *hdev = vport->back; 10633 int i, max_frm_size, ret; 10634 10635 /* HW supprt 2 layer vlan */ 10636 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 10637 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 10638 max_frm_size > hdev->ae_dev->dev_specs.max_frm_size) 10639 return -EINVAL; 10640 10641 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 10642 mutex_lock(&hdev->vport_lock); 10643 /* VF's mps must fit within hdev->mps */ 10644 if (vport->vport_id && max_frm_size > hdev->mps) { 10645 mutex_unlock(&hdev->vport_lock); 10646 return -EINVAL; 10647 } else if (vport->vport_id) { 10648 vport->mps = max_frm_size; 10649 mutex_unlock(&hdev->vport_lock); 10650 return 0; 10651 } 10652 10653 /* PF's mps must be greater then VF's mps */ 10654 for (i = 1; i < hdev->num_alloc_vport; i++) 10655 if (max_frm_size < hdev->vport[i].mps) { 10656 dev_err(&hdev->pdev->dev, 10657 "failed to set pf mtu for less than vport %d, mps = %u.\n", 10658 i, hdev->vport[i].mps); 10659 mutex_unlock(&hdev->vport_lock); 10660 return -EINVAL; 10661 } 10662 10663 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 10664 10665 ret = hclge_set_mac_mtu(hdev, max_frm_size); 10666 if (ret) { 10667 dev_err(&hdev->pdev->dev, 10668 "Change mtu fail, ret =%d\n", ret); 10669 goto out; 10670 } 10671 10672 hdev->mps = max_frm_size; 10673 vport->mps = max_frm_size; 10674 10675 ret = hclge_buffer_alloc(hdev); 10676 if (ret) 10677 dev_err(&hdev->pdev->dev, 10678 "Allocate buffer fail, ret =%d\n", ret); 10679 10680 out: 10681 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 10682 mutex_unlock(&hdev->vport_lock); 10683 return ret; 10684 } 10685 10686 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id, 10687 bool enable) 10688 { 10689 struct hclge_reset_tqp_queue_cmd *req; 10690 struct hclge_desc desc; 10691 int ret; 10692 10693 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 10694 10695 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10696 req->tqp_id = cpu_to_le16(queue_id); 10697 if (enable) 10698 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U); 10699 10700 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10701 if (ret) { 10702 dev_err(&hdev->pdev->dev, 10703 "Send tqp reset cmd error, status =%d\n", ret); 10704 return ret; 10705 } 10706 10707 return 0; 10708 } 10709 10710 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id, 10711 u8 *reset_status) 10712 { 10713 struct hclge_reset_tqp_queue_cmd *req; 10714 struct hclge_desc desc; 10715 int ret; 10716 10717 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 10718 10719 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10720 req->tqp_id = cpu_to_le16(queue_id); 10721 10722 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10723 if (ret) { 10724 dev_err(&hdev->pdev->dev, 10725 "Get reset status error, status =%d\n", ret); 10726 return ret; 10727 } 10728 10729 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 10730 10731 return 0; 10732 } 10733 10734 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id) 10735 { 10736 struct hclge_comm_tqp *tqp; 10737 struct hnae3_queue *queue; 10738 10739 queue = handle->kinfo.tqp[queue_id]; 10740 tqp = container_of(queue, struct hclge_comm_tqp, q); 10741 10742 return tqp->index; 10743 } 10744 10745 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle) 10746 { 10747 struct hclge_vport *vport = hclge_get_vport(handle); 10748 struct hclge_dev *hdev = vport->back; 10749 u16 reset_try_times = 0; 10750 u8 reset_status; 10751 u16 queue_gid; 10752 int ret; 10753 u16 i; 10754 10755 for (i = 0; i < handle->kinfo.num_tqps; i++) { 10756 queue_gid = hclge_covert_handle_qid_global(handle, i); 10757 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true); 10758 if (ret) { 10759 dev_err(&hdev->pdev->dev, 10760 "failed to send reset tqp cmd, ret = %d\n", 10761 ret); 10762 return ret; 10763 } 10764 10765 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 10766 ret = hclge_get_reset_status(hdev, queue_gid, 10767 &reset_status); 10768 if (ret) 10769 return ret; 10770 10771 if (reset_status) 10772 break; 10773 10774 /* Wait for tqp hw reset */ 10775 usleep_range(1000, 1200); 10776 } 10777 10778 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 10779 dev_err(&hdev->pdev->dev, 10780 "wait for tqp hw reset timeout\n"); 10781 return -ETIME; 10782 } 10783 10784 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false); 10785 if (ret) { 10786 dev_err(&hdev->pdev->dev, 10787 "failed to deassert soft reset, ret = %d\n", 10788 ret); 10789 return ret; 10790 } 10791 reset_try_times = 0; 10792 } 10793 return 0; 10794 } 10795 10796 static int hclge_reset_rcb(struct hnae3_handle *handle) 10797 { 10798 #define HCLGE_RESET_RCB_NOT_SUPPORT 0U 10799 #define HCLGE_RESET_RCB_SUCCESS 1U 10800 10801 struct hclge_vport *vport = hclge_get_vport(handle); 10802 struct hclge_dev *hdev = vport->back; 10803 struct hclge_reset_cmd *req; 10804 struct hclge_desc desc; 10805 u8 return_status; 10806 u16 queue_gid; 10807 int ret; 10808 10809 queue_gid = hclge_covert_handle_qid_global(handle, 0); 10810 10811 req = (struct hclge_reset_cmd *)desc.data; 10812 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 10813 hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1); 10814 req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid); 10815 req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps); 10816 10817 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10818 if (ret) { 10819 dev_err(&hdev->pdev->dev, 10820 "failed to send rcb reset cmd, ret = %d\n", ret); 10821 return ret; 10822 } 10823 10824 return_status = req->fun_reset_rcb_return_status; 10825 if (return_status == HCLGE_RESET_RCB_SUCCESS) 10826 return 0; 10827 10828 if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) { 10829 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n", 10830 return_status); 10831 return -EIO; 10832 } 10833 10834 /* if reset rcb cmd is unsupported, we need to send reset tqp cmd 10835 * again to reset all tqps 10836 */ 10837 return hclge_reset_tqp_cmd(handle); 10838 } 10839 10840 int hclge_reset_tqp(struct hnae3_handle *handle) 10841 { 10842 struct hclge_vport *vport = hclge_get_vport(handle); 10843 struct hclge_dev *hdev = vport->back; 10844 int ret; 10845 10846 /* only need to disable PF's tqp */ 10847 if (!vport->vport_id) { 10848 ret = hclge_tqp_enable(handle, false); 10849 if (ret) { 10850 dev_err(&hdev->pdev->dev, 10851 "failed to disable tqp, ret = %d\n", ret); 10852 return ret; 10853 } 10854 } 10855 10856 return hclge_reset_rcb(handle); 10857 } 10858 10859 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 10860 { 10861 struct hclge_vport *vport = hclge_get_vport(handle); 10862 struct hclge_dev *hdev = vport->back; 10863 10864 return hdev->fw_version; 10865 } 10866 10867 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10868 { 10869 struct phy_device *phydev = hdev->hw.mac.phydev; 10870 10871 if (!phydev) 10872 return; 10873 10874 phy_set_asym_pause(phydev, rx_en, tx_en); 10875 } 10876 10877 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10878 { 10879 int ret; 10880 10881 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 10882 return 0; 10883 10884 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 10885 if (ret) 10886 dev_err(&hdev->pdev->dev, 10887 "configure pauseparam error, ret = %d.\n", ret); 10888 10889 return ret; 10890 } 10891 10892 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 10893 { 10894 struct phy_device *phydev = hdev->hw.mac.phydev; 10895 u16 remote_advertising = 0; 10896 u16 local_advertising; 10897 u32 rx_pause, tx_pause; 10898 u8 flowctl; 10899 10900 if (!phydev->link || !phydev->autoneg) 10901 return 0; 10902 10903 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising); 10904 10905 if (phydev->pause) 10906 remote_advertising = LPA_PAUSE_CAP; 10907 10908 if (phydev->asym_pause) 10909 remote_advertising |= LPA_PAUSE_ASYM; 10910 10911 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 10912 remote_advertising); 10913 tx_pause = flowctl & FLOW_CTRL_TX; 10914 rx_pause = flowctl & FLOW_CTRL_RX; 10915 10916 if (phydev->duplex == HCLGE_MAC_HALF) { 10917 tx_pause = 0; 10918 rx_pause = 0; 10919 } 10920 10921 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 10922 } 10923 10924 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 10925 u32 *rx_en, u32 *tx_en) 10926 { 10927 struct hclge_vport *vport = hclge_get_vport(handle); 10928 struct hclge_dev *hdev = vport->back; 10929 u8 media_type = hdev->hw.mac.media_type; 10930 10931 *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ? 10932 hclge_get_autoneg(handle) : 0; 10933 10934 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 10935 *rx_en = 0; 10936 *tx_en = 0; 10937 return; 10938 } 10939 10940 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 10941 *rx_en = 1; 10942 *tx_en = 0; 10943 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 10944 *tx_en = 1; 10945 *rx_en = 0; 10946 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 10947 *rx_en = 1; 10948 *tx_en = 1; 10949 } else { 10950 *rx_en = 0; 10951 *tx_en = 0; 10952 } 10953 } 10954 10955 static void hclge_record_user_pauseparam(struct hclge_dev *hdev, 10956 u32 rx_en, u32 tx_en) 10957 { 10958 if (rx_en && tx_en) 10959 hdev->fc_mode_last_time = HCLGE_FC_FULL; 10960 else if (rx_en && !tx_en) 10961 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 10962 else if (!rx_en && tx_en) 10963 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 10964 else 10965 hdev->fc_mode_last_time = HCLGE_FC_NONE; 10966 10967 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 10968 } 10969 10970 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 10971 u32 rx_en, u32 tx_en) 10972 { 10973 struct hclge_vport *vport = hclge_get_vport(handle); 10974 struct hclge_dev *hdev = vport->back; 10975 struct phy_device *phydev = hdev->hw.mac.phydev; 10976 u32 fc_autoneg; 10977 10978 if (phydev || hnae3_dev_phy_imp_supported(hdev)) { 10979 fc_autoneg = hclge_get_autoneg(handle); 10980 if (auto_neg != fc_autoneg) { 10981 dev_info(&hdev->pdev->dev, 10982 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 10983 return -EOPNOTSUPP; 10984 } 10985 } 10986 10987 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 10988 dev_info(&hdev->pdev->dev, 10989 "Priority flow control enabled. Cannot set link flow control.\n"); 10990 return -EOPNOTSUPP; 10991 } 10992 10993 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 10994 10995 hclge_record_user_pauseparam(hdev, rx_en, tx_en); 10996 10997 if (!auto_neg || hnae3_dev_phy_imp_supported(hdev)) 10998 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 10999 11000 if (phydev) 11001 return phy_start_aneg(phydev); 11002 11003 return -EOPNOTSUPP; 11004 } 11005 11006 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 11007 u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num) 11008 { 11009 struct hclge_vport *vport = hclge_get_vport(handle); 11010 struct hclge_dev *hdev = vport->back; 11011 11012 if (speed) 11013 *speed = hdev->hw.mac.speed; 11014 if (duplex) 11015 *duplex = hdev->hw.mac.duplex; 11016 if (auto_neg) 11017 *auto_neg = hdev->hw.mac.autoneg; 11018 if (lane_num) 11019 *lane_num = hdev->hw.mac.lane_num; 11020 } 11021 11022 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type, 11023 u8 *module_type) 11024 { 11025 struct hclge_vport *vport = hclge_get_vport(handle); 11026 struct hclge_dev *hdev = vport->back; 11027 11028 /* When nic is down, the service task is not running, doesn't update 11029 * the port information per second. Query the port information before 11030 * return the media type, ensure getting the correct media information. 11031 */ 11032 hclge_update_port_info(hdev); 11033 11034 if (media_type) 11035 *media_type = hdev->hw.mac.media_type; 11036 11037 if (module_type) 11038 *module_type = hdev->hw.mac.module_type; 11039 } 11040 11041 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 11042 u8 *tp_mdix_ctrl, u8 *tp_mdix) 11043 { 11044 struct hclge_vport *vport = hclge_get_vport(handle); 11045 struct hclge_dev *hdev = vport->back; 11046 struct phy_device *phydev = hdev->hw.mac.phydev; 11047 int mdix_ctrl, mdix, is_resolved; 11048 unsigned int retval; 11049 11050 if (!phydev) { 11051 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11052 *tp_mdix = ETH_TP_MDI_INVALID; 11053 return; 11054 } 11055 11056 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 11057 11058 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 11059 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 11060 HCLGE_PHY_MDIX_CTRL_S); 11061 11062 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 11063 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 11064 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 11065 11066 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 11067 11068 switch (mdix_ctrl) { 11069 case 0x0: 11070 *tp_mdix_ctrl = ETH_TP_MDI; 11071 break; 11072 case 0x1: 11073 *tp_mdix_ctrl = ETH_TP_MDI_X; 11074 break; 11075 case 0x3: 11076 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 11077 break; 11078 default: 11079 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11080 break; 11081 } 11082 11083 if (!is_resolved) 11084 *tp_mdix = ETH_TP_MDI_INVALID; 11085 else if (mdix) 11086 *tp_mdix = ETH_TP_MDI_X; 11087 else 11088 *tp_mdix = ETH_TP_MDI; 11089 } 11090 11091 static void hclge_info_show(struct hclge_dev *hdev) 11092 { 11093 struct device *dev = &hdev->pdev->dev; 11094 11095 dev_info(dev, "PF info begin:\n"); 11096 11097 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 11098 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 11099 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 11100 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 11101 dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs); 11102 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 11103 dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size); 11104 dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size); 11105 dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size); 11106 dev_info(dev, "This is %s PF\n", 11107 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main"); 11108 dev_info(dev, "DCB %s\n", 11109 hdev->flag & HCLGE_FLAG_DCB_ENABLE ? "enable" : "disable"); 11110 dev_info(dev, "MQPRIO %s\n", 11111 hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE ? "enable" : "disable"); 11112 dev_info(dev, "Default tx spare buffer size: %u\n", 11113 hdev->tx_spare_buf_size); 11114 11115 dev_info(dev, "PF info end.\n"); 11116 } 11117 11118 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 11119 struct hclge_vport *vport) 11120 { 11121 struct hnae3_client *client = vport->nic.client; 11122 struct hclge_dev *hdev = ae_dev->priv; 11123 int rst_cnt = hdev->rst_stats.reset_cnt; 11124 int ret; 11125 11126 ret = client->ops->init_instance(&vport->nic); 11127 if (ret) 11128 return ret; 11129 11130 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11131 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11132 rst_cnt != hdev->rst_stats.reset_cnt) { 11133 ret = -EBUSY; 11134 goto init_nic_err; 11135 } 11136 11137 /* Enable nic hw error interrupts */ 11138 ret = hclge_config_nic_hw_error(hdev, true); 11139 if (ret) { 11140 dev_err(&ae_dev->pdev->dev, 11141 "fail(%d) to enable hw error interrupts\n", ret); 11142 goto init_nic_err; 11143 } 11144 11145 hnae3_set_client_init_flag(client, ae_dev, 1); 11146 11147 if (netif_msg_drv(&hdev->vport->nic)) 11148 hclge_info_show(hdev); 11149 11150 return ret; 11151 11152 init_nic_err: 11153 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11154 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11155 msleep(HCLGE_WAIT_RESET_DONE); 11156 11157 client->ops->uninit_instance(&vport->nic, 0); 11158 11159 return ret; 11160 } 11161 11162 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 11163 struct hclge_vport *vport) 11164 { 11165 struct hclge_dev *hdev = ae_dev->priv; 11166 struct hnae3_client *client; 11167 int rst_cnt; 11168 int ret; 11169 11170 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 11171 !hdev->nic_client) 11172 return 0; 11173 11174 client = hdev->roce_client; 11175 ret = hclge_init_roce_base_info(vport); 11176 if (ret) 11177 return ret; 11178 11179 rst_cnt = hdev->rst_stats.reset_cnt; 11180 ret = client->ops->init_instance(&vport->roce); 11181 if (ret) 11182 return ret; 11183 11184 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11185 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11186 rst_cnt != hdev->rst_stats.reset_cnt) { 11187 ret = -EBUSY; 11188 goto init_roce_err; 11189 } 11190 11191 /* Enable roce ras interrupts */ 11192 ret = hclge_config_rocee_ras_interrupt(hdev, true); 11193 if (ret) { 11194 dev_err(&ae_dev->pdev->dev, 11195 "fail(%d) to enable roce ras interrupts\n", ret); 11196 goto init_roce_err; 11197 } 11198 11199 hnae3_set_client_init_flag(client, ae_dev, 1); 11200 11201 return 0; 11202 11203 init_roce_err: 11204 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11205 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11206 msleep(HCLGE_WAIT_RESET_DONE); 11207 11208 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11209 11210 return ret; 11211 } 11212 11213 static int hclge_init_client_instance(struct hnae3_client *client, 11214 struct hnae3_ae_dev *ae_dev) 11215 { 11216 struct hclge_dev *hdev = ae_dev->priv; 11217 struct hclge_vport *vport = &hdev->vport[0]; 11218 int ret; 11219 11220 switch (client->type) { 11221 case HNAE3_CLIENT_KNIC: 11222 hdev->nic_client = client; 11223 vport->nic.client = client; 11224 ret = hclge_init_nic_client_instance(ae_dev, vport); 11225 if (ret) 11226 goto clear_nic; 11227 11228 ret = hclge_init_roce_client_instance(ae_dev, vport); 11229 if (ret) 11230 goto clear_roce; 11231 11232 break; 11233 case HNAE3_CLIENT_ROCE: 11234 if (hnae3_dev_roce_supported(hdev)) { 11235 hdev->roce_client = client; 11236 vport->roce.client = client; 11237 } 11238 11239 ret = hclge_init_roce_client_instance(ae_dev, vport); 11240 if (ret) 11241 goto clear_roce; 11242 11243 break; 11244 default: 11245 return -EINVAL; 11246 } 11247 11248 return 0; 11249 11250 clear_nic: 11251 hdev->nic_client = NULL; 11252 vport->nic.client = NULL; 11253 return ret; 11254 clear_roce: 11255 hdev->roce_client = NULL; 11256 vport->roce.client = NULL; 11257 return ret; 11258 } 11259 11260 static void hclge_uninit_client_instance(struct hnae3_client *client, 11261 struct hnae3_ae_dev *ae_dev) 11262 { 11263 struct hclge_dev *hdev = ae_dev->priv; 11264 struct hclge_vport *vport = &hdev->vport[0]; 11265 11266 if (hdev->roce_client) { 11267 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11268 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11269 msleep(HCLGE_WAIT_RESET_DONE); 11270 11271 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11272 hdev->roce_client = NULL; 11273 vport->roce.client = NULL; 11274 } 11275 if (client->type == HNAE3_CLIENT_ROCE) 11276 return; 11277 if (hdev->nic_client && client->ops->uninit_instance) { 11278 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11279 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11280 msleep(HCLGE_WAIT_RESET_DONE); 11281 11282 client->ops->uninit_instance(&vport->nic, 0); 11283 hdev->nic_client = NULL; 11284 vport->nic.client = NULL; 11285 } 11286 } 11287 11288 static int hclge_dev_mem_map(struct hclge_dev *hdev) 11289 { 11290 struct pci_dev *pdev = hdev->pdev; 11291 struct hclge_hw *hw = &hdev->hw; 11292 11293 /* for device does not have device memory, return directly */ 11294 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR))) 11295 return 0; 11296 11297 hw->hw.mem_base = 11298 devm_ioremap_wc(&pdev->dev, 11299 pci_resource_start(pdev, HCLGE_MEM_BAR), 11300 pci_resource_len(pdev, HCLGE_MEM_BAR)); 11301 if (!hw->hw.mem_base) { 11302 dev_err(&pdev->dev, "failed to map device memory\n"); 11303 return -EFAULT; 11304 } 11305 11306 return 0; 11307 } 11308 11309 static int hclge_pci_init(struct hclge_dev *hdev) 11310 { 11311 struct pci_dev *pdev = hdev->pdev; 11312 struct hclge_hw *hw; 11313 int ret; 11314 11315 ret = pci_enable_device(pdev); 11316 if (ret) { 11317 dev_err(&pdev->dev, "failed to enable PCI device\n"); 11318 return ret; 11319 } 11320 11321 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 11322 if (ret) { 11323 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 11324 if (ret) { 11325 dev_err(&pdev->dev, 11326 "can't set consistent PCI DMA"); 11327 goto err_disable_device; 11328 } 11329 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 11330 } 11331 11332 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 11333 if (ret) { 11334 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 11335 goto err_disable_device; 11336 } 11337 11338 pci_set_master(pdev); 11339 hw = &hdev->hw; 11340 hw->hw.io_base = pcim_iomap(pdev, 2, 0); 11341 if (!hw->hw.io_base) { 11342 dev_err(&pdev->dev, "Can't map configuration register space\n"); 11343 ret = -ENOMEM; 11344 goto err_clr_master; 11345 } 11346 11347 ret = hclge_dev_mem_map(hdev); 11348 if (ret) 11349 goto err_unmap_io_base; 11350 11351 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 11352 11353 return 0; 11354 11355 err_unmap_io_base: 11356 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11357 err_clr_master: 11358 pci_clear_master(pdev); 11359 pci_release_regions(pdev); 11360 err_disable_device: 11361 pci_disable_device(pdev); 11362 11363 return ret; 11364 } 11365 11366 static void hclge_pci_uninit(struct hclge_dev *hdev) 11367 { 11368 struct pci_dev *pdev = hdev->pdev; 11369 11370 if (hdev->hw.hw.mem_base) 11371 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 11372 11373 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11374 pci_free_irq_vectors(pdev); 11375 pci_clear_master(pdev); 11376 pci_release_mem_regions(pdev); 11377 pci_disable_device(pdev); 11378 } 11379 11380 static void hclge_state_init(struct hclge_dev *hdev) 11381 { 11382 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 11383 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11384 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 11385 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11386 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 11387 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 11388 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 11389 } 11390 11391 static void hclge_state_uninit(struct hclge_dev *hdev) 11392 { 11393 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11394 set_bit(HCLGE_STATE_REMOVING, &hdev->state); 11395 11396 if (hdev->reset_timer.function) 11397 del_timer_sync(&hdev->reset_timer); 11398 if (hdev->service_task.work.func) 11399 cancel_delayed_work_sync(&hdev->service_task); 11400 } 11401 11402 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 11403 enum hnae3_reset_type rst_type) 11404 { 11405 #define HCLGE_RESET_RETRY_WAIT_MS 500 11406 #define HCLGE_RESET_RETRY_CNT 5 11407 11408 struct hclge_dev *hdev = ae_dev->priv; 11409 int retry_cnt = 0; 11410 int ret; 11411 11412 while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) { 11413 down(&hdev->reset_sem); 11414 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11415 hdev->reset_type = rst_type; 11416 ret = hclge_reset_prepare(hdev); 11417 if (!ret && !hdev->reset_pending) 11418 break; 11419 11420 dev_err(&hdev->pdev->dev, 11421 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 11422 ret, hdev->reset_pending, retry_cnt); 11423 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11424 up(&hdev->reset_sem); 11425 msleep(HCLGE_RESET_RETRY_WAIT_MS); 11426 } 11427 11428 /* disable misc vector before reset done */ 11429 hclge_enable_vector(&hdev->misc_vector, false); 11430 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 11431 11432 if (hdev->reset_type == HNAE3_FLR_RESET) 11433 hdev->rst_stats.flr_rst_cnt++; 11434 } 11435 11436 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev) 11437 { 11438 struct hclge_dev *hdev = ae_dev->priv; 11439 int ret; 11440 11441 hclge_enable_vector(&hdev->misc_vector, true); 11442 11443 ret = hclge_reset_rebuild(hdev); 11444 if (ret) 11445 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret); 11446 11447 hdev->reset_type = HNAE3_NONE_RESET; 11448 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11449 up(&hdev->reset_sem); 11450 } 11451 11452 static void hclge_clear_resetting_state(struct hclge_dev *hdev) 11453 { 11454 u16 i; 11455 11456 for (i = 0; i < hdev->num_alloc_vport; i++) { 11457 struct hclge_vport *vport = &hdev->vport[i]; 11458 int ret; 11459 11460 /* Send cmd to clear vport's FUNC_RST_ING */ 11461 ret = hclge_set_vf_rst(hdev, vport->vport_id, false); 11462 if (ret) 11463 dev_warn(&hdev->pdev->dev, 11464 "clear vport(%u) rst failed %d!\n", 11465 vport->vport_id, ret); 11466 } 11467 } 11468 11469 static int hclge_clear_hw_resource(struct hclge_dev *hdev) 11470 { 11471 struct hclge_desc desc; 11472 int ret; 11473 11474 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false); 11475 11476 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11477 /* This new command is only supported by new firmware, it will 11478 * fail with older firmware. Error value -EOPNOSUPP can only be 11479 * returned by older firmware running this command, to keep code 11480 * backward compatible we will override this value and return 11481 * success. 11482 */ 11483 if (ret && ret != -EOPNOTSUPP) { 11484 dev_err(&hdev->pdev->dev, 11485 "failed to clear hw resource, ret = %d\n", ret); 11486 return ret; 11487 } 11488 return 0; 11489 } 11490 11491 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev) 11492 { 11493 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11494 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1); 11495 } 11496 11497 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev) 11498 { 11499 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11500 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0); 11501 } 11502 11503 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 11504 { 11505 struct pci_dev *pdev = ae_dev->pdev; 11506 struct hclge_dev *hdev; 11507 int ret; 11508 11509 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 11510 if (!hdev) 11511 return -ENOMEM; 11512 11513 hdev->pdev = pdev; 11514 hdev->ae_dev = ae_dev; 11515 hdev->reset_type = HNAE3_NONE_RESET; 11516 hdev->reset_level = HNAE3_FUNC_RESET; 11517 ae_dev->priv = hdev; 11518 11519 /* HW supprt 2 layer vlan */ 11520 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 11521 11522 mutex_init(&hdev->vport_lock); 11523 spin_lock_init(&hdev->fd_rule_lock); 11524 sema_init(&hdev->reset_sem, 1); 11525 11526 ret = hclge_pci_init(hdev); 11527 if (ret) 11528 goto out; 11529 11530 ret = hclge_devlink_init(hdev); 11531 if (ret) 11532 goto err_pci_uninit; 11533 11534 /* Firmware command queue initialize */ 11535 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 11536 if (ret) 11537 goto err_devlink_uninit; 11538 11539 /* Firmware command initialize */ 11540 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 11541 true, hdev->reset_pending); 11542 if (ret) 11543 goto err_cmd_uninit; 11544 11545 ret = hclge_clear_hw_resource(hdev); 11546 if (ret) 11547 goto err_cmd_uninit; 11548 11549 ret = hclge_get_cap(hdev); 11550 if (ret) 11551 goto err_cmd_uninit; 11552 11553 ret = hclge_query_dev_specs(hdev); 11554 if (ret) { 11555 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n", 11556 ret); 11557 goto err_cmd_uninit; 11558 } 11559 11560 ret = hclge_configure(hdev); 11561 if (ret) { 11562 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 11563 goto err_cmd_uninit; 11564 } 11565 11566 ret = hclge_init_msi(hdev); 11567 if (ret) { 11568 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 11569 goto err_cmd_uninit; 11570 } 11571 11572 ret = hclge_misc_irq_init(hdev); 11573 if (ret) 11574 goto err_msi_uninit; 11575 11576 ret = hclge_alloc_tqps(hdev); 11577 if (ret) { 11578 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 11579 goto err_msi_irq_uninit; 11580 } 11581 11582 ret = hclge_alloc_vport(hdev); 11583 if (ret) 11584 goto err_msi_irq_uninit; 11585 11586 ret = hclge_map_tqp(hdev); 11587 if (ret) 11588 goto err_msi_irq_uninit; 11589 11590 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { 11591 if (hnae3_dev_phy_imp_supported(hdev)) 11592 ret = hclge_update_tp_port_info(hdev); 11593 else 11594 ret = hclge_mac_mdio_config(hdev); 11595 11596 if (ret) 11597 goto err_msi_irq_uninit; 11598 } 11599 11600 ret = hclge_init_umv_space(hdev); 11601 if (ret) 11602 goto err_mdiobus_unreg; 11603 11604 ret = hclge_mac_init(hdev); 11605 if (ret) { 11606 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 11607 goto err_mdiobus_unreg; 11608 } 11609 11610 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 11611 if (ret) { 11612 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 11613 goto err_mdiobus_unreg; 11614 } 11615 11616 ret = hclge_config_gro(hdev); 11617 if (ret) 11618 goto err_mdiobus_unreg; 11619 11620 ret = hclge_init_vlan_config(hdev); 11621 if (ret) { 11622 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 11623 goto err_mdiobus_unreg; 11624 } 11625 11626 ret = hclge_tm_schd_init(hdev); 11627 if (ret) { 11628 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 11629 goto err_mdiobus_unreg; 11630 } 11631 11632 ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev, 11633 &hdev->rss_cfg); 11634 if (ret) { 11635 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 11636 goto err_mdiobus_unreg; 11637 } 11638 11639 ret = hclge_rss_init_hw(hdev); 11640 if (ret) { 11641 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 11642 goto err_mdiobus_unreg; 11643 } 11644 11645 ret = init_mgr_tbl(hdev); 11646 if (ret) { 11647 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 11648 goto err_mdiobus_unreg; 11649 } 11650 11651 ret = hclge_init_fd_config(hdev); 11652 if (ret) { 11653 dev_err(&pdev->dev, 11654 "fd table init fail, ret=%d\n", ret); 11655 goto err_mdiobus_unreg; 11656 } 11657 11658 ret = hclge_ptp_init(hdev); 11659 if (ret) 11660 goto err_mdiobus_unreg; 11661 11662 ret = hclge_update_port_info(hdev); 11663 if (ret) 11664 goto err_mdiobus_unreg; 11665 11666 INIT_KFIFO(hdev->mac_tnl_log); 11667 11668 hclge_dcb_ops_set(hdev); 11669 11670 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0); 11671 INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task); 11672 11673 hclge_clear_all_event_cause(hdev); 11674 hclge_clear_resetting_state(hdev); 11675 11676 /* Log and clear the hw errors those already occurred */ 11677 if (hnae3_dev_ras_imp_supported(hdev)) 11678 hclge_handle_occurred_error(hdev); 11679 else 11680 hclge_handle_all_hns_hw_errors(ae_dev); 11681 11682 /* request delayed reset for the error recovery because an immediate 11683 * global reset on a PF affecting pending initialization of other PFs 11684 */ 11685 if (ae_dev->hw_err_reset_req) { 11686 enum hnae3_reset_type reset_level; 11687 11688 reset_level = hclge_get_reset_level(ae_dev, 11689 &ae_dev->hw_err_reset_req); 11690 hclge_set_def_reset_request(ae_dev, reset_level); 11691 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 11692 } 11693 11694 hclge_init_rxd_adv_layout(hdev); 11695 11696 /* Enable MISC vector(vector0) */ 11697 hclge_enable_vector(&hdev->misc_vector, true); 11698 11699 hclge_state_init(hdev); 11700 hdev->last_reset_time = jiffies; 11701 11702 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", 11703 HCLGE_DRIVER_NAME); 11704 11705 hclge_task_schedule(hdev, round_jiffies_relative(HZ)); 11706 11707 return 0; 11708 11709 err_mdiobus_unreg: 11710 if (hdev->hw.mac.phydev) 11711 mdiobus_unregister(hdev->hw.mac.mdio_bus); 11712 err_msi_irq_uninit: 11713 hclge_misc_irq_uninit(hdev); 11714 err_msi_uninit: 11715 pci_free_irq_vectors(pdev); 11716 err_cmd_uninit: 11717 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 11718 err_devlink_uninit: 11719 hclge_devlink_uninit(hdev); 11720 err_pci_uninit: 11721 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11722 pci_clear_master(pdev); 11723 pci_release_regions(pdev); 11724 pci_disable_device(pdev); 11725 out: 11726 mutex_destroy(&hdev->vport_lock); 11727 return ret; 11728 } 11729 11730 static void hclge_stats_clear(struct hclge_dev *hdev) 11731 { 11732 memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats)); 11733 memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats)); 11734 } 11735 11736 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11737 { 11738 return hclge_config_switch_param(hdev, vf, enable, 11739 HCLGE_SWITCH_ANTI_SPOOF_MASK); 11740 } 11741 11742 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11743 { 11744 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 11745 HCLGE_FILTER_FE_NIC_INGRESS_B, 11746 enable, vf); 11747 } 11748 11749 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) 11750 { 11751 int ret; 11752 11753 ret = hclge_set_mac_spoofchk(hdev, vf, enable); 11754 if (ret) { 11755 dev_err(&hdev->pdev->dev, 11756 "Set vf %d mac spoof check %s failed, ret=%d\n", 11757 vf, enable ? "on" : "off", ret); 11758 return ret; 11759 } 11760 11761 ret = hclge_set_vlan_spoofchk(hdev, vf, enable); 11762 if (ret) 11763 dev_err(&hdev->pdev->dev, 11764 "Set vf %d vlan spoof check %s failed, ret=%d\n", 11765 vf, enable ? "on" : "off", ret); 11766 11767 return ret; 11768 } 11769 11770 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf, 11771 bool enable) 11772 { 11773 struct hclge_vport *vport = hclge_get_vport(handle); 11774 struct hclge_dev *hdev = vport->back; 11775 u32 new_spoofchk = enable ? 1 : 0; 11776 int ret; 11777 11778 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11779 return -EOPNOTSUPP; 11780 11781 vport = hclge_get_vf_vport(hdev, vf); 11782 if (!vport) 11783 return -EINVAL; 11784 11785 if (vport->vf_info.spoofchk == new_spoofchk) 11786 return 0; 11787 11788 if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full)) 11789 dev_warn(&hdev->pdev->dev, 11790 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n", 11791 vf); 11792 else if (enable && hclge_is_umv_space_full(vport, true)) 11793 dev_warn(&hdev->pdev->dev, 11794 "vf %d mac table is full, enable spoof check may cause its packet send fail\n", 11795 vf); 11796 11797 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable); 11798 if (ret) 11799 return ret; 11800 11801 vport->vf_info.spoofchk = new_spoofchk; 11802 return 0; 11803 } 11804 11805 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev) 11806 { 11807 struct hclge_vport *vport = hdev->vport; 11808 int ret; 11809 int i; 11810 11811 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11812 return 0; 11813 11814 /* resume the vf spoof check state after reset */ 11815 for (i = 0; i < hdev->num_alloc_vport; i++) { 11816 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, 11817 vport->vf_info.spoofchk); 11818 if (ret) 11819 return ret; 11820 11821 vport++; 11822 } 11823 11824 return 0; 11825 } 11826 11827 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable) 11828 { 11829 struct hclge_vport *vport = hclge_get_vport(handle); 11830 struct hclge_dev *hdev = vport->back; 11831 u32 new_trusted = enable ? 1 : 0; 11832 11833 vport = hclge_get_vf_vport(hdev, vf); 11834 if (!vport) 11835 return -EINVAL; 11836 11837 if (vport->vf_info.trusted == new_trusted) 11838 return 0; 11839 11840 vport->vf_info.trusted = new_trusted; 11841 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 11842 hclge_task_schedule(hdev, 0); 11843 11844 return 0; 11845 } 11846 11847 static void hclge_reset_vf_rate(struct hclge_dev *hdev) 11848 { 11849 int ret; 11850 int vf; 11851 11852 /* reset vf rate to default value */ 11853 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 11854 struct hclge_vport *vport = &hdev->vport[vf]; 11855 11856 vport->vf_info.max_tx_rate = 0; 11857 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); 11858 if (ret) 11859 dev_err(&hdev->pdev->dev, 11860 "vf%d failed to reset to default, ret=%d\n", 11861 vf - HCLGE_VF_VPORT_START_NUM, ret); 11862 } 11863 } 11864 11865 static int hclge_vf_rate_param_check(struct hclge_dev *hdev, 11866 int min_tx_rate, int max_tx_rate) 11867 { 11868 if (min_tx_rate != 0 || 11869 max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) { 11870 dev_err(&hdev->pdev->dev, 11871 "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n", 11872 min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed); 11873 return -EINVAL; 11874 } 11875 11876 return 0; 11877 } 11878 11879 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf, 11880 int min_tx_rate, int max_tx_rate, bool force) 11881 { 11882 struct hclge_vport *vport = hclge_get_vport(handle); 11883 struct hclge_dev *hdev = vport->back; 11884 int ret; 11885 11886 ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate); 11887 if (ret) 11888 return ret; 11889 11890 vport = hclge_get_vf_vport(hdev, vf); 11891 if (!vport) 11892 return -EINVAL; 11893 11894 if (!force && max_tx_rate == vport->vf_info.max_tx_rate) 11895 return 0; 11896 11897 ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); 11898 if (ret) 11899 return ret; 11900 11901 vport->vf_info.max_tx_rate = max_tx_rate; 11902 11903 return 0; 11904 } 11905 11906 static int hclge_resume_vf_rate(struct hclge_dev *hdev) 11907 { 11908 struct hnae3_handle *handle = &hdev->vport->nic; 11909 struct hclge_vport *vport; 11910 int ret; 11911 int vf; 11912 11913 /* resume the vf max_tx_rate after reset */ 11914 for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) { 11915 vport = hclge_get_vf_vport(hdev, vf); 11916 if (!vport) 11917 return -EINVAL; 11918 11919 /* zero means max rate, after reset, firmware already set it to 11920 * max rate, so just continue. 11921 */ 11922 if (!vport->vf_info.max_tx_rate) 11923 continue; 11924 11925 ret = hclge_set_vf_rate(handle, vf, 0, 11926 vport->vf_info.max_tx_rate, true); 11927 if (ret) { 11928 dev_err(&hdev->pdev->dev, 11929 "vf%d failed to resume tx_rate:%u, ret=%d\n", 11930 vf, vport->vf_info.max_tx_rate, ret); 11931 return ret; 11932 } 11933 } 11934 11935 return 0; 11936 } 11937 11938 static void hclge_reset_vport_state(struct hclge_dev *hdev) 11939 { 11940 struct hclge_vport *vport = hdev->vport; 11941 int i; 11942 11943 for (i = 0; i < hdev->num_alloc_vport; i++) { 11944 hclge_vport_stop(vport); 11945 vport++; 11946 } 11947 } 11948 11949 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 11950 { 11951 struct hclge_dev *hdev = ae_dev->priv; 11952 struct pci_dev *pdev = ae_dev->pdev; 11953 int ret; 11954 11955 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11956 11957 hclge_stats_clear(hdev); 11958 /* NOTE: pf reset needn't to clear or restore pf and vf table entry. 11959 * so here should not clean table in memory. 11960 */ 11961 if (hdev->reset_type == HNAE3_IMP_RESET || 11962 hdev->reset_type == HNAE3_GLOBAL_RESET) { 11963 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 11964 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full)); 11965 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport); 11966 hclge_reset_umv_space(hdev); 11967 } 11968 11969 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 11970 true, hdev->reset_pending); 11971 if (ret) { 11972 dev_err(&pdev->dev, "Cmd queue init failed\n"); 11973 return ret; 11974 } 11975 11976 ret = hclge_map_tqp(hdev); 11977 if (ret) { 11978 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 11979 return ret; 11980 } 11981 11982 ret = hclge_mac_init(hdev); 11983 if (ret) { 11984 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 11985 return ret; 11986 } 11987 11988 ret = hclge_tp_port_init(hdev); 11989 if (ret) { 11990 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n", 11991 ret); 11992 return ret; 11993 } 11994 11995 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 11996 if (ret) { 11997 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 11998 return ret; 11999 } 12000 12001 ret = hclge_config_gro(hdev); 12002 if (ret) 12003 return ret; 12004 12005 ret = hclge_init_vlan_config(hdev); 12006 if (ret) { 12007 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 12008 return ret; 12009 } 12010 12011 ret = hclge_tm_init_hw(hdev, true); 12012 if (ret) { 12013 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 12014 return ret; 12015 } 12016 12017 ret = hclge_rss_init_hw(hdev); 12018 if (ret) { 12019 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 12020 return ret; 12021 } 12022 12023 ret = init_mgr_tbl(hdev); 12024 if (ret) { 12025 dev_err(&pdev->dev, 12026 "failed to reinit manager table, ret = %d\n", ret); 12027 return ret; 12028 } 12029 12030 ret = hclge_init_fd_config(hdev); 12031 if (ret) { 12032 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret); 12033 return ret; 12034 } 12035 12036 ret = hclge_ptp_init(hdev); 12037 if (ret) 12038 return ret; 12039 12040 /* Log and clear the hw errors those already occurred */ 12041 if (hnae3_dev_ras_imp_supported(hdev)) 12042 hclge_handle_occurred_error(hdev); 12043 else 12044 hclge_handle_all_hns_hw_errors(ae_dev); 12045 12046 /* Re-enable the hw error interrupts because 12047 * the interrupts get disabled on global reset. 12048 */ 12049 ret = hclge_config_nic_hw_error(hdev, true); 12050 if (ret) { 12051 dev_err(&pdev->dev, 12052 "fail(%d) to re-enable NIC hw error interrupts\n", 12053 ret); 12054 return ret; 12055 } 12056 12057 if (hdev->roce_client) { 12058 ret = hclge_config_rocee_ras_interrupt(hdev, true); 12059 if (ret) { 12060 dev_err(&pdev->dev, 12061 "fail(%d) to re-enable roce ras interrupts\n", 12062 ret); 12063 return ret; 12064 } 12065 } 12066 12067 hclge_reset_vport_state(hdev); 12068 ret = hclge_reset_vport_spoofchk(hdev); 12069 if (ret) 12070 return ret; 12071 12072 ret = hclge_resume_vf_rate(hdev); 12073 if (ret) 12074 return ret; 12075 12076 hclge_init_rxd_adv_layout(hdev); 12077 12078 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 12079 HCLGE_DRIVER_NAME); 12080 12081 return 0; 12082 } 12083 12084 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 12085 { 12086 struct hclge_dev *hdev = ae_dev->priv; 12087 struct hclge_mac *mac = &hdev->hw.mac; 12088 12089 hclge_reset_vf_rate(hdev); 12090 hclge_clear_vf_vlan(hdev); 12091 hclge_state_uninit(hdev); 12092 hclge_ptp_uninit(hdev); 12093 hclge_uninit_rxd_adv_layout(hdev); 12094 hclge_uninit_mac_table(hdev); 12095 hclge_del_all_fd_entries(hdev); 12096 12097 if (mac->phydev) 12098 mdiobus_unregister(mac->mdio_bus); 12099 12100 /* Disable MISC vector(vector0) */ 12101 hclge_enable_vector(&hdev->misc_vector, false); 12102 synchronize_irq(hdev->misc_vector.vector_irq); 12103 12104 /* Disable all hw interrupts */ 12105 hclge_config_mac_tnl_int(hdev, false); 12106 hclge_config_nic_hw_error(hdev, false); 12107 hclge_config_rocee_ras_interrupt(hdev, false); 12108 12109 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 12110 hclge_misc_irq_uninit(hdev); 12111 hclge_devlink_uninit(hdev); 12112 hclge_pci_uninit(hdev); 12113 hclge_uninit_vport_vlan_table(hdev); 12114 mutex_destroy(&hdev->vport_lock); 12115 ae_dev->priv = NULL; 12116 } 12117 12118 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 12119 { 12120 struct hclge_vport *vport = hclge_get_vport(handle); 12121 struct hclge_dev *hdev = vport->back; 12122 12123 return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps); 12124 } 12125 12126 static void hclge_get_channels(struct hnae3_handle *handle, 12127 struct ethtool_channels *ch) 12128 { 12129 ch->max_combined = hclge_get_max_channels(handle); 12130 ch->other_count = 1; 12131 ch->max_other = 1; 12132 ch->combined_count = handle->kinfo.rss_size; 12133 } 12134 12135 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 12136 u16 *alloc_tqps, u16 *max_rss_size) 12137 { 12138 struct hclge_vport *vport = hclge_get_vport(handle); 12139 struct hclge_dev *hdev = vport->back; 12140 12141 *alloc_tqps = vport->alloc_tqps; 12142 *max_rss_size = hdev->pf_rss_size_max; 12143 } 12144 12145 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle) 12146 { 12147 struct hclge_vport *vport = hclge_get_vport(handle); 12148 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 12149 struct hclge_dev *hdev = vport->back; 12150 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 12151 u16 tc_valid[HCLGE_MAX_TC_NUM]; 12152 u16 roundup_size; 12153 unsigned int i; 12154 12155 roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size); 12156 roundup_size = ilog2(roundup_size); 12157 /* Set the RSS TC mode according to the new RSS size */ 12158 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 12159 tc_valid[i] = 0; 12160 12161 if (!(hdev->hw_tc_map & BIT(i))) 12162 continue; 12163 12164 tc_valid[i] = 1; 12165 tc_size[i] = roundup_size; 12166 tc_offset[i] = vport->nic.kinfo.rss_size * i; 12167 } 12168 12169 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 12170 tc_size); 12171 } 12172 12173 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 12174 bool rxfh_configured) 12175 { 12176 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 12177 struct hclge_vport *vport = hclge_get_vport(handle); 12178 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 12179 struct hclge_dev *hdev = vport->back; 12180 u16 cur_rss_size = kinfo->rss_size; 12181 u16 cur_tqps = kinfo->num_tqps; 12182 u32 *rss_indir; 12183 unsigned int i; 12184 int ret; 12185 12186 kinfo->req_rss_size = new_tqps_num; 12187 12188 ret = hclge_tm_vport_map_update(hdev); 12189 if (ret) { 12190 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret); 12191 return ret; 12192 } 12193 12194 ret = hclge_set_rss_tc_mode_cfg(handle); 12195 if (ret) 12196 return ret; 12197 12198 /* RSS indirection table has been configured by user */ 12199 if (rxfh_configured) 12200 goto out; 12201 12202 /* Reinitializes the rss indirect table according to the new RSS size */ 12203 rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32), 12204 GFP_KERNEL); 12205 if (!rss_indir) 12206 return -ENOMEM; 12207 12208 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 12209 rss_indir[i] = i % kinfo->rss_size; 12210 12211 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 12212 if (ret) 12213 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 12214 ret); 12215 12216 kfree(rss_indir); 12217 12218 out: 12219 if (!ret) 12220 dev_info(&hdev->pdev->dev, 12221 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 12222 cur_rss_size, kinfo->rss_size, 12223 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 12224 12225 return ret; 12226 } 12227 12228 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit, 12229 u32 *regs_num_64_bit) 12230 { 12231 struct hclge_desc desc; 12232 u32 total_num; 12233 int ret; 12234 12235 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true); 12236 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12237 if (ret) { 12238 dev_err(&hdev->pdev->dev, 12239 "Query register number cmd failed, ret = %d.\n", ret); 12240 return ret; 12241 } 12242 12243 *regs_num_32_bit = le32_to_cpu(desc.data[0]); 12244 *regs_num_64_bit = le32_to_cpu(desc.data[1]); 12245 12246 total_num = *regs_num_32_bit + *regs_num_64_bit; 12247 if (!total_num) 12248 return -EINVAL; 12249 12250 return 0; 12251 } 12252 12253 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num, 12254 void *data) 12255 { 12256 #define HCLGE_32_BIT_REG_RTN_DATANUM 8 12257 #define HCLGE_32_BIT_DESC_NODATA_LEN 2 12258 12259 struct hclge_desc *desc; 12260 u32 *reg_val = data; 12261 __le32 *desc_data; 12262 int nodata_num; 12263 int cmd_num; 12264 int i, k, n; 12265 int ret; 12266 12267 if (regs_num == 0) 12268 return 0; 12269 12270 nodata_num = HCLGE_32_BIT_DESC_NODATA_LEN; 12271 cmd_num = DIV_ROUND_UP(regs_num + nodata_num, 12272 HCLGE_32_BIT_REG_RTN_DATANUM); 12273 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 12274 if (!desc) 12275 return -ENOMEM; 12276 12277 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true); 12278 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 12279 if (ret) { 12280 dev_err(&hdev->pdev->dev, 12281 "Query 32 bit register cmd failed, ret = %d.\n", ret); 12282 kfree(desc); 12283 return ret; 12284 } 12285 12286 for (i = 0; i < cmd_num; i++) { 12287 if (i == 0) { 12288 desc_data = (__le32 *)(&desc[i].data[0]); 12289 n = HCLGE_32_BIT_REG_RTN_DATANUM - nodata_num; 12290 } else { 12291 desc_data = (__le32 *)(&desc[i]); 12292 n = HCLGE_32_BIT_REG_RTN_DATANUM; 12293 } 12294 for (k = 0; k < n; k++) { 12295 *reg_val++ = le32_to_cpu(*desc_data++); 12296 12297 regs_num--; 12298 if (!regs_num) 12299 break; 12300 } 12301 } 12302 12303 kfree(desc); 12304 return 0; 12305 } 12306 12307 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num, 12308 void *data) 12309 { 12310 #define HCLGE_64_BIT_REG_RTN_DATANUM 4 12311 #define HCLGE_64_BIT_DESC_NODATA_LEN 1 12312 12313 struct hclge_desc *desc; 12314 u64 *reg_val = data; 12315 __le64 *desc_data; 12316 int nodata_len; 12317 int cmd_num; 12318 int i, k, n; 12319 int ret; 12320 12321 if (regs_num == 0) 12322 return 0; 12323 12324 nodata_len = HCLGE_64_BIT_DESC_NODATA_LEN; 12325 cmd_num = DIV_ROUND_UP(regs_num + nodata_len, 12326 HCLGE_64_BIT_REG_RTN_DATANUM); 12327 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 12328 if (!desc) 12329 return -ENOMEM; 12330 12331 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true); 12332 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 12333 if (ret) { 12334 dev_err(&hdev->pdev->dev, 12335 "Query 64 bit register cmd failed, ret = %d.\n", ret); 12336 kfree(desc); 12337 return ret; 12338 } 12339 12340 for (i = 0; i < cmd_num; i++) { 12341 if (i == 0) { 12342 desc_data = (__le64 *)(&desc[i].data[0]); 12343 n = HCLGE_64_BIT_REG_RTN_DATANUM - nodata_len; 12344 } else { 12345 desc_data = (__le64 *)(&desc[i]); 12346 n = HCLGE_64_BIT_REG_RTN_DATANUM; 12347 } 12348 for (k = 0; k < n; k++) { 12349 *reg_val++ = le64_to_cpu(*desc_data++); 12350 12351 regs_num--; 12352 if (!regs_num) 12353 break; 12354 } 12355 } 12356 12357 kfree(desc); 12358 return 0; 12359 } 12360 12361 #define MAX_SEPARATE_NUM 4 12362 #define SEPARATOR_VALUE 0xFDFCFBFA 12363 #define REG_NUM_PER_LINE 4 12364 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 12365 #define REG_SEPARATOR_LINE 1 12366 #define REG_NUM_REMAIN_MASK 3 12367 12368 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc) 12369 { 12370 int i; 12371 12372 /* initialize command BD except the last one */ 12373 for (i = 0; i < HCLGE_GET_DFX_REG_TYPE_CNT - 1; i++) { 12374 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM, 12375 true); 12376 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12377 } 12378 12379 /* initialize the last command BD */ 12380 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM, true); 12381 12382 return hclge_cmd_send(&hdev->hw, desc, HCLGE_GET_DFX_REG_TYPE_CNT); 12383 } 12384 12385 static int hclge_get_dfx_reg_bd_num(struct hclge_dev *hdev, 12386 int *bd_num_list, 12387 u32 type_num) 12388 { 12389 u32 entries_per_desc, desc_index, index, offset, i; 12390 struct hclge_desc desc[HCLGE_GET_DFX_REG_TYPE_CNT]; 12391 int ret; 12392 12393 ret = hclge_query_bd_num_cmd_send(hdev, desc); 12394 if (ret) { 12395 dev_err(&hdev->pdev->dev, 12396 "Get dfx bd num fail, status is %d.\n", ret); 12397 return ret; 12398 } 12399 12400 entries_per_desc = ARRAY_SIZE(desc[0].data); 12401 for (i = 0; i < type_num; i++) { 12402 offset = hclge_dfx_bd_offset_list[i]; 12403 index = offset % entries_per_desc; 12404 desc_index = offset / entries_per_desc; 12405 bd_num_list[i] = le32_to_cpu(desc[desc_index].data[index]); 12406 } 12407 12408 return ret; 12409 } 12410 12411 static int hclge_dfx_reg_cmd_send(struct hclge_dev *hdev, 12412 struct hclge_desc *desc_src, int bd_num, 12413 enum hclge_opcode_type cmd) 12414 { 12415 struct hclge_desc *desc = desc_src; 12416 int i, ret; 12417 12418 hclge_cmd_setup_basic_desc(desc, cmd, true); 12419 for (i = 0; i < bd_num - 1; i++) { 12420 desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12421 desc++; 12422 hclge_cmd_setup_basic_desc(desc, cmd, true); 12423 } 12424 12425 desc = desc_src; 12426 ret = hclge_cmd_send(&hdev->hw, desc, bd_num); 12427 if (ret) 12428 dev_err(&hdev->pdev->dev, 12429 "Query dfx reg cmd(0x%x) send fail, status is %d.\n", 12430 cmd, ret); 12431 12432 return ret; 12433 } 12434 12435 static int hclge_dfx_reg_fetch_data(struct hclge_desc *desc_src, int bd_num, 12436 void *data) 12437 { 12438 int entries_per_desc, reg_num, separator_num, desc_index, index, i; 12439 struct hclge_desc *desc = desc_src; 12440 u32 *reg = data; 12441 12442 entries_per_desc = ARRAY_SIZE(desc->data); 12443 reg_num = entries_per_desc * bd_num; 12444 separator_num = REG_NUM_PER_LINE - (reg_num & REG_NUM_REMAIN_MASK); 12445 for (i = 0; i < reg_num; i++) { 12446 index = i % entries_per_desc; 12447 desc_index = i / entries_per_desc; 12448 *reg++ = le32_to_cpu(desc[desc_index].data[index]); 12449 } 12450 for (i = 0; i < separator_num; i++) 12451 *reg++ = SEPARATOR_VALUE; 12452 12453 return reg_num + separator_num; 12454 } 12455 12456 static int hclge_get_dfx_reg_len(struct hclge_dev *hdev, int *len) 12457 { 12458 u32 dfx_reg_type_num = ARRAY_SIZE(hclge_dfx_bd_offset_list); 12459 int data_len_per_desc, bd_num, i; 12460 int *bd_num_list; 12461 u32 data_len; 12462 int ret; 12463 12464 bd_num_list = kcalloc(dfx_reg_type_num, sizeof(int), GFP_KERNEL); 12465 if (!bd_num_list) 12466 return -ENOMEM; 12467 12468 ret = hclge_get_dfx_reg_bd_num(hdev, bd_num_list, dfx_reg_type_num); 12469 if (ret) { 12470 dev_err(&hdev->pdev->dev, 12471 "Get dfx reg bd num fail, status is %d.\n", ret); 12472 goto out; 12473 } 12474 12475 data_len_per_desc = sizeof_field(struct hclge_desc, data); 12476 *len = 0; 12477 for (i = 0; i < dfx_reg_type_num; i++) { 12478 bd_num = bd_num_list[i]; 12479 data_len = data_len_per_desc * bd_num; 12480 *len += (data_len / REG_LEN_PER_LINE + 1) * REG_LEN_PER_LINE; 12481 } 12482 12483 out: 12484 kfree(bd_num_list); 12485 return ret; 12486 } 12487 12488 static int hclge_get_dfx_reg(struct hclge_dev *hdev, void *data) 12489 { 12490 u32 dfx_reg_type_num = ARRAY_SIZE(hclge_dfx_bd_offset_list); 12491 int bd_num, bd_num_max, buf_len, i; 12492 struct hclge_desc *desc_src; 12493 int *bd_num_list; 12494 u32 *reg = data; 12495 int ret; 12496 12497 bd_num_list = kcalloc(dfx_reg_type_num, sizeof(int), GFP_KERNEL); 12498 if (!bd_num_list) 12499 return -ENOMEM; 12500 12501 ret = hclge_get_dfx_reg_bd_num(hdev, bd_num_list, dfx_reg_type_num); 12502 if (ret) { 12503 dev_err(&hdev->pdev->dev, 12504 "Get dfx reg bd num fail, status is %d.\n", ret); 12505 goto out; 12506 } 12507 12508 bd_num_max = bd_num_list[0]; 12509 for (i = 1; i < dfx_reg_type_num; i++) 12510 bd_num_max = max_t(int, bd_num_max, bd_num_list[i]); 12511 12512 buf_len = sizeof(*desc_src) * bd_num_max; 12513 desc_src = kzalloc(buf_len, GFP_KERNEL); 12514 if (!desc_src) { 12515 ret = -ENOMEM; 12516 goto out; 12517 } 12518 12519 for (i = 0; i < dfx_reg_type_num; i++) { 12520 bd_num = bd_num_list[i]; 12521 ret = hclge_dfx_reg_cmd_send(hdev, desc_src, bd_num, 12522 hclge_dfx_reg_opcode_list[i]); 12523 if (ret) { 12524 dev_err(&hdev->pdev->dev, 12525 "Get dfx reg fail, status is %d.\n", ret); 12526 break; 12527 } 12528 12529 reg += hclge_dfx_reg_fetch_data(desc_src, bd_num, reg); 12530 } 12531 12532 kfree(desc_src); 12533 out: 12534 kfree(bd_num_list); 12535 return ret; 12536 } 12537 12538 static int hclge_fetch_pf_reg(struct hclge_dev *hdev, void *data, 12539 struct hnae3_knic_private_info *kinfo) 12540 { 12541 #define HCLGE_RING_REG_OFFSET 0x200 12542 #define HCLGE_RING_INT_REG_OFFSET 0x4 12543 12544 int i, j, reg_num, separator_num; 12545 int data_num_sum; 12546 u32 *reg = data; 12547 12548 /* fetching per-PF registers valus from PF PCIe register space */ 12549 reg_num = ARRAY_SIZE(cmdq_reg_addr_list); 12550 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12551 for (i = 0; i < reg_num; i++) 12552 *reg++ = hclge_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 12553 for (i = 0; i < separator_num; i++) 12554 *reg++ = SEPARATOR_VALUE; 12555 data_num_sum = reg_num + separator_num; 12556 12557 reg_num = ARRAY_SIZE(common_reg_addr_list); 12558 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12559 for (i = 0; i < reg_num; i++) 12560 *reg++ = hclge_read_dev(&hdev->hw, common_reg_addr_list[i]); 12561 for (i = 0; i < separator_num; i++) 12562 *reg++ = SEPARATOR_VALUE; 12563 data_num_sum += reg_num + separator_num; 12564 12565 reg_num = ARRAY_SIZE(ring_reg_addr_list); 12566 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12567 for (j = 0; j < kinfo->num_tqps; j++) { 12568 for (i = 0; i < reg_num; i++) 12569 *reg++ = hclge_read_dev(&hdev->hw, 12570 ring_reg_addr_list[i] + 12571 HCLGE_RING_REG_OFFSET * j); 12572 for (i = 0; i < separator_num; i++) 12573 *reg++ = SEPARATOR_VALUE; 12574 } 12575 data_num_sum += (reg_num + separator_num) * kinfo->num_tqps; 12576 12577 reg_num = ARRAY_SIZE(tqp_intr_reg_addr_list); 12578 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12579 for (j = 0; j < hdev->num_msi_used - 1; j++) { 12580 for (i = 0; i < reg_num; i++) 12581 *reg++ = hclge_read_dev(&hdev->hw, 12582 tqp_intr_reg_addr_list[i] + 12583 HCLGE_RING_INT_REG_OFFSET * j); 12584 for (i = 0; i < separator_num; i++) 12585 *reg++ = SEPARATOR_VALUE; 12586 } 12587 data_num_sum += (reg_num + separator_num) * (hdev->num_msi_used - 1); 12588 12589 return data_num_sum; 12590 } 12591 12592 static int hclge_get_regs_len(struct hnae3_handle *handle) 12593 { 12594 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 12595 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 12596 struct hclge_vport *vport = hclge_get_vport(handle); 12597 struct hclge_dev *hdev = vport->back; 12598 int regs_num_32_bit, regs_num_64_bit, dfx_regs_len; 12599 int regs_lines_32_bit, regs_lines_64_bit; 12600 int ret; 12601 12602 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 12603 if (ret) { 12604 dev_err(&hdev->pdev->dev, 12605 "Get register number failed, ret = %d.\n", ret); 12606 return ret; 12607 } 12608 12609 ret = hclge_get_dfx_reg_len(hdev, &dfx_regs_len); 12610 if (ret) { 12611 dev_err(&hdev->pdev->dev, 12612 "Get dfx reg len failed, ret = %d.\n", ret); 12613 return ret; 12614 } 12615 12616 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 12617 REG_SEPARATOR_LINE; 12618 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 12619 REG_SEPARATOR_LINE; 12620 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 12621 REG_SEPARATOR_LINE; 12622 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 12623 REG_SEPARATOR_LINE; 12624 regs_lines_32_bit = regs_num_32_bit * sizeof(u32) / REG_LEN_PER_LINE + 12625 REG_SEPARATOR_LINE; 12626 regs_lines_64_bit = regs_num_64_bit * sizeof(u64) / REG_LEN_PER_LINE + 12627 REG_SEPARATOR_LINE; 12628 12629 return (cmdq_lines + common_lines + ring_lines * kinfo->num_tqps + 12630 tqp_intr_lines * (hdev->num_msi_used - 1) + regs_lines_32_bit + 12631 regs_lines_64_bit) * REG_LEN_PER_LINE + dfx_regs_len; 12632 } 12633 12634 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version, 12635 void *data) 12636 { 12637 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 12638 struct hclge_vport *vport = hclge_get_vport(handle); 12639 struct hclge_dev *hdev = vport->back; 12640 u32 regs_num_32_bit, regs_num_64_bit; 12641 int i, reg_num, separator_num, ret; 12642 u32 *reg = data; 12643 12644 *version = hdev->fw_version; 12645 12646 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 12647 if (ret) { 12648 dev_err(&hdev->pdev->dev, 12649 "Get register number failed, ret = %d.\n", ret); 12650 return; 12651 } 12652 12653 reg += hclge_fetch_pf_reg(hdev, reg, kinfo); 12654 12655 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, reg); 12656 if (ret) { 12657 dev_err(&hdev->pdev->dev, 12658 "Get 32 bit register failed, ret = %d.\n", ret); 12659 return; 12660 } 12661 reg_num = regs_num_32_bit; 12662 reg += reg_num; 12663 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12664 for (i = 0; i < separator_num; i++) 12665 *reg++ = SEPARATOR_VALUE; 12666 12667 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, reg); 12668 if (ret) { 12669 dev_err(&hdev->pdev->dev, 12670 "Get 64 bit register failed, ret = %d.\n", ret); 12671 return; 12672 } 12673 reg_num = regs_num_64_bit * 2; 12674 reg += reg_num; 12675 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12676 for (i = 0; i < separator_num; i++) 12677 *reg++ = SEPARATOR_VALUE; 12678 12679 ret = hclge_get_dfx_reg(hdev, reg); 12680 if (ret) 12681 dev_err(&hdev->pdev->dev, 12682 "Get dfx register failed, ret = %d.\n", ret); 12683 } 12684 12685 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 12686 { 12687 struct hclge_set_led_state_cmd *req; 12688 struct hclge_desc desc; 12689 int ret; 12690 12691 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 12692 12693 req = (struct hclge_set_led_state_cmd *)desc.data; 12694 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 12695 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 12696 12697 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12698 if (ret) 12699 dev_err(&hdev->pdev->dev, 12700 "Send set led state cmd error, ret =%d\n", ret); 12701 12702 return ret; 12703 } 12704 12705 enum hclge_led_status { 12706 HCLGE_LED_OFF, 12707 HCLGE_LED_ON, 12708 HCLGE_LED_NO_CHANGE = 0xFF, 12709 }; 12710 12711 static int hclge_set_led_id(struct hnae3_handle *handle, 12712 enum ethtool_phys_id_state status) 12713 { 12714 struct hclge_vport *vport = hclge_get_vport(handle); 12715 struct hclge_dev *hdev = vport->back; 12716 12717 switch (status) { 12718 case ETHTOOL_ID_ACTIVE: 12719 return hclge_set_led_status(hdev, HCLGE_LED_ON); 12720 case ETHTOOL_ID_INACTIVE: 12721 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 12722 default: 12723 return -EINVAL; 12724 } 12725 } 12726 12727 static void hclge_get_link_mode(struct hnae3_handle *handle, 12728 unsigned long *supported, 12729 unsigned long *advertising) 12730 { 12731 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 12732 struct hclge_vport *vport = hclge_get_vport(handle); 12733 struct hclge_dev *hdev = vport->back; 12734 unsigned int idx = 0; 12735 12736 for (; idx < size; idx++) { 12737 supported[idx] = hdev->hw.mac.supported[idx]; 12738 advertising[idx] = hdev->hw.mac.advertising[idx]; 12739 } 12740 } 12741 12742 static int hclge_gro_en(struct hnae3_handle *handle, bool enable) 12743 { 12744 struct hclge_vport *vport = hclge_get_vport(handle); 12745 struct hclge_dev *hdev = vport->back; 12746 bool gro_en_old = hdev->gro_en; 12747 int ret; 12748 12749 hdev->gro_en = enable; 12750 ret = hclge_config_gro(hdev); 12751 if (ret) 12752 hdev->gro_en = gro_en_old; 12753 12754 return ret; 12755 } 12756 12757 static void hclge_sync_promisc_mode(struct hclge_dev *hdev) 12758 { 12759 struct hclge_vport *vport = &hdev->vport[0]; 12760 struct hnae3_handle *handle = &vport->nic; 12761 u8 tmp_flags; 12762 int ret; 12763 u16 i; 12764 12765 if (vport->last_promisc_flags != vport->overflow_promisc_flags) { 12766 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12767 vport->last_promisc_flags = vport->overflow_promisc_flags; 12768 } 12769 12770 if (test_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state)) { 12771 tmp_flags = handle->netdev_flags | vport->last_promisc_flags; 12772 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE, 12773 tmp_flags & HNAE3_MPE); 12774 if (!ret) { 12775 clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12776 &vport->state); 12777 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 12778 &vport->state); 12779 } 12780 } 12781 12782 for (i = 1; i < hdev->num_alloc_vport; i++) { 12783 bool uc_en = false; 12784 bool mc_en = false; 12785 bool bc_en; 12786 12787 vport = &hdev->vport[i]; 12788 12789 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12790 &vport->state)) 12791 continue; 12792 12793 if (vport->vf_info.trusted) { 12794 uc_en = vport->vf_info.request_uc_en > 0 || 12795 vport->overflow_promisc_flags & 12796 HNAE3_OVERFLOW_UPE; 12797 mc_en = vport->vf_info.request_mc_en > 0 || 12798 vport->overflow_promisc_flags & 12799 HNAE3_OVERFLOW_MPE; 12800 } 12801 bc_en = vport->vf_info.request_bc_en > 0; 12802 12803 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en, 12804 mc_en, bc_en); 12805 if (ret) { 12806 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12807 &vport->state); 12808 return; 12809 } 12810 hclge_set_vport_vlan_fltr_change(vport); 12811 } 12812 } 12813 12814 static bool hclge_module_existed(struct hclge_dev *hdev) 12815 { 12816 struct hclge_desc desc; 12817 u32 existed; 12818 int ret; 12819 12820 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true); 12821 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12822 if (ret) { 12823 dev_err(&hdev->pdev->dev, 12824 "failed to get SFP exist state, ret = %d\n", ret); 12825 return false; 12826 } 12827 12828 existed = le32_to_cpu(desc.data[0]); 12829 12830 return existed != 0; 12831 } 12832 12833 /* need 6 bds(total 140 bytes) in one reading 12834 * return the number of bytes actually read, 0 means read failed. 12835 */ 12836 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset, 12837 u32 len, u8 *data) 12838 { 12839 struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM]; 12840 struct hclge_sfp_info_bd0_cmd *sfp_info_bd0; 12841 u16 read_len; 12842 u16 copy_len; 12843 int ret; 12844 int i; 12845 12846 /* setup all 6 bds to read module eeprom info. */ 12847 for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12848 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM, 12849 true); 12850 12851 /* bd0~bd4 need next flag */ 12852 if (i < HCLGE_SFP_INFO_CMD_NUM - 1) 12853 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12854 } 12855 12856 /* setup bd0, this bd contains offset and read length. */ 12857 sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data; 12858 sfp_info_bd0->offset = cpu_to_le16((u16)offset); 12859 read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN); 12860 sfp_info_bd0->read_len = cpu_to_le16(read_len); 12861 12862 ret = hclge_cmd_send(&hdev->hw, desc, i); 12863 if (ret) { 12864 dev_err(&hdev->pdev->dev, 12865 "failed to get SFP eeprom info, ret = %d\n", ret); 12866 return 0; 12867 } 12868 12869 /* copy sfp info from bd0 to out buffer. */ 12870 copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN); 12871 memcpy(data, sfp_info_bd0->data, copy_len); 12872 read_len = copy_len; 12873 12874 /* copy sfp info from bd1~bd5 to out buffer if needed. */ 12875 for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12876 if (read_len >= len) 12877 return read_len; 12878 12879 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN); 12880 memcpy(data + read_len, desc[i].data, copy_len); 12881 read_len += copy_len; 12882 } 12883 12884 return read_len; 12885 } 12886 12887 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset, 12888 u32 len, u8 *data) 12889 { 12890 struct hclge_vport *vport = hclge_get_vport(handle); 12891 struct hclge_dev *hdev = vport->back; 12892 u32 read_len = 0; 12893 u16 data_len; 12894 12895 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 12896 return -EOPNOTSUPP; 12897 12898 if (!hclge_module_existed(hdev)) 12899 return -ENXIO; 12900 12901 while (read_len < len) { 12902 data_len = hclge_get_sfp_eeprom_info(hdev, 12903 offset + read_len, 12904 len - read_len, 12905 data + read_len); 12906 if (!data_len) 12907 return -EIO; 12908 12909 read_len += data_len; 12910 } 12911 12912 return 0; 12913 } 12914 12915 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle, 12916 u32 *status_code) 12917 { 12918 struct hclge_vport *vport = hclge_get_vport(handle); 12919 struct hclge_dev *hdev = vport->back; 12920 struct hclge_desc desc; 12921 int ret; 12922 12923 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 12924 return -EOPNOTSUPP; 12925 12926 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true); 12927 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12928 if (ret) { 12929 dev_err(&hdev->pdev->dev, 12930 "failed to query link diagnosis info, ret = %d\n", ret); 12931 return ret; 12932 } 12933 12934 *status_code = le32_to_cpu(desc.data[0]); 12935 return 0; 12936 } 12937 12938 /* After disable sriov, VF still has some config and info need clean, 12939 * which configed by PF. 12940 */ 12941 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid) 12942 { 12943 struct hclge_dev *hdev = vport->back; 12944 struct hclge_vlan_info vlan_info; 12945 int ret; 12946 12947 /* after disable sriov, clean VF rate configured by PF */ 12948 ret = hclge_tm_qs_shaper_cfg(vport, 0); 12949 if (ret) 12950 dev_err(&hdev->pdev->dev, 12951 "failed to clean vf%d rate config, ret = %d\n", 12952 vfid, ret); 12953 12954 vlan_info.vlan_tag = 0; 12955 vlan_info.qos = 0; 12956 vlan_info.vlan_proto = ETH_P_8021Q; 12957 ret = hclge_update_port_base_vlan_cfg(vport, 12958 HNAE3_PORT_BASE_VLAN_DISABLE, 12959 &vlan_info); 12960 if (ret) 12961 dev_err(&hdev->pdev->dev, 12962 "failed to clean vf%d port base vlan, ret = %d\n", 12963 vfid, ret); 12964 12965 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false); 12966 if (ret) 12967 dev_err(&hdev->pdev->dev, 12968 "failed to clean vf%d spoof config, ret = %d\n", 12969 vfid, ret); 12970 12971 memset(&vport->vf_info, 0, sizeof(vport->vf_info)); 12972 } 12973 12974 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs) 12975 { 12976 struct hclge_dev *hdev = ae_dev->priv; 12977 struct hclge_vport *vport; 12978 int i; 12979 12980 for (i = 0; i < num_vfs; i++) { 12981 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 12982 12983 hclge_clear_vport_vf_info(vport, i); 12984 } 12985 } 12986 12987 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode, 12988 u8 *priority) 12989 { 12990 struct hclge_vport *vport = hclge_get_vport(h); 12991 12992 if (dscp >= HNAE3_MAX_DSCP) 12993 return -EINVAL; 12994 12995 if (tc_mode) 12996 *tc_mode = vport->nic.kinfo.tc_map_mode; 12997 if (priority) 12998 *priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 : 12999 vport->nic.kinfo.dscp_prio[dscp]; 13000 13001 return 0; 13002 } 13003 13004 static const struct hnae3_ae_ops hclge_ops = { 13005 .init_ae_dev = hclge_init_ae_dev, 13006 .uninit_ae_dev = hclge_uninit_ae_dev, 13007 .reset_prepare = hclge_reset_prepare_general, 13008 .reset_done = hclge_reset_done, 13009 .init_client_instance = hclge_init_client_instance, 13010 .uninit_client_instance = hclge_uninit_client_instance, 13011 .map_ring_to_vector = hclge_map_ring_to_vector, 13012 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 13013 .get_vector = hclge_get_vector, 13014 .put_vector = hclge_put_vector, 13015 .set_promisc_mode = hclge_set_promisc_mode, 13016 .request_update_promisc_mode = hclge_request_update_promisc_mode, 13017 .set_loopback = hclge_set_loopback, 13018 .start = hclge_ae_start, 13019 .stop = hclge_ae_stop, 13020 .client_start = hclge_client_start, 13021 .client_stop = hclge_client_stop, 13022 .get_status = hclge_get_status, 13023 .get_ksettings_an_result = hclge_get_ksettings_an_result, 13024 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 13025 .get_media_type = hclge_get_media_type, 13026 .check_port_speed = hclge_check_port_speed, 13027 .get_fec_stats = hclge_get_fec_stats, 13028 .get_fec = hclge_get_fec, 13029 .set_fec = hclge_set_fec, 13030 .get_rss_key_size = hclge_comm_get_rss_key_size, 13031 .get_rss = hclge_get_rss, 13032 .set_rss = hclge_set_rss, 13033 .set_rss_tuple = hclge_set_rss_tuple, 13034 .get_rss_tuple = hclge_get_rss_tuple, 13035 .get_tc_size = hclge_get_tc_size, 13036 .get_mac_addr = hclge_get_mac_addr, 13037 .set_mac_addr = hclge_set_mac_addr, 13038 .do_ioctl = hclge_do_ioctl, 13039 .add_uc_addr = hclge_add_uc_addr, 13040 .rm_uc_addr = hclge_rm_uc_addr, 13041 .add_mc_addr = hclge_add_mc_addr, 13042 .rm_mc_addr = hclge_rm_mc_addr, 13043 .set_autoneg = hclge_set_autoneg, 13044 .get_autoneg = hclge_get_autoneg, 13045 .restart_autoneg = hclge_restart_autoneg, 13046 .halt_autoneg = hclge_halt_autoneg, 13047 .get_pauseparam = hclge_get_pauseparam, 13048 .set_pauseparam = hclge_set_pauseparam, 13049 .set_mtu = hclge_set_mtu, 13050 .reset_queue = hclge_reset_tqp, 13051 .get_stats = hclge_get_stats, 13052 .get_mac_stats = hclge_get_mac_stat, 13053 .update_stats = hclge_update_stats, 13054 .get_strings = hclge_get_strings, 13055 .get_sset_count = hclge_get_sset_count, 13056 .get_fw_version = hclge_get_fw_version, 13057 .get_mdix_mode = hclge_get_mdix_mode, 13058 .enable_vlan_filter = hclge_enable_vlan_filter, 13059 .set_vlan_filter = hclge_set_vlan_filter, 13060 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 13061 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 13062 .reset_event = hclge_reset_event, 13063 .get_reset_level = hclge_get_reset_level, 13064 .set_default_reset_request = hclge_set_def_reset_request, 13065 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 13066 .set_channels = hclge_set_channels, 13067 .get_channels = hclge_get_channels, 13068 .get_regs_len = hclge_get_regs_len, 13069 .get_regs = hclge_get_regs, 13070 .set_led_id = hclge_set_led_id, 13071 .get_link_mode = hclge_get_link_mode, 13072 .add_fd_entry = hclge_add_fd_entry, 13073 .del_fd_entry = hclge_del_fd_entry, 13074 .get_fd_rule_cnt = hclge_get_fd_rule_cnt, 13075 .get_fd_rule_info = hclge_get_fd_rule_info, 13076 .get_fd_all_rules = hclge_get_all_rules, 13077 .enable_fd = hclge_enable_fd, 13078 .add_arfs_entry = hclge_add_fd_entry_by_arfs, 13079 .dbg_read_cmd = hclge_dbg_read_cmd, 13080 .handle_hw_ras_error = hclge_handle_hw_ras_error, 13081 .get_hw_reset_stat = hclge_get_hw_reset_stat, 13082 .ae_dev_resetting = hclge_ae_dev_resetting, 13083 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt, 13084 .set_gro_en = hclge_gro_en, 13085 .get_global_queue_id = hclge_covert_handle_qid_global, 13086 .set_timer_task = hclge_set_timer_task, 13087 .mac_connect_phy = hclge_mac_connect_phy, 13088 .mac_disconnect_phy = hclge_mac_disconnect_phy, 13089 .get_vf_config = hclge_get_vf_config, 13090 .set_vf_link_state = hclge_set_vf_link_state, 13091 .set_vf_spoofchk = hclge_set_vf_spoofchk, 13092 .set_vf_trust = hclge_set_vf_trust, 13093 .set_vf_rate = hclge_set_vf_rate, 13094 .set_vf_mac = hclge_set_vf_mac, 13095 .get_module_eeprom = hclge_get_module_eeprom, 13096 .get_cmdq_stat = hclge_get_cmdq_stat, 13097 .add_cls_flower = hclge_add_cls_flower, 13098 .del_cls_flower = hclge_del_cls_flower, 13099 .cls_flower_active = hclge_is_cls_flower_active, 13100 .get_phy_link_ksettings = hclge_get_phy_link_ksettings, 13101 .set_phy_link_ksettings = hclge_set_phy_link_ksettings, 13102 .set_tx_hwts_info = hclge_ptp_set_tx_info, 13103 .get_rx_hwts = hclge_ptp_get_rx_hwts, 13104 .get_ts_info = hclge_ptp_get_ts_info, 13105 .get_link_diagnosis_info = hclge_get_link_diagnosis_info, 13106 .clean_vf_config = hclge_clean_vport_config, 13107 .get_dscp_prio = hclge_get_dscp_prio, 13108 }; 13109 13110 static struct hnae3_ae_algo ae_algo = { 13111 .ops = &hclge_ops, 13112 .pdev_id_table = ae_algo_pci_tbl, 13113 }; 13114 13115 static int __init hclge_init(void) 13116 { 13117 pr_info("%s is initializing\n", HCLGE_NAME); 13118 13119 hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGE_NAME); 13120 if (!hclge_wq) { 13121 pr_err("%s: failed to create workqueue\n", HCLGE_NAME); 13122 return -ENOMEM; 13123 } 13124 13125 hnae3_register_ae_algo(&ae_algo); 13126 13127 return 0; 13128 } 13129 13130 static void __exit hclge_exit(void) 13131 { 13132 hnae3_unregister_ae_algo_prepare(&ae_algo); 13133 hnae3_unregister_ae_algo(&ae_algo); 13134 destroy_workqueue(hclge_wq); 13135 } 13136 module_init(hclge_init); 13137 module_exit(hclge_exit); 13138 13139 MODULE_LICENSE("GPL"); 13140 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 13141 MODULE_DESCRIPTION("HCLGE Driver"); 13142 MODULE_VERSION(HCLGE_MOD_VERSION); 13143