1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/pci.h> 13 #include <linux/platform_device.h> 14 #include <linux/if_vlan.h> 15 #include <net/rtnetlink.h> 16 #include "hclge_cmd.h" 17 #include "hclge_dcb.h" 18 #include "hclge_main.h" 19 #include "hclge_mbx.h" 20 #include "hclge_mdio.h" 21 #include "hclge_tm.h" 22 #include "hclge_err.h" 23 #include "hnae3.h" 24 25 #define HCLGE_NAME "hclge" 26 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset)))) 27 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f)) 28 29 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu); 30 static int hclge_init_vlan_config(struct hclge_dev *hdev); 31 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 32 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 33 u16 *allocated_size, bool is_alloc); 34 35 static struct hnae3_ae_algo ae_algo; 36 37 static const struct pci_device_id ae_algo_pci_tbl[] = { 38 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 39 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 45 /* required last entry */ 46 {0, } 47 }; 48 49 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 50 51 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 52 "App Loopback test", 53 "Serdes serial Loopback test", 54 "Serdes parallel Loopback test", 55 "Phy Loopback test" 56 }; 57 58 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 59 {"mac_tx_mac_pause_num", 60 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 61 {"mac_rx_mac_pause_num", 62 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 63 {"mac_tx_pfc_pri0_pkt_num", 64 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 65 {"mac_tx_pfc_pri1_pkt_num", 66 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 67 {"mac_tx_pfc_pri2_pkt_num", 68 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 69 {"mac_tx_pfc_pri3_pkt_num", 70 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 71 {"mac_tx_pfc_pri4_pkt_num", 72 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 73 {"mac_tx_pfc_pri5_pkt_num", 74 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 75 {"mac_tx_pfc_pri6_pkt_num", 76 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 77 {"mac_tx_pfc_pri7_pkt_num", 78 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 79 {"mac_rx_pfc_pri0_pkt_num", 80 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 81 {"mac_rx_pfc_pri1_pkt_num", 82 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 83 {"mac_rx_pfc_pri2_pkt_num", 84 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 85 {"mac_rx_pfc_pri3_pkt_num", 86 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 87 {"mac_rx_pfc_pri4_pkt_num", 88 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 89 {"mac_rx_pfc_pri5_pkt_num", 90 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 91 {"mac_rx_pfc_pri6_pkt_num", 92 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 93 {"mac_rx_pfc_pri7_pkt_num", 94 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 95 {"mac_tx_total_pkt_num", 96 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 97 {"mac_tx_total_oct_num", 98 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 99 {"mac_tx_good_pkt_num", 100 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 101 {"mac_tx_bad_pkt_num", 102 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 103 {"mac_tx_good_oct_num", 104 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 105 {"mac_tx_bad_oct_num", 106 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 107 {"mac_tx_uni_pkt_num", 108 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 109 {"mac_tx_multi_pkt_num", 110 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 111 {"mac_tx_broad_pkt_num", 112 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 113 {"mac_tx_undersize_pkt_num", 114 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 115 {"mac_tx_oversize_pkt_num", 116 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 117 {"mac_tx_64_oct_pkt_num", 118 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 119 {"mac_tx_65_127_oct_pkt_num", 120 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 121 {"mac_tx_128_255_oct_pkt_num", 122 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 123 {"mac_tx_256_511_oct_pkt_num", 124 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 125 {"mac_tx_512_1023_oct_pkt_num", 126 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 127 {"mac_tx_1024_1518_oct_pkt_num", 128 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 129 {"mac_tx_1519_2047_oct_pkt_num", 130 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 131 {"mac_tx_2048_4095_oct_pkt_num", 132 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 133 {"mac_tx_4096_8191_oct_pkt_num", 134 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 135 {"mac_tx_8192_9216_oct_pkt_num", 136 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 137 {"mac_tx_9217_12287_oct_pkt_num", 138 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 139 {"mac_tx_12288_16383_oct_pkt_num", 140 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 141 {"mac_tx_1519_max_good_pkt_num", 142 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 143 {"mac_tx_1519_max_bad_pkt_num", 144 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 145 {"mac_rx_total_pkt_num", 146 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 147 {"mac_rx_total_oct_num", 148 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 149 {"mac_rx_good_pkt_num", 150 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 151 {"mac_rx_bad_pkt_num", 152 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 153 {"mac_rx_good_oct_num", 154 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 155 {"mac_rx_bad_oct_num", 156 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 157 {"mac_rx_uni_pkt_num", 158 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 159 {"mac_rx_multi_pkt_num", 160 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 161 {"mac_rx_broad_pkt_num", 162 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 163 {"mac_rx_undersize_pkt_num", 164 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 165 {"mac_rx_oversize_pkt_num", 166 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 167 {"mac_rx_64_oct_pkt_num", 168 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 169 {"mac_rx_65_127_oct_pkt_num", 170 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 171 {"mac_rx_128_255_oct_pkt_num", 172 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 173 {"mac_rx_256_511_oct_pkt_num", 174 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 175 {"mac_rx_512_1023_oct_pkt_num", 176 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 177 {"mac_rx_1024_1518_oct_pkt_num", 178 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 179 {"mac_rx_1519_2047_oct_pkt_num", 180 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 181 {"mac_rx_2048_4095_oct_pkt_num", 182 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 183 {"mac_rx_4096_8191_oct_pkt_num", 184 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 185 {"mac_rx_8192_9216_oct_pkt_num", 186 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 187 {"mac_rx_9217_12287_oct_pkt_num", 188 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 189 {"mac_rx_12288_16383_oct_pkt_num", 190 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 191 {"mac_rx_1519_max_good_pkt_num", 192 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 193 {"mac_rx_1519_max_bad_pkt_num", 194 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 195 196 {"mac_tx_fragment_pkt_num", 197 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 198 {"mac_tx_undermin_pkt_num", 199 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 200 {"mac_tx_jabber_pkt_num", 201 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 202 {"mac_tx_err_all_pkt_num", 203 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 204 {"mac_tx_from_app_good_pkt_num", 205 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 206 {"mac_tx_from_app_bad_pkt_num", 207 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 208 {"mac_rx_fragment_pkt_num", 209 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 210 {"mac_rx_undermin_pkt_num", 211 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 212 {"mac_rx_jabber_pkt_num", 213 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 214 {"mac_rx_fcs_err_pkt_num", 215 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 216 {"mac_rx_send_app_good_pkt_num", 217 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 218 {"mac_rx_send_app_bad_pkt_num", 219 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 220 }; 221 222 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 223 { 224 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 225 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP), 226 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)), 227 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)), 228 .i_port_bitmap = 0x1, 229 }, 230 }; 231 232 static int hclge_mac_update_stats(struct hclge_dev *hdev) 233 { 234 #define HCLGE_MAC_CMD_NUM 21 235 #define HCLGE_RTN_DATA_NUM 4 236 237 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats); 238 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 239 __le64 *desc_data; 240 int i, k, n; 241 int ret; 242 243 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 244 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 245 if (ret) { 246 dev_err(&hdev->pdev->dev, 247 "Get MAC pkt stats fail, status = %d.\n", ret); 248 249 return ret; 250 } 251 252 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) { 253 if (unlikely(i == 0)) { 254 desc_data = (__le64 *)(&desc[i].data[0]); 255 n = HCLGE_RTN_DATA_NUM - 2; 256 } else { 257 desc_data = (__le64 *)(&desc[i]); 258 n = HCLGE_RTN_DATA_NUM; 259 } 260 for (k = 0; k < n; k++) { 261 *data++ += le64_to_cpu(*desc_data); 262 desc_data++; 263 } 264 } 265 266 return 0; 267 } 268 269 static int hclge_tqps_update_stats(struct hnae3_handle *handle) 270 { 271 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 272 struct hclge_vport *vport = hclge_get_vport(handle); 273 struct hclge_dev *hdev = vport->back; 274 struct hnae3_queue *queue; 275 struct hclge_desc desc[1]; 276 struct hclge_tqp *tqp; 277 int ret, i; 278 279 for (i = 0; i < kinfo->num_tqps; i++) { 280 queue = handle->kinfo.tqp[i]; 281 tqp = container_of(queue, struct hclge_tqp, q); 282 /* command : HCLGE_OPC_QUERY_IGU_STAT */ 283 hclge_cmd_setup_basic_desc(&desc[0], 284 HCLGE_OPC_QUERY_RX_STATUS, 285 true); 286 287 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff)); 288 ret = hclge_cmd_send(&hdev->hw, desc, 1); 289 if (ret) { 290 dev_err(&hdev->pdev->dev, 291 "Query tqp stat fail, status = %d,queue = %d\n", 292 ret, i); 293 return ret; 294 } 295 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 296 le32_to_cpu(desc[0].data[1]); 297 } 298 299 for (i = 0; i < kinfo->num_tqps; i++) { 300 queue = handle->kinfo.tqp[i]; 301 tqp = container_of(queue, struct hclge_tqp, q); 302 /* command : HCLGE_OPC_QUERY_IGU_STAT */ 303 hclge_cmd_setup_basic_desc(&desc[0], 304 HCLGE_OPC_QUERY_TX_STATUS, 305 true); 306 307 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff)); 308 ret = hclge_cmd_send(&hdev->hw, desc, 1); 309 if (ret) { 310 dev_err(&hdev->pdev->dev, 311 "Query tqp stat fail, status = %d,queue = %d\n", 312 ret, i); 313 return ret; 314 } 315 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 316 le32_to_cpu(desc[0].data[1]); 317 } 318 319 return 0; 320 } 321 322 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 323 { 324 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 325 struct hclge_tqp *tqp; 326 u64 *buff = data; 327 int i; 328 329 for (i = 0; i < kinfo->num_tqps; i++) { 330 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q); 331 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 332 } 333 334 for (i = 0; i < kinfo->num_tqps; i++) { 335 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q); 336 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 337 } 338 339 return buff; 340 } 341 342 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset) 343 { 344 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 345 346 return kinfo->num_tqps * (2); 347 } 348 349 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 350 { 351 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 352 u8 *buff = data; 353 int i = 0; 354 355 for (i = 0; i < kinfo->num_tqps; i++) { 356 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i], 357 struct hclge_tqp, q); 358 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd", 359 tqp->index); 360 buff = buff + ETH_GSTRING_LEN; 361 } 362 363 for (i = 0; i < kinfo->num_tqps; i++) { 364 struct hclge_tqp *tqp = container_of(kinfo->tqp[i], 365 struct hclge_tqp, q); 366 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd", 367 tqp->index); 368 buff = buff + ETH_GSTRING_LEN; 369 } 370 371 return buff; 372 } 373 374 static u64 *hclge_comm_get_stats(void *comm_stats, 375 const struct hclge_comm_stats_str strs[], 376 int size, u64 *data) 377 { 378 u64 *buf = data; 379 u32 i; 380 381 for (i = 0; i < size; i++) 382 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset); 383 384 return buf + size; 385 } 386 387 static u8 *hclge_comm_get_strings(u32 stringset, 388 const struct hclge_comm_stats_str strs[], 389 int size, u8 *data) 390 { 391 char *buff = (char *)data; 392 u32 i; 393 394 if (stringset != ETH_SS_STATS) 395 return buff; 396 397 for (i = 0; i < size; i++) { 398 snprintf(buff, ETH_GSTRING_LEN, 399 strs[i].desc); 400 buff = buff + ETH_GSTRING_LEN; 401 } 402 403 return (u8 *)buff; 404 } 405 406 static void hclge_update_netstat(struct hclge_hw_stats *hw_stats, 407 struct net_device_stats *net_stats) 408 { 409 net_stats->tx_dropped = 0; 410 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num; 411 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num; 412 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num; 413 414 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num; 415 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num; 416 417 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num; 418 net_stats->rx_length_errors = 419 hw_stats->mac_stats.mac_rx_undersize_pkt_num; 420 net_stats->rx_length_errors += 421 hw_stats->mac_stats.mac_rx_oversize_pkt_num; 422 net_stats->rx_over_errors = 423 hw_stats->mac_stats.mac_rx_oversize_pkt_num; 424 } 425 426 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 427 { 428 struct hnae3_handle *handle; 429 int status; 430 431 handle = &hdev->vport[0].nic; 432 if (handle->client) { 433 status = hclge_tqps_update_stats(handle); 434 if (status) { 435 dev_err(&hdev->pdev->dev, 436 "Update TQPS stats fail, status = %d.\n", 437 status); 438 } 439 } 440 441 status = hclge_mac_update_stats(hdev); 442 if (status) 443 dev_err(&hdev->pdev->dev, 444 "Update MAC stats fail, status = %d.\n", status); 445 446 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats); 447 } 448 449 static void hclge_update_stats(struct hnae3_handle *handle, 450 struct net_device_stats *net_stats) 451 { 452 struct hclge_vport *vport = hclge_get_vport(handle); 453 struct hclge_dev *hdev = vport->back; 454 struct hclge_hw_stats *hw_stats = &hdev->hw_stats; 455 int status; 456 457 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 458 return; 459 460 status = hclge_mac_update_stats(hdev); 461 if (status) 462 dev_err(&hdev->pdev->dev, 463 "Update MAC stats fail, status = %d.\n", 464 status); 465 466 status = hclge_tqps_update_stats(handle); 467 if (status) 468 dev_err(&hdev->pdev->dev, 469 "Update TQPS stats fail, status = %d.\n", 470 status); 471 472 hclge_update_netstat(hw_stats, net_stats); 473 474 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 475 } 476 477 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 478 { 479 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK |\ 480 HNAE3_SUPPORT_PHY_LOOPBACK |\ 481 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK |\ 482 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) 483 484 struct hclge_vport *vport = hclge_get_vport(handle); 485 struct hclge_dev *hdev = vport->back; 486 int count = 0; 487 488 /* Loopback test support rules: 489 * mac: only GE mode support 490 * serdes: all mac mode will support include GE/XGE/LGE/CGE 491 * phy: only support when phy device exist on board 492 */ 493 if (stringset == ETH_SS_TEST) { 494 /* clear loopback bit flags at first */ 495 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 496 if (hdev->pdev->revision >= 0x21 || 497 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 498 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 499 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 500 count += 1; 501 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; 502 } 503 504 count += 2; 505 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; 506 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; 507 } else if (stringset == ETH_SS_STATS) { 508 count = ARRAY_SIZE(g_mac_stats_string) + 509 hclge_tqps_get_sset_count(handle, stringset); 510 } 511 512 return count; 513 } 514 515 static void hclge_get_strings(struct hnae3_handle *handle, 516 u32 stringset, 517 u8 *data) 518 { 519 u8 *p = (char *)data; 520 int size; 521 522 if (stringset == ETH_SS_STATS) { 523 size = ARRAY_SIZE(g_mac_stats_string); 524 p = hclge_comm_get_strings(stringset, 525 g_mac_stats_string, 526 size, 527 p); 528 p = hclge_tqps_get_strings(handle, p); 529 } else if (stringset == ETH_SS_TEST) { 530 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { 531 memcpy(p, 532 hns3_nic_test_strs[HNAE3_LOOP_APP], 533 ETH_GSTRING_LEN); 534 p += ETH_GSTRING_LEN; 535 } 536 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { 537 memcpy(p, 538 hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES], 539 ETH_GSTRING_LEN); 540 p += ETH_GSTRING_LEN; 541 } 542 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { 543 memcpy(p, 544 hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES], 545 ETH_GSTRING_LEN); 546 p += ETH_GSTRING_LEN; 547 } 548 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 549 memcpy(p, 550 hns3_nic_test_strs[HNAE3_LOOP_PHY], 551 ETH_GSTRING_LEN); 552 p += ETH_GSTRING_LEN; 553 } 554 } 555 } 556 557 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 558 { 559 struct hclge_vport *vport = hclge_get_vport(handle); 560 struct hclge_dev *hdev = vport->back; 561 u64 *p; 562 563 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats, 564 g_mac_stats_string, 565 ARRAY_SIZE(g_mac_stats_string), 566 data); 567 p = hclge_tqps_get_stats(handle, p); 568 } 569 570 static int hclge_parse_func_status(struct hclge_dev *hdev, 571 struct hclge_func_status_cmd *status) 572 { 573 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 574 return -EINVAL; 575 576 /* Set the pf to main pf */ 577 if (status->pf_state & HCLGE_PF_STATE_MAIN) 578 hdev->flag |= HCLGE_FLAG_MAIN; 579 else 580 hdev->flag &= ~HCLGE_FLAG_MAIN; 581 582 return 0; 583 } 584 585 static int hclge_query_function_status(struct hclge_dev *hdev) 586 { 587 struct hclge_func_status_cmd *req; 588 struct hclge_desc desc; 589 int timeout = 0; 590 int ret; 591 592 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 593 req = (struct hclge_func_status_cmd *)desc.data; 594 595 do { 596 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 597 if (ret) { 598 dev_err(&hdev->pdev->dev, 599 "query function status failed %d.\n", 600 ret); 601 602 return ret; 603 } 604 605 /* Check pf reset is done */ 606 if (req->pf_state) 607 break; 608 usleep_range(1000, 2000); 609 } while (timeout++ < 5); 610 611 ret = hclge_parse_func_status(hdev, req); 612 613 return ret; 614 } 615 616 static int hclge_query_pf_resource(struct hclge_dev *hdev) 617 { 618 struct hclge_pf_res_cmd *req; 619 struct hclge_desc desc; 620 int ret; 621 622 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 623 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 624 if (ret) { 625 dev_err(&hdev->pdev->dev, 626 "query pf resource failed %d.\n", ret); 627 return ret; 628 } 629 630 req = (struct hclge_pf_res_cmd *)desc.data; 631 hdev->num_tqps = __le16_to_cpu(req->tqp_num); 632 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 633 634 if (hnae3_dev_roce_supported(hdev)) { 635 hdev->roce_base_msix_offset = 636 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee), 637 HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S); 638 hdev->num_roce_msi = 639 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number), 640 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); 641 642 /* PF should have NIC vectors and Roce vectors, 643 * NIC vectors are queued before Roce vectors. 644 */ 645 hdev->num_msi = hdev->num_roce_msi + 646 hdev->roce_base_msix_offset; 647 } else { 648 hdev->num_msi = 649 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number), 650 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); 651 } 652 653 return 0; 654 } 655 656 static int hclge_parse_speed(int speed_cmd, int *speed) 657 { 658 switch (speed_cmd) { 659 case 6: 660 *speed = HCLGE_MAC_SPEED_10M; 661 break; 662 case 7: 663 *speed = HCLGE_MAC_SPEED_100M; 664 break; 665 case 0: 666 *speed = HCLGE_MAC_SPEED_1G; 667 break; 668 case 1: 669 *speed = HCLGE_MAC_SPEED_10G; 670 break; 671 case 2: 672 *speed = HCLGE_MAC_SPEED_25G; 673 break; 674 case 3: 675 *speed = HCLGE_MAC_SPEED_40G; 676 break; 677 case 4: 678 *speed = HCLGE_MAC_SPEED_50G; 679 break; 680 case 5: 681 *speed = HCLGE_MAC_SPEED_100G; 682 break; 683 default: 684 return -EINVAL; 685 } 686 687 return 0; 688 } 689 690 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 691 u8 speed_ability) 692 { 693 unsigned long *supported = hdev->hw.mac.supported; 694 695 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 696 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 697 supported); 698 699 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 700 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 701 supported); 702 703 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 704 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 705 supported); 706 707 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 708 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 709 supported); 710 711 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 712 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 713 supported); 714 715 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported); 716 set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 717 } 718 719 static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability) 720 { 721 u8 media_type = hdev->hw.mac.media_type; 722 723 if (media_type != HNAE3_MEDIA_TYPE_FIBER) 724 return; 725 726 hclge_parse_fiber_link_mode(hdev, speed_ability); 727 } 728 729 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 730 { 731 struct hclge_cfg_param_cmd *req; 732 u64 mac_addr_tmp_high; 733 u64 mac_addr_tmp; 734 int i; 735 736 req = (struct hclge_cfg_param_cmd *)desc[0].data; 737 738 /* get the configuration */ 739 cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 740 HCLGE_CFG_VMDQ_M, 741 HCLGE_CFG_VMDQ_S); 742 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 743 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 744 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 745 HCLGE_CFG_TQP_DESC_N_M, 746 HCLGE_CFG_TQP_DESC_N_S); 747 748 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 749 HCLGE_CFG_PHY_ADDR_M, 750 HCLGE_CFG_PHY_ADDR_S); 751 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 752 HCLGE_CFG_MEDIA_TP_M, 753 HCLGE_CFG_MEDIA_TP_S); 754 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 755 HCLGE_CFG_RX_BUF_LEN_M, 756 HCLGE_CFG_RX_BUF_LEN_S); 757 /* get mac_address */ 758 mac_addr_tmp = __le32_to_cpu(req->param[2]); 759 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 760 HCLGE_CFG_MAC_ADDR_H_M, 761 HCLGE_CFG_MAC_ADDR_H_S); 762 763 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 764 765 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 766 HCLGE_CFG_DEFAULT_SPEED_M, 767 HCLGE_CFG_DEFAULT_SPEED_S); 768 cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 769 HCLGE_CFG_RSS_SIZE_M, 770 HCLGE_CFG_RSS_SIZE_S); 771 772 for (i = 0; i < ETH_ALEN; i++) 773 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 774 775 req = (struct hclge_cfg_param_cmd *)desc[1].data; 776 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 777 778 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 779 HCLGE_CFG_SPEED_ABILITY_M, 780 HCLGE_CFG_SPEED_ABILITY_S); 781 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]), 782 HCLGE_CFG_UMV_TBL_SPACE_M, 783 HCLGE_CFG_UMV_TBL_SPACE_S); 784 if (!cfg->umv_space) 785 cfg->umv_space = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 786 } 787 788 /* hclge_get_cfg: query the static parameter from flash 789 * @hdev: pointer to struct hclge_dev 790 * @hcfg: the config structure to be getted 791 */ 792 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 793 { 794 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 795 struct hclge_cfg_param_cmd *req; 796 int i, ret; 797 798 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 799 u32 offset = 0; 800 801 req = (struct hclge_cfg_param_cmd *)desc[i].data; 802 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 803 true); 804 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 805 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 806 /* Len should be united by 4 bytes when send to hardware */ 807 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 808 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 809 req->offset = cpu_to_le32(offset); 810 } 811 812 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 813 if (ret) { 814 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 815 return ret; 816 } 817 818 hclge_parse_cfg(hcfg, desc); 819 820 return 0; 821 } 822 823 static int hclge_get_cap(struct hclge_dev *hdev) 824 { 825 int ret; 826 827 ret = hclge_query_function_status(hdev); 828 if (ret) { 829 dev_err(&hdev->pdev->dev, 830 "query function status error %d.\n", ret); 831 return ret; 832 } 833 834 /* get pf resource */ 835 ret = hclge_query_pf_resource(hdev); 836 if (ret) 837 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret); 838 839 return ret; 840 } 841 842 static int hclge_configure(struct hclge_dev *hdev) 843 { 844 struct hclge_cfg cfg; 845 int ret, i; 846 847 ret = hclge_get_cfg(hdev, &cfg); 848 if (ret) { 849 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret); 850 return ret; 851 } 852 853 hdev->num_vmdq_vport = cfg.vmdq_vport_num; 854 hdev->base_tqp_pid = 0; 855 hdev->rss_size_max = cfg.rss_size_max; 856 hdev->rx_buf_len = cfg.rx_buf_len; 857 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 858 hdev->hw.mac.media_type = cfg.media_type; 859 hdev->hw.mac.phy_addr = cfg.phy_addr; 860 hdev->num_desc = cfg.tqp_desc_num; 861 hdev->tm_info.num_pg = 1; 862 hdev->tc_max = cfg.tc_num; 863 hdev->tm_info.hw_pfc_map = 0; 864 hdev->wanted_umv_size = cfg.umv_space; 865 866 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 867 if (ret) { 868 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret); 869 return ret; 870 } 871 872 hclge_parse_link_mode(hdev, cfg.speed_ability); 873 874 if ((hdev->tc_max > HNAE3_MAX_TC) || 875 (hdev->tc_max < 1)) { 876 dev_warn(&hdev->pdev->dev, "TC num = %d.\n", 877 hdev->tc_max); 878 hdev->tc_max = 1; 879 } 880 881 /* Dev does not support DCB */ 882 if (!hnae3_dev_dcb_supported(hdev)) { 883 hdev->tc_max = 1; 884 hdev->pfc_max = 0; 885 } else { 886 hdev->pfc_max = hdev->tc_max; 887 } 888 889 hdev->tm_info.num_tc = hdev->tc_max; 890 891 /* Currently not support uncontiuous tc */ 892 for (i = 0; i < hdev->tm_info.num_tc; i++) 893 hnae3_set_bit(hdev->hw_tc_map, i, 1); 894 895 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 896 897 return ret; 898 } 899 900 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min, 901 int tso_mss_max) 902 { 903 struct hclge_cfg_tso_status_cmd *req; 904 struct hclge_desc desc; 905 u16 tso_mss; 906 907 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 908 909 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 910 911 tso_mss = 0; 912 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, 913 HCLGE_TSO_MSS_MIN_S, tso_mss_min); 914 req->tso_mss_min = cpu_to_le16(tso_mss); 915 916 tso_mss = 0; 917 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, 918 HCLGE_TSO_MSS_MIN_S, tso_mss_max); 919 req->tso_mss_max = cpu_to_le16(tso_mss); 920 921 return hclge_cmd_send(&hdev->hw, &desc, 1); 922 } 923 924 static int hclge_alloc_tqps(struct hclge_dev *hdev) 925 { 926 struct hclge_tqp *tqp; 927 int i; 928 929 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 930 sizeof(struct hclge_tqp), GFP_KERNEL); 931 if (!hdev->htqp) 932 return -ENOMEM; 933 934 tqp = hdev->htqp; 935 936 for (i = 0; i < hdev->num_tqps; i++) { 937 tqp->dev = &hdev->pdev->dev; 938 tqp->index = i; 939 940 tqp->q.ae_algo = &ae_algo; 941 tqp->q.buf_size = hdev->rx_buf_len; 942 tqp->q.desc_num = hdev->num_desc; 943 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET + 944 i * HCLGE_TQP_REG_SIZE; 945 946 tqp++; 947 } 948 949 return 0; 950 } 951 952 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 953 u16 tqp_pid, u16 tqp_vid, bool is_pf) 954 { 955 struct hclge_tqp_map_cmd *req; 956 struct hclge_desc desc; 957 int ret; 958 959 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 960 961 req = (struct hclge_tqp_map_cmd *)desc.data; 962 req->tqp_id = cpu_to_le16(tqp_pid); 963 req->tqp_vf = func_id; 964 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B | 965 1 << HCLGE_TQP_MAP_EN_B; 966 req->tqp_vid = cpu_to_le16(tqp_vid); 967 968 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 969 if (ret) 970 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 971 972 return ret; 973 } 974 975 static int hclge_assign_tqp(struct hclge_vport *vport) 976 { 977 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 978 struct hclge_dev *hdev = vport->back; 979 int i, alloced; 980 981 for (i = 0, alloced = 0; i < hdev->num_tqps && 982 alloced < kinfo->num_tqps; i++) { 983 if (!hdev->htqp[i].alloced) { 984 hdev->htqp[i].q.handle = &vport->nic; 985 hdev->htqp[i].q.tqp_index = alloced; 986 hdev->htqp[i].q.desc_num = kinfo->num_desc; 987 kinfo->tqp[alloced] = &hdev->htqp[i].q; 988 hdev->htqp[i].alloced = true; 989 alloced++; 990 } 991 } 992 vport->alloc_tqps = kinfo->num_tqps; 993 994 return 0; 995 } 996 997 static int hclge_knic_setup(struct hclge_vport *vport, 998 u16 num_tqps, u16 num_desc) 999 { 1000 struct hnae3_handle *nic = &vport->nic; 1001 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1002 struct hclge_dev *hdev = vport->back; 1003 int i, ret; 1004 1005 kinfo->num_desc = num_desc; 1006 kinfo->rx_buf_len = hdev->rx_buf_len; 1007 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc); 1008 kinfo->rss_size 1009 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc); 1010 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc; 1011 1012 for (i = 0; i < HNAE3_MAX_TC; i++) { 1013 if (hdev->hw_tc_map & BIT(i)) { 1014 kinfo->tc_info[i].enable = true; 1015 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size; 1016 kinfo->tc_info[i].tqp_count = kinfo->rss_size; 1017 kinfo->tc_info[i].tc = i; 1018 } else { 1019 /* Set to default queue if TC is disable */ 1020 kinfo->tc_info[i].enable = false; 1021 kinfo->tc_info[i].tqp_offset = 0; 1022 kinfo->tc_info[i].tqp_count = 1; 1023 kinfo->tc_info[i].tc = 0; 1024 } 1025 } 1026 1027 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 1028 sizeof(struct hnae3_queue *), GFP_KERNEL); 1029 if (!kinfo->tqp) 1030 return -ENOMEM; 1031 1032 ret = hclge_assign_tqp(vport); 1033 if (ret) 1034 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1035 1036 return ret; 1037 } 1038 1039 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1040 struct hclge_vport *vport) 1041 { 1042 struct hnae3_handle *nic = &vport->nic; 1043 struct hnae3_knic_private_info *kinfo; 1044 u16 i; 1045 1046 kinfo = &nic->kinfo; 1047 for (i = 0; i < kinfo->num_tqps; i++) { 1048 struct hclge_tqp *q = 1049 container_of(kinfo->tqp[i], struct hclge_tqp, q); 1050 bool is_pf; 1051 int ret; 1052 1053 is_pf = !(vport->vport_id); 1054 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1055 i, is_pf); 1056 if (ret) 1057 return ret; 1058 } 1059 1060 return 0; 1061 } 1062 1063 static int hclge_map_tqp(struct hclge_dev *hdev) 1064 { 1065 struct hclge_vport *vport = hdev->vport; 1066 u16 i, num_vport; 1067 1068 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1; 1069 for (i = 0; i < num_vport; i++) { 1070 int ret; 1071 1072 ret = hclge_map_tqp_to_vport(hdev, vport); 1073 if (ret) 1074 return ret; 1075 1076 vport++; 1077 } 1078 1079 return 0; 1080 } 1081 1082 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps) 1083 { 1084 /* this would be initialized later */ 1085 } 1086 1087 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1088 { 1089 struct hnae3_handle *nic = &vport->nic; 1090 struct hclge_dev *hdev = vport->back; 1091 int ret; 1092 1093 nic->pdev = hdev->pdev; 1094 nic->ae_algo = &ae_algo; 1095 nic->numa_node_mask = hdev->numa_node_mask; 1096 1097 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) { 1098 ret = hclge_knic_setup(vport, num_tqps, hdev->num_desc); 1099 if (ret) { 1100 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", 1101 ret); 1102 return ret; 1103 } 1104 } else { 1105 hclge_unic_setup(vport, num_tqps); 1106 } 1107 1108 return 0; 1109 } 1110 1111 static int hclge_alloc_vport(struct hclge_dev *hdev) 1112 { 1113 struct pci_dev *pdev = hdev->pdev; 1114 struct hclge_vport *vport; 1115 u32 tqp_main_vport; 1116 u32 tqp_per_vport; 1117 int num_vport, i; 1118 int ret; 1119 1120 /* We need to alloc a vport for main NIC of PF */ 1121 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1; 1122 1123 if (hdev->num_tqps < num_vport) { 1124 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)", 1125 hdev->num_tqps, num_vport); 1126 return -EINVAL; 1127 } 1128 1129 /* Alloc the same number of TQPs for every vport */ 1130 tqp_per_vport = hdev->num_tqps / num_vport; 1131 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1132 1133 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1134 GFP_KERNEL); 1135 if (!vport) 1136 return -ENOMEM; 1137 1138 hdev->vport = vport; 1139 hdev->num_alloc_vport = num_vport; 1140 1141 if (IS_ENABLED(CONFIG_PCI_IOV)) 1142 hdev->num_alloc_vfs = hdev->num_req_vfs; 1143 1144 for (i = 0; i < num_vport; i++) { 1145 vport->back = hdev; 1146 vport->vport_id = i; 1147 1148 if (i == 0) 1149 ret = hclge_vport_setup(vport, tqp_main_vport); 1150 else 1151 ret = hclge_vport_setup(vport, tqp_per_vport); 1152 if (ret) { 1153 dev_err(&pdev->dev, 1154 "vport setup failed for vport %d, %d\n", 1155 i, ret); 1156 return ret; 1157 } 1158 1159 vport++; 1160 } 1161 1162 return 0; 1163 } 1164 1165 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1166 struct hclge_pkt_buf_alloc *buf_alloc) 1167 { 1168 /* TX buffer size is unit by 128 byte */ 1169 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1170 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1171 struct hclge_tx_buff_alloc_cmd *req; 1172 struct hclge_desc desc; 1173 int ret; 1174 u8 i; 1175 1176 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1177 1178 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1179 for (i = 0; i < HCLGE_TC_NUM; i++) { 1180 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1181 1182 req->tx_pkt_buff[i] = 1183 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1184 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1185 } 1186 1187 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1188 if (ret) 1189 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1190 ret); 1191 1192 return ret; 1193 } 1194 1195 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1196 struct hclge_pkt_buf_alloc *buf_alloc) 1197 { 1198 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1199 1200 if (ret) 1201 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1202 1203 return ret; 1204 } 1205 1206 static int hclge_get_tc_num(struct hclge_dev *hdev) 1207 { 1208 int i, cnt = 0; 1209 1210 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1211 if (hdev->hw_tc_map & BIT(i)) 1212 cnt++; 1213 return cnt; 1214 } 1215 1216 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev) 1217 { 1218 int i, cnt = 0; 1219 1220 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1221 if (hdev->hw_tc_map & BIT(i) && 1222 hdev->tm_info.hw_pfc_map & BIT(i)) 1223 cnt++; 1224 return cnt; 1225 } 1226 1227 /* Get the number of pfc enabled TCs, which have private buffer */ 1228 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1229 struct hclge_pkt_buf_alloc *buf_alloc) 1230 { 1231 struct hclge_priv_buf *priv; 1232 int i, cnt = 0; 1233 1234 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1235 priv = &buf_alloc->priv_buf[i]; 1236 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1237 priv->enable) 1238 cnt++; 1239 } 1240 1241 return cnt; 1242 } 1243 1244 /* Get the number of pfc disabled TCs, which have private buffer */ 1245 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1246 struct hclge_pkt_buf_alloc *buf_alloc) 1247 { 1248 struct hclge_priv_buf *priv; 1249 int i, cnt = 0; 1250 1251 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1252 priv = &buf_alloc->priv_buf[i]; 1253 if (hdev->hw_tc_map & BIT(i) && 1254 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 1255 priv->enable) 1256 cnt++; 1257 } 1258 1259 return cnt; 1260 } 1261 1262 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1263 { 1264 struct hclge_priv_buf *priv; 1265 u32 rx_priv = 0; 1266 int i; 1267 1268 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1269 priv = &buf_alloc->priv_buf[i]; 1270 if (priv->enable) 1271 rx_priv += priv->buf_size; 1272 } 1273 return rx_priv; 1274 } 1275 1276 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1277 { 1278 u32 i, total_tx_size = 0; 1279 1280 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1281 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 1282 1283 return total_tx_size; 1284 } 1285 1286 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 1287 struct hclge_pkt_buf_alloc *buf_alloc, 1288 u32 rx_all) 1289 { 1290 u32 shared_buf_min, shared_buf_tc, shared_std; 1291 int tc_num, pfc_enable_num; 1292 u32 shared_buf; 1293 u32 rx_priv; 1294 int i; 1295 1296 tc_num = hclge_get_tc_num(hdev); 1297 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev); 1298 1299 if (hnae3_dev_dcb_supported(hdev)) 1300 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV; 1301 else 1302 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV; 1303 1304 shared_buf_tc = pfc_enable_num * hdev->mps + 1305 (tc_num - pfc_enable_num) * hdev->mps / 2 + 1306 hdev->mps; 1307 shared_std = max_t(u32, shared_buf_min, shared_buf_tc); 1308 1309 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 1310 if (rx_all <= rx_priv + shared_std) 1311 return false; 1312 1313 shared_buf = rx_all - rx_priv; 1314 buf_alloc->s_buf.buf_size = shared_buf; 1315 buf_alloc->s_buf.self.high = shared_buf; 1316 buf_alloc->s_buf.self.low = 2 * hdev->mps; 1317 1318 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1319 if ((hdev->hw_tc_map & BIT(i)) && 1320 (hdev->tm_info.hw_pfc_map & BIT(i))) { 1321 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps; 1322 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps; 1323 } else { 1324 buf_alloc->s_buf.tc_thrd[i].low = 0; 1325 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps; 1326 } 1327 } 1328 1329 return true; 1330 } 1331 1332 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 1333 struct hclge_pkt_buf_alloc *buf_alloc) 1334 { 1335 u32 i, total_size; 1336 1337 total_size = hdev->pkt_buf_size; 1338 1339 /* alloc tx buffer for all enabled tc */ 1340 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1341 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 1342 1343 if (total_size < HCLGE_DEFAULT_TX_BUF) 1344 return -ENOMEM; 1345 1346 if (hdev->hw_tc_map & BIT(i)) 1347 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 1348 else 1349 priv->tx_buf_size = 0; 1350 1351 total_size -= priv->tx_buf_size; 1352 } 1353 1354 return 0; 1355 } 1356 1357 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 1358 * @hdev: pointer to struct hclge_dev 1359 * @buf_alloc: pointer to buffer calculation data 1360 * @return: 0: calculate sucessful, negative: fail 1361 */ 1362 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 1363 struct hclge_pkt_buf_alloc *buf_alloc) 1364 { 1365 #define HCLGE_BUF_SIZE_UNIT 128 1366 u32 rx_all = hdev->pkt_buf_size, aligned_mps; 1367 int no_pfc_priv_num, pfc_priv_num; 1368 struct hclge_priv_buf *priv; 1369 int i; 1370 1371 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT); 1372 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 1373 1374 /* When DCB is not supported, rx private 1375 * buffer is not allocated. 1376 */ 1377 if (!hnae3_dev_dcb_supported(hdev)) { 1378 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1379 return -ENOMEM; 1380 1381 return 0; 1382 } 1383 1384 /* step 1, try to alloc private buffer for all enabled tc */ 1385 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1386 priv = &buf_alloc->priv_buf[i]; 1387 if (hdev->hw_tc_map & BIT(i)) { 1388 priv->enable = 1; 1389 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 1390 priv->wl.low = aligned_mps; 1391 priv->wl.high = priv->wl.low + aligned_mps; 1392 priv->buf_size = priv->wl.high + 1393 HCLGE_DEFAULT_DV; 1394 } else { 1395 priv->wl.low = 0; 1396 priv->wl.high = 2 * aligned_mps; 1397 priv->buf_size = priv->wl.high; 1398 } 1399 } else { 1400 priv->enable = 0; 1401 priv->wl.low = 0; 1402 priv->wl.high = 0; 1403 priv->buf_size = 0; 1404 } 1405 } 1406 1407 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1408 return 0; 1409 1410 /* step 2, try to decrease the buffer size of 1411 * no pfc TC's private buffer 1412 */ 1413 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1414 priv = &buf_alloc->priv_buf[i]; 1415 1416 priv->enable = 0; 1417 priv->wl.low = 0; 1418 priv->wl.high = 0; 1419 priv->buf_size = 0; 1420 1421 if (!(hdev->hw_tc_map & BIT(i))) 1422 continue; 1423 1424 priv->enable = 1; 1425 1426 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 1427 priv->wl.low = 128; 1428 priv->wl.high = priv->wl.low + aligned_mps; 1429 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV; 1430 } else { 1431 priv->wl.low = 0; 1432 priv->wl.high = aligned_mps; 1433 priv->buf_size = priv->wl.high; 1434 } 1435 } 1436 1437 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1438 return 0; 1439 1440 /* step 3, try to reduce the number of pfc disabled TCs, 1441 * which have private buffer 1442 */ 1443 /* get the total no pfc enable TC number, which have private buffer */ 1444 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 1445 1446 /* let the last to be cleared first */ 1447 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 1448 priv = &buf_alloc->priv_buf[i]; 1449 1450 if (hdev->hw_tc_map & BIT(i) && 1451 !(hdev->tm_info.hw_pfc_map & BIT(i))) { 1452 /* Clear the no pfc TC private buffer */ 1453 priv->wl.low = 0; 1454 priv->wl.high = 0; 1455 priv->buf_size = 0; 1456 priv->enable = 0; 1457 no_pfc_priv_num--; 1458 } 1459 1460 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 1461 no_pfc_priv_num == 0) 1462 break; 1463 } 1464 1465 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1466 return 0; 1467 1468 /* step 4, try to reduce the number of pfc enabled TCs 1469 * which have private buffer. 1470 */ 1471 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 1472 1473 /* let the last to be cleared first */ 1474 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 1475 priv = &buf_alloc->priv_buf[i]; 1476 1477 if (hdev->hw_tc_map & BIT(i) && 1478 hdev->tm_info.hw_pfc_map & BIT(i)) { 1479 /* Reduce the number of pfc TC with private buffer */ 1480 priv->wl.low = 0; 1481 priv->enable = 0; 1482 priv->wl.high = 0; 1483 priv->buf_size = 0; 1484 pfc_priv_num--; 1485 } 1486 1487 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 1488 pfc_priv_num == 0) 1489 break; 1490 } 1491 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1492 return 0; 1493 1494 return -ENOMEM; 1495 } 1496 1497 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 1498 struct hclge_pkt_buf_alloc *buf_alloc) 1499 { 1500 struct hclge_rx_priv_buff_cmd *req; 1501 struct hclge_desc desc; 1502 int ret; 1503 int i; 1504 1505 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 1506 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 1507 1508 /* Alloc private buffer TCs */ 1509 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1510 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 1511 1512 req->buf_num[i] = 1513 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 1514 req->buf_num[i] |= 1515 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 1516 } 1517 1518 req->shared_buf = 1519 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 1520 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 1521 1522 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1523 if (ret) 1524 dev_err(&hdev->pdev->dev, 1525 "rx private buffer alloc cmd failed %d\n", ret); 1526 1527 return ret; 1528 } 1529 1530 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 1531 struct hclge_pkt_buf_alloc *buf_alloc) 1532 { 1533 struct hclge_rx_priv_wl_buf *req; 1534 struct hclge_priv_buf *priv; 1535 struct hclge_desc desc[2]; 1536 int i, j; 1537 int ret; 1538 1539 for (i = 0; i < 2; i++) { 1540 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 1541 false); 1542 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 1543 1544 /* The first descriptor set the NEXT bit to 1 */ 1545 if (i == 0) 1546 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1547 else 1548 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1549 1550 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 1551 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 1552 1553 priv = &buf_alloc->priv_buf[idx]; 1554 req->tc_wl[j].high = 1555 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 1556 req->tc_wl[j].high |= 1557 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 1558 req->tc_wl[j].low = 1559 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 1560 req->tc_wl[j].low |= 1561 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 1562 } 1563 } 1564 1565 /* Send 2 descriptor at one time */ 1566 ret = hclge_cmd_send(&hdev->hw, desc, 2); 1567 if (ret) 1568 dev_err(&hdev->pdev->dev, 1569 "rx private waterline config cmd failed %d\n", 1570 ret); 1571 return ret; 1572 } 1573 1574 static int hclge_common_thrd_config(struct hclge_dev *hdev, 1575 struct hclge_pkt_buf_alloc *buf_alloc) 1576 { 1577 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 1578 struct hclge_rx_com_thrd *req; 1579 struct hclge_desc desc[2]; 1580 struct hclge_tc_thrd *tc; 1581 int i, j; 1582 int ret; 1583 1584 for (i = 0; i < 2; i++) { 1585 hclge_cmd_setup_basic_desc(&desc[i], 1586 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 1587 req = (struct hclge_rx_com_thrd *)&desc[i].data; 1588 1589 /* The first descriptor set the NEXT bit to 1 */ 1590 if (i == 0) 1591 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1592 else 1593 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1594 1595 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 1596 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 1597 1598 req->com_thrd[j].high = 1599 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 1600 req->com_thrd[j].high |= 1601 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 1602 req->com_thrd[j].low = 1603 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 1604 req->com_thrd[j].low |= 1605 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 1606 } 1607 } 1608 1609 /* Send 2 descriptors at one time */ 1610 ret = hclge_cmd_send(&hdev->hw, desc, 2); 1611 if (ret) 1612 dev_err(&hdev->pdev->dev, 1613 "common threshold config cmd failed %d\n", ret); 1614 return ret; 1615 } 1616 1617 static int hclge_common_wl_config(struct hclge_dev *hdev, 1618 struct hclge_pkt_buf_alloc *buf_alloc) 1619 { 1620 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 1621 struct hclge_rx_com_wl *req; 1622 struct hclge_desc desc; 1623 int ret; 1624 1625 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 1626 1627 req = (struct hclge_rx_com_wl *)desc.data; 1628 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 1629 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 1630 1631 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 1632 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 1633 1634 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1635 if (ret) 1636 dev_err(&hdev->pdev->dev, 1637 "common waterline config cmd failed %d\n", ret); 1638 1639 return ret; 1640 } 1641 1642 int hclge_buffer_alloc(struct hclge_dev *hdev) 1643 { 1644 struct hclge_pkt_buf_alloc *pkt_buf; 1645 int ret; 1646 1647 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 1648 if (!pkt_buf) 1649 return -ENOMEM; 1650 1651 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 1652 if (ret) { 1653 dev_err(&hdev->pdev->dev, 1654 "could not calc tx buffer size for all TCs %d\n", ret); 1655 goto out; 1656 } 1657 1658 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 1659 if (ret) { 1660 dev_err(&hdev->pdev->dev, 1661 "could not alloc tx buffers %d\n", ret); 1662 goto out; 1663 } 1664 1665 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 1666 if (ret) { 1667 dev_err(&hdev->pdev->dev, 1668 "could not calc rx priv buffer size for all TCs %d\n", 1669 ret); 1670 goto out; 1671 } 1672 1673 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 1674 if (ret) { 1675 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 1676 ret); 1677 goto out; 1678 } 1679 1680 if (hnae3_dev_dcb_supported(hdev)) { 1681 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 1682 if (ret) { 1683 dev_err(&hdev->pdev->dev, 1684 "could not configure rx private waterline %d\n", 1685 ret); 1686 goto out; 1687 } 1688 1689 ret = hclge_common_thrd_config(hdev, pkt_buf); 1690 if (ret) { 1691 dev_err(&hdev->pdev->dev, 1692 "could not configure common threshold %d\n", 1693 ret); 1694 goto out; 1695 } 1696 } 1697 1698 ret = hclge_common_wl_config(hdev, pkt_buf); 1699 if (ret) 1700 dev_err(&hdev->pdev->dev, 1701 "could not configure common waterline %d\n", ret); 1702 1703 out: 1704 kfree(pkt_buf); 1705 return ret; 1706 } 1707 1708 static int hclge_init_roce_base_info(struct hclge_vport *vport) 1709 { 1710 struct hnae3_handle *roce = &vport->roce; 1711 struct hnae3_handle *nic = &vport->nic; 1712 1713 roce->rinfo.num_vectors = vport->back->num_roce_msi; 1714 1715 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors || 1716 vport->back->num_msi_left == 0) 1717 return -EINVAL; 1718 1719 roce->rinfo.base_vector = vport->back->roce_base_vector; 1720 1721 roce->rinfo.netdev = nic->kinfo.netdev; 1722 roce->rinfo.roce_io_base = vport->back->hw.io_base; 1723 1724 roce->pdev = nic->pdev; 1725 roce->ae_algo = nic->ae_algo; 1726 roce->numa_node_mask = nic->numa_node_mask; 1727 1728 return 0; 1729 } 1730 1731 static int hclge_init_msi(struct hclge_dev *hdev) 1732 { 1733 struct pci_dev *pdev = hdev->pdev; 1734 int vectors; 1735 int i; 1736 1737 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 1738 PCI_IRQ_MSI | PCI_IRQ_MSIX); 1739 if (vectors < 0) { 1740 dev_err(&pdev->dev, 1741 "failed(%d) to allocate MSI/MSI-X vectors\n", 1742 vectors); 1743 return vectors; 1744 } 1745 if (vectors < hdev->num_msi) 1746 dev_warn(&hdev->pdev->dev, 1747 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 1748 hdev->num_msi, vectors); 1749 1750 hdev->num_msi = vectors; 1751 hdev->num_msi_left = vectors; 1752 hdev->base_msi_vector = pdev->irq; 1753 hdev->roce_base_vector = hdev->base_msi_vector + 1754 hdev->roce_base_msix_offset; 1755 1756 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 1757 sizeof(u16), GFP_KERNEL); 1758 if (!hdev->vector_status) { 1759 pci_free_irq_vectors(pdev); 1760 return -ENOMEM; 1761 } 1762 1763 for (i = 0; i < hdev->num_msi; i++) 1764 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 1765 1766 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 1767 sizeof(int), GFP_KERNEL); 1768 if (!hdev->vector_irq) { 1769 pci_free_irq_vectors(pdev); 1770 return -ENOMEM; 1771 } 1772 1773 return 0; 1774 } 1775 1776 static u8 hclge_check_speed_dup(u8 duplex, int speed) 1777 { 1778 1779 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 1780 duplex = HCLGE_MAC_FULL; 1781 1782 return duplex; 1783 } 1784 1785 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 1786 u8 duplex) 1787 { 1788 struct hclge_config_mac_speed_dup_cmd *req; 1789 struct hclge_desc desc; 1790 int ret; 1791 1792 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 1793 1794 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 1795 1796 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex); 1797 1798 switch (speed) { 1799 case HCLGE_MAC_SPEED_10M: 1800 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 1801 HCLGE_CFG_SPEED_S, 6); 1802 break; 1803 case HCLGE_MAC_SPEED_100M: 1804 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 1805 HCLGE_CFG_SPEED_S, 7); 1806 break; 1807 case HCLGE_MAC_SPEED_1G: 1808 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 1809 HCLGE_CFG_SPEED_S, 0); 1810 break; 1811 case HCLGE_MAC_SPEED_10G: 1812 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 1813 HCLGE_CFG_SPEED_S, 1); 1814 break; 1815 case HCLGE_MAC_SPEED_25G: 1816 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 1817 HCLGE_CFG_SPEED_S, 2); 1818 break; 1819 case HCLGE_MAC_SPEED_40G: 1820 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 1821 HCLGE_CFG_SPEED_S, 3); 1822 break; 1823 case HCLGE_MAC_SPEED_50G: 1824 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 1825 HCLGE_CFG_SPEED_S, 4); 1826 break; 1827 case HCLGE_MAC_SPEED_100G: 1828 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 1829 HCLGE_CFG_SPEED_S, 5); 1830 break; 1831 default: 1832 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 1833 return -EINVAL; 1834 } 1835 1836 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 1837 1); 1838 1839 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1840 if (ret) { 1841 dev_err(&hdev->pdev->dev, 1842 "mac speed/duplex config cmd failed %d.\n", ret); 1843 return ret; 1844 } 1845 1846 return 0; 1847 } 1848 1849 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex) 1850 { 1851 int ret; 1852 1853 duplex = hclge_check_speed_dup(duplex, speed); 1854 if (hdev->hw.mac.speed == speed && hdev->hw.mac.duplex == duplex) 1855 return 0; 1856 1857 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex); 1858 if (ret) 1859 return ret; 1860 1861 hdev->hw.mac.speed = speed; 1862 hdev->hw.mac.duplex = duplex; 1863 1864 return 0; 1865 } 1866 1867 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 1868 u8 duplex) 1869 { 1870 struct hclge_vport *vport = hclge_get_vport(handle); 1871 struct hclge_dev *hdev = vport->back; 1872 1873 return hclge_cfg_mac_speed_dup(hdev, speed, duplex); 1874 } 1875 1876 static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed, 1877 u8 *duplex) 1878 { 1879 struct hclge_query_an_speed_dup_cmd *req; 1880 struct hclge_desc desc; 1881 int speed_tmp; 1882 int ret; 1883 1884 req = (struct hclge_query_an_speed_dup_cmd *)desc.data; 1885 1886 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true); 1887 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1888 if (ret) { 1889 dev_err(&hdev->pdev->dev, 1890 "mac speed/autoneg/duplex query cmd failed %d\n", 1891 ret); 1892 return ret; 1893 } 1894 1895 *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B); 1896 speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M, 1897 HCLGE_QUERY_SPEED_S); 1898 1899 ret = hclge_parse_speed(speed_tmp, speed); 1900 if (ret) 1901 dev_err(&hdev->pdev->dev, 1902 "could not parse speed(=%d), %d\n", speed_tmp, ret); 1903 1904 return ret; 1905 } 1906 1907 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 1908 { 1909 struct hclge_config_auto_neg_cmd *req; 1910 struct hclge_desc desc; 1911 u32 flag = 0; 1912 int ret; 1913 1914 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 1915 1916 req = (struct hclge_config_auto_neg_cmd *)desc.data; 1917 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable); 1918 req->cfg_an_cmd_flag = cpu_to_le32(flag); 1919 1920 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1921 if (ret) 1922 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 1923 ret); 1924 1925 return ret; 1926 } 1927 1928 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 1929 { 1930 struct hclge_vport *vport = hclge_get_vport(handle); 1931 struct hclge_dev *hdev = vport->back; 1932 1933 return hclge_set_autoneg_en(hdev, enable); 1934 } 1935 1936 static int hclge_get_autoneg(struct hnae3_handle *handle) 1937 { 1938 struct hclge_vport *vport = hclge_get_vport(handle); 1939 struct hclge_dev *hdev = vport->back; 1940 struct phy_device *phydev = hdev->hw.mac.phydev; 1941 1942 if (phydev) 1943 return phydev->autoneg; 1944 1945 return hdev->hw.mac.autoneg; 1946 } 1947 1948 static int hclge_mac_init(struct hclge_dev *hdev) 1949 { 1950 struct hnae3_handle *handle = &hdev->vport[0].nic; 1951 struct net_device *netdev = handle->kinfo.netdev; 1952 struct hclge_mac *mac = &hdev->hw.mac; 1953 int mtu; 1954 int ret; 1955 1956 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 1957 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed, 1958 hdev->hw.mac.duplex); 1959 if (ret) { 1960 dev_err(&hdev->pdev->dev, 1961 "Config mac speed dup fail ret=%d\n", ret); 1962 return ret; 1963 } 1964 1965 mac->link = 0; 1966 1967 if (netdev) 1968 mtu = netdev->mtu; 1969 else 1970 mtu = ETH_DATA_LEN; 1971 1972 ret = hclge_set_mtu(handle, mtu); 1973 if (ret) 1974 dev_err(&hdev->pdev->dev, 1975 "set mtu failed ret=%d\n", ret); 1976 1977 return ret; 1978 } 1979 1980 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 1981 { 1982 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) 1983 schedule_work(&hdev->mbx_service_task); 1984 } 1985 1986 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 1987 { 1988 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 1989 schedule_work(&hdev->rst_service_task); 1990 } 1991 1992 static void hclge_task_schedule(struct hclge_dev *hdev) 1993 { 1994 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) && 1995 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 1996 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state)) 1997 (void)schedule_work(&hdev->service_task); 1998 } 1999 2000 static int hclge_get_mac_link_status(struct hclge_dev *hdev) 2001 { 2002 struct hclge_link_status_cmd *req; 2003 struct hclge_desc desc; 2004 int link_status; 2005 int ret; 2006 2007 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 2008 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2009 if (ret) { 2010 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 2011 ret); 2012 return ret; 2013 } 2014 2015 req = (struct hclge_link_status_cmd *)desc.data; 2016 link_status = req->status & HCLGE_LINK_STATUS_UP_M; 2017 2018 return !!link_status; 2019 } 2020 2021 static int hclge_get_mac_phy_link(struct hclge_dev *hdev) 2022 { 2023 int mac_state; 2024 int link_stat; 2025 2026 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) 2027 return 0; 2028 2029 mac_state = hclge_get_mac_link_status(hdev); 2030 2031 if (hdev->hw.mac.phydev) { 2032 if (hdev->hw.mac.phydev->state == PHY_RUNNING) 2033 link_stat = mac_state & 2034 hdev->hw.mac.phydev->link; 2035 else 2036 link_stat = 0; 2037 2038 } else { 2039 link_stat = mac_state; 2040 } 2041 2042 return !!link_stat; 2043 } 2044 2045 static void hclge_update_link_status(struct hclge_dev *hdev) 2046 { 2047 struct hnae3_client *client = hdev->nic_client; 2048 struct hnae3_handle *handle; 2049 int state; 2050 int i; 2051 2052 if (!client) 2053 return; 2054 state = hclge_get_mac_phy_link(hdev); 2055 if (state != hdev->hw.mac.link) { 2056 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 2057 handle = &hdev->vport[i].nic; 2058 client->ops->link_status_change(handle, state); 2059 } 2060 hdev->hw.mac.link = state; 2061 } 2062 } 2063 2064 static int hclge_update_speed_duplex(struct hclge_dev *hdev) 2065 { 2066 struct hclge_mac mac = hdev->hw.mac; 2067 u8 duplex; 2068 int speed; 2069 int ret; 2070 2071 /* get the speed and duplex as autoneg'result from mac cmd when phy 2072 * doesn't exit. 2073 */ 2074 if (mac.phydev || !mac.autoneg) 2075 return 0; 2076 2077 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex); 2078 if (ret) { 2079 dev_err(&hdev->pdev->dev, 2080 "mac autoneg/speed/duplex query failed %d\n", ret); 2081 return ret; 2082 } 2083 2084 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex); 2085 if (ret) { 2086 dev_err(&hdev->pdev->dev, 2087 "mac speed/duplex config failed %d\n", ret); 2088 return ret; 2089 } 2090 2091 return 0; 2092 } 2093 2094 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle) 2095 { 2096 struct hclge_vport *vport = hclge_get_vport(handle); 2097 struct hclge_dev *hdev = vport->back; 2098 2099 return hclge_update_speed_duplex(hdev); 2100 } 2101 2102 static int hclge_get_status(struct hnae3_handle *handle) 2103 { 2104 struct hclge_vport *vport = hclge_get_vport(handle); 2105 struct hclge_dev *hdev = vport->back; 2106 2107 hclge_update_link_status(hdev); 2108 2109 return hdev->hw.mac.link; 2110 } 2111 2112 static void hclge_service_timer(struct timer_list *t) 2113 { 2114 struct hclge_dev *hdev = from_timer(hdev, t, service_timer); 2115 2116 mod_timer(&hdev->service_timer, jiffies + HZ); 2117 hdev->hw_stats.stats_timer++; 2118 hclge_task_schedule(hdev); 2119 } 2120 2121 static void hclge_service_complete(struct hclge_dev *hdev) 2122 { 2123 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state)); 2124 2125 /* Flush memory before next watchdog */ 2126 smp_mb__before_atomic(); 2127 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state); 2128 } 2129 2130 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 2131 { 2132 u32 rst_src_reg; 2133 u32 cmdq_src_reg; 2134 2135 /* fetch the events from their corresponding regs */ 2136 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 2137 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 2138 2139 /* Assumption: If by any chance reset and mailbox events are reported 2140 * together then we will only process reset event in this go and will 2141 * defer the processing of the mailbox events. Since, we would have not 2142 * cleared RX CMDQ event this time we would receive again another 2143 * interrupt from H/W just for the mailbox. 2144 */ 2145 2146 /* check for vector0 reset event sources */ 2147 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) { 2148 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state); 2149 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 2150 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 2151 return HCLGE_VECTOR0_EVENT_RST; 2152 } 2153 2154 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) { 2155 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state); 2156 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending); 2157 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B); 2158 return HCLGE_VECTOR0_EVENT_RST; 2159 } 2160 2161 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) { 2162 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); 2163 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 2164 return HCLGE_VECTOR0_EVENT_RST; 2165 } 2166 2167 /* check for vector0 mailbox(=CMDQ RX) event source */ 2168 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 2169 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 2170 *clearval = cmdq_src_reg; 2171 return HCLGE_VECTOR0_EVENT_MBX; 2172 } 2173 2174 return HCLGE_VECTOR0_EVENT_OTHER; 2175 } 2176 2177 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 2178 u32 regclr) 2179 { 2180 switch (event_type) { 2181 case HCLGE_VECTOR0_EVENT_RST: 2182 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 2183 break; 2184 case HCLGE_VECTOR0_EVENT_MBX: 2185 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 2186 break; 2187 default: 2188 break; 2189 } 2190 } 2191 2192 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 2193 { 2194 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 2195 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 2196 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 2197 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 2198 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 2199 } 2200 2201 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 2202 { 2203 writel(enable ? 1 : 0, vector->addr); 2204 } 2205 2206 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 2207 { 2208 struct hclge_dev *hdev = data; 2209 u32 event_cause; 2210 u32 clearval; 2211 2212 hclge_enable_vector(&hdev->misc_vector, false); 2213 event_cause = hclge_check_event_cause(hdev, &clearval); 2214 2215 /* vector 0 interrupt is shared with reset and mailbox source events.*/ 2216 switch (event_cause) { 2217 case HCLGE_VECTOR0_EVENT_RST: 2218 hclge_reset_task_schedule(hdev); 2219 break; 2220 case HCLGE_VECTOR0_EVENT_MBX: 2221 /* If we are here then, 2222 * 1. Either we are not handling any mbx task and we are not 2223 * scheduled as well 2224 * OR 2225 * 2. We could be handling a mbx task but nothing more is 2226 * scheduled. 2227 * In both cases, we should schedule mbx task as there are more 2228 * mbx messages reported by this interrupt. 2229 */ 2230 hclge_mbx_task_schedule(hdev); 2231 break; 2232 default: 2233 dev_warn(&hdev->pdev->dev, 2234 "received unknown or unhandled event of vector0\n"); 2235 break; 2236 } 2237 2238 /* clear the source of interrupt if it is not cause by reset */ 2239 if (event_cause == HCLGE_VECTOR0_EVENT_MBX) { 2240 hclge_clear_event_cause(hdev, event_cause, clearval); 2241 hclge_enable_vector(&hdev->misc_vector, true); 2242 } 2243 2244 return IRQ_HANDLED; 2245 } 2246 2247 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 2248 { 2249 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 2250 dev_warn(&hdev->pdev->dev, 2251 "vector(vector_id %d) has been freed.\n", vector_id); 2252 return; 2253 } 2254 2255 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 2256 hdev->num_msi_left += 1; 2257 hdev->num_msi_used -= 1; 2258 } 2259 2260 static void hclge_get_misc_vector(struct hclge_dev *hdev) 2261 { 2262 struct hclge_misc_vector *vector = &hdev->misc_vector; 2263 2264 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 2265 2266 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 2267 hdev->vector_status[0] = 0; 2268 2269 hdev->num_msi_left -= 1; 2270 hdev->num_msi_used += 1; 2271 } 2272 2273 static int hclge_misc_irq_init(struct hclge_dev *hdev) 2274 { 2275 int ret; 2276 2277 hclge_get_misc_vector(hdev); 2278 2279 /* this would be explicitly freed in the end */ 2280 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 2281 0, "hclge_misc", hdev); 2282 if (ret) { 2283 hclge_free_vector(hdev, 0); 2284 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 2285 hdev->misc_vector.vector_irq); 2286 } 2287 2288 return ret; 2289 } 2290 2291 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 2292 { 2293 free_irq(hdev->misc_vector.vector_irq, hdev); 2294 hclge_free_vector(hdev, 0); 2295 } 2296 2297 static int hclge_notify_client(struct hclge_dev *hdev, 2298 enum hnae3_reset_notify_type type) 2299 { 2300 struct hnae3_client *client = hdev->nic_client; 2301 u16 i; 2302 2303 if (!client->ops->reset_notify) 2304 return -EOPNOTSUPP; 2305 2306 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 2307 struct hnae3_handle *handle = &hdev->vport[i].nic; 2308 int ret; 2309 2310 ret = client->ops->reset_notify(handle, type); 2311 if (ret) 2312 return ret; 2313 } 2314 2315 return 0; 2316 } 2317 2318 static int hclge_reset_wait(struct hclge_dev *hdev) 2319 { 2320 #define HCLGE_RESET_WATI_MS 100 2321 #define HCLGE_RESET_WAIT_CNT 5 2322 u32 val, reg, reg_bit; 2323 u32 cnt = 0; 2324 2325 switch (hdev->reset_type) { 2326 case HNAE3_GLOBAL_RESET: 2327 reg = HCLGE_GLOBAL_RESET_REG; 2328 reg_bit = HCLGE_GLOBAL_RESET_BIT; 2329 break; 2330 case HNAE3_CORE_RESET: 2331 reg = HCLGE_GLOBAL_RESET_REG; 2332 reg_bit = HCLGE_CORE_RESET_BIT; 2333 break; 2334 case HNAE3_FUNC_RESET: 2335 reg = HCLGE_FUN_RST_ING; 2336 reg_bit = HCLGE_FUN_RST_ING_B; 2337 break; 2338 default: 2339 dev_err(&hdev->pdev->dev, 2340 "Wait for unsupported reset type: %d\n", 2341 hdev->reset_type); 2342 return -EINVAL; 2343 } 2344 2345 val = hclge_read_dev(&hdev->hw, reg); 2346 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 2347 msleep(HCLGE_RESET_WATI_MS); 2348 val = hclge_read_dev(&hdev->hw, reg); 2349 cnt++; 2350 } 2351 2352 if (cnt >= HCLGE_RESET_WAIT_CNT) { 2353 dev_warn(&hdev->pdev->dev, 2354 "Wait for reset timeout: %d\n", hdev->reset_type); 2355 return -EBUSY; 2356 } 2357 2358 return 0; 2359 } 2360 2361 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 2362 { 2363 struct hclge_desc desc; 2364 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 2365 int ret; 2366 2367 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 2368 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 2369 req->fun_reset_vfid = func_id; 2370 2371 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2372 if (ret) 2373 dev_err(&hdev->pdev->dev, 2374 "send function reset cmd fail, status =%d\n", ret); 2375 2376 return ret; 2377 } 2378 2379 static void hclge_do_reset(struct hclge_dev *hdev) 2380 { 2381 struct pci_dev *pdev = hdev->pdev; 2382 u32 val; 2383 2384 switch (hdev->reset_type) { 2385 case HNAE3_GLOBAL_RESET: 2386 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 2387 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 2388 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 2389 dev_info(&pdev->dev, "Global Reset requested\n"); 2390 break; 2391 case HNAE3_CORE_RESET: 2392 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 2393 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1); 2394 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 2395 dev_info(&pdev->dev, "Core Reset requested\n"); 2396 break; 2397 case HNAE3_FUNC_RESET: 2398 dev_info(&pdev->dev, "PF Reset requested\n"); 2399 hclge_func_reset_cmd(hdev, 0); 2400 /* schedule again to check later */ 2401 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); 2402 hclge_reset_task_schedule(hdev); 2403 break; 2404 default: 2405 dev_warn(&pdev->dev, 2406 "Unsupported reset type: %d\n", hdev->reset_type); 2407 break; 2408 } 2409 } 2410 2411 static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev, 2412 unsigned long *addr) 2413 { 2414 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 2415 2416 /* return the highest priority reset level amongst all */ 2417 if (test_bit(HNAE3_GLOBAL_RESET, addr)) 2418 rst_level = HNAE3_GLOBAL_RESET; 2419 else if (test_bit(HNAE3_CORE_RESET, addr)) 2420 rst_level = HNAE3_CORE_RESET; 2421 else if (test_bit(HNAE3_IMP_RESET, addr)) 2422 rst_level = HNAE3_IMP_RESET; 2423 else if (test_bit(HNAE3_FUNC_RESET, addr)) 2424 rst_level = HNAE3_FUNC_RESET; 2425 2426 /* now, clear all other resets */ 2427 clear_bit(HNAE3_GLOBAL_RESET, addr); 2428 clear_bit(HNAE3_CORE_RESET, addr); 2429 clear_bit(HNAE3_IMP_RESET, addr); 2430 clear_bit(HNAE3_FUNC_RESET, addr); 2431 2432 return rst_level; 2433 } 2434 2435 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 2436 { 2437 u32 clearval = 0; 2438 2439 switch (hdev->reset_type) { 2440 case HNAE3_IMP_RESET: 2441 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 2442 break; 2443 case HNAE3_GLOBAL_RESET: 2444 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 2445 break; 2446 case HNAE3_CORE_RESET: 2447 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B); 2448 break; 2449 default: 2450 break; 2451 } 2452 2453 if (!clearval) 2454 return; 2455 2456 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval); 2457 hclge_enable_vector(&hdev->misc_vector, true); 2458 } 2459 2460 static void hclge_reset(struct hclge_dev *hdev) 2461 { 2462 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2463 struct hnae3_handle *handle; 2464 2465 /* Initialize ae_dev reset status as well, in case enet layer wants to 2466 * know if device is undergoing reset 2467 */ 2468 ae_dev->reset_type = hdev->reset_type; 2469 /* perform reset of the stack & ae device for a client */ 2470 handle = &hdev->vport[0].nic; 2471 rtnl_lock(); 2472 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2473 rtnl_unlock(); 2474 2475 if (!hclge_reset_wait(hdev)) { 2476 rtnl_lock(); 2477 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 2478 hclge_reset_ae_dev(hdev->ae_dev); 2479 hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 2480 2481 hclge_clear_reset_cause(hdev); 2482 } else { 2483 rtnl_lock(); 2484 /* schedule again to check pending resets later */ 2485 set_bit(hdev->reset_type, &hdev->reset_pending); 2486 hclge_reset_task_schedule(hdev); 2487 } 2488 2489 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2490 handle->last_reset_time = jiffies; 2491 rtnl_unlock(); 2492 ae_dev->reset_type = HNAE3_NONE_RESET; 2493 } 2494 2495 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) 2496 { 2497 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2498 struct hclge_dev *hdev = ae_dev->priv; 2499 2500 /* We might end up getting called broadly because of 2 below cases: 2501 * 1. Recoverable error was conveyed through APEI and only way to bring 2502 * normalcy is to reset. 2503 * 2. A new reset request from the stack due to timeout 2504 * 2505 * For the first case,error event might not have ae handle available. 2506 * check if this is a new reset request and we are not here just because 2507 * last reset attempt did not succeed and watchdog hit us again. We will 2508 * know this if last reset request did not occur very recently (watchdog 2509 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 2510 * In case of new request we reset the "reset level" to PF reset. 2511 * And if it is a repeat reset request of the most recent one then we 2512 * want to make sure we throttle the reset request. Therefore, we will 2513 * not allow it again before 3*HZ times. 2514 */ 2515 if (!handle) 2516 handle = &hdev->vport[0].nic; 2517 2518 if (time_before(jiffies, (handle->last_reset_time + 3 * HZ))) 2519 return; 2520 else if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ))) 2521 handle->reset_level = HNAE3_FUNC_RESET; 2522 2523 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d", 2524 handle->reset_level); 2525 2526 /* request reset & schedule reset task */ 2527 set_bit(handle->reset_level, &hdev->reset_request); 2528 hclge_reset_task_schedule(hdev); 2529 2530 if (handle->reset_level < HNAE3_GLOBAL_RESET) 2531 handle->reset_level++; 2532 } 2533 2534 static void hclge_reset_subtask(struct hclge_dev *hdev) 2535 { 2536 /* check if there is any ongoing reset in the hardware. This status can 2537 * be checked from reset_pending. If there is then, we need to wait for 2538 * hardware to complete reset. 2539 * a. If we are able to figure out in reasonable time that hardware 2540 * has fully resetted then, we can proceed with driver, client 2541 * reset. 2542 * b. else, we can come back later to check this status so re-sched 2543 * now. 2544 */ 2545 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending); 2546 if (hdev->reset_type != HNAE3_NONE_RESET) 2547 hclge_reset(hdev); 2548 2549 /* check if we got any *new* reset requests to be honored */ 2550 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request); 2551 if (hdev->reset_type != HNAE3_NONE_RESET) 2552 hclge_do_reset(hdev); 2553 2554 hdev->reset_type = HNAE3_NONE_RESET; 2555 } 2556 2557 static void hclge_reset_service_task(struct work_struct *work) 2558 { 2559 struct hclge_dev *hdev = 2560 container_of(work, struct hclge_dev, rst_service_task); 2561 2562 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 2563 return; 2564 2565 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 2566 2567 hclge_reset_subtask(hdev); 2568 2569 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 2570 } 2571 2572 static void hclge_mailbox_service_task(struct work_struct *work) 2573 { 2574 struct hclge_dev *hdev = 2575 container_of(work, struct hclge_dev, mbx_service_task); 2576 2577 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 2578 return; 2579 2580 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 2581 2582 hclge_mbx_handler(hdev); 2583 2584 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 2585 } 2586 2587 static void hclge_service_task(struct work_struct *work) 2588 { 2589 struct hclge_dev *hdev = 2590 container_of(work, struct hclge_dev, service_task); 2591 2592 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) { 2593 hclge_update_stats_for_all(hdev); 2594 hdev->hw_stats.stats_timer = 0; 2595 } 2596 2597 hclge_update_speed_duplex(hdev); 2598 hclge_update_link_status(hdev); 2599 hclge_service_complete(hdev); 2600 } 2601 2602 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 2603 { 2604 /* VF handle has no client */ 2605 if (!handle->client) 2606 return container_of(handle, struct hclge_vport, nic); 2607 else if (handle->client->type == HNAE3_CLIENT_ROCE) 2608 return container_of(handle, struct hclge_vport, roce); 2609 else 2610 return container_of(handle, struct hclge_vport, nic); 2611 } 2612 2613 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 2614 struct hnae3_vector_info *vector_info) 2615 { 2616 struct hclge_vport *vport = hclge_get_vport(handle); 2617 struct hnae3_vector_info *vector = vector_info; 2618 struct hclge_dev *hdev = vport->back; 2619 int alloc = 0; 2620 int i, j; 2621 2622 vector_num = min(hdev->num_msi_left, vector_num); 2623 2624 for (j = 0; j < vector_num; j++) { 2625 for (i = 1; i < hdev->num_msi; i++) { 2626 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 2627 vector->vector = pci_irq_vector(hdev->pdev, i); 2628 vector->io_addr = hdev->hw.io_base + 2629 HCLGE_VECTOR_REG_BASE + 2630 (i - 1) * HCLGE_VECTOR_REG_OFFSET + 2631 vport->vport_id * 2632 HCLGE_VECTOR_VF_OFFSET; 2633 hdev->vector_status[i] = vport->vport_id; 2634 hdev->vector_irq[i] = vector->vector; 2635 2636 vector++; 2637 alloc++; 2638 2639 break; 2640 } 2641 } 2642 } 2643 hdev->num_msi_left -= alloc; 2644 hdev->num_msi_used += alloc; 2645 2646 return alloc; 2647 } 2648 2649 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 2650 { 2651 int i; 2652 2653 for (i = 0; i < hdev->num_msi; i++) 2654 if (vector == hdev->vector_irq[i]) 2655 return i; 2656 2657 return -EINVAL; 2658 } 2659 2660 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 2661 { 2662 struct hclge_vport *vport = hclge_get_vport(handle); 2663 struct hclge_dev *hdev = vport->back; 2664 int vector_id; 2665 2666 vector_id = hclge_get_vector_index(hdev, vector); 2667 if (vector_id < 0) { 2668 dev_err(&hdev->pdev->dev, 2669 "Get vector index fail. vector_id =%d\n", vector_id); 2670 return vector_id; 2671 } 2672 2673 hclge_free_vector(hdev, vector_id); 2674 2675 return 0; 2676 } 2677 2678 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle) 2679 { 2680 return HCLGE_RSS_KEY_SIZE; 2681 } 2682 2683 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle) 2684 { 2685 return HCLGE_RSS_IND_TBL_SIZE; 2686 } 2687 2688 static int hclge_set_rss_algo_key(struct hclge_dev *hdev, 2689 const u8 hfunc, const u8 *key) 2690 { 2691 struct hclge_rss_config_cmd *req; 2692 struct hclge_desc desc; 2693 int key_offset; 2694 int key_size; 2695 int ret; 2696 2697 req = (struct hclge_rss_config_cmd *)desc.data; 2698 2699 for (key_offset = 0; key_offset < 3; key_offset++) { 2700 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, 2701 false); 2702 2703 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK); 2704 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B); 2705 2706 if (key_offset == 2) 2707 key_size = 2708 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2; 2709 else 2710 key_size = HCLGE_RSS_HASH_KEY_NUM; 2711 2712 memcpy(req->hash_key, 2713 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size); 2714 2715 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2716 if (ret) { 2717 dev_err(&hdev->pdev->dev, 2718 "Configure RSS config fail, status = %d\n", 2719 ret); 2720 return ret; 2721 } 2722 } 2723 return 0; 2724 } 2725 2726 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir) 2727 { 2728 struct hclge_rss_indirection_table_cmd *req; 2729 struct hclge_desc desc; 2730 int i, j; 2731 int ret; 2732 2733 req = (struct hclge_rss_indirection_table_cmd *)desc.data; 2734 2735 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) { 2736 hclge_cmd_setup_basic_desc 2737 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false); 2738 2739 req->start_table_index = 2740 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE); 2741 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK); 2742 2743 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++) 2744 req->rss_result[j] = 2745 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j]; 2746 2747 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2748 if (ret) { 2749 dev_err(&hdev->pdev->dev, 2750 "Configure rss indir table fail,status = %d\n", 2751 ret); 2752 return ret; 2753 } 2754 } 2755 return 0; 2756 } 2757 2758 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid, 2759 u16 *tc_size, u16 *tc_offset) 2760 { 2761 struct hclge_rss_tc_mode_cmd *req; 2762 struct hclge_desc desc; 2763 int ret; 2764 int i; 2765 2766 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false); 2767 req = (struct hclge_rss_tc_mode_cmd *)desc.data; 2768 2769 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2770 u16 mode = 0; 2771 2772 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1)); 2773 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M, 2774 HCLGE_RSS_TC_SIZE_S, tc_size[i]); 2775 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M, 2776 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]); 2777 2778 req->rss_tc_mode[i] = cpu_to_le16(mode); 2779 } 2780 2781 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2782 if (ret) 2783 dev_err(&hdev->pdev->dev, 2784 "Configure rss tc mode fail, status = %d\n", ret); 2785 2786 return ret; 2787 } 2788 2789 static void hclge_get_rss_type(struct hclge_vport *vport) 2790 { 2791 if (vport->rss_tuple_sets.ipv4_tcp_en || 2792 vport->rss_tuple_sets.ipv4_udp_en || 2793 vport->rss_tuple_sets.ipv4_sctp_en || 2794 vport->rss_tuple_sets.ipv6_tcp_en || 2795 vport->rss_tuple_sets.ipv6_udp_en || 2796 vport->rss_tuple_sets.ipv6_sctp_en) 2797 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L4; 2798 else if (vport->rss_tuple_sets.ipv4_fragment_en || 2799 vport->rss_tuple_sets.ipv6_fragment_en) 2800 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L3; 2801 else 2802 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_NONE; 2803 } 2804 2805 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev) 2806 { 2807 struct hclge_rss_input_tuple_cmd *req; 2808 struct hclge_desc desc; 2809 int ret; 2810 2811 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false); 2812 2813 req = (struct hclge_rss_input_tuple_cmd *)desc.data; 2814 2815 /* Get the tuple cfg from pf */ 2816 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en; 2817 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en; 2818 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en; 2819 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en; 2820 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en; 2821 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en; 2822 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en; 2823 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en; 2824 hclge_get_rss_type(&hdev->vport[0]); 2825 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2826 if (ret) 2827 dev_err(&hdev->pdev->dev, 2828 "Configure rss input fail, status = %d\n", ret); 2829 return ret; 2830 } 2831 2832 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 2833 u8 *key, u8 *hfunc) 2834 { 2835 struct hclge_vport *vport = hclge_get_vport(handle); 2836 int i; 2837 2838 /* Get hash algorithm */ 2839 if (hfunc) { 2840 switch (vport->rss_algo) { 2841 case HCLGE_RSS_HASH_ALGO_TOEPLITZ: 2842 *hfunc = ETH_RSS_HASH_TOP; 2843 break; 2844 case HCLGE_RSS_HASH_ALGO_SIMPLE: 2845 *hfunc = ETH_RSS_HASH_XOR; 2846 break; 2847 default: 2848 *hfunc = ETH_RSS_HASH_UNKNOWN; 2849 break; 2850 } 2851 } 2852 2853 /* Get the RSS Key required by the user */ 2854 if (key) 2855 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE); 2856 2857 /* Get indirect table */ 2858 if (indir) 2859 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) 2860 indir[i] = vport->rss_indirection_tbl[i]; 2861 2862 return 0; 2863 } 2864 2865 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 2866 const u8 *key, const u8 hfunc) 2867 { 2868 struct hclge_vport *vport = hclge_get_vport(handle); 2869 struct hclge_dev *hdev = vport->back; 2870 u8 hash_algo; 2871 int ret, i; 2872 2873 /* Set the RSS Hash Key if specififed by the user */ 2874 if (key) { 2875 switch (hfunc) { 2876 case ETH_RSS_HASH_TOP: 2877 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ; 2878 break; 2879 case ETH_RSS_HASH_XOR: 2880 hash_algo = HCLGE_RSS_HASH_ALGO_SIMPLE; 2881 break; 2882 case ETH_RSS_HASH_NO_CHANGE: 2883 hash_algo = vport->rss_algo; 2884 break; 2885 default: 2886 return -EINVAL; 2887 } 2888 2889 ret = hclge_set_rss_algo_key(hdev, hash_algo, key); 2890 if (ret) 2891 return ret; 2892 2893 /* Update the shadow RSS key with user specified qids */ 2894 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE); 2895 vport->rss_algo = hash_algo; 2896 } 2897 2898 /* Update the shadow RSS table with user specified qids */ 2899 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) 2900 vport->rss_indirection_tbl[i] = indir[i]; 2901 2902 /* Update the hardware */ 2903 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl); 2904 } 2905 2906 static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 2907 { 2908 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0; 2909 2910 if (nfc->data & RXH_L4_B_2_3) 2911 hash_sets |= HCLGE_D_PORT_BIT; 2912 else 2913 hash_sets &= ~HCLGE_D_PORT_BIT; 2914 2915 if (nfc->data & RXH_IP_SRC) 2916 hash_sets |= HCLGE_S_IP_BIT; 2917 else 2918 hash_sets &= ~HCLGE_S_IP_BIT; 2919 2920 if (nfc->data & RXH_IP_DST) 2921 hash_sets |= HCLGE_D_IP_BIT; 2922 else 2923 hash_sets &= ~HCLGE_D_IP_BIT; 2924 2925 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 2926 hash_sets |= HCLGE_V_TAG_BIT; 2927 2928 return hash_sets; 2929 } 2930 2931 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 2932 struct ethtool_rxnfc *nfc) 2933 { 2934 struct hclge_vport *vport = hclge_get_vport(handle); 2935 struct hclge_dev *hdev = vport->back; 2936 struct hclge_rss_input_tuple_cmd *req; 2937 struct hclge_desc desc; 2938 u8 tuple_sets; 2939 int ret; 2940 2941 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2942 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2943 return -EINVAL; 2944 2945 req = (struct hclge_rss_input_tuple_cmd *)desc.data; 2946 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false); 2947 2948 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en; 2949 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en; 2950 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en; 2951 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en; 2952 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en; 2953 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en; 2954 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en; 2955 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en; 2956 2957 tuple_sets = hclge_get_rss_hash_bits(nfc); 2958 switch (nfc->flow_type) { 2959 case TCP_V4_FLOW: 2960 req->ipv4_tcp_en = tuple_sets; 2961 break; 2962 case TCP_V6_FLOW: 2963 req->ipv6_tcp_en = tuple_sets; 2964 break; 2965 case UDP_V4_FLOW: 2966 req->ipv4_udp_en = tuple_sets; 2967 break; 2968 case UDP_V6_FLOW: 2969 req->ipv6_udp_en = tuple_sets; 2970 break; 2971 case SCTP_V4_FLOW: 2972 req->ipv4_sctp_en = tuple_sets; 2973 break; 2974 case SCTP_V6_FLOW: 2975 if ((nfc->data & RXH_L4_B_0_1) || 2976 (nfc->data & RXH_L4_B_2_3)) 2977 return -EINVAL; 2978 2979 req->ipv6_sctp_en = tuple_sets; 2980 break; 2981 case IPV4_FLOW: 2982 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; 2983 break; 2984 case IPV6_FLOW: 2985 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; 2986 break; 2987 default: 2988 return -EINVAL; 2989 } 2990 2991 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2992 if (ret) { 2993 dev_err(&hdev->pdev->dev, 2994 "Set rss tuple fail, status = %d\n", ret); 2995 return ret; 2996 } 2997 2998 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 2999 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 3000 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 3001 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 3002 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 3003 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 3004 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 3005 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 3006 hclge_get_rss_type(vport); 3007 return 0; 3008 } 3009 3010 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 3011 struct ethtool_rxnfc *nfc) 3012 { 3013 struct hclge_vport *vport = hclge_get_vport(handle); 3014 u8 tuple_sets; 3015 3016 nfc->data = 0; 3017 3018 switch (nfc->flow_type) { 3019 case TCP_V4_FLOW: 3020 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en; 3021 break; 3022 case UDP_V4_FLOW: 3023 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en; 3024 break; 3025 case TCP_V6_FLOW: 3026 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en; 3027 break; 3028 case UDP_V6_FLOW: 3029 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en; 3030 break; 3031 case SCTP_V4_FLOW: 3032 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en; 3033 break; 3034 case SCTP_V6_FLOW: 3035 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en; 3036 break; 3037 case IPV4_FLOW: 3038 case IPV6_FLOW: 3039 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT; 3040 break; 3041 default: 3042 return -EINVAL; 3043 } 3044 3045 if (!tuple_sets) 3046 return 0; 3047 3048 if (tuple_sets & HCLGE_D_PORT_BIT) 3049 nfc->data |= RXH_L4_B_2_3; 3050 if (tuple_sets & HCLGE_S_PORT_BIT) 3051 nfc->data |= RXH_L4_B_0_1; 3052 if (tuple_sets & HCLGE_D_IP_BIT) 3053 nfc->data |= RXH_IP_DST; 3054 if (tuple_sets & HCLGE_S_IP_BIT) 3055 nfc->data |= RXH_IP_SRC; 3056 3057 return 0; 3058 } 3059 3060 static int hclge_get_tc_size(struct hnae3_handle *handle) 3061 { 3062 struct hclge_vport *vport = hclge_get_vport(handle); 3063 struct hclge_dev *hdev = vport->back; 3064 3065 return hdev->rss_size_max; 3066 } 3067 3068 int hclge_rss_init_hw(struct hclge_dev *hdev) 3069 { 3070 struct hclge_vport *vport = hdev->vport; 3071 u8 *rss_indir = vport[0].rss_indirection_tbl; 3072 u16 rss_size = vport[0].alloc_rss_size; 3073 u8 *key = vport[0].rss_hash_key; 3074 u8 hfunc = vport[0].rss_algo; 3075 u16 tc_offset[HCLGE_MAX_TC_NUM]; 3076 u16 tc_valid[HCLGE_MAX_TC_NUM]; 3077 u16 tc_size[HCLGE_MAX_TC_NUM]; 3078 u16 roundup_size; 3079 int i, ret; 3080 3081 ret = hclge_set_rss_indir_table(hdev, rss_indir); 3082 if (ret) 3083 return ret; 3084 3085 ret = hclge_set_rss_algo_key(hdev, hfunc, key); 3086 if (ret) 3087 return ret; 3088 3089 ret = hclge_set_rss_input_tuple(hdev); 3090 if (ret) 3091 return ret; 3092 3093 /* Each TC have the same queue size, and tc_size set to hardware is 3094 * the log2 of roundup power of two of rss_size, the acutal queue 3095 * size is limited by indirection table. 3096 */ 3097 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) { 3098 dev_err(&hdev->pdev->dev, 3099 "Configure rss tc size failed, invalid TC_SIZE = %d\n", 3100 rss_size); 3101 return -EINVAL; 3102 } 3103 3104 roundup_size = roundup_pow_of_two(rss_size); 3105 roundup_size = ilog2(roundup_size); 3106 3107 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 3108 tc_valid[i] = 0; 3109 3110 if (!(hdev->hw_tc_map & BIT(i))) 3111 continue; 3112 3113 tc_valid[i] = 1; 3114 tc_size[i] = roundup_size; 3115 tc_offset[i] = rss_size * i; 3116 } 3117 3118 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset); 3119 } 3120 3121 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev) 3122 { 3123 struct hclge_vport *vport = hdev->vport; 3124 int i, j; 3125 3126 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) { 3127 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) 3128 vport[j].rss_indirection_tbl[i] = 3129 i % vport[j].alloc_rss_size; 3130 } 3131 } 3132 3133 static void hclge_rss_init_cfg(struct hclge_dev *hdev) 3134 { 3135 struct hclge_vport *vport = hdev->vport; 3136 int i; 3137 3138 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 3139 vport[i].rss_tuple_sets.ipv4_tcp_en = 3140 HCLGE_RSS_INPUT_TUPLE_OTHER; 3141 vport[i].rss_tuple_sets.ipv4_udp_en = 3142 HCLGE_RSS_INPUT_TUPLE_OTHER; 3143 vport[i].rss_tuple_sets.ipv4_sctp_en = 3144 HCLGE_RSS_INPUT_TUPLE_SCTP; 3145 vport[i].rss_tuple_sets.ipv4_fragment_en = 3146 HCLGE_RSS_INPUT_TUPLE_OTHER; 3147 vport[i].rss_tuple_sets.ipv6_tcp_en = 3148 HCLGE_RSS_INPUT_TUPLE_OTHER; 3149 vport[i].rss_tuple_sets.ipv6_udp_en = 3150 HCLGE_RSS_INPUT_TUPLE_OTHER; 3151 vport[i].rss_tuple_sets.ipv6_sctp_en = 3152 HCLGE_RSS_INPUT_TUPLE_SCTP; 3153 vport[i].rss_tuple_sets.ipv6_fragment_en = 3154 HCLGE_RSS_INPUT_TUPLE_OTHER; 3155 3156 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ; 3157 3158 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE); 3159 } 3160 3161 hclge_rss_indir_init_cfg(hdev); 3162 } 3163 3164 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 3165 int vector_id, bool en, 3166 struct hnae3_ring_chain_node *ring_chain) 3167 { 3168 struct hclge_dev *hdev = vport->back; 3169 struct hnae3_ring_chain_node *node; 3170 struct hclge_desc desc; 3171 struct hclge_ctrl_vector_chain_cmd *req 3172 = (struct hclge_ctrl_vector_chain_cmd *)desc.data; 3173 enum hclge_cmd_status status; 3174 enum hclge_opcode_type op; 3175 u16 tqp_type_and_id; 3176 int i; 3177 3178 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 3179 hclge_cmd_setup_basic_desc(&desc, op, false); 3180 req->int_vector_id = vector_id; 3181 3182 i = 0; 3183 for (node = ring_chain; node; node = node->next) { 3184 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 3185 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 3186 HCLGE_INT_TYPE_S, 3187 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 3188 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 3189 HCLGE_TQP_ID_S, node->tqp_index); 3190 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 3191 HCLGE_INT_GL_IDX_S, 3192 hnae3_get_field(node->int_gl_idx, 3193 HNAE3_RING_GL_IDX_M, 3194 HNAE3_RING_GL_IDX_S)); 3195 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 3196 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 3197 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 3198 req->vfid = vport->vport_id; 3199 3200 status = hclge_cmd_send(&hdev->hw, &desc, 1); 3201 if (status) { 3202 dev_err(&hdev->pdev->dev, 3203 "Map TQP fail, status is %d.\n", 3204 status); 3205 return -EIO; 3206 } 3207 i = 0; 3208 3209 hclge_cmd_setup_basic_desc(&desc, 3210 op, 3211 false); 3212 req->int_vector_id = vector_id; 3213 } 3214 } 3215 3216 if (i > 0) { 3217 req->int_cause_num = i; 3218 req->vfid = vport->vport_id; 3219 status = hclge_cmd_send(&hdev->hw, &desc, 1); 3220 if (status) { 3221 dev_err(&hdev->pdev->dev, 3222 "Map TQP fail, status is %d.\n", status); 3223 return -EIO; 3224 } 3225 } 3226 3227 return 0; 3228 } 3229 3230 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, 3231 int vector, 3232 struct hnae3_ring_chain_node *ring_chain) 3233 { 3234 struct hclge_vport *vport = hclge_get_vport(handle); 3235 struct hclge_dev *hdev = vport->back; 3236 int vector_id; 3237 3238 vector_id = hclge_get_vector_index(hdev, vector); 3239 if (vector_id < 0) { 3240 dev_err(&hdev->pdev->dev, 3241 "Get vector index fail. vector_id =%d\n", vector_id); 3242 return vector_id; 3243 } 3244 3245 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 3246 } 3247 3248 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, 3249 int vector, 3250 struct hnae3_ring_chain_node *ring_chain) 3251 { 3252 struct hclge_vport *vport = hclge_get_vport(handle); 3253 struct hclge_dev *hdev = vport->back; 3254 int vector_id, ret; 3255 3256 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 3257 return 0; 3258 3259 vector_id = hclge_get_vector_index(hdev, vector); 3260 if (vector_id < 0) { 3261 dev_err(&handle->pdev->dev, 3262 "Get vector index fail. ret =%d\n", vector_id); 3263 return vector_id; 3264 } 3265 3266 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 3267 if (ret) 3268 dev_err(&handle->pdev->dev, 3269 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 3270 vector_id, 3271 ret); 3272 3273 return ret; 3274 } 3275 3276 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, 3277 struct hclge_promisc_param *param) 3278 { 3279 struct hclge_promisc_cfg_cmd *req; 3280 struct hclge_desc desc; 3281 int ret; 3282 3283 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 3284 3285 req = (struct hclge_promisc_cfg_cmd *)desc.data; 3286 req->vf_id = param->vf_id; 3287 3288 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on 3289 * pdev revision(0x20), new revision support them. The 3290 * value of this two fields will not return error when driver 3291 * send command to fireware in revision(0x20). 3292 */ 3293 req->flag = (param->enable << HCLGE_PROMISC_EN_B) | 3294 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B; 3295 3296 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3297 if (ret) 3298 dev_err(&hdev->pdev->dev, 3299 "Set promisc mode fail, status is %d.\n", ret); 3300 3301 return ret; 3302 } 3303 3304 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc, 3305 bool en_mc, bool en_bc, int vport_id) 3306 { 3307 if (!param) 3308 return; 3309 3310 memset(param, 0, sizeof(struct hclge_promisc_param)); 3311 if (en_uc) 3312 param->enable = HCLGE_PROMISC_EN_UC; 3313 if (en_mc) 3314 param->enable |= HCLGE_PROMISC_EN_MC; 3315 if (en_bc) 3316 param->enable |= HCLGE_PROMISC_EN_BC; 3317 param->vf_id = vport_id; 3318 } 3319 3320 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 3321 bool en_mc_pmc) 3322 { 3323 struct hclge_vport *vport = hclge_get_vport(handle); 3324 struct hclge_dev *hdev = vport->back; 3325 struct hclge_promisc_param param; 3326 3327 hclge_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, true, 3328 vport->vport_id); 3329 return hclge_cmd_set_promisc_mode(hdev, ¶m); 3330 } 3331 3332 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode) 3333 { 3334 struct hclge_get_fd_mode_cmd *req; 3335 struct hclge_desc desc; 3336 int ret; 3337 3338 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true); 3339 3340 req = (struct hclge_get_fd_mode_cmd *)desc.data; 3341 3342 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3343 if (ret) { 3344 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret); 3345 return ret; 3346 } 3347 3348 *fd_mode = req->mode; 3349 3350 return ret; 3351 } 3352 3353 static int hclge_get_fd_allocation(struct hclge_dev *hdev, 3354 u32 *stage1_entry_num, 3355 u32 *stage2_entry_num, 3356 u16 *stage1_counter_num, 3357 u16 *stage2_counter_num) 3358 { 3359 struct hclge_get_fd_allocation_cmd *req; 3360 struct hclge_desc desc; 3361 int ret; 3362 3363 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true); 3364 3365 req = (struct hclge_get_fd_allocation_cmd *)desc.data; 3366 3367 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3368 if (ret) { 3369 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n", 3370 ret); 3371 return ret; 3372 } 3373 3374 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num); 3375 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num); 3376 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num); 3377 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num); 3378 3379 return ret; 3380 } 3381 3382 static int hclge_set_fd_key_config(struct hclge_dev *hdev, int stage_num) 3383 { 3384 struct hclge_set_fd_key_config_cmd *req; 3385 struct hclge_fd_key_cfg *stage; 3386 struct hclge_desc desc; 3387 int ret; 3388 3389 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false); 3390 3391 req = (struct hclge_set_fd_key_config_cmd *)desc.data; 3392 stage = &hdev->fd_cfg.key_cfg[stage_num]; 3393 req->stage = stage_num; 3394 req->key_select = stage->key_sel; 3395 req->inner_sipv6_word_en = stage->inner_sipv6_word_en; 3396 req->inner_dipv6_word_en = stage->inner_dipv6_word_en; 3397 req->outer_sipv6_word_en = stage->outer_sipv6_word_en; 3398 req->outer_dipv6_word_en = stage->outer_dipv6_word_en; 3399 req->tuple_mask = cpu_to_le32(~stage->tuple_active); 3400 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active); 3401 3402 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3403 if (ret) 3404 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret); 3405 3406 return ret; 3407 } 3408 3409 static int hclge_init_fd_config(struct hclge_dev *hdev) 3410 { 3411 #define LOW_2_WORDS 0x03 3412 struct hclge_fd_key_cfg *key_cfg; 3413 int ret; 3414 3415 if (!hnae3_dev_fd_supported(hdev)) 3416 return 0; 3417 3418 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode); 3419 if (ret) 3420 return ret; 3421 3422 switch (hdev->fd_cfg.fd_mode) { 3423 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1: 3424 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH; 3425 break; 3426 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1: 3427 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2; 3428 break; 3429 default: 3430 dev_err(&hdev->pdev->dev, 3431 "Unsupported flow director mode %d\n", 3432 hdev->fd_cfg.fd_mode); 3433 return -EOPNOTSUPP; 3434 } 3435 3436 hdev->fd_cfg.fd_en = true; 3437 hdev->fd_cfg.proto_support = 3438 TCP_V4_FLOW | UDP_V4_FLOW | SCTP_V4_FLOW | TCP_V6_FLOW | 3439 UDP_V6_FLOW | SCTP_V6_FLOW | IPV4_USER_FLOW | IPV6_USER_FLOW; 3440 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1]; 3441 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE, 3442 key_cfg->inner_sipv6_word_en = LOW_2_WORDS; 3443 key_cfg->inner_dipv6_word_en = LOW_2_WORDS; 3444 key_cfg->outer_sipv6_word_en = 0; 3445 key_cfg->outer_dipv6_word_en = 0; 3446 3447 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) | 3448 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) | 3449 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 3450 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 3451 3452 /* If use max 400bit key, we can support tuples for ether type */ 3453 if (hdev->fd_cfg.max_key_length == MAX_KEY_LENGTH) { 3454 hdev->fd_cfg.proto_support |= ETHER_FLOW; 3455 key_cfg->tuple_active |= 3456 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC); 3457 } 3458 3459 /* roce_type is used to filter roce frames 3460 * dst_vport is used to specify the rule 3461 */ 3462 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT); 3463 3464 ret = hclge_get_fd_allocation(hdev, 3465 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1], 3466 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2], 3467 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1], 3468 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]); 3469 if (ret) 3470 return ret; 3471 3472 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1); 3473 } 3474 3475 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x, 3476 int loc, u8 *key, bool is_add) 3477 { 3478 struct hclge_fd_tcam_config_1_cmd *req1; 3479 struct hclge_fd_tcam_config_2_cmd *req2; 3480 struct hclge_fd_tcam_config_3_cmd *req3; 3481 struct hclge_desc desc[3]; 3482 int ret; 3483 3484 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false); 3485 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 3486 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false); 3487 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 3488 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false); 3489 3490 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 3491 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 3492 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 3493 3494 req1->stage = stage; 3495 req1->xy_sel = sel_x ? 1 : 0; 3496 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0); 3497 req1->index = cpu_to_le32(loc); 3498 req1->entry_vld = sel_x ? is_add : 0; 3499 3500 if (key) { 3501 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data)); 3502 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)], 3503 sizeof(req2->tcam_data)); 3504 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) + 3505 sizeof(req2->tcam_data)], sizeof(req3->tcam_data)); 3506 } 3507 3508 ret = hclge_cmd_send(&hdev->hw, desc, 3); 3509 if (ret) 3510 dev_err(&hdev->pdev->dev, 3511 "config tcam key fail, ret=%d\n", 3512 ret); 3513 3514 return ret; 3515 } 3516 3517 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc, 3518 struct hclge_fd_ad_data *action) 3519 { 3520 struct hclge_fd_ad_config_cmd *req; 3521 struct hclge_desc desc; 3522 u64 ad_data = 0; 3523 int ret; 3524 3525 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false); 3526 3527 req = (struct hclge_fd_ad_config_cmd *)desc.data; 3528 req->index = cpu_to_le32(loc); 3529 req->stage = stage; 3530 3531 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B, 3532 action->write_rule_id_to_bd); 3533 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S, 3534 action->rule_id); 3535 ad_data <<= 32; 3536 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet); 3537 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B, 3538 action->forward_to_direct_queue); 3539 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S, 3540 action->queue_id); 3541 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter); 3542 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M, 3543 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id); 3544 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage); 3545 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S, 3546 action->counter_id); 3547 3548 req->ad_data = cpu_to_le64(ad_data); 3549 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3550 if (ret) 3551 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret); 3552 3553 return ret; 3554 } 3555 3556 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y, 3557 struct hclge_fd_rule *rule) 3558 { 3559 u16 tmp_x_s, tmp_y_s; 3560 u32 tmp_x_l, tmp_y_l; 3561 int i; 3562 3563 if (rule->unused_tuple & tuple_bit) 3564 return true; 3565 3566 switch (tuple_bit) { 3567 case 0: 3568 return false; 3569 case BIT(INNER_DST_MAC): 3570 for (i = 0; i < 6; i++) { 3571 calc_x(key_x[5 - i], rule->tuples.dst_mac[i], 3572 rule->tuples_mask.dst_mac[i]); 3573 calc_y(key_y[5 - i], rule->tuples.dst_mac[i], 3574 rule->tuples_mask.dst_mac[i]); 3575 } 3576 3577 return true; 3578 case BIT(INNER_SRC_MAC): 3579 for (i = 0; i < 6; i++) { 3580 calc_x(key_x[5 - i], rule->tuples.src_mac[i], 3581 rule->tuples.src_mac[i]); 3582 calc_y(key_y[5 - i], rule->tuples.src_mac[i], 3583 rule->tuples.src_mac[i]); 3584 } 3585 3586 return true; 3587 case BIT(INNER_VLAN_TAG_FST): 3588 calc_x(tmp_x_s, rule->tuples.vlan_tag1, 3589 rule->tuples_mask.vlan_tag1); 3590 calc_y(tmp_y_s, rule->tuples.vlan_tag1, 3591 rule->tuples_mask.vlan_tag1); 3592 *(__le16 *)key_x = cpu_to_le16(tmp_x_s); 3593 *(__le16 *)key_y = cpu_to_le16(tmp_y_s); 3594 3595 return true; 3596 case BIT(INNER_ETH_TYPE): 3597 calc_x(tmp_x_s, rule->tuples.ether_proto, 3598 rule->tuples_mask.ether_proto); 3599 calc_y(tmp_y_s, rule->tuples.ether_proto, 3600 rule->tuples_mask.ether_proto); 3601 *(__le16 *)key_x = cpu_to_le16(tmp_x_s); 3602 *(__le16 *)key_y = cpu_to_le16(tmp_y_s); 3603 3604 return true; 3605 case BIT(INNER_IP_TOS): 3606 calc_x(*key_x, rule->tuples.ip_tos, rule->tuples_mask.ip_tos); 3607 calc_y(*key_y, rule->tuples.ip_tos, rule->tuples_mask.ip_tos); 3608 3609 return true; 3610 case BIT(INNER_IP_PROTO): 3611 calc_x(*key_x, rule->tuples.ip_proto, 3612 rule->tuples_mask.ip_proto); 3613 calc_y(*key_y, rule->tuples.ip_proto, 3614 rule->tuples_mask.ip_proto); 3615 3616 return true; 3617 case BIT(INNER_SRC_IP): 3618 calc_x(tmp_x_l, rule->tuples.src_ip[3], 3619 rule->tuples_mask.src_ip[3]); 3620 calc_y(tmp_y_l, rule->tuples.src_ip[3], 3621 rule->tuples_mask.src_ip[3]); 3622 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 3623 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 3624 3625 return true; 3626 case BIT(INNER_DST_IP): 3627 calc_x(tmp_x_l, rule->tuples.dst_ip[3], 3628 rule->tuples_mask.dst_ip[3]); 3629 calc_y(tmp_y_l, rule->tuples.dst_ip[3], 3630 rule->tuples_mask.dst_ip[3]); 3631 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 3632 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 3633 3634 return true; 3635 case BIT(INNER_SRC_PORT): 3636 calc_x(tmp_x_s, rule->tuples.src_port, 3637 rule->tuples_mask.src_port); 3638 calc_y(tmp_y_s, rule->tuples.src_port, 3639 rule->tuples_mask.src_port); 3640 *(__le16 *)key_x = cpu_to_le16(tmp_x_s); 3641 *(__le16 *)key_y = cpu_to_le16(tmp_y_s); 3642 3643 return true; 3644 case BIT(INNER_DST_PORT): 3645 calc_x(tmp_x_s, rule->tuples.dst_port, 3646 rule->tuples_mask.dst_port); 3647 calc_y(tmp_y_s, rule->tuples.dst_port, 3648 rule->tuples_mask.dst_port); 3649 *(__le16 *)key_x = cpu_to_le16(tmp_x_s); 3650 *(__le16 *)key_y = cpu_to_le16(tmp_y_s); 3651 3652 return true; 3653 default: 3654 return false; 3655 } 3656 } 3657 3658 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 3659 u8 vf_id, u8 network_port_id) 3660 { 3661 u32 port_number = 0; 3662 3663 if (port_type == HOST_PORT) { 3664 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S, 3665 pf_id); 3666 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S, 3667 vf_id); 3668 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT); 3669 } else { 3670 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M, 3671 HCLGE_NETWORK_PORT_ID_S, network_port_id); 3672 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT); 3673 } 3674 3675 return port_number; 3676 } 3677 3678 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg, 3679 __le32 *key_x, __le32 *key_y, 3680 struct hclge_fd_rule *rule) 3681 { 3682 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number; 3683 u8 cur_pos = 0, tuple_size, shift_bits; 3684 int i; 3685 3686 for (i = 0; i < MAX_META_DATA; i++) { 3687 tuple_size = meta_data_key_info[i].key_length; 3688 tuple_bit = key_cfg->meta_data_active & BIT(i); 3689 3690 switch (tuple_bit) { 3691 case BIT(ROCE_TYPE): 3692 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET); 3693 cur_pos += tuple_size; 3694 break; 3695 case BIT(DST_VPORT): 3696 port_number = hclge_get_port_number(HOST_PORT, 0, 3697 rule->vf_id, 0); 3698 hnae3_set_field(meta_data, 3699 GENMASK(cur_pos + tuple_size, cur_pos), 3700 cur_pos, port_number); 3701 cur_pos += tuple_size; 3702 break; 3703 default: 3704 break; 3705 } 3706 } 3707 3708 calc_x(tmp_x, meta_data, 0xFFFFFFFF); 3709 calc_y(tmp_y, meta_data, 0xFFFFFFFF); 3710 shift_bits = sizeof(meta_data) * 8 - cur_pos; 3711 3712 *key_x = cpu_to_le32(tmp_x << shift_bits); 3713 *key_y = cpu_to_le32(tmp_y << shift_bits); 3714 } 3715 3716 /* A complete key is combined with meta data key and tuple key. 3717 * Meta data key is stored at the MSB region, and tuple key is stored at 3718 * the LSB region, unused bits will be filled 0. 3719 */ 3720 static int hclge_config_key(struct hclge_dev *hdev, u8 stage, 3721 struct hclge_fd_rule *rule) 3722 { 3723 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage]; 3724 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES]; 3725 u8 *cur_key_x, *cur_key_y; 3726 int i, ret, tuple_size; 3727 u8 meta_data_region; 3728 3729 memset(key_x, 0, sizeof(key_x)); 3730 memset(key_y, 0, sizeof(key_y)); 3731 cur_key_x = key_x; 3732 cur_key_y = key_y; 3733 3734 for (i = 0 ; i < MAX_TUPLE; i++) { 3735 bool tuple_valid; 3736 u32 check_tuple; 3737 3738 tuple_size = tuple_key_info[i].key_length / 8; 3739 check_tuple = key_cfg->tuple_active & BIT(i); 3740 3741 tuple_valid = hclge_fd_convert_tuple(check_tuple, cur_key_x, 3742 cur_key_y, rule); 3743 if (tuple_valid) { 3744 cur_key_x += tuple_size; 3745 cur_key_y += tuple_size; 3746 } 3747 } 3748 3749 meta_data_region = hdev->fd_cfg.max_key_length / 8 - 3750 MAX_META_DATA_LENGTH / 8; 3751 3752 hclge_fd_convert_meta_data(key_cfg, 3753 (__le32 *)(key_x + meta_data_region), 3754 (__le32 *)(key_y + meta_data_region), 3755 rule); 3756 3757 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y, 3758 true); 3759 if (ret) { 3760 dev_err(&hdev->pdev->dev, 3761 "fd key_y config fail, loc=%d, ret=%d\n", 3762 rule->queue_id, ret); 3763 return ret; 3764 } 3765 3766 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x, 3767 true); 3768 if (ret) 3769 dev_err(&hdev->pdev->dev, 3770 "fd key_x config fail, loc=%d, ret=%d\n", 3771 rule->queue_id, ret); 3772 return ret; 3773 } 3774 3775 static int hclge_config_action(struct hclge_dev *hdev, u8 stage, 3776 struct hclge_fd_rule *rule) 3777 { 3778 struct hclge_fd_ad_data ad_data; 3779 3780 ad_data.ad_id = rule->location; 3781 3782 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 3783 ad_data.drop_packet = true; 3784 ad_data.forward_to_direct_queue = false; 3785 ad_data.queue_id = 0; 3786 } else { 3787 ad_data.drop_packet = false; 3788 ad_data.forward_to_direct_queue = true; 3789 ad_data.queue_id = rule->queue_id; 3790 } 3791 3792 ad_data.use_counter = false; 3793 ad_data.counter_id = 0; 3794 3795 ad_data.use_next_stage = false; 3796 ad_data.next_input_key = 0; 3797 3798 ad_data.write_rule_id_to_bd = true; 3799 ad_data.rule_id = rule->location; 3800 3801 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data); 3802 } 3803 3804 static int hclge_fd_check_spec(struct hclge_dev *hdev, 3805 struct ethtool_rx_flow_spec *fs, u32 *unused) 3806 { 3807 struct ethtool_tcpip4_spec *tcp_ip4_spec; 3808 struct ethtool_usrip4_spec *usr_ip4_spec; 3809 struct ethtool_tcpip6_spec *tcp_ip6_spec; 3810 struct ethtool_usrip6_spec *usr_ip6_spec; 3811 struct ethhdr *ether_spec; 3812 3813 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 3814 return -EINVAL; 3815 3816 if (!(fs->flow_type & hdev->fd_cfg.proto_support)) 3817 return -EOPNOTSUPP; 3818 3819 if ((fs->flow_type & FLOW_EXT) && 3820 (fs->h_ext.data[0] != 0 || fs->h_ext.data[1] != 0)) { 3821 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n"); 3822 return -EOPNOTSUPP; 3823 } 3824 3825 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 3826 case SCTP_V4_FLOW: 3827 case TCP_V4_FLOW: 3828 case UDP_V4_FLOW: 3829 tcp_ip4_spec = &fs->h_u.tcp_ip4_spec; 3830 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 3831 3832 if (!tcp_ip4_spec->ip4src) 3833 *unused |= BIT(INNER_SRC_IP); 3834 3835 if (!tcp_ip4_spec->ip4dst) 3836 *unused |= BIT(INNER_DST_IP); 3837 3838 if (!tcp_ip4_spec->psrc) 3839 *unused |= BIT(INNER_SRC_PORT); 3840 3841 if (!tcp_ip4_spec->pdst) 3842 *unused |= BIT(INNER_DST_PORT); 3843 3844 if (!tcp_ip4_spec->tos) 3845 *unused |= BIT(INNER_IP_TOS); 3846 3847 break; 3848 case IP_USER_FLOW: 3849 usr_ip4_spec = &fs->h_u.usr_ip4_spec; 3850 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 3851 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 3852 3853 if (!usr_ip4_spec->ip4src) 3854 *unused |= BIT(INNER_SRC_IP); 3855 3856 if (!usr_ip4_spec->ip4dst) 3857 *unused |= BIT(INNER_DST_IP); 3858 3859 if (!usr_ip4_spec->tos) 3860 *unused |= BIT(INNER_IP_TOS); 3861 3862 if (!usr_ip4_spec->proto) 3863 *unused |= BIT(INNER_IP_PROTO); 3864 3865 if (usr_ip4_spec->l4_4_bytes) 3866 return -EOPNOTSUPP; 3867 3868 if (usr_ip4_spec->ip_ver != ETH_RX_NFC_IP4) 3869 return -EOPNOTSUPP; 3870 3871 break; 3872 case SCTP_V6_FLOW: 3873 case TCP_V6_FLOW: 3874 case UDP_V6_FLOW: 3875 tcp_ip6_spec = &fs->h_u.tcp_ip6_spec; 3876 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 3877 BIT(INNER_IP_TOS); 3878 3879 if (!tcp_ip6_spec->ip6src[0] && !tcp_ip6_spec->ip6src[1] && 3880 !tcp_ip6_spec->ip6src[2] && !tcp_ip6_spec->ip6src[3]) 3881 *unused |= BIT(INNER_SRC_IP); 3882 3883 if (!tcp_ip6_spec->ip6dst[0] && !tcp_ip6_spec->ip6dst[1] && 3884 !tcp_ip6_spec->ip6dst[2] && !tcp_ip6_spec->ip6dst[3]) 3885 *unused |= BIT(INNER_DST_IP); 3886 3887 if (!tcp_ip6_spec->psrc) 3888 *unused |= BIT(INNER_SRC_PORT); 3889 3890 if (!tcp_ip6_spec->pdst) 3891 *unused |= BIT(INNER_DST_PORT); 3892 3893 if (tcp_ip6_spec->tclass) 3894 return -EOPNOTSUPP; 3895 3896 break; 3897 case IPV6_USER_FLOW: 3898 usr_ip6_spec = &fs->h_u.usr_ip6_spec; 3899 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 3900 BIT(INNER_IP_TOS) | BIT(INNER_SRC_PORT) | 3901 BIT(INNER_DST_PORT); 3902 3903 if (!usr_ip6_spec->ip6src[0] && !usr_ip6_spec->ip6src[1] && 3904 !usr_ip6_spec->ip6src[2] && !usr_ip6_spec->ip6src[3]) 3905 *unused |= BIT(INNER_SRC_IP); 3906 3907 if (!usr_ip6_spec->ip6dst[0] && !usr_ip6_spec->ip6dst[1] && 3908 !usr_ip6_spec->ip6dst[2] && !usr_ip6_spec->ip6dst[3]) 3909 *unused |= BIT(INNER_DST_IP); 3910 3911 if (!usr_ip6_spec->l4_proto) 3912 *unused |= BIT(INNER_IP_PROTO); 3913 3914 if (usr_ip6_spec->tclass) 3915 return -EOPNOTSUPP; 3916 3917 if (usr_ip6_spec->l4_4_bytes) 3918 return -EOPNOTSUPP; 3919 3920 break; 3921 case ETHER_FLOW: 3922 ether_spec = &fs->h_u.ether_spec; 3923 *unused |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 3924 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) | 3925 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO); 3926 3927 if (is_zero_ether_addr(ether_spec->h_source)) 3928 *unused |= BIT(INNER_SRC_MAC); 3929 3930 if (is_zero_ether_addr(ether_spec->h_dest)) 3931 *unused |= BIT(INNER_DST_MAC); 3932 3933 if (!ether_spec->h_proto) 3934 *unused |= BIT(INNER_ETH_TYPE); 3935 3936 break; 3937 default: 3938 return -EOPNOTSUPP; 3939 } 3940 3941 if ((fs->flow_type & FLOW_EXT)) { 3942 if (fs->h_ext.vlan_etype) 3943 return -EOPNOTSUPP; 3944 if (!fs->h_ext.vlan_tci) 3945 *unused |= BIT(INNER_VLAN_TAG_FST); 3946 3947 if (fs->m_ext.vlan_tci) { 3948 if (be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) 3949 return -EINVAL; 3950 } 3951 } else { 3952 *unused |= BIT(INNER_VLAN_TAG_FST); 3953 } 3954 3955 if (fs->flow_type & FLOW_MAC_EXT) { 3956 if (!(hdev->fd_cfg.proto_support & ETHER_FLOW)) 3957 return -EOPNOTSUPP; 3958 3959 if (is_zero_ether_addr(fs->h_ext.h_dest)) 3960 *unused |= BIT(INNER_DST_MAC); 3961 else 3962 *unused &= ~(BIT(INNER_DST_MAC)); 3963 } 3964 3965 return 0; 3966 } 3967 3968 static bool hclge_fd_rule_exist(struct hclge_dev *hdev, u16 location) 3969 { 3970 struct hclge_fd_rule *rule = NULL; 3971 struct hlist_node *node2; 3972 3973 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) { 3974 if (rule->location >= location) 3975 break; 3976 } 3977 3978 return rule && rule->location == location; 3979 } 3980 3981 static int hclge_fd_update_rule_list(struct hclge_dev *hdev, 3982 struct hclge_fd_rule *new_rule, 3983 u16 location, 3984 bool is_add) 3985 { 3986 struct hclge_fd_rule *rule = NULL, *parent = NULL; 3987 struct hlist_node *node2; 3988 3989 if (is_add && !new_rule) 3990 return -EINVAL; 3991 3992 hlist_for_each_entry_safe(rule, node2, 3993 &hdev->fd_rule_list, rule_node) { 3994 if (rule->location >= location) 3995 break; 3996 parent = rule; 3997 } 3998 3999 if (rule && rule->location == location) { 4000 hlist_del(&rule->rule_node); 4001 kfree(rule); 4002 hdev->hclge_fd_rule_num--; 4003 4004 if (!is_add) 4005 return 0; 4006 4007 } else if (!is_add) { 4008 dev_err(&hdev->pdev->dev, 4009 "delete fail, rule %d is inexistent\n", 4010 location); 4011 return -EINVAL; 4012 } 4013 4014 INIT_HLIST_NODE(&new_rule->rule_node); 4015 4016 if (parent) 4017 hlist_add_behind(&new_rule->rule_node, &parent->rule_node); 4018 else 4019 hlist_add_head(&new_rule->rule_node, &hdev->fd_rule_list); 4020 4021 hdev->hclge_fd_rule_num++; 4022 4023 return 0; 4024 } 4025 4026 static int hclge_fd_get_tuple(struct hclge_dev *hdev, 4027 struct ethtool_rx_flow_spec *fs, 4028 struct hclge_fd_rule *rule) 4029 { 4030 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 4031 4032 switch (flow_type) { 4033 case SCTP_V4_FLOW: 4034 case TCP_V4_FLOW: 4035 case UDP_V4_FLOW: 4036 rule->tuples.src_ip[3] = 4037 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src); 4038 rule->tuples_mask.src_ip[3] = 4039 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src); 4040 4041 rule->tuples.dst_ip[3] = 4042 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst); 4043 rule->tuples_mask.dst_ip[3] = 4044 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst); 4045 4046 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc); 4047 rule->tuples_mask.src_port = 4048 be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc); 4049 4050 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst); 4051 rule->tuples_mask.dst_port = 4052 be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst); 4053 4054 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos; 4055 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos; 4056 4057 rule->tuples.ether_proto = ETH_P_IP; 4058 rule->tuples_mask.ether_proto = 0xFFFF; 4059 4060 break; 4061 case IP_USER_FLOW: 4062 rule->tuples.src_ip[3] = 4063 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src); 4064 rule->tuples_mask.src_ip[3] = 4065 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src); 4066 4067 rule->tuples.dst_ip[3] = 4068 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst); 4069 rule->tuples_mask.dst_ip[3] = 4070 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst); 4071 4072 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos; 4073 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos; 4074 4075 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto; 4076 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto; 4077 4078 rule->tuples.ether_proto = ETH_P_IP; 4079 rule->tuples_mask.ether_proto = 0xFFFF; 4080 4081 break; 4082 case SCTP_V6_FLOW: 4083 case TCP_V6_FLOW: 4084 case UDP_V6_FLOW: 4085 be32_to_cpu_array(rule->tuples.src_ip, 4086 fs->h_u.tcp_ip6_spec.ip6src, 4); 4087 be32_to_cpu_array(rule->tuples_mask.src_ip, 4088 fs->m_u.tcp_ip6_spec.ip6src, 4); 4089 4090 be32_to_cpu_array(rule->tuples.dst_ip, 4091 fs->h_u.tcp_ip6_spec.ip6dst, 4); 4092 be32_to_cpu_array(rule->tuples_mask.dst_ip, 4093 fs->m_u.tcp_ip6_spec.ip6dst, 4); 4094 4095 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc); 4096 rule->tuples_mask.src_port = 4097 be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc); 4098 4099 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst); 4100 rule->tuples_mask.dst_port = 4101 be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst); 4102 4103 rule->tuples.ether_proto = ETH_P_IPV6; 4104 rule->tuples_mask.ether_proto = 0xFFFF; 4105 4106 break; 4107 case IPV6_USER_FLOW: 4108 be32_to_cpu_array(rule->tuples.src_ip, 4109 fs->h_u.usr_ip6_spec.ip6src, 4); 4110 be32_to_cpu_array(rule->tuples_mask.src_ip, 4111 fs->m_u.usr_ip6_spec.ip6src, 4); 4112 4113 be32_to_cpu_array(rule->tuples.dst_ip, 4114 fs->h_u.usr_ip6_spec.ip6dst, 4); 4115 be32_to_cpu_array(rule->tuples_mask.dst_ip, 4116 fs->m_u.usr_ip6_spec.ip6dst, 4); 4117 4118 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto; 4119 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto; 4120 4121 rule->tuples.ether_proto = ETH_P_IPV6; 4122 rule->tuples_mask.ether_proto = 0xFFFF; 4123 4124 break; 4125 case ETHER_FLOW: 4126 ether_addr_copy(rule->tuples.src_mac, 4127 fs->h_u.ether_spec.h_source); 4128 ether_addr_copy(rule->tuples_mask.src_mac, 4129 fs->m_u.ether_spec.h_source); 4130 4131 ether_addr_copy(rule->tuples.dst_mac, 4132 fs->h_u.ether_spec.h_dest); 4133 ether_addr_copy(rule->tuples_mask.dst_mac, 4134 fs->m_u.ether_spec.h_dest); 4135 4136 rule->tuples.ether_proto = 4137 be16_to_cpu(fs->h_u.ether_spec.h_proto); 4138 rule->tuples_mask.ether_proto = 4139 be16_to_cpu(fs->m_u.ether_spec.h_proto); 4140 4141 break; 4142 default: 4143 return -EOPNOTSUPP; 4144 } 4145 4146 switch (flow_type) { 4147 case SCTP_V4_FLOW: 4148 case SCTP_V6_FLOW: 4149 rule->tuples.ip_proto = IPPROTO_SCTP; 4150 rule->tuples_mask.ip_proto = 0xFF; 4151 break; 4152 case TCP_V4_FLOW: 4153 case TCP_V6_FLOW: 4154 rule->tuples.ip_proto = IPPROTO_TCP; 4155 rule->tuples_mask.ip_proto = 0xFF; 4156 break; 4157 case UDP_V4_FLOW: 4158 case UDP_V6_FLOW: 4159 rule->tuples.ip_proto = IPPROTO_UDP; 4160 rule->tuples_mask.ip_proto = 0xFF; 4161 break; 4162 default: 4163 break; 4164 } 4165 4166 if ((fs->flow_type & FLOW_EXT)) { 4167 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci); 4168 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci); 4169 } 4170 4171 if (fs->flow_type & FLOW_MAC_EXT) { 4172 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest); 4173 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest); 4174 } 4175 4176 return 0; 4177 } 4178 4179 static int hclge_add_fd_entry(struct hnae3_handle *handle, 4180 struct ethtool_rxnfc *cmd) 4181 { 4182 struct hclge_vport *vport = hclge_get_vport(handle); 4183 struct hclge_dev *hdev = vport->back; 4184 u16 dst_vport_id = 0, q_index = 0; 4185 struct ethtool_rx_flow_spec *fs; 4186 struct hclge_fd_rule *rule; 4187 u32 unused = 0; 4188 u8 action; 4189 int ret; 4190 4191 if (!hnae3_dev_fd_supported(hdev)) 4192 return -EOPNOTSUPP; 4193 4194 if (!hdev->fd_cfg.fd_en) { 4195 dev_warn(&hdev->pdev->dev, 4196 "Please enable flow director first\n"); 4197 return -EOPNOTSUPP; 4198 } 4199 4200 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 4201 4202 ret = hclge_fd_check_spec(hdev, fs, &unused); 4203 if (ret) { 4204 dev_err(&hdev->pdev->dev, "Check fd spec failed\n"); 4205 return ret; 4206 } 4207 4208 if (fs->ring_cookie == RX_CLS_FLOW_DISC) { 4209 action = HCLGE_FD_ACTION_DROP_PACKET; 4210 } else { 4211 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie); 4212 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie); 4213 u16 tqps; 4214 4215 dst_vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id; 4216 tqps = vf ? hdev->vport[vf].alloc_tqps : vport->alloc_tqps; 4217 4218 if (ring >= tqps) { 4219 dev_err(&hdev->pdev->dev, 4220 "Error: queue id (%d) > max tqp num (%d)\n", 4221 ring, tqps - 1); 4222 return -EINVAL; 4223 } 4224 4225 if (vf > hdev->num_req_vfs) { 4226 dev_err(&hdev->pdev->dev, 4227 "Error: vf id (%d) > max vf num (%d)\n", 4228 vf, hdev->num_req_vfs); 4229 return -EINVAL; 4230 } 4231 4232 action = HCLGE_FD_ACTION_ACCEPT_PACKET; 4233 q_index = ring; 4234 } 4235 4236 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 4237 if (!rule) 4238 return -ENOMEM; 4239 4240 ret = hclge_fd_get_tuple(hdev, fs, rule); 4241 if (ret) 4242 goto free_rule; 4243 4244 rule->flow_type = fs->flow_type; 4245 4246 rule->location = fs->location; 4247 rule->unused_tuple = unused; 4248 rule->vf_id = dst_vport_id; 4249 rule->queue_id = q_index; 4250 rule->action = action; 4251 4252 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule); 4253 if (ret) 4254 goto free_rule; 4255 4256 ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule); 4257 if (ret) 4258 goto free_rule; 4259 4260 ret = hclge_fd_update_rule_list(hdev, rule, fs->location, true); 4261 if (ret) 4262 goto free_rule; 4263 4264 return ret; 4265 4266 free_rule: 4267 kfree(rule); 4268 return ret; 4269 } 4270 4271 static int hclge_del_fd_entry(struct hnae3_handle *handle, 4272 struct ethtool_rxnfc *cmd) 4273 { 4274 struct hclge_vport *vport = hclge_get_vport(handle); 4275 struct hclge_dev *hdev = vport->back; 4276 struct ethtool_rx_flow_spec *fs; 4277 int ret; 4278 4279 if (!hnae3_dev_fd_supported(hdev)) 4280 return -EOPNOTSUPP; 4281 4282 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 4283 4284 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 4285 return -EINVAL; 4286 4287 if (!hclge_fd_rule_exist(hdev, fs->location)) { 4288 dev_err(&hdev->pdev->dev, 4289 "Delete fail, rule %d is inexistent\n", 4290 fs->location); 4291 return -ENOENT; 4292 } 4293 4294 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 4295 fs->location, NULL, false); 4296 if (ret) 4297 return ret; 4298 4299 return hclge_fd_update_rule_list(hdev, NULL, fs->location, 4300 false); 4301 } 4302 4303 static void hclge_del_all_fd_entries(struct hnae3_handle *handle, 4304 bool clear_list) 4305 { 4306 struct hclge_vport *vport = hclge_get_vport(handle); 4307 struct hclge_dev *hdev = vport->back; 4308 struct hclge_fd_rule *rule; 4309 struct hlist_node *node; 4310 4311 if (!hnae3_dev_fd_supported(hdev)) 4312 return; 4313 4314 if (clear_list) { 4315 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, 4316 rule_node) { 4317 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 4318 rule->location, NULL, false); 4319 hlist_del(&rule->rule_node); 4320 kfree(rule); 4321 hdev->hclge_fd_rule_num--; 4322 } 4323 } else { 4324 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, 4325 rule_node) 4326 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 4327 rule->location, NULL, false); 4328 } 4329 } 4330 4331 static int hclge_restore_fd_entries(struct hnae3_handle *handle) 4332 { 4333 struct hclge_vport *vport = hclge_get_vport(handle); 4334 struct hclge_dev *hdev = vport->back; 4335 struct hclge_fd_rule *rule; 4336 struct hlist_node *node; 4337 int ret; 4338 4339 if (!hnae3_dev_fd_supported(hdev)) 4340 return -EOPNOTSUPP; 4341 4342 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 4343 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule); 4344 if (!ret) 4345 ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule); 4346 4347 if (ret) { 4348 dev_warn(&hdev->pdev->dev, 4349 "Restore rule %d failed, remove it\n", 4350 rule->location); 4351 hlist_del(&rule->rule_node); 4352 kfree(rule); 4353 hdev->hclge_fd_rule_num--; 4354 } 4355 } 4356 return 0; 4357 } 4358 4359 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle, 4360 struct ethtool_rxnfc *cmd) 4361 { 4362 struct hclge_vport *vport = hclge_get_vport(handle); 4363 struct hclge_dev *hdev = vport->back; 4364 4365 if (!hnae3_dev_fd_supported(hdev)) 4366 return -EOPNOTSUPP; 4367 4368 cmd->rule_cnt = hdev->hclge_fd_rule_num; 4369 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 4370 4371 return 0; 4372 } 4373 4374 static int hclge_get_fd_rule_info(struct hnae3_handle *handle, 4375 struct ethtool_rxnfc *cmd) 4376 { 4377 struct hclge_vport *vport = hclge_get_vport(handle); 4378 struct hclge_fd_rule *rule = NULL; 4379 struct hclge_dev *hdev = vport->back; 4380 struct ethtool_rx_flow_spec *fs; 4381 struct hlist_node *node2; 4382 4383 if (!hnae3_dev_fd_supported(hdev)) 4384 return -EOPNOTSUPP; 4385 4386 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 4387 4388 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) { 4389 if (rule->location >= fs->location) 4390 break; 4391 } 4392 4393 if (!rule || fs->location != rule->location) 4394 return -ENOENT; 4395 4396 fs->flow_type = rule->flow_type; 4397 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 4398 case SCTP_V4_FLOW: 4399 case TCP_V4_FLOW: 4400 case UDP_V4_FLOW: 4401 fs->h_u.tcp_ip4_spec.ip4src = 4402 cpu_to_be32(rule->tuples.src_ip[3]); 4403 fs->m_u.tcp_ip4_spec.ip4src = 4404 rule->unused_tuple & BIT(INNER_SRC_IP) ? 4405 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]); 4406 4407 fs->h_u.tcp_ip4_spec.ip4dst = 4408 cpu_to_be32(rule->tuples.dst_ip[3]); 4409 fs->m_u.tcp_ip4_spec.ip4dst = 4410 rule->unused_tuple & BIT(INNER_DST_IP) ? 4411 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]); 4412 4413 fs->h_u.tcp_ip4_spec.psrc = cpu_to_be16(rule->tuples.src_port); 4414 fs->m_u.tcp_ip4_spec.psrc = 4415 rule->unused_tuple & BIT(INNER_SRC_PORT) ? 4416 0 : cpu_to_be16(rule->tuples_mask.src_port); 4417 4418 fs->h_u.tcp_ip4_spec.pdst = cpu_to_be16(rule->tuples.dst_port); 4419 fs->m_u.tcp_ip4_spec.pdst = 4420 rule->unused_tuple & BIT(INNER_DST_PORT) ? 4421 0 : cpu_to_be16(rule->tuples_mask.dst_port); 4422 4423 fs->h_u.tcp_ip4_spec.tos = rule->tuples.ip_tos; 4424 fs->m_u.tcp_ip4_spec.tos = 4425 rule->unused_tuple & BIT(INNER_IP_TOS) ? 4426 0 : rule->tuples_mask.ip_tos; 4427 4428 break; 4429 case IP_USER_FLOW: 4430 fs->h_u.usr_ip4_spec.ip4src = 4431 cpu_to_be32(rule->tuples.src_ip[3]); 4432 fs->m_u.tcp_ip4_spec.ip4src = 4433 rule->unused_tuple & BIT(INNER_SRC_IP) ? 4434 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]); 4435 4436 fs->h_u.usr_ip4_spec.ip4dst = 4437 cpu_to_be32(rule->tuples.dst_ip[3]); 4438 fs->m_u.usr_ip4_spec.ip4dst = 4439 rule->unused_tuple & BIT(INNER_DST_IP) ? 4440 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]); 4441 4442 fs->h_u.usr_ip4_spec.tos = rule->tuples.ip_tos; 4443 fs->m_u.usr_ip4_spec.tos = 4444 rule->unused_tuple & BIT(INNER_IP_TOS) ? 4445 0 : rule->tuples_mask.ip_tos; 4446 4447 fs->h_u.usr_ip4_spec.proto = rule->tuples.ip_proto; 4448 fs->m_u.usr_ip4_spec.proto = 4449 rule->unused_tuple & BIT(INNER_IP_PROTO) ? 4450 0 : rule->tuples_mask.ip_proto; 4451 4452 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 4453 4454 break; 4455 case SCTP_V6_FLOW: 4456 case TCP_V6_FLOW: 4457 case UDP_V6_FLOW: 4458 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6src, 4459 rule->tuples.src_ip, 4); 4460 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 4461 memset(fs->m_u.tcp_ip6_spec.ip6src, 0, sizeof(int) * 4); 4462 else 4463 cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6src, 4464 rule->tuples_mask.src_ip, 4); 4465 4466 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6dst, 4467 rule->tuples.dst_ip, 4); 4468 if (rule->unused_tuple & BIT(INNER_DST_IP)) 4469 memset(fs->m_u.tcp_ip6_spec.ip6dst, 0, sizeof(int) * 4); 4470 else 4471 cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6dst, 4472 rule->tuples_mask.dst_ip, 4); 4473 4474 fs->h_u.tcp_ip6_spec.psrc = cpu_to_be16(rule->tuples.src_port); 4475 fs->m_u.tcp_ip6_spec.psrc = 4476 rule->unused_tuple & BIT(INNER_SRC_PORT) ? 4477 0 : cpu_to_be16(rule->tuples_mask.src_port); 4478 4479 fs->h_u.tcp_ip6_spec.pdst = cpu_to_be16(rule->tuples.dst_port); 4480 fs->m_u.tcp_ip6_spec.pdst = 4481 rule->unused_tuple & BIT(INNER_DST_PORT) ? 4482 0 : cpu_to_be16(rule->tuples_mask.dst_port); 4483 4484 break; 4485 case IPV6_USER_FLOW: 4486 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6src, 4487 rule->tuples.src_ip, 4); 4488 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 4489 memset(fs->m_u.usr_ip6_spec.ip6src, 0, sizeof(int) * 4); 4490 else 4491 cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6src, 4492 rule->tuples_mask.src_ip, 4); 4493 4494 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6dst, 4495 rule->tuples.dst_ip, 4); 4496 if (rule->unused_tuple & BIT(INNER_DST_IP)) 4497 memset(fs->m_u.usr_ip6_spec.ip6dst, 0, sizeof(int) * 4); 4498 else 4499 cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6dst, 4500 rule->tuples_mask.dst_ip, 4); 4501 4502 fs->h_u.usr_ip6_spec.l4_proto = rule->tuples.ip_proto; 4503 fs->m_u.usr_ip6_spec.l4_proto = 4504 rule->unused_tuple & BIT(INNER_IP_PROTO) ? 4505 0 : rule->tuples_mask.ip_proto; 4506 4507 break; 4508 case ETHER_FLOW: 4509 ether_addr_copy(fs->h_u.ether_spec.h_source, 4510 rule->tuples.src_mac); 4511 if (rule->unused_tuple & BIT(INNER_SRC_MAC)) 4512 eth_zero_addr(fs->m_u.ether_spec.h_source); 4513 else 4514 ether_addr_copy(fs->m_u.ether_spec.h_source, 4515 rule->tuples_mask.src_mac); 4516 4517 ether_addr_copy(fs->h_u.ether_spec.h_dest, 4518 rule->tuples.dst_mac); 4519 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 4520 eth_zero_addr(fs->m_u.ether_spec.h_dest); 4521 else 4522 ether_addr_copy(fs->m_u.ether_spec.h_dest, 4523 rule->tuples_mask.dst_mac); 4524 4525 fs->h_u.ether_spec.h_proto = 4526 cpu_to_be16(rule->tuples.ether_proto); 4527 fs->m_u.ether_spec.h_proto = 4528 rule->unused_tuple & BIT(INNER_ETH_TYPE) ? 4529 0 : cpu_to_be16(rule->tuples_mask.ether_proto); 4530 4531 break; 4532 default: 4533 return -EOPNOTSUPP; 4534 } 4535 4536 if (fs->flow_type & FLOW_EXT) { 4537 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1); 4538 fs->m_ext.vlan_tci = 4539 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ? 4540 cpu_to_be16(VLAN_VID_MASK) : 4541 cpu_to_be16(rule->tuples_mask.vlan_tag1); 4542 } 4543 4544 if (fs->flow_type & FLOW_MAC_EXT) { 4545 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac); 4546 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 4547 eth_zero_addr(fs->m_u.ether_spec.h_dest); 4548 else 4549 ether_addr_copy(fs->m_u.ether_spec.h_dest, 4550 rule->tuples_mask.dst_mac); 4551 } 4552 4553 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 4554 fs->ring_cookie = RX_CLS_FLOW_DISC; 4555 } else { 4556 u64 vf_id; 4557 4558 fs->ring_cookie = rule->queue_id; 4559 vf_id = rule->vf_id; 4560 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 4561 fs->ring_cookie |= vf_id; 4562 } 4563 4564 return 0; 4565 } 4566 4567 static int hclge_get_all_rules(struct hnae3_handle *handle, 4568 struct ethtool_rxnfc *cmd, u32 *rule_locs) 4569 { 4570 struct hclge_vport *vport = hclge_get_vport(handle); 4571 struct hclge_dev *hdev = vport->back; 4572 struct hclge_fd_rule *rule; 4573 struct hlist_node *node2; 4574 int cnt = 0; 4575 4576 if (!hnae3_dev_fd_supported(hdev)) 4577 return -EOPNOTSUPP; 4578 4579 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 4580 4581 hlist_for_each_entry_safe(rule, node2, 4582 &hdev->fd_rule_list, rule_node) { 4583 if (cnt == cmd->rule_cnt) 4584 return -EMSGSIZE; 4585 4586 rule_locs[cnt] = rule->location; 4587 cnt++; 4588 } 4589 4590 cmd->rule_cnt = cnt; 4591 4592 return 0; 4593 } 4594 4595 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable) 4596 { 4597 struct hclge_vport *vport = hclge_get_vport(handle); 4598 struct hclge_dev *hdev = vport->back; 4599 4600 hdev->fd_cfg.fd_en = enable; 4601 if (!enable) 4602 hclge_del_all_fd_entries(handle, false); 4603 else 4604 hclge_restore_fd_entries(handle); 4605 } 4606 4607 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 4608 { 4609 struct hclge_desc desc; 4610 struct hclge_config_mac_mode_cmd *req = 4611 (struct hclge_config_mac_mode_cmd *)desc.data; 4612 u32 loop_en = 0; 4613 int ret; 4614 4615 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 4616 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable); 4617 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable); 4618 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable); 4619 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable); 4620 hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0); 4621 hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0); 4622 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0); 4623 hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0); 4624 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable); 4625 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable); 4626 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable); 4627 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable); 4628 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable); 4629 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable); 4630 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 4631 4632 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4633 if (ret) 4634 dev_err(&hdev->pdev->dev, 4635 "mac enable fail, ret =%d.\n", ret); 4636 } 4637 4638 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) 4639 { 4640 struct hclge_config_mac_mode_cmd *req; 4641 struct hclge_desc desc; 4642 u32 loop_en; 4643 int ret; 4644 4645 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 4646 /* 1 Read out the MAC mode config at first */ 4647 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 4648 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4649 if (ret) { 4650 dev_err(&hdev->pdev->dev, 4651 "mac loopback get fail, ret =%d.\n", ret); 4652 return ret; 4653 } 4654 4655 /* 2 Then setup the loopback flag */ 4656 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 4657 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 4658 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, en ? 1 : 0); 4659 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, en ? 1 : 0); 4660 4661 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 4662 4663 /* 3 Config mac work mode with loopback flag 4664 * and its original configure parameters 4665 */ 4666 hclge_cmd_reuse_desc(&desc, false); 4667 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4668 if (ret) 4669 dev_err(&hdev->pdev->dev, 4670 "mac loopback set fail, ret =%d.\n", ret); 4671 return ret; 4672 } 4673 4674 static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en, 4675 enum hnae3_loop loop_mode) 4676 { 4677 #define HCLGE_SERDES_RETRY_MS 10 4678 #define HCLGE_SERDES_RETRY_NUM 100 4679 struct hclge_serdes_lb_cmd *req; 4680 struct hclge_desc desc; 4681 int ret, i = 0; 4682 u8 loop_mode_b; 4683 4684 req = (struct hclge_serdes_lb_cmd *)desc.data; 4685 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false); 4686 4687 switch (loop_mode) { 4688 case HNAE3_LOOP_SERIAL_SERDES: 4689 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 4690 break; 4691 case HNAE3_LOOP_PARALLEL_SERDES: 4692 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B; 4693 break; 4694 default: 4695 dev_err(&hdev->pdev->dev, 4696 "unsupported serdes loopback mode %d\n", loop_mode); 4697 return -ENOTSUPP; 4698 } 4699 4700 if (en) { 4701 req->enable = loop_mode_b; 4702 req->mask = loop_mode_b; 4703 } else { 4704 req->mask = loop_mode_b; 4705 } 4706 4707 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4708 if (ret) { 4709 dev_err(&hdev->pdev->dev, 4710 "serdes loopback set fail, ret = %d\n", ret); 4711 return ret; 4712 } 4713 4714 do { 4715 msleep(HCLGE_SERDES_RETRY_MS); 4716 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, 4717 true); 4718 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4719 if (ret) { 4720 dev_err(&hdev->pdev->dev, 4721 "serdes loopback get, ret = %d\n", ret); 4722 return ret; 4723 } 4724 } while (++i < HCLGE_SERDES_RETRY_NUM && 4725 !(req->result & HCLGE_CMD_SERDES_DONE_B)); 4726 4727 if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) { 4728 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n"); 4729 return -EBUSY; 4730 } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) { 4731 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n"); 4732 return -EIO; 4733 } 4734 4735 hclge_cfg_mac_mode(hdev, en); 4736 return 0; 4737 } 4738 4739 static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id, 4740 int stream_id, bool enable) 4741 { 4742 struct hclge_desc desc; 4743 struct hclge_cfg_com_tqp_queue_cmd *req = 4744 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 4745 int ret; 4746 4747 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 4748 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK); 4749 req->stream_id = cpu_to_le16(stream_id); 4750 req->enable |= enable << HCLGE_TQP_ENABLE_B; 4751 4752 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4753 if (ret) 4754 dev_err(&hdev->pdev->dev, 4755 "Tqp enable fail, status =%d.\n", ret); 4756 return ret; 4757 } 4758 4759 static int hclge_set_loopback(struct hnae3_handle *handle, 4760 enum hnae3_loop loop_mode, bool en) 4761 { 4762 struct hclge_vport *vport = hclge_get_vport(handle); 4763 struct hclge_dev *hdev = vport->back; 4764 int i, ret; 4765 4766 switch (loop_mode) { 4767 case HNAE3_LOOP_APP: 4768 ret = hclge_set_app_loopback(hdev, en); 4769 break; 4770 case HNAE3_LOOP_SERIAL_SERDES: 4771 case HNAE3_LOOP_PARALLEL_SERDES: 4772 ret = hclge_set_serdes_loopback(hdev, en, loop_mode); 4773 break; 4774 default: 4775 ret = -ENOTSUPP; 4776 dev_err(&hdev->pdev->dev, 4777 "loop_mode %d is not supported\n", loop_mode); 4778 break; 4779 } 4780 4781 for (i = 0; i < vport->alloc_tqps; i++) { 4782 ret = hclge_tqp_enable(hdev, i, 0, en); 4783 if (ret) 4784 return ret; 4785 } 4786 4787 return 0; 4788 } 4789 4790 static void hclge_reset_tqp_stats(struct hnae3_handle *handle) 4791 { 4792 struct hclge_vport *vport = hclge_get_vport(handle); 4793 struct hnae3_queue *queue; 4794 struct hclge_tqp *tqp; 4795 int i; 4796 4797 for (i = 0; i < vport->alloc_tqps; i++) { 4798 queue = handle->kinfo.tqp[i]; 4799 tqp = container_of(queue, struct hclge_tqp, q); 4800 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 4801 } 4802 } 4803 4804 static int hclge_ae_start(struct hnae3_handle *handle) 4805 { 4806 struct hclge_vport *vport = hclge_get_vport(handle); 4807 struct hclge_dev *hdev = vport->back; 4808 int i; 4809 4810 for (i = 0; i < vport->alloc_tqps; i++) 4811 hclge_tqp_enable(hdev, i, 0, true); 4812 4813 /* mac enable */ 4814 hclge_cfg_mac_mode(hdev, true); 4815 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 4816 mod_timer(&hdev->service_timer, jiffies + HZ); 4817 hdev->hw.mac.link = 0; 4818 4819 /* reset tqp stats */ 4820 hclge_reset_tqp_stats(handle); 4821 4822 hclge_mac_start_phy(hdev); 4823 4824 return 0; 4825 } 4826 4827 static void hclge_ae_stop(struct hnae3_handle *handle) 4828 { 4829 struct hclge_vport *vport = hclge_get_vport(handle); 4830 struct hclge_dev *hdev = vport->back; 4831 int i; 4832 4833 set_bit(HCLGE_STATE_DOWN, &hdev->state); 4834 4835 del_timer_sync(&hdev->service_timer); 4836 cancel_work_sync(&hdev->service_task); 4837 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state); 4838 4839 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { 4840 hclge_mac_stop_phy(hdev); 4841 return; 4842 } 4843 4844 for (i = 0; i < vport->alloc_tqps; i++) 4845 hclge_tqp_enable(hdev, i, 0, false); 4846 4847 /* Mac disable */ 4848 hclge_cfg_mac_mode(hdev, false); 4849 4850 hclge_mac_stop_phy(hdev); 4851 4852 /* reset tqp stats */ 4853 hclge_reset_tqp_stats(handle); 4854 del_timer_sync(&hdev->service_timer); 4855 cancel_work_sync(&hdev->service_task); 4856 hclge_update_link_status(hdev); 4857 } 4858 4859 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 4860 u16 cmdq_resp, u8 resp_code, 4861 enum hclge_mac_vlan_tbl_opcode op) 4862 { 4863 struct hclge_dev *hdev = vport->back; 4864 int return_status = -EIO; 4865 4866 if (cmdq_resp) { 4867 dev_err(&hdev->pdev->dev, 4868 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n", 4869 cmdq_resp); 4870 return -EIO; 4871 } 4872 4873 if (op == HCLGE_MAC_VLAN_ADD) { 4874 if ((!resp_code) || (resp_code == 1)) { 4875 return_status = 0; 4876 } else if (resp_code == 2) { 4877 return_status = -ENOSPC; 4878 dev_err(&hdev->pdev->dev, 4879 "add mac addr failed for uc_overflow.\n"); 4880 } else if (resp_code == 3) { 4881 return_status = -ENOSPC; 4882 dev_err(&hdev->pdev->dev, 4883 "add mac addr failed for mc_overflow.\n"); 4884 } else { 4885 dev_err(&hdev->pdev->dev, 4886 "add mac addr failed for undefined, code=%d.\n", 4887 resp_code); 4888 } 4889 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 4890 if (!resp_code) { 4891 return_status = 0; 4892 } else if (resp_code == 1) { 4893 return_status = -ENOENT; 4894 dev_dbg(&hdev->pdev->dev, 4895 "remove mac addr failed for miss.\n"); 4896 } else { 4897 dev_err(&hdev->pdev->dev, 4898 "remove mac addr failed for undefined, code=%d.\n", 4899 resp_code); 4900 } 4901 } else if (op == HCLGE_MAC_VLAN_LKUP) { 4902 if (!resp_code) { 4903 return_status = 0; 4904 } else if (resp_code == 1) { 4905 return_status = -ENOENT; 4906 dev_dbg(&hdev->pdev->dev, 4907 "lookup mac addr failed for miss.\n"); 4908 } else { 4909 dev_err(&hdev->pdev->dev, 4910 "lookup mac addr failed for undefined, code=%d.\n", 4911 resp_code); 4912 } 4913 } else { 4914 return_status = -EINVAL; 4915 dev_err(&hdev->pdev->dev, 4916 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n", 4917 op); 4918 } 4919 4920 return return_status; 4921 } 4922 4923 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 4924 { 4925 int word_num; 4926 int bit_num; 4927 4928 if (vfid > 255 || vfid < 0) 4929 return -EIO; 4930 4931 if (vfid >= 0 && vfid <= 191) { 4932 word_num = vfid / 32; 4933 bit_num = vfid % 32; 4934 if (clr) 4935 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 4936 else 4937 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 4938 } else { 4939 word_num = (vfid - 192) / 32; 4940 bit_num = vfid % 32; 4941 if (clr) 4942 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 4943 else 4944 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 4945 } 4946 4947 return 0; 4948 } 4949 4950 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 4951 { 4952 #define HCLGE_DESC_NUMBER 3 4953 #define HCLGE_FUNC_NUMBER_PER_DESC 6 4954 int i, j; 4955 4956 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 4957 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 4958 if (desc[i].data[j]) 4959 return false; 4960 4961 return true; 4962 } 4963 4964 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 4965 const u8 *addr) 4966 { 4967 const unsigned char *mac_addr = addr; 4968 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 4969 (mac_addr[0]) | (mac_addr[1] << 8); 4970 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 4971 4972 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 4973 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 4974 } 4975 4976 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 4977 struct hclge_mac_vlan_tbl_entry_cmd *req) 4978 { 4979 struct hclge_dev *hdev = vport->back; 4980 struct hclge_desc desc; 4981 u8 resp_code; 4982 u16 retval; 4983 int ret; 4984 4985 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 4986 4987 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4988 4989 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4990 if (ret) { 4991 dev_err(&hdev->pdev->dev, 4992 "del mac addr failed for cmd_send, ret =%d.\n", 4993 ret); 4994 return ret; 4995 } 4996 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 4997 retval = le16_to_cpu(desc.retval); 4998 4999 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 5000 HCLGE_MAC_VLAN_REMOVE); 5001 } 5002 5003 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 5004 struct hclge_mac_vlan_tbl_entry_cmd *req, 5005 struct hclge_desc *desc, 5006 bool is_mc) 5007 { 5008 struct hclge_dev *hdev = vport->back; 5009 u8 resp_code; 5010 u16 retval; 5011 int ret; 5012 5013 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 5014 if (is_mc) { 5015 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 5016 memcpy(desc[0].data, 5017 req, 5018 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 5019 hclge_cmd_setup_basic_desc(&desc[1], 5020 HCLGE_OPC_MAC_VLAN_ADD, 5021 true); 5022 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 5023 hclge_cmd_setup_basic_desc(&desc[2], 5024 HCLGE_OPC_MAC_VLAN_ADD, 5025 true); 5026 ret = hclge_cmd_send(&hdev->hw, desc, 3); 5027 } else { 5028 memcpy(desc[0].data, 5029 req, 5030 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 5031 ret = hclge_cmd_send(&hdev->hw, desc, 1); 5032 } 5033 if (ret) { 5034 dev_err(&hdev->pdev->dev, 5035 "lookup mac addr failed for cmd_send, ret =%d.\n", 5036 ret); 5037 return ret; 5038 } 5039 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 5040 retval = le16_to_cpu(desc[0].retval); 5041 5042 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 5043 HCLGE_MAC_VLAN_LKUP); 5044 } 5045 5046 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 5047 struct hclge_mac_vlan_tbl_entry_cmd *req, 5048 struct hclge_desc *mc_desc) 5049 { 5050 struct hclge_dev *hdev = vport->back; 5051 int cfg_status; 5052 u8 resp_code; 5053 u16 retval; 5054 int ret; 5055 5056 if (!mc_desc) { 5057 struct hclge_desc desc; 5058 5059 hclge_cmd_setup_basic_desc(&desc, 5060 HCLGE_OPC_MAC_VLAN_ADD, 5061 false); 5062 memcpy(desc.data, req, 5063 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 5064 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5065 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 5066 retval = le16_to_cpu(desc.retval); 5067 5068 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 5069 resp_code, 5070 HCLGE_MAC_VLAN_ADD); 5071 } else { 5072 hclge_cmd_reuse_desc(&mc_desc[0], false); 5073 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 5074 hclge_cmd_reuse_desc(&mc_desc[1], false); 5075 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 5076 hclge_cmd_reuse_desc(&mc_desc[2], false); 5077 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT); 5078 memcpy(mc_desc[0].data, req, 5079 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 5080 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 5081 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 5082 retval = le16_to_cpu(mc_desc[0].retval); 5083 5084 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 5085 resp_code, 5086 HCLGE_MAC_VLAN_ADD); 5087 } 5088 5089 if (ret) { 5090 dev_err(&hdev->pdev->dev, 5091 "add mac addr failed for cmd_send, ret =%d.\n", 5092 ret); 5093 return ret; 5094 } 5095 5096 return cfg_status; 5097 } 5098 5099 static int hclge_init_umv_space(struct hclge_dev *hdev) 5100 { 5101 u16 allocated_size = 0; 5102 int ret; 5103 5104 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size, 5105 true); 5106 if (ret) 5107 return ret; 5108 5109 if (allocated_size < hdev->wanted_umv_size) 5110 dev_warn(&hdev->pdev->dev, 5111 "Alloc umv space failed, want %d, get %d\n", 5112 hdev->wanted_umv_size, allocated_size); 5113 5114 mutex_init(&hdev->umv_mutex); 5115 hdev->max_umv_size = allocated_size; 5116 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_req_vfs + 2); 5117 hdev->share_umv_size = hdev->priv_umv_size + 5118 hdev->max_umv_size % (hdev->num_req_vfs + 2); 5119 5120 return 0; 5121 } 5122 5123 static int hclge_uninit_umv_space(struct hclge_dev *hdev) 5124 { 5125 int ret; 5126 5127 if (hdev->max_umv_size > 0) { 5128 ret = hclge_set_umv_space(hdev, hdev->max_umv_size, NULL, 5129 false); 5130 if (ret) 5131 return ret; 5132 hdev->max_umv_size = 0; 5133 } 5134 mutex_destroy(&hdev->umv_mutex); 5135 5136 return 0; 5137 } 5138 5139 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 5140 u16 *allocated_size, bool is_alloc) 5141 { 5142 struct hclge_umv_spc_alc_cmd *req; 5143 struct hclge_desc desc; 5144 int ret; 5145 5146 req = (struct hclge_umv_spc_alc_cmd *)desc.data; 5147 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false); 5148 hnae3_set_bit(req->allocate, HCLGE_UMV_SPC_ALC_B, !is_alloc); 5149 req->space_size = cpu_to_le32(space_size); 5150 5151 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5152 if (ret) { 5153 dev_err(&hdev->pdev->dev, 5154 "%s umv space failed for cmd_send, ret =%d\n", 5155 is_alloc ? "allocate" : "free", ret); 5156 return ret; 5157 } 5158 5159 if (is_alloc && allocated_size) 5160 *allocated_size = le32_to_cpu(desc.data[1]); 5161 5162 return 0; 5163 } 5164 5165 static void hclge_reset_umv_space(struct hclge_dev *hdev) 5166 { 5167 struct hclge_vport *vport; 5168 int i; 5169 5170 for (i = 0; i < hdev->num_alloc_vport; i++) { 5171 vport = &hdev->vport[i]; 5172 vport->used_umv_num = 0; 5173 } 5174 5175 mutex_lock(&hdev->umv_mutex); 5176 hdev->share_umv_size = hdev->priv_umv_size + 5177 hdev->max_umv_size % (hdev->num_req_vfs + 2); 5178 mutex_unlock(&hdev->umv_mutex); 5179 } 5180 5181 static bool hclge_is_umv_space_full(struct hclge_vport *vport) 5182 { 5183 struct hclge_dev *hdev = vport->back; 5184 bool is_full; 5185 5186 mutex_lock(&hdev->umv_mutex); 5187 is_full = (vport->used_umv_num >= hdev->priv_umv_size && 5188 hdev->share_umv_size == 0); 5189 mutex_unlock(&hdev->umv_mutex); 5190 5191 return is_full; 5192 } 5193 5194 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free) 5195 { 5196 struct hclge_dev *hdev = vport->back; 5197 5198 mutex_lock(&hdev->umv_mutex); 5199 if (is_free) { 5200 if (vport->used_umv_num > hdev->priv_umv_size) 5201 hdev->share_umv_size++; 5202 vport->used_umv_num--; 5203 } else { 5204 if (vport->used_umv_num >= hdev->priv_umv_size) 5205 hdev->share_umv_size--; 5206 vport->used_umv_num++; 5207 } 5208 mutex_unlock(&hdev->umv_mutex); 5209 } 5210 5211 static int hclge_add_uc_addr(struct hnae3_handle *handle, 5212 const unsigned char *addr) 5213 { 5214 struct hclge_vport *vport = hclge_get_vport(handle); 5215 5216 return hclge_add_uc_addr_common(vport, addr); 5217 } 5218 5219 int hclge_add_uc_addr_common(struct hclge_vport *vport, 5220 const unsigned char *addr) 5221 { 5222 struct hclge_dev *hdev = vport->back; 5223 struct hclge_mac_vlan_tbl_entry_cmd req; 5224 struct hclge_desc desc; 5225 u16 egress_port = 0; 5226 int ret; 5227 5228 /* mac addr check */ 5229 if (is_zero_ether_addr(addr) || 5230 is_broadcast_ether_addr(addr) || 5231 is_multicast_ether_addr(addr)) { 5232 dev_err(&hdev->pdev->dev, 5233 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n", 5234 addr, 5235 is_zero_ether_addr(addr), 5236 is_broadcast_ether_addr(addr), 5237 is_multicast_ether_addr(addr)); 5238 return -EINVAL; 5239 } 5240 5241 memset(&req, 0, sizeof(req)); 5242 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 5243 5244 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 5245 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 5246 5247 req.egress_port = cpu_to_le16(egress_port); 5248 5249 hclge_prepare_mac_addr(&req, addr); 5250 5251 /* Lookup the mac address in the mac_vlan table, and add 5252 * it if the entry is inexistent. Repeated unicast entry 5253 * is not allowed in the mac vlan table. 5254 */ 5255 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 5256 if (ret == -ENOENT) { 5257 if (!hclge_is_umv_space_full(vport)) { 5258 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL); 5259 if (!ret) 5260 hclge_update_umv_space(vport, false); 5261 return ret; 5262 } 5263 5264 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n", 5265 hdev->priv_umv_size); 5266 5267 return -ENOSPC; 5268 } 5269 5270 /* check if we just hit the duplicate */ 5271 if (!ret) 5272 ret = -EINVAL; 5273 5274 dev_err(&hdev->pdev->dev, 5275 "PF failed to add unicast entry(%pM) in the MAC table\n", 5276 addr); 5277 5278 return ret; 5279 } 5280 5281 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 5282 const unsigned char *addr) 5283 { 5284 struct hclge_vport *vport = hclge_get_vport(handle); 5285 5286 return hclge_rm_uc_addr_common(vport, addr); 5287 } 5288 5289 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 5290 const unsigned char *addr) 5291 { 5292 struct hclge_dev *hdev = vport->back; 5293 struct hclge_mac_vlan_tbl_entry_cmd req; 5294 int ret; 5295 5296 /* mac addr check */ 5297 if (is_zero_ether_addr(addr) || 5298 is_broadcast_ether_addr(addr) || 5299 is_multicast_ether_addr(addr)) { 5300 dev_dbg(&hdev->pdev->dev, 5301 "Remove mac err! invalid mac:%pM.\n", 5302 addr); 5303 return -EINVAL; 5304 } 5305 5306 memset(&req, 0, sizeof(req)); 5307 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 5308 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 5309 hclge_prepare_mac_addr(&req, addr); 5310 ret = hclge_remove_mac_vlan_tbl(vport, &req); 5311 if (!ret) 5312 hclge_update_umv_space(vport, true); 5313 5314 return ret; 5315 } 5316 5317 static int hclge_add_mc_addr(struct hnae3_handle *handle, 5318 const unsigned char *addr) 5319 { 5320 struct hclge_vport *vport = hclge_get_vport(handle); 5321 5322 return hclge_add_mc_addr_common(vport, addr); 5323 } 5324 5325 int hclge_add_mc_addr_common(struct hclge_vport *vport, 5326 const unsigned char *addr) 5327 { 5328 struct hclge_dev *hdev = vport->back; 5329 struct hclge_mac_vlan_tbl_entry_cmd req; 5330 struct hclge_desc desc[3]; 5331 int status; 5332 5333 /* mac addr check */ 5334 if (!is_multicast_ether_addr(addr)) { 5335 dev_err(&hdev->pdev->dev, 5336 "Add mc mac err! invalid mac:%pM.\n", 5337 addr); 5338 return -EINVAL; 5339 } 5340 memset(&req, 0, sizeof(req)); 5341 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 5342 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 5343 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 5344 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 5345 hclge_prepare_mac_addr(&req, addr); 5346 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 5347 if (!status) { 5348 /* This mac addr exist, update VFID for it */ 5349 hclge_update_desc_vfid(desc, vport->vport_id, false); 5350 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 5351 } else { 5352 /* This mac addr do not exist, add new entry for it */ 5353 memset(desc[0].data, 0, sizeof(desc[0].data)); 5354 memset(desc[1].data, 0, sizeof(desc[0].data)); 5355 memset(desc[2].data, 0, sizeof(desc[0].data)); 5356 hclge_update_desc_vfid(desc, vport->vport_id, false); 5357 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 5358 } 5359 5360 if (status == -ENOSPC) 5361 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n"); 5362 5363 return status; 5364 } 5365 5366 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 5367 const unsigned char *addr) 5368 { 5369 struct hclge_vport *vport = hclge_get_vport(handle); 5370 5371 return hclge_rm_mc_addr_common(vport, addr); 5372 } 5373 5374 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 5375 const unsigned char *addr) 5376 { 5377 struct hclge_dev *hdev = vport->back; 5378 struct hclge_mac_vlan_tbl_entry_cmd req; 5379 enum hclge_cmd_status status; 5380 struct hclge_desc desc[3]; 5381 5382 /* mac addr check */ 5383 if (!is_multicast_ether_addr(addr)) { 5384 dev_dbg(&hdev->pdev->dev, 5385 "Remove mc mac err! invalid mac:%pM.\n", 5386 addr); 5387 return -EINVAL; 5388 } 5389 5390 memset(&req, 0, sizeof(req)); 5391 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 5392 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 5393 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 5394 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 5395 hclge_prepare_mac_addr(&req, addr); 5396 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 5397 if (!status) { 5398 /* This mac addr exist, remove this handle's VFID for it */ 5399 hclge_update_desc_vfid(desc, vport->vport_id, true); 5400 5401 if (hclge_is_all_function_id_zero(desc)) 5402 /* All the vfid is zero, so need to delete this entry */ 5403 status = hclge_remove_mac_vlan_tbl(vport, &req); 5404 else 5405 /* Not all the vfid is zero, update the vfid */ 5406 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 5407 5408 } else { 5409 /* Maybe this mac address is in mta table, but it cannot be 5410 * deleted here because an entry of mta represents an address 5411 * range rather than a specific address. the delete action to 5412 * all entries will take effect in update_mta_status called by 5413 * hns3_nic_set_rx_mode. 5414 */ 5415 status = 0; 5416 } 5417 5418 return status; 5419 } 5420 5421 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 5422 u16 cmdq_resp, u8 resp_code) 5423 { 5424 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 5425 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 5426 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 5427 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 5428 5429 int return_status; 5430 5431 if (cmdq_resp) { 5432 dev_err(&hdev->pdev->dev, 5433 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n", 5434 cmdq_resp); 5435 return -EIO; 5436 } 5437 5438 switch (resp_code) { 5439 case HCLGE_ETHERTYPE_SUCCESS_ADD: 5440 case HCLGE_ETHERTYPE_ALREADY_ADD: 5441 return_status = 0; 5442 break; 5443 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 5444 dev_err(&hdev->pdev->dev, 5445 "add mac ethertype failed for manager table overflow.\n"); 5446 return_status = -EIO; 5447 break; 5448 case HCLGE_ETHERTYPE_KEY_CONFLICT: 5449 dev_err(&hdev->pdev->dev, 5450 "add mac ethertype failed for key conflict.\n"); 5451 return_status = -EIO; 5452 break; 5453 default: 5454 dev_err(&hdev->pdev->dev, 5455 "add mac ethertype failed for undefined, code=%d.\n", 5456 resp_code); 5457 return_status = -EIO; 5458 } 5459 5460 return return_status; 5461 } 5462 5463 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 5464 const struct hclge_mac_mgr_tbl_entry_cmd *req) 5465 { 5466 struct hclge_desc desc; 5467 u8 resp_code; 5468 u16 retval; 5469 int ret; 5470 5471 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 5472 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 5473 5474 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5475 if (ret) { 5476 dev_err(&hdev->pdev->dev, 5477 "add mac ethertype failed for cmd_send, ret =%d.\n", 5478 ret); 5479 return ret; 5480 } 5481 5482 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 5483 retval = le16_to_cpu(desc.retval); 5484 5485 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 5486 } 5487 5488 static int init_mgr_tbl(struct hclge_dev *hdev) 5489 { 5490 int ret; 5491 int i; 5492 5493 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 5494 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 5495 if (ret) { 5496 dev_err(&hdev->pdev->dev, 5497 "add mac ethertype failed, ret =%d.\n", 5498 ret); 5499 return ret; 5500 } 5501 } 5502 5503 return 0; 5504 } 5505 5506 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 5507 { 5508 struct hclge_vport *vport = hclge_get_vport(handle); 5509 struct hclge_dev *hdev = vport->back; 5510 5511 ether_addr_copy(p, hdev->hw.mac.mac_addr); 5512 } 5513 5514 static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p, 5515 bool is_first) 5516 { 5517 const unsigned char *new_addr = (const unsigned char *)p; 5518 struct hclge_vport *vport = hclge_get_vport(handle); 5519 struct hclge_dev *hdev = vport->back; 5520 int ret; 5521 5522 /* mac addr check */ 5523 if (is_zero_ether_addr(new_addr) || 5524 is_broadcast_ether_addr(new_addr) || 5525 is_multicast_ether_addr(new_addr)) { 5526 dev_err(&hdev->pdev->dev, 5527 "Change uc mac err! invalid mac:%p.\n", 5528 new_addr); 5529 return -EINVAL; 5530 } 5531 5532 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr)) 5533 dev_warn(&hdev->pdev->dev, 5534 "remove old uc mac address fail.\n"); 5535 5536 ret = hclge_add_uc_addr(handle, new_addr); 5537 if (ret) { 5538 dev_err(&hdev->pdev->dev, 5539 "add uc mac address fail, ret =%d.\n", 5540 ret); 5541 5542 if (!is_first && 5543 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr)) 5544 dev_err(&hdev->pdev->dev, 5545 "restore uc mac address fail.\n"); 5546 5547 return -EIO; 5548 } 5549 5550 ret = hclge_pause_addr_cfg(hdev, new_addr); 5551 if (ret) { 5552 dev_err(&hdev->pdev->dev, 5553 "configure mac pause address fail, ret =%d.\n", 5554 ret); 5555 return -EIO; 5556 } 5557 5558 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 5559 5560 return 0; 5561 } 5562 5563 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr, 5564 int cmd) 5565 { 5566 struct hclge_vport *vport = hclge_get_vport(handle); 5567 struct hclge_dev *hdev = vport->back; 5568 5569 if (!hdev->hw.mac.phydev) 5570 return -EOPNOTSUPP; 5571 5572 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd); 5573 } 5574 5575 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 5576 u8 fe_type, bool filter_en) 5577 { 5578 struct hclge_vlan_filter_ctrl_cmd *req; 5579 struct hclge_desc desc; 5580 int ret; 5581 5582 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false); 5583 5584 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 5585 req->vlan_type = vlan_type; 5586 req->vlan_fe = filter_en ? fe_type : 0; 5587 5588 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5589 if (ret) 5590 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n", 5591 ret); 5592 5593 return ret; 5594 } 5595 5596 #define HCLGE_FILTER_TYPE_VF 0 5597 #define HCLGE_FILTER_TYPE_PORT 1 5598 #define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0) 5599 #define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0) 5600 #define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1) 5601 #define HCLGE_FILTER_FE_ROCE_INGRESS_B BIT(2) 5602 #define HCLGE_FILTER_FE_ROCE_EGRESS_B BIT(3) 5603 #define HCLGE_FILTER_FE_EGRESS (HCLGE_FILTER_FE_NIC_EGRESS_B \ 5604 | HCLGE_FILTER_FE_ROCE_EGRESS_B) 5605 #define HCLGE_FILTER_FE_INGRESS (HCLGE_FILTER_FE_NIC_INGRESS_B \ 5606 | HCLGE_FILTER_FE_ROCE_INGRESS_B) 5607 5608 static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 5609 { 5610 struct hclge_vport *vport = hclge_get_vport(handle); 5611 struct hclge_dev *hdev = vport->back; 5612 5613 if (hdev->pdev->revision >= 0x21) { 5614 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 5615 HCLGE_FILTER_FE_EGRESS, enable); 5616 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 5617 HCLGE_FILTER_FE_INGRESS, enable); 5618 } else { 5619 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 5620 HCLGE_FILTER_FE_EGRESS_V1_B, enable); 5621 } 5622 if (enable) 5623 handle->netdev_flags |= HNAE3_VLAN_FLTR; 5624 else 5625 handle->netdev_flags &= ~HNAE3_VLAN_FLTR; 5626 } 5627 5628 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid, 5629 bool is_kill, u16 vlan, u8 qos, 5630 __be16 proto) 5631 { 5632 #define HCLGE_MAX_VF_BYTES 16 5633 struct hclge_vlan_filter_vf_cfg_cmd *req0; 5634 struct hclge_vlan_filter_vf_cfg_cmd *req1; 5635 struct hclge_desc desc[2]; 5636 u8 vf_byte_val; 5637 u8 vf_byte_off; 5638 int ret; 5639 5640 hclge_cmd_setup_basic_desc(&desc[0], 5641 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 5642 hclge_cmd_setup_basic_desc(&desc[1], 5643 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 5644 5645 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 5646 5647 vf_byte_off = vfid / 8; 5648 vf_byte_val = 1 << (vfid % 8); 5649 5650 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 5651 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 5652 5653 req0->vlan_id = cpu_to_le16(vlan); 5654 req0->vlan_cfg = is_kill; 5655 5656 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 5657 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 5658 else 5659 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 5660 5661 ret = hclge_cmd_send(&hdev->hw, desc, 2); 5662 if (ret) { 5663 dev_err(&hdev->pdev->dev, 5664 "Send vf vlan command fail, ret =%d.\n", 5665 ret); 5666 return ret; 5667 } 5668 5669 if (!is_kill) { 5670 #define HCLGE_VF_VLAN_NO_ENTRY 2 5671 if (!req0->resp_code || req0->resp_code == 1) 5672 return 0; 5673 5674 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 5675 dev_warn(&hdev->pdev->dev, 5676 "vf vlan table is full, vf vlan filter is disabled\n"); 5677 return 0; 5678 } 5679 5680 dev_err(&hdev->pdev->dev, 5681 "Add vf vlan filter fail, ret =%d.\n", 5682 req0->resp_code); 5683 } else { 5684 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 5685 if (!req0->resp_code) 5686 return 0; 5687 5688 if (req0->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) { 5689 dev_warn(&hdev->pdev->dev, 5690 "vlan %d filter is not in vf vlan table\n", 5691 vlan); 5692 return 0; 5693 } 5694 5695 dev_err(&hdev->pdev->dev, 5696 "Kill vf vlan filter fail, ret =%d.\n", 5697 req0->resp_code); 5698 } 5699 5700 return -EIO; 5701 } 5702 5703 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 5704 u16 vlan_id, bool is_kill) 5705 { 5706 struct hclge_vlan_filter_pf_cfg_cmd *req; 5707 struct hclge_desc desc; 5708 u8 vlan_offset_byte_val; 5709 u8 vlan_offset_byte; 5710 u8 vlan_offset_160; 5711 int ret; 5712 5713 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 5714 5715 vlan_offset_160 = vlan_id / 160; 5716 vlan_offset_byte = (vlan_id % 160) / 8; 5717 vlan_offset_byte_val = 1 << (vlan_id % 8); 5718 5719 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 5720 req->vlan_offset = vlan_offset_160; 5721 req->vlan_cfg = is_kill; 5722 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 5723 5724 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5725 if (ret) 5726 dev_err(&hdev->pdev->dev, 5727 "port vlan command, send fail, ret =%d.\n", ret); 5728 return ret; 5729 } 5730 5731 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 5732 u16 vport_id, u16 vlan_id, u8 qos, 5733 bool is_kill) 5734 { 5735 u16 vport_idx, vport_num = 0; 5736 int ret; 5737 5738 if (is_kill && !vlan_id) 5739 return 0; 5740 5741 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id, 5742 0, proto); 5743 if (ret) { 5744 dev_err(&hdev->pdev->dev, 5745 "Set %d vport vlan filter config fail, ret =%d.\n", 5746 vport_id, ret); 5747 return ret; 5748 } 5749 5750 /* vlan 0 may be added twice when 8021q module is enabled */ 5751 if (!is_kill && !vlan_id && 5752 test_bit(vport_id, hdev->vlan_table[vlan_id])) 5753 return 0; 5754 5755 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 5756 dev_err(&hdev->pdev->dev, 5757 "Add port vlan failed, vport %d is already in vlan %d\n", 5758 vport_id, vlan_id); 5759 return -EINVAL; 5760 } 5761 5762 if (is_kill && 5763 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 5764 dev_err(&hdev->pdev->dev, 5765 "Delete port vlan failed, vport %d is not in vlan %d\n", 5766 vport_id, vlan_id); 5767 return -EINVAL; 5768 } 5769 5770 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 5771 vport_num++; 5772 5773 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 5774 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 5775 is_kill); 5776 5777 return ret; 5778 } 5779 5780 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 5781 u16 vlan_id, bool is_kill) 5782 { 5783 struct hclge_vport *vport = hclge_get_vport(handle); 5784 struct hclge_dev *hdev = vport->back; 5785 5786 return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id, 5787 0, is_kill); 5788 } 5789 5790 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 5791 u16 vlan, u8 qos, __be16 proto) 5792 { 5793 struct hclge_vport *vport = hclge_get_vport(handle); 5794 struct hclge_dev *hdev = vport->back; 5795 5796 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7)) 5797 return -EINVAL; 5798 if (proto != htons(ETH_P_8021Q)) 5799 return -EPROTONOSUPPORT; 5800 5801 return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false); 5802 } 5803 5804 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 5805 { 5806 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 5807 struct hclge_vport_vtag_tx_cfg_cmd *req; 5808 struct hclge_dev *hdev = vport->back; 5809 struct hclge_desc desc; 5810 int status; 5811 5812 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 5813 5814 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 5815 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 5816 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 5817 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 5818 vcfg->accept_tag1 ? 1 : 0); 5819 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 5820 vcfg->accept_untag1 ? 1 : 0); 5821 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 5822 vcfg->accept_tag2 ? 1 : 0); 5823 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 5824 vcfg->accept_untag2 ? 1 : 0); 5825 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 5826 vcfg->insert_tag1_en ? 1 : 0); 5827 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 5828 vcfg->insert_tag2_en ? 1 : 0); 5829 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 5830 5831 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 5832 req->vf_bitmap[req->vf_offset] = 5833 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 5834 5835 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5836 if (status) 5837 dev_err(&hdev->pdev->dev, 5838 "Send port txvlan cfg command fail, ret =%d\n", 5839 status); 5840 5841 return status; 5842 } 5843 5844 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 5845 { 5846 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 5847 struct hclge_vport_vtag_rx_cfg_cmd *req; 5848 struct hclge_dev *hdev = vport->back; 5849 struct hclge_desc desc; 5850 int status; 5851 5852 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 5853 5854 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 5855 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 5856 vcfg->strip_tag1_en ? 1 : 0); 5857 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 5858 vcfg->strip_tag2_en ? 1 : 0); 5859 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 5860 vcfg->vlan1_vlan_prionly ? 1 : 0); 5861 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 5862 vcfg->vlan2_vlan_prionly ? 1 : 0); 5863 5864 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 5865 req->vf_bitmap[req->vf_offset] = 5866 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 5867 5868 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5869 if (status) 5870 dev_err(&hdev->pdev->dev, 5871 "Send port rxvlan cfg command fail, ret =%d\n", 5872 status); 5873 5874 return status; 5875 } 5876 5877 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 5878 { 5879 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 5880 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 5881 struct hclge_desc desc; 5882 int status; 5883 5884 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 5885 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 5886 rx_req->ot_fst_vlan_type = 5887 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 5888 rx_req->ot_sec_vlan_type = 5889 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 5890 rx_req->in_fst_vlan_type = 5891 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 5892 rx_req->in_sec_vlan_type = 5893 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 5894 5895 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5896 if (status) { 5897 dev_err(&hdev->pdev->dev, 5898 "Send rxvlan protocol type command fail, ret =%d\n", 5899 status); 5900 return status; 5901 } 5902 5903 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 5904 5905 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data; 5906 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 5907 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 5908 5909 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5910 if (status) 5911 dev_err(&hdev->pdev->dev, 5912 "Send txvlan protocol type command fail, ret =%d\n", 5913 status); 5914 5915 return status; 5916 } 5917 5918 static int hclge_init_vlan_config(struct hclge_dev *hdev) 5919 { 5920 #define HCLGE_DEF_VLAN_TYPE 0x8100 5921 5922 struct hnae3_handle *handle = &hdev->vport[0].nic; 5923 struct hclge_vport *vport; 5924 int ret; 5925 int i; 5926 5927 if (hdev->pdev->revision >= 0x21) { 5928 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 5929 HCLGE_FILTER_FE_EGRESS, true); 5930 if (ret) 5931 return ret; 5932 5933 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 5934 HCLGE_FILTER_FE_INGRESS, true); 5935 if (ret) 5936 return ret; 5937 } else { 5938 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 5939 HCLGE_FILTER_FE_EGRESS_V1_B, 5940 true); 5941 if (ret) 5942 return ret; 5943 } 5944 5945 handle->netdev_flags |= HNAE3_VLAN_FLTR; 5946 5947 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE; 5948 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE; 5949 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE; 5950 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE; 5951 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE; 5952 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE; 5953 5954 ret = hclge_set_vlan_protocol_type(hdev); 5955 if (ret) 5956 return ret; 5957 5958 for (i = 0; i < hdev->num_alloc_vport; i++) { 5959 vport = &hdev->vport[i]; 5960 vport->txvlan_cfg.accept_tag1 = true; 5961 vport->txvlan_cfg.accept_untag1 = true; 5962 5963 /* accept_tag2 and accept_untag2 are not supported on 5964 * pdev revision(0x20), new revision support them. The 5965 * value of this two fields will not return error when driver 5966 * send command to fireware in revision(0x20). 5967 * This two fields can not configured by user. 5968 */ 5969 vport->txvlan_cfg.accept_tag2 = true; 5970 vport->txvlan_cfg.accept_untag2 = true; 5971 5972 vport->txvlan_cfg.insert_tag1_en = false; 5973 vport->txvlan_cfg.insert_tag2_en = false; 5974 vport->txvlan_cfg.default_tag1 = 0; 5975 vport->txvlan_cfg.default_tag2 = 0; 5976 5977 ret = hclge_set_vlan_tx_offload_cfg(vport); 5978 if (ret) 5979 return ret; 5980 5981 vport->rxvlan_cfg.strip_tag1_en = false; 5982 vport->rxvlan_cfg.strip_tag2_en = true; 5983 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 5984 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 5985 5986 ret = hclge_set_vlan_rx_offload_cfg(vport); 5987 if (ret) 5988 return ret; 5989 } 5990 5991 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 5992 } 5993 5994 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 5995 { 5996 struct hclge_vport *vport = hclge_get_vport(handle); 5997 5998 vport->rxvlan_cfg.strip_tag1_en = false; 5999 vport->rxvlan_cfg.strip_tag2_en = enable; 6000 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 6001 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 6002 6003 return hclge_set_vlan_rx_offload_cfg(vport); 6004 } 6005 6006 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu) 6007 { 6008 struct hclge_config_max_frm_size_cmd *req; 6009 struct hclge_desc desc; 6010 int max_frm_size; 6011 int ret; 6012 6013 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 6014 6015 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 6016 max_frm_size > HCLGE_MAC_MAX_FRAME) 6017 return -EINVAL; 6018 6019 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 6020 6021 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 6022 6023 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 6024 req->max_frm_size = cpu_to_le16(max_frm_size); 6025 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 6026 6027 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 6028 if (ret) 6029 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret); 6030 else 6031 hdev->mps = max_frm_size; 6032 6033 return ret; 6034 } 6035 6036 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 6037 { 6038 struct hclge_vport *vport = hclge_get_vport(handle); 6039 struct hclge_dev *hdev = vport->back; 6040 int ret; 6041 6042 ret = hclge_set_mac_mtu(hdev, new_mtu); 6043 if (ret) { 6044 dev_err(&hdev->pdev->dev, 6045 "Change mtu fail, ret =%d\n", ret); 6046 return ret; 6047 } 6048 6049 ret = hclge_buffer_alloc(hdev); 6050 if (ret) 6051 dev_err(&hdev->pdev->dev, 6052 "Allocate buffer fail, ret =%d\n", ret); 6053 6054 return ret; 6055 } 6056 6057 static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id, 6058 bool enable) 6059 { 6060 struct hclge_reset_tqp_queue_cmd *req; 6061 struct hclge_desc desc; 6062 int ret; 6063 6064 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 6065 6066 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 6067 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK); 6068 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable); 6069 6070 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 6071 if (ret) { 6072 dev_err(&hdev->pdev->dev, 6073 "Send tqp reset cmd error, status =%d\n", ret); 6074 return ret; 6075 } 6076 6077 return 0; 6078 } 6079 6080 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id) 6081 { 6082 struct hclge_reset_tqp_queue_cmd *req; 6083 struct hclge_desc desc; 6084 int ret; 6085 6086 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 6087 6088 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 6089 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK); 6090 6091 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 6092 if (ret) { 6093 dev_err(&hdev->pdev->dev, 6094 "Get reset status error, status =%d\n", ret); 6095 return ret; 6096 } 6097 6098 return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 6099 } 6100 6101 static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, 6102 u16 queue_id) 6103 { 6104 struct hnae3_queue *queue; 6105 struct hclge_tqp *tqp; 6106 6107 queue = handle->kinfo.tqp[queue_id]; 6108 tqp = container_of(queue, struct hclge_tqp, q); 6109 6110 return tqp->index; 6111 } 6112 6113 int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 6114 { 6115 struct hclge_vport *vport = hclge_get_vport(handle); 6116 struct hclge_dev *hdev = vport->back; 6117 int reset_try_times = 0; 6118 int reset_status; 6119 u16 queue_gid; 6120 int ret = 0; 6121 6122 queue_gid = hclge_covert_handle_qid_global(handle, queue_id); 6123 6124 ret = hclge_tqp_enable(hdev, queue_id, 0, false); 6125 if (ret) { 6126 dev_err(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret); 6127 return ret; 6128 } 6129 6130 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true); 6131 if (ret) { 6132 dev_err(&hdev->pdev->dev, 6133 "Send reset tqp cmd fail, ret = %d\n", ret); 6134 return ret; 6135 } 6136 6137 reset_try_times = 0; 6138 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 6139 /* Wait for tqp hw reset */ 6140 msleep(20); 6141 reset_status = hclge_get_reset_status(hdev, queue_gid); 6142 if (reset_status) 6143 break; 6144 } 6145 6146 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 6147 dev_err(&hdev->pdev->dev, "Reset TQP fail\n"); 6148 return ret; 6149 } 6150 6151 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false); 6152 if (ret) 6153 dev_err(&hdev->pdev->dev, 6154 "Deassert the soft reset fail, ret = %d\n", ret); 6155 6156 return ret; 6157 } 6158 6159 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id) 6160 { 6161 struct hclge_dev *hdev = vport->back; 6162 int reset_try_times = 0; 6163 int reset_status; 6164 u16 queue_gid; 6165 int ret; 6166 6167 queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id); 6168 6169 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true); 6170 if (ret) { 6171 dev_warn(&hdev->pdev->dev, 6172 "Send reset tqp cmd fail, ret = %d\n", ret); 6173 return; 6174 } 6175 6176 reset_try_times = 0; 6177 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 6178 /* Wait for tqp hw reset */ 6179 msleep(20); 6180 reset_status = hclge_get_reset_status(hdev, queue_gid); 6181 if (reset_status) 6182 break; 6183 } 6184 6185 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 6186 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n"); 6187 return; 6188 } 6189 6190 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false); 6191 if (ret) 6192 dev_warn(&hdev->pdev->dev, 6193 "Deassert the soft reset fail, ret = %d\n", ret); 6194 } 6195 6196 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 6197 { 6198 struct hclge_vport *vport = hclge_get_vport(handle); 6199 struct hclge_dev *hdev = vport->back; 6200 6201 return hdev->fw_version; 6202 } 6203 6204 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 6205 { 6206 struct phy_device *phydev = hdev->hw.mac.phydev; 6207 6208 if (!phydev) 6209 return; 6210 6211 phy_set_asym_pause(phydev, rx_en, tx_en); 6212 } 6213 6214 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 6215 { 6216 int ret; 6217 6218 if (rx_en && tx_en) 6219 hdev->fc_mode_last_time = HCLGE_FC_FULL; 6220 else if (rx_en && !tx_en) 6221 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 6222 else if (!rx_en && tx_en) 6223 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 6224 else 6225 hdev->fc_mode_last_time = HCLGE_FC_NONE; 6226 6227 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 6228 return 0; 6229 6230 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 6231 if (ret) { 6232 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n", 6233 ret); 6234 return ret; 6235 } 6236 6237 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 6238 6239 return 0; 6240 } 6241 6242 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 6243 { 6244 struct phy_device *phydev = hdev->hw.mac.phydev; 6245 u16 remote_advertising = 0; 6246 u16 local_advertising = 0; 6247 u32 rx_pause, tx_pause; 6248 u8 flowctl; 6249 6250 if (!phydev->link || !phydev->autoneg) 6251 return 0; 6252 6253 local_advertising = ethtool_adv_to_lcl_adv_t(phydev->advertising); 6254 6255 if (phydev->pause) 6256 remote_advertising = LPA_PAUSE_CAP; 6257 6258 if (phydev->asym_pause) 6259 remote_advertising |= LPA_PAUSE_ASYM; 6260 6261 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 6262 remote_advertising); 6263 tx_pause = flowctl & FLOW_CTRL_TX; 6264 rx_pause = flowctl & FLOW_CTRL_RX; 6265 6266 if (phydev->duplex == HCLGE_MAC_HALF) { 6267 tx_pause = 0; 6268 rx_pause = 0; 6269 } 6270 6271 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 6272 } 6273 6274 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 6275 u32 *rx_en, u32 *tx_en) 6276 { 6277 struct hclge_vport *vport = hclge_get_vport(handle); 6278 struct hclge_dev *hdev = vport->back; 6279 6280 *auto_neg = hclge_get_autoneg(handle); 6281 6282 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 6283 *rx_en = 0; 6284 *tx_en = 0; 6285 return; 6286 } 6287 6288 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 6289 *rx_en = 1; 6290 *tx_en = 0; 6291 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 6292 *tx_en = 1; 6293 *rx_en = 0; 6294 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 6295 *rx_en = 1; 6296 *tx_en = 1; 6297 } else { 6298 *rx_en = 0; 6299 *tx_en = 0; 6300 } 6301 } 6302 6303 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 6304 u32 rx_en, u32 tx_en) 6305 { 6306 struct hclge_vport *vport = hclge_get_vport(handle); 6307 struct hclge_dev *hdev = vport->back; 6308 struct phy_device *phydev = hdev->hw.mac.phydev; 6309 u32 fc_autoneg; 6310 6311 fc_autoneg = hclge_get_autoneg(handle); 6312 if (auto_neg != fc_autoneg) { 6313 dev_info(&hdev->pdev->dev, 6314 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 6315 return -EOPNOTSUPP; 6316 } 6317 6318 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 6319 dev_info(&hdev->pdev->dev, 6320 "Priority flow control enabled. Cannot set link flow control.\n"); 6321 return -EOPNOTSUPP; 6322 } 6323 6324 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 6325 6326 if (!fc_autoneg) 6327 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 6328 6329 /* Only support flow control negotiation for netdev with 6330 * phy attached for now. 6331 */ 6332 if (!phydev) 6333 return -EOPNOTSUPP; 6334 6335 return phy_start_aneg(phydev); 6336 } 6337 6338 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 6339 u8 *auto_neg, u32 *speed, u8 *duplex) 6340 { 6341 struct hclge_vport *vport = hclge_get_vport(handle); 6342 struct hclge_dev *hdev = vport->back; 6343 6344 if (speed) 6345 *speed = hdev->hw.mac.speed; 6346 if (duplex) 6347 *duplex = hdev->hw.mac.duplex; 6348 if (auto_neg) 6349 *auto_neg = hdev->hw.mac.autoneg; 6350 } 6351 6352 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type) 6353 { 6354 struct hclge_vport *vport = hclge_get_vport(handle); 6355 struct hclge_dev *hdev = vport->back; 6356 6357 if (media_type) 6358 *media_type = hdev->hw.mac.media_type; 6359 } 6360 6361 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 6362 u8 *tp_mdix_ctrl, u8 *tp_mdix) 6363 { 6364 struct hclge_vport *vport = hclge_get_vport(handle); 6365 struct hclge_dev *hdev = vport->back; 6366 struct phy_device *phydev = hdev->hw.mac.phydev; 6367 int mdix_ctrl, mdix, retval, is_resolved; 6368 6369 if (!phydev) { 6370 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 6371 *tp_mdix = ETH_TP_MDI_INVALID; 6372 return; 6373 } 6374 6375 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 6376 6377 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 6378 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 6379 HCLGE_PHY_MDIX_CTRL_S); 6380 6381 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 6382 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 6383 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 6384 6385 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 6386 6387 switch (mdix_ctrl) { 6388 case 0x0: 6389 *tp_mdix_ctrl = ETH_TP_MDI; 6390 break; 6391 case 0x1: 6392 *tp_mdix_ctrl = ETH_TP_MDI_X; 6393 break; 6394 case 0x3: 6395 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 6396 break; 6397 default: 6398 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 6399 break; 6400 } 6401 6402 if (!is_resolved) 6403 *tp_mdix = ETH_TP_MDI_INVALID; 6404 else if (mdix) 6405 *tp_mdix = ETH_TP_MDI_X; 6406 else 6407 *tp_mdix = ETH_TP_MDI; 6408 } 6409 6410 static int hclge_init_instance_hw(struct hclge_dev *hdev) 6411 { 6412 return hclge_mac_connect_phy(hdev); 6413 } 6414 6415 static void hclge_uninit_instance_hw(struct hclge_dev *hdev) 6416 { 6417 hclge_mac_disconnect_phy(hdev); 6418 } 6419 6420 static int hclge_init_client_instance(struct hnae3_client *client, 6421 struct hnae3_ae_dev *ae_dev) 6422 { 6423 struct hclge_dev *hdev = ae_dev->priv; 6424 struct hclge_vport *vport; 6425 int i, ret; 6426 6427 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 6428 vport = &hdev->vport[i]; 6429 6430 switch (client->type) { 6431 case HNAE3_CLIENT_KNIC: 6432 6433 hdev->nic_client = client; 6434 vport->nic.client = client; 6435 ret = client->ops->init_instance(&vport->nic); 6436 if (ret) 6437 goto clear_nic; 6438 6439 ret = hclge_init_instance_hw(hdev); 6440 if (ret) { 6441 client->ops->uninit_instance(&vport->nic, 6442 0); 6443 goto clear_nic; 6444 } 6445 6446 hnae3_set_client_init_flag(client, ae_dev, 1); 6447 6448 if (hdev->roce_client && 6449 hnae3_dev_roce_supported(hdev)) { 6450 struct hnae3_client *rc = hdev->roce_client; 6451 6452 ret = hclge_init_roce_base_info(vport); 6453 if (ret) 6454 goto clear_roce; 6455 6456 ret = rc->ops->init_instance(&vport->roce); 6457 if (ret) 6458 goto clear_roce; 6459 6460 hnae3_set_client_init_flag(hdev->roce_client, 6461 ae_dev, 1); 6462 } 6463 6464 break; 6465 case HNAE3_CLIENT_UNIC: 6466 hdev->nic_client = client; 6467 vport->nic.client = client; 6468 6469 ret = client->ops->init_instance(&vport->nic); 6470 if (ret) 6471 goto clear_nic; 6472 6473 hnae3_set_client_init_flag(client, ae_dev, 1); 6474 6475 break; 6476 case HNAE3_CLIENT_ROCE: 6477 if (hnae3_dev_roce_supported(hdev)) { 6478 hdev->roce_client = client; 6479 vport->roce.client = client; 6480 } 6481 6482 if (hdev->roce_client && hdev->nic_client) { 6483 ret = hclge_init_roce_base_info(vport); 6484 if (ret) 6485 goto clear_roce; 6486 6487 ret = client->ops->init_instance(&vport->roce); 6488 if (ret) 6489 goto clear_roce; 6490 6491 hnae3_set_client_init_flag(client, ae_dev, 1); 6492 } 6493 6494 break; 6495 default: 6496 return -EINVAL; 6497 } 6498 } 6499 6500 return 0; 6501 6502 clear_nic: 6503 hdev->nic_client = NULL; 6504 vport->nic.client = NULL; 6505 return ret; 6506 clear_roce: 6507 hdev->roce_client = NULL; 6508 vport->roce.client = NULL; 6509 return ret; 6510 } 6511 6512 static void hclge_uninit_client_instance(struct hnae3_client *client, 6513 struct hnae3_ae_dev *ae_dev) 6514 { 6515 struct hclge_dev *hdev = ae_dev->priv; 6516 struct hclge_vport *vport; 6517 int i; 6518 6519 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 6520 vport = &hdev->vport[i]; 6521 if (hdev->roce_client) { 6522 hdev->roce_client->ops->uninit_instance(&vport->roce, 6523 0); 6524 hdev->roce_client = NULL; 6525 vport->roce.client = NULL; 6526 } 6527 if (client->type == HNAE3_CLIENT_ROCE) 6528 return; 6529 if (hdev->nic_client && client->ops->uninit_instance) { 6530 hclge_uninit_instance_hw(hdev); 6531 client->ops->uninit_instance(&vport->nic, 0); 6532 hdev->nic_client = NULL; 6533 vport->nic.client = NULL; 6534 } 6535 } 6536 } 6537 6538 static int hclge_pci_init(struct hclge_dev *hdev) 6539 { 6540 struct pci_dev *pdev = hdev->pdev; 6541 struct hclge_hw *hw; 6542 int ret; 6543 6544 ret = pci_enable_device(pdev); 6545 if (ret) { 6546 dev_err(&pdev->dev, "failed to enable PCI device\n"); 6547 return ret; 6548 } 6549 6550 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 6551 if (ret) { 6552 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 6553 if (ret) { 6554 dev_err(&pdev->dev, 6555 "can't set consistent PCI DMA"); 6556 goto err_disable_device; 6557 } 6558 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 6559 } 6560 6561 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 6562 if (ret) { 6563 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 6564 goto err_disable_device; 6565 } 6566 6567 pci_set_master(pdev); 6568 hw = &hdev->hw; 6569 hw->io_base = pcim_iomap(pdev, 2, 0); 6570 if (!hw->io_base) { 6571 dev_err(&pdev->dev, "Can't map configuration register space\n"); 6572 ret = -ENOMEM; 6573 goto err_clr_master; 6574 } 6575 6576 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 6577 6578 return 0; 6579 err_clr_master: 6580 pci_clear_master(pdev); 6581 pci_release_regions(pdev); 6582 err_disable_device: 6583 pci_disable_device(pdev); 6584 6585 return ret; 6586 } 6587 6588 static void hclge_pci_uninit(struct hclge_dev *hdev) 6589 { 6590 struct pci_dev *pdev = hdev->pdev; 6591 6592 pcim_iounmap(pdev, hdev->hw.io_base); 6593 pci_free_irq_vectors(pdev); 6594 pci_clear_master(pdev); 6595 pci_release_mem_regions(pdev); 6596 pci_disable_device(pdev); 6597 } 6598 6599 static void hclge_state_init(struct hclge_dev *hdev) 6600 { 6601 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 6602 set_bit(HCLGE_STATE_DOWN, &hdev->state); 6603 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 6604 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 6605 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 6606 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 6607 } 6608 6609 static void hclge_state_uninit(struct hclge_dev *hdev) 6610 { 6611 set_bit(HCLGE_STATE_DOWN, &hdev->state); 6612 6613 if (hdev->service_timer.function) 6614 del_timer_sync(&hdev->service_timer); 6615 if (hdev->service_task.func) 6616 cancel_work_sync(&hdev->service_task); 6617 if (hdev->rst_service_task.func) 6618 cancel_work_sync(&hdev->rst_service_task); 6619 if (hdev->mbx_service_task.func) 6620 cancel_work_sync(&hdev->mbx_service_task); 6621 } 6622 6623 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 6624 { 6625 struct pci_dev *pdev = ae_dev->pdev; 6626 struct hclge_dev *hdev; 6627 int ret; 6628 6629 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 6630 if (!hdev) { 6631 ret = -ENOMEM; 6632 goto out; 6633 } 6634 6635 hdev->pdev = pdev; 6636 hdev->ae_dev = ae_dev; 6637 hdev->reset_type = HNAE3_NONE_RESET; 6638 ae_dev->priv = hdev; 6639 6640 ret = hclge_pci_init(hdev); 6641 if (ret) { 6642 dev_err(&pdev->dev, "PCI init failed\n"); 6643 goto out; 6644 } 6645 6646 /* Firmware command queue initialize */ 6647 ret = hclge_cmd_queue_init(hdev); 6648 if (ret) { 6649 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret); 6650 goto err_pci_uninit; 6651 } 6652 6653 /* Firmware command initialize */ 6654 ret = hclge_cmd_init(hdev); 6655 if (ret) 6656 goto err_cmd_uninit; 6657 6658 ret = hclge_get_cap(hdev); 6659 if (ret) { 6660 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n", 6661 ret); 6662 goto err_cmd_uninit; 6663 } 6664 6665 ret = hclge_configure(hdev); 6666 if (ret) { 6667 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 6668 goto err_cmd_uninit; 6669 } 6670 6671 ret = hclge_init_msi(hdev); 6672 if (ret) { 6673 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 6674 goto err_cmd_uninit; 6675 } 6676 6677 ret = hclge_misc_irq_init(hdev); 6678 if (ret) { 6679 dev_err(&pdev->dev, 6680 "Misc IRQ(vector0) init error, ret = %d.\n", 6681 ret); 6682 goto err_msi_uninit; 6683 } 6684 6685 ret = hclge_alloc_tqps(hdev); 6686 if (ret) { 6687 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 6688 goto err_msi_irq_uninit; 6689 } 6690 6691 ret = hclge_alloc_vport(hdev); 6692 if (ret) { 6693 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret); 6694 goto err_msi_irq_uninit; 6695 } 6696 6697 ret = hclge_map_tqp(hdev); 6698 if (ret) { 6699 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 6700 goto err_msi_irq_uninit; 6701 } 6702 6703 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { 6704 ret = hclge_mac_mdio_config(hdev); 6705 if (ret) { 6706 dev_err(&hdev->pdev->dev, 6707 "mdio config fail ret=%d\n", ret); 6708 goto err_msi_irq_uninit; 6709 } 6710 } 6711 6712 ret = hclge_init_umv_space(hdev); 6713 if (ret) { 6714 dev_err(&pdev->dev, "umv space init error, ret=%d.\n", ret); 6715 goto err_msi_irq_uninit; 6716 } 6717 6718 ret = hclge_mac_init(hdev); 6719 if (ret) { 6720 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 6721 goto err_mdiobus_unreg; 6722 } 6723 6724 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 6725 if (ret) { 6726 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 6727 goto err_mdiobus_unreg; 6728 } 6729 6730 ret = hclge_init_vlan_config(hdev); 6731 if (ret) { 6732 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 6733 goto err_mdiobus_unreg; 6734 } 6735 6736 ret = hclge_tm_schd_init(hdev); 6737 if (ret) { 6738 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 6739 goto err_mdiobus_unreg; 6740 } 6741 6742 hclge_rss_init_cfg(hdev); 6743 ret = hclge_rss_init_hw(hdev); 6744 if (ret) { 6745 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 6746 goto err_mdiobus_unreg; 6747 } 6748 6749 ret = init_mgr_tbl(hdev); 6750 if (ret) { 6751 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 6752 goto err_mdiobus_unreg; 6753 } 6754 6755 ret = hclge_init_fd_config(hdev); 6756 if (ret) { 6757 dev_err(&pdev->dev, 6758 "fd table init fail, ret=%d\n", ret); 6759 goto err_mdiobus_unreg; 6760 } 6761 6762 ret = hclge_hw_error_set_state(hdev, true); 6763 if (ret) { 6764 dev_err(&pdev->dev, 6765 "hw error interrupts enable failed, ret =%d\n", ret); 6766 goto err_mdiobus_unreg; 6767 } 6768 6769 hclge_dcb_ops_set(hdev); 6770 6771 timer_setup(&hdev->service_timer, hclge_service_timer, 0); 6772 INIT_WORK(&hdev->service_task, hclge_service_task); 6773 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task); 6774 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task); 6775 6776 hclge_clear_all_event_cause(hdev); 6777 6778 /* Enable MISC vector(vector0) */ 6779 hclge_enable_vector(&hdev->misc_vector, true); 6780 6781 hclge_state_init(hdev); 6782 6783 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME); 6784 return 0; 6785 6786 err_mdiobus_unreg: 6787 if (hdev->hw.mac.phydev) 6788 mdiobus_unregister(hdev->hw.mac.mdio_bus); 6789 err_msi_irq_uninit: 6790 hclge_misc_irq_uninit(hdev); 6791 err_msi_uninit: 6792 pci_free_irq_vectors(pdev); 6793 err_cmd_uninit: 6794 hclge_destroy_cmd_queue(&hdev->hw); 6795 err_pci_uninit: 6796 pcim_iounmap(pdev, hdev->hw.io_base); 6797 pci_clear_master(pdev); 6798 pci_release_regions(pdev); 6799 pci_disable_device(pdev); 6800 out: 6801 return ret; 6802 } 6803 6804 static void hclge_stats_clear(struct hclge_dev *hdev) 6805 { 6806 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats)); 6807 } 6808 6809 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 6810 { 6811 struct hclge_dev *hdev = ae_dev->priv; 6812 struct pci_dev *pdev = ae_dev->pdev; 6813 int ret; 6814 6815 set_bit(HCLGE_STATE_DOWN, &hdev->state); 6816 6817 hclge_stats_clear(hdev); 6818 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 6819 6820 ret = hclge_cmd_init(hdev); 6821 if (ret) { 6822 dev_err(&pdev->dev, "Cmd queue init failed\n"); 6823 return ret; 6824 } 6825 6826 ret = hclge_get_cap(hdev); 6827 if (ret) { 6828 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n", 6829 ret); 6830 return ret; 6831 } 6832 6833 ret = hclge_configure(hdev); 6834 if (ret) { 6835 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 6836 return ret; 6837 } 6838 6839 ret = hclge_map_tqp(hdev); 6840 if (ret) { 6841 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 6842 return ret; 6843 } 6844 6845 hclge_reset_umv_space(hdev); 6846 6847 ret = hclge_mac_init(hdev); 6848 if (ret) { 6849 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 6850 return ret; 6851 } 6852 6853 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 6854 if (ret) { 6855 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 6856 return ret; 6857 } 6858 6859 ret = hclge_init_vlan_config(hdev); 6860 if (ret) { 6861 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 6862 return ret; 6863 } 6864 6865 ret = hclge_tm_init_hw(hdev); 6866 if (ret) { 6867 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 6868 return ret; 6869 } 6870 6871 ret = hclge_rss_init_hw(hdev); 6872 if (ret) { 6873 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 6874 return ret; 6875 } 6876 6877 ret = hclge_init_fd_config(hdev); 6878 if (ret) { 6879 dev_err(&pdev->dev, 6880 "fd table init fail, ret=%d\n", ret); 6881 return ret; 6882 } 6883 6884 /* Re-enable the TM hw error interrupts because 6885 * they get disabled on core/global reset. 6886 */ 6887 if (hclge_enable_tm_hw_error(hdev, true)) 6888 dev_err(&pdev->dev, "failed to enable TM hw error interrupts\n"); 6889 6890 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 6891 HCLGE_DRIVER_NAME); 6892 6893 return 0; 6894 } 6895 6896 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 6897 { 6898 struct hclge_dev *hdev = ae_dev->priv; 6899 struct hclge_mac *mac = &hdev->hw.mac; 6900 6901 hclge_state_uninit(hdev); 6902 6903 if (mac->phydev) 6904 mdiobus_unregister(mac->mdio_bus); 6905 6906 hclge_uninit_umv_space(hdev); 6907 6908 /* Disable MISC vector(vector0) */ 6909 hclge_enable_vector(&hdev->misc_vector, false); 6910 synchronize_irq(hdev->misc_vector.vector_irq); 6911 6912 hclge_hw_error_set_state(hdev, false); 6913 hclge_destroy_cmd_queue(&hdev->hw); 6914 hclge_misc_irq_uninit(hdev); 6915 hclge_pci_uninit(hdev); 6916 ae_dev->priv = NULL; 6917 } 6918 6919 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 6920 { 6921 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 6922 struct hclge_vport *vport = hclge_get_vport(handle); 6923 struct hclge_dev *hdev = vport->back; 6924 6925 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps); 6926 } 6927 6928 static void hclge_get_channels(struct hnae3_handle *handle, 6929 struct ethtool_channels *ch) 6930 { 6931 struct hclge_vport *vport = hclge_get_vport(handle); 6932 6933 ch->max_combined = hclge_get_max_channels(handle); 6934 ch->other_count = 1; 6935 ch->max_other = 1; 6936 ch->combined_count = vport->alloc_tqps; 6937 } 6938 6939 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 6940 u16 *alloc_tqps, u16 *max_rss_size) 6941 { 6942 struct hclge_vport *vport = hclge_get_vport(handle); 6943 struct hclge_dev *hdev = vport->back; 6944 6945 *alloc_tqps = vport->alloc_tqps; 6946 *max_rss_size = hdev->rss_size_max; 6947 } 6948 6949 static void hclge_release_tqp(struct hclge_vport *vport) 6950 { 6951 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 6952 struct hclge_dev *hdev = vport->back; 6953 int i; 6954 6955 for (i = 0; i < kinfo->num_tqps; i++) { 6956 struct hclge_tqp *tqp = 6957 container_of(kinfo->tqp[i], struct hclge_tqp, q); 6958 6959 tqp->q.handle = NULL; 6960 tqp->q.tqp_index = 0; 6961 tqp->alloced = false; 6962 } 6963 6964 devm_kfree(&hdev->pdev->dev, kinfo->tqp); 6965 kinfo->tqp = NULL; 6966 } 6967 6968 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num) 6969 { 6970 struct hclge_vport *vport = hclge_get_vport(handle); 6971 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 6972 struct hclge_dev *hdev = vport->back; 6973 int cur_rss_size = kinfo->rss_size; 6974 int cur_tqps = kinfo->num_tqps; 6975 u16 tc_offset[HCLGE_MAX_TC_NUM]; 6976 u16 tc_valid[HCLGE_MAX_TC_NUM]; 6977 u16 tc_size[HCLGE_MAX_TC_NUM]; 6978 u16 roundup_size; 6979 u32 *rss_indir; 6980 int ret, i; 6981 6982 /* Free old tqps, and reallocate with new tqp number when nic setup */ 6983 hclge_release_tqp(vport); 6984 6985 ret = hclge_knic_setup(vport, new_tqps_num, kinfo->num_desc); 6986 if (ret) { 6987 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret); 6988 return ret; 6989 } 6990 6991 ret = hclge_map_tqp_to_vport(hdev, vport); 6992 if (ret) { 6993 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret); 6994 return ret; 6995 } 6996 6997 ret = hclge_tm_schd_init(hdev); 6998 if (ret) { 6999 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret); 7000 return ret; 7001 } 7002 7003 roundup_size = roundup_pow_of_two(kinfo->rss_size); 7004 roundup_size = ilog2(roundup_size); 7005 /* Set the RSS TC mode according to the new RSS size */ 7006 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 7007 tc_valid[i] = 0; 7008 7009 if (!(hdev->hw_tc_map & BIT(i))) 7010 continue; 7011 7012 tc_valid[i] = 1; 7013 tc_size[i] = roundup_size; 7014 tc_offset[i] = kinfo->rss_size * i; 7015 } 7016 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset); 7017 if (ret) 7018 return ret; 7019 7020 /* Reinitializes the rss indirect table according to the new RSS size */ 7021 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); 7022 if (!rss_indir) 7023 return -ENOMEM; 7024 7025 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) 7026 rss_indir[i] = i % kinfo->rss_size; 7027 7028 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 7029 if (ret) 7030 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 7031 ret); 7032 7033 kfree(rss_indir); 7034 7035 if (!ret) 7036 dev_info(&hdev->pdev->dev, 7037 "Channels changed, rss_size from %d to %d, tqps from %d to %d", 7038 cur_rss_size, kinfo->rss_size, 7039 cur_tqps, kinfo->rss_size * kinfo->num_tc); 7040 7041 return ret; 7042 } 7043 7044 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit, 7045 u32 *regs_num_64_bit) 7046 { 7047 struct hclge_desc desc; 7048 u32 total_num; 7049 int ret; 7050 7051 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true); 7052 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7053 if (ret) { 7054 dev_err(&hdev->pdev->dev, 7055 "Query register number cmd failed, ret = %d.\n", ret); 7056 return ret; 7057 } 7058 7059 *regs_num_32_bit = le32_to_cpu(desc.data[0]); 7060 *regs_num_64_bit = le32_to_cpu(desc.data[1]); 7061 7062 total_num = *regs_num_32_bit + *regs_num_64_bit; 7063 if (!total_num) 7064 return -EINVAL; 7065 7066 return 0; 7067 } 7068 7069 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num, 7070 void *data) 7071 { 7072 #define HCLGE_32_BIT_REG_RTN_DATANUM 8 7073 7074 struct hclge_desc *desc; 7075 u32 *reg_val = data; 7076 __le32 *desc_data; 7077 int cmd_num; 7078 int i, k, n; 7079 int ret; 7080 7081 if (regs_num == 0) 7082 return 0; 7083 7084 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM); 7085 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 7086 if (!desc) 7087 return -ENOMEM; 7088 7089 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true); 7090 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 7091 if (ret) { 7092 dev_err(&hdev->pdev->dev, 7093 "Query 32 bit register cmd failed, ret = %d.\n", ret); 7094 kfree(desc); 7095 return ret; 7096 } 7097 7098 for (i = 0; i < cmd_num; i++) { 7099 if (i == 0) { 7100 desc_data = (__le32 *)(&desc[i].data[0]); 7101 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2; 7102 } else { 7103 desc_data = (__le32 *)(&desc[i]); 7104 n = HCLGE_32_BIT_REG_RTN_DATANUM; 7105 } 7106 for (k = 0; k < n; k++) { 7107 *reg_val++ = le32_to_cpu(*desc_data++); 7108 7109 regs_num--; 7110 if (!regs_num) 7111 break; 7112 } 7113 } 7114 7115 kfree(desc); 7116 return 0; 7117 } 7118 7119 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num, 7120 void *data) 7121 { 7122 #define HCLGE_64_BIT_REG_RTN_DATANUM 4 7123 7124 struct hclge_desc *desc; 7125 u64 *reg_val = data; 7126 __le64 *desc_data; 7127 int cmd_num; 7128 int i, k, n; 7129 int ret; 7130 7131 if (regs_num == 0) 7132 return 0; 7133 7134 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM); 7135 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 7136 if (!desc) 7137 return -ENOMEM; 7138 7139 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true); 7140 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 7141 if (ret) { 7142 dev_err(&hdev->pdev->dev, 7143 "Query 64 bit register cmd failed, ret = %d.\n", ret); 7144 kfree(desc); 7145 return ret; 7146 } 7147 7148 for (i = 0; i < cmd_num; i++) { 7149 if (i == 0) { 7150 desc_data = (__le64 *)(&desc[i].data[0]); 7151 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1; 7152 } else { 7153 desc_data = (__le64 *)(&desc[i]); 7154 n = HCLGE_64_BIT_REG_RTN_DATANUM; 7155 } 7156 for (k = 0; k < n; k++) { 7157 *reg_val++ = le64_to_cpu(*desc_data++); 7158 7159 regs_num--; 7160 if (!regs_num) 7161 break; 7162 } 7163 } 7164 7165 kfree(desc); 7166 return 0; 7167 } 7168 7169 static int hclge_get_regs_len(struct hnae3_handle *handle) 7170 { 7171 struct hclge_vport *vport = hclge_get_vport(handle); 7172 struct hclge_dev *hdev = vport->back; 7173 u32 regs_num_32_bit, regs_num_64_bit; 7174 int ret; 7175 7176 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 7177 if (ret) { 7178 dev_err(&hdev->pdev->dev, 7179 "Get register number failed, ret = %d.\n", ret); 7180 return -EOPNOTSUPP; 7181 } 7182 7183 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64); 7184 } 7185 7186 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version, 7187 void *data) 7188 { 7189 struct hclge_vport *vport = hclge_get_vport(handle); 7190 struct hclge_dev *hdev = vport->back; 7191 u32 regs_num_32_bit, regs_num_64_bit; 7192 int ret; 7193 7194 *version = hdev->fw_version; 7195 7196 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 7197 if (ret) { 7198 dev_err(&hdev->pdev->dev, 7199 "Get register number failed, ret = %d.\n", ret); 7200 return; 7201 } 7202 7203 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data); 7204 if (ret) { 7205 dev_err(&hdev->pdev->dev, 7206 "Get 32 bit register failed, ret = %d.\n", ret); 7207 return; 7208 } 7209 7210 data = (u32 *)data + regs_num_32_bit; 7211 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, 7212 data); 7213 if (ret) 7214 dev_err(&hdev->pdev->dev, 7215 "Get 64 bit register failed, ret = %d.\n", ret); 7216 } 7217 7218 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 7219 { 7220 struct hclge_set_led_state_cmd *req; 7221 struct hclge_desc desc; 7222 int ret; 7223 7224 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 7225 7226 req = (struct hclge_set_led_state_cmd *)desc.data; 7227 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 7228 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 7229 7230 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7231 if (ret) 7232 dev_err(&hdev->pdev->dev, 7233 "Send set led state cmd error, ret =%d\n", ret); 7234 7235 return ret; 7236 } 7237 7238 enum hclge_led_status { 7239 HCLGE_LED_OFF, 7240 HCLGE_LED_ON, 7241 HCLGE_LED_NO_CHANGE = 0xFF, 7242 }; 7243 7244 static int hclge_set_led_id(struct hnae3_handle *handle, 7245 enum ethtool_phys_id_state status) 7246 { 7247 struct hclge_vport *vport = hclge_get_vport(handle); 7248 struct hclge_dev *hdev = vport->back; 7249 7250 switch (status) { 7251 case ETHTOOL_ID_ACTIVE: 7252 return hclge_set_led_status(hdev, HCLGE_LED_ON); 7253 case ETHTOOL_ID_INACTIVE: 7254 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 7255 default: 7256 return -EINVAL; 7257 } 7258 } 7259 7260 static void hclge_get_link_mode(struct hnae3_handle *handle, 7261 unsigned long *supported, 7262 unsigned long *advertising) 7263 { 7264 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 7265 struct hclge_vport *vport = hclge_get_vport(handle); 7266 struct hclge_dev *hdev = vport->back; 7267 unsigned int idx = 0; 7268 7269 for (; idx < size; idx++) { 7270 supported[idx] = hdev->hw.mac.supported[idx]; 7271 advertising[idx] = hdev->hw.mac.advertising[idx]; 7272 } 7273 } 7274 7275 static const struct hnae3_ae_ops hclge_ops = { 7276 .init_ae_dev = hclge_init_ae_dev, 7277 .uninit_ae_dev = hclge_uninit_ae_dev, 7278 .init_client_instance = hclge_init_client_instance, 7279 .uninit_client_instance = hclge_uninit_client_instance, 7280 .map_ring_to_vector = hclge_map_ring_to_vector, 7281 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 7282 .get_vector = hclge_get_vector, 7283 .put_vector = hclge_put_vector, 7284 .set_promisc_mode = hclge_set_promisc_mode, 7285 .set_loopback = hclge_set_loopback, 7286 .start = hclge_ae_start, 7287 .stop = hclge_ae_stop, 7288 .get_status = hclge_get_status, 7289 .get_ksettings_an_result = hclge_get_ksettings_an_result, 7290 .update_speed_duplex_h = hclge_update_speed_duplex_h, 7291 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 7292 .get_media_type = hclge_get_media_type, 7293 .get_rss_key_size = hclge_get_rss_key_size, 7294 .get_rss_indir_size = hclge_get_rss_indir_size, 7295 .get_rss = hclge_get_rss, 7296 .set_rss = hclge_set_rss, 7297 .set_rss_tuple = hclge_set_rss_tuple, 7298 .get_rss_tuple = hclge_get_rss_tuple, 7299 .get_tc_size = hclge_get_tc_size, 7300 .get_mac_addr = hclge_get_mac_addr, 7301 .set_mac_addr = hclge_set_mac_addr, 7302 .do_ioctl = hclge_do_ioctl, 7303 .add_uc_addr = hclge_add_uc_addr, 7304 .rm_uc_addr = hclge_rm_uc_addr, 7305 .add_mc_addr = hclge_add_mc_addr, 7306 .rm_mc_addr = hclge_rm_mc_addr, 7307 .set_autoneg = hclge_set_autoneg, 7308 .get_autoneg = hclge_get_autoneg, 7309 .get_pauseparam = hclge_get_pauseparam, 7310 .set_pauseparam = hclge_set_pauseparam, 7311 .set_mtu = hclge_set_mtu, 7312 .reset_queue = hclge_reset_tqp, 7313 .get_stats = hclge_get_stats, 7314 .update_stats = hclge_update_stats, 7315 .get_strings = hclge_get_strings, 7316 .get_sset_count = hclge_get_sset_count, 7317 .get_fw_version = hclge_get_fw_version, 7318 .get_mdix_mode = hclge_get_mdix_mode, 7319 .enable_vlan_filter = hclge_enable_vlan_filter, 7320 .set_vlan_filter = hclge_set_vlan_filter, 7321 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 7322 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 7323 .reset_event = hclge_reset_event, 7324 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 7325 .set_channels = hclge_set_channels, 7326 .get_channels = hclge_get_channels, 7327 .get_regs_len = hclge_get_regs_len, 7328 .get_regs = hclge_get_regs, 7329 .set_led_id = hclge_set_led_id, 7330 .get_link_mode = hclge_get_link_mode, 7331 .add_fd_entry = hclge_add_fd_entry, 7332 .del_fd_entry = hclge_del_fd_entry, 7333 .del_all_fd_entries = hclge_del_all_fd_entries, 7334 .get_fd_rule_cnt = hclge_get_fd_rule_cnt, 7335 .get_fd_rule_info = hclge_get_fd_rule_info, 7336 .get_fd_all_rules = hclge_get_all_rules, 7337 .restore_fd_rules = hclge_restore_fd_entries, 7338 .enable_fd = hclge_enable_fd, 7339 .process_hw_error = hclge_process_ras_hw_error, 7340 }; 7341 7342 static struct hnae3_ae_algo ae_algo = { 7343 .ops = &hclge_ops, 7344 .pdev_id_table = ae_algo_pci_tbl, 7345 }; 7346 7347 static int hclge_init(void) 7348 { 7349 pr_info("%s is initializing\n", HCLGE_NAME); 7350 7351 hnae3_register_ae_algo(&ae_algo); 7352 7353 return 0; 7354 } 7355 7356 static void hclge_exit(void) 7357 { 7358 hnae3_unregister_ae_algo(&ae_algo); 7359 } 7360 module_init(hclge_init); 7361 module_exit(hclge_exit); 7362 7363 MODULE_LICENSE("GPL"); 7364 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 7365 MODULE_DESCRIPTION("HCLGE Driver"); 7366 MODULE_VERSION(HCLGE_MOD_VERSION); 7367