1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/pci.h> 13 #include <linux/platform_device.h> 14 #include <linux/if_vlan.h> 15 #include <linux/crash_dump.h> 16 #include <net/ipv6.h> 17 #include <net/rtnetlink.h> 18 #include "hclge_cmd.h" 19 #include "hclge_dcb.h" 20 #include "hclge_main.h" 21 #include "hclge_mbx.h" 22 #include "hclge_mdio.h" 23 #include "hclge_regs.h" 24 #include "hclge_tm.h" 25 #include "hclge_err.h" 26 #include "hnae3.h" 27 #include "hclge_devlink.h" 28 #include "hclge_comm_cmd.h" 29 30 #define HCLGE_NAME "hclge" 31 32 #define HCLGE_BUF_SIZE_UNIT 256U 33 #define HCLGE_BUF_MUL_BY 2 34 #define HCLGE_BUF_DIV_BY 2 35 #define NEED_RESERVE_TC_NUM 2 36 #define BUF_MAX_PERCENT 100 37 #define BUF_RESERVE_PERCENT 90 38 39 #define HCLGE_RESET_MAX_FAIL_CNT 5 40 #define HCLGE_RESET_SYNC_TIME 100 41 #define HCLGE_PF_RESET_SYNC_TIME 20 42 #define HCLGE_PF_RESET_SYNC_CNT 1500 43 44 #define HCLGE_LINK_STATUS_MS 10 45 46 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps); 47 static int hclge_init_vlan_config(struct hclge_dev *hdev); 48 static void hclge_sync_vlan_filter(struct hclge_dev *hdev); 49 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 50 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle); 51 static void hclge_rfs_filter_expire(struct hclge_dev *hdev); 52 static int hclge_clear_arfs_rules(struct hclge_dev *hdev); 53 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 54 unsigned long *addr); 55 static int hclge_set_default_loopback(struct hclge_dev *hdev); 56 57 static void hclge_sync_mac_table(struct hclge_dev *hdev); 58 static void hclge_restore_hw_table(struct hclge_dev *hdev); 59 static void hclge_sync_promisc_mode(struct hclge_dev *hdev); 60 static void hclge_sync_fd_table(struct hclge_dev *hdev); 61 static void hclge_update_fec_stats(struct hclge_dev *hdev); 62 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 63 int wait_cnt); 64 static int hclge_update_port_info(struct hclge_dev *hdev); 65 66 static struct hnae3_ae_algo ae_algo; 67 68 static struct workqueue_struct *hclge_wq; 69 70 static const struct pci_device_id ae_algo_pci_tbl[] = { 71 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 72 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 75 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 77 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 79 /* required last entry */ 80 {0, } 81 }; 82 83 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 84 85 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 86 "External Loopback test", 87 "App Loopback test", 88 "Serdes serial Loopback test", 89 "Serdes parallel Loopback test", 90 "Phy Loopback test" 91 }; 92 93 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 94 {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 95 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 96 {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 97 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 98 {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 99 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)}, 100 {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 101 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)}, 102 {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 103 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)}, 104 {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 105 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)}, 106 {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 107 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)}, 108 {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 109 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 110 {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 111 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 112 {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 113 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 114 {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 115 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 116 {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 117 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 118 {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 119 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 120 {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 121 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 122 {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 123 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 124 {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 125 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)}, 126 {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 127 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)}, 128 {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 129 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)}, 130 {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 131 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)}, 132 {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 133 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)}, 134 {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 135 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)}, 136 {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 137 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)}, 138 {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 139 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)}, 140 {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 141 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)}, 142 {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 143 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 144 {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 145 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 146 {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 147 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 148 {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 149 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 150 {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 151 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 152 {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 153 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 154 {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 155 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 156 {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 157 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 158 {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 159 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)}, 160 {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 161 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)}, 162 {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 163 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)}, 164 {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 165 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)}, 166 {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 167 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)}, 168 {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 169 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)}, 170 {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 171 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)}, 172 {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 173 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)}, 174 {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 175 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 176 {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 177 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 178 {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 179 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 180 {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 181 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 182 {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 183 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 184 {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 185 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 186 {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 187 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 188 {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 189 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 190 {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 191 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 192 {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 193 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 194 {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 195 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 196 {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 197 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 198 {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 199 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 200 {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 201 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 202 {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 203 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 204 {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 205 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 206 {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 207 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 208 {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 209 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 210 {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 211 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 212 {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 213 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 214 {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 215 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 216 {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 217 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 218 {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 219 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 220 {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 221 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 222 {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 223 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 224 {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 225 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 226 {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 228 {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 230 {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 231 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 232 {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 234 {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 235 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 236 {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 237 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 238 {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 239 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 240 {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 241 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 242 {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 243 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 244 {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 246 {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 248 {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 250 {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 252 {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 254 {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 256 {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 258 {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 260 {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 262 {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 264 {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 265 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 266 {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 267 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 268 {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 269 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 270 {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 271 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 272 {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 273 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 274 275 {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 277 {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 279 {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 281 {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 283 {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 285 {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 287 {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 288 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 289 {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 290 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 291 {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 292 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 293 {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 294 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 295 {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 296 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 297 {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 298 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 299 }; 300 301 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 302 { 303 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 304 .ethter_type = cpu_to_le16(ETH_P_LLDP), 305 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e}, 306 .i_port_bitmap = 0x1, 307 }, 308 }; 309 310 static const struct key_info meta_data_key_info[] = { 311 { PACKET_TYPE_ID, 6 }, 312 { IP_FRAGEMENT, 1 }, 313 { ROCE_TYPE, 1 }, 314 { NEXT_KEY, 5 }, 315 { VLAN_NUMBER, 2 }, 316 { SRC_VPORT, 12 }, 317 { DST_VPORT, 12 }, 318 { TUNNEL_PACKET, 1 }, 319 }; 320 321 static const struct key_info tuple_key_info[] = { 322 { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 }, 323 { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 }, 324 { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 }, 325 { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 326 { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 }, 327 { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 }, 328 { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 }, 329 { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 }, 330 { OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 }, 331 { OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 }, 332 { OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 }, 333 { OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 }, 334 { OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 }, 335 { OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 }, 336 { OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 }, 337 { OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 }, 338 { INNER_DST_MAC, 48, KEY_OPT_MAC, 339 offsetof(struct hclge_fd_rule, tuples.dst_mac), 340 offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) }, 341 { INNER_SRC_MAC, 48, KEY_OPT_MAC, 342 offsetof(struct hclge_fd_rule, tuples.src_mac), 343 offsetof(struct hclge_fd_rule, tuples_mask.src_mac) }, 344 { INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16, 345 offsetof(struct hclge_fd_rule, tuples.vlan_tag1), 346 offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) }, 347 { INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 348 { INNER_ETH_TYPE, 16, KEY_OPT_LE16, 349 offsetof(struct hclge_fd_rule, tuples.ether_proto), 350 offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) }, 351 { INNER_L2_RSV, 16, KEY_OPT_LE16, 352 offsetof(struct hclge_fd_rule, tuples.l2_user_def), 353 offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) }, 354 { INNER_IP_TOS, 8, KEY_OPT_U8, 355 offsetof(struct hclge_fd_rule, tuples.ip_tos), 356 offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) }, 357 { INNER_IP_PROTO, 8, KEY_OPT_U8, 358 offsetof(struct hclge_fd_rule, tuples.ip_proto), 359 offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) }, 360 { INNER_SRC_IP, 32, KEY_OPT_IP, 361 offsetof(struct hclge_fd_rule, tuples.src_ip), 362 offsetof(struct hclge_fd_rule, tuples_mask.src_ip) }, 363 { INNER_DST_IP, 32, KEY_OPT_IP, 364 offsetof(struct hclge_fd_rule, tuples.dst_ip), 365 offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) }, 366 { INNER_L3_RSV, 16, KEY_OPT_LE16, 367 offsetof(struct hclge_fd_rule, tuples.l3_user_def), 368 offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) }, 369 { INNER_SRC_PORT, 16, KEY_OPT_LE16, 370 offsetof(struct hclge_fd_rule, tuples.src_port), 371 offsetof(struct hclge_fd_rule, tuples_mask.src_port) }, 372 { INNER_DST_PORT, 16, KEY_OPT_LE16, 373 offsetof(struct hclge_fd_rule, tuples.dst_port), 374 offsetof(struct hclge_fd_rule, tuples_mask.dst_port) }, 375 { INNER_L4_RSV, 32, KEY_OPT_LE32, 376 offsetof(struct hclge_fd_rule, tuples.l4_user_def), 377 offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) }, 378 }; 379 380 /** 381 * hclge_cmd_send - send command to command queue 382 * @hw: pointer to the hw struct 383 * @desc: prefilled descriptor for describing the command 384 * @num : the number of descriptors to be sent 385 * 386 * This is the main send command for command queue, it 387 * sends the queue, cleans the queue, etc 388 **/ 389 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 390 { 391 return hclge_comm_cmd_send(&hw->hw, desc, num); 392 } 393 394 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev) 395 { 396 #define HCLGE_MAC_CMD_NUM 21 397 398 u64 *data = (u64 *)(&hdev->mac_stats); 399 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 400 __le64 *desc_data; 401 u32 data_size; 402 int ret; 403 u32 i; 404 405 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 406 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 407 if (ret) { 408 dev_err(&hdev->pdev->dev, 409 "Get MAC pkt stats fail, status = %d.\n", ret); 410 411 return ret; 412 } 413 414 /* The first desc has a 64-bit header, so data size need to minus 1 */ 415 data_size = sizeof(desc) / (sizeof(u64)) - 1; 416 417 desc_data = (__le64 *)(&desc[0].data[0]); 418 for (i = 0; i < data_size; i++) { 419 /* data memory is continuous becase only the first desc has a 420 * header in this command 421 */ 422 *data += le64_to_cpu(*desc_data); 423 data++; 424 desc_data++; 425 } 426 427 return 0; 428 } 429 430 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev) 431 { 432 #define HCLGE_REG_NUM_PER_DESC 4 433 434 u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num; 435 u64 *data = (u64 *)(&hdev->mac_stats); 436 struct hclge_desc *desc; 437 __le64 *desc_data; 438 u32 data_size; 439 u32 desc_num; 440 int ret; 441 u32 i; 442 443 /* The first desc has a 64-bit header, so need to consider it */ 444 desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1; 445 446 /* This may be called inside atomic sections, 447 * so GFP_ATOMIC is more suitalbe here 448 */ 449 desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC); 450 if (!desc) 451 return -ENOMEM; 452 453 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true); 454 ret = hclge_cmd_send(&hdev->hw, desc, desc_num); 455 if (ret) { 456 kfree(desc); 457 return ret; 458 } 459 460 data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num); 461 462 desc_data = (__le64 *)(&desc[0].data[0]); 463 for (i = 0; i < data_size; i++) { 464 /* data memory is continuous becase only the first desc has a 465 * header in this command 466 */ 467 *data += le64_to_cpu(*desc_data); 468 data++; 469 desc_data++; 470 } 471 472 kfree(desc); 473 474 return 0; 475 } 476 477 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num) 478 { 479 struct hclge_desc desc; 480 int ret; 481 482 /* Driver needs total register number of both valid registers and 483 * reserved registers, but the old firmware only returns number 484 * of valid registers in device V2. To be compatible with these 485 * devices, driver uses a fixed value. 486 */ 487 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) { 488 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1; 489 return 0; 490 } 491 492 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true); 493 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 494 if (ret) { 495 dev_err(&hdev->pdev->dev, 496 "failed to query mac statistic reg number, ret = %d\n", 497 ret); 498 return ret; 499 } 500 501 *reg_num = le32_to_cpu(desc.data[0]); 502 if (*reg_num == 0) { 503 dev_err(&hdev->pdev->dev, 504 "mac statistic reg number is invalid!\n"); 505 return -ENODATA; 506 } 507 508 return 0; 509 } 510 511 int hclge_mac_update_stats(struct hclge_dev *hdev) 512 { 513 /* The firmware supports the new statistics acquisition method */ 514 if (hdev->ae_dev->dev_specs.mac_stats_num) 515 return hclge_mac_update_stats_complete(hdev); 516 else 517 return hclge_mac_update_stats_defective(hdev); 518 } 519 520 static int hclge_comm_get_count(struct hclge_dev *hdev, 521 const struct hclge_comm_stats_str strs[], 522 u32 size) 523 { 524 int count = 0; 525 u32 i; 526 527 for (i = 0; i < size; i++) 528 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num) 529 count++; 530 531 return count; 532 } 533 534 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, 535 const struct hclge_comm_stats_str strs[], 536 int size, u64 *data) 537 { 538 u64 *buf = data; 539 u32 i; 540 541 for (i = 0; i < size; i++) { 542 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 543 continue; 544 545 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset); 546 buf++; 547 } 548 549 return buf; 550 } 551 552 static u8 *hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, 553 const struct hclge_comm_stats_str strs[], 554 int size, u8 *data) 555 { 556 char *buff = (char *)data; 557 u32 i; 558 559 if (stringset != ETH_SS_STATS) 560 return buff; 561 562 for (i = 0; i < size; i++) { 563 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 564 continue; 565 566 snprintf(buff, ETH_GSTRING_LEN, "%s", strs[i].desc); 567 buff = buff + ETH_GSTRING_LEN; 568 } 569 570 return (u8 *)buff; 571 } 572 573 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 574 { 575 struct hnae3_handle *handle; 576 int status; 577 578 handle = &hdev->vport[0].nic; 579 if (handle->client) { 580 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 581 if (status) { 582 dev_err(&hdev->pdev->dev, 583 "Update TQPS stats fail, status = %d.\n", 584 status); 585 } 586 } 587 588 hclge_update_fec_stats(hdev); 589 590 status = hclge_mac_update_stats(hdev); 591 if (status) 592 dev_err(&hdev->pdev->dev, 593 "Update MAC stats fail, status = %d.\n", status); 594 } 595 596 static void hclge_update_stats(struct hnae3_handle *handle) 597 { 598 struct hclge_vport *vport = hclge_get_vport(handle); 599 struct hclge_dev *hdev = vport->back; 600 int status; 601 602 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 603 return; 604 605 status = hclge_mac_update_stats(hdev); 606 if (status) 607 dev_err(&hdev->pdev->dev, 608 "Update MAC stats fail, status = %d.\n", 609 status); 610 611 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 612 if (status) 613 dev_err(&hdev->pdev->dev, 614 "Update TQPS stats fail, status = %d.\n", 615 status); 616 617 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 618 } 619 620 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 621 { 622 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \ 623 HNAE3_SUPPORT_PHY_LOOPBACK | \ 624 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \ 625 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \ 626 HNAE3_SUPPORT_EXTERNAL_LOOPBACK) 627 628 struct hclge_vport *vport = hclge_get_vport(handle); 629 struct hclge_dev *hdev = vport->back; 630 int count = 0; 631 632 /* Loopback test support rules: 633 * mac: only GE mode support 634 * serdes: all mac mode will support include GE/XGE/LGE/CGE 635 * phy: only support when phy device exist on board 636 */ 637 if (stringset == ETH_SS_TEST) { 638 /* clear loopback bit flags at first */ 639 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 640 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 || 641 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 642 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 643 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 644 count += 1; 645 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; 646 } 647 648 count += 1; 649 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; 650 count += 1; 651 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; 652 count += 1; 653 handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK; 654 655 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv && 656 hdev->hw.mac.phydev->drv->set_loopback) || 657 hnae3_dev_phy_imp_supported(hdev)) { 658 count += 1; 659 handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK; 660 } 661 } else if (stringset == ETH_SS_STATS) { 662 count = hclge_comm_get_count(hdev, g_mac_stats_string, 663 ARRAY_SIZE(g_mac_stats_string)) + 664 hclge_comm_tqps_get_sset_count(handle); 665 } 666 667 return count; 668 } 669 670 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset, 671 u8 *data) 672 { 673 struct hclge_vport *vport = hclge_get_vport(handle); 674 struct hclge_dev *hdev = vport->back; 675 u8 *p = (char *)data; 676 int size; 677 678 if (stringset == ETH_SS_STATS) { 679 size = ARRAY_SIZE(g_mac_stats_string); 680 p = hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, 681 size, p); 682 p = hclge_comm_tqps_get_strings(handle, p); 683 } else if (stringset == ETH_SS_TEST) { 684 if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) { 685 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL], 686 ETH_GSTRING_LEN); 687 p += ETH_GSTRING_LEN; 688 } 689 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { 690 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_APP], 691 ETH_GSTRING_LEN); 692 p += ETH_GSTRING_LEN; 693 } 694 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { 695 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES], 696 ETH_GSTRING_LEN); 697 p += ETH_GSTRING_LEN; 698 } 699 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { 700 memcpy(p, 701 hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES], 702 ETH_GSTRING_LEN); 703 p += ETH_GSTRING_LEN; 704 } 705 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 706 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_PHY], 707 ETH_GSTRING_LEN); 708 p += ETH_GSTRING_LEN; 709 } 710 } 711 } 712 713 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 714 { 715 struct hclge_vport *vport = hclge_get_vport(handle); 716 struct hclge_dev *hdev = vport->back; 717 u64 *p; 718 719 p = hclge_comm_get_stats(hdev, g_mac_stats_string, 720 ARRAY_SIZE(g_mac_stats_string), data); 721 p = hclge_comm_tqps_get_stats(handle, p); 722 } 723 724 static void hclge_get_mac_stat(struct hnae3_handle *handle, 725 struct hns3_mac_stats *mac_stats) 726 { 727 struct hclge_vport *vport = hclge_get_vport(handle); 728 struct hclge_dev *hdev = vport->back; 729 730 hclge_update_stats(handle); 731 732 mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num; 733 mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num; 734 } 735 736 static int hclge_parse_func_status(struct hclge_dev *hdev, 737 struct hclge_func_status_cmd *status) 738 { 739 #define HCLGE_MAC_ID_MASK 0xF 740 741 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 742 return -EINVAL; 743 744 /* Set the pf to main pf */ 745 if (status->pf_state & HCLGE_PF_STATE_MAIN) 746 hdev->flag |= HCLGE_FLAG_MAIN; 747 else 748 hdev->flag &= ~HCLGE_FLAG_MAIN; 749 750 hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK; 751 return 0; 752 } 753 754 static int hclge_query_function_status(struct hclge_dev *hdev) 755 { 756 #define HCLGE_QUERY_MAX_CNT 5 757 758 struct hclge_func_status_cmd *req; 759 struct hclge_desc desc; 760 int timeout = 0; 761 int ret; 762 763 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 764 req = (struct hclge_func_status_cmd *)desc.data; 765 766 do { 767 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 768 if (ret) { 769 dev_err(&hdev->pdev->dev, 770 "query function status failed %d.\n", ret); 771 return ret; 772 } 773 774 /* Check pf reset is done */ 775 if (req->pf_state) 776 break; 777 usleep_range(1000, 2000); 778 } while (timeout++ < HCLGE_QUERY_MAX_CNT); 779 780 return hclge_parse_func_status(hdev, req); 781 } 782 783 static int hclge_query_pf_resource(struct hclge_dev *hdev) 784 { 785 struct hclge_pf_res_cmd *req; 786 struct hclge_desc desc; 787 int ret; 788 789 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 790 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 791 if (ret) { 792 dev_err(&hdev->pdev->dev, 793 "query pf resource failed %d.\n", ret); 794 return ret; 795 } 796 797 req = (struct hclge_pf_res_cmd *)desc.data; 798 hdev->num_tqps = le16_to_cpu(req->tqp_num) + 799 le16_to_cpu(req->ext_tqp_num); 800 hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 801 802 if (req->tx_buf_size) 803 hdev->tx_buf_size = 804 le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S; 805 else 806 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 807 808 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT); 809 810 if (req->dv_buf_size) 811 hdev->dv_buf_size = 812 le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S; 813 else 814 hdev->dv_buf_size = HCLGE_DEFAULT_DV; 815 816 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT); 817 818 hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic); 819 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) { 820 dev_err(&hdev->pdev->dev, 821 "only %u msi resources available, not enough for pf(min:2).\n", 822 hdev->num_nic_msi); 823 return -EINVAL; 824 } 825 826 if (hnae3_dev_roce_supported(hdev)) { 827 hdev->num_roce_msi = 828 le16_to_cpu(req->pf_intr_vector_number_roce); 829 830 /* PF should have NIC vectors and Roce vectors, 831 * NIC vectors are queued before Roce vectors. 832 */ 833 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi; 834 } else { 835 hdev->num_msi = hdev->num_nic_msi; 836 } 837 838 return 0; 839 } 840 841 static int hclge_parse_speed(u8 speed_cmd, u32 *speed) 842 { 843 switch (speed_cmd) { 844 case HCLGE_FW_MAC_SPEED_10M: 845 *speed = HCLGE_MAC_SPEED_10M; 846 break; 847 case HCLGE_FW_MAC_SPEED_100M: 848 *speed = HCLGE_MAC_SPEED_100M; 849 break; 850 case HCLGE_FW_MAC_SPEED_1G: 851 *speed = HCLGE_MAC_SPEED_1G; 852 break; 853 case HCLGE_FW_MAC_SPEED_10G: 854 *speed = HCLGE_MAC_SPEED_10G; 855 break; 856 case HCLGE_FW_MAC_SPEED_25G: 857 *speed = HCLGE_MAC_SPEED_25G; 858 break; 859 case HCLGE_FW_MAC_SPEED_40G: 860 *speed = HCLGE_MAC_SPEED_40G; 861 break; 862 case HCLGE_FW_MAC_SPEED_50G: 863 *speed = HCLGE_MAC_SPEED_50G; 864 break; 865 case HCLGE_FW_MAC_SPEED_100G: 866 *speed = HCLGE_MAC_SPEED_100G; 867 break; 868 case HCLGE_FW_MAC_SPEED_200G: 869 *speed = HCLGE_MAC_SPEED_200G; 870 break; 871 default: 872 return -EINVAL; 873 } 874 875 return 0; 876 } 877 878 static const struct hclge_speed_bit_map speed_bit_map[] = { 879 {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT}, 880 {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT}, 881 {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT}, 882 {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT}, 883 {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT}, 884 {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT}, 885 {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BIT}, 886 {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BIT}, 887 {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT}, 888 }; 889 890 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit) 891 { 892 u16 i; 893 894 for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) { 895 if (speed == speed_bit_map[i].speed) { 896 *speed_bit = speed_bit_map[i].speed_bit; 897 return 0; 898 } 899 } 900 901 return -EINVAL; 902 } 903 904 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed) 905 { 906 struct hclge_vport *vport = hclge_get_vport(handle); 907 struct hclge_dev *hdev = vport->back; 908 u32 speed_ability = hdev->hw.mac.speed_ability; 909 u32 speed_bit = 0; 910 int ret; 911 912 ret = hclge_get_speed_bit(speed, &speed_bit); 913 if (ret) 914 return ret; 915 916 if (speed_bit & speed_ability) 917 return 0; 918 919 return -EINVAL; 920 } 921 922 static void hclge_update_fec_support(struct hclge_mac *mac) 923 { 924 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported); 925 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported); 926 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported); 927 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 928 929 if (mac->fec_ability & BIT(HNAE3_FEC_BASER)) 930 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 931 mac->supported); 932 if (mac->fec_ability & BIT(HNAE3_FEC_RS)) 933 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 934 mac->supported); 935 if (mac->fec_ability & BIT(HNAE3_FEC_LLRS)) 936 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 937 mac->supported); 938 if (mac->fec_ability & BIT(HNAE3_FEC_NONE)) 939 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 940 mac->supported); 941 } 942 943 static void hclge_convert_setting_sr(u16 speed_ability, 944 unsigned long *link_mode) 945 { 946 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 947 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 948 link_mode); 949 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 950 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 951 link_mode); 952 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 953 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 954 link_mode); 955 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 956 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 957 link_mode); 958 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 959 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 960 link_mode); 961 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 962 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 963 link_mode); 964 } 965 966 static void hclge_convert_setting_lr(u16 speed_ability, 967 unsigned long *link_mode) 968 { 969 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 970 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 971 link_mode); 972 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 973 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 974 link_mode); 975 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 976 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 977 link_mode); 978 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 979 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 980 link_mode); 981 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 982 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 983 link_mode); 984 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 985 linkmode_set_bit( 986 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 987 link_mode); 988 } 989 990 static void hclge_convert_setting_cr(u16 speed_ability, 991 unsigned long *link_mode) 992 { 993 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 994 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 995 link_mode); 996 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 997 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 998 link_mode); 999 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1000 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 1001 link_mode); 1002 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1003 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 1004 link_mode); 1005 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1006 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 1007 link_mode); 1008 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1009 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 1010 link_mode); 1011 } 1012 1013 static void hclge_convert_setting_kr(u16 speed_ability, 1014 unsigned long *link_mode) 1015 { 1016 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1017 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1018 link_mode); 1019 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1020 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1021 link_mode); 1022 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1023 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 1024 link_mode); 1025 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1026 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 1027 link_mode); 1028 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1029 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 1030 link_mode); 1031 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1032 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 1033 link_mode); 1034 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1035 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 1036 link_mode); 1037 } 1038 1039 static void hclge_convert_setting_fec(struct hclge_mac *mac) 1040 { 1041 /* If firmware has reported fec_ability, don't need to convert by speed */ 1042 if (mac->fec_ability) 1043 goto out; 1044 1045 switch (mac->speed) { 1046 case HCLGE_MAC_SPEED_10G: 1047 case HCLGE_MAC_SPEED_40G: 1048 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) | 1049 BIT(HNAE3_FEC_NONE); 1050 break; 1051 case HCLGE_MAC_SPEED_25G: 1052 case HCLGE_MAC_SPEED_50G: 1053 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) | 1054 BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE); 1055 break; 1056 case HCLGE_MAC_SPEED_100G: 1057 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1058 BIT(HNAE3_FEC_NONE); 1059 break; 1060 case HCLGE_MAC_SPEED_200G: 1061 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1062 BIT(HNAE3_FEC_LLRS); 1063 break; 1064 default: 1065 mac->fec_ability = 0; 1066 break; 1067 } 1068 1069 out: 1070 hclge_update_fec_support(mac); 1071 } 1072 1073 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 1074 u16 speed_ability) 1075 { 1076 struct hclge_mac *mac = &hdev->hw.mac; 1077 1078 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1079 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1080 mac->supported); 1081 1082 hclge_convert_setting_sr(speed_ability, mac->supported); 1083 hclge_convert_setting_lr(speed_ability, mac->supported); 1084 hclge_convert_setting_cr(speed_ability, mac->supported); 1085 if (hnae3_dev_fec_supported(hdev)) 1086 hclge_convert_setting_fec(mac); 1087 1088 if (hnae3_dev_pause_supported(hdev)) 1089 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1090 1091 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported); 1092 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1093 } 1094 1095 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev, 1096 u16 speed_ability) 1097 { 1098 struct hclge_mac *mac = &hdev->hw.mac; 1099 1100 hclge_convert_setting_kr(speed_ability, mac->supported); 1101 if (hnae3_dev_fec_supported(hdev)) 1102 hclge_convert_setting_fec(mac); 1103 1104 if (hnae3_dev_pause_supported(hdev)) 1105 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1106 1107 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported); 1108 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1109 } 1110 1111 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev, 1112 u16 speed_ability) 1113 { 1114 unsigned long *supported = hdev->hw.mac.supported; 1115 1116 /* default to support all speed for GE port */ 1117 if (!speed_ability) 1118 speed_ability = HCLGE_SUPPORT_GE; 1119 1120 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1121 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1122 supported); 1123 1124 if (speed_ability & HCLGE_SUPPORT_100M_BIT) { 1125 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1126 supported); 1127 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1128 supported); 1129 } 1130 1131 if (speed_ability & HCLGE_SUPPORT_10M_BIT) { 1132 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported); 1133 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported); 1134 } 1135 1136 if (hnae3_dev_pause_supported(hdev)) { 1137 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1138 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 1139 } 1140 1141 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 1142 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 1143 } 1144 1145 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 1146 { 1147 u8 media_type = hdev->hw.mac.media_type; 1148 1149 if (media_type == HNAE3_MEDIA_TYPE_FIBER) 1150 hclge_parse_fiber_link_mode(hdev, speed_ability); 1151 else if (media_type == HNAE3_MEDIA_TYPE_COPPER) 1152 hclge_parse_copper_link_mode(hdev, speed_ability); 1153 else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE) 1154 hclge_parse_backplane_link_mode(hdev, speed_ability); 1155 } 1156 1157 static u32 hclge_get_max_speed(u16 speed_ability) 1158 { 1159 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1160 return HCLGE_MAC_SPEED_200G; 1161 1162 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1163 return HCLGE_MAC_SPEED_100G; 1164 1165 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1166 return HCLGE_MAC_SPEED_50G; 1167 1168 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1169 return HCLGE_MAC_SPEED_40G; 1170 1171 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1172 return HCLGE_MAC_SPEED_25G; 1173 1174 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1175 return HCLGE_MAC_SPEED_10G; 1176 1177 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1178 return HCLGE_MAC_SPEED_1G; 1179 1180 if (speed_ability & HCLGE_SUPPORT_100M_BIT) 1181 return HCLGE_MAC_SPEED_100M; 1182 1183 if (speed_ability & HCLGE_SUPPORT_10M_BIT) 1184 return HCLGE_MAC_SPEED_10M; 1185 1186 return HCLGE_MAC_SPEED_1G; 1187 } 1188 1189 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1190 { 1191 #define HCLGE_TX_SPARE_SIZE_UNIT 4096 1192 #define SPEED_ABILITY_EXT_SHIFT 8 1193 1194 struct hclge_cfg_param_cmd *req; 1195 u64 mac_addr_tmp_high; 1196 u16 speed_ability_ext; 1197 u64 mac_addr_tmp; 1198 unsigned int i; 1199 1200 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1201 1202 /* get the configuration */ 1203 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1204 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1205 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1206 HCLGE_CFG_TQP_DESC_N_M, 1207 HCLGE_CFG_TQP_DESC_N_S); 1208 1209 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1210 HCLGE_CFG_PHY_ADDR_M, 1211 HCLGE_CFG_PHY_ADDR_S); 1212 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1213 HCLGE_CFG_MEDIA_TP_M, 1214 HCLGE_CFG_MEDIA_TP_S); 1215 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1216 HCLGE_CFG_RX_BUF_LEN_M, 1217 HCLGE_CFG_RX_BUF_LEN_S); 1218 /* get mac_address */ 1219 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1220 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1221 HCLGE_CFG_MAC_ADDR_H_M, 1222 HCLGE_CFG_MAC_ADDR_H_S); 1223 1224 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1225 1226 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1227 HCLGE_CFG_DEFAULT_SPEED_M, 1228 HCLGE_CFG_DEFAULT_SPEED_S); 1229 cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1230 HCLGE_CFG_RSS_SIZE_M, 1231 HCLGE_CFG_RSS_SIZE_S); 1232 1233 for (i = 0; i < ETH_ALEN; i++) 1234 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1235 1236 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1237 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1238 1239 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1240 HCLGE_CFG_SPEED_ABILITY_M, 1241 HCLGE_CFG_SPEED_ABILITY_S); 1242 speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]), 1243 HCLGE_CFG_SPEED_ABILITY_EXT_M, 1244 HCLGE_CFG_SPEED_ABILITY_EXT_S); 1245 cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT; 1246 1247 cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]), 1248 HCLGE_CFG_VLAN_FLTR_CAP_M, 1249 HCLGE_CFG_VLAN_FLTR_CAP_S); 1250 1251 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]), 1252 HCLGE_CFG_UMV_TBL_SPACE_M, 1253 HCLGE_CFG_UMV_TBL_SPACE_S); 1254 1255 cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]), 1256 HCLGE_CFG_PF_RSS_SIZE_M, 1257 HCLGE_CFG_PF_RSS_SIZE_S); 1258 1259 /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a 1260 * power of 2, instead of reading out directly. This would 1261 * be more flexible for future changes and expansions. 1262 * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S, 1263 * it does not make sense if PF's field is 0. In this case, PF and VF 1264 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S. 1265 */ 1266 cfg->pf_rss_size_max = cfg->pf_rss_size_max ? 1267 1U << cfg->pf_rss_size_max : 1268 cfg->vf_rss_size_max; 1269 1270 /* The unit of the tx spare buffer size queried from configuration 1271 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is 1272 * needed here. 1273 */ 1274 cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]), 1275 HCLGE_CFG_TX_SPARE_BUF_SIZE_M, 1276 HCLGE_CFG_TX_SPARE_BUF_SIZE_S); 1277 cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT; 1278 } 1279 1280 /* hclge_get_cfg: query the static parameter from flash 1281 * @hdev: pointer to struct hclge_dev 1282 * @hcfg: the config structure to be getted 1283 */ 1284 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1285 { 1286 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1287 struct hclge_cfg_param_cmd *req; 1288 unsigned int i; 1289 int ret; 1290 1291 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1292 u32 offset = 0; 1293 1294 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1295 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1296 true); 1297 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1298 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1299 /* Len should be united by 4 bytes when send to hardware */ 1300 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1301 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1302 req->offset = cpu_to_le32(offset); 1303 } 1304 1305 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1306 if (ret) { 1307 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1308 return ret; 1309 } 1310 1311 hclge_parse_cfg(hcfg, desc); 1312 1313 return 0; 1314 } 1315 1316 static void hclge_set_default_dev_specs(struct hclge_dev *hdev) 1317 { 1318 #define HCLGE_MAX_NON_TSO_BD_NUM 8U 1319 1320 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1321 1322 ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1323 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1324 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1325 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE; 1326 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL; 1327 ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME; 1328 ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM; 1329 ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1330 ae_dev->dev_specs.tnl_num = 0; 1331 } 1332 1333 static void hclge_parse_dev_specs(struct hclge_dev *hdev, 1334 struct hclge_desc *desc) 1335 { 1336 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1337 struct hclge_dev_specs_0_cmd *req0; 1338 struct hclge_dev_specs_1_cmd *req1; 1339 1340 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data; 1341 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data; 1342 1343 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 1344 ae_dev->dev_specs.rss_ind_tbl_size = 1345 le16_to_cpu(req0->rss_ind_tbl_size); 1346 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 1347 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 1348 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate); 1349 ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num); 1350 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 1351 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 1352 ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size); 1353 ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size); 1354 ae_dev->dev_specs.tnl_num = req1->tnl_num; 1355 } 1356 1357 static void hclge_check_dev_specs(struct hclge_dev *hdev) 1358 { 1359 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 1360 1361 if (!dev_specs->max_non_tso_bd_num) 1362 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1363 if (!dev_specs->rss_ind_tbl_size) 1364 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1365 if (!dev_specs->rss_key_size) 1366 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1367 if (!dev_specs->max_tm_rate) 1368 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE; 1369 if (!dev_specs->max_qset_num) 1370 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM; 1371 if (!dev_specs->max_int_gl) 1372 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL; 1373 if (!dev_specs->max_frm_size) 1374 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME; 1375 if (!dev_specs->umv_size) 1376 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1377 } 1378 1379 static int hclge_query_mac_stats_num(struct hclge_dev *hdev) 1380 { 1381 u32 reg_num = 0; 1382 int ret; 1383 1384 ret = hclge_mac_query_reg_num(hdev, ®_num); 1385 if (ret && ret != -EOPNOTSUPP) 1386 return ret; 1387 1388 hdev->ae_dev->dev_specs.mac_stats_num = reg_num; 1389 return 0; 1390 } 1391 1392 static int hclge_query_dev_specs(struct hclge_dev *hdev) 1393 { 1394 struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM]; 1395 int ret; 1396 int i; 1397 1398 ret = hclge_query_mac_stats_num(hdev); 1399 if (ret) 1400 return ret; 1401 1402 /* set default specifications as devices lower than version V3 do not 1403 * support querying specifications from firmware. 1404 */ 1405 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 1406 hclge_set_default_dev_specs(hdev); 1407 return 0; 1408 } 1409 1410 for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1411 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, 1412 true); 1413 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 1414 } 1415 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 1416 1417 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM); 1418 if (ret) 1419 return ret; 1420 1421 hclge_parse_dev_specs(hdev, desc); 1422 hclge_check_dev_specs(hdev); 1423 1424 return 0; 1425 } 1426 1427 static int hclge_get_cap(struct hclge_dev *hdev) 1428 { 1429 int ret; 1430 1431 ret = hclge_query_function_status(hdev); 1432 if (ret) { 1433 dev_err(&hdev->pdev->dev, 1434 "query function status error %d.\n", ret); 1435 return ret; 1436 } 1437 1438 /* get pf resource */ 1439 return hclge_query_pf_resource(hdev); 1440 } 1441 1442 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev) 1443 { 1444 #define HCLGE_MIN_TX_DESC 64 1445 #define HCLGE_MIN_RX_DESC 64 1446 1447 if (!is_kdump_kernel()) 1448 return; 1449 1450 dev_info(&hdev->pdev->dev, 1451 "Running kdump kernel. Using minimal resources\n"); 1452 1453 /* minimal queue pairs equals to the number of vports */ 1454 hdev->num_tqps = hdev->num_req_vfs + 1; 1455 hdev->num_tx_desc = HCLGE_MIN_TX_DESC; 1456 hdev->num_rx_desc = HCLGE_MIN_RX_DESC; 1457 } 1458 1459 static void hclge_init_tc_config(struct hclge_dev *hdev) 1460 { 1461 unsigned int i; 1462 1463 if (hdev->tc_max > HNAE3_MAX_TC || 1464 hdev->tc_max < 1) { 1465 dev_warn(&hdev->pdev->dev, "TC num = %u.\n", 1466 hdev->tc_max); 1467 hdev->tc_max = 1; 1468 } 1469 1470 /* Dev does not support DCB */ 1471 if (!hnae3_dev_dcb_supported(hdev)) { 1472 hdev->tc_max = 1; 1473 hdev->pfc_max = 0; 1474 } else { 1475 hdev->pfc_max = hdev->tc_max; 1476 } 1477 1478 hdev->tm_info.num_tc = 1; 1479 1480 /* Currently not support uncontiuous tc */ 1481 for (i = 0; i < hdev->tm_info.num_tc; i++) 1482 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1483 1484 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1485 } 1486 1487 static int hclge_configure(struct hclge_dev *hdev) 1488 { 1489 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1490 struct hclge_cfg cfg; 1491 int ret; 1492 1493 ret = hclge_get_cfg(hdev, &cfg); 1494 if (ret) 1495 return ret; 1496 1497 hdev->base_tqp_pid = 0; 1498 hdev->vf_rss_size_max = cfg.vf_rss_size_max; 1499 hdev->pf_rss_size_max = cfg.pf_rss_size_max; 1500 hdev->rx_buf_len = cfg.rx_buf_len; 1501 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1502 hdev->hw.mac.media_type = cfg.media_type; 1503 hdev->hw.mac.phy_addr = cfg.phy_addr; 1504 hdev->num_tx_desc = cfg.tqp_desc_num; 1505 hdev->num_rx_desc = cfg.tqp_desc_num; 1506 hdev->tm_info.num_pg = 1; 1507 hdev->tc_max = cfg.tc_num; 1508 hdev->tm_info.hw_pfc_map = 0; 1509 if (cfg.umv_space) 1510 hdev->wanted_umv_size = cfg.umv_space; 1511 else 1512 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size; 1513 hdev->tx_spare_buf_size = cfg.tx_spare_buf_size; 1514 hdev->gro_en = true; 1515 if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF) 1516 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 1517 1518 if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 1519 hdev->fd_en = true; 1520 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 1521 } 1522 1523 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1524 if (ret) { 1525 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n", 1526 cfg.default_speed, ret); 1527 return ret; 1528 } 1529 hdev->hw.mac.req_speed = hdev->hw.mac.speed; 1530 hdev->hw.mac.req_autoneg = AUTONEG_ENABLE; 1531 hdev->hw.mac.req_duplex = DUPLEX_FULL; 1532 1533 hclge_parse_link_mode(hdev, cfg.speed_ability); 1534 1535 hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability); 1536 1537 hclge_init_tc_config(hdev); 1538 hclge_init_kdump_kernel_config(hdev); 1539 1540 return ret; 1541 } 1542 1543 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min, 1544 u16 tso_mss_max) 1545 { 1546 struct hclge_cfg_tso_status_cmd *req; 1547 struct hclge_desc desc; 1548 1549 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1550 1551 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1552 req->tso_mss_min = cpu_to_le16(tso_mss_min); 1553 req->tso_mss_max = cpu_to_le16(tso_mss_max); 1554 1555 return hclge_cmd_send(&hdev->hw, &desc, 1); 1556 } 1557 1558 static int hclge_config_gro(struct hclge_dev *hdev) 1559 { 1560 struct hclge_cfg_gro_status_cmd *req; 1561 struct hclge_desc desc; 1562 int ret; 1563 1564 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 1565 return 0; 1566 1567 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false); 1568 req = (struct hclge_cfg_gro_status_cmd *)desc.data; 1569 1570 req->gro_en = hdev->gro_en ? 1 : 0; 1571 1572 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1573 if (ret) 1574 dev_err(&hdev->pdev->dev, 1575 "GRO hardware config cmd failed, ret = %d\n", ret); 1576 1577 return ret; 1578 } 1579 1580 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1581 { 1582 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1583 struct hclge_comm_tqp *tqp; 1584 int i; 1585 1586 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1587 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 1588 if (!hdev->htqp) 1589 return -ENOMEM; 1590 1591 tqp = hdev->htqp; 1592 1593 for (i = 0; i < hdev->num_tqps; i++) { 1594 tqp->dev = &hdev->pdev->dev; 1595 tqp->index = i; 1596 1597 tqp->q.ae_algo = &ae_algo; 1598 tqp->q.buf_size = hdev->rx_buf_len; 1599 tqp->q.tx_desc_num = hdev->num_tx_desc; 1600 tqp->q.rx_desc_num = hdev->num_rx_desc; 1601 1602 /* need an extended offset to configure queues >= 1603 * HCLGE_TQP_MAX_SIZE_DEV_V2 1604 */ 1605 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2) 1606 tqp->q.io_base = hdev->hw.hw.io_base + 1607 HCLGE_TQP_REG_OFFSET + 1608 i * HCLGE_TQP_REG_SIZE; 1609 else 1610 tqp->q.io_base = hdev->hw.hw.io_base + 1611 HCLGE_TQP_REG_OFFSET + 1612 HCLGE_TQP_EXT_REG_OFFSET + 1613 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) * 1614 HCLGE_TQP_REG_SIZE; 1615 1616 /* when device supports tx push and has device memory, 1617 * the queue can execute push mode or doorbell mode on 1618 * device memory. 1619 */ 1620 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 1621 tqp->q.mem_base = hdev->hw.hw.mem_base + 1622 HCLGE_TQP_MEM_OFFSET(hdev, i); 1623 1624 tqp++; 1625 } 1626 1627 return 0; 1628 } 1629 1630 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1631 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1632 { 1633 struct hclge_tqp_map_cmd *req; 1634 struct hclge_desc desc; 1635 int ret; 1636 1637 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1638 1639 req = (struct hclge_tqp_map_cmd *)desc.data; 1640 req->tqp_id = cpu_to_le16(tqp_pid); 1641 req->tqp_vf = func_id; 1642 req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B; 1643 if (!is_pf) 1644 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B; 1645 req->tqp_vid = cpu_to_le16(tqp_vid); 1646 1647 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1648 if (ret) 1649 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1650 1651 return ret; 1652 } 1653 1654 static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) 1655 { 1656 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1657 struct hclge_dev *hdev = vport->back; 1658 int i, alloced; 1659 1660 for (i = 0, alloced = 0; i < hdev->num_tqps && 1661 alloced < num_tqps; i++) { 1662 if (!hdev->htqp[i].alloced) { 1663 hdev->htqp[i].q.handle = &vport->nic; 1664 hdev->htqp[i].q.tqp_index = alloced; 1665 hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc; 1666 hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc; 1667 kinfo->tqp[alloced] = &hdev->htqp[i].q; 1668 hdev->htqp[i].alloced = true; 1669 alloced++; 1670 } 1671 } 1672 vport->alloc_tqps = alloced; 1673 kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max, 1674 vport->alloc_tqps / hdev->tm_info.num_tc); 1675 1676 /* ensure one to one mapping between irq and queue at default */ 1677 kinfo->rss_size = min_t(u16, kinfo->rss_size, 1678 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc); 1679 1680 return 0; 1681 } 1682 1683 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps, 1684 u16 num_tx_desc, u16 num_rx_desc) 1685 1686 { 1687 struct hnae3_handle *nic = &vport->nic; 1688 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1689 struct hclge_dev *hdev = vport->back; 1690 int ret; 1691 1692 kinfo->num_tx_desc = num_tx_desc; 1693 kinfo->num_rx_desc = num_rx_desc; 1694 1695 kinfo->rx_buf_len = hdev->rx_buf_len; 1696 kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size; 1697 1698 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps, 1699 sizeof(struct hnae3_queue *), GFP_KERNEL); 1700 if (!kinfo->tqp) 1701 return -ENOMEM; 1702 1703 ret = hclge_assign_tqp(vport, num_tqps); 1704 if (ret) 1705 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1706 1707 return ret; 1708 } 1709 1710 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1711 struct hclge_vport *vport) 1712 { 1713 struct hnae3_handle *nic = &vport->nic; 1714 struct hnae3_knic_private_info *kinfo; 1715 u16 i; 1716 1717 kinfo = &nic->kinfo; 1718 for (i = 0; i < vport->alloc_tqps; i++) { 1719 struct hclge_comm_tqp *q = 1720 container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); 1721 bool is_pf; 1722 int ret; 1723 1724 is_pf = !(vport->vport_id); 1725 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1726 i, is_pf); 1727 if (ret) 1728 return ret; 1729 } 1730 1731 return 0; 1732 } 1733 1734 static int hclge_map_tqp(struct hclge_dev *hdev) 1735 { 1736 struct hclge_vport *vport = hdev->vport; 1737 u16 i, num_vport; 1738 1739 num_vport = hdev->num_req_vfs + 1; 1740 for (i = 0; i < num_vport; i++) { 1741 int ret; 1742 1743 ret = hclge_map_tqp_to_vport(hdev, vport); 1744 if (ret) 1745 return ret; 1746 1747 vport++; 1748 } 1749 1750 return 0; 1751 } 1752 1753 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1754 { 1755 struct hnae3_handle *nic = &vport->nic; 1756 struct hclge_dev *hdev = vport->back; 1757 int ret; 1758 1759 nic->pdev = hdev->pdev; 1760 nic->ae_algo = &ae_algo; 1761 bitmap_copy(nic->numa_node_mask.bits, hdev->numa_node_mask.bits, 1762 MAX_NUMNODES); 1763 nic->kinfo.io_base = hdev->hw.hw.io_base; 1764 1765 ret = hclge_knic_setup(vport, num_tqps, 1766 hdev->num_tx_desc, hdev->num_rx_desc); 1767 if (ret) 1768 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret); 1769 1770 return ret; 1771 } 1772 1773 static int hclge_alloc_vport(struct hclge_dev *hdev) 1774 { 1775 struct pci_dev *pdev = hdev->pdev; 1776 struct hclge_vport *vport; 1777 u32 tqp_main_vport; 1778 u32 tqp_per_vport; 1779 int num_vport, i; 1780 int ret; 1781 1782 /* We need to alloc a vport for main NIC of PF */ 1783 num_vport = hdev->num_req_vfs + 1; 1784 1785 if (hdev->num_tqps < num_vport) { 1786 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)", 1787 hdev->num_tqps, num_vport); 1788 return -EINVAL; 1789 } 1790 1791 /* Alloc the same number of TQPs for every vport */ 1792 tqp_per_vport = hdev->num_tqps / num_vport; 1793 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1794 1795 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1796 GFP_KERNEL); 1797 if (!vport) 1798 return -ENOMEM; 1799 1800 hdev->vport = vport; 1801 hdev->num_alloc_vport = num_vport; 1802 1803 if (IS_ENABLED(CONFIG_PCI_IOV)) 1804 hdev->num_alloc_vfs = hdev->num_req_vfs; 1805 1806 for (i = 0; i < num_vport; i++) { 1807 vport->back = hdev; 1808 vport->vport_id = i; 1809 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO; 1810 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 1811 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE; 1812 vport->port_base_vlan_cfg.tbl_sta = true; 1813 vport->rxvlan_cfg.rx_vlan_offload_en = true; 1814 vport->req_vlan_fltr_en = true; 1815 INIT_LIST_HEAD(&vport->vlan_list); 1816 INIT_LIST_HEAD(&vport->uc_mac_list); 1817 INIT_LIST_HEAD(&vport->mc_mac_list); 1818 spin_lock_init(&vport->mac_list_lock); 1819 1820 if (i == 0) 1821 ret = hclge_vport_setup(vport, tqp_main_vport); 1822 else 1823 ret = hclge_vport_setup(vport, tqp_per_vport); 1824 if (ret) { 1825 dev_err(&pdev->dev, 1826 "vport setup failed for vport %d, %d\n", 1827 i, ret); 1828 return ret; 1829 } 1830 1831 vport++; 1832 } 1833 1834 return 0; 1835 } 1836 1837 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1838 struct hclge_pkt_buf_alloc *buf_alloc) 1839 { 1840 /* TX buffer size is unit by 128 byte */ 1841 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1842 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1843 struct hclge_tx_buff_alloc_cmd *req; 1844 struct hclge_desc desc; 1845 int ret; 1846 u8 i; 1847 1848 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1849 1850 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1851 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1852 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1853 1854 req->tx_pkt_buff[i] = 1855 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1856 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1857 } 1858 1859 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1860 if (ret) 1861 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1862 ret); 1863 1864 return ret; 1865 } 1866 1867 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1868 struct hclge_pkt_buf_alloc *buf_alloc) 1869 { 1870 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1871 1872 if (ret) 1873 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1874 1875 return ret; 1876 } 1877 1878 static u32 hclge_get_tc_num(struct hclge_dev *hdev) 1879 { 1880 unsigned int i; 1881 u32 cnt = 0; 1882 1883 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1884 if (hdev->hw_tc_map & BIT(i)) 1885 cnt++; 1886 return cnt; 1887 } 1888 1889 /* Get the number of pfc enabled TCs, which have private buffer */ 1890 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1891 struct hclge_pkt_buf_alloc *buf_alloc) 1892 { 1893 struct hclge_priv_buf *priv; 1894 unsigned int i; 1895 int cnt = 0; 1896 1897 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1898 priv = &buf_alloc->priv_buf[i]; 1899 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1900 priv->enable) 1901 cnt++; 1902 } 1903 1904 return cnt; 1905 } 1906 1907 /* Get the number of pfc disabled TCs, which have private buffer */ 1908 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1909 struct hclge_pkt_buf_alloc *buf_alloc) 1910 { 1911 struct hclge_priv_buf *priv; 1912 unsigned int i; 1913 int cnt = 0; 1914 1915 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1916 priv = &buf_alloc->priv_buf[i]; 1917 if (hdev->hw_tc_map & BIT(i) && 1918 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 1919 priv->enable) 1920 cnt++; 1921 } 1922 1923 return cnt; 1924 } 1925 1926 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1927 { 1928 struct hclge_priv_buf *priv; 1929 u32 rx_priv = 0; 1930 int i; 1931 1932 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1933 priv = &buf_alloc->priv_buf[i]; 1934 if (priv->enable) 1935 rx_priv += priv->buf_size; 1936 } 1937 return rx_priv; 1938 } 1939 1940 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1941 { 1942 u32 i, total_tx_size = 0; 1943 1944 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1945 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 1946 1947 return total_tx_size; 1948 } 1949 1950 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 1951 struct hclge_pkt_buf_alloc *buf_alloc, 1952 u32 rx_all) 1953 { 1954 u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 1955 u32 tc_num = hclge_get_tc_num(hdev); 1956 u32 shared_buf, aligned_mps; 1957 u32 rx_priv; 1958 int i; 1959 1960 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT); 1961 1962 if (hnae3_dev_dcb_supported(hdev)) 1963 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps + 1964 hdev->dv_buf_size; 1965 else 1966 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF 1967 + hdev->dv_buf_size; 1968 1969 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 1970 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc), 1971 HCLGE_BUF_SIZE_UNIT); 1972 1973 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 1974 if (rx_all < rx_priv + shared_std) 1975 return false; 1976 1977 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT); 1978 buf_alloc->s_buf.buf_size = shared_buf; 1979 if (hnae3_dev_dcb_supported(hdev)) { 1980 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size; 1981 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 1982 - roundup(aligned_mps / HCLGE_BUF_DIV_BY, 1983 HCLGE_BUF_SIZE_UNIT); 1984 } else { 1985 buf_alloc->s_buf.self.high = aligned_mps + 1986 HCLGE_NON_DCB_ADDITIONAL_BUF; 1987 buf_alloc->s_buf.self.low = aligned_mps; 1988 } 1989 1990 if (hnae3_dev_dcb_supported(hdev)) { 1991 hi_thrd = shared_buf - hdev->dv_buf_size; 1992 1993 if (tc_num <= NEED_RESERVE_TC_NUM) 1994 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 1995 / BUF_MAX_PERCENT; 1996 1997 if (tc_num) 1998 hi_thrd = hi_thrd / tc_num; 1999 2000 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps); 2001 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT); 2002 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY; 2003 } else { 2004 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF; 2005 lo_thrd = aligned_mps; 2006 } 2007 2008 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2009 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 2010 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 2011 } 2012 2013 return true; 2014 } 2015 2016 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 2017 struct hclge_pkt_buf_alloc *buf_alloc) 2018 { 2019 u32 i, total_size; 2020 2021 total_size = hdev->pkt_buf_size; 2022 2023 /* alloc tx buffer for all enabled tc */ 2024 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2025 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2026 2027 if (hdev->hw_tc_map & BIT(i)) { 2028 if (total_size < hdev->tx_buf_size) 2029 return -ENOMEM; 2030 2031 priv->tx_buf_size = hdev->tx_buf_size; 2032 } else { 2033 priv->tx_buf_size = 0; 2034 } 2035 2036 total_size -= priv->tx_buf_size; 2037 } 2038 2039 return 0; 2040 } 2041 2042 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max, 2043 struct hclge_pkt_buf_alloc *buf_alloc) 2044 { 2045 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2046 u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2047 unsigned int i; 2048 2049 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2050 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2051 2052 priv->enable = 0; 2053 priv->wl.low = 0; 2054 priv->wl.high = 0; 2055 priv->buf_size = 0; 2056 2057 if (!(hdev->hw_tc_map & BIT(i))) 2058 continue; 2059 2060 priv->enable = 1; 2061 2062 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 2063 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT; 2064 priv->wl.high = roundup(priv->wl.low + aligned_mps, 2065 HCLGE_BUF_SIZE_UNIT); 2066 } else { 2067 priv->wl.low = 0; 2068 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) : 2069 aligned_mps; 2070 } 2071 2072 priv->buf_size = priv->wl.high + hdev->dv_buf_size; 2073 } 2074 2075 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2076 } 2077 2078 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev, 2079 struct hclge_pkt_buf_alloc *buf_alloc) 2080 { 2081 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2082 int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 2083 int i; 2084 2085 /* let the last to be cleared first */ 2086 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2087 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2088 unsigned int mask = BIT((unsigned int)i); 2089 2090 if (hdev->hw_tc_map & mask && 2091 !(hdev->tm_info.hw_pfc_map & mask)) { 2092 /* Clear the no pfc TC private buffer */ 2093 priv->wl.low = 0; 2094 priv->wl.high = 0; 2095 priv->buf_size = 0; 2096 priv->enable = 0; 2097 no_pfc_priv_num--; 2098 } 2099 2100 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2101 no_pfc_priv_num == 0) 2102 break; 2103 } 2104 2105 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2106 } 2107 2108 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev, 2109 struct hclge_pkt_buf_alloc *buf_alloc) 2110 { 2111 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2112 int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 2113 int i; 2114 2115 /* let the last to be cleared first */ 2116 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2117 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2118 unsigned int mask = BIT((unsigned int)i); 2119 2120 if (hdev->hw_tc_map & mask && 2121 hdev->tm_info.hw_pfc_map & mask) { 2122 /* Reduce the number of pfc TC with private buffer */ 2123 priv->wl.low = 0; 2124 priv->enable = 0; 2125 priv->wl.high = 0; 2126 priv->buf_size = 0; 2127 pfc_priv_num--; 2128 } 2129 2130 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2131 pfc_priv_num == 0) 2132 break; 2133 } 2134 2135 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2136 } 2137 2138 static int hclge_only_alloc_priv_buff(struct hclge_dev *hdev, 2139 struct hclge_pkt_buf_alloc *buf_alloc) 2140 { 2141 #define COMPENSATE_BUFFER 0x3C00 2142 #define COMPENSATE_HALF_MPS_NUM 5 2143 #define PRIV_WL_GAP 0x1800 2144 2145 u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2146 u32 tc_num = hclge_get_tc_num(hdev); 2147 u32 half_mps = hdev->mps >> 1; 2148 u32 min_rx_priv; 2149 unsigned int i; 2150 2151 if (tc_num) 2152 rx_priv = rx_priv / tc_num; 2153 2154 if (tc_num <= NEED_RESERVE_TC_NUM) 2155 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 2156 2157 min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER + 2158 COMPENSATE_HALF_MPS_NUM * half_mps; 2159 min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT); 2160 rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT); 2161 if (rx_priv < min_rx_priv) 2162 return false; 2163 2164 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2165 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2166 2167 priv->enable = 0; 2168 priv->wl.low = 0; 2169 priv->wl.high = 0; 2170 priv->buf_size = 0; 2171 2172 if (!(hdev->hw_tc_map & BIT(i))) 2173 continue; 2174 2175 priv->enable = 1; 2176 priv->buf_size = rx_priv; 2177 priv->wl.high = rx_priv - hdev->dv_buf_size; 2178 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 2179 } 2180 2181 buf_alloc->s_buf.buf_size = 0; 2182 2183 return true; 2184 } 2185 2186 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 2187 * @hdev: pointer to struct hclge_dev 2188 * @buf_alloc: pointer to buffer calculation data 2189 * @return: 0: calculate successful, negative: fail 2190 */ 2191 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 2192 struct hclge_pkt_buf_alloc *buf_alloc) 2193 { 2194 /* When DCB is not supported, rx private buffer is not allocated. */ 2195 if (!hnae3_dev_dcb_supported(hdev)) { 2196 u32 rx_all = hdev->pkt_buf_size; 2197 2198 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 2199 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 2200 return -ENOMEM; 2201 2202 return 0; 2203 } 2204 2205 if (hclge_only_alloc_priv_buff(hdev, buf_alloc)) 2206 return 0; 2207 2208 if (hclge_rx_buf_calc_all(hdev, true, buf_alloc)) 2209 return 0; 2210 2211 /* try to decrease the buffer size */ 2212 if (hclge_rx_buf_calc_all(hdev, false, buf_alloc)) 2213 return 0; 2214 2215 if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc)) 2216 return 0; 2217 2218 if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc)) 2219 return 0; 2220 2221 return -ENOMEM; 2222 } 2223 2224 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 2225 struct hclge_pkt_buf_alloc *buf_alloc) 2226 { 2227 struct hclge_rx_priv_buff_cmd *req; 2228 struct hclge_desc desc; 2229 int ret; 2230 int i; 2231 2232 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 2233 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 2234 2235 /* Alloc private buffer TCs */ 2236 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2237 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2238 2239 req->buf_num[i] = 2240 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 2241 req->buf_num[i] |= 2242 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 2243 } 2244 2245 req->shared_buf = 2246 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 2247 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 2248 2249 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2250 if (ret) 2251 dev_err(&hdev->pdev->dev, 2252 "rx private buffer alloc cmd failed %d\n", ret); 2253 2254 return ret; 2255 } 2256 2257 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 2258 struct hclge_pkt_buf_alloc *buf_alloc) 2259 { 2260 struct hclge_rx_priv_wl_buf *req; 2261 struct hclge_priv_buf *priv; 2262 struct hclge_desc desc[2]; 2263 int i, j; 2264 int ret; 2265 2266 for (i = 0; i < 2; i++) { 2267 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 2268 false); 2269 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 2270 2271 /* The first descriptor set the NEXT bit to 1 */ 2272 if (i == 0) 2273 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2274 else 2275 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2276 2277 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2278 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 2279 2280 priv = &buf_alloc->priv_buf[idx]; 2281 req->tc_wl[j].high = 2282 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 2283 req->tc_wl[j].high |= 2284 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2285 req->tc_wl[j].low = 2286 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 2287 req->tc_wl[j].low |= 2288 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2289 } 2290 } 2291 2292 /* Send 2 descriptor at one time */ 2293 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2294 if (ret) 2295 dev_err(&hdev->pdev->dev, 2296 "rx private waterline config cmd failed %d\n", 2297 ret); 2298 return ret; 2299 } 2300 2301 static int hclge_common_thrd_config(struct hclge_dev *hdev, 2302 struct hclge_pkt_buf_alloc *buf_alloc) 2303 { 2304 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 2305 struct hclge_rx_com_thrd *req; 2306 struct hclge_desc desc[2]; 2307 struct hclge_tc_thrd *tc; 2308 int i, j; 2309 int ret; 2310 2311 for (i = 0; i < 2; i++) { 2312 hclge_cmd_setup_basic_desc(&desc[i], 2313 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 2314 req = (struct hclge_rx_com_thrd *)&desc[i].data; 2315 2316 /* The first descriptor set the NEXT bit to 1 */ 2317 if (i == 0) 2318 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2319 else 2320 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2321 2322 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2323 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 2324 2325 req->com_thrd[j].high = 2326 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 2327 req->com_thrd[j].high |= 2328 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2329 req->com_thrd[j].low = 2330 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 2331 req->com_thrd[j].low |= 2332 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2333 } 2334 } 2335 2336 /* Send 2 descriptors at one time */ 2337 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2338 if (ret) 2339 dev_err(&hdev->pdev->dev, 2340 "common threshold config cmd failed %d\n", ret); 2341 return ret; 2342 } 2343 2344 static int hclge_common_wl_config(struct hclge_dev *hdev, 2345 struct hclge_pkt_buf_alloc *buf_alloc) 2346 { 2347 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 2348 struct hclge_rx_com_wl *req; 2349 struct hclge_desc desc; 2350 int ret; 2351 2352 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 2353 2354 req = (struct hclge_rx_com_wl *)desc.data; 2355 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 2356 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2357 2358 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 2359 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2360 2361 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2362 if (ret) 2363 dev_err(&hdev->pdev->dev, 2364 "common waterline config cmd failed %d\n", ret); 2365 2366 return ret; 2367 } 2368 2369 int hclge_buffer_alloc(struct hclge_dev *hdev) 2370 { 2371 struct hclge_pkt_buf_alloc *pkt_buf; 2372 int ret; 2373 2374 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 2375 if (!pkt_buf) 2376 return -ENOMEM; 2377 2378 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 2379 if (ret) { 2380 dev_err(&hdev->pdev->dev, 2381 "could not calc tx buffer size for all TCs %d\n", ret); 2382 goto out; 2383 } 2384 2385 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 2386 if (ret) { 2387 dev_err(&hdev->pdev->dev, 2388 "could not alloc tx buffers %d\n", ret); 2389 goto out; 2390 } 2391 2392 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 2393 if (ret) { 2394 dev_err(&hdev->pdev->dev, 2395 "could not calc rx priv buffer size for all TCs %d\n", 2396 ret); 2397 goto out; 2398 } 2399 2400 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 2401 if (ret) { 2402 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 2403 ret); 2404 goto out; 2405 } 2406 2407 if (hnae3_dev_dcb_supported(hdev)) { 2408 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2409 if (ret) { 2410 dev_err(&hdev->pdev->dev, 2411 "could not configure rx private waterline %d\n", 2412 ret); 2413 goto out; 2414 } 2415 2416 ret = hclge_common_thrd_config(hdev, pkt_buf); 2417 if (ret) { 2418 dev_err(&hdev->pdev->dev, 2419 "could not configure common threshold %d\n", 2420 ret); 2421 goto out; 2422 } 2423 } 2424 2425 ret = hclge_common_wl_config(hdev, pkt_buf); 2426 if (ret) 2427 dev_err(&hdev->pdev->dev, 2428 "could not configure common waterline %d\n", ret); 2429 2430 out: 2431 kfree(pkt_buf); 2432 return ret; 2433 } 2434 2435 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2436 { 2437 struct hnae3_handle *roce = &vport->roce; 2438 struct hnae3_handle *nic = &vport->nic; 2439 struct hclge_dev *hdev = vport->back; 2440 2441 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2442 2443 if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi) 2444 return -EINVAL; 2445 2446 roce->rinfo.base_vector = hdev->num_nic_msi; 2447 2448 roce->rinfo.netdev = nic->kinfo.netdev; 2449 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2450 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2451 2452 roce->pdev = nic->pdev; 2453 roce->ae_algo = nic->ae_algo; 2454 bitmap_copy(roce->numa_node_mask.bits, nic->numa_node_mask.bits, 2455 MAX_NUMNODES); 2456 2457 return 0; 2458 } 2459 2460 static int hclge_init_msi(struct hclge_dev *hdev) 2461 { 2462 struct pci_dev *pdev = hdev->pdev; 2463 int vectors; 2464 int i; 2465 2466 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2467 hdev->num_msi, 2468 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2469 if (vectors < 0) { 2470 dev_err(&pdev->dev, 2471 "failed(%d) to allocate MSI/MSI-X vectors\n", 2472 vectors); 2473 return vectors; 2474 } 2475 if (vectors < hdev->num_msi) 2476 dev_warn(&hdev->pdev->dev, 2477 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2478 hdev->num_msi, vectors); 2479 2480 hdev->num_msi = vectors; 2481 hdev->num_msi_left = vectors; 2482 2483 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2484 sizeof(u16), GFP_KERNEL); 2485 if (!hdev->vector_status) { 2486 pci_free_irq_vectors(pdev); 2487 return -ENOMEM; 2488 } 2489 2490 for (i = 0; i < hdev->num_msi; i++) 2491 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2492 2493 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2494 sizeof(int), GFP_KERNEL); 2495 if (!hdev->vector_irq) { 2496 pci_free_irq_vectors(pdev); 2497 return -ENOMEM; 2498 } 2499 2500 return 0; 2501 } 2502 2503 static u8 hclge_check_speed_dup(u8 duplex, int speed) 2504 { 2505 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 2506 duplex = HCLGE_MAC_FULL; 2507 2508 return duplex; 2509 } 2510 2511 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = { 2512 {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M}, 2513 {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M}, 2514 {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G}, 2515 {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G}, 2516 {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G}, 2517 {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G}, 2518 {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G}, 2519 {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G}, 2520 {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G}, 2521 }; 2522 2523 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw) 2524 { 2525 u16 i; 2526 2527 for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) { 2528 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) { 2529 *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw; 2530 return 0; 2531 } 2532 } 2533 2534 return -EINVAL; 2535 } 2536 2537 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 2538 u8 duplex, u8 lane_num) 2539 { 2540 struct hclge_config_mac_speed_dup_cmd *req; 2541 struct hclge_desc desc; 2542 u32 speed_fw; 2543 int ret; 2544 2545 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2546 2547 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2548 2549 if (duplex) 2550 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1); 2551 2552 ret = hclge_convert_to_fw_speed(speed, &speed_fw); 2553 if (ret) { 2554 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2555 return ret; 2556 } 2557 2558 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S, 2559 speed_fw); 2560 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2561 1); 2562 req->lane_num = lane_num; 2563 2564 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2565 if (ret) { 2566 dev_err(&hdev->pdev->dev, 2567 "mac speed/duplex config cmd failed %d.\n", ret); 2568 return ret; 2569 } 2570 2571 return 0; 2572 } 2573 2574 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num) 2575 { 2576 struct hclge_mac *mac = &hdev->hw.mac; 2577 int ret; 2578 2579 duplex = hclge_check_speed_dup(duplex, speed); 2580 if (!mac->support_autoneg && mac->speed == speed && 2581 mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0)) 2582 return 0; 2583 2584 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num); 2585 if (ret) 2586 return ret; 2587 2588 hdev->hw.mac.speed = speed; 2589 hdev->hw.mac.duplex = duplex; 2590 if (!lane_num) 2591 hdev->hw.mac.lane_num = lane_num; 2592 2593 return 0; 2594 } 2595 2596 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2597 u8 duplex, u8 lane_num) 2598 { 2599 struct hclge_vport *vport = hclge_get_vport(handle); 2600 struct hclge_dev *hdev = vport->back; 2601 int ret; 2602 2603 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num); 2604 2605 if (ret) 2606 return ret; 2607 2608 hdev->hw.mac.req_speed = speed; 2609 hdev->hw.mac.req_duplex = duplex; 2610 2611 return 0; 2612 } 2613 2614 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2615 { 2616 struct hclge_config_auto_neg_cmd *req; 2617 struct hclge_desc desc; 2618 u32 flag = 0; 2619 int ret; 2620 2621 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2622 2623 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2624 if (enable) 2625 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U); 2626 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2627 2628 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2629 if (ret) 2630 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2631 ret); 2632 2633 return ret; 2634 } 2635 2636 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2637 { 2638 struct hclge_vport *vport = hclge_get_vport(handle); 2639 struct hclge_dev *hdev = vport->back; 2640 2641 if (!hdev->hw.mac.support_autoneg) { 2642 if (enable) { 2643 dev_err(&hdev->pdev->dev, 2644 "autoneg is not supported by current port\n"); 2645 return -EOPNOTSUPP; 2646 } else { 2647 return 0; 2648 } 2649 } 2650 2651 return hclge_set_autoneg_en(hdev, enable); 2652 } 2653 2654 static int hclge_get_autoneg(struct hnae3_handle *handle) 2655 { 2656 struct hclge_vport *vport = hclge_get_vport(handle); 2657 struct hclge_dev *hdev = vport->back; 2658 struct phy_device *phydev = hdev->hw.mac.phydev; 2659 2660 if (phydev) 2661 return phydev->autoneg; 2662 2663 return hdev->hw.mac.autoneg; 2664 } 2665 2666 static int hclge_restart_autoneg(struct hnae3_handle *handle) 2667 { 2668 struct hclge_vport *vport = hclge_get_vport(handle); 2669 struct hclge_dev *hdev = vport->back; 2670 int ret; 2671 2672 dev_dbg(&hdev->pdev->dev, "restart autoneg\n"); 2673 2674 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2675 if (ret) 2676 return ret; 2677 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2678 } 2679 2680 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt) 2681 { 2682 struct hclge_vport *vport = hclge_get_vport(handle); 2683 struct hclge_dev *hdev = vport->back; 2684 2685 if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) 2686 return hclge_set_autoneg_en(hdev, !halt); 2687 2688 return 0; 2689 } 2690 2691 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev, 2692 struct hclge_desc *desc, u32 desc_len) 2693 { 2694 u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2; 2695 u32 desc_index = 0; 2696 u32 data_index = 0; 2697 u32 i; 2698 2699 for (i = 0; i < lane_size; i++) { 2700 if (data_index >= HCLGE_DESC_DATA_LEN) { 2701 desc_index++; 2702 data_index = 0; 2703 } 2704 2705 if (desc_index >= desc_len) 2706 return; 2707 2708 hdev->fec_stats.per_lanes[i] += 2709 le32_to_cpu(desc[desc_index].data[data_index]); 2710 data_index++; 2711 } 2712 } 2713 2714 static void hclge_parse_fec_stats(struct hclge_dev *hdev, 2715 struct hclge_desc *desc, u32 desc_len) 2716 { 2717 struct hclge_query_fec_stats_cmd *req; 2718 2719 req = (struct hclge_query_fec_stats_cmd *)desc[0].data; 2720 2721 hdev->fec_stats.base_r_lane_num = req->base_r_lane_num; 2722 hdev->fec_stats.rs_corr_blocks += 2723 le32_to_cpu(req->rs_fec_corr_blocks); 2724 hdev->fec_stats.rs_uncorr_blocks += 2725 le32_to_cpu(req->rs_fec_uncorr_blocks); 2726 hdev->fec_stats.rs_error_blocks += 2727 le32_to_cpu(req->rs_fec_error_blocks); 2728 hdev->fec_stats.base_r_corr_blocks += 2729 le32_to_cpu(req->base_r_fec_corr_blocks); 2730 hdev->fec_stats.base_r_uncorr_blocks += 2731 le32_to_cpu(req->base_r_fec_uncorr_blocks); 2732 2733 hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1); 2734 } 2735 2736 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev) 2737 { 2738 struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM]; 2739 int ret; 2740 u32 i; 2741 2742 for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) { 2743 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS, 2744 true); 2745 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1)) 2746 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2747 } 2748 2749 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM); 2750 if (ret) 2751 return ret; 2752 2753 hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM); 2754 2755 return 0; 2756 } 2757 2758 static void hclge_update_fec_stats(struct hclge_dev *hdev) 2759 { 2760 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2761 int ret; 2762 2763 if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || 2764 test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state)) 2765 return; 2766 2767 ret = hclge_update_fec_stats_hw(hdev); 2768 if (ret) 2769 dev_err(&hdev->pdev->dev, 2770 "failed to update fec stats, ret = %d\n", ret); 2771 2772 clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state); 2773 } 2774 2775 static void hclge_get_fec_stats_total(struct hclge_dev *hdev, 2776 struct ethtool_fec_stats *fec_stats) 2777 { 2778 fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks; 2779 fec_stats->uncorrectable_blocks.total = 2780 hdev->fec_stats.rs_uncorr_blocks; 2781 } 2782 2783 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev, 2784 struct ethtool_fec_stats *fec_stats) 2785 { 2786 u32 i; 2787 2788 if (hdev->fec_stats.base_r_lane_num == 0 || 2789 hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) { 2790 dev_err(&hdev->pdev->dev, 2791 "fec stats lane number(%llu) is invalid\n", 2792 hdev->fec_stats.base_r_lane_num); 2793 return; 2794 } 2795 2796 for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) { 2797 fec_stats->corrected_blocks.lanes[i] = 2798 hdev->fec_stats.base_r_corr_per_lanes[i]; 2799 fec_stats->uncorrectable_blocks.lanes[i] = 2800 hdev->fec_stats.base_r_uncorr_per_lanes[i]; 2801 } 2802 } 2803 2804 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev, 2805 struct ethtool_fec_stats *fec_stats) 2806 { 2807 u32 fec_mode = hdev->hw.mac.fec_mode; 2808 2809 switch (fec_mode) { 2810 case BIT(HNAE3_FEC_RS): 2811 case BIT(HNAE3_FEC_LLRS): 2812 hclge_get_fec_stats_total(hdev, fec_stats); 2813 break; 2814 case BIT(HNAE3_FEC_BASER): 2815 hclge_get_fec_stats_lanes(hdev, fec_stats); 2816 break; 2817 default: 2818 dev_err(&hdev->pdev->dev, 2819 "fec stats is not supported by current fec mode(0x%x)\n", 2820 fec_mode); 2821 break; 2822 } 2823 } 2824 2825 static void hclge_get_fec_stats(struct hnae3_handle *handle, 2826 struct ethtool_fec_stats *fec_stats) 2827 { 2828 struct hclge_vport *vport = hclge_get_vport(handle); 2829 struct hclge_dev *hdev = vport->back; 2830 u32 fec_mode = hdev->hw.mac.fec_mode; 2831 2832 if (fec_mode == BIT(HNAE3_FEC_NONE) || 2833 fec_mode == BIT(HNAE3_FEC_AUTO) || 2834 fec_mode == BIT(HNAE3_FEC_USER_DEF)) 2835 return; 2836 2837 hclge_update_fec_stats(hdev); 2838 2839 hclge_comm_get_fec_stats(hdev, fec_stats); 2840 } 2841 2842 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode) 2843 { 2844 struct hclge_config_fec_cmd *req; 2845 struct hclge_desc desc; 2846 int ret; 2847 2848 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false); 2849 2850 req = (struct hclge_config_fec_cmd *)desc.data; 2851 if (fec_mode & BIT(HNAE3_FEC_AUTO)) 2852 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1); 2853 if (fec_mode & BIT(HNAE3_FEC_RS)) 2854 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2855 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS); 2856 if (fec_mode & BIT(HNAE3_FEC_LLRS)) 2857 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2858 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS); 2859 if (fec_mode & BIT(HNAE3_FEC_BASER)) 2860 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2861 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER); 2862 2863 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2864 if (ret) 2865 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret); 2866 2867 return ret; 2868 } 2869 2870 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode) 2871 { 2872 struct hclge_vport *vport = hclge_get_vport(handle); 2873 struct hclge_dev *hdev = vport->back; 2874 struct hclge_mac *mac = &hdev->hw.mac; 2875 int ret; 2876 2877 if (fec_mode && !(mac->fec_ability & fec_mode)) { 2878 dev_err(&hdev->pdev->dev, "unsupported fec mode\n"); 2879 return -EINVAL; 2880 } 2881 2882 ret = hclge_set_fec_hw(hdev, fec_mode); 2883 if (ret) 2884 return ret; 2885 2886 mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF); 2887 return 0; 2888 } 2889 2890 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability, 2891 u8 *fec_mode) 2892 { 2893 struct hclge_vport *vport = hclge_get_vport(handle); 2894 struct hclge_dev *hdev = vport->back; 2895 struct hclge_mac *mac = &hdev->hw.mac; 2896 2897 if (fec_ability) 2898 *fec_ability = mac->fec_ability; 2899 if (fec_mode) 2900 *fec_mode = mac->fec_mode; 2901 } 2902 2903 static int hclge_mac_init(struct hclge_dev *hdev) 2904 { 2905 struct hclge_mac *mac = &hdev->hw.mac; 2906 int ret; 2907 2908 hdev->support_sfp_query = true; 2909 2910 if (!test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 2911 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 2912 2913 if (hdev->hw.mac.support_autoneg) { 2914 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg); 2915 if (ret) 2916 return ret; 2917 } 2918 2919 if (!hdev->hw.mac.autoneg) { 2920 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.req_speed, 2921 hdev->hw.mac.req_duplex, 2922 hdev->hw.mac.lane_num); 2923 if (ret) 2924 return ret; 2925 } 2926 2927 mac->link = 0; 2928 2929 if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { 2930 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode); 2931 if (ret) 2932 return ret; 2933 } 2934 2935 ret = hclge_set_mac_mtu(hdev, hdev->mps); 2936 if (ret) { 2937 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret); 2938 return ret; 2939 } 2940 2941 ret = hclge_set_default_loopback(hdev); 2942 if (ret) 2943 return ret; 2944 2945 ret = hclge_buffer_alloc(hdev); 2946 if (ret) 2947 dev_err(&hdev->pdev->dev, 2948 "allocate buffer fail, ret=%d\n", ret); 2949 2950 return ret; 2951 } 2952 2953 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 2954 { 2955 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2956 !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) { 2957 hdev->last_mbx_scheduled = jiffies; 2958 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2959 } 2960 } 2961 2962 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 2963 { 2964 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2965 test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) && 2966 !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) { 2967 hdev->last_rst_scheduled = jiffies; 2968 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2969 } 2970 } 2971 2972 static void hclge_errhand_task_schedule(struct hclge_dev *hdev) 2973 { 2974 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2975 !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 2976 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2977 } 2978 2979 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time) 2980 { 2981 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2982 !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 2983 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time); 2984 } 2985 2986 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status) 2987 { 2988 struct hclge_link_status_cmd *req; 2989 struct hclge_desc desc; 2990 int ret; 2991 2992 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 2993 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2994 if (ret) { 2995 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 2996 ret); 2997 return ret; 2998 } 2999 3000 req = (struct hclge_link_status_cmd *)desc.data; 3001 *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ? 3002 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 3003 3004 return 0; 3005 } 3006 3007 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status) 3008 { 3009 struct phy_device *phydev = hdev->hw.mac.phydev; 3010 3011 *link_status = HCLGE_LINK_STATUS_DOWN; 3012 3013 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) 3014 return 0; 3015 3016 if (phydev && (phydev->state != PHY_RUNNING || !phydev->link)) 3017 return 0; 3018 3019 return hclge_get_mac_link_status(hdev, link_status); 3020 } 3021 3022 static void hclge_push_link_status(struct hclge_dev *hdev) 3023 { 3024 struct hclge_vport *vport; 3025 int ret; 3026 u16 i; 3027 3028 for (i = 0; i < pci_num_vf(hdev->pdev); i++) { 3029 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 3030 3031 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) || 3032 vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO) 3033 continue; 3034 3035 ret = hclge_push_vf_link_status(vport); 3036 if (ret) { 3037 dev_err(&hdev->pdev->dev, 3038 "failed to push link status to vf%u, ret = %d\n", 3039 i, ret); 3040 } 3041 } 3042 } 3043 3044 static void hclge_update_link_status(struct hclge_dev *hdev) 3045 { 3046 struct hnae3_handle *handle = &hdev->vport[0].nic; 3047 struct hnae3_client *client = hdev->nic_client; 3048 int state; 3049 int ret; 3050 3051 if (!client) 3052 return; 3053 3054 if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state)) 3055 return; 3056 3057 ret = hclge_get_mac_phy_link(hdev, &state); 3058 if (ret) { 3059 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3060 return; 3061 } 3062 3063 if (state != hdev->hw.mac.link) { 3064 hdev->hw.mac.link = state; 3065 if (state == HCLGE_LINK_STATUS_UP) 3066 hclge_update_port_info(hdev); 3067 3068 client->ops->link_status_change(handle, state); 3069 hclge_config_mac_tnl_int(hdev, state); 3070 3071 if (test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state)) { 3072 struct hnae3_handle *rhandle = &hdev->vport[0].roce; 3073 struct hnae3_client *rclient = hdev->roce_client; 3074 3075 if (rclient && rclient->ops->link_status_change) 3076 rclient->ops->link_status_change(rhandle, 3077 state); 3078 } 3079 3080 hclge_push_link_status(hdev); 3081 } 3082 3083 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3084 } 3085 3086 static void hclge_update_speed_advertising(struct hclge_mac *mac) 3087 { 3088 u32 speed_ability; 3089 3090 if (hclge_get_speed_bit(mac->speed, &speed_ability)) 3091 return; 3092 3093 switch (mac->module_type) { 3094 case HNAE3_MODULE_TYPE_FIBRE_LR: 3095 hclge_convert_setting_lr(speed_ability, mac->advertising); 3096 break; 3097 case HNAE3_MODULE_TYPE_FIBRE_SR: 3098 case HNAE3_MODULE_TYPE_AOC: 3099 hclge_convert_setting_sr(speed_ability, mac->advertising); 3100 break; 3101 case HNAE3_MODULE_TYPE_CR: 3102 hclge_convert_setting_cr(speed_ability, mac->advertising); 3103 break; 3104 case HNAE3_MODULE_TYPE_KR: 3105 hclge_convert_setting_kr(speed_ability, mac->advertising); 3106 break; 3107 default: 3108 break; 3109 } 3110 } 3111 3112 static void hclge_update_fec_advertising(struct hclge_mac *mac) 3113 { 3114 if (mac->fec_mode & BIT(HNAE3_FEC_RS)) 3115 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 3116 mac->advertising); 3117 else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS)) 3118 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 3119 mac->advertising); 3120 else if (mac->fec_mode & BIT(HNAE3_FEC_BASER)) 3121 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 3122 mac->advertising); 3123 else 3124 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 3125 mac->advertising); 3126 } 3127 3128 static void hclge_update_pause_advertising(struct hclge_dev *hdev) 3129 { 3130 struct hclge_mac *mac = &hdev->hw.mac; 3131 bool rx_en, tx_en; 3132 3133 switch (hdev->fc_mode_last_time) { 3134 case HCLGE_FC_RX_PAUSE: 3135 rx_en = true; 3136 tx_en = false; 3137 break; 3138 case HCLGE_FC_TX_PAUSE: 3139 rx_en = false; 3140 tx_en = true; 3141 break; 3142 case HCLGE_FC_FULL: 3143 rx_en = true; 3144 tx_en = true; 3145 break; 3146 default: 3147 rx_en = false; 3148 tx_en = false; 3149 break; 3150 } 3151 3152 linkmode_set_pause(mac->advertising, tx_en, rx_en); 3153 } 3154 3155 static void hclge_update_advertising(struct hclge_dev *hdev) 3156 { 3157 struct hclge_mac *mac = &hdev->hw.mac; 3158 3159 linkmode_zero(mac->advertising); 3160 hclge_update_speed_advertising(mac); 3161 hclge_update_fec_advertising(mac); 3162 hclge_update_pause_advertising(hdev); 3163 } 3164 3165 static void hclge_update_port_capability(struct hclge_dev *hdev, 3166 struct hclge_mac *mac) 3167 { 3168 if (hnae3_dev_fec_supported(hdev)) 3169 hclge_convert_setting_fec(mac); 3170 3171 /* firmware can not identify back plane type, the media type 3172 * read from configuration can help deal it 3173 */ 3174 if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE && 3175 mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN) 3176 mac->module_type = HNAE3_MODULE_TYPE_KR; 3177 else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3178 mac->module_type = HNAE3_MODULE_TYPE_TP; 3179 3180 if (mac->support_autoneg) { 3181 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported); 3182 linkmode_copy(mac->advertising, mac->supported); 3183 } else { 3184 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3185 mac->supported); 3186 hclge_update_advertising(hdev); 3187 } 3188 } 3189 3190 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed) 3191 { 3192 struct hclge_sfp_info_cmd *resp; 3193 struct hclge_desc desc; 3194 int ret; 3195 3196 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3197 resp = (struct hclge_sfp_info_cmd *)desc.data; 3198 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3199 if (ret == -EOPNOTSUPP) { 3200 dev_warn(&hdev->pdev->dev, 3201 "IMP do not support get SFP speed %d\n", ret); 3202 return ret; 3203 } else if (ret) { 3204 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret); 3205 return ret; 3206 } 3207 3208 *speed = le32_to_cpu(resp->speed); 3209 3210 return 0; 3211 } 3212 3213 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac) 3214 { 3215 struct hclge_sfp_info_cmd *resp; 3216 struct hclge_desc desc; 3217 int ret; 3218 3219 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3220 resp = (struct hclge_sfp_info_cmd *)desc.data; 3221 3222 resp->query_type = QUERY_ACTIVE_SPEED; 3223 3224 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3225 if (ret == -EOPNOTSUPP) { 3226 dev_warn(&hdev->pdev->dev, 3227 "IMP does not support get SFP info %d\n", ret); 3228 return ret; 3229 } else if (ret) { 3230 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret); 3231 return ret; 3232 } 3233 3234 /* In some case, mac speed get from IMP may be 0, it shouldn't be 3235 * set to mac->speed. 3236 */ 3237 if (!le32_to_cpu(resp->speed)) 3238 return 0; 3239 3240 mac->speed = le32_to_cpu(resp->speed); 3241 /* if resp->speed_ability is 0, it means it's an old version 3242 * firmware, do not update these params 3243 */ 3244 if (resp->speed_ability) { 3245 mac->module_type = le32_to_cpu(resp->module_type); 3246 mac->speed_ability = le32_to_cpu(resp->speed_ability); 3247 mac->autoneg = resp->autoneg; 3248 mac->support_autoneg = resp->autoneg_ability; 3249 mac->speed_type = QUERY_ACTIVE_SPEED; 3250 mac->lane_num = resp->lane_num; 3251 if (!resp->active_fec) 3252 mac->fec_mode = 0; 3253 else 3254 mac->fec_mode = BIT(resp->active_fec); 3255 mac->fec_ability = resp->fec_ability; 3256 } else { 3257 mac->speed_type = QUERY_SFP_SPEED; 3258 } 3259 3260 return 0; 3261 } 3262 3263 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle, 3264 struct ethtool_link_ksettings *cmd) 3265 { 3266 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3267 struct hclge_vport *vport = hclge_get_vport(handle); 3268 struct hclge_phy_link_ksetting_0_cmd *req0; 3269 struct hclge_phy_link_ksetting_1_cmd *req1; 3270 u32 supported, advertising, lp_advertising; 3271 struct hclge_dev *hdev = vport->back; 3272 int ret; 3273 3274 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3275 true); 3276 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3277 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3278 true); 3279 3280 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3281 if (ret) { 3282 dev_err(&hdev->pdev->dev, 3283 "failed to get phy link ksetting, ret = %d.\n", ret); 3284 return ret; 3285 } 3286 3287 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3288 cmd->base.autoneg = req0->autoneg; 3289 cmd->base.speed = le32_to_cpu(req0->speed); 3290 cmd->base.duplex = req0->duplex; 3291 cmd->base.port = req0->port; 3292 cmd->base.transceiver = req0->transceiver; 3293 cmd->base.phy_address = req0->phy_address; 3294 cmd->base.eth_tp_mdix = req0->eth_tp_mdix; 3295 cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl; 3296 supported = le32_to_cpu(req0->supported); 3297 advertising = le32_to_cpu(req0->advertising); 3298 lp_advertising = le32_to_cpu(req0->lp_advertising); 3299 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3300 supported); 3301 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3302 advertising); 3303 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 3304 lp_advertising); 3305 3306 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3307 cmd->base.master_slave_cfg = req1->master_slave_cfg; 3308 cmd->base.master_slave_state = req1->master_slave_state; 3309 3310 return 0; 3311 } 3312 3313 static int 3314 hclge_set_phy_link_ksettings(struct hnae3_handle *handle, 3315 const struct ethtool_link_ksettings *cmd) 3316 { 3317 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3318 struct hclge_vport *vport = hclge_get_vport(handle); 3319 struct hclge_phy_link_ksetting_0_cmd *req0; 3320 struct hclge_phy_link_ksetting_1_cmd *req1; 3321 struct hclge_dev *hdev = vport->back; 3322 u32 advertising; 3323 int ret; 3324 3325 if (cmd->base.autoneg == AUTONEG_DISABLE && 3326 ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) || 3327 (cmd->base.duplex != DUPLEX_HALF && 3328 cmd->base.duplex != DUPLEX_FULL))) 3329 return -EINVAL; 3330 3331 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3332 false); 3333 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3334 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3335 false); 3336 3337 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3338 req0->autoneg = cmd->base.autoneg; 3339 req0->speed = cpu_to_le32(cmd->base.speed); 3340 req0->duplex = cmd->base.duplex; 3341 ethtool_convert_link_mode_to_legacy_u32(&advertising, 3342 cmd->link_modes.advertising); 3343 req0->advertising = cpu_to_le32(advertising); 3344 req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; 3345 3346 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3347 req1->master_slave_cfg = cmd->base.master_slave_cfg; 3348 3349 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3350 if (ret) { 3351 dev_err(&hdev->pdev->dev, 3352 "failed to set phy link ksettings, ret = %d.\n", ret); 3353 return ret; 3354 } 3355 3356 hdev->hw.mac.req_autoneg = cmd->base.autoneg; 3357 hdev->hw.mac.req_speed = cmd->base.speed; 3358 hdev->hw.mac.req_duplex = cmd->base.duplex; 3359 linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising); 3360 3361 return 0; 3362 } 3363 3364 static int hclge_update_tp_port_info(struct hclge_dev *hdev) 3365 { 3366 struct ethtool_link_ksettings cmd; 3367 int ret; 3368 3369 if (!hnae3_dev_phy_imp_supported(hdev)) 3370 return 0; 3371 3372 ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd); 3373 if (ret) 3374 return ret; 3375 3376 hdev->hw.mac.autoneg = cmd.base.autoneg; 3377 hdev->hw.mac.speed = cmd.base.speed; 3378 hdev->hw.mac.duplex = cmd.base.duplex; 3379 linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising); 3380 3381 return 0; 3382 } 3383 3384 static int hclge_tp_port_init(struct hclge_dev *hdev) 3385 { 3386 struct ethtool_link_ksettings cmd; 3387 3388 if (!hnae3_dev_phy_imp_supported(hdev)) 3389 return 0; 3390 3391 cmd.base.autoneg = hdev->hw.mac.req_autoneg; 3392 cmd.base.speed = hdev->hw.mac.req_speed; 3393 cmd.base.duplex = hdev->hw.mac.req_duplex; 3394 linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising); 3395 3396 return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd); 3397 } 3398 3399 static int hclge_update_port_info(struct hclge_dev *hdev) 3400 { 3401 struct hclge_mac *mac = &hdev->hw.mac; 3402 int speed; 3403 int ret; 3404 3405 /* get the port info from SFP cmd if not copper port */ 3406 if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3407 return hclge_update_tp_port_info(hdev); 3408 3409 /* if IMP does not support get SFP/qSFP info, return directly */ 3410 if (!hdev->support_sfp_query) 3411 return 0; 3412 3413 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3414 speed = mac->speed; 3415 ret = hclge_get_sfp_info(hdev, mac); 3416 } else { 3417 speed = HCLGE_MAC_SPEED_UNKNOWN; 3418 ret = hclge_get_sfp_speed(hdev, &speed); 3419 } 3420 3421 if (ret == -EOPNOTSUPP) { 3422 hdev->support_sfp_query = false; 3423 return ret; 3424 } else if (ret) { 3425 return ret; 3426 } 3427 3428 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3429 if (mac->speed_type == QUERY_ACTIVE_SPEED) { 3430 hclge_update_port_capability(hdev, mac); 3431 if (mac->speed != speed) 3432 (void)hclge_tm_port_shaper_cfg(hdev); 3433 return 0; 3434 } 3435 return hclge_cfg_mac_speed_dup(hdev, mac->speed, 3436 HCLGE_MAC_FULL, mac->lane_num); 3437 } else { 3438 if (speed == HCLGE_MAC_SPEED_UNKNOWN) 3439 return 0; /* do nothing if no SFP */ 3440 3441 /* must config full duplex for SFP */ 3442 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0); 3443 } 3444 } 3445 3446 static int hclge_get_status(struct hnae3_handle *handle) 3447 { 3448 struct hclge_vport *vport = hclge_get_vport(handle); 3449 struct hclge_dev *hdev = vport->back; 3450 3451 hclge_update_link_status(hdev); 3452 3453 return hdev->hw.mac.link; 3454 } 3455 3456 static struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf) 3457 { 3458 if (!pci_num_vf(hdev->pdev)) { 3459 dev_err(&hdev->pdev->dev, 3460 "SRIOV is disabled, can not get vport(%d) info.\n", vf); 3461 return NULL; 3462 } 3463 3464 if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) { 3465 dev_err(&hdev->pdev->dev, 3466 "vf id(%d) is out of range(0 <= vfid < %d)\n", 3467 vf, pci_num_vf(hdev->pdev)); 3468 return NULL; 3469 } 3470 3471 /* VF start from 1 in vport */ 3472 vf += HCLGE_VF_VPORT_START_NUM; 3473 return &hdev->vport[vf]; 3474 } 3475 3476 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf, 3477 struct ifla_vf_info *ivf) 3478 { 3479 struct hclge_vport *vport = hclge_get_vport(handle); 3480 struct hclge_dev *hdev = vport->back; 3481 3482 vport = hclge_get_vf_vport(hdev, vf); 3483 if (!vport) 3484 return -EINVAL; 3485 3486 ivf->vf = vf; 3487 ivf->linkstate = vport->vf_info.link_state; 3488 ivf->spoofchk = vport->vf_info.spoofchk; 3489 ivf->trusted = vport->vf_info.trusted; 3490 ivf->min_tx_rate = 0; 3491 ivf->max_tx_rate = vport->vf_info.max_tx_rate; 3492 ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag; 3493 ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto); 3494 ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos; 3495 ether_addr_copy(ivf->mac, vport->vf_info.mac); 3496 3497 return 0; 3498 } 3499 3500 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, 3501 int link_state) 3502 { 3503 struct hclge_vport *vport = hclge_get_vport(handle); 3504 struct hclge_dev *hdev = vport->back; 3505 int link_state_old; 3506 int ret; 3507 3508 vport = hclge_get_vf_vport(hdev, vf); 3509 if (!vport) 3510 return -EINVAL; 3511 3512 link_state_old = vport->vf_info.link_state; 3513 vport->vf_info.link_state = link_state; 3514 3515 /* return success directly if the VF is unalive, VF will 3516 * query link state itself when it starts work. 3517 */ 3518 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3519 return 0; 3520 3521 ret = hclge_push_vf_link_status(vport); 3522 if (ret) { 3523 vport->vf_info.link_state = link_state_old; 3524 dev_err(&hdev->pdev->dev, 3525 "failed to push vf%d link status, ret = %d\n", vf, ret); 3526 } 3527 3528 return ret; 3529 } 3530 3531 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 3532 { 3533 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; 3534 3535 /* fetch the events from their corresponding regs */ 3536 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 3537 msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 3538 hw_err_src_reg = hclge_read_dev(&hdev->hw, 3539 HCLGE_RAS_PF_OTHER_INT_STS_REG); 3540 3541 /* Assumption: If by any chance reset and mailbox events are reported 3542 * together then we will only process reset event in this go and will 3543 * defer the processing of the mailbox events. Since, we would have not 3544 * cleared RX CMDQ event this time we would receive again another 3545 * interrupt from H/W just for the mailbox. 3546 * 3547 * check for vector0 reset event sources 3548 */ 3549 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { 3550 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); 3551 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); 3552 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3553 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3554 hdev->rst_stats.imp_rst_cnt++; 3555 return HCLGE_VECTOR0_EVENT_RST; 3556 } 3557 3558 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { 3559 dev_info(&hdev->pdev->dev, "global reset interrupt\n"); 3560 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3561 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 3562 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3563 hdev->rst_stats.global_rst_cnt++; 3564 return HCLGE_VECTOR0_EVENT_RST; 3565 } 3566 3567 /* check for vector0 msix event and hardware error event source */ 3568 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK || 3569 hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK) 3570 return HCLGE_VECTOR0_EVENT_ERR; 3571 3572 /* check for vector0 ptp event source */ 3573 if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) { 3574 *clearval = msix_src_reg; 3575 return HCLGE_VECTOR0_EVENT_PTP; 3576 } 3577 3578 /* check for vector0 mailbox(=CMDQ RX) event source */ 3579 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 3580 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 3581 *clearval = cmdq_src_reg; 3582 return HCLGE_VECTOR0_EVENT_MBX; 3583 } 3584 3585 /* print other vector0 event source */ 3586 dev_info(&hdev->pdev->dev, 3587 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n", 3588 cmdq_src_reg, hw_err_src_reg, msix_src_reg); 3589 3590 return HCLGE_VECTOR0_EVENT_OTHER; 3591 } 3592 3593 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 3594 u32 regclr) 3595 { 3596 #define HCLGE_IMP_RESET_DELAY 5 3597 3598 switch (event_type) { 3599 case HCLGE_VECTOR0_EVENT_PTP: 3600 case HCLGE_VECTOR0_EVENT_RST: 3601 if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B)) 3602 mdelay(HCLGE_IMP_RESET_DELAY); 3603 3604 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 3605 break; 3606 case HCLGE_VECTOR0_EVENT_MBX: 3607 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 3608 break; 3609 default: 3610 break; 3611 } 3612 } 3613 3614 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 3615 { 3616 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 3617 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 3618 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 3619 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 3620 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 3621 } 3622 3623 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 3624 { 3625 writel(enable ? 1 : 0, vector->addr); 3626 } 3627 3628 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 3629 { 3630 struct hclge_dev *hdev = data; 3631 unsigned long flags; 3632 u32 clearval = 0; 3633 u32 event_cause; 3634 3635 hclge_enable_vector(&hdev->misc_vector, false); 3636 event_cause = hclge_check_event_cause(hdev, &clearval); 3637 3638 /* vector 0 interrupt is shared with reset and mailbox source events. */ 3639 switch (event_cause) { 3640 case HCLGE_VECTOR0_EVENT_ERR: 3641 hclge_errhand_task_schedule(hdev); 3642 break; 3643 case HCLGE_VECTOR0_EVENT_RST: 3644 hclge_reset_task_schedule(hdev); 3645 break; 3646 case HCLGE_VECTOR0_EVENT_PTP: 3647 spin_lock_irqsave(&hdev->ptp->lock, flags); 3648 hclge_ptp_clean_tx_hwts(hdev); 3649 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 3650 break; 3651 case HCLGE_VECTOR0_EVENT_MBX: 3652 /* If we are here then, 3653 * 1. Either we are not handling any mbx task and we are not 3654 * scheduled as well 3655 * OR 3656 * 2. We could be handling a mbx task but nothing more is 3657 * scheduled. 3658 * In both cases, we should schedule mbx task as there are more 3659 * mbx messages reported by this interrupt. 3660 */ 3661 hclge_mbx_task_schedule(hdev); 3662 break; 3663 default: 3664 dev_warn(&hdev->pdev->dev, 3665 "received unknown or unhandled event of vector0\n"); 3666 break; 3667 } 3668 3669 hclge_clear_event_cause(hdev, event_cause, clearval); 3670 3671 /* Enable interrupt if it is not caused by reset event or error event */ 3672 if (event_cause == HCLGE_VECTOR0_EVENT_PTP || 3673 event_cause == HCLGE_VECTOR0_EVENT_MBX || 3674 event_cause == HCLGE_VECTOR0_EVENT_OTHER) 3675 hclge_enable_vector(&hdev->misc_vector, true); 3676 3677 return IRQ_HANDLED; 3678 } 3679 3680 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 3681 { 3682 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 3683 dev_warn(&hdev->pdev->dev, 3684 "vector(vector_id %d) has been freed.\n", vector_id); 3685 return; 3686 } 3687 3688 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 3689 hdev->num_msi_left += 1; 3690 hdev->num_msi_used -= 1; 3691 } 3692 3693 static void hclge_get_misc_vector(struct hclge_dev *hdev) 3694 { 3695 struct hclge_misc_vector *vector = &hdev->misc_vector; 3696 3697 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 3698 3699 vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 3700 hdev->vector_status[0] = 0; 3701 3702 hdev->num_msi_left -= 1; 3703 hdev->num_msi_used += 1; 3704 } 3705 3706 static int hclge_misc_irq_init(struct hclge_dev *hdev) 3707 { 3708 int ret; 3709 3710 hclge_get_misc_vector(hdev); 3711 3712 /* this would be explicitly freed in the end */ 3713 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 3714 HCLGE_NAME, pci_name(hdev->pdev)); 3715 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 3716 0, hdev->misc_vector.name, hdev); 3717 if (ret) { 3718 hclge_free_vector(hdev, 0); 3719 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 3720 hdev->misc_vector.vector_irq); 3721 } 3722 3723 return ret; 3724 } 3725 3726 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 3727 { 3728 free_irq(hdev->misc_vector.vector_irq, hdev); 3729 hclge_free_vector(hdev, 0); 3730 } 3731 3732 int hclge_notify_client(struct hclge_dev *hdev, 3733 enum hnae3_reset_notify_type type) 3734 { 3735 struct hnae3_handle *handle = &hdev->vport[0].nic; 3736 struct hnae3_client *client = hdev->nic_client; 3737 int ret; 3738 3739 if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client) 3740 return 0; 3741 3742 if (!client->ops->reset_notify) 3743 return -EOPNOTSUPP; 3744 3745 ret = client->ops->reset_notify(handle, type); 3746 if (ret) 3747 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 3748 type, ret); 3749 3750 return ret; 3751 } 3752 3753 static int hclge_notify_roce_client(struct hclge_dev *hdev, 3754 enum hnae3_reset_notify_type type) 3755 { 3756 struct hnae3_handle *handle = &hdev->vport[0].roce; 3757 struct hnae3_client *client = hdev->roce_client; 3758 int ret; 3759 3760 if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client) 3761 return 0; 3762 3763 if (!client->ops->reset_notify) 3764 return -EOPNOTSUPP; 3765 3766 ret = client->ops->reset_notify(handle, type); 3767 if (ret) 3768 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 3769 type, ret); 3770 3771 return ret; 3772 } 3773 3774 static int hclge_reset_wait(struct hclge_dev *hdev) 3775 { 3776 #define HCLGE_RESET_WATI_MS 100 3777 #define HCLGE_RESET_WAIT_CNT 350 3778 3779 u32 val, reg, reg_bit; 3780 u32 cnt = 0; 3781 3782 switch (hdev->reset_type) { 3783 case HNAE3_IMP_RESET: 3784 reg = HCLGE_GLOBAL_RESET_REG; 3785 reg_bit = HCLGE_IMP_RESET_BIT; 3786 break; 3787 case HNAE3_GLOBAL_RESET: 3788 reg = HCLGE_GLOBAL_RESET_REG; 3789 reg_bit = HCLGE_GLOBAL_RESET_BIT; 3790 break; 3791 case HNAE3_FUNC_RESET: 3792 reg = HCLGE_FUN_RST_ING; 3793 reg_bit = HCLGE_FUN_RST_ING_B; 3794 break; 3795 default: 3796 dev_err(&hdev->pdev->dev, 3797 "Wait for unsupported reset type: %d\n", 3798 hdev->reset_type); 3799 return -EINVAL; 3800 } 3801 3802 val = hclge_read_dev(&hdev->hw, reg); 3803 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 3804 msleep(HCLGE_RESET_WATI_MS); 3805 val = hclge_read_dev(&hdev->hw, reg); 3806 cnt++; 3807 } 3808 3809 if (cnt >= HCLGE_RESET_WAIT_CNT) { 3810 dev_warn(&hdev->pdev->dev, 3811 "Wait for reset timeout: %d\n", hdev->reset_type); 3812 return -EBUSY; 3813 } 3814 3815 return 0; 3816 } 3817 3818 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset) 3819 { 3820 struct hclge_vf_rst_cmd *req; 3821 struct hclge_desc desc; 3822 3823 req = (struct hclge_vf_rst_cmd *)desc.data; 3824 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false); 3825 req->dest_vfid = func_id; 3826 3827 if (reset) 3828 req->vf_rst = 0x1; 3829 3830 return hclge_cmd_send(&hdev->hw, &desc, 1); 3831 } 3832 3833 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset) 3834 { 3835 int i; 3836 3837 for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) { 3838 struct hclge_vport *vport = &hdev->vport[i]; 3839 int ret; 3840 3841 /* Send cmd to set/clear VF's FUNC_RST_ING */ 3842 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset); 3843 if (ret) { 3844 dev_err(&hdev->pdev->dev, 3845 "set vf(%u) rst failed %d!\n", 3846 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3847 ret); 3848 return ret; 3849 } 3850 3851 if (!reset || 3852 !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state)) 3853 continue; 3854 3855 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) && 3856 hdev->reset_type == HNAE3_FUNC_RESET) { 3857 set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET, 3858 &vport->need_notify); 3859 continue; 3860 } 3861 3862 /* Inform VF to process the reset. 3863 * hclge_inform_reset_assert_to_vf may fail if VF 3864 * driver is not loaded. 3865 */ 3866 ret = hclge_inform_reset_assert_to_vf(vport); 3867 if (ret) 3868 dev_warn(&hdev->pdev->dev, 3869 "inform reset to vf(%u) failed %d!\n", 3870 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3871 ret); 3872 } 3873 3874 return 0; 3875 } 3876 3877 static void hclge_mailbox_service_task(struct hclge_dev *hdev) 3878 { 3879 if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) || 3880 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) || 3881 test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 3882 return; 3883 3884 if (time_is_before_jiffies(hdev->last_mbx_scheduled + 3885 HCLGE_MBX_SCHED_TIMEOUT)) 3886 dev_warn(&hdev->pdev->dev, 3887 "mbx service task is scheduled after %ums on cpu%u!\n", 3888 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled), 3889 smp_processor_id()); 3890 3891 hclge_mbx_handler(hdev); 3892 3893 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 3894 } 3895 3896 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev) 3897 { 3898 struct hclge_pf_rst_sync_cmd *req; 3899 struct hclge_desc desc; 3900 int cnt = 0; 3901 int ret; 3902 3903 req = (struct hclge_pf_rst_sync_cmd *)desc.data; 3904 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true); 3905 3906 do { 3907 /* vf need to down netdev by mbx during PF or FLR reset */ 3908 hclge_mailbox_service_task(hdev); 3909 3910 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3911 /* for compatible with old firmware, wait 3912 * 100 ms for VF to stop IO 3913 */ 3914 if (ret == -EOPNOTSUPP) { 3915 msleep(HCLGE_RESET_SYNC_TIME); 3916 return; 3917 } else if (ret) { 3918 dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n", 3919 ret); 3920 return; 3921 } else if (req->all_vf_ready) { 3922 return; 3923 } 3924 msleep(HCLGE_PF_RESET_SYNC_TIME); 3925 hclge_comm_cmd_reuse_desc(&desc, true); 3926 } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT); 3927 3928 dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n"); 3929 } 3930 3931 void hclge_report_hw_error(struct hclge_dev *hdev, 3932 enum hnae3_hw_error_type type) 3933 { 3934 struct hnae3_client *client = hdev->nic_client; 3935 3936 if (!client || !client->ops->process_hw_error || 3937 !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) 3938 return; 3939 3940 client->ops->process_hw_error(&hdev->vport[0].nic, type); 3941 } 3942 3943 static void hclge_handle_imp_error(struct hclge_dev *hdev) 3944 { 3945 u32 reg_val; 3946 3947 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 3948 if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { 3949 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); 3950 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); 3951 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 3952 } 3953 3954 if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { 3955 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); 3956 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); 3957 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 3958 } 3959 } 3960 3961 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 3962 { 3963 struct hclge_desc desc; 3964 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 3965 int ret; 3966 3967 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 3968 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 3969 req->fun_reset_vfid = func_id; 3970 3971 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3972 if (ret) 3973 dev_err(&hdev->pdev->dev, 3974 "send function reset cmd fail, status =%d\n", ret); 3975 3976 return ret; 3977 } 3978 3979 static void hclge_do_reset(struct hclge_dev *hdev) 3980 { 3981 struct hnae3_handle *handle = &hdev->vport[0].nic; 3982 struct pci_dev *pdev = hdev->pdev; 3983 u32 val; 3984 3985 if (hclge_get_hw_reset_stat(handle)) { 3986 dev_info(&pdev->dev, "hardware reset not finish\n"); 3987 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n", 3988 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING), 3989 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 3990 return; 3991 } 3992 3993 switch (hdev->reset_type) { 3994 case HNAE3_IMP_RESET: 3995 dev_info(&pdev->dev, "IMP reset requested\n"); 3996 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 3997 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1); 3998 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val); 3999 break; 4000 case HNAE3_GLOBAL_RESET: 4001 dev_info(&pdev->dev, "global reset requested\n"); 4002 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 4003 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 4004 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 4005 break; 4006 case HNAE3_FUNC_RESET: 4007 dev_info(&pdev->dev, "PF reset requested\n"); 4008 /* schedule again to check later */ 4009 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); 4010 hclge_reset_task_schedule(hdev); 4011 break; 4012 default: 4013 dev_warn(&pdev->dev, 4014 "unsupported reset type: %d\n", hdev->reset_type); 4015 break; 4016 } 4017 } 4018 4019 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 4020 unsigned long *addr) 4021 { 4022 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 4023 struct hclge_dev *hdev = ae_dev->priv; 4024 4025 /* return the highest priority reset level amongst all */ 4026 if (test_bit(HNAE3_IMP_RESET, addr)) { 4027 rst_level = HNAE3_IMP_RESET; 4028 clear_bit(HNAE3_IMP_RESET, addr); 4029 clear_bit(HNAE3_GLOBAL_RESET, addr); 4030 clear_bit(HNAE3_FUNC_RESET, addr); 4031 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) { 4032 rst_level = HNAE3_GLOBAL_RESET; 4033 clear_bit(HNAE3_GLOBAL_RESET, addr); 4034 clear_bit(HNAE3_FUNC_RESET, addr); 4035 } else if (test_bit(HNAE3_FUNC_RESET, addr)) { 4036 rst_level = HNAE3_FUNC_RESET; 4037 clear_bit(HNAE3_FUNC_RESET, addr); 4038 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 4039 rst_level = HNAE3_FLR_RESET; 4040 clear_bit(HNAE3_FLR_RESET, addr); 4041 } 4042 4043 if (hdev->reset_type != HNAE3_NONE_RESET && 4044 rst_level < hdev->reset_type) 4045 return HNAE3_NONE_RESET; 4046 4047 return rst_level; 4048 } 4049 4050 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 4051 { 4052 u32 clearval = 0; 4053 4054 switch (hdev->reset_type) { 4055 case HNAE3_IMP_RESET: 4056 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 4057 break; 4058 case HNAE3_GLOBAL_RESET: 4059 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 4060 break; 4061 default: 4062 break; 4063 } 4064 4065 if (!clearval) 4066 return; 4067 4068 /* For revision 0x20, the reset interrupt source 4069 * can only be cleared after hardware reset done 4070 */ 4071 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 4072 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, 4073 clearval); 4074 4075 hclge_enable_vector(&hdev->misc_vector, true); 4076 } 4077 4078 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable) 4079 { 4080 u32 reg_val; 4081 4082 reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 4083 if (enable) 4084 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY; 4085 else 4086 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY; 4087 4088 hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val); 4089 } 4090 4091 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev) 4092 { 4093 int ret; 4094 4095 ret = hclge_set_all_vf_rst(hdev, true); 4096 if (ret) 4097 return ret; 4098 4099 hclge_func_reset_sync_vf(hdev); 4100 4101 return 0; 4102 } 4103 4104 static int hclge_reset_prepare_wait(struct hclge_dev *hdev) 4105 { 4106 u32 reg_val; 4107 int ret = 0; 4108 4109 switch (hdev->reset_type) { 4110 case HNAE3_FUNC_RESET: 4111 ret = hclge_func_reset_notify_vf(hdev); 4112 if (ret) 4113 return ret; 4114 4115 ret = hclge_func_reset_cmd(hdev, 0); 4116 if (ret) { 4117 dev_err(&hdev->pdev->dev, 4118 "asserting function reset fail %d!\n", ret); 4119 return ret; 4120 } 4121 4122 /* After performaning pf reset, it is not necessary to do the 4123 * mailbox handling or send any command to firmware, because 4124 * any mailbox handling or command to firmware is only valid 4125 * after hclge_comm_cmd_init is called. 4126 */ 4127 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 4128 hdev->rst_stats.pf_rst_cnt++; 4129 break; 4130 case HNAE3_FLR_RESET: 4131 ret = hclge_func_reset_notify_vf(hdev); 4132 if (ret) 4133 return ret; 4134 break; 4135 case HNAE3_IMP_RESET: 4136 hclge_handle_imp_error(hdev); 4137 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4138 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, 4139 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); 4140 break; 4141 default: 4142 break; 4143 } 4144 4145 /* inform hardware that preparatory work is done */ 4146 msleep(HCLGE_RESET_SYNC_TIME); 4147 hclge_reset_handshake(hdev, true); 4148 dev_info(&hdev->pdev->dev, "prepare wait ok\n"); 4149 4150 return ret; 4151 } 4152 4153 static void hclge_show_rst_info(struct hclge_dev *hdev) 4154 { 4155 char *buf; 4156 4157 buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL); 4158 if (!buf) 4159 return; 4160 4161 hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN); 4162 4163 dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf); 4164 4165 kfree(buf); 4166 } 4167 4168 static bool hclge_reset_err_handle(struct hclge_dev *hdev) 4169 { 4170 #define MAX_RESET_FAIL_CNT 5 4171 4172 if (hdev->reset_pending) { 4173 dev_info(&hdev->pdev->dev, "Reset pending %lu\n", 4174 hdev->reset_pending); 4175 return true; 4176 } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) & 4177 HCLGE_RESET_INT_M) { 4178 dev_info(&hdev->pdev->dev, 4179 "reset failed because new reset interrupt\n"); 4180 hclge_clear_reset_cause(hdev); 4181 return false; 4182 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { 4183 hdev->rst_stats.reset_fail_cnt++; 4184 set_bit(hdev->reset_type, &hdev->reset_pending); 4185 dev_info(&hdev->pdev->dev, 4186 "re-schedule reset task(%u)\n", 4187 hdev->rst_stats.reset_fail_cnt); 4188 return true; 4189 } 4190 4191 hclge_clear_reset_cause(hdev); 4192 4193 /* recover the handshake status when reset fail */ 4194 hclge_reset_handshake(hdev, true); 4195 4196 dev_err(&hdev->pdev->dev, "Reset fail!\n"); 4197 4198 hclge_show_rst_info(hdev); 4199 4200 set_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4201 4202 return false; 4203 } 4204 4205 static void hclge_update_reset_level(struct hclge_dev *hdev) 4206 { 4207 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4208 enum hnae3_reset_type reset_level; 4209 4210 /* reset request will not be set during reset, so clear 4211 * pending reset request to avoid unnecessary reset 4212 * caused by the same reason. 4213 */ 4214 hclge_get_reset_level(ae_dev, &hdev->reset_request); 4215 4216 /* if default_reset_request has a higher level reset request, 4217 * it should be handled as soon as possible. since some errors 4218 * need this kind of reset to fix. 4219 */ 4220 reset_level = hclge_get_reset_level(ae_dev, 4221 &hdev->default_reset_request); 4222 if (reset_level != HNAE3_NONE_RESET) 4223 set_bit(reset_level, &hdev->reset_request); 4224 } 4225 4226 static int hclge_set_rst_done(struct hclge_dev *hdev) 4227 { 4228 struct hclge_pf_rst_done_cmd *req; 4229 struct hclge_desc desc; 4230 int ret; 4231 4232 req = (struct hclge_pf_rst_done_cmd *)desc.data; 4233 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false); 4234 req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT; 4235 4236 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4237 /* To be compatible with the old firmware, which does not support 4238 * command HCLGE_OPC_PF_RST_DONE, just print a warning and 4239 * return success 4240 */ 4241 if (ret == -EOPNOTSUPP) { 4242 dev_warn(&hdev->pdev->dev, 4243 "current firmware does not support command(0x%x)!\n", 4244 HCLGE_OPC_PF_RST_DONE); 4245 return 0; 4246 } else if (ret) { 4247 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n", 4248 ret); 4249 } 4250 4251 return ret; 4252 } 4253 4254 static int hclge_reset_prepare_up(struct hclge_dev *hdev) 4255 { 4256 int ret = 0; 4257 4258 switch (hdev->reset_type) { 4259 case HNAE3_FUNC_RESET: 4260 case HNAE3_FLR_RESET: 4261 ret = hclge_set_all_vf_rst(hdev, false); 4262 break; 4263 case HNAE3_GLOBAL_RESET: 4264 case HNAE3_IMP_RESET: 4265 ret = hclge_set_rst_done(hdev); 4266 break; 4267 default: 4268 break; 4269 } 4270 4271 /* clear up the handshake status after re-initialize done */ 4272 hclge_reset_handshake(hdev, false); 4273 4274 return ret; 4275 } 4276 4277 static int hclge_reset_stack(struct hclge_dev *hdev) 4278 { 4279 int ret; 4280 4281 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 4282 if (ret) 4283 return ret; 4284 4285 ret = hclge_reset_ae_dev(hdev->ae_dev); 4286 if (ret) 4287 return ret; 4288 4289 return hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 4290 } 4291 4292 static int hclge_reset_prepare(struct hclge_dev *hdev) 4293 { 4294 int ret; 4295 4296 hdev->rst_stats.reset_cnt++; 4297 /* perform reset of the stack & ae device for a client */ 4298 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 4299 if (ret) 4300 return ret; 4301 4302 rtnl_lock(); 4303 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 4304 rtnl_unlock(); 4305 if (ret) 4306 return ret; 4307 4308 return hclge_reset_prepare_wait(hdev); 4309 } 4310 4311 static int hclge_reset_rebuild(struct hclge_dev *hdev) 4312 { 4313 int ret; 4314 4315 hdev->rst_stats.hw_reset_done_cnt++; 4316 4317 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 4318 if (ret) 4319 return ret; 4320 4321 rtnl_lock(); 4322 ret = hclge_reset_stack(hdev); 4323 rtnl_unlock(); 4324 if (ret) 4325 return ret; 4326 4327 hclge_clear_reset_cause(hdev); 4328 4329 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 4330 /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1 4331 * times 4332 */ 4333 if (ret && 4334 hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1) 4335 return ret; 4336 4337 ret = hclge_reset_prepare_up(hdev); 4338 if (ret) 4339 return ret; 4340 4341 rtnl_lock(); 4342 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT); 4343 rtnl_unlock(); 4344 if (ret) 4345 return ret; 4346 4347 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT); 4348 if (ret) 4349 return ret; 4350 4351 hdev->last_reset_time = jiffies; 4352 hdev->rst_stats.reset_fail_cnt = 0; 4353 hdev->rst_stats.reset_done_cnt++; 4354 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4355 4356 hclge_update_reset_level(hdev); 4357 4358 return 0; 4359 } 4360 4361 static void hclge_reset(struct hclge_dev *hdev) 4362 { 4363 if (hclge_reset_prepare(hdev)) 4364 goto err_reset; 4365 4366 if (hclge_reset_wait(hdev)) 4367 goto err_reset; 4368 4369 if (hclge_reset_rebuild(hdev)) 4370 goto err_reset; 4371 4372 return; 4373 4374 err_reset: 4375 if (hclge_reset_err_handle(hdev)) 4376 hclge_reset_task_schedule(hdev); 4377 } 4378 4379 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) 4380 { 4381 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4382 struct hclge_dev *hdev = ae_dev->priv; 4383 4384 /* We might end up getting called broadly because of 2 below cases: 4385 * 1. Recoverable error was conveyed through APEI and only way to bring 4386 * normalcy is to reset. 4387 * 2. A new reset request from the stack due to timeout 4388 * 4389 * check if this is a new reset request and we are not here just because 4390 * last reset attempt did not succeed and watchdog hit us again. We will 4391 * know this if last reset request did not occur very recently (watchdog 4392 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 4393 * In case of new request we reset the "reset level" to PF reset. 4394 * And if it is a repeat reset request of the most recent one then we 4395 * want to make sure we throttle the reset request. Therefore, we will 4396 * not allow it again before 3*HZ times. 4397 */ 4398 4399 if (time_before(jiffies, (hdev->last_reset_time + 4400 HCLGE_RESET_INTERVAL))) { 4401 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 4402 return; 4403 } 4404 4405 if (hdev->default_reset_request) { 4406 hdev->reset_level = 4407 hclge_get_reset_level(ae_dev, 4408 &hdev->default_reset_request); 4409 } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) { 4410 hdev->reset_level = HNAE3_FUNC_RESET; 4411 } 4412 4413 dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n", 4414 hdev->reset_level); 4415 4416 /* request reset & schedule reset task */ 4417 set_bit(hdev->reset_level, &hdev->reset_request); 4418 hclge_reset_task_schedule(hdev); 4419 4420 if (hdev->reset_level < HNAE3_GLOBAL_RESET) 4421 hdev->reset_level++; 4422 } 4423 4424 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 4425 enum hnae3_reset_type rst_type) 4426 { 4427 struct hclge_dev *hdev = ae_dev->priv; 4428 4429 set_bit(rst_type, &hdev->default_reset_request); 4430 } 4431 4432 static void hclge_reset_timer(struct timer_list *t) 4433 { 4434 struct hclge_dev *hdev = from_timer(hdev, t, reset_timer); 4435 4436 /* if default_reset_request has no value, it means that this reset 4437 * request has already be handled, so just return here 4438 */ 4439 if (!hdev->default_reset_request) 4440 return; 4441 4442 dev_info(&hdev->pdev->dev, 4443 "triggering reset in reset timer\n"); 4444 hclge_reset_event(hdev->pdev, NULL); 4445 } 4446 4447 static void hclge_reset_subtask(struct hclge_dev *hdev) 4448 { 4449 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4450 4451 /* check if there is any ongoing reset in the hardware. This status can 4452 * be checked from reset_pending. If there is then, we need to wait for 4453 * hardware to complete reset. 4454 * a. If we are able to figure out in reasonable time that hardware 4455 * has fully resetted then, we can proceed with driver, client 4456 * reset. 4457 * b. else, we can come back later to check this status so re-sched 4458 * now. 4459 */ 4460 hdev->last_reset_time = jiffies; 4461 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending); 4462 if (hdev->reset_type != HNAE3_NONE_RESET) 4463 hclge_reset(hdev); 4464 4465 /* check if we got any *new* reset requests to be honored */ 4466 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request); 4467 if (hdev->reset_type != HNAE3_NONE_RESET) 4468 hclge_do_reset(hdev); 4469 4470 hdev->reset_type = HNAE3_NONE_RESET; 4471 } 4472 4473 static void hclge_handle_err_reset_request(struct hclge_dev *hdev) 4474 { 4475 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4476 enum hnae3_reset_type reset_type; 4477 4478 if (ae_dev->hw_err_reset_req) { 4479 reset_type = hclge_get_reset_level(ae_dev, 4480 &ae_dev->hw_err_reset_req); 4481 hclge_set_def_reset_request(ae_dev, reset_type); 4482 } 4483 4484 if (hdev->default_reset_request && ae_dev->ops->reset_event) 4485 ae_dev->ops->reset_event(hdev->pdev, NULL); 4486 4487 /* enable interrupt after error handling complete */ 4488 hclge_enable_vector(&hdev->misc_vector, true); 4489 } 4490 4491 static void hclge_handle_err_recovery(struct hclge_dev *hdev) 4492 { 4493 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4494 4495 ae_dev->hw_err_reset_req = 0; 4496 4497 if (hclge_find_error_source(hdev)) { 4498 hclge_handle_error_info_log(ae_dev); 4499 hclge_handle_mac_tnl(hdev); 4500 } 4501 4502 hclge_handle_err_reset_request(hdev); 4503 } 4504 4505 static void hclge_misc_err_recovery(struct hclge_dev *hdev) 4506 { 4507 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4508 struct device *dev = &hdev->pdev->dev; 4509 u32 msix_sts_reg; 4510 4511 msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 4512 if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) { 4513 if (hclge_handle_hw_msix_error 4514 (hdev, &hdev->default_reset_request)) 4515 dev_info(dev, "received msix interrupt 0x%x\n", 4516 msix_sts_reg); 4517 } 4518 4519 hclge_handle_hw_ras_error(ae_dev); 4520 4521 hclge_handle_err_reset_request(hdev); 4522 } 4523 4524 static void hclge_errhand_service_task(struct hclge_dev *hdev) 4525 { 4526 if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 4527 return; 4528 4529 if (hnae3_dev_ras_imp_supported(hdev)) 4530 hclge_handle_err_recovery(hdev); 4531 else 4532 hclge_misc_err_recovery(hdev); 4533 } 4534 4535 static void hclge_reset_service_task(struct hclge_dev *hdev) 4536 { 4537 if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 4538 return; 4539 4540 if (time_is_before_jiffies(hdev->last_rst_scheduled + 4541 HCLGE_RESET_SCHED_TIMEOUT)) 4542 dev_warn(&hdev->pdev->dev, 4543 "reset service task is scheduled after %ums on cpu%u!\n", 4544 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled), 4545 smp_processor_id()); 4546 4547 down(&hdev->reset_sem); 4548 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4549 4550 hclge_reset_subtask(hdev); 4551 4552 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4553 up(&hdev->reset_sem); 4554 } 4555 4556 static void hclge_update_vport_alive(struct hclge_dev *hdev) 4557 { 4558 #define HCLGE_ALIVE_SECONDS_NORMAL 8 4559 4560 unsigned long alive_time = HCLGE_ALIVE_SECONDS_NORMAL * HZ; 4561 int i; 4562 4563 /* start from vport 1 for PF is always alive */ 4564 for (i = 1; i < hdev->num_alloc_vport; i++) { 4565 struct hclge_vport *vport = &hdev->vport[i]; 4566 4567 if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) || 4568 !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 4569 continue; 4570 if (time_after(jiffies, vport->last_active_jiffies + 4571 alive_time)) { 4572 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 4573 dev_warn(&hdev->pdev->dev, 4574 "VF %u heartbeat timeout\n", 4575 i - HCLGE_VF_VPORT_START_NUM); 4576 } 4577 } 4578 } 4579 4580 static void hclge_periodic_service_task(struct hclge_dev *hdev) 4581 { 4582 unsigned long delta = round_jiffies_relative(HZ); 4583 4584 if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 4585 return; 4586 4587 /* Always handle the link updating to make sure link state is 4588 * updated when it is triggered by mbx. 4589 */ 4590 hclge_update_link_status(hdev); 4591 hclge_sync_mac_table(hdev); 4592 hclge_sync_promisc_mode(hdev); 4593 hclge_sync_fd_table(hdev); 4594 4595 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 4596 delta = jiffies - hdev->last_serv_processed; 4597 4598 if (delta < round_jiffies_relative(HZ)) { 4599 delta = round_jiffies_relative(HZ) - delta; 4600 goto out; 4601 } 4602 } 4603 4604 hdev->serv_processed_cnt++; 4605 hclge_update_vport_alive(hdev); 4606 4607 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) { 4608 hdev->last_serv_processed = jiffies; 4609 goto out; 4610 } 4611 4612 if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL)) 4613 hclge_update_stats_for_all(hdev); 4614 4615 hclge_update_port_info(hdev); 4616 hclge_sync_vlan_filter(hdev); 4617 4618 if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL)) 4619 hclge_rfs_filter_expire(hdev); 4620 4621 hdev->last_serv_processed = jiffies; 4622 4623 out: 4624 hclge_task_schedule(hdev, delta); 4625 } 4626 4627 static void hclge_ptp_service_task(struct hclge_dev *hdev) 4628 { 4629 unsigned long flags; 4630 4631 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) || 4632 !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) || 4633 !time_is_before_jiffies(hdev->ptp->tx_start + HZ)) 4634 return; 4635 4636 /* to prevent concurrence with the irq handler */ 4637 spin_lock_irqsave(&hdev->ptp->lock, flags); 4638 4639 /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq 4640 * handler may handle it just before spin_lock_irqsave(). 4641 */ 4642 if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) 4643 hclge_ptp_clean_tx_hwts(hdev); 4644 4645 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 4646 } 4647 4648 static void hclge_service_task(struct work_struct *work) 4649 { 4650 struct hclge_dev *hdev = 4651 container_of(work, struct hclge_dev, service_task.work); 4652 4653 hclge_errhand_service_task(hdev); 4654 hclge_reset_service_task(hdev); 4655 hclge_ptp_service_task(hdev); 4656 hclge_mailbox_service_task(hdev); 4657 hclge_periodic_service_task(hdev); 4658 4659 /* Handle error recovery, reset and mbx again in case periodical task 4660 * delays the handling by calling hclge_task_schedule() in 4661 * hclge_periodic_service_task(). 4662 */ 4663 hclge_errhand_service_task(hdev); 4664 hclge_reset_service_task(hdev); 4665 hclge_mailbox_service_task(hdev); 4666 } 4667 4668 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 4669 { 4670 /* VF handle has no client */ 4671 if (!handle->client) 4672 return container_of(handle, struct hclge_vport, nic); 4673 else if (handle->client->type == HNAE3_CLIENT_ROCE) 4674 return container_of(handle, struct hclge_vport, roce); 4675 else 4676 return container_of(handle, struct hclge_vport, nic); 4677 } 4678 4679 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx, 4680 struct hnae3_vector_info *vector_info) 4681 { 4682 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 64 4683 4684 vector_info->vector = pci_irq_vector(hdev->pdev, idx); 4685 4686 /* need an extend offset to config vector >= 64 */ 4687 if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2) 4688 vector_info->io_addr = hdev->hw.hw.io_base + 4689 HCLGE_VECTOR_REG_BASE + 4690 (idx - 1) * HCLGE_VECTOR_REG_OFFSET; 4691 else 4692 vector_info->io_addr = hdev->hw.hw.io_base + 4693 HCLGE_VECTOR_EXT_REG_BASE + 4694 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4695 HCLGE_VECTOR_REG_OFFSET_H + 4696 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4697 HCLGE_VECTOR_REG_OFFSET; 4698 4699 hdev->vector_status[idx] = hdev->vport[0].vport_id; 4700 hdev->vector_irq[idx] = vector_info->vector; 4701 } 4702 4703 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 4704 struct hnae3_vector_info *vector_info) 4705 { 4706 struct hclge_vport *vport = hclge_get_vport(handle); 4707 struct hnae3_vector_info *vector = vector_info; 4708 struct hclge_dev *hdev = vport->back; 4709 int alloc = 0; 4710 u16 i = 0; 4711 u16 j; 4712 4713 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num); 4714 vector_num = min(hdev->num_msi_left, vector_num); 4715 4716 for (j = 0; j < vector_num; j++) { 4717 while (++i < hdev->num_nic_msi) { 4718 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 4719 hclge_get_vector_info(hdev, i, vector); 4720 vector++; 4721 alloc++; 4722 4723 break; 4724 } 4725 } 4726 } 4727 hdev->num_msi_left -= alloc; 4728 hdev->num_msi_used += alloc; 4729 4730 return alloc; 4731 } 4732 4733 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 4734 { 4735 int i; 4736 4737 for (i = 0; i < hdev->num_msi; i++) 4738 if (vector == hdev->vector_irq[i]) 4739 return i; 4740 4741 return -EINVAL; 4742 } 4743 4744 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 4745 { 4746 struct hclge_vport *vport = hclge_get_vport(handle); 4747 struct hclge_dev *hdev = vport->back; 4748 int vector_id; 4749 4750 vector_id = hclge_get_vector_index(hdev, vector); 4751 if (vector_id < 0) { 4752 dev_err(&hdev->pdev->dev, 4753 "Get vector index fail. vector = %d\n", vector); 4754 return vector_id; 4755 } 4756 4757 hclge_free_vector(hdev, vector_id); 4758 4759 return 0; 4760 } 4761 4762 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 4763 u8 *key, u8 *hfunc) 4764 { 4765 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4766 struct hclge_vport *vport = hclge_get_vport(handle); 4767 struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg; 4768 4769 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 4770 4771 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 4772 ae_dev->dev_specs.rss_ind_tbl_size); 4773 4774 return 0; 4775 } 4776 4777 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 4778 const u8 *key, const u8 hfunc) 4779 { 4780 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4781 struct hclge_vport *vport = hclge_get_vport(handle); 4782 struct hclge_dev *hdev = vport->back; 4783 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 4784 int ret, i; 4785 4786 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc); 4787 if (ret) { 4788 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc); 4789 return ret; 4790 } 4791 4792 /* Update the shadow RSS table with user specified qids */ 4793 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 4794 rss_cfg->rss_indirection_tbl[i] = indir[i]; 4795 4796 /* Update the hardware */ 4797 return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw, 4798 rss_cfg->rss_indirection_tbl); 4799 } 4800 4801 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 4802 struct ethtool_rxnfc *nfc) 4803 { 4804 struct hclge_vport *vport = hclge_get_vport(handle); 4805 struct hclge_dev *hdev = vport->back; 4806 int ret; 4807 4808 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 4809 &hdev->rss_cfg, nfc); 4810 if (ret) { 4811 dev_err(&hdev->pdev->dev, 4812 "failed to set rss tuple, ret = %d.\n", ret); 4813 return ret; 4814 } 4815 4816 return 0; 4817 } 4818 4819 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 4820 struct ethtool_rxnfc *nfc) 4821 { 4822 struct hclge_vport *vport = hclge_get_vport(handle); 4823 u8 tuple_sets; 4824 int ret; 4825 4826 nfc->data = 0; 4827 4828 ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type, 4829 &tuple_sets); 4830 if (ret || !tuple_sets) 4831 return ret; 4832 4833 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 4834 4835 return 0; 4836 } 4837 4838 static int hclge_get_tc_size(struct hnae3_handle *handle) 4839 { 4840 struct hclge_vport *vport = hclge_get_vport(handle); 4841 struct hclge_dev *hdev = vport->back; 4842 4843 return hdev->pf_rss_size_max; 4844 } 4845 4846 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev) 4847 { 4848 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 4849 struct hclge_vport *vport = hdev->vport; 4850 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 4851 u16 tc_valid[HCLGE_MAX_TC_NUM] = {0}; 4852 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 4853 struct hnae3_tc_info *tc_info; 4854 u16 roundup_size; 4855 u16 rss_size; 4856 int i; 4857 4858 tc_info = &vport->nic.kinfo.tc_info; 4859 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 4860 rss_size = tc_info->tqp_count[i]; 4861 tc_valid[i] = 0; 4862 4863 if (!(hdev->hw_tc_map & BIT(i))) 4864 continue; 4865 4866 /* tc_size set to hardware is the log2 of roundup power of two 4867 * of rss_size, the acutal queue size is limited by indirection 4868 * table. 4869 */ 4870 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size || 4871 rss_size == 0) { 4872 dev_err(&hdev->pdev->dev, 4873 "Configure rss tc size failed, invalid TC_SIZE = %u\n", 4874 rss_size); 4875 return -EINVAL; 4876 } 4877 4878 roundup_size = roundup_pow_of_two(rss_size); 4879 roundup_size = ilog2(roundup_size); 4880 4881 tc_valid[i] = 1; 4882 tc_size[i] = roundup_size; 4883 tc_offset[i] = tc_info->tqp_offset[i]; 4884 } 4885 4886 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 4887 tc_size); 4888 } 4889 4890 int hclge_rss_init_hw(struct hclge_dev *hdev) 4891 { 4892 u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl; 4893 u8 *key = hdev->rss_cfg.rss_hash_key; 4894 u8 hfunc = hdev->rss_cfg.rss_algo; 4895 int ret; 4896 4897 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 4898 rss_indir); 4899 if (ret) 4900 return ret; 4901 4902 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key); 4903 if (ret) 4904 return ret; 4905 4906 ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, &hdev->rss_cfg); 4907 if (ret) 4908 return ret; 4909 4910 return hclge_init_rss_tc_mode(hdev); 4911 } 4912 4913 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 4914 int vector_id, bool en, 4915 struct hnae3_ring_chain_node *ring_chain) 4916 { 4917 struct hclge_dev *hdev = vport->back; 4918 struct hnae3_ring_chain_node *node; 4919 struct hclge_desc desc; 4920 struct hclge_ctrl_vector_chain_cmd *req = 4921 (struct hclge_ctrl_vector_chain_cmd *)desc.data; 4922 enum hclge_comm_cmd_status status; 4923 enum hclge_opcode_type op; 4924 u16 tqp_type_and_id; 4925 int i; 4926 4927 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 4928 hclge_cmd_setup_basic_desc(&desc, op, false); 4929 req->int_vector_id_l = hnae3_get_field(vector_id, 4930 HCLGE_VECTOR_ID_L_M, 4931 HCLGE_VECTOR_ID_L_S); 4932 req->int_vector_id_h = hnae3_get_field(vector_id, 4933 HCLGE_VECTOR_ID_H_M, 4934 HCLGE_VECTOR_ID_H_S); 4935 4936 i = 0; 4937 for (node = ring_chain; node; node = node->next) { 4938 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 4939 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 4940 HCLGE_INT_TYPE_S, 4941 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 4942 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 4943 HCLGE_TQP_ID_S, node->tqp_index); 4944 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 4945 HCLGE_INT_GL_IDX_S, 4946 hnae3_get_field(node->int_gl_idx, 4947 HNAE3_RING_GL_IDX_M, 4948 HNAE3_RING_GL_IDX_S)); 4949 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 4950 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 4951 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 4952 req->vfid = vport->vport_id; 4953 4954 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4955 if (status) { 4956 dev_err(&hdev->pdev->dev, 4957 "Map TQP fail, status is %d.\n", 4958 status); 4959 return -EIO; 4960 } 4961 i = 0; 4962 4963 hclge_cmd_setup_basic_desc(&desc, 4964 op, 4965 false); 4966 req->int_vector_id_l = 4967 hnae3_get_field(vector_id, 4968 HCLGE_VECTOR_ID_L_M, 4969 HCLGE_VECTOR_ID_L_S); 4970 req->int_vector_id_h = 4971 hnae3_get_field(vector_id, 4972 HCLGE_VECTOR_ID_H_M, 4973 HCLGE_VECTOR_ID_H_S); 4974 } 4975 } 4976 4977 if (i > 0) { 4978 req->int_cause_num = i; 4979 req->vfid = vport->vport_id; 4980 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4981 if (status) { 4982 dev_err(&hdev->pdev->dev, 4983 "Map TQP fail, status is %d.\n", status); 4984 return -EIO; 4985 } 4986 } 4987 4988 return 0; 4989 } 4990 4991 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector, 4992 struct hnae3_ring_chain_node *ring_chain) 4993 { 4994 struct hclge_vport *vport = hclge_get_vport(handle); 4995 struct hclge_dev *hdev = vport->back; 4996 int vector_id; 4997 4998 vector_id = hclge_get_vector_index(hdev, vector); 4999 if (vector_id < 0) { 5000 dev_err(&hdev->pdev->dev, 5001 "failed to get vector index. vector=%d\n", vector); 5002 return vector_id; 5003 } 5004 5005 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 5006 } 5007 5008 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector, 5009 struct hnae3_ring_chain_node *ring_chain) 5010 { 5011 struct hclge_vport *vport = hclge_get_vport(handle); 5012 struct hclge_dev *hdev = vport->back; 5013 int vector_id, ret; 5014 5015 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 5016 return 0; 5017 5018 vector_id = hclge_get_vector_index(hdev, vector); 5019 if (vector_id < 0) { 5020 dev_err(&handle->pdev->dev, 5021 "Get vector index fail. ret =%d\n", vector_id); 5022 return vector_id; 5023 } 5024 5025 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 5026 if (ret) 5027 dev_err(&handle->pdev->dev, 5028 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 5029 vector_id, ret); 5030 5031 return ret; 5032 } 5033 5034 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id, 5035 bool en_uc, bool en_mc, bool en_bc) 5036 { 5037 struct hclge_vport *vport = &hdev->vport[vf_id]; 5038 struct hnae3_handle *handle = &vport->nic; 5039 struct hclge_promisc_cfg_cmd *req; 5040 struct hclge_desc desc; 5041 bool uc_tx_en = en_uc; 5042 u8 promisc_cfg = 0; 5043 int ret; 5044 5045 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 5046 5047 req = (struct hclge_promisc_cfg_cmd *)desc.data; 5048 req->vf_id = vf_id; 5049 5050 if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags)) 5051 uc_tx_en = false; 5052 5053 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0); 5054 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0); 5055 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0); 5056 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0); 5057 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0); 5058 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0); 5059 req->extend_promisc = promisc_cfg; 5060 5061 /* to be compatible with DEVICE_VERSION_V1/2 */ 5062 promisc_cfg = 0; 5063 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0); 5064 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0); 5065 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0); 5066 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1); 5067 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1); 5068 req->promisc = promisc_cfg; 5069 5070 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5071 if (ret) 5072 dev_err(&hdev->pdev->dev, 5073 "failed to set vport %u promisc mode, ret = %d.\n", 5074 vf_id, ret); 5075 5076 return ret; 5077 } 5078 5079 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 5080 bool en_mc_pmc, bool en_bc_pmc) 5081 { 5082 return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id, 5083 en_uc_pmc, en_mc_pmc, en_bc_pmc); 5084 } 5085 5086 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 5087 bool en_mc_pmc) 5088 { 5089 struct hclge_vport *vport = hclge_get_vport(handle); 5090 struct hclge_dev *hdev = vport->back; 5091 bool en_bc_pmc = true; 5092 5093 /* For device whose version below V2, if broadcast promisc enabled, 5094 * vlan filter is always bypassed. So broadcast promisc should be 5095 * disabled until user enable promisc mode 5096 */ 5097 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 5098 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false; 5099 5100 return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc, 5101 en_bc_pmc); 5102 } 5103 5104 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle) 5105 { 5106 struct hclge_vport *vport = hclge_get_vport(handle); 5107 5108 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5109 } 5110 5111 static void hclge_sync_fd_state(struct hclge_dev *hdev) 5112 { 5113 if (hlist_empty(&hdev->fd_rule_list)) 5114 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 5115 } 5116 5117 static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location) 5118 { 5119 if (!test_bit(location, hdev->fd_bmap)) { 5120 set_bit(location, hdev->fd_bmap); 5121 hdev->hclge_fd_rule_num++; 5122 } 5123 } 5124 5125 static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location) 5126 { 5127 if (test_bit(location, hdev->fd_bmap)) { 5128 clear_bit(location, hdev->fd_bmap); 5129 hdev->hclge_fd_rule_num--; 5130 } 5131 } 5132 5133 static void hclge_fd_free_node(struct hclge_dev *hdev, 5134 struct hclge_fd_rule *rule) 5135 { 5136 hlist_del(&rule->rule_node); 5137 kfree(rule); 5138 hclge_sync_fd_state(hdev); 5139 } 5140 5141 static void hclge_update_fd_rule_node(struct hclge_dev *hdev, 5142 struct hclge_fd_rule *old_rule, 5143 struct hclge_fd_rule *new_rule, 5144 enum HCLGE_FD_NODE_STATE state) 5145 { 5146 switch (state) { 5147 case HCLGE_FD_TO_ADD: 5148 case HCLGE_FD_ACTIVE: 5149 /* 1) if the new state is TO_ADD, just replace the old rule 5150 * with the same location, no matter its state, because the 5151 * new rule will be configured to the hardware. 5152 * 2) if the new state is ACTIVE, it means the new rule 5153 * has been configured to the hardware, so just replace 5154 * the old rule node with the same location. 5155 * 3) for it doesn't add a new node to the list, so it's 5156 * unnecessary to update the rule number and fd_bmap. 5157 */ 5158 new_rule->rule_node.next = old_rule->rule_node.next; 5159 new_rule->rule_node.pprev = old_rule->rule_node.pprev; 5160 memcpy(old_rule, new_rule, sizeof(*old_rule)); 5161 kfree(new_rule); 5162 break; 5163 case HCLGE_FD_DELETED: 5164 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5165 hclge_fd_free_node(hdev, old_rule); 5166 break; 5167 case HCLGE_FD_TO_DEL: 5168 /* if new request is TO_DEL, and old rule is existent 5169 * 1) the state of old rule is TO_DEL, we need do nothing, 5170 * because we delete rule by location, other rule content 5171 * is unncessary. 5172 * 2) the state of old rule is ACTIVE, we need to change its 5173 * state to TO_DEL, so the rule will be deleted when periodic 5174 * task being scheduled. 5175 * 3) the state of old rule is TO_ADD, it means the rule hasn't 5176 * been added to hardware, so we just delete the rule node from 5177 * fd_rule_list directly. 5178 */ 5179 if (old_rule->state == HCLGE_FD_TO_ADD) { 5180 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5181 hclge_fd_free_node(hdev, old_rule); 5182 return; 5183 } 5184 old_rule->state = HCLGE_FD_TO_DEL; 5185 break; 5186 } 5187 } 5188 5189 static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist, 5190 u16 location, 5191 struct hclge_fd_rule **parent) 5192 { 5193 struct hclge_fd_rule *rule; 5194 struct hlist_node *node; 5195 5196 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 5197 if (rule->location == location) 5198 return rule; 5199 else if (rule->location > location) 5200 return NULL; 5201 /* record the parent node, use to keep the nodes in fd_rule_list 5202 * in ascend order. 5203 */ 5204 *parent = rule; 5205 } 5206 5207 return NULL; 5208 } 5209 5210 /* insert fd rule node in ascend order according to rule->location */ 5211 static void hclge_fd_insert_rule_node(struct hlist_head *hlist, 5212 struct hclge_fd_rule *rule, 5213 struct hclge_fd_rule *parent) 5214 { 5215 INIT_HLIST_NODE(&rule->rule_node); 5216 5217 if (parent) 5218 hlist_add_behind(&rule->rule_node, &parent->rule_node); 5219 else 5220 hlist_add_head(&rule->rule_node, hlist); 5221 } 5222 5223 static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev, 5224 struct hclge_fd_user_def_cfg *cfg) 5225 { 5226 struct hclge_fd_user_def_cfg_cmd *req; 5227 struct hclge_desc desc; 5228 u16 data = 0; 5229 int ret; 5230 5231 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false); 5232 5233 req = (struct hclge_fd_user_def_cfg_cmd *)desc.data; 5234 5235 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0); 5236 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5237 HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset); 5238 req->ol2_cfg = cpu_to_le16(data); 5239 5240 data = 0; 5241 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0); 5242 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5243 HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset); 5244 req->ol3_cfg = cpu_to_le16(data); 5245 5246 data = 0; 5247 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0); 5248 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5249 HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset); 5250 req->ol4_cfg = cpu_to_le16(data); 5251 5252 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5253 if (ret) 5254 dev_err(&hdev->pdev->dev, 5255 "failed to set fd user def data, ret= %d\n", ret); 5256 return ret; 5257 } 5258 5259 static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked) 5260 { 5261 int ret; 5262 5263 if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state)) 5264 return; 5265 5266 if (!locked) 5267 spin_lock_bh(&hdev->fd_rule_lock); 5268 5269 ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg); 5270 if (ret) 5271 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5272 5273 if (!locked) 5274 spin_unlock_bh(&hdev->fd_rule_lock); 5275 } 5276 5277 static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev, 5278 struct hclge_fd_rule *rule) 5279 { 5280 struct hlist_head *hlist = &hdev->fd_rule_list; 5281 struct hclge_fd_rule *fd_rule, *parent = NULL; 5282 struct hclge_fd_user_def_info *info, *old_info; 5283 struct hclge_fd_user_def_cfg *cfg; 5284 5285 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5286 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5287 return 0; 5288 5289 /* for valid layer is start from 1, so need minus 1 to get the cfg */ 5290 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5291 info = &rule->ep.user_def; 5292 5293 if (!cfg->ref_cnt || cfg->offset == info->offset) 5294 return 0; 5295 5296 if (cfg->ref_cnt > 1) 5297 goto error; 5298 5299 fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent); 5300 if (fd_rule) { 5301 old_info = &fd_rule->ep.user_def; 5302 if (info->layer == old_info->layer) 5303 return 0; 5304 } 5305 5306 error: 5307 dev_err(&hdev->pdev->dev, 5308 "No available offset for layer%d fd rule, each layer only support one user def offset.\n", 5309 info->layer + 1); 5310 return -ENOSPC; 5311 } 5312 5313 static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev, 5314 struct hclge_fd_rule *rule) 5315 { 5316 struct hclge_fd_user_def_cfg *cfg; 5317 5318 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5319 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5320 return; 5321 5322 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5323 if (!cfg->ref_cnt) { 5324 cfg->offset = rule->ep.user_def.offset; 5325 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5326 } 5327 cfg->ref_cnt++; 5328 } 5329 5330 static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev, 5331 struct hclge_fd_rule *rule) 5332 { 5333 struct hclge_fd_user_def_cfg *cfg; 5334 5335 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5336 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5337 return; 5338 5339 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5340 if (!cfg->ref_cnt) 5341 return; 5342 5343 cfg->ref_cnt--; 5344 if (!cfg->ref_cnt) { 5345 cfg->offset = 0; 5346 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5347 } 5348 } 5349 5350 static void hclge_update_fd_list(struct hclge_dev *hdev, 5351 enum HCLGE_FD_NODE_STATE state, u16 location, 5352 struct hclge_fd_rule *new_rule) 5353 { 5354 struct hlist_head *hlist = &hdev->fd_rule_list; 5355 struct hclge_fd_rule *fd_rule, *parent = NULL; 5356 5357 fd_rule = hclge_find_fd_rule(hlist, location, &parent); 5358 if (fd_rule) { 5359 hclge_fd_dec_user_def_refcnt(hdev, fd_rule); 5360 if (state == HCLGE_FD_ACTIVE) 5361 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5362 hclge_sync_fd_user_def_cfg(hdev, true); 5363 5364 hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state); 5365 return; 5366 } 5367 5368 /* it's unlikely to fail here, because we have checked the rule 5369 * exist before. 5370 */ 5371 if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) { 5372 dev_warn(&hdev->pdev->dev, 5373 "failed to delete fd rule %u, it's inexistent\n", 5374 location); 5375 return; 5376 } 5377 5378 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5379 hclge_sync_fd_user_def_cfg(hdev, true); 5380 5381 hclge_fd_insert_rule_node(hlist, new_rule, parent); 5382 hclge_fd_inc_rule_cnt(hdev, new_rule->location); 5383 5384 if (state == HCLGE_FD_TO_ADD) { 5385 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 5386 hclge_task_schedule(hdev, 0); 5387 } 5388 } 5389 5390 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode) 5391 { 5392 struct hclge_get_fd_mode_cmd *req; 5393 struct hclge_desc desc; 5394 int ret; 5395 5396 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true); 5397 5398 req = (struct hclge_get_fd_mode_cmd *)desc.data; 5399 5400 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5401 if (ret) { 5402 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret); 5403 return ret; 5404 } 5405 5406 *fd_mode = req->mode; 5407 5408 return ret; 5409 } 5410 5411 static int hclge_get_fd_allocation(struct hclge_dev *hdev, 5412 u32 *stage1_entry_num, 5413 u32 *stage2_entry_num, 5414 u16 *stage1_counter_num, 5415 u16 *stage2_counter_num) 5416 { 5417 struct hclge_get_fd_allocation_cmd *req; 5418 struct hclge_desc desc; 5419 int ret; 5420 5421 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true); 5422 5423 req = (struct hclge_get_fd_allocation_cmd *)desc.data; 5424 5425 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5426 if (ret) { 5427 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n", 5428 ret); 5429 return ret; 5430 } 5431 5432 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num); 5433 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num); 5434 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num); 5435 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num); 5436 5437 return ret; 5438 } 5439 5440 static int hclge_set_fd_key_config(struct hclge_dev *hdev, 5441 enum HCLGE_FD_STAGE stage_num) 5442 { 5443 struct hclge_set_fd_key_config_cmd *req; 5444 struct hclge_fd_key_cfg *stage; 5445 struct hclge_desc desc; 5446 int ret; 5447 5448 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false); 5449 5450 req = (struct hclge_set_fd_key_config_cmd *)desc.data; 5451 stage = &hdev->fd_cfg.key_cfg[stage_num]; 5452 req->stage = stage_num; 5453 req->key_select = stage->key_sel; 5454 req->inner_sipv6_word_en = stage->inner_sipv6_word_en; 5455 req->inner_dipv6_word_en = stage->inner_dipv6_word_en; 5456 req->outer_sipv6_word_en = stage->outer_sipv6_word_en; 5457 req->outer_dipv6_word_en = stage->outer_dipv6_word_en; 5458 req->tuple_mask = cpu_to_le32(~stage->tuple_active); 5459 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active); 5460 5461 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5462 if (ret) 5463 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret); 5464 5465 return ret; 5466 } 5467 5468 static void hclge_fd_disable_user_def(struct hclge_dev *hdev) 5469 { 5470 struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg; 5471 5472 spin_lock_bh(&hdev->fd_rule_lock); 5473 memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg)); 5474 spin_unlock_bh(&hdev->fd_rule_lock); 5475 5476 hclge_fd_set_user_def_cmd(hdev, cfg); 5477 } 5478 5479 static int hclge_init_fd_config(struct hclge_dev *hdev) 5480 { 5481 #define LOW_2_WORDS 0x03 5482 struct hclge_fd_key_cfg *key_cfg; 5483 int ret; 5484 5485 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 5486 return 0; 5487 5488 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode); 5489 if (ret) 5490 return ret; 5491 5492 switch (hdev->fd_cfg.fd_mode) { 5493 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1: 5494 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH; 5495 break; 5496 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1: 5497 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2; 5498 break; 5499 default: 5500 dev_err(&hdev->pdev->dev, 5501 "Unsupported flow director mode %u\n", 5502 hdev->fd_cfg.fd_mode); 5503 return -EOPNOTSUPP; 5504 } 5505 5506 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1]; 5507 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE; 5508 key_cfg->inner_sipv6_word_en = LOW_2_WORDS; 5509 key_cfg->inner_dipv6_word_en = LOW_2_WORDS; 5510 key_cfg->outer_sipv6_word_en = 0; 5511 key_cfg->outer_dipv6_word_en = 0; 5512 5513 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) | 5514 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) | 5515 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5516 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5517 5518 /* If use max 400bit key, we can support tuples for ether type */ 5519 if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 5520 key_cfg->tuple_active |= 5521 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC); 5522 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5523 key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 5524 } 5525 5526 /* roce_type is used to filter roce frames 5527 * dst_vport is used to specify the rule 5528 */ 5529 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT); 5530 5531 ret = hclge_get_fd_allocation(hdev, 5532 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1], 5533 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2], 5534 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1], 5535 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]); 5536 if (ret) 5537 return ret; 5538 5539 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1); 5540 } 5541 5542 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x, 5543 int loc, u8 *key, bool is_add) 5544 { 5545 struct hclge_fd_tcam_config_1_cmd *req1; 5546 struct hclge_fd_tcam_config_2_cmd *req2; 5547 struct hclge_fd_tcam_config_3_cmd *req3; 5548 struct hclge_desc desc[3]; 5549 int ret; 5550 5551 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false); 5552 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5553 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false); 5554 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5555 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false); 5556 5557 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 5558 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 5559 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 5560 5561 req1->stage = stage; 5562 req1->xy_sel = sel_x ? 1 : 0; 5563 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0); 5564 req1->index = cpu_to_le32(loc); 5565 req1->entry_vld = sel_x ? is_add : 0; 5566 5567 if (key) { 5568 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data)); 5569 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)], 5570 sizeof(req2->tcam_data)); 5571 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) + 5572 sizeof(req2->tcam_data)], sizeof(req3->tcam_data)); 5573 } 5574 5575 ret = hclge_cmd_send(&hdev->hw, desc, 3); 5576 if (ret) 5577 dev_err(&hdev->pdev->dev, 5578 "config tcam key fail, ret=%d\n", 5579 ret); 5580 5581 return ret; 5582 } 5583 5584 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc, 5585 struct hclge_fd_ad_data *action) 5586 { 5587 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 5588 struct hclge_fd_ad_config_cmd *req; 5589 struct hclge_desc desc; 5590 u64 ad_data = 0; 5591 int ret; 5592 5593 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false); 5594 5595 req = (struct hclge_fd_ad_config_cmd *)desc.data; 5596 req->index = cpu_to_le32(loc); 5597 req->stage = stage; 5598 5599 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B, 5600 action->write_rule_id_to_bd); 5601 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S, 5602 action->rule_id); 5603 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) { 5604 hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B, 5605 action->override_tc); 5606 hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M, 5607 HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size); 5608 } 5609 ad_data <<= 32; 5610 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet); 5611 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B, 5612 action->forward_to_direct_queue); 5613 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S, 5614 action->queue_id); 5615 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter); 5616 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M, 5617 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id); 5618 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage); 5619 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S, 5620 action->counter_id); 5621 5622 req->ad_data = cpu_to_le64(ad_data); 5623 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5624 if (ret) 5625 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret); 5626 5627 return ret; 5628 } 5629 5630 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y, 5631 struct hclge_fd_rule *rule) 5632 { 5633 int offset, moffset, ip_offset; 5634 enum HCLGE_FD_KEY_OPT key_opt; 5635 u16 tmp_x_s, tmp_y_s; 5636 u32 tmp_x_l, tmp_y_l; 5637 u8 *p = (u8 *)rule; 5638 int i; 5639 5640 if (rule->unused_tuple & BIT(tuple_bit)) 5641 return true; 5642 5643 key_opt = tuple_key_info[tuple_bit].key_opt; 5644 offset = tuple_key_info[tuple_bit].offset; 5645 moffset = tuple_key_info[tuple_bit].moffset; 5646 5647 switch (key_opt) { 5648 case KEY_OPT_U8: 5649 calc_x(*key_x, p[offset], p[moffset]); 5650 calc_y(*key_y, p[offset], p[moffset]); 5651 5652 return true; 5653 case KEY_OPT_LE16: 5654 calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5655 calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5656 *(__le16 *)key_x = cpu_to_le16(tmp_x_s); 5657 *(__le16 *)key_y = cpu_to_le16(tmp_y_s); 5658 5659 return true; 5660 case KEY_OPT_LE32: 5661 calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5662 calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5663 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5664 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5665 5666 return true; 5667 case KEY_OPT_MAC: 5668 for (i = 0; i < ETH_ALEN; i++) { 5669 calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i], 5670 p[moffset + i]); 5671 calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i], 5672 p[moffset + i]); 5673 } 5674 5675 return true; 5676 case KEY_OPT_IP: 5677 ip_offset = IPV4_INDEX * sizeof(u32); 5678 calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]), 5679 *(u32 *)(&p[moffset + ip_offset])); 5680 calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]), 5681 *(u32 *)(&p[moffset + ip_offset])); 5682 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5683 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5684 5685 return true; 5686 default: 5687 return false; 5688 } 5689 } 5690 5691 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 5692 u8 vf_id, u8 network_port_id) 5693 { 5694 u32 port_number = 0; 5695 5696 if (port_type == HOST_PORT) { 5697 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S, 5698 pf_id); 5699 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S, 5700 vf_id); 5701 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT); 5702 } else { 5703 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M, 5704 HCLGE_NETWORK_PORT_ID_S, network_port_id); 5705 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT); 5706 } 5707 5708 return port_number; 5709 } 5710 5711 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg, 5712 __le32 *key_x, __le32 *key_y, 5713 struct hclge_fd_rule *rule) 5714 { 5715 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number; 5716 u8 cur_pos = 0, tuple_size, shift_bits; 5717 unsigned int i; 5718 5719 for (i = 0; i < MAX_META_DATA; i++) { 5720 tuple_size = meta_data_key_info[i].key_length; 5721 tuple_bit = key_cfg->meta_data_active & BIT(i); 5722 5723 switch (tuple_bit) { 5724 case BIT(ROCE_TYPE): 5725 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET); 5726 cur_pos += tuple_size; 5727 break; 5728 case BIT(DST_VPORT): 5729 port_number = hclge_get_port_number(HOST_PORT, 0, 5730 rule->vf_id, 0); 5731 hnae3_set_field(meta_data, 5732 GENMASK(cur_pos + tuple_size, cur_pos), 5733 cur_pos, port_number); 5734 cur_pos += tuple_size; 5735 break; 5736 default: 5737 break; 5738 } 5739 } 5740 5741 calc_x(tmp_x, meta_data, 0xFFFFFFFF); 5742 calc_y(tmp_y, meta_data, 0xFFFFFFFF); 5743 shift_bits = sizeof(meta_data) * 8 - cur_pos; 5744 5745 *key_x = cpu_to_le32(tmp_x << shift_bits); 5746 *key_y = cpu_to_le32(tmp_y << shift_bits); 5747 } 5748 5749 /* A complete key is combined with meta data key and tuple key. 5750 * Meta data key is stored at the MSB region, and tuple key is stored at 5751 * the LSB region, unused bits will be filled 0. 5752 */ 5753 static int hclge_config_key(struct hclge_dev *hdev, u8 stage, 5754 struct hclge_fd_rule *rule) 5755 { 5756 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage]; 5757 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES]; 5758 u8 *cur_key_x, *cur_key_y; 5759 u8 meta_data_region; 5760 u8 tuple_size; 5761 int ret; 5762 u32 i; 5763 5764 memset(key_x, 0, sizeof(key_x)); 5765 memset(key_y, 0, sizeof(key_y)); 5766 cur_key_x = key_x; 5767 cur_key_y = key_y; 5768 5769 for (i = 0; i < MAX_TUPLE; i++) { 5770 bool tuple_valid; 5771 5772 tuple_size = tuple_key_info[i].key_length / 8; 5773 if (!(key_cfg->tuple_active & BIT(i))) 5774 continue; 5775 5776 tuple_valid = hclge_fd_convert_tuple(i, cur_key_x, 5777 cur_key_y, rule); 5778 if (tuple_valid) { 5779 cur_key_x += tuple_size; 5780 cur_key_y += tuple_size; 5781 } 5782 } 5783 5784 meta_data_region = hdev->fd_cfg.max_key_length / 8 - 5785 MAX_META_DATA_LENGTH / 8; 5786 5787 hclge_fd_convert_meta_data(key_cfg, 5788 (__le32 *)(key_x + meta_data_region), 5789 (__le32 *)(key_y + meta_data_region), 5790 rule); 5791 5792 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y, 5793 true); 5794 if (ret) { 5795 dev_err(&hdev->pdev->dev, 5796 "fd key_y config fail, loc=%u, ret=%d\n", 5797 rule->queue_id, ret); 5798 return ret; 5799 } 5800 5801 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x, 5802 true); 5803 if (ret) 5804 dev_err(&hdev->pdev->dev, 5805 "fd key_x config fail, loc=%u, ret=%d\n", 5806 rule->queue_id, ret); 5807 return ret; 5808 } 5809 5810 static int hclge_config_action(struct hclge_dev *hdev, u8 stage, 5811 struct hclge_fd_rule *rule) 5812 { 5813 struct hclge_vport *vport = hdev->vport; 5814 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5815 struct hclge_fd_ad_data ad_data; 5816 5817 memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data)); 5818 ad_data.ad_id = rule->location; 5819 5820 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 5821 ad_data.drop_packet = true; 5822 } else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) { 5823 ad_data.override_tc = true; 5824 ad_data.queue_id = 5825 kinfo->tc_info.tqp_offset[rule->cls_flower.tc]; 5826 ad_data.tc_size = 5827 ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]); 5828 } else { 5829 ad_data.forward_to_direct_queue = true; 5830 ad_data.queue_id = rule->queue_id; 5831 } 5832 5833 if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) { 5834 ad_data.use_counter = true; 5835 ad_data.counter_id = rule->vf_id % 5836 hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]; 5837 } else { 5838 ad_data.use_counter = false; 5839 ad_data.counter_id = 0; 5840 } 5841 5842 ad_data.use_next_stage = false; 5843 ad_data.next_input_key = 0; 5844 5845 ad_data.write_rule_id_to_bd = true; 5846 ad_data.rule_id = rule->location; 5847 5848 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data); 5849 } 5850 5851 static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec, 5852 u32 *unused_tuple) 5853 { 5854 if (!spec || !unused_tuple) 5855 return -EINVAL; 5856 5857 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5858 5859 if (!spec->ip4src) 5860 *unused_tuple |= BIT(INNER_SRC_IP); 5861 5862 if (!spec->ip4dst) 5863 *unused_tuple |= BIT(INNER_DST_IP); 5864 5865 if (!spec->psrc) 5866 *unused_tuple |= BIT(INNER_SRC_PORT); 5867 5868 if (!spec->pdst) 5869 *unused_tuple |= BIT(INNER_DST_PORT); 5870 5871 if (!spec->tos) 5872 *unused_tuple |= BIT(INNER_IP_TOS); 5873 5874 return 0; 5875 } 5876 5877 static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec, 5878 u32 *unused_tuple) 5879 { 5880 if (!spec || !unused_tuple) 5881 return -EINVAL; 5882 5883 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5884 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5885 5886 if (!spec->ip4src) 5887 *unused_tuple |= BIT(INNER_SRC_IP); 5888 5889 if (!spec->ip4dst) 5890 *unused_tuple |= BIT(INNER_DST_IP); 5891 5892 if (!spec->tos) 5893 *unused_tuple |= BIT(INNER_IP_TOS); 5894 5895 if (!spec->proto) 5896 *unused_tuple |= BIT(INNER_IP_PROTO); 5897 5898 if (spec->l4_4_bytes) 5899 return -EOPNOTSUPP; 5900 5901 if (spec->ip_ver != ETH_RX_NFC_IP4) 5902 return -EOPNOTSUPP; 5903 5904 return 0; 5905 } 5906 5907 static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec, 5908 u32 *unused_tuple) 5909 { 5910 if (!spec || !unused_tuple) 5911 return -EINVAL; 5912 5913 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5914 5915 /* check whether src/dst ip address used */ 5916 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5917 *unused_tuple |= BIT(INNER_SRC_IP); 5918 5919 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5920 *unused_tuple |= BIT(INNER_DST_IP); 5921 5922 if (!spec->psrc) 5923 *unused_tuple |= BIT(INNER_SRC_PORT); 5924 5925 if (!spec->pdst) 5926 *unused_tuple |= BIT(INNER_DST_PORT); 5927 5928 if (!spec->tclass) 5929 *unused_tuple |= BIT(INNER_IP_TOS); 5930 5931 return 0; 5932 } 5933 5934 static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec, 5935 u32 *unused_tuple) 5936 { 5937 if (!spec || !unused_tuple) 5938 return -EINVAL; 5939 5940 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5941 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5942 5943 /* check whether src/dst ip address used */ 5944 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5945 *unused_tuple |= BIT(INNER_SRC_IP); 5946 5947 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5948 *unused_tuple |= BIT(INNER_DST_IP); 5949 5950 if (!spec->l4_proto) 5951 *unused_tuple |= BIT(INNER_IP_PROTO); 5952 5953 if (!spec->tclass) 5954 *unused_tuple |= BIT(INNER_IP_TOS); 5955 5956 if (spec->l4_4_bytes) 5957 return -EOPNOTSUPP; 5958 5959 return 0; 5960 } 5961 5962 static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple) 5963 { 5964 if (!spec || !unused_tuple) 5965 return -EINVAL; 5966 5967 *unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5968 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) | 5969 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO); 5970 5971 if (is_zero_ether_addr(spec->h_source)) 5972 *unused_tuple |= BIT(INNER_SRC_MAC); 5973 5974 if (is_zero_ether_addr(spec->h_dest)) 5975 *unused_tuple |= BIT(INNER_DST_MAC); 5976 5977 if (!spec->h_proto) 5978 *unused_tuple |= BIT(INNER_ETH_TYPE); 5979 5980 return 0; 5981 } 5982 5983 static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev, 5984 struct ethtool_rx_flow_spec *fs, 5985 u32 *unused_tuple) 5986 { 5987 if (fs->flow_type & FLOW_EXT) { 5988 if (fs->h_ext.vlan_etype) { 5989 dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n"); 5990 return -EOPNOTSUPP; 5991 } 5992 5993 if (!fs->h_ext.vlan_tci) 5994 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 5995 5996 if (fs->m_ext.vlan_tci && 5997 be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) { 5998 dev_err(&hdev->pdev->dev, 5999 "failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n", 6000 ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1); 6001 return -EINVAL; 6002 } 6003 } else { 6004 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6005 } 6006 6007 if (fs->flow_type & FLOW_MAC_EXT) { 6008 if (hdev->fd_cfg.fd_mode != 6009 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6010 dev_err(&hdev->pdev->dev, 6011 "FLOW_MAC_EXT is not supported in current fd mode!\n"); 6012 return -EOPNOTSUPP; 6013 } 6014 6015 if (is_zero_ether_addr(fs->h_ext.h_dest)) 6016 *unused_tuple |= BIT(INNER_DST_MAC); 6017 else 6018 *unused_tuple &= ~BIT(INNER_DST_MAC); 6019 } 6020 6021 return 0; 6022 } 6023 6024 static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple, 6025 struct hclge_fd_user_def_info *info) 6026 { 6027 switch (flow_type) { 6028 case ETHER_FLOW: 6029 info->layer = HCLGE_FD_USER_DEF_L2; 6030 *unused_tuple &= ~BIT(INNER_L2_RSV); 6031 break; 6032 case IP_USER_FLOW: 6033 case IPV6_USER_FLOW: 6034 info->layer = HCLGE_FD_USER_DEF_L3; 6035 *unused_tuple &= ~BIT(INNER_L3_RSV); 6036 break; 6037 case TCP_V4_FLOW: 6038 case UDP_V4_FLOW: 6039 case TCP_V6_FLOW: 6040 case UDP_V6_FLOW: 6041 info->layer = HCLGE_FD_USER_DEF_L4; 6042 *unused_tuple &= ~BIT(INNER_L4_RSV); 6043 break; 6044 default: 6045 return -EOPNOTSUPP; 6046 } 6047 6048 return 0; 6049 } 6050 6051 static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs) 6052 { 6053 return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0; 6054 } 6055 6056 static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev, 6057 struct ethtool_rx_flow_spec *fs, 6058 u32 *unused_tuple, 6059 struct hclge_fd_user_def_info *info) 6060 { 6061 u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active; 6062 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6063 u16 data, offset, data_mask, offset_mask; 6064 int ret; 6065 6066 info->layer = HCLGE_FD_USER_DEF_NONE; 6067 *unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 6068 6069 if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs)) 6070 return 0; 6071 6072 /* user-def data from ethtool is 64 bit value, the bit0~15 is used 6073 * for data, and bit32~47 is used for offset. 6074 */ 6075 data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6076 data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6077 offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6078 offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6079 6080 if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) { 6081 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n"); 6082 return -EOPNOTSUPP; 6083 } 6084 6085 if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) { 6086 dev_err(&hdev->pdev->dev, 6087 "user-def offset[%u] should be no more than %u\n", 6088 offset, HCLGE_FD_MAX_USER_DEF_OFFSET); 6089 return -EINVAL; 6090 } 6091 6092 if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) { 6093 dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n"); 6094 return -EINVAL; 6095 } 6096 6097 ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info); 6098 if (ret) { 6099 dev_err(&hdev->pdev->dev, 6100 "unsupported flow type for user-def bytes, ret = %d\n", 6101 ret); 6102 return ret; 6103 } 6104 6105 info->data = data; 6106 info->data_mask = data_mask; 6107 info->offset = offset; 6108 6109 return 0; 6110 } 6111 6112 static int hclge_fd_check_spec(struct hclge_dev *hdev, 6113 struct ethtool_rx_flow_spec *fs, 6114 u32 *unused_tuple, 6115 struct hclge_fd_user_def_info *info) 6116 { 6117 u32 flow_type; 6118 int ret; 6119 6120 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 6121 dev_err(&hdev->pdev->dev, 6122 "failed to config fd rules, invalid rule location: %u, max is %u\n.", 6123 fs->location, 6124 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1); 6125 return -EINVAL; 6126 } 6127 6128 ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info); 6129 if (ret) 6130 return ret; 6131 6132 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6133 switch (flow_type) { 6134 case SCTP_V4_FLOW: 6135 case TCP_V4_FLOW: 6136 case UDP_V4_FLOW: 6137 ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec, 6138 unused_tuple); 6139 break; 6140 case IP_USER_FLOW: 6141 ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec, 6142 unused_tuple); 6143 break; 6144 case SCTP_V6_FLOW: 6145 case TCP_V6_FLOW: 6146 case UDP_V6_FLOW: 6147 ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec, 6148 unused_tuple); 6149 break; 6150 case IPV6_USER_FLOW: 6151 ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec, 6152 unused_tuple); 6153 break; 6154 case ETHER_FLOW: 6155 if (hdev->fd_cfg.fd_mode != 6156 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6157 dev_err(&hdev->pdev->dev, 6158 "ETHER_FLOW is not supported in current fd mode!\n"); 6159 return -EOPNOTSUPP; 6160 } 6161 6162 ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec, 6163 unused_tuple); 6164 break; 6165 default: 6166 dev_err(&hdev->pdev->dev, 6167 "unsupported protocol type, protocol type = %#x\n", 6168 flow_type); 6169 return -EOPNOTSUPP; 6170 } 6171 6172 if (ret) { 6173 dev_err(&hdev->pdev->dev, 6174 "failed to check flow union tuple, ret = %d\n", 6175 ret); 6176 return ret; 6177 } 6178 6179 return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple); 6180 } 6181 6182 static void hclge_fd_get_tcpip4_tuple(struct ethtool_rx_flow_spec *fs, 6183 struct hclge_fd_rule *rule, u8 ip_proto) 6184 { 6185 rule->tuples.src_ip[IPV4_INDEX] = 6186 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src); 6187 rule->tuples_mask.src_ip[IPV4_INDEX] = 6188 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src); 6189 6190 rule->tuples.dst_ip[IPV4_INDEX] = 6191 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst); 6192 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6193 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst); 6194 6195 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc); 6196 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc); 6197 6198 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst); 6199 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst); 6200 6201 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos; 6202 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos; 6203 6204 rule->tuples.ether_proto = ETH_P_IP; 6205 rule->tuples_mask.ether_proto = 0xFFFF; 6206 6207 rule->tuples.ip_proto = ip_proto; 6208 rule->tuples_mask.ip_proto = 0xFF; 6209 } 6210 6211 static void hclge_fd_get_ip4_tuple(struct ethtool_rx_flow_spec *fs, 6212 struct hclge_fd_rule *rule) 6213 { 6214 rule->tuples.src_ip[IPV4_INDEX] = 6215 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src); 6216 rule->tuples_mask.src_ip[IPV4_INDEX] = 6217 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src); 6218 6219 rule->tuples.dst_ip[IPV4_INDEX] = 6220 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst); 6221 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6222 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst); 6223 6224 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos; 6225 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos; 6226 6227 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto; 6228 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto; 6229 6230 rule->tuples.ether_proto = ETH_P_IP; 6231 rule->tuples_mask.ether_proto = 0xFFFF; 6232 } 6233 6234 static void hclge_fd_get_tcpip6_tuple(struct ethtool_rx_flow_spec *fs, 6235 struct hclge_fd_rule *rule, u8 ip_proto) 6236 { 6237 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.tcp_ip6_spec.ip6src, 6238 IPV6_SIZE); 6239 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.tcp_ip6_spec.ip6src, 6240 IPV6_SIZE); 6241 6242 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.tcp_ip6_spec.ip6dst, 6243 IPV6_SIZE); 6244 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.tcp_ip6_spec.ip6dst, 6245 IPV6_SIZE); 6246 6247 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc); 6248 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc); 6249 6250 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst); 6251 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst); 6252 6253 rule->tuples.ether_proto = ETH_P_IPV6; 6254 rule->tuples_mask.ether_proto = 0xFFFF; 6255 6256 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6257 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6258 6259 rule->tuples.ip_proto = ip_proto; 6260 rule->tuples_mask.ip_proto = 0xFF; 6261 } 6262 6263 static void hclge_fd_get_ip6_tuple(struct ethtool_rx_flow_spec *fs, 6264 struct hclge_fd_rule *rule) 6265 { 6266 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.usr_ip6_spec.ip6src, 6267 IPV6_SIZE); 6268 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.usr_ip6_spec.ip6src, 6269 IPV6_SIZE); 6270 6271 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.usr_ip6_spec.ip6dst, 6272 IPV6_SIZE); 6273 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.usr_ip6_spec.ip6dst, 6274 IPV6_SIZE); 6275 6276 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto; 6277 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto; 6278 6279 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6280 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6281 6282 rule->tuples.ether_proto = ETH_P_IPV6; 6283 rule->tuples_mask.ether_proto = 0xFFFF; 6284 } 6285 6286 static void hclge_fd_get_ether_tuple(struct ethtool_rx_flow_spec *fs, 6287 struct hclge_fd_rule *rule) 6288 { 6289 ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source); 6290 ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source); 6291 6292 ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest); 6293 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest); 6294 6295 rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto); 6296 rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto); 6297 } 6298 6299 static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info, 6300 struct hclge_fd_rule *rule) 6301 { 6302 switch (info->layer) { 6303 case HCLGE_FD_USER_DEF_L2: 6304 rule->tuples.l2_user_def = info->data; 6305 rule->tuples_mask.l2_user_def = info->data_mask; 6306 break; 6307 case HCLGE_FD_USER_DEF_L3: 6308 rule->tuples.l3_user_def = info->data; 6309 rule->tuples_mask.l3_user_def = info->data_mask; 6310 break; 6311 case HCLGE_FD_USER_DEF_L4: 6312 rule->tuples.l4_user_def = (u32)info->data << 16; 6313 rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16; 6314 break; 6315 default: 6316 break; 6317 } 6318 6319 rule->ep.user_def = *info; 6320 } 6321 6322 static int hclge_fd_get_tuple(struct ethtool_rx_flow_spec *fs, 6323 struct hclge_fd_rule *rule, 6324 struct hclge_fd_user_def_info *info) 6325 { 6326 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6327 6328 switch (flow_type) { 6329 case SCTP_V4_FLOW: 6330 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_SCTP); 6331 break; 6332 case TCP_V4_FLOW: 6333 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_TCP); 6334 break; 6335 case UDP_V4_FLOW: 6336 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_UDP); 6337 break; 6338 case IP_USER_FLOW: 6339 hclge_fd_get_ip4_tuple(fs, rule); 6340 break; 6341 case SCTP_V6_FLOW: 6342 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_SCTP); 6343 break; 6344 case TCP_V6_FLOW: 6345 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_TCP); 6346 break; 6347 case UDP_V6_FLOW: 6348 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_UDP); 6349 break; 6350 case IPV6_USER_FLOW: 6351 hclge_fd_get_ip6_tuple(fs, rule); 6352 break; 6353 case ETHER_FLOW: 6354 hclge_fd_get_ether_tuple(fs, rule); 6355 break; 6356 default: 6357 return -EOPNOTSUPP; 6358 } 6359 6360 if (fs->flow_type & FLOW_EXT) { 6361 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci); 6362 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci); 6363 hclge_fd_get_user_def_tuple(info, rule); 6364 } 6365 6366 if (fs->flow_type & FLOW_MAC_EXT) { 6367 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest); 6368 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest); 6369 } 6370 6371 return 0; 6372 } 6373 6374 static int hclge_fd_config_rule(struct hclge_dev *hdev, 6375 struct hclge_fd_rule *rule) 6376 { 6377 int ret; 6378 6379 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule); 6380 if (ret) 6381 return ret; 6382 6383 return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule); 6384 } 6385 6386 static int hclge_add_fd_entry_common(struct hclge_dev *hdev, 6387 struct hclge_fd_rule *rule) 6388 { 6389 int ret; 6390 6391 spin_lock_bh(&hdev->fd_rule_lock); 6392 6393 if (hdev->fd_active_type != rule->rule_type && 6394 (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6395 hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) { 6396 dev_err(&hdev->pdev->dev, 6397 "mode conflict(new type %d, active type %d), please delete existent rules first\n", 6398 rule->rule_type, hdev->fd_active_type); 6399 spin_unlock_bh(&hdev->fd_rule_lock); 6400 return -EINVAL; 6401 } 6402 6403 ret = hclge_fd_check_user_def_refcnt(hdev, rule); 6404 if (ret) 6405 goto out; 6406 6407 ret = hclge_clear_arfs_rules(hdev); 6408 if (ret) 6409 goto out; 6410 6411 ret = hclge_fd_config_rule(hdev, rule); 6412 if (ret) 6413 goto out; 6414 6415 rule->state = HCLGE_FD_ACTIVE; 6416 hdev->fd_active_type = rule->rule_type; 6417 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 6418 6419 out: 6420 spin_unlock_bh(&hdev->fd_rule_lock); 6421 return ret; 6422 } 6423 6424 static bool hclge_is_cls_flower_active(struct hnae3_handle *handle) 6425 { 6426 struct hclge_vport *vport = hclge_get_vport(handle); 6427 struct hclge_dev *hdev = vport->back; 6428 6429 return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE; 6430 } 6431 6432 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie, 6433 u16 *vport_id, u8 *action, u16 *queue_id) 6434 { 6435 struct hclge_vport *vport = hdev->vport; 6436 6437 if (ring_cookie == RX_CLS_FLOW_DISC) { 6438 *action = HCLGE_FD_ACTION_DROP_PACKET; 6439 } else { 6440 u32 ring = ethtool_get_flow_spec_ring(ring_cookie); 6441 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie); 6442 u16 tqps; 6443 6444 /* To keep consistent with user's configuration, minus 1 when 6445 * printing 'vf', because vf id from ethtool is added 1 for vf. 6446 */ 6447 if (vf > hdev->num_req_vfs) { 6448 dev_err(&hdev->pdev->dev, 6449 "Error: vf id (%u) should be less than %u\n", 6450 vf - 1U, hdev->num_req_vfs); 6451 return -EINVAL; 6452 } 6453 6454 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id; 6455 tqps = hdev->vport[vf].nic.kinfo.num_tqps; 6456 6457 if (ring >= tqps) { 6458 dev_err(&hdev->pdev->dev, 6459 "Error: queue id (%u) > max tqp num (%u)\n", 6460 ring, tqps - 1U); 6461 return -EINVAL; 6462 } 6463 6464 *action = HCLGE_FD_ACTION_SELECT_QUEUE; 6465 *queue_id = ring; 6466 } 6467 6468 return 0; 6469 } 6470 6471 static int hclge_add_fd_entry(struct hnae3_handle *handle, 6472 struct ethtool_rxnfc *cmd) 6473 { 6474 struct hclge_vport *vport = hclge_get_vport(handle); 6475 struct hclge_dev *hdev = vport->back; 6476 struct hclge_fd_user_def_info info; 6477 u16 dst_vport_id = 0, q_index = 0; 6478 struct ethtool_rx_flow_spec *fs; 6479 struct hclge_fd_rule *rule; 6480 u32 unused = 0; 6481 u8 action; 6482 int ret; 6483 6484 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 6485 dev_err(&hdev->pdev->dev, 6486 "flow table director is not supported\n"); 6487 return -EOPNOTSUPP; 6488 } 6489 6490 if (!hdev->fd_en) { 6491 dev_err(&hdev->pdev->dev, 6492 "please enable flow director first\n"); 6493 return -EOPNOTSUPP; 6494 } 6495 6496 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6497 6498 ret = hclge_fd_check_spec(hdev, fs, &unused, &info); 6499 if (ret) 6500 return ret; 6501 6502 ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id, 6503 &action, &q_index); 6504 if (ret) 6505 return ret; 6506 6507 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 6508 if (!rule) 6509 return -ENOMEM; 6510 6511 ret = hclge_fd_get_tuple(fs, rule, &info); 6512 if (ret) { 6513 kfree(rule); 6514 return ret; 6515 } 6516 6517 rule->flow_type = fs->flow_type; 6518 rule->location = fs->location; 6519 rule->unused_tuple = unused; 6520 rule->vf_id = dst_vport_id; 6521 rule->queue_id = q_index; 6522 rule->action = action; 6523 rule->rule_type = HCLGE_FD_EP_ACTIVE; 6524 6525 ret = hclge_add_fd_entry_common(hdev, rule); 6526 if (ret) 6527 kfree(rule); 6528 6529 return ret; 6530 } 6531 6532 static int hclge_del_fd_entry(struct hnae3_handle *handle, 6533 struct ethtool_rxnfc *cmd) 6534 { 6535 struct hclge_vport *vport = hclge_get_vport(handle); 6536 struct hclge_dev *hdev = vport->back; 6537 struct ethtool_rx_flow_spec *fs; 6538 int ret; 6539 6540 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6541 return -EOPNOTSUPP; 6542 6543 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6544 6545 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6546 return -EINVAL; 6547 6548 spin_lock_bh(&hdev->fd_rule_lock); 6549 if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6550 !test_bit(fs->location, hdev->fd_bmap)) { 6551 dev_err(&hdev->pdev->dev, 6552 "Delete fail, rule %u is inexistent\n", fs->location); 6553 spin_unlock_bh(&hdev->fd_rule_lock); 6554 return -ENOENT; 6555 } 6556 6557 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location, 6558 NULL, false); 6559 if (ret) 6560 goto out; 6561 6562 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL); 6563 6564 out: 6565 spin_unlock_bh(&hdev->fd_rule_lock); 6566 return ret; 6567 } 6568 6569 static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev, 6570 bool clear_list) 6571 { 6572 struct hclge_fd_rule *rule; 6573 struct hlist_node *node; 6574 u16 location; 6575 6576 spin_lock_bh(&hdev->fd_rule_lock); 6577 6578 for_each_set_bit(location, hdev->fd_bmap, 6579 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6580 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location, 6581 NULL, false); 6582 6583 if (clear_list) { 6584 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, 6585 rule_node) { 6586 hlist_del(&rule->rule_node); 6587 kfree(rule); 6588 } 6589 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 6590 hdev->hclge_fd_rule_num = 0; 6591 bitmap_zero(hdev->fd_bmap, 6592 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 6593 } 6594 6595 spin_unlock_bh(&hdev->fd_rule_lock); 6596 } 6597 6598 static void hclge_del_all_fd_entries(struct hclge_dev *hdev) 6599 { 6600 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6601 return; 6602 6603 hclge_clear_fd_rules_in_list(hdev, true); 6604 hclge_fd_disable_user_def(hdev); 6605 } 6606 6607 static int hclge_restore_fd_entries(struct hnae3_handle *handle) 6608 { 6609 struct hclge_vport *vport = hclge_get_vport(handle); 6610 struct hclge_dev *hdev = vport->back; 6611 struct hclge_fd_rule *rule; 6612 struct hlist_node *node; 6613 6614 /* Return ok here, because reset error handling will check this 6615 * return value. If error is returned here, the reset process will 6616 * fail. 6617 */ 6618 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6619 return 0; 6620 6621 /* if fd is disabled, should not restore it when reset */ 6622 if (!hdev->fd_en) 6623 return 0; 6624 6625 spin_lock_bh(&hdev->fd_rule_lock); 6626 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6627 if (rule->state == HCLGE_FD_ACTIVE) 6628 rule->state = HCLGE_FD_TO_ADD; 6629 } 6630 spin_unlock_bh(&hdev->fd_rule_lock); 6631 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 6632 6633 return 0; 6634 } 6635 6636 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle, 6637 struct ethtool_rxnfc *cmd) 6638 { 6639 struct hclge_vport *vport = hclge_get_vport(handle); 6640 struct hclge_dev *hdev = vport->back; 6641 6642 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev) || hclge_is_cls_flower_active(handle)) 6643 return -EOPNOTSUPP; 6644 6645 cmd->rule_cnt = hdev->hclge_fd_rule_num; 6646 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6647 6648 return 0; 6649 } 6650 6651 static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule, 6652 struct ethtool_tcpip4_spec *spec, 6653 struct ethtool_tcpip4_spec *spec_mask) 6654 { 6655 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6656 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6657 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6658 6659 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6660 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6661 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6662 6663 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6664 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6665 0 : cpu_to_be16(rule->tuples_mask.src_port); 6666 6667 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6668 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6669 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6670 6671 spec->tos = rule->tuples.ip_tos; 6672 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6673 0 : rule->tuples_mask.ip_tos; 6674 } 6675 6676 static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule, 6677 struct ethtool_usrip4_spec *spec, 6678 struct ethtool_usrip4_spec *spec_mask) 6679 { 6680 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6681 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6682 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6683 6684 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6685 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6686 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6687 6688 spec->tos = rule->tuples.ip_tos; 6689 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6690 0 : rule->tuples_mask.ip_tos; 6691 6692 spec->proto = rule->tuples.ip_proto; 6693 spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6694 0 : rule->tuples_mask.ip_proto; 6695 6696 spec->ip_ver = ETH_RX_NFC_IP4; 6697 } 6698 6699 static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule, 6700 struct ethtool_tcpip6_spec *spec, 6701 struct ethtool_tcpip6_spec *spec_mask) 6702 { 6703 cpu_to_be32_array(spec->ip6src, 6704 rule->tuples.src_ip, IPV6_SIZE); 6705 cpu_to_be32_array(spec->ip6dst, 6706 rule->tuples.dst_ip, IPV6_SIZE); 6707 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6708 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6709 else 6710 cpu_to_be32_array(spec_mask->ip6src, rule->tuples_mask.src_ip, 6711 IPV6_SIZE); 6712 6713 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6714 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6715 else 6716 cpu_to_be32_array(spec_mask->ip6dst, rule->tuples_mask.dst_ip, 6717 IPV6_SIZE); 6718 6719 spec->tclass = rule->tuples.ip_tos; 6720 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6721 0 : rule->tuples_mask.ip_tos; 6722 6723 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6724 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6725 0 : cpu_to_be16(rule->tuples_mask.src_port); 6726 6727 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6728 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6729 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6730 } 6731 6732 static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule, 6733 struct ethtool_usrip6_spec *spec, 6734 struct ethtool_usrip6_spec *spec_mask) 6735 { 6736 cpu_to_be32_array(spec->ip6src, rule->tuples.src_ip, IPV6_SIZE); 6737 cpu_to_be32_array(spec->ip6dst, rule->tuples.dst_ip, IPV6_SIZE); 6738 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6739 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6740 else 6741 cpu_to_be32_array(spec_mask->ip6src, 6742 rule->tuples_mask.src_ip, IPV6_SIZE); 6743 6744 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6745 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6746 else 6747 cpu_to_be32_array(spec_mask->ip6dst, 6748 rule->tuples_mask.dst_ip, IPV6_SIZE); 6749 6750 spec->tclass = rule->tuples.ip_tos; 6751 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6752 0 : rule->tuples_mask.ip_tos; 6753 6754 spec->l4_proto = rule->tuples.ip_proto; 6755 spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6756 0 : rule->tuples_mask.ip_proto; 6757 } 6758 6759 static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule, 6760 struct ethhdr *spec, 6761 struct ethhdr *spec_mask) 6762 { 6763 ether_addr_copy(spec->h_source, rule->tuples.src_mac); 6764 ether_addr_copy(spec->h_dest, rule->tuples.dst_mac); 6765 6766 if (rule->unused_tuple & BIT(INNER_SRC_MAC)) 6767 eth_zero_addr(spec_mask->h_source); 6768 else 6769 ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac); 6770 6771 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6772 eth_zero_addr(spec_mask->h_dest); 6773 else 6774 ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac); 6775 6776 spec->h_proto = cpu_to_be16(rule->tuples.ether_proto); 6777 spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ? 6778 0 : cpu_to_be16(rule->tuples_mask.ether_proto); 6779 } 6780 6781 static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs, 6782 struct hclge_fd_rule *rule) 6783 { 6784 if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) == 6785 HCLGE_FD_TUPLE_USER_DEF_TUPLES) { 6786 fs->h_ext.data[0] = 0; 6787 fs->h_ext.data[1] = 0; 6788 fs->m_ext.data[0] = 0; 6789 fs->m_ext.data[1] = 0; 6790 } else { 6791 fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset); 6792 fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data); 6793 fs->m_ext.data[0] = 6794 cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK); 6795 fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask); 6796 } 6797 } 6798 6799 static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs, 6800 struct hclge_fd_rule *rule) 6801 { 6802 if (fs->flow_type & FLOW_EXT) { 6803 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1); 6804 fs->m_ext.vlan_tci = 6805 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ? 6806 0 : cpu_to_be16(rule->tuples_mask.vlan_tag1); 6807 6808 hclge_fd_get_user_def_info(fs, rule); 6809 } 6810 6811 if (fs->flow_type & FLOW_MAC_EXT) { 6812 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac); 6813 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6814 eth_zero_addr(fs->m_u.ether_spec.h_dest); 6815 else 6816 ether_addr_copy(fs->m_u.ether_spec.h_dest, 6817 rule->tuples_mask.dst_mac); 6818 } 6819 } 6820 6821 static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev, 6822 u16 location) 6823 { 6824 struct hclge_fd_rule *rule = NULL; 6825 struct hlist_node *node2; 6826 6827 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) { 6828 if (rule->location == location) 6829 return rule; 6830 else if (rule->location > location) 6831 return NULL; 6832 } 6833 6834 return NULL; 6835 } 6836 6837 static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs, 6838 struct hclge_fd_rule *rule) 6839 { 6840 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 6841 fs->ring_cookie = RX_CLS_FLOW_DISC; 6842 } else { 6843 u64 vf_id; 6844 6845 fs->ring_cookie = rule->queue_id; 6846 vf_id = rule->vf_id; 6847 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 6848 fs->ring_cookie |= vf_id; 6849 } 6850 } 6851 6852 static int hclge_get_fd_rule_info(struct hnae3_handle *handle, 6853 struct ethtool_rxnfc *cmd) 6854 { 6855 struct hclge_vport *vport = hclge_get_vport(handle); 6856 struct hclge_fd_rule *rule = NULL; 6857 struct hclge_dev *hdev = vport->back; 6858 struct ethtool_rx_flow_spec *fs; 6859 6860 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6861 return -EOPNOTSUPP; 6862 6863 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6864 6865 spin_lock_bh(&hdev->fd_rule_lock); 6866 6867 rule = hclge_get_fd_rule(hdev, fs->location); 6868 if (!rule) { 6869 spin_unlock_bh(&hdev->fd_rule_lock); 6870 return -ENOENT; 6871 } 6872 6873 fs->flow_type = rule->flow_type; 6874 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 6875 case SCTP_V4_FLOW: 6876 case TCP_V4_FLOW: 6877 case UDP_V4_FLOW: 6878 hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec, 6879 &fs->m_u.tcp_ip4_spec); 6880 break; 6881 case IP_USER_FLOW: 6882 hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec, 6883 &fs->m_u.usr_ip4_spec); 6884 break; 6885 case SCTP_V6_FLOW: 6886 case TCP_V6_FLOW: 6887 case UDP_V6_FLOW: 6888 hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec, 6889 &fs->m_u.tcp_ip6_spec); 6890 break; 6891 case IPV6_USER_FLOW: 6892 hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec, 6893 &fs->m_u.usr_ip6_spec); 6894 break; 6895 /* The flow type of fd rule has been checked before adding in to rule 6896 * list. As other flow types have been handled, it must be ETHER_FLOW 6897 * for the default case 6898 */ 6899 default: 6900 hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec, 6901 &fs->m_u.ether_spec); 6902 break; 6903 } 6904 6905 hclge_fd_get_ext_info(fs, rule); 6906 6907 hclge_fd_get_ring_cookie(fs, rule); 6908 6909 spin_unlock_bh(&hdev->fd_rule_lock); 6910 6911 return 0; 6912 } 6913 6914 static int hclge_get_all_rules(struct hnae3_handle *handle, 6915 struct ethtool_rxnfc *cmd, u32 *rule_locs) 6916 { 6917 struct hclge_vport *vport = hclge_get_vport(handle); 6918 struct hclge_dev *hdev = vport->back; 6919 struct hclge_fd_rule *rule; 6920 struct hlist_node *node2; 6921 int cnt = 0; 6922 6923 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6924 return -EOPNOTSUPP; 6925 6926 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6927 6928 spin_lock_bh(&hdev->fd_rule_lock); 6929 hlist_for_each_entry_safe(rule, node2, 6930 &hdev->fd_rule_list, rule_node) { 6931 if (cnt == cmd->rule_cnt) { 6932 spin_unlock_bh(&hdev->fd_rule_lock); 6933 return -EMSGSIZE; 6934 } 6935 6936 if (rule->state == HCLGE_FD_TO_DEL) 6937 continue; 6938 6939 rule_locs[cnt] = rule->location; 6940 cnt++; 6941 } 6942 6943 spin_unlock_bh(&hdev->fd_rule_lock); 6944 6945 cmd->rule_cnt = cnt; 6946 6947 return 0; 6948 } 6949 6950 static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys, 6951 struct hclge_fd_rule_tuples *tuples) 6952 { 6953 #define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32 6954 #define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32 6955 6956 tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto); 6957 tuples->ip_proto = fkeys->basic.ip_proto; 6958 tuples->dst_port = be16_to_cpu(fkeys->ports.dst); 6959 6960 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 6961 tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src); 6962 tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst); 6963 } else { 6964 int i; 6965 6966 for (i = 0; i < IPV6_SIZE; i++) { 6967 tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]); 6968 tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]); 6969 } 6970 } 6971 } 6972 6973 /* traverse all rules, check whether an existed rule has the same tuples */ 6974 static struct hclge_fd_rule * 6975 hclge_fd_search_flow_keys(struct hclge_dev *hdev, 6976 const struct hclge_fd_rule_tuples *tuples) 6977 { 6978 struct hclge_fd_rule *rule = NULL; 6979 struct hlist_node *node; 6980 6981 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6982 if (!memcmp(tuples, &rule->tuples, sizeof(*tuples))) 6983 return rule; 6984 } 6985 6986 return NULL; 6987 } 6988 6989 static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples, 6990 struct hclge_fd_rule *rule) 6991 { 6992 rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 6993 BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) | 6994 BIT(INNER_SRC_PORT); 6995 rule->action = 0; 6996 rule->vf_id = 0; 6997 rule->rule_type = HCLGE_FD_ARFS_ACTIVE; 6998 rule->state = HCLGE_FD_TO_ADD; 6999 if (tuples->ether_proto == ETH_P_IP) { 7000 if (tuples->ip_proto == IPPROTO_TCP) 7001 rule->flow_type = TCP_V4_FLOW; 7002 else 7003 rule->flow_type = UDP_V4_FLOW; 7004 } else { 7005 if (tuples->ip_proto == IPPROTO_TCP) 7006 rule->flow_type = TCP_V6_FLOW; 7007 else 7008 rule->flow_type = UDP_V6_FLOW; 7009 } 7010 memcpy(&rule->tuples, tuples, sizeof(rule->tuples)); 7011 memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask)); 7012 } 7013 7014 static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id, 7015 u16 flow_id, struct flow_keys *fkeys) 7016 { 7017 struct hclge_vport *vport = hclge_get_vport(handle); 7018 struct hclge_fd_rule_tuples new_tuples = {}; 7019 struct hclge_dev *hdev = vport->back; 7020 struct hclge_fd_rule *rule; 7021 u16 bit_id; 7022 7023 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7024 return -EOPNOTSUPP; 7025 7026 /* when there is already fd rule existed add by user, 7027 * arfs should not work 7028 */ 7029 spin_lock_bh(&hdev->fd_rule_lock); 7030 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE && 7031 hdev->fd_active_type != HCLGE_FD_RULE_NONE) { 7032 spin_unlock_bh(&hdev->fd_rule_lock); 7033 return -EOPNOTSUPP; 7034 } 7035 7036 hclge_fd_get_flow_tuples(fkeys, &new_tuples); 7037 7038 /* check is there flow director filter existed for this flow, 7039 * if not, create a new filter for it; 7040 * if filter exist with different queue id, modify the filter; 7041 * if filter exist with same queue id, do nothing 7042 */ 7043 rule = hclge_fd_search_flow_keys(hdev, &new_tuples); 7044 if (!rule) { 7045 bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM); 7046 if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7047 spin_unlock_bh(&hdev->fd_rule_lock); 7048 return -ENOSPC; 7049 } 7050 7051 rule = kzalloc(sizeof(*rule), GFP_ATOMIC); 7052 if (!rule) { 7053 spin_unlock_bh(&hdev->fd_rule_lock); 7054 return -ENOMEM; 7055 } 7056 7057 rule->location = bit_id; 7058 rule->arfs.flow_id = flow_id; 7059 rule->queue_id = queue_id; 7060 hclge_fd_build_arfs_rule(&new_tuples, rule); 7061 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 7062 hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE; 7063 } else if (rule->queue_id != queue_id) { 7064 rule->queue_id = queue_id; 7065 rule->state = HCLGE_FD_TO_ADD; 7066 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7067 hclge_task_schedule(hdev, 0); 7068 } 7069 spin_unlock_bh(&hdev->fd_rule_lock); 7070 return rule->location; 7071 } 7072 7073 static void hclge_rfs_filter_expire(struct hclge_dev *hdev) 7074 { 7075 #ifdef CONFIG_RFS_ACCEL 7076 struct hnae3_handle *handle = &hdev->vport[0].nic; 7077 struct hclge_fd_rule *rule; 7078 struct hlist_node *node; 7079 7080 spin_lock_bh(&hdev->fd_rule_lock); 7081 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) { 7082 spin_unlock_bh(&hdev->fd_rule_lock); 7083 return; 7084 } 7085 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7086 if (rule->state != HCLGE_FD_ACTIVE) 7087 continue; 7088 if (rps_may_expire_flow(handle->netdev, rule->queue_id, 7089 rule->arfs.flow_id, rule->location)) { 7090 rule->state = HCLGE_FD_TO_DEL; 7091 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7092 } 7093 } 7094 spin_unlock_bh(&hdev->fd_rule_lock); 7095 #endif 7096 } 7097 7098 /* make sure being called after lock up with fd_rule_lock */ 7099 static int hclge_clear_arfs_rules(struct hclge_dev *hdev) 7100 { 7101 #ifdef CONFIG_RFS_ACCEL 7102 struct hclge_fd_rule *rule; 7103 struct hlist_node *node; 7104 int ret; 7105 7106 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) 7107 return 0; 7108 7109 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7110 switch (rule->state) { 7111 case HCLGE_FD_TO_DEL: 7112 case HCLGE_FD_ACTIVE: 7113 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7114 rule->location, NULL, false); 7115 if (ret) 7116 return ret; 7117 fallthrough; 7118 case HCLGE_FD_TO_ADD: 7119 hclge_fd_dec_rule_cnt(hdev, rule->location); 7120 hlist_del(&rule->rule_node); 7121 kfree(rule); 7122 break; 7123 default: 7124 break; 7125 } 7126 } 7127 hclge_sync_fd_state(hdev); 7128 7129 #endif 7130 return 0; 7131 } 7132 7133 static void hclge_get_cls_key_basic(const struct flow_rule *flow, 7134 struct hclge_fd_rule *rule) 7135 { 7136 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) { 7137 struct flow_match_basic match; 7138 u16 ethtype_key, ethtype_mask; 7139 7140 flow_rule_match_basic(flow, &match); 7141 ethtype_key = ntohs(match.key->n_proto); 7142 ethtype_mask = ntohs(match.mask->n_proto); 7143 7144 if (ethtype_key == ETH_P_ALL) { 7145 ethtype_key = 0; 7146 ethtype_mask = 0; 7147 } 7148 rule->tuples.ether_proto = ethtype_key; 7149 rule->tuples_mask.ether_proto = ethtype_mask; 7150 rule->tuples.ip_proto = match.key->ip_proto; 7151 rule->tuples_mask.ip_proto = match.mask->ip_proto; 7152 } else { 7153 rule->unused_tuple |= BIT(INNER_IP_PROTO); 7154 rule->unused_tuple |= BIT(INNER_ETH_TYPE); 7155 } 7156 } 7157 7158 static void hclge_get_cls_key_mac(const struct flow_rule *flow, 7159 struct hclge_fd_rule *rule) 7160 { 7161 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 7162 struct flow_match_eth_addrs match; 7163 7164 flow_rule_match_eth_addrs(flow, &match); 7165 ether_addr_copy(rule->tuples.dst_mac, match.key->dst); 7166 ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst); 7167 ether_addr_copy(rule->tuples.src_mac, match.key->src); 7168 ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src); 7169 } else { 7170 rule->unused_tuple |= BIT(INNER_DST_MAC); 7171 rule->unused_tuple |= BIT(INNER_SRC_MAC); 7172 } 7173 } 7174 7175 static void hclge_get_cls_key_vlan(const struct flow_rule *flow, 7176 struct hclge_fd_rule *rule) 7177 { 7178 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) { 7179 struct flow_match_vlan match; 7180 7181 flow_rule_match_vlan(flow, &match); 7182 rule->tuples.vlan_tag1 = match.key->vlan_id | 7183 (match.key->vlan_priority << VLAN_PRIO_SHIFT); 7184 rule->tuples_mask.vlan_tag1 = match.mask->vlan_id | 7185 (match.mask->vlan_priority << VLAN_PRIO_SHIFT); 7186 } else { 7187 rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST); 7188 } 7189 } 7190 7191 static void hclge_get_cls_key_ip(const struct flow_rule *flow, 7192 struct hclge_fd_rule *rule) 7193 { 7194 u16 addr_type = 0; 7195 7196 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) { 7197 struct flow_match_control match; 7198 7199 flow_rule_match_control(flow, &match); 7200 addr_type = match.key->addr_type; 7201 } 7202 7203 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { 7204 struct flow_match_ipv4_addrs match; 7205 7206 flow_rule_match_ipv4_addrs(flow, &match); 7207 rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src); 7208 rule->tuples_mask.src_ip[IPV4_INDEX] = 7209 be32_to_cpu(match.mask->src); 7210 rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst); 7211 rule->tuples_mask.dst_ip[IPV4_INDEX] = 7212 be32_to_cpu(match.mask->dst); 7213 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { 7214 struct flow_match_ipv6_addrs match; 7215 7216 flow_rule_match_ipv6_addrs(flow, &match); 7217 be32_to_cpu_array(rule->tuples.src_ip, match.key->src.s6_addr32, 7218 IPV6_SIZE); 7219 be32_to_cpu_array(rule->tuples_mask.src_ip, 7220 match.mask->src.s6_addr32, IPV6_SIZE); 7221 be32_to_cpu_array(rule->tuples.dst_ip, match.key->dst.s6_addr32, 7222 IPV6_SIZE); 7223 be32_to_cpu_array(rule->tuples_mask.dst_ip, 7224 match.mask->dst.s6_addr32, IPV6_SIZE); 7225 } else { 7226 rule->unused_tuple |= BIT(INNER_SRC_IP); 7227 rule->unused_tuple |= BIT(INNER_DST_IP); 7228 } 7229 } 7230 7231 static void hclge_get_cls_key_port(const struct flow_rule *flow, 7232 struct hclge_fd_rule *rule) 7233 { 7234 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) { 7235 struct flow_match_ports match; 7236 7237 flow_rule_match_ports(flow, &match); 7238 7239 rule->tuples.src_port = be16_to_cpu(match.key->src); 7240 rule->tuples_mask.src_port = be16_to_cpu(match.mask->src); 7241 rule->tuples.dst_port = be16_to_cpu(match.key->dst); 7242 rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst); 7243 } else { 7244 rule->unused_tuple |= BIT(INNER_SRC_PORT); 7245 rule->unused_tuple |= BIT(INNER_DST_PORT); 7246 } 7247 } 7248 7249 static int hclge_parse_cls_flower(struct hclge_dev *hdev, 7250 struct flow_cls_offload *cls_flower, 7251 struct hclge_fd_rule *rule) 7252 { 7253 struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower); 7254 struct flow_dissector *dissector = flow->match.dissector; 7255 7256 if (dissector->used_keys & 7257 ~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 7258 BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 7259 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 7260 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) | 7261 BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | 7262 BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | 7263 BIT_ULL(FLOW_DISSECTOR_KEY_PORTS))) { 7264 dev_err(&hdev->pdev->dev, "unsupported key set: %#llx\n", 7265 dissector->used_keys); 7266 return -EOPNOTSUPP; 7267 } 7268 7269 hclge_get_cls_key_basic(flow, rule); 7270 hclge_get_cls_key_mac(flow, rule); 7271 hclge_get_cls_key_vlan(flow, rule); 7272 hclge_get_cls_key_ip(flow, rule); 7273 hclge_get_cls_key_port(flow, rule); 7274 7275 return 0; 7276 } 7277 7278 static int hclge_check_cls_flower(struct hclge_dev *hdev, 7279 struct flow_cls_offload *cls_flower, int tc) 7280 { 7281 u32 prio = cls_flower->common.prio; 7282 7283 if (tc < 0 || tc > hdev->tc_max) { 7284 dev_err(&hdev->pdev->dev, "invalid traffic class\n"); 7285 return -EINVAL; 7286 } 7287 7288 if (prio == 0 || 7289 prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7290 dev_err(&hdev->pdev->dev, 7291 "prio %u should be in range[1, %u]\n", 7292 prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 7293 return -EINVAL; 7294 } 7295 7296 if (test_bit(prio - 1, hdev->fd_bmap)) { 7297 dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio); 7298 return -EINVAL; 7299 } 7300 return 0; 7301 } 7302 7303 static int hclge_add_cls_flower(struct hnae3_handle *handle, 7304 struct flow_cls_offload *cls_flower, 7305 int tc) 7306 { 7307 struct hclge_vport *vport = hclge_get_vport(handle); 7308 struct hclge_dev *hdev = vport->back; 7309 struct hclge_fd_rule *rule; 7310 int ret; 7311 7312 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 7313 dev_err(&hdev->pdev->dev, 7314 "cls flower is not supported\n"); 7315 return -EOPNOTSUPP; 7316 } 7317 7318 ret = hclge_check_cls_flower(hdev, cls_flower, tc); 7319 if (ret) { 7320 dev_err(&hdev->pdev->dev, 7321 "failed to check cls flower params, ret = %d\n", ret); 7322 return ret; 7323 } 7324 7325 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 7326 if (!rule) 7327 return -ENOMEM; 7328 7329 ret = hclge_parse_cls_flower(hdev, cls_flower, rule); 7330 if (ret) { 7331 kfree(rule); 7332 return ret; 7333 } 7334 7335 rule->action = HCLGE_FD_ACTION_SELECT_TC; 7336 rule->cls_flower.tc = tc; 7337 rule->location = cls_flower->common.prio - 1; 7338 rule->vf_id = 0; 7339 rule->cls_flower.cookie = cls_flower->cookie; 7340 rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE; 7341 7342 ret = hclge_add_fd_entry_common(hdev, rule); 7343 if (ret) 7344 kfree(rule); 7345 7346 return ret; 7347 } 7348 7349 static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev, 7350 unsigned long cookie) 7351 { 7352 struct hclge_fd_rule *rule; 7353 struct hlist_node *node; 7354 7355 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7356 if (rule->cls_flower.cookie == cookie) 7357 return rule; 7358 } 7359 7360 return NULL; 7361 } 7362 7363 static int hclge_del_cls_flower(struct hnae3_handle *handle, 7364 struct flow_cls_offload *cls_flower) 7365 { 7366 struct hclge_vport *vport = hclge_get_vport(handle); 7367 struct hclge_dev *hdev = vport->back; 7368 struct hclge_fd_rule *rule; 7369 int ret; 7370 7371 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7372 return -EOPNOTSUPP; 7373 7374 spin_lock_bh(&hdev->fd_rule_lock); 7375 7376 rule = hclge_find_cls_flower(hdev, cls_flower->cookie); 7377 if (!rule) { 7378 spin_unlock_bh(&hdev->fd_rule_lock); 7379 return -EINVAL; 7380 } 7381 7382 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location, 7383 NULL, false); 7384 if (ret) { 7385 /* if tcam config fail, set rule state to TO_DEL, 7386 * so the rule will be deleted when periodic 7387 * task being scheduled. 7388 */ 7389 hclge_update_fd_list(hdev, HCLGE_FD_TO_DEL, rule->location, NULL); 7390 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7391 spin_unlock_bh(&hdev->fd_rule_lock); 7392 return ret; 7393 } 7394 7395 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL); 7396 spin_unlock_bh(&hdev->fd_rule_lock); 7397 7398 return 0; 7399 } 7400 7401 static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist) 7402 { 7403 struct hclge_fd_rule *rule; 7404 struct hlist_node *node; 7405 int ret = 0; 7406 7407 if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state)) 7408 return; 7409 7410 spin_lock_bh(&hdev->fd_rule_lock); 7411 7412 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 7413 switch (rule->state) { 7414 case HCLGE_FD_TO_ADD: 7415 ret = hclge_fd_config_rule(hdev, rule); 7416 if (ret) 7417 goto out; 7418 rule->state = HCLGE_FD_ACTIVE; 7419 break; 7420 case HCLGE_FD_TO_DEL: 7421 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7422 rule->location, NULL, false); 7423 if (ret) 7424 goto out; 7425 hclge_fd_dec_rule_cnt(hdev, rule->location); 7426 hclge_fd_free_node(hdev, rule); 7427 break; 7428 default: 7429 break; 7430 } 7431 } 7432 7433 out: 7434 if (ret) 7435 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7436 7437 spin_unlock_bh(&hdev->fd_rule_lock); 7438 } 7439 7440 static void hclge_sync_fd_table(struct hclge_dev *hdev) 7441 { 7442 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7443 return; 7444 7445 if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) { 7446 bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE; 7447 7448 hclge_clear_fd_rules_in_list(hdev, clear_list); 7449 } 7450 7451 hclge_sync_fd_user_def_cfg(hdev, false); 7452 7453 hclge_sync_fd_list(hdev, &hdev->fd_rule_list); 7454 } 7455 7456 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle) 7457 { 7458 struct hclge_vport *vport = hclge_get_vport(handle); 7459 struct hclge_dev *hdev = vport->back; 7460 7461 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) || 7462 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING); 7463 } 7464 7465 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle) 7466 { 7467 struct hclge_vport *vport = hclge_get_vport(handle); 7468 struct hclge_dev *hdev = vport->back; 7469 7470 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 7471 } 7472 7473 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle) 7474 { 7475 struct hclge_vport *vport = hclge_get_vport(handle); 7476 struct hclge_dev *hdev = vport->back; 7477 7478 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 7479 } 7480 7481 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle) 7482 { 7483 struct hclge_vport *vport = hclge_get_vport(handle); 7484 struct hclge_dev *hdev = vport->back; 7485 7486 return hdev->rst_stats.hw_reset_done_cnt; 7487 } 7488 7489 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable) 7490 { 7491 struct hclge_vport *vport = hclge_get_vport(handle); 7492 struct hclge_dev *hdev = vport->back; 7493 7494 hdev->fd_en = enable; 7495 7496 if (!enable) 7497 set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state); 7498 else 7499 hclge_restore_fd_entries(handle); 7500 7501 hclge_task_schedule(hdev, 0); 7502 } 7503 7504 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 7505 { 7506 #define HCLGE_LINK_STATUS_WAIT_CNT 3 7507 7508 struct hclge_desc desc; 7509 struct hclge_config_mac_mode_cmd *req = 7510 (struct hclge_config_mac_mode_cmd *)desc.data; 7511 u32 loop_en = 0; 7512 int ret; 7513 7514 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 7515 7516 if (enable) { 7517 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U); 7518 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U); 7519 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U); 7520 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U); 7521 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U); 7522 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U); 7523 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U); 7524 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U); 7525 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U); 7526 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U); 7527 } 7528 7529 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7530 7531 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7532 if (ret) { 7533 dev_err(&hdev->pdev->dev, 7534 "mac enable fail, ret =%d.\n", ret); 7535 return; 7536 } 7537 7538 if (!enable) 7539 hclge_mac_link_status_wait(hdev, HCLGE_LINK_STATUS_DOWN, 7540 HCLGE_LINK_STATUS_WAIT_CNT); 7541 } 7542 7543 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid, 7544 u8 switch_param, u8 param_mask) 7545 { 7546 struct hclge_mac_vlan_switch_cmd *req; 7547 struct hclge_desc desc; 7548 u32 func_id; 7549 int ret; 7550 7551 func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0); 7552 req = (struct hclge_mac_vlan_switch_cmd *)desc.data; 7553 7554 /* read current config parameter */ 7555 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM, 7556 true); 7557 req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL; 7558 req->func_id = cpu_to_le32(func_id); 7559 7560 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7561 if (ret) { 7562 dev_err(&hdev->pdev->dev, 7563 "read mac vlan switch parameter fail, ret = %d\n", ret); 7564 return ret; 7565 } 7566 7567 /* modify and write new config parameter */ 7568 hclge_comm_cmd_reuse_desc(&desc, false); 7569 req->switch_param = (req->switch_param & param_mask) | switch_param; 7570 req->param_mask = param_mask; 7571 7572 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7573 if (ret) 7574 dev_err(&hdev->pdev->dev, 7575 "set mac vlan switch parameter fail, ret = %d\n", ret); 7576 return ret; 7577 } 7578 7579 static void hclge_phy_link_status_wait(struct hclge_dev *hdev, 7580 int link_ret) 7581 { 7582 #define HCLGE_PHY_LINK_STATUS_NUM 200 7583 7584 struct phy_device *phydev = hdev->hw.mac.phydev; 7585 int i = 0; 7586 int ret; 7587 7588 do { 7589 ret = phy_read_status(phydev); 7590 if (ret) { 7591 dev_err(&hdev->pdev->dev, 7592 "phy update link status fail, ret = %d\n", ret); 7593 return; 7594 } 7595 7596 if (phydev->link == link_ret) 7597 break; 7598 7599 msleep(HCLGE_LINK_STATUS_MS); 7600 } while (++i < HCLGE_PHY_LINK_STATUS_NUM); 7601 } 7602 7603 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 7604 int wait_cnt) 7605 { 7606 int link_status; 7607 int i = 0; 7608 int ret; 7609 7610 do { 7611 ret = hclge_get_mac_link_status(hdev, &link_status); 7612 if (ret) 7613 return ret; 7614 if (link_status == link_ret) 7615 return 0; 7616 7617 msleep(HCLGE_LINK_STATUS_MS); 7618 } while (++i < wait_cnt); 7619 return -EBUSY; 7620 } 7621 7622 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en, 7623 bool is_phy) 7624 { 7625 #define HCLGE_MAC_LINK_STATUS_NUM 100 7626 7627 int link_ret; 7628 7629 link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 7630 7631 if (is_phy) 7632 hclge_phy_link_status_wait(hdev, link_ret); 7633 7634 return hclge_mac_link_status_wait(hdev, link_ret, 7635 HCLGE_MAC_LINK_STATUS_NUM); 7636 } 7637 7638 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) 7639 { 7640 struct hclge_config_mac_mode_cmd *req; 7641 struct hclge_desc desc; 7642 u32 loop_en; 7643 int ret; 7644 7645 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 7646 /* 1 Read out the MAC mode config at first */ 7647 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 7648 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7649 if (ret) { 7650 dev_err(&hdev->pdev->dev, 7651 "mac loopback get fail, ret =%d.\n", ret); 7652 return ret; 7653 } 7654 7655 /* 2 Then setup the loopback flag */ 7656 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 7657 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 7658 7659 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7660 7661 /* 3 Config mac work mode with loopback flag 7662 * and its original configure parameters 7663 */ 7664 hclge_comm_cmd_reuse_desc(&desc, false); 7665 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7666 if (ret) 7667 dev_err(&hdev->pdev->dev, 7668 "mac loopback set fail, ret =%d.\n", ret); 7669 return ret; 7670 } 7671 7672 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en, 7673 enum hnae3_loop loop_mode) 7674 { 7675 struct hclge_common_lb_cmd *req; 7676 struct hclge_desc desc; 7677 u8 loop_mode_b; 7678 int ret; 7679 7680 req = (struct hclge_common_lb_cmd *)desc.data; 7681 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false); 7682 7683 switch (loop_mode) { 7684 case HNAE3_LOOP_SERIAL_SERDES: 7685 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 7686 break; 7687 case HNAE3_LOOP_PARALLEL_SERDES: 7688 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B; 7689 break; 7690 case HNAE3_LOOP_PHY: 7691 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B; 7692 break; 7693 default: 7694 dev_err(&hdev->pdev->dev, 7695 "unsupported loopback mode %d\n", loop_mode); 7696 return -ENOTSUPP; 7697 } 7698 7699 req->mask = loop_mode_b; 7700 if (en) 7701 req->enable = loop_mode_b; 7702 7703 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7704 if (ret) 7705 dev_err(&hdev->pdev->dev, 7706 "failed to send loopback cmd, loop_mode = %d, ret = %d\n", 7707 loop_mode, ret); 7708 7709 return ret; 7710 } 7711 7712 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev) 7713 { 7714 #define HCLGE_COMMON_LB_RETRY_MS 10 7715 #define HCLGE_COMMON_LB_RETRY_NUM 100 7716 7717 struct hclge_common_lb_cmd *req; 7718 struct hclge_desc desc; 7719 u32 i = 0; 7720 int ret; 7721 7722 req = (struct hclge_common_lb_cmd *)desc.data; 7723 7724 do { 7725 msleep(HCLGE_COMMON_LB_RETRY_MS); 7726 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, 7727 true); 7728 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7729 if (ret) { 7730 dev_err(&hdev->pdev->dev, 7731 "failed to get loopback done status, ret = %d\n", 7732 ret); 7733 return ret; 7734 } 7735 } while (++i < HCLGE_COMMON_LB_RETRY_NUM && 7736 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B)); 7737 7738 if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) { 7739 dev_err(&hdev->pdev->dev, "wait loopback timeout\n"); 7740 return -EBUSY; 7741 } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) { 7742 dev_err(&hdev->pdev->dev, "failed to do loopback test\n"); 7743 return -EIO; 7744 } 7745 7746 return 0; 7747 } 7748 7749 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en, 7750 enum hnae3_loop loop_mode) 7751 { 7752 int ret; 7753 7754 ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode); 7755 if (ret) 7756 return ret; 7757 7758 return hclge_cfg_common_loopback_wait(hdev); 7759 } 7760 7761 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en, 7762 enum hnae3_loop loop_mode) 7763 { 7764 int ret; 7765 7766 ret = hclge_cfg_common_loopback(hdev, en, loop_mode); 7767 if (ret) 7768 return ret; 7769 7770 hclge_cfg_mac_mode(hdev, en); 7771 7772 ret = hclge_mac_phy_link_status_wait(hdev, en, false); 7773 if (ret) 7774 dev_err(&hdev->pdev->dev, 7775 "serdes loopback config mac mode timeout\n"); 7776 7777 return ret; 7778 } 7779 7780 static int hclge_enable_phy_loopback(struct hclge_dev *hdev, 7781 struct phy_device *phydev) 7782 { 7783 int ret; 7784 7785 if (!phydev->suspended) { 7786 ret = phy_suspend(phydev); 7787 if (ret) 7788 return ret; 7789 } 7790 7791 ret = phy_resume(phydev); 7792 if (ret) 7793 return ret; 7794 7795 return phy_loopback(phydev, true); 7796 } 7797 7798 static int hclge_disable_phy_loopback(struct hclge_dev *hdev, 7799 struct phy_device *phydev) 7800 { 7801 int ret; 7802 7803 ret = phy_loopback(phydev, false); 7804 if (ret) 7805 return ret; 7806 7807 return phy_suspend(phydev); 7808 } 7809 7810 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en) 7811 { 7812 struct phy_device *phydev = hdev->hw.mac.phydev; 7813 int ret; 7814 7815 if (!phydev) { 7816 if (hnae3_dev_phy_imp_supported(hdev)) 7817 return hclge_set_common_loopback(hdev, en, 7818 HNAE3_LOOP_PHY); 7819 return -ENOTSUPP; 7820 } 7821 7822 if (en) 7823 ret = hclge_enable_phy_loopback(hdev, phydev); 7824 else 7825 ret = hclge_disable_phy_loopback(hdev, phydev); 7826 if (ret) { 7827 dev_err(&hdev->pdev->dev, 7828 "set phy loopback fail, ret = %d\n", ret); 7829 return ret; 7830 } 7831 7832 hclge_cfg_mac_mode(hdev, en); 7833 7834 ret = hclge_mac_phy_link_status_wait(hdev, en, true); 7835 if (ret) 7836 dev_err(&hdev->pdev->dev, 7837 "phy loopback config mac mode timeout\n"); 7838 7839 return ret; 7840 } 7841 7842 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id, 7843 u16 stream_id, bool enable) 7844 { 7845 struct hclge_desc desc; 7846 struct hclge_cfg_com_tqp_queue_cmd *req = 7847 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 7848 7849 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 7850 req->tqp_id = cpu_to_le16(tqp_id); 7851 req->stream_id = cpu_to_le16(stream_id); 7852 if (enable) 7853 req->enable |= 1U << HCLGE_TQP_ENABLE_B; 7854 7855 return hclge_cmd_send(&hdev->hw, &desc, 1); 7856 } 7857 7858 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable) 7859 { 7860 struct hclge_vport *vport = hclge_get_vport(handle); 7861 struct hclge_dev *hdev = vport->back; 7862 int ret; 7863 u16 i; 7864 7865 for (i = 0; i < handle->kinfo.num_tqps; i++) { 7866 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable); 7867 if (ret) 7868 return ret; 7869 } 7870 return 0; 7871 } 7872 7873 static int hclge_set_loopback(struct hnae3_handle *handle, 7874 enum hnae3_loop loop_mode, bool en) 7875 { 7876 struct hclge_vport *vport = hclge_get_vport(handle); 7877 struct hclge_dev *hdev = vport->back; 7878 int ret = 0; 7879 7880 /* Loopback can be enabled in three places: SSU, MAC, and serdes. By 7881 * default, SSU loopback is enabled, so if the SMAC and the DMAC are 7882 * the same, the packets are looped back in the SSU. If SSU loopback 7883 * is disabled, packets can reach MAC even if SMAC is the same as DMAC. 7884 */ 7885 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 7886 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B); 7887 7888 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param, 7889 HCLGE_SWITCH_ALW_LPBK_MASK); 7890 if (ret) 7891 return ret; 7892 } 7893 7894 switch (loop_mode) { 7895 case HNAE3_LOOP_APP: 7896 ret = hclge_set_app_loopback(hdev, en); 7897 break; 7898 case HNAE3_LOOP_SERIAL_SERDES: 7899 case HNAE3_LOOP_PARALLEL_SERDES: 7900 ret = hclge_set_common_loopback(hdev, en, loop_mode); 7901 break; 7902 case HNAE3_LOOP_PHY: 7903 ret = hclge_set_phy_loopback(hdev, en); 7904 break; 7905 case HNAE3_LOOP_EXTERNAL: 7906 break; 7907 default: 7908 ret = -ENOTSUPP; 7909 dev_err(&hdev->pdev->dev, 7910 "loop_mode %d is not supported\n", loop_mode); 7911 break; 7912 } 7913 7914 if (ret) 7915 return ret; 7916 7917 ret = hclge_tqp_enable(handle, en); 7918 if (ret) 7919 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n", 7920 en ? "enable" : "disable", ret); 7921 7922 return ret; 7923 } 7924 7925 static int hclge_set_default_loopback(struct hclge_dev *hdev) 7926 { 7927 int ret; 7928 7929 ret = hclge_set_app_loopback(hdev, false); 7930 if (ret) 7931 return ret; 7932 7933 ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES); 7934 if (ret) 7935 return ret; 7936 7937 return hclge_cfg_common_loopback(hdev, false, 7938 HNAE3_LOOP_PARALLEL_SERDES); 7939 } 7940 7941 static void hclge_flush_link_update(struct hclge_dev *hdev) 7942 { 7943 #define HCLGE_FLUSH_LINK_TIMEOUT 100000 7944 7945 unsigned long last = hdev->serv_processed_cnt; 7946 int i = 0; 7947 7948 while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) && 7949 i++ < HCLGE_FLUSH_LINK_TIMEOUT && 7950 last == hdev->serv_processed_cnt) 7951 usleep_range(1, 1); 7952 } 7953 7954 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable) 7955 { 7956 struct hclge_vport *vport = hclge_get_vport(handle); 7957 struct hclge_dev *hdev = vport->back; 7958 7959 if (enable) { 7960 hclge_task_schedule(hdev, 0); 7961 } else { 7962 /* Set the DOWN flag here to disable link updating */ 7963 set_bit(HCLGE_STATE_DOWN, &hdev->state); 7964 7965 smp_mb__after_atomic(); /* flush memory to make sure DOWN is seen by service task */ 7966 hclge_flush_link_update(hdev); 7967 } 7968 } 7969 7970 static int hclge_ae_start(struct hnae3_handle *handle) 7971 { 7972 struct hclge_vport *vport = hclge_get_vport(handle); 7973 struct hclge_dev *hdev = vport->back; 7974 7975 /* mac enable */ 7976 hclge_cfg_mac_mode(hdev, true); 7977 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 7978 hdev->hw.mac.link = 0; 7979 7980 /* reset tqp stats */ 7981 hclge_comm_reset_tqp_stats(handle); 7982 7983 hclge_mac_start_phy(hdev); 7984 7985 return 0; 7986 } 7987 7988 static void hclge_ae_stop(struct hnae3_handle *handle) 7989 { 7990 struct hclge_vport *vport = hclge_get_vport(handle); 7991 struct hclge_dev *hdev = vport->back; 7992 7993 set_bit(HCLGE_STATE_DOWN, &hdev->state); 7994 spin_lock_bh(&hdev->fd_rule_lock); 7995 hclge_clear_arfs_rules(hdev); 7996 spin_unlock_bh(&hdev->fd_rule_lock); 7997 7998 /* If it is not PF reset or FLR, the firmware will disable the MAC, 7999 * so it only need to stop phy here. 8000 */ 8001 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { 8002 hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE, 8003 HCLGE_PFC_DISABLE); 8004 if (hdev->reset_type != HNAE3_FUNC_RESET && 8005 hdev->reset_type != HNAE3_FLR_RESET) { 8006 hclge_mac_stop_phy(hdev); 8007 hclge_update_link_status(hdev); 8008 return; 8009 } 8010 } 8011 8012 hclge_reset_tqp(handle); 8013 8014 hclge_config_mac_tnl_int(hdev, false); 8015 8016 /* Mac disable */ 8017 hclge_cfg_mac_mode(hdev, false); 8018 8019 hclge_mac_stop_phy(hdev); 8020 8021 /* reset tqp stats */ 8022 hclge_comm_reset_tqp_stats(handle); 8023 hclge_update_link_status(hdev); 8024 } 8025 8026 int hclge_vport_start(struct hclge_vport *vport) 8027 { 8028 struct hclge_dev *hdev = vport->back; 8029 8030 set_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8031 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8032 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 8033 vport->last_active_jiffies = jiffies; 8034 vport->need_notify = 0; 8035 8036 if (test_bit(vport->vport_id, hdev->vport_config_block)) { 8037 if (vport->vport_id) { 8038 hclge_restore_mac_table_common(vport); 8039 hclge_restore_vport_vlan_table(vport); 8040 } else { 8041 hclge_restore_hw_table(hdev); 8042 } 8043 } 8044 8045 clear_bit(vport->vport_id, hdev->vport_config_block); 8046 8047 return 0; 8048 } 8049 8050 void hclge_vport_stop(struct hclge_vport *vport) 8051 { 8052 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8053 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8054 vport->need_notify = 0; 8055 } 8056 8057 static int hclge_client_start(struct hnae3_handle *handle) 8058 { 8059 struct hclge_vport *vport = hclge_get_vport(handle); 8060 8061 return hclge_vport_start(vport); 8062 } 8063 8064 static void hclge_client_stop(struct hnae3_handle *handle) 8065 { 8066 struct hclge_vport *vport = hclge_get_vport(handle); 8067 8068 hclge_vport_stop(vport); 8069 } 8070 8071 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 8072 u16 cmdq_resp, u8 resp_code, 8073 enum hclge_mac_vlan_tbl_opcode op) 8074 { 8075 struct hclge_dev *hdev = vport->back; 8076 8077 if (cmdq_resp) { 8078 dev_err(&hdev->pdev->dev, 8079 "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n", 8080 cmdq_resp); 8081 return -EIO; 8082 } 8083 8084 if (op == HCLGE_MAC_VLAN_ADD) { 8085 if (!resp_code || resp_code == 1) 8086 return 0; 8087 else if (resp_code == HCLGE_ADD_UC_OVERFLOW || 8088 resp_code == HCLGE_ADD_MC_OVERFLOW) 8089 return -ENOSPC; 8090 8091 dev_err(&hdev->pdev->dev, 8092 "add mac addr failed for undefined, code=%u.\n", 8093 resp_code); 8094 return -EIO; 8095 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 8096 if (!resp_code) { 8097 return 0; 8098 } else if (resp_code == 1) { 8099 dev_dbg(&hdev->pdev->dev, 8100 "remove mac addr failed for miss.\n"); 8101 return -ENOENT; 8102 } 8103 8104 dev_err(&hdev->pdev->dev, 8105 "remove mac addr failed for undefined, code=%u.\n", 8106 resp_code); 8107 return -EIO; 8108 } else if (op == HCLGE_MAC_VLAN_LKUP) { 8109 if (!resp_code) { 8110 return 0; 8111 } else if (resp_code == 1) { 8112 dev_dbg(&hdev->pdev->dev, 8113 "lookup mac addr failed for miss.\n"); 8114 return -ENOENT; 8115 } 8116 8117 dev_err(&hdev->pdev->dev, 8118 "lookup mac addr failed for undefined, code=%u.\n", 8119 resp_code); 8120 return -EIO; 8121 } 8122 8123 dev_err(&hdev->pdev->dev, 8124 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op); 8125 8126 return -EINVAL; 8127 } 8128 8129 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 8130 { 8131 #define HCLGE_VF_NUM_IN_FIRST_DESC 192 8132 8133 unsigned int word_num; 8134 unsigned int bit_num; 8135 8136 if (vfid > 255 || vfid < 0) 8137 return -EIO; 8138 8139 if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) { 8140 word_num = vfid / 32; 8141 bit_num = vfid % 32; 8142 if (clr) 8143 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8144 else 8145 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 8146 } else { 8147 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32; 8148 bit_num = vfid % 32; 8149 if (clr) 8150 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8151 else 8152 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 8153 } 8154 8155 return 0; 8156 } 8157 8158 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 8159 { 8160 #define HCLGE_DESC_NUMBER 3 8161 #define HCLGE_FUNC_NUMBER_PER_DESC 6 8162 int i, j; 8163 8164 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 8165 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 8166 if (desc[i].data[j]) 8167 return false; 8168 8169 return true; 8170 } 8171 8172 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 8173 const u8 *addr, bool is_mc) 8174 { 8175 const unsigned char *mac_addr = addr; 8176 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 8177 (mac_addr[0]) | (mac_addr[1] << 8); 8178 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 8179 8180 hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8181 if (is_mc) { 8182 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 8183 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8184 } 8185 8186 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 8187 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 8188 } 8189 8190 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 8191 struct hclge_mac_vlan_tbl_entry_cmd *req) 8192 { 8193 struct hclge_dev *hdev = vport->back; 8194 struct hclge_desc desc; 8195 u8 resp_code; 8196 u16 retval; 8197 int ret; 8198 8199 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 8200 8201 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8202 8203 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8204 if (ret) { 8205 dev_err(&hdev->pdev->dev, 8206 "del mac addr failed for cmd_send, ret =%d.\n", 8207 ret); 8208 return ret; 8209 } 8210 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8211 retval = le16_to_cpu(desc.retval); 8212 8213 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8214 HCLGE_MAC_VLAN_REMOVE); 8215 } 8216 8217 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 8218 struct hclge_mac_vlan_tbl_entry_cmd *req, 8219 struct hclge_desc *desc, 8220 bool is_mc) 8221 { 8222 struct hclge_dev *hdev = vport->back; 8223 u8 resp_code; 8224 u16 retval; 8225 int ret; 8226 8227 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 8228 if (is_mc) { 8229 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8230 memcpy(desc[0].data, 8231 req, 8232 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8233 hclge_cmd_setup_basic_desc(&desc[1], 8234 HCLGE_OPC_MAC_VLAN_ADD, 8235 true); 8236 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8237 hclge_cmd_setup_basic_desc(&desc[2], 8238 HCLGE_OPC_MAC_VLAN_ADD, 8239 true); 8240 ret = hclge_cmd_send(&hdev->hw, desc, 3); 8241 } else { 8242 memcpy(desc[0].data, 8243 req, 8244 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8245 ret = hclge_cmd_send(&hdev->hw, desc, 1); 8246 } 8247 if (ret) { 8248 dev_err(&hdev->pdev->dev, 8249 "lookup mac addr failed for cmd_send, ret =%d.\n", 8250 ret); 8251 return ret; 8252 } 8253 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 8254 retval = le16_to_cpu(desc[0].retval); 8255 8256 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8257 HCLGE_MAC_VLAN_LKUP); 8258 } 8259 8260 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 8261 struct hclge_mac_vlan_tbl_entry_cmd *req, 8262 struct hclge_desc *mc_desc) 8263 { 8264 struct hclge_dev *hdev = vport->back; 8265 int cfg_status; 8266 u8 resp_code; 8267 u16 retval; 8268 int ret; 8269 8270 if (!mc_desc) { 8271 struct hclge_desc desc; 8272 8273 hclge_cmd_setup_basic_desc(&desc, 8274 HCLGE_OPC_MAC_VLAN_ADD, 8275 false); 8276 memcpy(desc.data, req, 8277 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8278 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8279 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8280 retval = le16_to_cpu(desc.retval); 8281 8282 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8283 resp_code, 8284 HCLGE_MAC_VLAN_ADD); 8285 } else { 8286 hclge_comm_cmd_reuse_desc(&mc_desc[0], false); 8287 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8288 hclge_comm_cmd_reuse_desc(&mc_desc[1], false); 8289 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8290 hclge_comm_cmd_reuse_desc(&mc_desc[2], false); 8291 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT); 8292 memcpy(mc_desc[0].data, req, 8293 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8294 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 8295 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 8296 retval = le16_to_cpu(mc_desc[0].retval); 8297 8298 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8299 resp_code, 8300 HCLGE_MAC_VLAN_ADD); 8301 } 8302 8303 if (ret) { 8304 dev_err(&hdev->pdev->dev, 8305 "add mac addr failed for cmd_send, ret =%d.\n", 8306 ret); 8307 return ret; 8308 } 8309 8310 return cfg_status; 8311 } 8312 8313 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 8314 u16 *allocated_size) 8315 { 8316 struct hclge_umv_spc_alc_cmd *req; 8317 struct hclge_desc desc; 8318 int ret; 8319 8320 req = (struct hclge_umv_spc_alc_cmd *)desc.data; 8321 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false); 8322 8323 req->space_size = cpu_to_le32(space_size); 8324 8325 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8326 if (ret) { 8327 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n", 8328 ret); 8329 return ret; 8330 } 8331 8332 *allocated_size = le32_to_cpu(desc.data[1]); 8333 8334 return 0; 8335 } 8336 8337 static int hclge_init_umv_space(struct hclge_dev *hdev) 8338 { 8339 u16 allocated_size = 0; 8340 int ret; 8341 8342 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size); 8343 if (ret) 8344 return ret; 8345 8346 if (allocated_size < hdev->wanted_umv_size) 8347 dev_warn(&hdev->pdev->dev, 8348 "failed to alloc umv space, want %u, get %u\n", 8349 hdev->wanted_umv_size, allocated_size); 8350 8351 hdev->max_umv_size = allocated_size; 8352 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1); 8353 hdev->share_umv_size = hdev->priv_umv_size + 8354 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8355 8356 if (hdev->ae_dev->dev_specs.mc_mac_size) 8357 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps); 8358 8359 return 0; 8360 } 8361 8362 static void hclge_reset_umv_space(struct hclge_dev *hdev) 8363 { 8364 struct hclge_vport *vport; 8365 int i; 8366 8367 for (i = 0; i < hdev->num_alloc_vport; i++) { 8368 vport = &hdev->vport[i]; 8369 vport->used_umv_num = 0; 8370 } 8371 8372 mutex_lock(&hdev->vport_lock); 8373 hdev->share_umv_size = hdev->priv_umv_size + 8374 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8375 mutex_unlock(&hdev->vport_lock); 8376 8377 hdev->used_mc_mac_num = 0; 8378 } 8379 8380 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock) 8381 { 8382 struct hclge_dev *hdev = vport->back; 8383 bool is_full; 8384 8385 if (need_lock) 8386 mutex_lock(&hdev->vport_lock); 8387 8388 is_full = (vport->used_umv_num >= hdev->priv_umv_size && 8389 hdev->share_umv_size == 0); 8390 8391 if (need_lock) 8392 mutex_unlock(&hdev->vport_lock); 8393 8394 return is_full; 8395 } 8396 8397 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free) 8398 { 8399 struct hclge_dev *hdev = vport->back; 8400 8401 if (is_free) { 8402 if (vport->used_umv_num > hdev->priv_umv_size) 8403 hdev->share_umv_size++; 8404 8405 if (vport->used_umv_num > 0) 8406 vport->used_umv_num--; 8407 } else { 8408 if (vport->used_umv_num >= hdev->priv_umv_size && 8409 hdev->share_umv_size > 0) 8410 hdev->share_umv_size--; 8411 vport->used_umv_num++; 8412 } 8413 } 8414 8415 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list, 8416 const u8 *mac_addr) 8417 { 8418 struct hclge_mac_node *mac_node, *tmp; 8419 8420 list_for_each_entry_safe(mac_node, tmp, list, node) 8421 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 8422 return mac_node; 8423 8424 return NULL; 8425 } 8426 8427 static void hclge_update_mac_node(struct hclge_mac_node *mac_node, 8428 enum HCLGE_MAC_NODE_STATE state) 8429 { 8430 switch (state) { 8431 /* from set_rx_mode or tmp_add_list */ 8432 case HCLGE_MAC_TO_ADD: 8433 if (mac_node->state == HCLGE_MAC_TO_DEL) 8434 mac_node->state = HCLGE_MAC_ACTIVE; 8435 break; 8436 /* only from set_rx_mode */ 8437 case HCLGE_MAC_TO_DEL: 8438 if (mac_node->state == HCLGE_MAC_TO_ADD) { 8439 list_del(&mac_node->node); 8440 kfree(mac_node); 8441 } else { 8442 mac_node->state = HCLGE_MAC_TO_DEL; 8443 } 8444 break; 8445 /* only from tmp_add_list, the mac_node->state won't be 8446 * ACTIVE. 8447 */ 8448 case HCLGE_MAC_ACTIVE: 8449 if (mac_node->state == HCLGE_MAC_TO_ADD) 8450 mac_node->state = HCLGE_MAC_ACTIVE; 8451 8452 break; 8453 } 8454 } 8455 8456 int hclge_update_mac_list(struct hclge_vport *vport, 8457 enum HCLGE_MAC_NODE_STATE state, 8458 enum HCLGE_MAC_ADDR_TYPE mac_type, 8459 const unsigned char *addr) 8460 { 8461 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8462 struct hclge_dev *hdev = vport->back; 8463 struct hclge_mac_node *mac_node; 8464 struct list_head *list; 8465 8466 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8467 &vport->uc_mac_list : &vport->mc_mac_list; 8468 8469 spin_lock_bh(&vport->mac_list_lock); 8470 8471 /* if the mac addr is already in the mac list, no need to add a new 8472 * one into it, just check the mac addr state, convert it to a new 8473 * state, or just remove it, or do nothing. 8474 */ 8475 mac_node = hclge_find_mac_node(list, addr); 8476 if (mac_node) { 8477 hclge_update_mac_node(mac_node, state); 8478 spin_unlock_bh(&vport->mac_list_lock); 8479 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8480 return 0; 8481 } 8482 8483 /* if this address is never added, unnecessary to delete */ 8484 if (state == HCLGE_MAC_TO_DEL) { 8485 spin_unlock_bh(&vport->mac_list_lock); 8486 hnae3_format_mac_addr(format_mac_addr, addr); 8487 dev_err(&hdev->pdev->dev, 8488 "failed to delete address %s from mac list\n", 8489 format_mac_addr); 8490 return -ENOENT; 8491 } 8492 8493 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 8494 if (!mac_node) { 8495 spin_unlock_bh(&vport->mac_list_lock); 8496 return -ENOMEM; 8497 } 8498 8499 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8500 8501 mac_node->state = state; 8502 ether_addr_copy(mac_node->mac_addr, addr); 8503 list_add_tail(&mac_node->node, list); 8504 8505 spin_unlock_bh(&vport->mac_list_lock); 8506 8507 return 0; 8508 } 8509 8510 static int hclge_add_uc_addr(struct hnae3_handle *handle, 8511 const unsigned char *addr) 8512 { 8513 struct hclge_vport *vport = hclge_get_vport(handle); 8514 8515 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC, 8516 addr); 8517 } 8518 8519 int hclge_add_uc_addr_common(struct hclge_vport *vport, 8520 const unsigned char *addr) 8521 { 8522 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8523 struct hclge_dev *hdev = vport->back; 8524 struct hclge_mac_vlan_tbl_entry_cmd req; 8525 struct hclge_desc desc; 8526 u16 egress_port = 0; 8527 int ret; 8528 8529 /* mac addr check */ 8530 if (is_zero_ether_addr(addr) || 8531 is_broadcast_ether_addr(addr) || 8532 is_multicast_ether_addr(addr)) { 8533 hnae3_format_mac_addr(format_mac_addr, addr); 8534 dev_err(&hdev->pdev->dev, 8535 "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n", 8536 format_mac_addr, is_zero_ether_addr(addr), 8537 is_broadcast_ether_addr(addr), 8538 is_multicast_ether_addr(addr)); 8539 return -EINVAL; 8540 } 8541 8542 memset(&req, 0, sizeof(req)); 8543 8544 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 8545 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 8546 8547 req.egress_port = cpu_to_le16(egress_port); 8548 8549 hclge_prepare_mac_addr(&req, addr, false); 8550 8551 /* Lookup the mac address in the mac_vlan table, and add 8552 * it if the entry is inexistent. Repeated unicast entry 8553 * is not allowed in the mac vlan table. 8554 */ 8555 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 8556 if (ret == -ENOENT) { 8557 mutex_lock(&hdev->vport_lock); 8558 if (!hclge_is_umv_space_full(vport, false)) { 8559 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL); 8560 if (!ret) 8561 hclge_update_umv_space(vport, false); 8562 mutex_unlock(&hdev->vport_lock); 8563 return ret; 8564 } 8565 mutex_unlock(&hdev->vport_lock); 8566 8567 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE)) 8568 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n", 8569 hdev->priv_umv_size); 8570 8571 return -ENOSPC; 8572 } 8573 8574 /* check if we just hit the duplicate */ 8575 if (!ret) 8576 return -EEXIST; 8577 8578 return ret; 8579 } 8580 8581 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 8582 const unsigned char *addr) 8583 { 8584 struct hclge_vport *vport = hclge_get_vport(handle); 8585 8586 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC, 8587 addr); 8588 } 8589 8590 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 8591 const unsigned char *addr) 8592 { 8593 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8594 struct hclge_dev *hdev = vport->back; 8595 struct hclge_mac_vlan_tbl_entry_cmd req; 8596 int ret; 8597 8598 /* mac addr check */ 8599 if (is_zero_ether_addr(addr) || 8600 is_broadcast_ether_addr(addr) || 8601 is_multicast_ether_addr(addr)) { 8602 hnae3_format_mac_addr(format_mac_addr, addr); 8603 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n", 8604 format_mac_addr); 8605 return -EINVAL; 8606 } 8607 8608 memset(&req, 0, sizeof(req)); 8609 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 8610 hclge_prepare_mac_addr(&req, addr, false); 8611 ret = hclge_remove_mac_vlan_tbl(vport, &req); 8612 if (!ret || ret == -ENOENT) { 8613 mutex_lock(&hdev->vport_lock); 8614 hclge_update_umv_space(vport, true); 8615 mutex_unlock(&hdev->vport_lock); 8616 return 0; 8617 } 8618 8619 return ret; 8620 } 8621 8622 static int hclge_add_mc_addr(struct hnae3_handle *handle, 8623 const unsigned char *addr) 8624 { 8625 struct hclge_vport *vport = hclge_get_vport(handle); 8626 8627 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC, 8628 addr); 8629 } 8630 8631 int hclge_add_mc_addr_common(struct hclge_vport *vport, 8632 const unsigned char *addr) 8633 { 8634 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8635 struct hclge_dev *hdev = vport->back; 8636 struct hclge_mac_vlan_tbl_entry_cmd req; 8637 struct hclge_desc desc[3]; 8638 bool is_new_addr = false; 8639 int status; 8640 8641 /* mac addr check */ 8642 if (!is_multicast_ether_addr(addr)) { 8643 hnae3_format_mac_addr(format_mac_addr, addr); 8644 dev_err(&hdev->pdev->dev, 8645 "Add mc mac err! invalid mac:%s.\n", 8646 format_mac_addr); 8647 return -EINVAL; 8648 } 8649 memset(&req, 0, sizeof(req)); 8650 hclge_prepare_mac_addr(&req, addr, true); 8651 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8652 if (status) { 8653 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) && 8654 hdev->used_mc_mac_num >= 8655 hdev->ae_dev->dev_specs.mc_mac_size) 8656 goto err_no_space; 8657 8658 is_new_addr = true; 8659 8660 /* This mac addr do not exist, add new entry for it */ 8661 memset(desc[0].data, 0, sizeof(desc[0].data)); 8662 memset(desc[1].data, 0, sizeof(desc[0].data)); 8663 memset(desc[2].data, 0, sizeof(desc[0].data)); 8664 } 8665 status = hclge_update_desc_vfid(desc, vport->vport_id, false); 8666 if (status) 8667 return status; 8668 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8669 if (status == -ENOSPC) 8670 goto err_no_space; 8671 else if (!status && is_new_addr) 8672 hdev->used_mc_mac_num++; 8673 8674 return status; 8675 8676 err_no_space: 8677 /* if already overflow, not to print each time */ 8678 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) { 8679 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8680 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n"); 8681 } 8682 8683 return -ENOSPC; 8684 } 8685 8686 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 8687 const unsigned char *addr) 8688 { 8689 struct hclge_vport *vport = hclge_get_vport(handle); 8690 8691 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC, 8692 addr); 8693 } 8694 8695 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 8696 const unsigned char *addr) 8697 { 8698 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8699 struct hclge_dev *hdev = vport->back; 8700 struct hclge_mac_vlan_tbl_entry_cmd req; 8701 enum hclge_comm_cmd_status status; 8702 struct hclge_desc desc[3]; 8703 8704 /* mac addr check */ 8705 if (!is_multicast_ether_addr(addr)) { 8706 hnae3_format_mac_addr(format_mac_addr, addr); 8707 dev_dbg(&hdev->pdev->dev, 8708 "Remove mc mac err! invalid mac:%s.\n", 8709 format_mac_addr); 8710 return -EINVAL; 8711 } 8712 8713 memset(&req, 0, sizeof(req)); 8714 hclge_prepare_mac_addr(&req, addr, true); 8715 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8716 if (!status) { 8717 /* This mac addr exist, remove this handle's VFID for it */ 8718 status = hclge_update_desc_vfid(desc, vport->vport_id, true); 8719 if (status) 8720 return status; 8721 8722 if (hclge_is_all_function_id_zero(desc)) { 8723 /* All the vfid is zero, so need to delete this entry */ 8724 status = hclge_remove_mac_vlan_tbl(vport, &req); 8725 if (!status) 8726 hdev->used_mc_mac_num--; 8727 } else { 8728 /* Not all the vfid is zero, update the vfid */ 8729 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8730 } 8731 } else if (status == -ENOENT) { 8732 status = 0; 8733 } 8734 8735 return status; 8736 } 8737 8738 static void hclge_sync_vport_mac_list(struct hclge_vport *vport, 8739 struct list_head *list, 8740 enum HCLGE_MAC_ADDR_TYPE mac_type) 8741 { 8742 int (*sync)(struct hclge_vport *vport, const unsigned char *addr); 8743 struct hclge_mac_node *mac_node, *tmp; 8744 int ret; 8745 8746 if (mac_type == HCLGE_MAC_ADDR_UC) 8747 sync = hclge_add_uc_addr_common; 8748 else 8749 sync = hclge_add_mc_addr_common; 8750 8751 list_for_each_entry_safe(mac_node, tmp, list, node) { 8752 ret = sync(vport, mac_node->mac_addr); 8753 if (!ret) { 8754 mac_node->state = HCLGE_MAC_ACTIVE; 8755 } else { 8756 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8757 &vport->state); 8758 8759 /* If one unicast mac address is existing in hardware, 8760 * we need to try whether other unicast mac addresses 8761 * are new addresses that can be added. 8762 * Multicast mac address can be reusable, even though 8763 * there is no space to add new multicast mac address, 8764 * we should check whether other mac addresses are 8765 * existing in hardware for reuse. 8766 */ 8767 if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) || 8768 (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC)) 8769 break; 8770 } 8771 } 8772 } 8773 8774 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport, 8775 struct list_head *list, 8776 enum HCLGE_MAC_ADDR_TYPE mac_type) 8777 { 8778 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 8779 struct hclge_mac_node *mac_node, *tmp; 8780 int ret; 8781 8782 if (mac_type == HCLGE_MAC_ADDR_UC) 8783 unsync = hclge_rm_uc_addr_common; 8784 else 8785 unsync = hclge_rm_mc_addr_common; 8786 8787 list_for_each_entry_safe(mac_node, tmp, list, node) { 8788 ret = unsync(vport, mac_node->mac_addr); 8789 if (!ret || ret == -ENOENT) { 8790 list_del(&mac_node->node); 8791 kfree(mac_node); 8792 } else { 8793 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8794 &vport->state); 8795 break; 8796 } 8797 } 8798 } 8799 8800 static bool hclge_sync_from_add_list(struct list_head *add_list, 8801 struct list_head *mac_list) 8802 { 8803 struct hclge_mac_node *mac_node, *tmp, *new_node; 8804 bool all_added = true; 8805 8806 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 8807 if (mac_node->state == HCLGE_MAC_TO_ADD) 8808 all_added = false; 8809 8810 /* if the mac address from tmp_add_list is not in the 8811 * uc/mc_mac_list, it means have received a TO_DEL request 8812 * during the time window of adding the mac address into mac 8813 * table. if mac_node state is ACTIVE, then change it to TO_DEL, 8814 * then it will be removed at next time. else it must be TO_ADD, 8815 * this address hasn't been added into mac table, 8816 * so just remove the mac node. 8817 */ 8818 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8819 if (new_node) { 8820 hclge_update_mac_node(new_node, mac_node->state); 8821 list_del(&mac_node->node); 8822 kfree(mac_node); 8823 } else if (mac_node->state == HCLGE_MAC_ACTIVE) { 8824 mac_node->state = HCLGE_MAC_TO_DEL; 8825 list_move_tail(&mac_node->node, mac_list); 8826 } else { 8827 list_del(&mac_node->node); 8828 kfree(mac_node); 8829 } 8830 } 8831 8832 return all_added; 8833 } 8834 8835 static void hclge_sync_from_del_list(struct list_head *del_list, 8836 struct list_head *mac_list) 8837 { 8838 struct hclge_mac_node *mac_node, *tmp, *new_node; 8839 8840 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 8841 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8842 if (new_node) { 8843 /* If the mac addr exists in the mac list, it means 8844 * received a new TO_ADD request during the time window 8845 * of configuring the mac address. For the mac node 8846 * state is TO_ADD, and the address is already in the 8847 * in the hardware(due to delete fail), so we just need 8848 * to change the mac node state to ACTIVE. 8849 */ 8850 new_node->state = HCLGE_MAC_ACTIVE; 8851 list_del(&mac_node->node); 8852 kfree(mac_node); 8853 } else { 8854 list_move_tail(&mac_node->node, mac_list); 8855 } 8856 } 8857 } 8858 8859 static void hclge_update_overflow_flags(struct hclge_vport *vport, 8860 enum HCLGE_MAC_ADDR_TYPE mac_type, 8861 bool is_all_added) 8862 { 8863 if (mac_type == HCLGE_MAC_ADDR_UC) { 8864 if (is_all_added) 8865 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE; 8866 else if (hclge_is_umv_space_full(vport, true)) 8867 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE; 8868 } else { 8869 if (is_all_added) 8870 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE; 8871 else 8872 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8873 } 8874 } 8875 8876 static void hclge_sync_vport_mac_table(struct hclge_vport *vport, 8877 enum HCLGE_MAC_ADDR_TYPE mac_type) 8878 { 8879 struct hclge_mac_node *mac_node, *tmp, *new_node; 8880 struct list_head tmp_add_list, tmp_del_list; 8881 struct list_head *list; 8882 bool all_added; 8883 8884 INIT_LIST_HEAD(&tmp_add_list); 8885 INIT_LIST_HEAD(&tmp_del_list); 8886 8887 /* move the mac addr to the tmp_add_list and tmp_del_list, then 8888 * we can add/delete these mac addr outside the spin lock 8889 */ 8890 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8891 &vport->uc_mac_list : &vport->mc_mac_list; 8892 8893 spin_lock_bh(&vport->mac_list_lock); 8894 8895 list_for_each_entry_safe(mac_node, tmp, list, node) { 8896 switch (mac_node->state) { 8897 case HCLGE_MAC_TO_DEL: 8898 list_move_tail(&mac_node->node, &tmp_del_list); 8899 break; 8900 case HCLGE_MAC_TO_ADD: 8901 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 8902 if (!new_node) 8903 goto stop_traverse; 8904 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 8905 new_node->state = mac_node->state; 8906 list_add_tail(&new_node->node, &tmp_add_list); 8907 break; 8908 default: 8909 break; 8910 } 8911 } 8912 8913 stop_traverse: 8914 spin_unlock_bh(&vport->mac_list_lock); 8915 8916 /* delete first, in order to get max mac table space for adding */ 8917 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 8918 hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type); 8919 8920 /* if some mac addresses were added/deleted fail, move back to the 8921 * mac_list, and retry at next time. 8922 */ 8923 spin_lock_bh(&vport->mac_list_lock); 8924 8925 hclge_sync_from_del_list(&tmp_del_list, list); 8926 all_added = hclge_sync_from_add_list(&tmp_add_list, list); 8927 8928 spin_unlock_bh(&vport->mac_list_lock); 8929 8930 hclge_update_overflow_flags(vport, mac_type, all_added); 8931 } 8932 8933 static bool hclge_need_sync_mac_table(struct hclge_vport *vport) 8934 { 8935 struct hclge_dev *hdev = vport->back; 8936 8937 if (test_bit(vport->vport_id, hdev->vport_config_block)) 8938 return false; 8939 8940 if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state)) 8941 return true; 8942 8943 return false; 8944 } 8945 8946 static void hclge_sync_mac_table(struct hclge_dev *hdev) 8947 { 8948 int i; 8949 8950 for (i = 0; i < hdev->num_alloc_vport; i++) { 8951 struct hclge_vport *vport = &hdev->vport[i]; 8952 8953 if (!hclge_need_sync_mac_table(vport)) 8954 continue; 8955 8956 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC); 8957 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC); 8958 } 8959 } 8960 8961 static void hclge_build_del_list(struct list_head *list, 8962 bool is_del_list, 8963 struct list_head *tmp_del_list) 8964 { 8965 struct hclge_mac_node *mac_cfg, *tmp; 8966 8967 list_for_each_entry_safe(mac_cfg, tmp, list, node) { 8968 switch (mac_cfg->state) { 8969 case HCLGE_MAC_TO_DEL: 8970 case HCLGE_MAC_ACTIVE: 8971 list_move_tail(&mac_cfg->node, tmp_del_list); 8972 break; 8973 case HCLGE_MAC_TO_ADD: 8974 if (is_del_list) { 8975 list_del(&mac_cfg->node); 8976 kfree(mac_cfg); 8977 } 8978 break; 8979 } 8980 } 8981 } 8982 8983 static void hclge_unsync_del_list(struct hclge_vport *vport, 8984 int (*unsync)(struct hclge_vport *vport, 8985 const unsigned char *addr), 8986 bool is_del_list, 8987 struct list_head *tmp_del_list) 8988 { 8989 struct hclge_mac_node *mac_cfg, *tmp; 8990 int ret; 8991 8992 list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) { 8993 ret = unsync(vport, mac_cfg->mac_addr); 8994 if (!ret || ret == -ENOENT) { 8995 /* clear all mac addr from hardware, but remain these 8996 * mac addr in the mac list, and restore them after 8997 * vf reset finished. 8998 */ 8999 if (!is_del_list && 9000 mac_cfg->state == HCLGE_MAC_ACTIVE) { 9001 mac_cfg->state = HCLGE_MAC_TO_ADD; 9002 } else { 9003 list_del(&mac_cfg->node); 9004 kfree(mac_cfg); 9005 } 9006 } else if (is_del_list) { 9007 mac_cfg->state = HCLGE_MAC_TO_DEL; 9008 } 9009 } 9010 } 9011 9012 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 9013 enum HCLGE_MAC_ADDR_TYPE mac_type) 9014 { 9015 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 9016 struct hclge_dev *hdev = vport->back; 9017 struct list_head tmp_del_list, *list; 9018 9019 if (mac_type == HCLGE_MAC_ADDR_UC) { 9020 list = &vport->uc_mac_list; 9021 unsync = hclge_rm_uc_addr_common; 9022 } else { 9023 list = &vport->mc_mac_list; 9024 unsync = hclge_rm_mc_addr_common; 9025 } 9026 9027 INIT_LIST_HEAD(&tmp_del_list); 9028 9029 if (!is_del_list) 9030 set_bit(vport->vport_id, hdev->vport_config_block); 9031 9032 spin_lock_bh(&vport->mac_list_lock); 9033 9034 hclge_build_del_list(list, is_del_list, &tmp_del_list); 9035 9036 spin_unlock_bh(&vport->mac_list_lock); 9037 9038 hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list); 9039 9040 spin_lock_bh(&vport->mac_list_lock); 9041 9042 hclge_sync_from_del_list(&tmp_del_list, list); 9043 9044 spin_unlock_bh(&vport->mac_list_lock); 9045 } 9046 9047 /* remove all mac address when uninitailize */ 9048 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport, 9049 enum HCLGE_MAC_ADDR_TYPE mac_type) 9050 { 9051 struct hclge_mac_node *mac_node, *tmp; 9052 struct hclge_dev *hdev = vport->back; 9053 struct list_head tmp_del_list, *list; 9054 9055 INIT_LIST_HEAD(&tmp_del_list); 9056 9057 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 9058 &vport->uc_mac_list : &vport->mc_mac_list; 9059 9060 spin_lock_bh(&vport->mac_list_lock); 9061 9062 list_for_each_entry_safe(mac_node, tmp, list, node) { 9063 switch (mac_node->state) { 9064 case HCLGE_MAC_TO_DEL: 9065 case HCLGE_MAC_ACTIVE: 9066 list_move_tail(&mac_node->node, &tmp_del_list); 9067 break; 9068 case HCLGE_MAC_TO_ADD: 9069 list_del(&mac_node->node); 9070 kfree(mac_node); 9071 break; 9072 } 9073 } 9074 9075 spin_unlock_bh(&vport->mac_list_lock); 9076 9077 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 9078 9079 if (!list_empty(&tmp_del_list)) 9080 dev_warn(&hdev->pdev->dev, 9081 "uninit %s mac list for vport %u not completely.\n", 9082 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc", 9083 vport->vport_id); 9084 9085 list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) { 9086 list_del(&mac_node->node); 9087 kfree(mac_node); 9088 } 9089 } 9090 9091 static void hclge_uninit_mac_table(struct hclge_dev *hdev) 9092 { 9093 struct hclge_vport *vport; 9094 int i; 9095 9096 for (i = 0; i < hdev->num_alloc_vport; i++) { 9097 vport = &hdev->vport[i]; 9098 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC); 9099 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC); 9100 } 9101 } 9102 9103 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 9104 u16 cmdq_resp, u8 resp_code) 9105 { 9106 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 9107 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 9108 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 9109 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 9110 9111 int return_status; 9112 9113 if (cmdq_resp) { 9114 dev_err(&hdev->pdev->dev, 9115 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 9116 cmdq_resp); 9117 return -EIO; 9118 } 9119 9120 switch (resp_code) { 9121 case HCLGE_ETHERTYPE_SUCCESS_ADD: 9122 case HCLGE_ETHERTYPE_ALREADY_ADD: 9123 return_status = 0; 9124 break; 9125 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 9126 dev_err(&hdev->pdev->dev, 9127 "add mac ethertype failed for manager table overflow.\n"); 9128 return_status = -EIO; 9129 break; 9130 case HCLGE_ETHERTYPE_KEY_CONFLICT: 9131 dev_err(&hdev->pdev->dev, 9132 "add mac ethertype failed for key conflict.\n"); 9133 return_status = -EIO; 9134 break; 9135 default: 9136 dev_err(&hdev->pdev->dev, 9137 "add mac ethertype failed for undefined, code=%u.\n", 9138 resp_code); 9139 return_status = -EIO; 9140 } 9141 9142 return return_status; 9143 } 9144 9145 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf, 9146 u8 *mac_addr) 9147 { 9148 struct hclge_vport *vport = hclge_get_vport(handle); 9149 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9150 struct hclge_dev *hdev = vport->back; 9151 9152 vport = hclge_get_vf_vport(hdev, vf); 9153 if (!vport) 9154 return -EINVAL; 9155 9156 hnae3_format_mac_addr(format_mac_addr, mac_addr); 9157 if (ether_addr_equal(mac_addr, vport->vf_info.mac)) { 9158 dev_info(&hdev->pdev->dev, 9159 "Specified MAC(=%s) is same as before, no change committed!\n", 9160 format_mac_addr); 9161 return 0; 9162 } 9163 9164 ether_addr_copy(vport->vf_info.mac, mac_addr); 9165 9166 /* there is a timewindow for PF to know VF unalive, it may 9167 * cause send mailbox fail, but it doesn't matter, VF will 9168 * query it when reinit. 9169 */ 9170 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) { 9171 dev_info(&hdev->pdev->dev, 9172 "MAC of VF %d has been set to %s, and it will be reinitialized!\n", 9173 vf, format_mac_addr); 9174 (void)hclge_inform_reset_assert_to_vf(vport); 9175 return 0; 9176 } 9177 9178 dev_info(&hdev->pdev->dev, 9179 "MAC of VF %d has been set to %s, will be active after VF reset\n", 9180 vf, format_mac_addr); 9181 return 0; 9182 } 9183 9184 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 9185 const struct hclge_mac_mgr_tbl_entry_cmd *req) 9186 { 9187 struct hclge_desc desc; 9188 u8 resp_code; 9189 u16 retval; 9190 int ret; 9191 9192 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 9193 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 9194 9195 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9196 if (ret) { 9197 dev_err(&hdev->pdev->dev, 9198 "add mac ethertype failed for cmd_send, ret =%d.\n", 9199 ret); 9200 return ret; 9201 } 9202 9203 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 9204 retval = le16_to_cpu(desc.retval); 9205 9206 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 9207 } 9208 9209 static int init_mgr_tbl(struct hclge_dev *hdev) 9210 { 9211 int ret; 9212 int i; 9213 9214 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 9215 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 9216 if (ret) { 9217 dev_err(&hdev->pdev->dev, 9218 "add mac ethertype failed, ret =%d.\n", 9219 ret); 9220 return ret; 9221 } 9222 } 9223 9224 return 0; 9225 } 9226 9227 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 9228 { 9229 struct hclge_vport *vport = hclge_get_vport(handle); 9230 struct hclge_dev *hdev = vport->back; 9231 9232 ether_addr_copy(p, hdev->hw.mac.mac_addr); 9233 } 9234 9235 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 9236 const u8 *old_addr, const u8 *new_addr) 9237 { 9238 struct list_head *list = &vport->uc_mac_list; 9239 struct hclge_mac_node *old_node, *new_node; 9240 9241 new_node = hclge_find_mac_node(list, new_addr); 9242 if (!new_node) { 9243 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 9244 if (!new_node) 9245 return -ENOMEM; 9246 9247 new_node->state = HCLGE_MAC_TO_ADD; 9248 ether_addr_copy(new_node->mac_addr, new_addr); 9249 list_add(&new_node->node, list); 9250 } else { 9251 if (new_node->state == HCLGE_MAC_TO_DEL) 9252 new_node->state = HCLGE_MAC_ACTIVE; 9253 9254 /* make sure the new addr is in the list head, avoid dev 9255 * addr may be not re-added into mac table for the umv space 9256 * limitation after global/imp reset which will clear mac 9257 * table by hardware. 9258 */ 9259 list_move(&new_node->node, list); 9260 } 9261 9262 if (old_addr && !ether_addr_equal(old_addr, new_addr)) { 9263 old_node = hclge_find_mac_node(list, old_addr); 9264 if (old_node) { 9265 if (old_node->state == HCLGE_MAC_TO_ADD) { 9266 list_del(&old_node->node); 9267 kfree(old_node); 9268 } else { 9269 old_node->state = HCLGE_MAC_TO_DEL; 9270 } 9271 } 9272 } 9273 9274 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 9275 9276 return 0; 9277 } 9278 9279 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p, 9280 bool is_first) 9281 { 9282 const unsigned char *new_addr = (const unsigned char *)p; 9283 struct hclge_vport *vport = hclge_get_vport(handle); 9284 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9285 struct hclge_dev *hdev = vport->back; 9286 unsigned char *old_addr = NULL; 9287 int ret; 9288 9289 /* mac addr check */ 9290 if (is_zero_ether_addr(new_addr) || 9291 is_broadcast_ether_addr(new_addr) || 9292 is_multicast_ether_addr(new_addr)) { 9293 hnae3_format_mac_addr(format_mac_addr, new_addr); 9294 dev_err(&hdev->pdev->dev, 9295 "change uc mac err! invalid mac: %s.\n", 9296 format_mac_addr); 9297 return -EINVAL; 9298 } 9299 9300 ret = hclge_pause_addr_cfg(hdev, new_addr); 9301 if (ret) { 9302 dev_err(&hdev->pdev->dev, 9303 "failed to configure mac pause address, ret = %d\n", 9304 ret); 9305 return ret; 9306 } 9307 9308 if (!is_first) 9309 old_addr = hdev->hw.mac.mac_addr; 9310 9311 spin_lock_bh(&vport->mac_list_lock); 9312 ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr); 9313 if (ret) { 9314 hnae3_format_mac_addr(format_mac_addr, new_addr); 9315 dev_err(&hdev->pdev->dev, 9316 "failed to change the mac addr:%s, ret = %d\n", 9317 format_mac_addr, ret); 9318 spin_unlock_bh(&vport->mac_list_lock); 9319 9320 if (!is_first) 9321 hclge_pause_addr_cfg(hdev, old_addr); 9322 9323 return ret; 9324 } 9325 /* we must update dev addr with spin lock protect, preventing dev addr 9326 * being removed by set_rx_mode path. 9327 */ 9328 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 9329 spin_unlock_bh(&vport->mac_list_lock); 9330 9331 hclge_task_schedule(hdev, 0); 9332 9333 return 0; 9334 } 9335 9336 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd) 9337 { 9338 struct mii_ioctl_data *data = if_mii(ifr); 9339 9340 if (!hnae3_dev_phy_imp_supported(hdev)) 9341 return -EOPNOTSUPP; 9342 9343 switch (cmd) { 9344 case SIOCGMIIPHY: 9345 data->phy_id = hdev->hw.mac.phy_addr; 9346 /* this command reads phy id and register at the same time */ 9347 fallthrough; 9348 case SIOCGMIIREG: 9349 data->val_out = hclge_read_phy_reg(hdev, data->reg_num); 9350 return 0; 9351 9352 case SIOCSMIIREG: 9353 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in); 9354 default: 9355 return -EOPNOTSUPP; 9356 } 9357 } 9358 9359 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr, 9360 int cmd) 9361 { 9362 struct hclge_vport *vport = hclge_get_vport(handle); 9363 struct hclge_dev *hdev = vport->back; 9364 9365 switch (cmd) { 9366 case SIOCGHWTSTAMP: 9367 return hclge_ptp_get_cfg(hdev, ifr); 9368 case SIOCSHWTSTAMP: 9369 return hclge_ptp_set_cfg(hdev, ifr); 9370 default: 9371 if (!hdev->hw.mac.phydev) 9372 return hclge_mii_ioctl(hdev, ifr, cmd); 9373 } 9374 9375 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd); 9376 } 9377 9378 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id, 9379 bool bypass_en) 9380 { 9381 struct hclge_port_vlan_filter_bypass_cmd *req; 9382 struct hclge_desc desc; 9383 int ret; 9384 9385 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false); 9386 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 9387 req->vf_id = vf_id; 9388 hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B, 9389 bypass_en ? 1 : 0); 9390 9391 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9392 if (ret) 9393 dev_err(&hdev->pdev->dev, 9394 "failed to set vport%u port vlan filter bypass state, ret = %d.\n", 9395 vf_id, ret); 9396 9397 return ret; 9398 } 9399 9400 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 9401 u8 fe_type, bool filter_en, u8 vf_id) 9402 { 9403 struct hclge_vlan_filter_ctrl_cmd *req; 9404 struct hclge_desc desc; 9405 int ret; 9406 9407 /* read current vlan filter parameter */ 9408 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 9409 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 9410 req->vlan_type = vlan_type; 9411 req->vf_id = vf_id; 9412 9413 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9414 if (ret) { 9415 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n", 9416 vf_id, ret); 9417 return ret; 9418 } 9419 9420 /* modify and write new config parameter */ 9421 hclge_comm_cmd_reuse_desc(&desc, false); 9422 req->vlan_fe = filter_en ? 9423 (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type); 9424 9425 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9426 if (ret) 9427 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n", 9428 vf_id, ret); 9429 9430 return ret; 9431 } 9432 9433 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable) 9434 { 9435 struct hclge_dev *hdev = vport->back; 9436 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 9437 int ret; 9438 9439 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9440 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9441 HCLGE_FILTER_FE_EGRESS_V1_B, 9442 enable, vport->vport_id); 9443 9444 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9445 HCLGE_FILTER_FE_EGRESS, enable, 9446 vport->vport_id); 9447 if (ret) 9448 return ret; 9449 9450 if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) { 9451 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id, 9452 !enable); 9453 } else if (!vport->vport_id) { 9454 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 9455 enable = false; 9456 9457 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9458 HCLGE_FILTER_FE_INGRESS, 9459 enable, 0); 9460 } 9461 9462 return ret; 9463 } 9464 9465 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport) 9466 { 9467 struct hnae3_handle *handle = &vport->nic; 9468 struct hclge_vport_vlan_cfg *vlan, *tmp; 9469 struct hclge_dev *hdev = vport->back; 9470 9471 if (vport->vport_id) { 9472 if (vport->port_base_vlan_cfg.state != 9473 HNAE3_PORT_BASE_VLAN_DISABLE) 9474 return true; 9475 9476 if (vport->vf_info.trusted && vport->vf_info.request_uc_en) 9477 return false; 9478 } else if (handle->netdev_flags & HNAE3_USER_UPE) { 9479 return false; 9480 } 9481 9482 if (!vport->req_vlan_fltr_en) 9483 return false; 9484 9485 /* compatible with former device, always enable vlan filter */ 9486 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 9487 return true; 9488 9489 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) 9490 if (vlan->vlan_id != 0) 9491 return true; 9492 9493 return false; 9494 } 9495 9496 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) 9497 { 9498 struct hclge_dev *hdev = vport->back; 9499 bool need_en; 9500 int ret; 9501 9502 mutex_lock(&hdev->vport_lock); 9503 9504 vport->req_vlan_fltr_en = request_en; 9505 9506 need_en = hclge_need_enable_vport_vlan_filter(vport); 9507 if (need_en == vport->cur_vlan_fltr_en) { 9508 mutex_unlock(&hdev->vport_lock); 9509 return 0; 9510 } 9511 9512 ret = hclge_set_vport_vlan_filter(vport, need_en); 9513 if (ret) { 9514 mutex_unlock(&hdev->vport_lock); 9515 return ret; 9516 } 9517 9518 vport->cur_vlan_fltr_en = need_en; 9519 9520 mutex_unlock(&hdev->vport_lock); 9521 9522 return 0; 9523 } 9524 9525 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 9526 { 9527 struct hclge_vport *vport = hclge_get_vport(handle); 9528 9529 return hclge_enable_vport_vlan_filter(vport, enable); 9530 } 9531 9532 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid, 9533 bool is_kill, u16 vlan, 9534 struct hclge_desc *desc) 9535 { 9536 struct hclge_vlan_filter_vf_cfg_cmd *req0; 9537 struct hclge_vlan_filter_vf_cfg_cmd *req1; 9538 u8 vf_byte_val; 9539 u8 vf_byte_off; 9540 int ret; 9541 9542 hclge_cmd_setup_basic_desc(&desc[0], 9543 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9544 hclge_cmd_setup_basic_desc(&desc[1], 9545 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9546 9547 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 9548 9549 vf_byte_off = vfid / 8; 9550 vf_byte_val = 1 << (vfid % 8); 9551 9552 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9553 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 9554 9555 req0->vlan_id = cpu_to_le16(vlan); 9556 req0->vlan_cfg = is_kill; 9557 9558 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 9559 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 9560 else 9561 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 9562 9563 ret = hclge_cmd_send(&hdev->hw, desc, 2); 9564 if (ret) { 9565 dev_err(&hdev->pdev->dev, 9566 "Send vf vlan command fail, ret =%d.\n", 9567 ret); 9568 return ret; 9569 } 9570 9571 return 0; 9572 } 9573 9574 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid, 9575 bool is_kill, struct hclge_desc *desc) 9576 { 9577 struct hclge_vlan_filter_vf_cfg_cmd *req; 9578 9579 req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9580 9581 if (!is_kill) { 9582 #define HCLGE_VF_VLAN_NO_ENTRY 2 9583 if (!req->resp_code || req->resp_code == 1) 9584 return 0; 9585 9586 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 9587 set_bit(vfid, hdev->vf_vlan_full); 9588 dev_warn(&hdev->pdev->dev, 9589 "vf vlan table is full, vf vlan filter is disabled\n"); 9590 return 0; 9591 } 9592 9593 dev_err(&hdev->pdev->dev, 9594 "Add vf vlan filter fail, ret =%u.\n", 9595 req->resp_code); 9596 } else { 9597 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 9598 if (!req->resp_code) 9599 return 0; 9600 9601 /* vf vlan filter is disabled when vf vlan table is full, 9602 * then new vlan id will not be added into vf vlan table. 9603 * Just return 0 without warning, avoid massive verbose 9604 * print logs when unload. 9605 */ 9606 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) 9607 return 0; 9608 9609 dev_err(&hdev->pdev->dev, 9610 "Kill vf vlan filter fail, ret =%u.\n", 9611 req->resp_code); 9612 } 9613 9614 return -EIO; 9615 } 9616 9617 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid, 9618 bool is_kill, u16 vlan) 9619 { 9620 struct hclge_vport *vport = &hdev->vport[vfid]; 9621 struct hclge_desc desc[2]; 9622 int ret; 9623 9624 /* if vf vlan table is full, firmware will close vf vlan filter, it 9625 * is unable and unnecessary to add new vlan id to vf vlan filter. 9626 * If spoof check is enable, and vf vlan is full, it shouldn't add 9627 * new vlan, because tx packets with these vlan id will be dropped. 9628 */ 9629 if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) { 9630 if (vport->vf_info.spoofchk && vlan) { 9631 dev_err(&hdev->pdev->dev, 9632 "Can't add vlan due to spoof check is on and vf vlan table is full\n"); 9633 return -EPERM; 9634 } 9635 return 0; 9636 } 9637 9638 ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc); 9639 if (ret) 9640 return ret; 9641 9642 return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc); 9643 } 9644 9645 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 9646 u16 vlan_id, bool is_kill) 9647 { 9648 struct hclge_vlan_filter_pf_cfg_cmd *req; 9649 struct hclge_desc desc; 9650 u8 vlan_offset_byte_val; 9651 u8 vlan_offset_byte; 9652 u8 vlan_offset_160; 9653 int ret; 9654 9655 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 9656 9657 vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP; 9658 vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) / 9659 HCLGE_VLAN_BYTE_SIZE; 9660 vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE); 9661 9662 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 9663 req->vlan_offset = vlan_offset_160; 9664 req->vlan_cfg = is_kill; 9665 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 9666 9667 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9668 if (ret) 9669 dev_err(&hdev->pdev->dev, 9670 "port vlan command, send fail, ret =%d.\n", ret); 9671 return ret; 9672 } 9673 9674 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id, 9675 u16 vlan_id, bool is_kill) 9676 { 9677 /* vlan 0 may be added twice when 8021q module is enabled */ 9678 if (!is_kill && !vlan_id && 9679 test_bit(vport_id, hdev->vlan_table[vlan_id])) 9680 return false; 9681 9682 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 9683 dev_warn(&hdev->pdev->dev, 9684 "Add port vlan failed, vport %u is already in vlan %u\n", 9685 vport_id, vlan_id); 9686 return false; 9687 } 9688 9689 if (is_kill && 9690 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 9691 dev_warn(&hdev->pdev->dev, 9692 "Delete port vlan failed, vport %u is not in vlan %u\n", 9693 vport_id, vlan_id); 9694 return false; 9695 } 9696 9697 return true; 9698 } 9699 9700 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 9701 u16 vport_id, u16 vlan_id, 9702 bool is_kill) 9703 { 9704 u16 vport_idx, vport_num = 0; 9705 int ret; 9706 9707 if (is_kill && !vlan_id) 9708 return 0; 9709 9710 if (vlan_id >= VLAN_N_VID) 9711 return -EINVAL; 9712 9713 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id); 9714 if (ret) { 9715 dev_err(&hdev->pdev->dev, 9716 "Set %u vport vlan filter config fail, ret =%d.\n", 9717 vport_id, ret); 9718 return ret; 9719 } 9720 9721 if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill)) 9722 return 0; 9723 9724 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 9725 vport_num++; 9726 9727 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 9728 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 9729 is_kill); 9730 9731 return ret; 9732 } 9733 9734 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 9735 { 9736 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 9737 struct hclge_vport_vtag_tx_cfg_cmd *req; 9738 struct hclge_dev *hdev = vport->back; 9739 struct hclge_desc desc; 9740 u16 bmap_index; 9741 int status; 9742 9743 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 9744 9745 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 9746 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 9747 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 9748 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 9749 vcfg->accept_tag1 ? 1 : 0); 9750 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 9751 vcfg->accept_untag1 ? 1 : 0); 9752 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 9753 vcfg->accept_tag2 ? 1 : 0); 9754 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 9755 vcfg->accept_untag2 ? 1 : 0); 9756 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 9757 vcfg->insert_tag1_en ? 1 : 0); 9758 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 9759 vcfg->insert_tag2_en ? 1 : 0); 9760 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B, 9761 vcfg->tag_shift_mode_en ? 1 : 0); 9762 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 9763 9764 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9765 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9766 HCLGE_VF_NUM_PER_BYTE; 9767 req->vf_bitmap[bmap_index] = 9768 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9769 9770 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9771 if (status) 9772 dev_err(&hdev->pdev->dev, 9773 "Send port txvlan cfg command fail, ret =%d\n", 9774 status); 9775 9776 return status; 9777 } 9778 9779 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 9780 { 9781 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 9782 struct hclge_vport_vtag_rx_cfg_cmd *req; 9783 struct hclge_dev *hdev = vport->back; 9784 struct hclge_desc desc; 9785 u16 bmap_index; 9786 int status; 9787 9788 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 9789 9790 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 9791 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 9792 vcfg->strip_tag1_en ? 1 : 0); 9793 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 9794 vcfg->strip_tag2_en ? 1 : 0); 9795 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 9796 vcfg->vlan1_vlan_prionly ? 1 : 0); 9797 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 9798 vcfg->vlan2_vlan_prionly ? 1 : 0); 9799 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B, 9800 vcfg->strip_tag1_discard_en ? 1 : 0); 9801 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B, 9802 vcfg->strip_tag2_discard_en ? 1 : 0); 9803 9804 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9805 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9806 HCLGE_VF_NUM_PER_BYTE; 9807 req->vf_bitmap[bmap_index] = 9808 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9809 9810 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9811 if (status) 9812 dev_err(&hdev->pdev->dev, 9813 "Send port rxvlan cfg command fail, ret =%d\n", 9814 status); 9815 9816 return status; 9817 } 9818 9819 static int hclge_vlan_offload_cfg(struct hclge_vport *vport, 9820 u16 port_base_vlan_state, 9821 u16 vlan_tag, u8 qos) 9822 { 9823 int ret; 9824 9825 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9826 vport->txvlan_cfg.accept_tag1 = true; 9827 vport->txvlan_cfg.insert_tag1_en = false; 9828 vport->txvlan_cfg.default_tag1 = 0; 9829 } else { 9830 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev); 9831 9832 vport->txvlan_cfg.accept_tag1 = 9833 ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3; 9834 vport->txvlan_cfg.insert_tag1_en = true; 9835 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) | 9836 vlan_tag; 9837 } 9838 9839 vport->txvlan_cfg.accept_untag1 = true; 9840 9841 /* accept_tag2 and accept_untag2 are not supported on 9842 * pdev revision(0x20), new revision support them, 9843 * this two fields can not be configured by user. 9844 */ 9845 vport->txvlan_cfg.accept_tag2 = true; 9846 vport->txvlan_cfg.accept_untag2 = true; 9847 vport->txvlan_cfg.insert_tag2_en = false; 9848 vport->txvlan_cfg.default_tag2 = 0; 9849 vport->txvlan_cfg.tag_shift_mode_en = true; 9850 9851 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9852 vport->rxvlan_cfg.strip_tag1_en = false; 9853 vport->rxvlan_cfg.strip_tag2_en = 9854 vport->rxvlan_cfg.rx_vlan_offload_en; 9855 vport->rxvlan_cfg.strip_tag2_discard_en = false; 9856 } else { 9857 vport->rxvlan_cfg.strip_tag1_en = 9858 vport->rxvlan_cfg.rx_vlan_offload_en; 9859 vport->rxvlan_cfg.strip_tag2_en = true; 9860 vport->rxvlan_cfg.strip_tag2_discard_en = true; 9861 } 9862 9863 vport->rxvlan_cfg.strip_tag1_discard_en = false; 9864 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 9865 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 9866 9867 ret = hclge_set_vlan_tx_offload_cfg(vport); 9868 if (ret) 9869 return ret; 9870 9871 return hclge_set_vlan_rx_offload_cfg(vport); 9872 } 9873 9874 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 9875 { 9876 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 9877 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 9878 struct hclge_desc desc; 9879 int status; 9880 9881 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 9882 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 9883 rx_req->ot_fst_vlan_type = 9884 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 9885 rx_req->ot_sec_vlan_type = 9886 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 9887 rx_req->in_fst_vlan_type = 9888 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 9889 rx_req->in_sec_vlan_type = 9890 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 9891 9892 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9893 if (status) { 9894 dev_err(&hdev->pdev->dev, 9895 "Send rxvlan protocol type command fail, ret =%d\n", 9896 status); 9897 return status; 9898 } 9899 9900 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 9901 9902 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data; 9903 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 9904 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 9905 9906 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9907 if (status) 9908 dev_err(&hdev->pdev->dev, 9909 "Send txvlan protocol type command fail, ret =%d\n", 9910 status); 9911 9912 return status; 9913 } 9914 9915 static int hclge_init_vlan_filter(struct hclge_dev *hdev) 9916 { 9917 struct hclge_vport *vport; 9918 bool enable = true; 9919 int ret; 9920 int i; 9921 9922 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9923 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9924 HCLGE_FILTER_FE_EGRESS_V1_B, 9925 true, 0); 9926 9927 /* for revision 0x21, vf vlan filter is per function */ 9928 for (i = 0; i < hdev->num_alloc_vport; i++) { 9929 vport = &hdev->vport[i]; 9930 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9931 HCLGE_FILTER_FE_EGRESS, true, 9932 vport->vport_id); 9933 if (ret) 9934 return ret; 9935 vport->cur_vlan_fltr_en = true; 9936 } 9937 9938 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps) && 9939 !test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, hdev->ae_dev->caps)) 9940 enable = false; 9941 9942 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9943 HCLGE_FILTER_FE_INGRESS, enable, 0); 9944 } 9945 9946 static int hclge_init_vlan_type(struct hclge_dev *hdev) 9947 { 9948 hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q; 9949 hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q; 9950 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q; 9951 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q; 9952 hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q; 9953 hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q; 9954 9955 return hclge_set_vlan_protocol_type(hdev); 9956 } 9957 9958 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev) 9959 { 9960 struct hclge_port_base_vlan_config *cfg; 9961 struct hclge_vport *vport; 9962 int ret; 9963 int i; 9964 9965 for (i = 0; i < hdev->num_alloc_vport; i++) { 9966 vport = &hdev->vport[i]; 9967 cfg = &vport->port_base_vlan_cfg; 9968 9969 ret = hclge_vlan_offload_cfg(vport, cfg->state, 9970 cfg->vlan_info.vlan_tag, 9971 cfg->vlan_info.qos); 9972 if (ret) 9973 return ret; 9974 } 9975 return 0; 9976 } 9977 9978 static int hclge_init_vlan_config(struct hclge_dev *hdev) 9979 { 9980 struct hnae3_handle *handle = &hdev->vport[0].nic; 9981 int ret; 9982 9983 ret = hclge_init_vlan_filter(hdev); 9984 if (ret) 9985 return ret; 9986 9987 ret = hclge_init_vlan_type(hdev); 9988 if (ret) 9989 return ret; 9990 9991 ret = hclge_init_vport_vlan_offload(hdev); 9992 if (ret) 9993 return ret; 9994 9995 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 9996 } 9997 9998 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 9999 bool writen_to_tbl) 10000 { 10001 struct hclge_vport_vlan_cfg *vlan, *tmp; 10002 struct hclge_dev *hdev = vport->back; 10003 10004 mutex_lock(&hdev->vport_lock); 10005 10006 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10007 if (vlan->vlan_id == vlan_id) { 10008 mutex_unlock(&hdev->vport_lock); 10009 return; 10010 } 10011 } 10012 10013 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 10014 if (!vlan) { 10015 mutex_unlock(&hdev->vport_lock); 10016 return; 10017 } 10018 10019 vlan->hd_tbl_status = writen_to_tbl; 10020 vlan->vlan_id = vlan_id; 10021 10022 list_add_tail(&vlan->node, &vport->vlan_list); 10023 mutex_unlock(&hdev->vport_lock); 10024 } 10025 10026 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport) 10027 { 10028 struct hclge_vport_vlan_cfg *vlan, *tmp; 10029 struct hclge_dev *hdev = vport->back; 10030 int ret; 10031 10032 mutex_lock(&hdev->vport_lock); 10033 10034 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10035 if (!vlan->hd_tbl_status) { 10036 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10037 vport->vport_id, 10038 vlan->vlan_id, false); 10039 if (ret) { 10040 dev_err(&hdev->pdev->dev, 10041 "restore vport vlan list failed, ret=%d\n", 10042 ret); 10043 10044 mutex_unlock(&hdev->vport_lock); 10045 return ret; 10046 } 10047 } 10048 vlan->hd_tbl_status = true; 10049 } 10050 10051 mutex_unlock(&hdev->vport_lock); 10052 10053 return 0; 10054 } 10055 10056 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10057 bool is_write_tbl) 10058 { 10059 struct hclge_vport_vlan_cfg *vlan, *tmp; 10060 struct hclge_dev *hdev = vport->back; 10061 10062 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10063 if (vlan->vlan_id == vlan_id) { 10064 if (is_write_tbl && vlan->hd_tbl_status) 10065 hclge_set_vlan_filter_hw(hdev, 10066 htons(ETH_P_8021Q), 10067 vport->vport_id, 10068 vlan_id, 10069 true); 10070 10071 list_del(&vlan->node); 10072 kfree(vlan); 10073 break; 10074 } 10075 } 10076 } 10077 10078 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list) 10079 { 10080 struct hclge_vport_vlan_cfg *vlan, *tmp; 10081 struct hclge_dev *hdev = vport->back; 10082 10083 mutex_lock(&hdev->vport_lock); 10084 10085 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10086 if (vlan->hd_tbl_status) 10087 hclge_set_vlan_filter_hw(hdev, 10088 htons(ETH_P_8021Q), 10089 vport->vport_id, 10090 vlan->vlan_id, 10091 true); 10092 10093 vlan->hd_tbl_status = false; 10094 if (is_del_list) { 10095 list_del(&vlan->node); 10096 kfree(vlan); 10097 } 10098 } 10099 clear_bit(vport->vport_id, hdev->vf_vlan_full); 10100 mutex_unlock(&hdev->vport_lock); 10101 } 10102 10103 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev) 10104 { 10105 struct hclge_vport_vlan_cfg *vlan, *tmp; 10106 struct hclge_vport *vport; 10107 int i; 10108 10109 mutex_lock(&hdev->vport_lock); 10110 10111 for (i = 0; i < hdev->num_alloc_vport; i++) { 10112 vport = &hdev->vport[i]; 10113 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10114 list_del(&vlan->node); 10115 kfree(vlan); 10116 } 10117 } 10118 10119 mutex_unlock(&hdev->vport_lock); 10120 } 10121 10122 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev) 10123 { 10124 struct hclge_vlan_info *vlan_info; 10125 struct hclge_vport *vport; 10126 u16 vlan_proto; 10127 u16 vlan_id; 10128 u16 state; 10129 int vf_id; 10130 int ret; 10131 10132 /* PF should restore all vfs port base vlan */ 10133 for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) { 10134 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM]; 10135 vlan_info = vport->port_base_vlan_cfg.tbl_sta ? 10136 &vport->port_base_vlan_cfg.vlan_info : 10137 &vport->port_base_vlan_cfg.old_vlan_info; 10138 10139 vlan_id = vlan_info->vlan_tag; 10140 vlan_proto = vlan_info->vlan_proto; 10141 state = vport->port_base_vlan_cfg.state; 10142 10143 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) { 10144 clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]); 10145 ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto), 10146 vport->vport_id, 10147 vlan_id, false); 10148 vport->port_base_vlan_cfg.tbl_sta = ret == 0; 10149 } 10150 } 10151 } 10152 10153 void hclge_restore_vport_vlan_table(struct hclge_vport *vport) 10154 { 10155 struct hclge_vport_vlan_cfg *vlan, *tmp; 10156 struct hclge_dev *hdev = vport->back; 10157 int ret; 10158 10159 mutex_lock(&hdev->vport_lock); 10160 10161 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10162 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10163 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10164 vport->vport_id, 10165 vlan->vlan_id, false); 10166 if (ret) 10167 break; 10168 vlan->hd_tbl_status = true; 10169 } 10170 } 10171 10172 mutex_unlock(&hdev->vport_lock); 10173 } 10174 10175 /* For global reset and imp reset, hardware will clear the mac table, 10176 * so we change the mac address state from ACTIVE to TO_ADD, then they 10177 * can be restored in the service task after reset complete. Furtherly, 10178 * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to 10179 * be restored after reset, so just remove these mac nodes from mac_list. 10180 */ 10181 static void hclge_mac_node_convert_for_reset(struct list_head *list) 10182 { 10183 struct hclge_mac_node *mac_node, *tmp; 10184 10185 list_for_each_entry_safe(mac_node, tmp, list, node) { 10186 if (mac_node->state == HCLGE_MAC_ACTIVE) { 10187 mac_node->state = HCLGE_MAC_TO_ADD; 10188 } else if (mac_node->state == HCLGE_MAC_TO_DEL) { 10189 list_del(&mac_node->node); 10190 kfree(mac_node); 10191 } 10192 } 10193 } 10194 10195 void hclge_restore_mac_table_common(struct hclge_vport *vport) 10196 { 10197 spin_lock_bh(&vport->mac_list_lock); 10198 10199 hclge_mac_node_convert_for_reset(&vport->uc_mac_list); 10200 hclge_mac_node_convert_for_reset(&vport->mc_mac_list); 10201 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 10202 10203 spin_unlock_bh(&vport->mac_list_lock); 10204 } 10205 10206 static void hclge_restore_hw_table(struct hclge_dev *hdev) 10207 { 10208 struct hclge_vport *vport = &hdev->vport[0]; 10209 struct hnae3_handle *handle = &vport->nic; 10210 10211 hclge_restore_mac_table_common(vport); 10212 hclge_restore_vport_port_base_vlan_config(hdev); 10213 hclge_restore_vport_vlan_table(vport); 10214 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 10215 hclge_restore_fd_entries(handle); 10216 } 10217 10218 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 10219 { 10220 struct hclge_vport *vport = hclge_get_vport(handle); 10221 10222 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10223 vport->rxvlan_cfg.strip_tag1_en = false; 10224 vport->rxvlan_cfg.strip_tag2_en = enable; 10225 vport->rxvlan_cfg.strip_tag2_discard_en = false; 10226 } else { 10227 vport->rxvlan_cfg.strip_tag1_en = enable; 10228 vport->rxvlan_cfg.strip_tag2_en = true; 10229 vport->rxvlan_cfg.strip_tag2_discard_en = true; 10230 } 10231 10232 vport->rxvlan_cfg.strip_tag1_discard_en = false; 10233 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 10234 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 10235 vport->rxvlan_cfg.rx_vlan_offload_en = enable; 10236 10237 return hclge_set_vlan_rx_offload_cfg(vport); 10238 } 10239 10240 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport) 10241 { 10242 struct hclge_dev *hdev = vport->back; 10243 10244 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 10245 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state); 10246 } 10247 10248 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport, 10249 u16 port_base_vlan_state, 10250 struct hclge_vlan_info *new_info, 10251 struct hclge_vlan_info *old_info) 10252 { 10253 struct hclge_dev *hdev = vport->back; 10254 int ret; 10255 10256 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) { 10257 hclge_rm_vport_all_vlan_table(vport, false); 10258 /* force clear VLAN 0 */ 10259 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0); 10260 if (ret) 10261 return ret; 10262 return hclge_set_vlan_filter_hw(hdev, 10263 htons(new_info->vlan_proto), 10264 vport->vport_id, 10265 new_info->vlan_tag, 10266 false); 10267 } 10268 10269 vport->port_base_vlan_cfg.tbl_sta = false; 10270 10271 /* force add VLAN 0 */ 10272 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0); 10273 if (ret) 10274 return ret; 10275 10276 ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto), 10277 vport->vport_id, old_info->vlan_tag, 10278 true); 10279 if (ret) 10280 return ret; 10281 10282 return hclge_add_vport_all_vlan_table(vport); 10283 } 10284 10285 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg, 10286 const struct hclge_vlan_info *old_cfg) 10287 { 10288 if (new_cfg->vlan_tag != old_cfg->vlan_tag) 10289 return true; 10290 10291 if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0)) 10292 return true; 10293 10294 return false; 10295 } 10296 10297 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport, 10298 struct hclge_vlan_info *new_info, 10299 struct hclge_vlan_info *old_info) 10300 { 10301 struct hclge_dev *hdev = vport->back; 10302 int ret; 10303 10304 /* add new VLAN tag */ 10305 ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto), 10306 vport->vport_id, new_info->vlan_tag, 10307 false); 10308 if (ret) 10309 return ret; 10310 10311 vport->port_base_vlan_cfg.tbl_sta = false; 10312 /* remove old VLAN tag */ 10313 if (old_info->vlan_tag == 0) 10314 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, 10315 true, 0); 10316 else 10317 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10318 vport->vport_id, 10319 old_info->vlan_tag, true); 10320 if (ret) 10321 dev_err(&hdev->pdev->dev, 10322 "failed to clear vport%u port base vlan %u, ret = %d.\n", 10323 vport->vport_id, old_info->vlan_tag, ret); 10324 10325 return ret; 10326 } 10327 10328 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 10329 struct hclge_vlan_info *vlan_info) 10330 { 10331 struct hnae3_handle *nic = &vport->nic; 10332 struct hclge_vlan_info *old_vlan_info; 10333 int ret; 10334 10335 old_vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10336 10337 ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag, 10338 vlan_info->qos); 10339 if (ret) 10340 return ret; 10341 10342 if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info)) 10343 goto out; 10344 10345 if (state == HNAE3_PORT_BASE_VLAN_MODIFY) 10346 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info, 10347 old_vlan_info); 10348 else 10349 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info, 10350 old_vlan_info); 10351 if (ret) 10352 return ret; 10353 10354 out: 10355 vport->port_base_vlan_cfg.state = state; 10356 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 10357 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 10358 else 10359 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 10360 10361 vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info; 10362 vport->port_base_vlan_cfg.vlan_info = *vlan_info; 10363 vport->port_base_vlan_cfg.tbl_sta = true; 10364 hclge_set_vport_vlan_fltr_change(vport); 10365 10366 return 0; 10367 } 10368 10369 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport, 10370 enum hnae3_port_base_vlan_state state, 10371 u16 vlan, u8 qos) 10372 { 10373 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10374 if (!vlan && !qos) 10375 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10376 10377 return HNAE3_PORT_BASE_VLAN_ENABLE; 10378 } 10379 10380 if (!vlan && !qos) 10381 return HNAE3_PORT_BASE_VLAN_DISABLE; 10382 10383 if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan && 10384 vport->port_base_vlan_cfg.vlan_info.qos == qos) 10385 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10386 10387 return HNAE3_PORT_BASE_VLAN_MODIFY; 10388 } 10389 10390 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 10391 u16 vlan, u8 qos, __be16 proto) 10392 { 10393 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 10394 struct hclge_vport *vport = hclge_get_vport(handle); 10395 struct hclge_dev *hdev = vport->back; 10396 struct hclge_vlan_info vlan_info; 10397 u16 state; 10398 int ret; 10399 10400 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 10401 return -EOPNOTSUPP; 10402 10403 vport = hclge_get_vf_vport(hdev, vfid); 10404 if (!vport) 10405 return -EINVAL; 10406 10407 /* qos is a 3 bits value, so can not be bigger than 7 */ 10408 if (vlan > VLAN_N_VID - 1 || qos > 7) 10409 return -EINVAL; 10410 if (proto != htons(ETH_P_8021Q)) 10411 return -EPROTONOSUPPORT; 10412 10413 state = hclge_get_port_base_vlan_state(vport, 10414 vport->port_base_vlan_cfg.state, 10415 vlan, qos); 10416 if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE) 10417 return 0; 10418 10419 vlan_info.vlan_tag = vlan; 10420 vlan_info.qos = qos; 10421 vlan_info.vlan_proto = ntohs(proto); 10422 10423 ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info); 10424 if (ret) { 10425 dev_err(&hdev->pdev->dev, 10426 "failed to update port base vlan for vf %d, ret = %d\n", 10427 vfid, ret); 10428 return ret; 10429 } 10430 10431 /* there is a timewindow for PF to know VF unalive, it may 10432 * cause send mailbox fail, but it doesn't matter, VF will 10433 * query it when reinit. 10434 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based 10435 * VLAN state. 10436 */ 10437 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 10438 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 10439 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0], 10440 vport->vport_id, 10441 state, 10442 &vlan_info); 10443 else 10444 set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, 10445 &vport->need_notify); 10446 } 10447 return 0; 10448 } 10449 10450 static void hclge_clear_vf_vlan(struct hclge_dev *hdev) 10451 { 10452 struct hclge_vlan_info *vlan_info; 10453 struct hclge_vport *vport; 10454 int ret; 10455 int vf; 10456 10457 /* clear port base vlan for all vf */ 10458 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 10459 vport = &hdev->vport[vf]; 10460 vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10461 10462 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10463 vport->vport_id, 10464 vlan_info->vlan_tag, true); 10465 if (ret) 10466 dev_err(&hdev->pdev->dev, 10467 "failed to clear vf vlan for vf%d, ret = %d\n", 10468 vf - HCLGE_VF_VPORT_START_NUM, ret); 10469 } 10470 } 10471 10472 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 10473 u16 vlan_id, bool is_kill) 10474 { 10475 struct hclge_vport *vport = hclge_get_vport(handle); 10476 struct hclge_dev *hdev = vport->back; 10477 bool writen_to_tbl = false; 10478 int ret = 0; 10479 10480 /* When device is resetting or reset failed, firmware is unable to 10481 * handle mailbox. Just record the vlan id, and remove it after 10482 * reset finished. 10483 */ 10484 mutex_lock(&hdev->vport_lock); 10485 if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 10486 test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) { 10487 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10488 mutex_unlock(&hdev->vport_lock); 10489 return -EBUSY; 10490 } else if (!is_kill && test_bit(vlan_id, vport->vlan_del_fail_bmap)) { 10491 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10492 } 10493 mutex_unlock(&hdev->vport_lock); 10494 10495 /* when port base vlan enabled, we use port base vlan as the vlan 10496 * filter entry. In this case, we don't update vlan filter table 10497 * when user add new vlan or remove exist vlan, just update the vport 10498 * vlan list. The vlan id in vlan list will be writen in vlan filter 10499 * table until port base vlan disabled 10500 */ 10501 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10502 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, 10503 vlan_id, is_kill); 10504 writen_to_tbl = true; 10505 } 10506 10507 if (!ret) { 10508 if (!is_kill) { 10509 hclge_add_vport_vlan_table(vport, vlan_id, 10510 writen_to_tbl); 10511 } else if (is_kill && vlan_id != 0) { 10512 mutex_lock(&hdev->vport_lock); 10513 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10514 mutex_unlock(&hdev->vport_lock); 10515 } 10516 } else if (is_kill) { 10517 /* when remove hw vlan filter failed, record the vlan id, 10518 * and try to remove it from hw later, to be consistence 10519 * with stack 10520 */ 10521 mutex_lock(&hdev->vport_lock); 10522 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10523 mutex_unlock(&hdev->vport_lock); 10524 } 10525 10526 hclge_set_vport_vlan_fltr_change(vport); 10527 10528 return ret; 10529 } 10530 10531 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev) 10532 { 10533 struct hclge_vport *vport; 10534 int ret; 10535 u16 i; 10536 10537 for (i = 0; i < hdev->num_alloc_vport; i++) { 10538 vport = &hdev->vport[i]; 10539 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10540 &vport->state)) 10541 continue; 10542 10543 ret = hclge_enable_vport_vlan_filter(vport, 10544 vport->req_vlan_fltr_en); 10545 if (ret) { 10546 dev_err(&hdev->pdev->dev, 10547 "failed to sync vlan filter state for vport%u, ret = %d\n", 10548 vport->vport_id, ret); 10549 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10550 &vport->state); 10551 return; 10552 } 10553 } 10554 } 10555 10556 static void hclge_sync_vlan_filter(struct hclge_dev *hdev) 10557 { 10558 #define HCLGE_MAX_SYNC_COUNT 60 10559 10560 int i, ret, sync_cnt = 0; 10561 u16 vlan_id; 10562 10563 mutex_lock(&hdev->vport_lock); 10564 /* start from vport 1 for PF is always alive */ 10565 for (i = 0; i < hdev->num_alloc_vport; i++) { 10566 struct hclge_vport *vport = &hdev->vport[i]; 10567 10568 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10569 VLAN_N_VID); 10570 while (vlan_id != VLAN_N_VID) { 10571 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10572 vport->vport_id, vlan_id, 10573 true); 10574 if (ret && ret != -EINVAL) { 10575 mutex_unlock(&hdev->vport_lock); 10576 return; 10577 } 10578 10579 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10580 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10581 hclge_set_vport_vlan_fltr_change(vport); 10582 10583 sync_cnt++; 10584 if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) { 10585 mutex_unlock(&hdev->vport_lock); 10586 return; 10587 } 10588 10589 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10590 VLAN_N_VID); 10591 } 10592 } 10593 mutex_unlock(&hdev->vport_lock); 10594 10595 hclge_sync_vlan_fltr_state(hdev); 10596 } 10597 10598 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps) 10599 { 10600 struct hclge_config_max_frm_size_cmd *req; 10601 struct hclge_desc desc; 10602 10603 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 10604 10605 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 10606 req->max_frm_size = cpu_to_le16(new_mps); 10607 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 10608 10609 return hclge_cmd_send(&hdev->hw, &desc, 1); 10610 } 10611 10612 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 10613 { 10614 struct hclge_vport *vport = hclge_get_vport(handle); 10615 10616 return hclge_set_vport_mtu(vport, new_mtu); 10617 } 10618 10619 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) 10620 { 10621 struct hclge_dev *hdev = vport->back; 10622 int i, max_frm_size, ret; 10623 10624 /* HW supprt 2 layer vlan */ 10625 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 10626 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 10627 max_frm_size > hdev->ae_dev->dev_specs.max_frm_size) 10628 return -EINVAL; 10629 10630 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 10631 mutex_lock(&hdev->vport_lock); 10632 /* VF's mps must fit within hdev->mps */ 10633 if (vport->vport_id && max_frm_size > hdev->mps) { 10634 mutex_unlock(&hdev->vport_lock); 10635 return -EINVAL; 10636 } else if (vport->vport_id) { 10637 vport->mps = max_frm_size; 10638 mutex_unlock(&hdev->vport_lock); 10639 return 0; 10640 } 10641 10642 /* PF's mps must be greater then VF's mps */ 10643 for (i = 1; i < hdev->num_alloc_vport; i++) 10644 if (max_frm_size < hdev->vport[i].mps) { 10645 dev_err(&hdev->pdev->dev, 10646 "failed to set pf mtu for less than vport %d, mps = %u.\n", 10647 i, hdev->vport[i].mps); 10648 mutex_unlock(&hdev->vport_lock); 10649 return -EINVAL; 10650 } 10651 10652 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 10653 10654 ret = hclge_set_mac_mtu(hdev, max_frm_size); 10655 if (ret) { 10656 dev_err(&hdev->pdev->dev, 10657 "Change mtu fail, ret =%d\n", ret); 10658 goto out; 10659 } 10660 10661 hdev->mps = max_frm_size; 10662 vport->mps = max_frm_size; 10663 10664 ret = hclge_buffer_alloc(hdev); 10665 if (ret) 10666 dev_err(&hdev->pdev->dev, 10667 "Allocate buffer fail, ret =%d\n", ret); 10668 10669 out: 10670 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 10671 mutex_unlock(&hdev->vport_lock); 10672 return ret; 10673 } 10674 10675 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id, 10676 bool enable) 10677 { 10678 struct hclge_reset_tqp_queue_cmd *req; 10679 struct hclge_desc desc; 10680 int ret; 10681 10682 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 10683 10684 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10685 req->tqp_id = cpu_to_le16(queue_id); 10686 if (enable) 10687 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U); 10688 10689 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10690 if (ret) { 10691 dev_err(&hdev->pdev->dev, 10692 "Send tqp reset cmd error, status =%d\n", ret); 10693 return ret; 10694 } 10695 10696 return 0; 10697 } 10698 10699 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id, 10700 u8 *reset_status) 10701 { 10702 struct hclge_reset_tqp_queue_cmd *req; 10703 struct hclge_desc desc; 10704 int ret; 10705 10706 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 10707 10708 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10709 req->tqp_id = cpu_to_le16(queue_id); 10710 10711 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10712 if (ret) { 10713 dev_err(&hdev->pdev->dev, 10714 "Get reset status error, status =%d\n", ret); 10715 return ret; 10716 } 10717 10718 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 10719 10720 return 0; 10721 } 10722 10723 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id) 10724 { 10725 struct hclge_comm_tqp *tqp; 10726 struct hnae3_queue *queue; 10727 10728 queue = handle->kinfo.tqp[queue_id]; 10729 tqp = container_of(queue, struct hclge_comm_tqp, q); 10730 10731 return tqp->index; 10732 } 10733 10734 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle) 10735 { 10736 struct hclge_vport *vport = hclge_get_vport(handle); 10737 struct hclge_dev *hdev = vport->back; 10738 u16 reset_try_times = 0; 10739 u8 reset_status; 10740 u16 queue_gid; 10741 int ret; 10742 u16 i; 10743 10744 for (i = 0; i < handle->kinfo.num_tqps; i++) { 10745 queue_gid = hclge_covert_handle_qid_global(handle, i); 10746 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true); 10747 if (ret) { 10748 dev_err(&hdev->pdev->dev, 10749 "failed to send reset tqp cmd, ret = %d\n", 10750 ret); 10751 return ret; 10752 } 10753 10754 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 10755 ret = hclge_get_reset_status(hdev, queue_gid, 10756 &reset_status); 10757 if (ret) 10758 return ret; 10759 10760 if (reset_status) 10761 break; 10762 10763 /* Wait for tqp hw reset */ 10764 usleep_range(1000, 1200); 10765 } 10766 10767 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 10768 dev_err(&hdev->pdev->dev, 10769 "wait for tqp hw reset timeout\n"); 10770 return -ETIME; 10771 } 10772 10773 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false); 10774 if (ret) { 10775 dev_err(&hdev->pdev->dev, 10776 "failed to deassert soft reset, ret = %d\n", 10777 ret); 10778 return ret; 10779 } 10780 reset_try_times = 0; 10781 } 10782 return 0; 10783 } 10784 10785 static int hclge_reset_rcb(struct hnae3_handle *handle) 10786 { 10787 #define HCLGE_RESET_RCB_NOT_SUPPORT 0U 10788 #define HCLGE_RESET_RCB_SUCCESS 1U 10789 10790 struct hclge_vport *vport = hclge_get_vport(handle); 10791 struct hclge_dev *hdev = vport->back; 10792 struct hclge_reset_cmd *req; 10793 struct hclge_desc desc; 10794 u8 return_status; 10795 u16 queue_gid; 10796 int ret; 10797 10798 queue_gid = hclge_covert_handle_qid_global(handle, 0); 10799 10800 req = (struct hclge_reset_cmd *)desc.data; 10801 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 10802 hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1); 10803 req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid); 10804 req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps); 10805 10806 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10807 if (ret) { 10808 dev_err(&hdev->pdev->dev, 10809 "failed to send rcb reset cmd, ret = %d\n", ret); 10810 return ret; 10811 } 10812 10813 return_status = req->fun_reset_rcb_return_status; 10814 if (return_status == HCLGE_RESET_RCB_SUCCESS) 10815 return 0; 10816 10817 if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) { 10818 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n", 10819 return_status); 10820 return -EIO; 10821 } 10822 10823 /* if reset rcb cmd is unsupported, we need to send reset tqp cmd 10824 * again to reset all tqps 10825 */ 10826 return hclge_reset_tqp_cmd(handle); 10827 } 10828 10829 int hclge_reset_tqp(struct hnae3_handle *handle) 10830 { 10831 struct hclge_vport *vport = hclge_get_vport(handle); 10832 struct hclge_dev *hdev = vport->back; 10833 int ret; 10834 10835 /* only need to disable PF's tqp */ 10836 if (!vport->vport_id) { 10837 ret = hclge_tqp_enable(handle, false); 10838 if (ret) { 10839 dev_err(&hdev->pdev->dev, 10840 "failed to disable tqp, ret = %d\n", ret); 10841 return ret; 10842 } 10843 } 10844 10845 return hclge_reset_rcb(handle); 10846 } 10847 10848 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 10849 { 10850 struct hclge_vport *vport = hclge_get_vport(handle); 10851 struct hclge_dev *hdev = vport->back; 10852 10853 return hdev->fw_version; 10854 } 10855 10856 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10857 { 10858 struct phy_device *phydev = hdev->hw.mac.phydev; 10859 10860 if (!phydev) 10861 return; 10862 10863 phy_set_asym_pause(phydev, rx_en, tx_en); 10864 } 10865 10866 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10867 { 10868 int ret; 10869 10870 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 10871 return 0; 10872 10873 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 10874 if (ret) 10875 dev_err(&hdev->pdev->dev, 10876 "configure pauseparam error, ret = %d.\n", ret); 10877 10878 return ret; 10879 } 10880 10881 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 10882 { 10883 struct phy_device *phydev = hdev->hw.mac.phydev; 10884 u16 remote_advertising = 0; 10885 u16 local_advertising; 10886 u32 rx_pause, tx_pause; 10887 u8 flowctl; 10888 10889 if (!phydev->link) 10890 return 0; 10891 10892 if (!phydev->autoneg) 10893 return hclge_mac_pause_setup_hw(hdev); 10894 10895 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising); 10896 10897 if (phydev->pause) 10898 remote_advertising = LPA_PAUSE_CAP; 10899 10900 if (phydev->asym_pause) 10901 remote_advertising |= LPA_PAUSE_ASYM; 10902 10903 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 10904 remote_advertising); 10905 tx_pause = flowctl & FLOW_CTRL_TX; 10906 rx_pause = flowctl & FLOW_CTRL_RX; 10907 10908 if (phydev->duplex == HCLGE_MAC_HALF) { 10909 tx_pause = 0; 10910 rx_pause = 0; 10911 } 10912 10913 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 10914 } 10915 10916 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 10917 u32 *rx_en, u32 *tx_en) 10918 { 10919 struct hclge_vport *vport = hclge_get_vport(handle); 10920 struct hclge_dev *hdev = vport->back; 10921 u8 media_type = hdev->hw.mac.media_type; 10922 10923 *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ? 10924 hclge_get_autoneg(handle) : 0; 10925 10926 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 10927 *rx_en = 0; 10928 *tx_en = 0; 10929 return; 10930 } 10931 10932 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 10933 *rx_en = 1; 10934 *tx_en = 0; 10935 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 10936 *tx_en = 1; 10937 *rx_en = 0; 10938 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 10939 *rx_en = 1; 10940 *tx_en = 1; 10941 } else { 10942 *rx_en = 0; 10943 *tx_en = 0; 10944 } 10945 } 10946 10947 static void hclge_record_user_pauseparam(struct hclge_dev *hdev, 10948 u32 rx_en, u32 tx_en) 10949 { 10950 if (rx_en && tx_en) 10951 hdev->fc_mode_last_time = HCLGE_FC_FULL; 10952 else if (rx_en && !tx_en) 10953 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 10954 else if (!rx_en && tx_en) 10955 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 10956 else 10957 hdev->fc_mode_last_time = HCLGE_FC_NONE; 10958 10959 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 10960 } 10961 10962 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 10963 u32 rx_en, u32 tx_en) 10964 { 10965 struct hclge_vport *vport = hclge_get_vport(handle); 10966 struct hclge_dev *hdev = vport->back; 10967 struct phy_device *phydev = hdev->hw.mac.phydev; 10968 u32 fc_autoneg; 10969 10970 if (phydev || hnae3_dev_phy_imp_supported(hdev)) { 10971 fc_autoneg = hclge_get_autoneg(handle); 10972 if (auto_neg != fc_autoneg) { 10973 dev_info(&hdev->pdev->dev, 10974 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 10975 return -EOPNOTSUPP; 10976 } 10977 } 10978 10979 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 10980 dev_info(&hdev->pdev->dev, 10981 "Priority flow control enabled. Cannot set link flow control.\n"); 10982 return -EOPNOTSUPP; 10983 } 10984 10985 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 10986 10987 hclge_record_user_pauseparam(hdev, rx_en, tx_en); 10988 10989 if (!auto_neg || hnae3_dev_phy_imp_supported(hdev)) 10990 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 10991 10992 if (phydev) 10993 return phy_start_aneg(phydev); 10994 10995 return -EOPNOTSUPP; 10996 } 10997 10998 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 10999 u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num) 11000 { 11001 struct hclge_vport *vport = hclge_get_vport(handle); 11002 struct hclge_dev *hdev = vport->back; 11003 11004 if (speed) 11005 *speed = hdev->hw.mac.speed; 11006 if (duplex) 11007 *duplex = hdev->hw.mac.duplex; 11008 if (auto_neg) 11009 *auto_neg = hdev->hw.mac.autoneg; 11010 if (lane_num) 11011 *lane_num = hdev->hw.mac.lane_num; 11012 } 11013 11014 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type, 11015 u8 *module_type) 11016 { 11017 struct hclge_vport *vport = hclge_get_vport(handle); 11018 struct hclge_dev *hdev = vport->back; 11019 11020 /* When nic is down, the service task is not running, doesn't update 11021 * the port information per second. Query the port information before 11022 * return the media type, ensure getting the correct media information. 11023 */ 11024 hclge_update_port_info(hdev); 11025 11026 if (media_type) 11027 *media_type = hdev->hw.mac.media_type; 11028 11029 if (module_type) 11030 *module_type = hdev->hw.mac.module_type; 11031 } 11032 11033 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 11034 u8 *tp_mdix_ctrl, u8 *tp_mdix) 11035 { 11036 struct hclge_vport *vport = hclge_get_vport(handle); 11037 struct hclge_dev *hdev = vport->back; 11038 struct phy_device *phydev = hdev->hw.mac.phydev; 11039 int mdix_ctrl, mdix, is_resolved; 11040 unsigned int retval; 11041 11042 if (!phydev) { 11043 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11044 *tp_mdix = ETH_TP_MDI_INVALID; 11045 return; 11046 } 11047 11048 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 11049 11050 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 11051 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 11052 HCLGE_PHY_MDIX_CTRL_S); 11053 11054 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 11055 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 11056 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 11057 11058 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 11059 11060 switch (mdix_ctrl) { 11061 case 0x0: 11062 *tp_mdix_ctrl = ETH_TP_MDI; 11063 break; 11064 case 0x1: 11065 *tp_mdix_ctrl = ETH_TP_MDI_X; 11066 break; 11067 case 0x3: 11068 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 11069 break; 11070 default: 11071 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11072 break; 11073 } 11074 11075 if (!is_resolved) 11076 *tp_mdix = ETH_TP_MDI_INVALID; 11077 else if (mdix) 11078 *tp_mdix = ETH_TP_MDI_X; 11079 else 11080 *tp_mdix = ETH_TP_MDI; 11081 } 11082 11083 static void hclge_info_show(struct hclge_dev *hdev) 11084 { 11085 struct hnae3_handle *handle = &hdev->vport->nic; 11086 struct device *dev = &hdev->pdev->dev; 11087 11088 dev_info(dev, "PF info begin:\n"); 11089 11090 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 11091 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 11092 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 11093 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 11094 dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs); 11095 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 11096 dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size); 11097 dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size); 11098 dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size); 11099 dev_info(dev, "This is %s PF\n", 11100 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main"); 11101 dev_info(dev, "DCB %s\n", 11102 handle->kinfo.tc_info.dcb_ets_active ? "enable" : "disable"); 11103 dev_info(dev, "MQPRIO %s\n", 11104 handle->kinfo.tc_info.mqprio_active ? "enable" : "disable"); 11105 dev_info(dev, "Default tx spare buffer size: %u\n", 11106 hdev->tx_spare_buf_size); 11107 11108 dev_info(dev, "PF info end.\n"); 11109 } 11110 11111 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 11112 struct hclge_vport *vport) 11113 { 11114 struct hnae3_client *client = vport->nic.client; 11115 struct hclge_dev *hdev = ae_dev->priv; 11116 int rst_cnt = hdev->rst_stats.reset_cnt; 11117 int ret; 11118 11119 ret = client->ops->init_instance(&vport->nic); 11120 if (ret) 11121 return ret; 11122 11123 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11124 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11125 rst_cnt != hdev->rst_stats.reset_cnt) { 11126 ret = -EBUSY; 11127 goto init_nic_err; 11128 } 11129 11130 /* Enable nic hw error interrupts */ 11131 ret = hclge_config_nic_hw_error(hdev, true); 11132 if (ret) { 11133 dev_err(&ae_dev->pdev->dev, 11134 "fail(%d) to enable hw error interrupts\n", ret); 11135 goto init_nic_err; 11136 } 11137 11138 hnae3_set_client_init_flag(client, ae_dev, 1); 11139 11140 if (netif_msg_drv(&hdev->vport->nic)) 11141 hclge_info_show(hdev); 11142 11143 return ret; 11144 11145 init_nic_err: 11146 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11147 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11148 msleep(HCLGE_WAIT_RESET_DONE); 11149 11150 client->ops->uninit_instance(&vport->nic, 0); 11151 11152 return ret; 11153 } 11154 11155 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 11156 struct hclge_vport *vport) 11157 { 11158 struct hclge_dev *hdev = ae_dev->priv; 11159 struct hnae3_client *client; 11160 int rst_cnt; 11161 int ret; 11162 11163 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 11164 !hdev->nic_client) 11165 return 0; 11166 11167 client = hdev->roce_client; 11168 ret = hclge_init_roce_base_info(vport); 11169 if (ret) 11170 return ret; 11171 11172 rst_cnt = hdev->rst_stats.reset_cnt; 11173 ret = client->ops->init_instance(&vport->roce); 11174 if (ret) 11175 return ret; 11176 11177 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11178 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11179 rst_cnt != hdev->rst_stats.reset_cnt) { 11180 ret = -EBUSY; 11181 goto init_roce_err; 11182 } 11183 11184 /* Enable roce ras interrupts */ 11185 ret = hclge_config_rocee_ras_interrupt(hdev, true); 11186 if (ret) { 11187 dev_err(&ae_dev->pdev->dev, 11188 "fail(%d) to enable roce ras interrupts\n", ret); 11189 goto init_roce_err; 11190 } 11191 11192 hnae3_set_client_init_flag(client, ae_dev, 1); 11193 11194 return 0; 11195 11196 init_roce_err: 11197 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11198 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11199 msleep(HCLGE_WAIT_RESET_DONE); 11200 11201 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11202 11203 return ret; 11204 } 11205 11206 static int hclge_init_client_instance(struct hnae3_client *client, 11207 struct hnae3_ae_dev *ae_dev) 11208 { 11209 struct hclge_dev *hdev = ae_dev->priv; 11210 struct hclge_vport *vport = &hdev->vport[0]; 11211 int ret; 11212 11213 switch (client->type) { 11214 case HNAE3_CLIENT_KNIC: 11215 hdev->nic_client = client; 11216 vport->nic.client = client; 11217 ret = hclge_init_nic_client_instance(ae_dev, vport); 11218 if (ret) 11219 goto clear_nic; 11220 11221 ret = hclge_init_roce_client_instance(ae_dev, vport); 11222 if (ret) 11223 goto clear_roce; 11224 11225 break; 11226 case HNAE3_CLIENT_ROCE: 11227 if (hnae3_dev_roce_supported(hdev)) { 11228 hdev->roce_client = client; 11229 vport->roce.client = client; 11230 } 11231 11232 ret = hclge_init_roce_client_instance(ae_dev, vport); 11233 if (ret) 11234 goto clear_roce; 11235 11236 break; 11237 default: 11238 return -EINVAL; 11239 } 11240 11241 return 0; 11242 11243 clear_nic: 11244 hdev->nic_client = NULL; 11245 vport->nic.client = NULL; 11246 return ret; 11247 clear_roce: 11248 hdev->roce_client = NULL; 11249 vport->roce.client = NULL; 11250 return ret; 11251 } 11252 11253 static bool hclge_uninit_need_wait(struct hclge_dev *hdev) 11254 { 11255 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11256 test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 11257 } 11258 11259 static void hclge_uninit_client_instance(struct hnae3_client *client, 11260 struct hnae3_ae_dev *ae_dev) 11261 { 11262 struct hclge_dev *hdev = ae_dev->priv; 11263 struct hclge_vport *vport = &hdev->vport[0]; 11264 11265 if (hdev->roce_client) { 11266 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11267 while (hclge_uninit_need_wait(hdev)) 11268 msleep(HCLGE_WAIT_RESET_DONE); 11269 11270 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11271 hdev->roce_client = NULL; 11272 vport->roce.client = NULL; 11273 } 11274 if (client->type == HNAE3_CLIENT_ROCE) 11275 return; 11276 if (hdev->nic_client && client->ops->uninit_instance) { 11277 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11278 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11279 msleep(HCLGE_WAIT_RESET_DONE); 11280 11281 client->ops->uninit_instance(&vport->nic, 0); 11282 hdev->nic_client = NULL; 11283 vport->nic.client = NULL; 11284 } 11285 } 11286 11287 static int hclge_dev_mem_map(struct hclge_dev *hdev) 11288 { 11289 struct pci_dev *pdev = hdev->pdev; 11290 struct hclge_hw *hw = &hdev->hw; 11291 11292 /* for device does not have device memory, return directly */ 11293 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR))) 11294 return 0; 11295 11296 hw->hw.mem_base = 11297 devm_ioremap_wc(&pdev->dev, 11298 pci_resource_start(pdev, HCLGE_MEM_BAR), 11299 pci_resource_len(pdev, HCLGE_MEM_BAR)); 11300 if (!hw->hw.mem_base) { 11301 dev_err(&pdev->dev, "failed to map device memory\n"); 11302 return -EFAULT; 11303 } 11304 11305 return 0; 11306 } 11307 11308 static int hclge_pci_init(struct hclge_dev *hdev) 11309 { 11310 struct pci_dev *pdev = hdev->pdev; 11311 struct hclge_hw *hw; 11312 int ret; 11313 11314 ret = pci_enable_device(pdev); 11315 if (ret) { 11316 dev_err(&pdev->dev, "failed to enable PCI device\n"); 11317 return ret; 11318 } 11319 11320 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 11321 if (ret) { 11322 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 11323 if (ret) { 11324 dev_err(&pdev->dev, 11325 "can't set consistent PCI DMA"); 11326 goto err_disable_device; 11327 } 11328 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 11329 } 11330 11331 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 11332 if (ret) { 11333 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 11334 goto err_disable_device; 11335 } 11336 11337 pci_set_master(pdev); 11338 hw = &hdev->hw; 11339 hw->hw.io_base = pcim_iomap(pdev, 2, 0); 11340 if (!hw->hw.io_base) { 11341 dev_err(&pdev->dev, "Can't map configuration register space\n"); 11342 ret = -ENOMEM; 11343 goto err_release_regions; 11344 } 11345 11346 ret = hclge_dev_mem_map(hdev); 11347 if (ret) 11348 goto err_unmap_io_base; 11349 11350 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 11351 11352 return 0; 11353 11354 err_unmap_io_base: 11355 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11356 err_release_regions: 11357 pci_release_regions(pdev); 11358 err_disable_device: 11359 pci_disable_device(pdev); 11360 11361 return ret; 11362 } 11363 11364 static void hclge_pci_uninit(struct hclge_dev *hdev) 11365 { 11366 struct pci_dev *pdev = hdev->pdev; 11367 11368 if (hdev->hw.hw.mem_base) 11369 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 11370 11371 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11372 pci_free_irq_vectors(pdev); 11373 pci_release_mem_regions(pdev); 11374 pci_disable_device(pdev); 11375 } 11376 11377 static void hclge_state_init(struct hclge_dev *hdev) 11378 { 11379 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 11380 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11381 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 11382 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11383 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 11384 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 11385 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 11386 } 11387 11388 static void hclge_state_uninit(struct hclge_dev *hdev) 11389 { 11390 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11391 set_bit(HCLGE_STATE_REMOVING, &hdev->state); 11392 11393 if (hdev->reset_timer.function) 11394 del_timer_sync(&hdev->reset_timer); 11395 if (hdev->service_task.work.func) 11396 cancel_delayed_work_sync(&hdev->service_task); 11397 } 11398 11399 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 11400 enum hnae3_reset_type rst_type) 11401 { 11402 #define HCLGE_RESET_RETRY_WAIT_MS 500 11403 #define HCLGE_RESET_RETRY_CNT 5 11404 11405 struct hclge_dev *hdev = ae_dev->priv; 11406 int retry_cnt = 0; 11407 int ret; 11408 11409 while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) { 11410 down(&hdev->reset_sem); 11411 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11412 hdev->reset_type = rst_type; 11413 ret = hclge_reset_prepare(hdev); 11414 if (!ret && !hdev->reset_pending) 11415 break; 11416 11417 dev_err(&hdev->pdev->dev, 11418 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 11419 ret, hdev->reset_pending, retry_cnt); 11420 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11421 up(&hdev->reset_sem); 11422 msleep(HCLGE_RESET_RETRY_WAIT_MS); 11423 } 11424 11425 /* disable misc vector before reset done */ 11426 hclge_enable_vector(&hdev->misc_vector, false); 11427 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 11428 11429 if (hdev->reset_type == HNAE3_FLR_RESET) 11430 hdev->rst_stats.flr_rst_cnt++; 11431 } 11432 11433 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev) 11434 { 11435 struct hclge_dev *hdev = ae_dev->priv; 11436 int ret; 11437 11438 hclge_enable_vector(&hdev->misc_vector, true); 11439 11440 ret = hclge_reset_rebuild(hdev); 11441 if (ret) 11442 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret); 11443 11444 hdev->reset_type = HNAE3_NONE_RESET; 11445 if (test_and_clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11446 up(&hdev->reset_sem); 11447 } 11448 11449 static void hclge_clear_resetting_state(struct hclge_dev *hdev) 11450 { 11451 u16 i; 11452 11453 for (i = 0; i < hdev->num_alloc_vport; i++) { 11454 struct hclge_vport *vport = &hdev->vport[i]; 11455 int ret; 11456 11457 /* Send cmd to clear vport's FUNC_RST_ING */ 11458 ret = hclge_set_vf_rst(hdev, vport->vport_id, false); 11459 if (ret) 11460 dev_warn(&hdev->pdev->dev, 11461 "clear vport(%u) rst failed %d!\n", 11462 vport->vport_id, ret); 11463 } 11464 } 11465 11466 static int hclge_clear_hw_resource(struct hclge_dev *hdev) 11467 { 11468 struct hclge_desc desc; 11469 int ret; 11470 11471 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false); 11472 11473 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11474 /* This new command is only supported by new firmware, it will 11475 * fail with older firmware. Error value -EOPNOSUPP can only be 11476 * returned by older firmware running this command, to keep code 11477 * backward compatible we will override this value and return 11478 * success. 11479 */ 11480 if (ret && ret != -EOPNOTSUPP) { 11481 dev_err(&hdev->pdev->dev, 11482 "failed to clear hw resource, ret = %d\n", ret); 11483 return ret; 11484 } 11485 return 0; 11486 } 11487 11488 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev) 11489 { 11490 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11491 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1); 11492 } 11493 11494 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev) 11495 { 11496 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11497 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0); 11498 } 11499 11500 static struct hclge_wol_info *hclge_get_wol_info(struct hnae3_handle *handle) 11501 { 11502 struct hclge_vport *vport = hclge_get_vport(handle); 11503 11504 return &vport->back->hw.mac.wol; 11505 } 11506 11507 static int hclge_get_wol_supported_mode(struct hclge_dev *hdev, 11508 u32 *wol_supported) 11509 { 11510 struct hclge_query_wol_supported_cmd *wol_supported_cmd; 11511 struct hclge_desc desc; 11512 int ret; 11513 11514 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_GET_SUPPORTED_MODE, 11515 true); 11516 wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)desc.data; 11517 11518 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11519 if (ret) { 11520 dev_err(&hdev->pdev->dev, 11521 "failed to query wol supported, ret = %d\n", ret); 11522 return ret; 11523 } 11524 11525 *wol_supported = le32_to_cpu(wol_supported_cmd->supported_wake_mode); 11526 11527 return 0; 11528 } 11529 11530 static int hclge_set_wol_cfg(struct hclge_dev *hdev, 11531 struct hclge_wol_info *wol_info) 11532 { 11533 struct hclge_wol_cfg_cmd *wol_cfg_cmd; 11534 struct hclge_desc desc; 11535 int ret; 11536 11537 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, false); 11538 wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)desc.data; 11539 wol_cfg_cmd->wake_on_lan_mode = cpu_to_le32(wol_info->wol_current_mode); 11540 wol_cfg_cmd->sopass_size = wol_info->wol_sopass_size; 11541 memcpy(wol_cfg_cmd->sopass, wol_info->wol_sopass, SOPASS_MAX); 11542 11543 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11544 if (ret) 11545 dev_err(&hdev->pdev->dev, 11546 "failed to set wol config, ret = %d\n", ret); 11547 11548 return ret; 11549 } 11550 11551 static int hclge_update_wol(struct hclge_dev *hdev) 11552 { 11553 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11554 11555 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11556 return 0; 11557 11558 return hclge_set_wol_cfg(hdev, wol_info); 11559 } 11560 11561 static int hclge_init_wol(struct hclge_dev *hdev) 11562 { 11563 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11564 int ret; 11565 11566 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11567 return 0; 11568 11569 memset(wol_info, 0, sizeof(struct hclge_wol_info)); 11570 ret = hclge_get_wol_supported_mode(hdev, 11571 &wol_info->wol_support_mode); 11572 if (ret) { 11573 wol_info->wol_support_mode = 0; 11574 return ret; 11575 } 11576 11577 return hclge_update_wol(hdev); 11578 } 11579 11580 static void hclge_get_wol(struct hnae3_handle *handle, 11581 struct ethtool_wolinfo *wol) 11582 { 11583 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11584 11585 wol->supported = wol_info->wol_support_mode; 11586 wol->wolopts = wol_info->wol_current_mode; 11587 if (wol_info->wol_current_mode & WAKE_MAGICSECURE) 11588 memcpy(wol->sopass, wol_info->wol_sopass, SOPASS_MAX); 11589 } 11590 11591 static int hclge_set_wol(struct hnae3_handle *handle, 11592 struct ethtool_wolinfo *wol) 11593 { 11594 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11595 struct hclge_vport *vport = hclge_get_vport(handle); 11596 u32 wol_mode; 11597 int ret; 11598 11599 wol_mode = wol->wolopts; 11600 if (wol_mode & ~wol_info->wol_support_mode) 11601 return -EINVAL; 11602 11603 wol_info->wol_current_mode = wol_mode; 11604 if (wol_mode & WAKE_MAGICSECURE) { 11605 memcpy(wol_info->wol_sopass, wol->sopass, SOPASS_MAX); 11606 wol_info->wol_sopass_size = SOPASS_MAX; 11607 } else { 11608 wol_info->wol_sopass_size = 0; 11609 } 11610 11611 ret = hclge_set_wol_cfg(vport->back, wol_info); 11612 if (ret) 11613 wol_info->wol_current_mode = 0; 11614 11615 return ret; 11616 } 11617 11618 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 11619 { 11620 struct pci_dev *pdev = ae_dev->pdev; 11621 struct hclge_dev *hdev; 11622 int ret; 11623 11624 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 11625 if (!hdev) 11626 return -ENOMEM; 11627 11628 hdev->pdev = pdev; 11629 hdev->ae_dev = ae_dev; 11630 hdev->reset_type = HNAE3_NONE_RESET; 11631 hdev->reset_level = HNAE3_FUNC_RESET; 11632 ae_dev->priv = hdev; 11633 11634 /* HW supprt 2 layer vlan */ 11635 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 11636 11637 mutex_init(&hdev->vport_lock); 11638 spin_lock_init(&hdev->fd_rule_lock); 11639 sema_init(&hdev->reset_sem, 1); 11640 11641 ret = hclge_pci_init(hdev); 11642 if (ret) 11643 goto out; 11644 11645 /* Firmware command queue initialize */ 11646 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 11647 if (ret) 11648 goto err_pci_uninit; 11649 11650 /* Firmware command initialize */ 11651 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 11652 true, hdev->reset_pending); 11653 if (ret) 11654 goto err_cmd_uninit; 11655 11656 ret = hclge_clear_hw_resource(hdev); 11657 if (ret) 11658 goto err_cmd_uninit; 11659 11660 ret = hclge_get_cap(hdev); 11661 if (ret) 11662 goto err_cmd_uninit; 11663 11664 ret = hclge_query_dev_specs(hdev); 11665 if (ret) { 11666 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n", 11667 ret); 11668 goto err_cmd_uninit; 11669 } 11670 11671 ret = hclge_configure(hdev); 11672 if (ret) { 11673 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 11674 goto err_cmd_uninit; 11675 } 11676 11677 ret = hclge_init_msi(hdev); 11678 if (ret) { 11679 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 11680 goto err_cmd_uninit; 11681 } 11682 11683 ret = hclge_misc_irq_init(hdev); 11684 if (ret) 11685 goto err_msi_uninit; 11686 11687 ret = hclge_alloc_tqps(hdev); 11688 if (ret) { 11689 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 11690 goto err_msi_irq_uninit; 11691 } 11692 11693 ret = hclge_alloc_vport(hdev); 11694 if (ret) 11695 goto err_msi_irq_uninit; 11696 11697 ret = hclge_map_tqp(hdev); 11698 if (ret) 11699 goto err_msi_irq_uninit; 11700 11701 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { 11702 clear_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps); 11703 if (hnae3_dev_phy_imp_supported(hdev)) 11704 ret = hclge_update_tp_port_info(hdev); 11705 else 11706 ret = hclge_mac_mdio_config(hdev); 11707 11708 if (ret) 11709 goto err_msi_irq_uninit; 11710 } 11711 11712 ret = hclge_init_umv_space(hdev); 11713 if (ret) 11714 goto err_mdiobus_unreg; 11715 11716 ret = hclge_mac_init(hdev); 11717 if (ret) { 11718 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 11719 goto err_mdiobus_unreg; 11720 } 11721 11722 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 11723 if (ret) { 11724 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 11725 goto err_mdiobus_unreg; 11726 } 11727 11728 ret = hclge_config_gro(hdev); 11729 if (ret) 11730 goto err_mdiobus_unreg; 11731 11732 ret = hclge_init_vlan_config(hdev); 11733 if (ret) { 11734 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 11735 goto err_mdiobus_unreg; 11736 } 11737 11738 ret = hclge_tm_schd_init(hdev); 11739 if (ret) { 11740 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 11741 goto err_mdiobus_unreg; 11742 } 11743 11744 ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev, 11745 &hdev->rss_cfg); 11746 if (ret) { 11747 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 11748 goto err_mdiobus_unreg; 11749 } 11750 11751 ret = hclge_rss_init_hw(hdev); 11752 if (ret) { 11753 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 11754 goto err_mdiobus_unreg; 11755 } 11756 11757 ret = init_mgr_tbl(hdev); 11758 if (ret) { 11759 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 11760 goto err_mdiobus_unreg; 11761 } 11762 11763 ret = hclge_init_fd_config(hdev); 11764 if (ret) { 11765 dev_err(&pdev->dev, 11766 "fd table init fail, ret=%d\n", ret); 11767 goto err_mdiobus_unreg; 11768 } 11769 11770 ret = hclge_ptp_init(hdev); 11771 if (ret) 11772 goto err_mdiobus_unreg; 11773 11774 ret = hclge_update_port_info(hdev); 11775 if (ret) 11776 goto err_ptp_uninit; 11777 11778 INIT_KFIFO(hdev->mac_tnl_log); 11779 11780 hclge_dcb_ops_set(hdev); 11781 11782 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0); 11783 INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task); 11784 11785 hclge_clear_all_event_cause(hdev); 11786 hclge_clear_resetting_state(hdev); 11787 11788 /* Log and clear the hw errors those already occurred */ 11789 if (hnae3_dev_ras_imp_supported(hdev)) 11790 hclge_handle_occurred_error(hdev); 11791 else 11792 hclge_handle_all_hns_hw_errors(ae_dev); 11793 11794 /* request delayed reset for the error recovery because an immediate 11795 * global reset on a PF affecting pending initialization of other PFs 11796 */ 11797 if (ae_dev->hw_err_reset_req) { 11798 enum hnae3_reset_type reset_level; 11799 11800 reset_level = hclge_get_reset_level(ae_dev, 11801 &ae_dev->hw_err_reset_req); 11802 hclge_set_def_reset_request(ae_dev, reset_level); 11803 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 11804 } 11805 11806 hclge_init_rxd_adv_layout(hdev); 11807 11808 /* Enable MISC vector(vector0) */ 11809 hclge_enable_vector(&hdev->misc_vector, true); 11810 11811 ret = hclge_init_wol(hdev); 11812 if (ret) 11813 dev_warn(&pdev->dev, 11814 "failed to wake on lan init, ret = %d\n", ret); 11815 11816 ret = hclge_devlink_init(hdev); 11817 if (ret) 11818 goto err_ptp_uninit; 11819 11820 hclge_state_init(hdev); 11821 hdev->last_reset_time = jiffies; 11822 11823 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", 11824 HCLGE_DRIVER_NAME); 11825 11826 hclge_task_schedule(hdev, round_jiffies_relative(HZ)); 11827 return 0; 11828 11829 err_ptp_uninit: 11830 hclge_ptp_uninit(hdev); 11831 err_mdiobus_unreg: 11832 if (hdev->hw.mac.phydev) 11833 mdiobus_unregister(hdev->hw.mac.mdio_bus); 11834 err_msi_irq_uninit: 11835 hclge_misc_irq_uninit(hdev); 11836 err_msi_uninit: 11837 pci_free_irq_vectors(pdev); 11838 err_cmd_uninit: 11839 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 11840 err_pci_uninit: 11841 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11842 pci_release_regions(pdev); 11843 pci_disable_device(pdev); 11844 out: 11845 mutex_destroy(&hdev->vport_lock); 11846 return ret; 11847 } 11848 11849 static void hclge_stats_clear(struct hclge_dev *hdev) 11850 { 11851 memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats)); 11852 memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats)); 11853 } 11854 11855 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11856 { 11857 return hclge_config_switch_param(hdev, vf, enable, 11858 HCLGE_SWITCH_ANTI_SPOOF_MASK); 11859 } 11860 11861 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11862 { 11863 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 11864 HCLGE_FILTER_FE_NIC_INGRESS_B, 11865 enable, vf); 11866 } 11867 11868 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) 11869 { 11870 int ret; 11871 11872 ret = hclge_set_mac_spoofchk(hdev, vf, enable); 11873 if (ret) { 11874 dev_err(&hdev->pdev->dev, 11875 "Set vf %d mac spoof check %s failed, ret=%d\n", 11876 vf, enable ? "on" : "off", ret); 11877 return ret; 11878 } 11879 11880 ret = hclge_set_vlan_spoofchk(hdev, vf, enable); 11881 if (ret) 11882 dev_err(&hdev->pdev->dev, 11883 "Set vf %d vlan spoof check %s failed, ret=%d\n", 11884 vf, enable ? "on" : "off", ret); 11885 11886 return ret; 11887 } 11888 11889 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf, 11890 bool enable) 11891 { 11892 struct hclge_vport *vport = hclge_get_vport(handle); 11893 struct hclge_dev *hdev = vport->back; 11894 u32 new_spoofchk = enable ? 1 : 0; 11895 int ret; 11896 11897 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11898 return -EOPNOTSUPP; 11899 11900 vport = hclge_get_vf_vport(hdev, vf); 11901 if (!vport) 11902 return -EINVAL; 11903 11904 if (vport->vf_info.spoofchk == new_spoofchk) 11905 return 0; 11906 11907 if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full)) 11908 dev_warn(&hdev->pdev->dev, 11909 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n", 11910 vf); 11911 else if (enable && hclge_is_umv_space_full(vport, true)) 11912 dev_warn(&hdev->pdev->dev, 11913 "vf %d mac table is full, enable spoof check may cause its packet send fail\n", 11914 vf); 11915 11916 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable); 11917 if (ret) 11918 return ret; 11919 11920 vport->vf_info.spoofchk = new_spoofchk; 11921 return 0; 11922 } 11923 11924 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev) 11925 { 11926 struct hclge_vport *vport = hdev->vport; 11927 int ret; 11928 int i; 11929 11930 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11931 return 0; 11932 11933 /* resume the vf spoof check state after reset */ 11934 for (i = 0; i < hdev->num_alloc_vport; i++) { 11935 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, 11936 vport->vf_info.spoofchk); 11937 if (ret) 11938 return ret; 11939 11940 vport++; 11941 } 11942 11943 return 0; 11944 } 11945 11946 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable) 11947 { 11948 struct hclge_vport *vport = hclge_get_vport(handle); 11949 struct hclge_dev *hdev = vport->back; 11950 u32 new_trusted = enable ? 1 : 0; 11951 11952 vport = hclge_get_vf_vport(hdev, vf); 11953 if (!vport) 11954 return -EINVAL; 11955 11956 if (vport->vf_info.trusted == new_trusted) 11957 return 0; 11958 11959 vport->vf_info.trusted = new_trusted; 11960 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 11961 hclge_task_schedule(hdev, 0); 11962 11963 return 0; 11964 } 11965 11966 static void hclge_reset_vf_rate(struct hclge_dev *hdev) 11967 { 11968 int ret; 11969 int vf; 11970 11971 /* reset vf rate to default value */ 11972 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 11973 struct hclge_vport *vport = &hdev->vport[vf]; 11974 11975 vport->vf_info.max_tx_rate = 0; 11976 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); 11977 if (ret) 11978 dev_err(&hdev->pdev->dev, 11979 "vf%d failed to reset to default, ret=%d\n", 11980 vf - HCLGE_VF_VPORT_START_NUM, ret); 11981 } 11982 } 11983 11984 static int hclge_vf_rate_param_check(struct hclge_dev *hdev, 11985 int min_tx_rate, int max_tx_rate) 11986 { 11987 if (min_tx_rate != 0 || 11988 max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) { 11989 dev_err(&hdev->pdev->dev, 11990 "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n", 11991 min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed); 11992 return -EINVAL; 11993 } 11994 11995 return 0; 11996 } 11997 11998 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf, 11999 int min_tx_rate, int max_tx_rate, bool force) 12000 { 12001 struct hclge_vport *vport = hclge_get_vport(handle); 12002 struct hclge_dev *hdev = vport->back; 12003 int ret; 12004 12005 ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate); 12006 if (ret) 12007 return ret; 12008 12009 vport = hclge_get_vf_vport(hdev, vf); 12010 if (!vport) 12011 return -EINVAL; 12012 12013 if (!force && max_tx_rate == vport->vf_info.max_tx_rate) 12014 return 0; 12015 12016 ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); 12017 if (ret) 12018 return ret; 12019 12020 vport->vf_info.max_tx_rate = max_tx_rate; 12021 12022 return 0; 12023 } 12024 12025 static int hclge_resume_vf_rate(struct hclge_dev *hdev) 12026 { 12027 struct hnae3_handle *handle = &hdev->vport->nic; 12028 struct hclge_vport *vport; 12029 int ret; 12030 int vf; 12031 12032 /* resume the vf max_tx_rate after reset */ 12033 for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) { 12034 vport = hclge_get_vf_vport(hdev, vf); 12035 if (!vport) 12036 return -EINVAL; 12037 12038 /* zero means max rate, after reset, firmware already set it to 12039 * max rate, so just continue. 12040 */ 12041 if (!vport->vf_info.max_tx_rate) 12042 continue; 12043 12044 ret = hclge_set_vf_rate(handle, vf, 0, 12045 vport->vf_info.max_tx_rate, true); 12046 if (ret) { 12047 dev_err(&hdev->pdev->dev, 12048 "vf%d failed to resume tx_rate:%u, ret=%d\n", 12049 vf, vport->vf_info.max_tx_rate, ret); 12050 return ret; 12051 } 12052 } 12053 12054 return 0; 12055 } 12056 12057 static void hclge_reset_vport_state(struct hclge_dev *hdev) 12058 { 12059 struct hclge_vport *vport = hdev->vport; 12060 int i; 12061 12062 for (i = 0; i < hdev->num_alloc_vport; i++) { 12063 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12064 vport++; 12065 } 12066 } 12067 12068 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 12069 { 12070 struct hclge_dev *hdev = ae_dev->priv; 12071 struct pci_dev *pdev = ae_dev->pdev; 12072 int ret; 12073 12074 set_bit(HCLGE_STATE_DOWN, &hdev->state); 12075 12076 hclge_stats_clear(hdev); 12077 /* NOTE: pf reset needn't to clear or restore pf and vf table entry. 12078 * so here should not clean table in memory. 12079 */ 12080 if (hdev->reset_type == HNAE3_IMP_RESET || 12081 hdev->reset_type == HNAE3_GLOBAL_RESET) { 12082 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 12083 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full)); 12084 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport); 12085 hclge_reset_umv_space(hdev); 12086 } 12087 12088 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 12089 true, hdev->reset_pending); 12090 if (ret) { 12091 dev_err(&pdev->dev, "Cmd queue init failed\n"); 12092 return ret; 12093 } 12094 12095 ret = hclge_map_tqp(hdev); 12096 if (ret) { 12097 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 12098 return ret; 12099 } 12100 12101 ret = hclge_mac_init(hdev); 12102 if (ret) { 12103 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 12104 return ret; 12105 } 12106 12107 ret = hclge_tp_port_init(hdev); 12108 if (ret) { 12109 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n", 12110 ret); 12111 return ret; 12112 } 12113 12114 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 12115 if (ret) { 12116 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 12117 return ret; 12118 } 12119 12120 ret = hclge_config_gro(hdev); 12121 if (ret) 12122 return ret; 12123 12124 ret = hclge_init_vlan_config(hdev); 12125 if (ret) { 12126 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 12127 return ret; 12128 } 12129 12130 ret = hclge_tm_init_hw(hdev, true); 12131 if (ret) { 12132 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 12133 return ret; 12134 } 12135 12136 ret = hclge_rss_init_hw(hdev); 12137 if (ret) { 12138 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 12139 return ret; 12140 } 12141 12142 ret = init_mgr_tbl(hdev); 12143 if (ret) { 12144 dev_err(&pdev->dev, 12145 "failed to reinit manager table, ret = %d\n", ret); 12146 return ret; 12147 } 12148 12149 ret = hclge_init_fd_config(hdev); 12150 if (ret) { 12151 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret); 12152 return ret; 12153 } 12154 12155 ret = hclge_ptp_init(hdev); 12156 if (ret) 12157 return ret; 12158 12159 /* Log and clear the hw errors those already occurred */ 12160 if (hnae3_dev_ras_imp_supported(hdev)) 12161 hclge_handle_occurred_error(hdev); 12162 else 12163 hclge_handle_all_hns_hw_errors(ae_dev); 12164 12165 /* Re-enable the hw error interrupts because 12166 * the interrupts get disabled on global reset. 12167 */ 12168 ret = hclge_config_nic_hw_error(hdev, true); 12169 if (ret) { 12170 dev_err(&pdev->dev, 12171 "fail(%d) to re-enable NIC hw error interrupts\n", 12172 ret); 12173 return ret; 12174 } 12175 12176 if (hdev->roce_client) { 12177 ret = hclge_config_rocee_ras_interrupt(hdev, true); 12178 if (ret) { 12179 dev_err(&pdev->dev, 12180 "fail(%d) to re-enable roce ras interrupts\n", 12181 ret); 12182 return ret; 12183 } 12184 } 12185 12186 hclge_reset_vport_state(hdev); 12187 ret = hclge_reset_vport_spoofchk(hdev); 12188 if (ret) 12189 return ret; 12190 12191 ret = hclge_resume_vf_rate(hdev); 12192 if (ret) 12193 return ret; 12194 12195 hclge_init_rxd_adv_layout(hdev); 12196 12197 ret = hclge_update_wol(hdev); 12198 if (ret) 12199 dev_warn(&pdev->dev, 12200 "failed to update wol config, ret = %d\n", ret); 12201 12202 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 12203 HCLGE_DRIVER_NAME); 12204 12205 return 0; 12206 } 12207 12208 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 12209 { 12210 struct hclge_dev *hdev = ae_dev->priv; 12211 struct hclge_mac *mac = &hdev->hw.mac; 12212 12213 hclge_reset_vf_rate(hdev); 12214 hclge_clear_vf_vlan(hdev); 12215 hclge_state_uninit(hdev); 12216 hclge_ptp_uninit(hdev); 12217 hclge_uninit_rxd_adv_layout(hdev); 12218 hclge_uninit_mac_table(hdev); 12219 hclge_del_all_fd_entries(hdev); 12220 12221 if (mac->phydev) 12222 mdiobus_unregister(mac->mdio_bus); 12223 12224 /* Disable MISC vector(vector0) */ 12225 hclge_enable_vector(&hdev->misc_vector, false); 12226 synchronize_irq(hdev->misc_vector.vector_irq); 12227 12228 /* Disable all hw interrupts */ 12229 hclge_config_mac_tnl_int(hdev, false); 12230 hclge_config_nic_hw_error(hdev, false); 12231 hclge_config_rocee_ras_interrupt(hdev, false); 12232 12233 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 12234 hclge_misc_irq_uninit(hdev); 12235 hclge_devlink_uninit(hdev); 12236 hclge_pci_uninit(hdev); 12237 hclge_uninit_vport_vlan_table(hdev); 12238 mutex_destroy(&hdev->vport_lock); 12239 ae_dev->priv = NULL; 12240 } 12241 12242 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 12243 { 12244 struct hclge_vport *vport = hclge_get_vport(handle); 12245 struct hclge_dev *hdev = vport->back; 12246 12247 return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps); 12248 } 12249 12250 static void hclge_get_channels(struct hnae3_handle *handle, 12251 struct ethtool_channels *ch) 12252 { 12253 ch->max_combined = hclge_get_max_channels(handle); 12254 ch->other_count = 1; 12255 ch->max_other = 1; 12256 ch->combined_count = handle->kinfo.rss_size; 12257 } 12258 12259 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 12260 u16 *alloc_tqps, u16 *max_rss_size) 12261 { 12262 struct hclge_vport *vport = hclge_get_vport(handle); 12263 struct hclge_dev *hdev = vport->back; 12264 12265 *alloc_tqps = vport->alloc_tqps; 12266 *max_rss_size = hdev->pf_rss_size_max; 12267 } 12268 12269 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle) 12270 { 12271 struct hclge_vport *vport = hclge_get_vport(handle); 12272 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 12273 struct hclge_dev *hdev = vport->back; 12274 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 12275 u16 tc_valid[HCLGE_MAX_TC_NUM]; 12276 u16 roundup_size; 12277 unsigned int i; 12278 12279 roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size); 12280 roundup_size = ilog2(roundup_size); 12281 /* Set the RSS TC mode according to the new RSS size */ 12282 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 12283 tc_valid[i] = 0; 12284 12285 if (!(hdev->hw_tc_map & BIT(i))) 12286 continue; 12287 12288 tc_valid[i] = 1; 12289 tc_size[i] = roundup_size; 12290 tc_offset[i] = vport->nic.kinfo.rss_size * i; 12291 } 12292 12293 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 12294 tc_size); 12295 } 12296 12297 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 12298 bool rxfh_configured) 12299 { 12300 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 12301 struct hclge_vport *vport = hclge_get_vport(handle); 12302 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 12303 struct hclge_dev *hdev = vport->back; 12304 u16 cur_rss_size = kinfo->rss_size; 12305 u16 cur_tqps = kinfo->num_tqps; 12306 u32 *rss_indir; 12307 unsigned int i; 12308 int ret; 12309 12310 kinfo->req_rss_size = new_tqps_num; 12311 12312 ret = hclge_tm_vport_map_update(hdev); 12313 if (ret) { 12314 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret); 12315 return ret; 12316 } 12317 12318 ret = hclge_set_rss_tc_mode_cfg(handle); 12319 if (ret) 12320 return ret; 12321 12322 /* RSS indirection table has been configured by user */ 12323 if (rxfh_configured) 12324 goto out; 12325 12326 /* Reinitializes the rss indirect table according to the new RSS size */ 12327 rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32), 12328 GFP_KERNEL); 12329 if (!rss_indir) 12330 return -ENOMEM; 12331 12332 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 12333 rss_indir[i] = i % kinfo->rss_size; 12334 12335 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 12336 if (ret) 12337 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 12338 ret); 12339 12340 kfree(rss_indir); 12341 12342 out: 12343 if (!ret) 12344 dev_info(&hdev->pdev->dev, 12345 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 12346 cur_rss_size, kinfo->rss_size, 12347 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 12348 12349 return ret; 12350 } 12351 12352 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 12353 { 12354 struct hclge_set_led_state_cmd *req; 12355 struct hclge_desc desc; 12356 int ret; 12357 12358 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 12359 12360 req = (struct hclge_set_led_state_cmd *)desc.data; 12361 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 12362 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 12363 12364 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12365 if (ret) 12366 dev_err(&hdev->pdev->dev, 12367 "Send set led state cmd error, ret =%d\n", ret); 12368 12369 return ret; 12370 } 12371 12372 enum hclge_led_status { 12373 HCLGE_LED_OFF, 12374 HCLGE_LED_ON, 12375 HCLGE_LED_NO_CHANGE = 0xFF, 12376 }; 12377 12378 static int hclge_set_led_id(struct hnae3_handle *handle, 12379 enum ethtool_phys_id_state status) 12380 { 12381 struct hclge_vport *vport = hclge_get_vport(handle); 12382 struct hclge_dev *hdev = vport->back; 12383 12384 switch (status) { 12385 case ETHTOOL_ID_ACTIVE: 12386 return hclge_set_led_status(hdev, HCLGE_LED_ON); 12387 case ETHTOOL_ID_INACTIVE: 12388 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 12389 default: 12390 return -EINVAL; 12391 } 12392 } 12393 12394 static void hclge_get_link_mode(struct hnae3_handle *handle, 12395 unsigned long *supported, 12396 unsigned long *advertising) 12397 { 12398 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 12399 struct hclge_vport *vport = hclge_get_vport(handle); 12400 struct hclge_dev *hdev = vport->back; 12401 unsigned int idx = 0; 12402 12403 for (; idx < size; idx++) { 12404 supported[idx] = hdev->hw.mac.supported[idx]; 12405 advertising[idx] = hdev->hw.mac.advertising[idx]; 12406 } 12407 } 12408 12409 static int hclge_gro_en(struct hnae3_handle *handle, bool enable) 12410 { 12411 struct hclge_vport *vport = hclge_get_vport(handle); 12412 struct hclge_dev *hdev = vport->back; 12413 bool gro_en_old = hdev->gro_en; 12414 int ret; 12415 12416 hdev->gro_en = enable; 12417 ret = hclge_config_gro(hdev); 12418 if (ret) 12419 hdev->gro_en = gro_en_old; 12420 12421 return ret; 12422 } 12423 12424 static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport) 12425 { 12426 struct hnae3_handle *handle = &vport->nic; 12427 struct hclge_dev *hdev = vport->back; 12428 bool uc_en = false; 12429 bool mc_en = false; 12430 u8 tmp_flags; 12431 bool bc_en; 12432 int ret; 12433 12434 if (vport->last_promisc_flags != vport->overflow_promisc_flags) { 12435 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12436 vport->last_promisc_flags = vport->overflow_promisc_flags; 12437 } 12438 12439 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12440 &vport->state)) 12441 return 0; 12442 12443 /* for PF */ 12444 if (!vport->vport_id) { 12445 tmp_flags = handle->netdev_flags | vport->last_promisc_flags; 12446 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE, 12447 tmp_flags & HNAE3_MPE); 12448 if (!ret) 12449 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 12450 &vport->state); 12451 else 12452 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12453 &vport->state); 12454 return ret; 12455 } 12456 12457 /* for VF */ 12458 if (vport->vf_info.trusted) { 12459 uc_en = vport->vf_info.request_uc_en > 0 || 12460 vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE; 12461 mc_en = vport->vf_info.request_mc_en > 0 || 12462 vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE; 12463 } 12464 bc_en = vport->vf_info.request_bc_en > 0; 12465 12466 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en, 12467 mc_en, bc_en); 12468 if (ret) { 12469 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12470 return ret; 12471 } 12472 hclge_set_vport_vlan_fltr_change(vport); 12473 12474 return 0; 12475 } 12476 12477 static void hclge_sync_promisc_mode(struct hclge_dev *hdev) 12478 { 12479 struct hclge_vport *vport; 12480 int ret; 12481 u16 i; 12482 12483 for (i = 0; i < hdev->num_alloc_vport; i++) { 12484 vport = &hdev->vport[i]; 12485 12486 ret = hclge_sync_vport_promisc_mode(vport); 12487 if (ret) 12488 return; 12489 } 12490 } 12491 12492 static bool hclge_module_existed(struct hclge_dev *hdev) 12493 { 12494 struct hclge_desc desc; 12495 u32 existed; 12496 int ret; 12497 12498 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true); 12499 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12500 if (ret) { 12501 dev_err(&hdev->pdev->dev, 12502 "failed to get SFP exist state, ret = %d\n", ret); 12503 return false; 12504 } 12505 12506 existed = le32_to_cpu(desc.data[0]); 12507 12508 return existed != 0; 12509 } 12510 12511 /* need 6 bds(total 140 bytes) in one reading 12512 * return the number of bytes actually read, 0 means read failed. 12513 */ 12514 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset, 12515 u32 len, u8 *data) 12516 { 12517 struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM]; 12518 struct hclge_sfp_info_bd0_cmd *sfp_info_bd0; 12519 u16 read_len; 12520 u16 copy_len; 12521 int ret; 12522 int i; 12523 12524 /* setup all 6 bds to read module eeprom info. */ 12525 for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12526 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM, 12527 true); 12528 12529 /* bd0~bd4 need next flag */ 12530 if (i < HCLGE_SFP_INFO_CMD_NUM - 1) 12531 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12532 } 12533 12534 /* setup bd0, this bd contains offset and read length. */ 12535 sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data; 12536 sfp_info_bd0->offset = cpu_to_le16((u16)offset); 12537 read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN); 12538 sfp_info_bd0->read_len = cpu_to_le16(read_len); 12539 12540 ret = hclge_cmd_send(&hdev->hw, desc, i); 12541 if (ret) { 12542 dev_err(&hdev->pdev->dev, 12543 "failed to get SFP eeprom info, ret = %d\n", ret); 12544 return 0; 12545 } 12546 12547 /* copy sfp info from bd0 to out buffer. */ 12548 copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN); 12549 memcpy(data, sfp_info_bd0->data, copy_len); 12550 read_len = copy_len; 12551 12552 /* copy sfp info from bd1~bd5 to out buffer if needed. */ 12553 for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12554 if (read_len >= len) 12555 return read_len; 12556 12557 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN); 12558 memcpy(data + read_len, desc[i].data, copy_len); 12559 read_len += copy_len; 12560 } 12561 12562 return read_len; 12563 } 12564 12565 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset, 12566 u32 len, u8 *data) 12567 { 12568 struct hclge_vport *vport = hclge_get_vport(handle); 12569 struct hclge_dev *hdev = vport->back; 12570 u32 read_len = 0; 12571 u16 data_len; 12572 12573 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 12574 return -EOPNOTSUPP; 12575 12576 if (!hclge_module_existed(hdev)) 12577 return -ENXIO; 12578 12579 while (read_len < len) { 12580 data_len = hclge_get_sfp_eeprom_info(hdev, 12581 offset + read_len, 12582 len - read_len, 12583 data + read_len); 12584 if (!data_len) 12585 return -EIO; 12586 12587 read_len += data_len; 12588 } 12589 12590 return 0; 12591 } 12592 12593 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle, 12594 u32 *status_code) 12595 { 12596 struct hclge_vport *vport = hclge_get_vport(handle); 12597 struct hclge_dev *hdev = vport->back; 12598 struct hclge_desc desc; 12599 int ret; 12600 12601 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 12602 return -EOPNOTSUPP; 12603 12604 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true); 12605 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12606 if (ret) { 12607 dev_err(&hdev->pdev->dev, 12608 "failed to query link diagnosis info, ret = %d\n", ret); 12609 return ret; 12610 } 12611 12612 *status_code = le32_to_cpu(desc.data[0]); 12613 return 0; 12614 } 12615 12616 /* After disable sriov, VF still has some config and info need clean, 12617 * which configed by PF. 12618 */ 12619 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid) 12620 { 12621 struct hclge_dev *hdev = vport->back; 12622 struct hclge_vlan_info vlan_info; 12623 int ret; 12624 12625 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 12626 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12627 vport->need_notify = 0; 12628 vport->mps = 0; 12629 12630 /* after disable sriov, clean VF rate configured by PF */ 12631 ret = hclge_tm_qs_shaper_cfg(vport, 0); 12632 if (ret) 12633 dev_err(&hdev->pdev->dev, 12634 "failed to clean vf%d rate config, ret = %d\n", 12635 vfid, ret); 12636 12637 vlan_info.vlan_tag = 0; 12638 vlan_info.qos = 0; 12639 vlan_info.vlan_proto = ETH_P_8021Q; 12640 ret = hclge_update_port_base_vlan_cfg(vport, 12641 HNAE3_PORT_BASE_VLAN_DISABLE, 12642 &vlan_info); 12643 if (ret) 12644 dev_err(&hdev->pdev->dev, 12645 "failed to clean vf%d port base vlan, ret = %d\n", 12646 vfid, ret); 12647 12648 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false); 12649 if (ret) 12650 dev_err(&hdev->pdev->dev, 12651 "failed to clean vf%d spoof config, ret = %d\n", 12652 vfid, ret); 12653 12654 memset(&vport->vf_info, 0, sizeof(vport->vf_info)); 12655 } 12656 12657 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs) 12658 { 12659 struct hclge_dev *hdev = ae_dev->priv; 12660 struct hclge_vport *vport; 12661 int i; 12662 12663 for (i = 0; i < num_vfs; i++) { 12664 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 12665 12666 hclge_clear_vport_vf_info(vport, i); 12667 } 12668 } 12669 12670 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode, 12671 u8 *priority) 12672 { 12673 struct hclge_vport *vport = hclge_get_vport(h); 12674 12675 if (dscp >= HNAE3_MAX_DSCP) 12676 return -EINVAL; 12677 12678 if (tc_mode) 12679 *tc_mode = vport->nic.kinfo.tc_map_mode; 12680 if (priority) 12681 *priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 : 12682 vport->nic.kinfo.dscp_prio[dscp]; 12683 12684 return 0; 12685 } 12686 12687 static const struct hnae3_ae_ops hclge_ops = { 12688 .init_ae_dev = hclge_init_ae_dev, 12689 .uninit_ae_dev = hclge_uninit_ae_dev, 12690 .reset_prepare = hclge_reset_prepare_general, 12691 .reset_done = hclge_reset_done, 12692 .init_client_instance = hclge_init_client_instance, 12693 .uninit_client_instance = hclge_uninit_client_instance, 12694 .map_ring_to_vector = hclge_map_ring_to_vector, 12695 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 12696 .get_vector = hclge_get_vector, 12697 .put_vector = hclge_put_vector, 12698 .set_promisc_mode = hclge_set_promisc_mode, 12699 .request_update_promisc_mode = hclge_request_update_promisc_mode, 12700 .set_loopback = hclge_set_loopback, 12701 .start = hclge_ae_start, 12702 .stop = hclge_ae_stop, 12703 .client_start = hclge_client_start, 12704 .client_stop = hclge_client_stop, 12705 .get_status = hclge_get_status, 12706 .get_ksettings_an_result = hclge_get_ksettings_an_result, 12707 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 12708 .get_media_type = hclge_get_media_type, 12709 .check_port_speed = hclge_check_port_speed, 12710 .get_fec_stats = hclge_get_fec_stats, 12711 .get_fec = hclge_get_fec, 12712 .set_fec = hclge_set_fec, 12713 .get_rss_key_size = hclge_comm_get_rss_key_size, 12714 .get_rss = hclge_get_rss, 12715 .set_rss = hclge_set_rss, 12716 .set_rss_tuple = hclge_set_rss_tuple, 12717 .get_rss_tuple = hclge_get_rss_tuple, 12718 .get_tc_size = hclge_get_tc_size, 12719 .get_mac_addr = hclge_get_mac_addr, 12720 .set_mac_addr = hclge_set_mac_addr, 12721 .do_ioctl = hclge_do_ioctl, 12722 .add_uc_addr = hclge_add_uc_addr, 12723 .rm_uc_addr = hclge_rm_uc_addr, 12724 .add_mc_addr = hclge_add_mc_addr, 12725 .rm_mc_addr = hclge_rm_mc_addr, 12726 .set_autoneg = hclge_set_autoneg, 12727 .get_autoneg = hclge_get_autoneg, 12728 .restart_autoneg = hclge_restart_autoneg, 12729 .halt_autoneg = hclge_halt_autoneg, 12730 .get_pauseparam = hclge_get_pauseparam, 12731 .set_pauseparam = hclge_set_pauseparam, 12732 .set_mtu = hclge_set_mtu, 12733 .reset_queue = hclge_reset_tqp, 12734 .get_stats = hclge_get_stats, 12735 .get_mac_stats = hclge_get_mac_stat, 12736 .update_stats = hclge_update_stats, 12737 .get_strings = hclge_get_strings, 12738 .get_sset_count = hclge_get_sset_count, 12739 .get_fw_version = hclge_get_fw_version, 12740 .get_mdix_mode = hclge_get_mdix_mode, 12741 .enable_vlan_filter = hclge_enable_vlan_filter, 12742 .set_vlan_filter = hclge_set_vlan_filter, 12743 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 12744 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 12745 .reset_event = hclge_reset_event, 12746 .get_reset_level = hclge_get_reset_level, 12747 .set_default_reset_request = hclge_set_def_reset_request, 12748 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 12749 .set_channels = hclge_set_channels, 12750 .get_channels = hclge_get_channels, 12751 .get_regs_len = hclge_get_regs_len, 12752 .get_regs = hclge_get_regs, 12753 .set_led_id = hclge_set_led_id, 12754 .get_link_mode = hclge_get_link_mode, 12755 .add_fd_entry = hclge_add_fd_entry, 12756 .del_fd_entry = hclge_del_fd_entry, 12757 .get_fd_rule_cnt = hclge_get_fd_rule_cnt, 12758 .get_fd_rule_info = hclge_get_fd_rule_info, 12759 .get_fd_all_rules = hclge_get_all_rules, 12760 .enable_fd = hclge_enable_fd, 12761 .add_arfs_entry = hclge_add_fd_entry_by_arfs, 12762 .dbg_read_cmd = hclge_dbg_read_cmd, 12763 .handle_hw_ras_error = hclge_handle_hw_ras_error, 12764 .get_hw_reset_stat = hclge_get_hw_reset_stat, 12765 .ae_dev_resetting = hclge_ae_dev_resetting, 12766 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt, 12767 .set_gro_en = hclge_gro_en, 12768 .get_global_queue_id = hclge_covert_handle_qid_global, 12769 .set_timer_task = hclge_set_timer_task, 12770 .mac_connect_phy = hclge_mac_connect_phy, 12771 .mac_disconnect_phy = hclge_mac_disconnect_phy, 12772 .get_vf_config = hclge_get_vf_config, 12773 .set_vf_link_state = hclge_set_vf_link_state, 12774 .set_vf_spoofchk = hclge_set_vf_spoofchk, 12775 .set_vf_trust = hclge_set_vf_trust, 12776 .set_vf_rate = hclge_set_vf_rate, 12777 .set_vf_mac = hclge_set_vf_mac, 12778 .get_module_eeprom = hclge_get_module_eeprom, 12779 .get_cmdq_stat = hclge_get_cmdq_stat, 12780 .add_cls_flower = hclge_add_cls_flower, 12781 .del_cls_flower = hclge_del_cls_flower, 12782 .cls_flower_active = hclge_is_cls_flower_active, 12783 .get_phy_link_ksettings = hclge_get_phy_link_ksettings, 12784 .set_phy_link_ksettings = hclge_set_phy_link_ksettings, 12785 .set_tx_hwts_info = hclge_ptp_set_tx_info, 12786 .get_rx_hwts = hclge_ptp_get_rx_hwts, 12787 .get_ts_info = hclge_ptp_get_ts_info, 12788 .get_link_diagnosis_info = hclge_get_link_diagnosis_info, 12789 .clean_vf_config = hclge_clean_vport_config, 12790 .get_dscp_prio = hclge_get_dscp_prio, 12791 .get_wol = hclge_get_wol, 12792 .set_wol = hclge_set_wol, 12793 }; 12794 12795 static struct hnae3_ae_algo ae_algo = { 12796 .ops = &hclge_ops, 12797 .pdev_id_table = ae_algo_pci_tbl, 12798 }; 12799 12800 static int __init hclge_init(void) 12801 { 12802 pr_info("%s is initializing\n", HCLGE_NAME); 12803 12804 hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGE_NAME); 12805 if (!hclge_wq) { 12806 pr_err("%s: failed to create workqueue\n", HCLGE_NAME); 12807 return -ENOMEM; 12808 } 12809 12810 hnae3_register_ae_algo(&ae_algo); 12811 12812 return 0; 12813 } 12814 12815 static void __exit hclge_exit(void) 12816 { 12817 hnae3_unregister_ae_algo_prepare(&ae_algo); 12818 hnae3_unregister_ae_algo(&ae_algo); 12819 destroy_workqueue(hclge_wq); 12820 } 12821 module_init(hclge_init); 12822 module_exit(hclge_exit); 12823 12824 MODULE_LICENSE("GPL"); 12825 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 12826 MODULE_DESCRIPTION("HCLGE Driver"); 12827 MODULE_VERSION(HCLGE_MOD_VERSION); 12828