1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/pci.h> 13 #include <linux/platform_device.h> 14 #include <linux/if_vlan.h> 15 #include <linux/crash_dump.h> 16 #include <net/ipv6.h> 17 #include <net/rtnetlink.h> 18 #include "hclge_cmd.h" 19 #include "hclge_dcb.h" 20 #include "hclge_main.h" 21 #include "hclge_mbx.h" 22 #include "hclge_mdio.h" 23 #include "hclge_regs.h" 24 #include "hclge_tm.h" 25 #include "hclge_err.h" 26 #include "hnae3.h" 27 #include "hclge_devlink.h" 28 #include "hclge_comm_cmd.h" 29 30 #define HCLGE_NAME "hclge" 31 32 #define HCLGE_BUF_SIZE_UNIT 256U 33 #define HCLGE_BUF_MUL_BY 2 34 #define HCLGE_BUF_DIV_BY 2 35 #define NEED_RESERVE_TC_NUM 2 36 #define BUF_MAX_PERCENT 100 37 #define BUF_RESERVE_PERCENT 90 38 39 #define HCLGE_RESET_MAX_FAIL_CNT 5 40 #define HCLGE_RESET_SYNC_TIME 100 41 #define HCLGE_PF_RESET_SYNC_TIME 20 42 #define HCLGE_PF_RESET_SYNC_CNT 1500 43 44 #define HCLGE_LINK_STATUS_MS 10 45 46 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps); 47 static int hclge_init_vlan_config(struct hclge_dev *hdev); 48 static void hclge_sync_vlan_filter(struct hclge_dev *hdev); 49 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 50 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle); 51 static void hclge_rfs_filter_expire(struct hclge_dev *hdev); 52 static int hclge_clear_arfs_rules(struct hclge_dev *hdev); 53 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 54 unsigned long *addr); 55 static int hclge_set_default_loopback(struct hclge_dev *hdev); 56 57 static void hclge_sync_mac_table(struct hclge_dev *hdev); 58 static void hclge_restore_hw_table(struct hclge_dev *hdev); 59 static void hclge_sync_promisc_mode(struct hclge_dev *hdev); 60 static void hclge_sync_fd_table(struct hclge_dev *hdev); 61 static void hclge_update_fec_stats(struct hclge_dev *hdev); 62 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 63 int wait_cnt); 64 static int hclge_update_port_info(struct hclge_dev *hdev); 65 66 static struct hnae3_ae_algo ae_algo; 67 68 static struct workqueue_struct *hclge_wq; 69 70 static const struct pci_device_id ae_algo_pci_tbl[] = { 71 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 72 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 75 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 77 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 79 /* required last entry */ 80 {0, } 81 }; 82 83 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 84 85 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 86 "External Loopback test", 87 "App Loopback test", 88 "Serdes serial Loopback test", 89 "Serdes parallel Loopback test", 90 "Phy Loopback test" 91 }; 92 93 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 94 {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 95 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 96 {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 97 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 98 {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 99 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)}, 100 {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 101 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)}, 102 {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 103 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)}, 104 {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 105 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)}, 106 {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 107 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)}, 108 {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 109 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 110 {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 111 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 112 {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 113 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 114 {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 115 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 116 {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 117 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 118 {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 119 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 120 {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 121 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 122 {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 123 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 124 {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 125 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)}, 126 {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 127 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)}, 128 {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 129 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)}, 130 {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 131 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)}, 132 {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 133 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)}, 134 {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 135 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)}, 136 {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 137 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)}, 138 {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 139 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)}, 140 {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 141 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)}, 142 {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 143 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 144 {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 145 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 146 {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 147 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 148 {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 149 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 150 {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 151 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 152 {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 153 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 154 {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 155 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 156 {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 157 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 158 {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 159 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)}, 160 {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 161 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)}, 162 {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 163 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)}, 164 {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 165 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)}, 166 {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 167 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)}, 168 {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 169 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)}, 170 {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 171 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)}, 172 {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 173 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)}, 174 {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 175 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 176 {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 177 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 178 {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 179 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 180 {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 181 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 182 {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 183 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 184 {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 185 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 186 {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 187 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 188 {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 189 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 190 {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 191 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 192 {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 193 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 194 {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 195 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 196 {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 197 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 198 {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 199 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 200 {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 201 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 202 {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 203 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 204 {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 205 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 206 {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 207 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 208 {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 209 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 210 {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 211 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 212 {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 213 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 214 {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 215 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 216 {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 217 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 218 {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 219 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 220 {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 221 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 222 {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 223 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 224 {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 225 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 226 {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 228 {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 230 {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 231 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 232 {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 234 {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 235 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 236 {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 237 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 238 {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 239 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 240 {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 241 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 242 {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 243 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 244 {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 246 {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 248 {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 250 {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 252 {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 254 {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 256 {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 258 {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 260 {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 262 {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 264 {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 265 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 266 {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 267 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 268 {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 269 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 270 {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 271 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 272 {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 273 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 274 275 {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 277 {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 279 {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 281 {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 283 {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 285 {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 287 {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 288 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 289 {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 290 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 291 {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 292 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 293 {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 294 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 295 {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 296 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 297 {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 298 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 299 }; 300 301 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 302 { 303 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 304 .ethter_type = cpu_to_le16(ETH_P_LLDP), 305 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e}, 306 .i_port_bitmap = 0x1, 307 }, 308 }; 309 310 static const struct key_info meta_data_key_info[] = { 311 { PACKET_TYPE_ID, 6 }, 312 { IP_FRAGEMENT, 1 }, 313 { ROCE_TYPE, 1 }, 314 { NEXT_KEY, 5 }, 315 { VLAN_NUMBER, 2 }, 316 { SRC_VPORT, 12 }, 317 { DST_VPORT, 12 }, 318 { TUNNEL_PACKET, 1 }, 319 }; 320 321 static const struct key_info tuple_key_info[] = { 322 { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 }, 323 { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 }, 324 { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 }, 325 { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 326 { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 }, 327 { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 }, 328 { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 }, 329 { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 }, 330 { OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 }, 331 { OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 }, 332 { OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 }, 333 { OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 }, 334 { OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 }, 335 { OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 }, 336 { OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 }, 337 { OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 }, 338 { INNER_DST_MAC, 48, KEY_OPT_MAC, 339 offsetof(struct hclge_fd_rule, tuples.dst_mac), 340 offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) }, 341 { INNER_SRC_MAC, 48, KEY_OPT_MAC, 342 offsetof(struct hclge_fd_rule, tuples.src_mac), 343 offsetof(struct hclge_fd_rule, tuples_mask.src_mac) }, 344 { INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16, 345 offsetof(struct hclge_fd_rule, tuples.vlan_tag1), 346 offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) }, 347 { INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 348 { INNER_ETH_TYPE, 16, KEY_OPT_LE16, 349 offsetof(struct hclge_fd_rule, tuples.ether_proto), 350 offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) }, 351 { INNER_L2_RSV, 16, KEY_OPT_LE16, 352 offsetof(struct hclge_fd_rule, tuples.l2_user_def), 353 offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) }, 354 { INNER_IP_TOS, 8, KEY_OPT_U8, 355 offsetof(struct hclge_fd_rule, tuples.ip_tos), 356 offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) }, 357 { INNER_IP_PROTO, 8, KEY_OPT_U8, 358 offsetof(struct hclge_fd_rule, tuples.ip_proto), 359 offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) }, 360 { INNER_SRC_IP, 32, KEY_OPT_IP, 361 offsetof(struct hclge_fd_rule, tuples.src_ip), 362 offsetof(struct hclge_fd_rule, tuples_mask.src_ip) }, 363 { INNER_DST_IP, 32, KEY_OPT_IP, 364 offsetof(struct hclge_fd_rule, tuples.dst_ip), 365 offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) }, 366 { INNER_L3_RSV, 16, KEY_OPT_LE16, 367 offsetof(struct hclge_fd_rule, tuples.l3_user_def), 368 offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) }, 369 { INNER_SRC_PORT, 16, KEY_OPT_LE16, 370 offsetof(struct hclge_fd_rule, tuples.src_port), 371 offsetof(struct hclge_fd_rule, tuples_mask.src_port) }, 372 { INNER_DST_PORT, 16, KEY_OPT_LE16, 373 offsetof(struct hclge_fd_rule, tuples.dst_port), 374 offsetof(struct hclge_fd_rule, tuples_mask.dst_port) }, 375 { INNER_L4_RSV, 32, KEY_OPT_LE32, 376 offsetof(struct hclge_fd_rule, tuples.l4_user_def), 377 offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) }, 378 }; 379 380 /** 381 * hclge_cmd_send - send command to command queue 382 * @hw: pointer to the hw struct 383 * @desc: prefilled descriptor for describing the command 384 * @num : the number of descriptors to be sent 385 * 386 * This is the main send command for command queue, it 387 * sends the queue, cleans the queue, etc 388 **/ 389 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 390 { 391 return hclge_comm_cmd_send(&hw->hw, desc, num); 392 } 393 394 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev) 395 { 396 #define HCLGE_MAC_CMD_NUM 21 397 398 u64 *data = (u64 *)(&hdev->mac_stats); 399 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 400 __le64 *desc_data; 401 u32 data_size; 402 int ret; 403 u32 i; 404 405 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 406 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 407 if (ret) { 408 dev_err(&hdev->pdev->dev, 409 "Get MAC pkt stats fail, status = %d.\n", ret); 410 411 return ret; 412 } 413 414 /* The first desc has a 64-bit header, so data size need to minus 1 */ 415 data_size = sizeof(desc) / (sizeof(u64)) - 1; 416 417 desc_data = (__le64 *)(&desc[0].data[0]); 418 for (i = 0; i < data_size; i++) { 419 /* data memory is continuous becase only the first desc has a 420 * header in this command 421 */ 422 *data += le64_to_cpu(*desc_data); 423 data++; 424 desc_data++; 425 } 426 427 return 0; 428 } 429 430 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev) 431 { 432 #define HCLGE_REG_NUM_PER_DESC 4 433 434 u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num; 435 u64 *data = (u64 *)(&hdev->mac_stats); 436 struct hclge_desc *desc; 437 __le64 *desc_data; 438 u32 data_size; 439 u32 desc_num; 440 int ret; 441 u32 i; 442 443 /* The first desc has a 64-bit header, so need to consider it */ 444 desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1; 445 446 /* This may be called inside atomic sections, 447 * so GFP_ATOMIC is more suitalbe here 448 */ 449 desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC); 450 if (!desc) 451 return -ENOMEM; 452 453 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true); 454 ret = hclge_cmd_send(&hdev->hw, desc, desc_num); 455 if (ret) { 456 kfree(desc); 457 return ret; 458 } 459 460 data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num); 461 462 desc_data = (__le64 *)(&desc[0].data[0]); 463 for (i = 0; i < data_size; i++) { 464 /* data memory is continuous becase only the first desc has a 465 * header in this command 466 */ 467 *data += le64_to_cpu(*desc_data); 468 data++; 469 desc_data++; 470 } 471 472 kfree(desc); 473 474 return 0; 475 } 476 477 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num) 478 { 479 struct hclge_desc desc; 480 int ret; 481 482 /* Driver needs total register number of both valid registers and 483 * reserved registers, but the old firmware only returns number 484 * of valid registers in device V2. To be compatible with these 485 * devices, driver uses a fixed value. 486 */ 487 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) { 488 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1; 489 return 0; 490 } 491 492 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true); 493 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 494 if (ret) { 495 dev_err(&hdev->pdev->dev, 496 "failed to query mac statistic reg number, ret = %d\n", 497 ret); 498 return ret; 499 } 500 501 *reg_num = le32_to_cpu(desc.data[0]); 502 if (*reg_num == 0) { 503 dev_err(&hdev->pdev->dev, 504 "mac statistic reg number is invalid!\n"); 505 return -ENODATA; 506 } 507 508 return 0; 509 } 510 511 int hclge_mac_update_stats(struct hclge_dev *hdev) 512 { 513 /* The firmware supports the new statistics acquisition method */ 514 if (hdev->ae_dev->dev_specs.mac_stats_num) 515 return hclge_mac_update_stats_complete(hdev); 516 else 517 return hclge_mac_update_stats_defective(hdev); 518 } 519 520 static int hclge_comm_get_count(struct hclge_dev *hdev, 521 const struct hclge_comm_stats_str strs[], 522 u32 size) 523 { 524 int count = 0; 525 u32 i; 526 527 for (i = 0; i < size; i++) 528 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num) 529 count++; 530 531 return count; 532 } 533 534 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, 535 const struct hclge_comm_stats_str strs[], 536 int size, u64 *data) 537 { 538 u64 *buf = data; 539 u32 i; 540 541 for (i = 0; i < size; i++) { 542 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 543 continue; 544 545 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset); 546 buf++; 547 } 548 549 return buf; 550 } 551 552 static u8 *hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, 553 const struct hclge_comm_stats_str strs[], 554 int size, u8 *data) 555 { 556 char *buff = (char *)data; 557 u32 i; 558 559 if (stringset != ETH_SS_STATS) 560 return buff; 561 562 for (i = 0; i < size; i++) { 563 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 564 continue; 565 566 snprintf(buff, ETH_GSTRING_LEN, "%s", strs[i].desc); 567 buff = buff + ETH_GSTRING_LEN; 568 } 569 570 return (u8 *)buff; 571 } 572 573 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 574 { 575 struct hnae3_handle *handle; 576 int status; 577 578 handle = &hdev->vport[0].nic; 579 if (handle->client) { 580 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 581 if (status) { 582 dev_err(&hdev->pdev->dev, 583 "Update TQPS stats fail, status = %d.\n", 584 status); 585 } 586 } 587 588 hclge_update_fec_stats(hdev); 589 590 status = hclge_mac_update_stats(hdev); 591 if (status) 592 dev_err(&hdev->pdev->dev, 593 "Update MAC stats fail, status = %d.\n", status); 594 } 595 596 static void hclge_update_stats(struct hnae3_handle *handle) 597 { 598 struct hclge_vport *vport = hclge_get_vport(handle); 599 struct hclge_dev *hdev = vport->back; 600 int status; 601 602 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 603 return; 604 605 status = hclge_mac_update_stats(hdev); 606 if (status) 607 dev_err(&hdev->pdev->dev, 608 "Update MAC stats fail, status = %d.\n", 609 status); 610 611 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 612 if (status) 613 dev_err(&hdev->pdev->dev, 614 "Update TQPS stats fail, status = %d.\n", 615 status); 616 617 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 618 } 619 620 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 621 { 622 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \ 623 HNAE3_SUPPORT_PHY_LOOPBACK | \ 624 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \ 625 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \ 626 HNAE3_SUPPORT_EXTERNAL_LOOPBACK) 627 628 struct hclge_vport *vport = hclge_get_vport(handle); 629 struct hclge_dev *hdev = vport->back; 630 int count = 0; 631 632 /* Loopback test support rules: 633 * mac: only GE mode support 634 * serdes: all mac mode will support include GE/XGE/LGE/CGE 635 * phy: only support when phy device exist on board 636 */ 637 if (stringset == ETH_SS_TEST) { 638 /* clear loopback bit flags at first */ 639 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 640 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 || 641 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 642 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 643 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 644 count += 1; 645 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; 646 } 647 648 count += 1; 649 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; 650 count += 1; 651 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; 652 count += 1; 653 handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK; 654 655 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv && 656 hdev->hw.mac.phydev->drv->set_loopback) || 657 hnae3_dev_phy_imp_supported(hdev)) { 658 count += 1; 659 handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK; 660 } 661 } else if (stringset == ETH_SS_STATS) { 662 count = hclge_comm_get_count(hdev, g_mac_stats_string, 663 ARRAY_SIZE(g_mac_stats_string)) + 664 hclge_comm_tqps_get_sset_count(handle); 665 } 666 667 return count; 668 } 669 670 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset, 671 u8 *data) 672 { 673 struct hclge_vport *vport = hclge_get_vport(handle); 674 struct hclge_dev *hdev = vport->back; 675 u8 *p = (char *)data; 676 int size; 677 678 if (stringset == ETH_SS_STATS) { 679 size = ARRAY_SIZE(g_mac_stats_string); 680 p = hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, 681 size, p); 682 p = hclge_comm_tqps_get_strings(handle, p); 683 } else if (stringset == ETH_SS_TEST) { 684 if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) { 685 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL], 686 ETH_GSTRING_LEN); 687 p += ETH_GSTRING_LEN; 688 } 689 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { 690 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_APP], 691 ETH_GSTRING_LEN); 692 p += ETH_GSTRING_LEN; 693 } 694 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { 695 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES], 696 ETH_GSTRING_LEN); 697 p += ETH_GSTRING_LEN; 698 } 699 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { 700 memcpy(p, 701 hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES], 702 ETH_GSTRING_LEN); 703 p += ETH_GSTRING_LEN; 704 } 705 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 706 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_PHY], 707 ETH_GSTRING_LEN); 708 p += ETH_GSTRING_LEN; 709 } 710 } 711 } 712 713 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 714 { 715 struct hclge_vport *vport = hclge_get_vport(handle); 716 struct hclge_dev *hdev = vport->back; 717 u64 *p; 718 719 p = hclge_comm_get_stats(hdev, g_mac_stats_string, 720 ARRAY_SIZE(g_mac_stats_string), data); 721 p = hclge_comm_tqps_get_stats(handle, p); 722 } 723 724 static void hclge_get_mac_stat(struct hnae3_handle *handle, 725 struct hns3_mac_stats *mac_stats) 726 { 727 struct hclge_vport *vport = hclge_get_vport(handle); 728 struct hclge_dev *hdev = vport->back; 729 730 hclge_update_stats(handle); 731 732 mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num; 733 mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num; 734 } 735 736 static int hclge_parse_func_status(struct hclge_dev *hdev, 737 struct hclge_func_status_cmd *status) 738 { 739 #define HCLGE_MAC_ID_MASK 0xF 740 741 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 742 return -EINVAL; 743 744 /* Set the pf to main pf */ 745 if (status->pf_state & HCLGE_PF_STATE_MAIN) 746 hdev->flag |= HCLGE_FLAG_MAIN; 747 else 748 hdev->flag &= ~HCLGE_FLAG_MAIN; 749 750 hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK; 751 return 0; 752 } 753 754 static int hclge_query_function_status(struct hclge_dev *hdev) 755 { 756 #define HCLGE_QUERY_MAX_CNT 5 757 758 struct hclge_func_status_cmd *req; 759 struct hclge_desc desc; 760 int timeout = 0; 761 int ret; 762 763 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 764 req = (struct hclge_func_status_cmd *)desc.data; 765 766 do { 767 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 768 if (ret) { 769 dev_err(&hdev->pdev->dev, 770 "query function status failed %d.\n", ret); 771 return ret; 772 } 773 774 /* Check pf reset is done */ 775 if (req->pf_state) 776 break; 777 usleep_range(1000, 2000); 778 } while (timeout++ < HCLGE_QUERY_MAX_CNT); 779 780 return hclge_parse_func_status(hdev, req); 781 } 782 783 static int hclge_query_pf_resource(struct hclge_dev *hdev) 784 { 785 struct hclge_pf_res_cmd *req; 786 struct hclge_desc desc; 787 int ret; 788 789 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 790 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 791 if (ret) { 792 dev_err(&hdev->pdev->dev, 793 "query pf resource failed %d.\n", ret); 794 return ret; 795 } 796 797 req = (struct hclge_pf_res_cmd *)desc.data; 798 hdev->num_tqps = le16_to_cpu(req->tqp_num) + 799 le16_to_cpu(req->ext_tqp_num); 800 hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 801 802 if (req->tx_buf_size) 803 hdev->tx_buf_size = 804 le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S; 805 else 806 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 807 808 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT); 809 810 if (req->dv_buf_size) 811 hdev->dv_buf_size = 812 le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S; 813 else 814 hdev->dv_buf_size = HCLGE_DEFAULT_DV; 815 816 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT); 817 818 hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic); 819 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) { 820 dev_err(&hdev->pdev->dev, 821 "only %u msi resources available, not enough for pf(min:2).\n", 822 hdev->num_nic_msi); 823 return -EINVAL; 824 } 825 826 if (hnae3_dev_roce_supported(hdev)) { 827 hdev->num_roce_msi = 828 le16_to_cpu(req->pf_intr_vector_number_roce); 829 830 /* PF should have NIC vectors and Roce vectors, 831 * NIC vectors are queued before Roce vectors. 832 */ 833 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi; 834 } else { 835 hdev->num_msi = hdev->num_nic_msi; 836 } 837 838 return 0; 839 } 840 841 static int hclge_parse_speed(u8 speed_cmd, u32 *speed) 842 { 843 switch (speed_cmd) { 844 case HCLGE_FW_MAC_SPEED_10M: 845 *speed = HCLGE_MAC_SPEED_10M; 846 break; 847 case HCLGE_FW_MAC_SPEED_100M: 848 *speed = HCLGE_MAC_SPEED_100M; 849 break; 850 case HCLGE_FW_MAC_SPEED_1G: 851 *speed = HCLGE_MAC_SPEED_1G; 852 break; 853 case HCLGE_FW_MAC_SPEED_10G: 854 *speed = HCLGE_MAC_SPEED_10G; 855 break; 856 case HCLGE_FW_MAC_SPEED_25G: 857 *speed = HCLGE_MAC_SPEED_25G; 858 break; 859 case HCLGE_FW_MAC_SPEED_40G: 860 *speed = HCLGE_MAC_SPEED_40G; 861 break; 862 case HCLGE_FW_MAC_SPEED_50G: 863 *speed = HCLGE_MAC_SPEED_50G; 864 break; 865 case HCLGE_FW_MAC_SPEED_100G: 866 *speed = HCLGE_MAC_SPEED_100G; 867 break; 868 case HCLGE_FW_MAC_SPEED_200G: 869 *speed = HCLGE_MAC_SPEED_200G; 870 break; 871 default: 872 return -EINVAL; 873 } 874 875 return 0; 876 } 877 878 static const struct hclge_speed_bit_map speed_bit_map[] = { 879 {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT}, 880 {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT}, 881 {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT}, 882 {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT}, 883 {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT}, 884 {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT}, 885 {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BIT}, 886 {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BIT}, 887 {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT}, 888 }; 889 890 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit) 891 { 892 u16 i; 893 894 for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) { 895 if (speed == speed_bit_map[i].speed) { 896 *speed_bit = speed_bit_map[i].speed_bit; 897 return 0; 898 } 899 } 900 901 return -EINVAL; 902 } 903 904 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed) 905 { 906 struct hclge_vport *vport = hclge_get_vport(handle); 907 struct hclge_dev *hdev = vport->back; 908 u32 speed_ability = hdev->hw.mac.speed_ability; 909 u32 speed_bit = 0; 910 int ret; 911 912 ret = hclge_get_speed_bit(speed, &speed_bit); 913 if (ret) 914 return ret; 915 916 if (speed_bit & speed_ability) 917 return 0; 918 919 return -EINVAL; 920 } 921 922 static void hclge_update_fec_support(struct hclge_mac *mac) 923 { 924 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported); 925 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported); 926 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported); 927 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 928 929 if (mac->fec_ability & BIT(HNAE3_FEC_BASER)) 930 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 931 mac->supported); 932 if (mac->fec_ability & BIT(HNAE3_FEC_RS)) 933 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 934 mac->supported); 935 if (mac->fec_ability & BIT(HNAE3_FEC_LLRS)) 936 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 937 mac->supported); 938 if (mac->fec_ability & BIT(HNAE3_FEC_NONE)) 939 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 940 mac->supported); 941 } 942 943 static void hclge_convert_setting_sr(u16 speed_ability, 944 unsigned long *link_mode) 945 { 946 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 947 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 948 link_mode); 949 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 950 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 951 link_mode); 952 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 953 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 954 link_mode); 955 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 956 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 957 link_mode); 958 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 959 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 960 link_mode); 961 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 962 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 963 link_mode); 964 } 965 966 static void hclge_convert_setting_lr(u16 speed_ability, 967 unsigned long *link_mode) 968 { 969 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 970 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 971 link_mode); 972 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 973 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 974 link_mode); 975 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 976 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 977 link_mode); 978 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 979 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 980 link_mode); 981 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 982 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 983 link_mode); 984 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 985 linkmode_set_bit( 986 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 987 link_mode); 988 } 989 990 static void hclge_convert_setting_cr(u16 speed_ability, 991 unsigned long *link_mode) 992 { 993 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 994 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 995 link_mode); 996 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 997 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 998 link_mode); 999 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1000 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 1001 link_mode); 1002 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1003 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 1004 link_mode); 1005 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1006 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 1007 link_mode); 1008 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1009 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 1010 link_mode); 1011 } 1012 1013 static void hclge_convert_setting_kr(u16 speed_ability, 1014 unsigned long *link_mode) 1015 { 1016 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1017 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1018 link_mode); 1019 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1020 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1021 link_mode); 1022 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1023 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 1024 link_mode); 1025 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1026 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 1027 link_mode); 1028 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1029 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 1030 link_mode); 1031 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1032 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 1033 link_mode); 1034 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1035 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 1036 link_mode); 1037 } 1038 1039 static void hclge_convert_setting_fec(struct hclge_mac *mac) 1040 { 1041 /* If firmware has reported fec_ability, don't need to convert by speed */ 1042 if (mac->fec_ability) 1043 goto out; 1044 1045 switch (mac->speed) { 1046 case HCLGE_MAC_SPEED_10G: 1047 case HCLGE_MAC_SPEED_40G: 1048 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) | 1049 BIT(HNAE3_FEC_NONE); 1050 break; 1051 case HCLGE_MAC_SPEED_25G: 1052 case HCLGE_MAC_SPEED_50G: 1053 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) | 1054 BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE); 1055 break; 1056 case HCLGE_MAC_SPEED_100G: 1057 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1058 BIT(HNAE3_FEC_NONE); 1059 break; 1060 case HCLGE_MAC_SPEED_200G: 1061 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1062 BIT(HNAE3_FEC_LLRS); 1063 break; 1064 default: 1065 mac->fec_ability = 0; 1066 break; 1067 } 1068 1069 out: 1070 hclge_update_fec_support(mac); 1071 } 1072 1073 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 1074 u16 speed_ability) 1075 { 1076 struct hclge_mac *mac = &hdev->hw.mac; 1077 1078 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1079 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1080 mac->supported); 1081 1082 hclge_convert_setting_sr(speed_ability, mac->supported); 1083 hclge_convert_setting_lr(speed_ability, mac->supported); 1084 hclge_convert_setting_cr(speed_ability, mac->supported); 1085 if (hnae3_dev_fec_supported(hdev)) 1086 hclge_convert_setting_fec(mac); 1087 1088 if (hnae3_dev_pause_supported(hdev)) 1089 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1090 1091 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported); 1092 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1093 } 1094 1095 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev, 1096 u16 speed_ability) 1097 { 1098 struct hclge_mac *mac = &hdev->hw.mac; 1099 1100 hclge_convert_setting_kr(speed_ability, mac->supported); 1101 if (hnae3_dev_fec_supported(hdev)) 1102 hclge_convert_setting_fec(mac); 1103 1104 if (hnae3_dev_pause_supported(hdev)) 1105 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1106 1107 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported); 1108 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1109 } 1110 1111 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev, 1112 u16 speed_ability) 1113 { 1114 unsigned long *supported = hdev->hw.mac.supported; 1115 1116 /* default to support all speed for GE port */ 1117 if (!speed_ability) 1118 speed_ability = HCLGE_SUPPORT_GE; 1119 1120 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1121 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1122 supported); 1123 1124 if (speed_ability & HCLGE_SUPPORT_100M_BIT) { 1125 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1126 supported); 1127 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1128 supported); 1129 } 1130 1131 if (speed_ability & HCLGE_SUPPORT_10M_BIT) { 1132 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported); 1133 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported); 1134 } 1135 1136 if (hnae3_dev_pause_supported(hdev)) { 1137 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1138 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 1139 } 1140 1141 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 1142 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 1143 } 1144 1145 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 1146 { 1147 u8 media_type = hdev->hw.mac.media_type; 1148 1149 if (media_type == HNAE3_MEDIA_TYPE_FIBER) 1150 hclge_parse_fiber_link_mode(hdev, speed_ability); 1151 else if (media_type == HNAE3_MEDIA_TYPE_COPPER) 1152 hclge_parse_copper_link_mode(hdev, speed_ability); 1153 else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE) 1154 hclge_parse_backplane_link_mode(hdev, speed_ability); 1155 } 1156 1157 static u32 hclge_get_max_speed(u16 speed_ability) 1158 { 1159 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1160 return HCLGE_MAC_SPEED_200G; 1161 1162 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1163 return HCLGE_MAC_SPEED_100G; 1164 1165 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1166 return HCLGE_MAC_SPEED_50G; 1167 1168 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1169 return HCLGE_MAC_SPEED_40G; 1170 1171 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1172 return HCLGE_MAC_SPEED_25G; 1173 1174 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1175 return HCLGE_MAC_SPEED_10G; 1176 1177 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1178 return HCLGE_MAC_SPEED_1G; 1179 1180 if (speed_ability & HCLGE_SUPPORT_100M_BIT) 1181 return HCLGE_MAC_SPEED_100M; 1182 1183 if (speed_ability & HCLGE_SUPPORT_10M_BIT) 1184 return HCLGE_MAC_SPEED_10M; 1185 1186 return HCLGE_MAC_SPEED_1G; 1187 } 1188 1189 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1190 { 1191 #define HCLGE_TX_SPARE_SIZE_UNIT 4096 1192 #define SPEED_ABILITY_EXT_SHIFT 8 1193 1194 struct hclge_cfg_param_cmd *req; 1195 u64 mac_addr_tmp_high; 1196 u16 speed_ability_ext; 1197 u64 mac_addr_tmp; 1198 unsigned int i; 1199 1200 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1201 1202 /* get the configuration */ 1203 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1204 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1205 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1206 HCLGE_CFG_TQP_DESC_N_M, 1207 HCLGE_CFG_TQP_DESC_N_S); 1208 1209 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1210 HCLGE_CFG_PHY_ADDR_M, 1211 HCLGE_CFG_PHY_ADDR_S); 1212 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1213 HCLGE_CFG_MEDIA_TP_M, 1214 HCLGE_CFG_MEDIA_TP_S); 1215 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1216 HCLGE_CFG_RX_BUF_LEN_M, 1217 HCLGE_CFG_RX_BUF_LEN_S); 1218 /* get mac_address */ 1219 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1220 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1221 HCLGE_CFG_MAC_ADDR_H_M, 1222 HCLGE_CFG_MAC_ADDR_H_S); 1223 1224 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1225 1226 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1227 HCLGE_CFG_DEFAULT_SPEED_M, 1228 HCLGE_CFG_DEFAULT_SPEED_S); 1229 cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1230 HCLGE_CFG_RSS_SIZE_M, 1231 HCLGE_CFG_RSS_SIZE_S); 1232 1233 for (i = 0; i < ETH_ALEN; i++) 1234 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1235 1236 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1237 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1238 1239 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1240 HCLGE_CFG_SPEED_ABILITY_M, 1241 HCLGE_CFG_SPEED_ABILITY_S); 1242 speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]), 1243 HCLGE_CFG_SPEED_ABILITY_EXT_M, 1244 HCLGE_CFG_SPEED_ABILITY_EXT_S); 1245 cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT; 1246 1247 cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]), 1248 HCLGE_CFG_VLAN_FLTR_CAP_M, 1249 HCLGE_CFG_VLAN_FLTR_CAP_S); 1250 1251 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]), 1252 HCLGE_CFG_UMV_TBL_SPACE_M, 1253 HCLGE_CFG_UMV_TBL_SPACE_S); 1254 1255 cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]), 1256 HCLGE_CFG_PF_RSS_SIZE_M, 1257 HCLGE_CFG_PF_RSS_SIZE_S); 1258 1259 /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a 1260 * power of 2, instead of reading out directly. This would 1261 * be more flexible for future changes and expansions. 1262 * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S, 1263 * it does not make sense if PF's field is 0. In this case, PF and VF 1264 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S. 1265 */ 1266 cfg->pf_rss_size_max = cfg->pf_rss_size_max ? 1267 1U << cfg->pf_rss_size_max : 1268 cfg->vf_rss_size_max; 1269 1270 /* The unit of the tx spare buffer size queried from configuration 1271 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is 1272 * needed here. 1273 */ 1274 cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]), 1275 HCLGE_CFG_TX_SPARE_BUF_SIZE_M, 1276 HCLGE_CFG_TX_SPARE_BUF_SIZE_S); 1277 cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT; 1278 } 1279 1280 /* hclge_get_cfg: query the static parameter from flash 1281 * @hdev: pointer to struct hclge_dev 1282 * @hcfg: the config structure to be getted 1283 */ 1284 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1285 { 1286 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1287 struct hclge_cfg_param_cmd *req; 1288 unsigned int i; 1289 int ret; 1290 1291 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1292 u32 offset = 0; 1293 1294 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1295 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1296 true); 1297 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1298 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1299 /* Len should be united by 4 bytes when send to hardware */ 1300 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1301 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1302 req->offset = cpu_to_le32(offset); 1303 } 1304 1305 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1306 if (ret) { 1307 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1308 return ret; 1309 } 1310 1311 hclge_parse_cfg(hcfg, desc); 1312 1313 return 0; 1314 } 1315 1316 static void hclge_set_default_dev_specs(struct hclge_dev *hdev) 1317 { 1318 #define HCLGE_MAX_NON_TSO_BD_NUM 8U 1319 1320 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1321 1322 ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1323 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1324 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1325 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE; 1326 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL; 1327 ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME; 1328 ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM; 1329 ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1330 ae_dev->dev_specs.tnl_num = 0; 1331 } 1332 1333 static void hclge_parse_dev_specs(struct hclge_dev *hdev, 1334 struct hclge_desc *desc) 1335 { 1336 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1337 struct hclge_dev_specs_0_cmd *req0; 1338 struct hclge_dev_specs_1_cmd *req1; 1339 1340 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data; 1341 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data; 1342 1343 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 1344 ae_dev->dev_specs.rss_ind_tbl_size = 1345 le16_to_cpu(req0->rss_ind_tbl_size); 1346 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 1347 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 1348 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate); 1349 ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num); 1350 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 1351 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 1352 ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size); 1353 ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size); 1354 ae_dev->dev_specs.tnl_num = req1->tnl_num; 1355 } 1356 1357 static void hclge_check_dev_specs(struct hclge_dev *hdev) 1358 { 1359 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 1360 1361 if (!dev_specs->max_non_tso_bd_num) 1362 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1363 if (!dev_specs->rss_ind_tbl_size) 1364 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1365 if (!dev_specs->rss_key_size) 1366 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1367 if (!dev_specs->max_tm_rate) 1368 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE; 1369 if (!dev_specs->max_qset_num) 1370 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM; 1371 if (!dev_specs->max_int_gl) 1372 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL; 1373 if (!dev_specs->max_frm_size) 1374 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME; 1375 if (!dev_specs->umv_size) 1376 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1377 } 1378 1379 static int hclge_query_mac_stats_num(struct hclge_dev *hdev) 1380 { 1381 u32 reg_num = 0; 1382 int ret; 1383 1384 ret = hclge_mac_query_reg_num(hdev, ®_num); 1385 if (ret && ret != -EOPNOTSUPP) 1386 return ret; 1387 1388 hdev->ae_dev->dev_specs.mac_stats_num = reg_num; 1389 return 0; 1390 } 1391 1392 static int hclge_query_dev_specs(struct hclge_dev *hdev) 1393 { 1394 struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM]; 1395 int ret; 1396 int i; 1397 1398 ret = hclge_query_mac_stats_num(hdev); 1399 if (ret) 1400 return ret; 1401 1402 /* set default specifications as devices lower than version V3 do not 1403 * support querying specifications from firmware. 1404 */ 1405 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 1406 hclge_set_default_dev_specs(hdev); 1407 return 0; 1408 } 1409 1410 for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1411 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, 1412 true); 1413 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 1414 } 1415 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 1416 1417 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM); 1418 if (ret) 1419 return ret; 1420 1421 hclge_parse_dev_specs(hdev, desc); 1422 hclge_check_dev_specs(hdev); 1423 1424 return 0; 1425 } 1426 1427 static int hclge_get_cap(struct hclge_dev *hdev) 1428 { 1429 int ret; 1430 1431 ret = hclge_query_function_status(hdev); 1432 if (ret) { 1433 dev_err(&hdev->pdev->dev, 1434 "query function status error %d.\n", ret); 1435 return ret; 1436 } 1437 1438 /* get pf resource */ 1439 return hclge_query_pf_resource(hdev); 1440 } 1441 1442 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev) 1443 { 1444 #define HCLGE_MIN_TX_DESC 64 1445 #define HCLGE_MIN_RX_DESC 64 1446 1447 if (!is_kdump_kernel()) 1448 return; 1449 1450 dev_info(&hdev->pdev->dev, 1451 "Running kdump kernel. Using minimal resources\n"); 1452 1453 /* minimal queue pairs equals to the number of vports */ 1454 hdev->num_tqps = hdev->num_req_vfs + 1; 1455 hdev->num_tx_desc = HCLGE_MIN_TX_DESC; 1456 hdev->num_rx_desc = HCLGE_MIN_RX_DESC; 1457 } 1458 1459 static void hclge_init_tc_config(struct hclge_dev *hdev) 1460 { 1461 unsigned int i; 1462 1463 if (hdev->tc_max > HNAE3_MAX_TC || 1464 hdev->tc_max < 1) { 1465 dev_warn(&hdev->pdev->dev, "TC num = %u.\n", 1466 hdev->tc_max); 1467 hdev->tc_max = 1; 1468 } 1469 1470 /* Dev does not support DCB */ 1471 if (!hnae3_dev_dcb_supported(hdev)) { 1472 hdev->tc_max = 1; 1473 hdev->pfc_max = 0; 1474 } else { 1475 hdev->pfc_max = hdev->tc_max; 1476 } 1477 1478 hdev->tm_info.num_tc = 1; 1479 1480 /* Currently not support uncontiuous tc */ 1481 for (i = 0; i < hdev->tm_info.num_tc; i++) 1482 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1483 1484 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1485 } 1486 1487 static int hclge_configure(struct hclge_dev *hdev) 1488 { 1489 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1490 struct hclge_cfg cfg; 1491 int ret; 1492 1493 ret = hclge_get_cfg(hdev, &cfg); 1494 if (ret) 1495 return ret; 1496 1497 hdev->base_tqp_pid = 0; 1498 hdev->vf_rss_size_max = cfg.vf_rss_size_max; 1499 hdev->pf_rss_size_max = cfg.pf_rss_size_max; 1500 hdev->rx_buf_len = cfg.rx_buf_len; 1501 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1502 hdev->hw.mac.media_type = cfg.media_type; 1503 hdev->hw.mac.phy_addr = cfg.phy_addr; 1504 hdev->num_tx_desc = cfg.tqp_desc_num; 1505 hdev->num_rx_desc = cfg.tqp_desc_num; 1506 hdev->tm_info.num_pg = 1; 1507 hdev->tc_max = cfg.tc_num; 1508 hdev->tm_info.hw_pfc_map = 0; 1509 if (cfg.umv_space) 1510 hdev->wanted_umv_size = cfg.umv_space; 1511 else 1512 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size; 1513 hdev->tx_spare_buf_size = cfg.tx_spare_buf_size; 1514 hdev->gro_en = true; 1515 if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF) 1516 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 1517 1518 if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 1519 hdev->fd_en = true; 1520 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 1521 } 1522 1523 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1524 if (ret) { 1525 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n", 1526 cfg.default_speed, ret); 1527 return ret; 1528 } 1529 1530 hclge_parse_link_mode(hdev, cfg.speed_ability); 1531 1532 hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability); 1533 1534 hclge_init_tc_config(hdev); 1535 hclge_init_kdump_kernel_config(hdev); 1536 1537 return ret; 1538 } 1539 1540 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min, 1541 u16 tso_mss_max) 1542 { 1543 struct hclge_cfg_tso_status_cmd *req; 1544 struct hclge_desc desc; 1545 1546 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1547 1548 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1549 req->tso_mss_min = cpu_to_le16(tso_mss_min); 1550 req->tso_mss_max = cpu_to_le16(tso_mss_max); 1551 1552 return hclge_cmd_send(&hdev->hw, &desc, 1); 1553 } 1554 1555 static int hclge_config_gro(struct hclge_dev *hdev) 1556 { 1557 struct hclge_cfg_gro_status_cmd *req; 1558 struct hclge_desc desc; 1559 int ret; 1560 1561 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 1562 return 0; 1563 1564 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false); 1565 req = (struct hclge_cfg_gro_status_cmd *)desc.data; 1566 1567 req->gro_en = hdev->gro_en ? 1 : 0; 1568 1569 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1570 if (ret) 1571 dev_err(&hdev->pdev->dev, 1572 "GRO hardware config cmd failed, ret = %d\n", ret); 1573 1574 return ret; 1575 } 1576 1577 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1578 { 1579 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1580 struct hclge_comm_tqp *tqp; 1581 int i; 1582 1583 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1584 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 1585 if (!hdev->htqp) 1586 return -ENOMEM; 1587 1588 tqp = hdev->htqp; 1589 1590 for (i = 0; i < hdev->num_tqps; i++) { 1591 tqp->dev = &hdev->pdev->dev; 1592 tqp->index = i; 1593 1594 tqp->q.ae_algo = &ae_algo; 1595 tqp->q.buf_size = hdev->rx_buf_len; 1596 tqp->q.tx_desc_num = hdev->num_tx_desc; 1597 tqp->q.rx_desc_num = hdev->num_rx_desc; 1598 1599 /* need an extended offset to configure queues >= 1600 * HCLGE_TQP_MAX_SIZE_DEV_V2 1601 */ 1602 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2) 1603 tqp->q.io_base = hdev->hw.hw.io_base + 1604 HCLGE_TQP_REG_OFFSET + 1605 i * HCLGE_TQP_REG_SIZE; 1606 else 1607 tqp->q.io_base = hdev->hw.hw.io_base + 1608 HCLGE_TQP_REG_OFFSET + 1609 HCLGE_TQP_EXT_REG_OFFSET + 1610 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) * 1611 HCLGE_TQP_REG_SIZE; 1612 1613 /* when device supports tx push and has device memory, 1614 * the queue can execute push mode or doorbell mode on 1615 * device memory. 1616 */ 1617 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 1618 tqp->q.mem_base = hdev->hw.hw.mem_base + 1619 HCLGE_TQP_MEM_OFFSET(hdev, i); 1620 1621 tqp++; 1622 } 1623 1624 return 0; 1625 } 1626 1627 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1628 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1629 { 1630 struct hclge_tqp_map_cmd *req; 1631 struct hclge_desc desc; 1632 int ret; 1633 1634 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1635 1636 req = (struct hclge_tqp_map_cmd *)desc.data; 1637 req->tqp_id = cpu_to_le16(tqp_pid); 1638 req->tqp_vf = func_id; 1639 req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B; 1640 if (!is_pf) 1641 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B; 1642 req->tqp_vid = cpu_to_le16(tqp_vid); 1643 1644 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1645 if (ret) 1646 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1647 1648 return ret; 1649 } 1650 1651 static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) 1652 { 1653 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1654 struct hclge_dev *hdev = vport->back; 1655 int i, alloced; 1656 1657 for (i = 0, alloced = 0; i < hdev->num_tqps && 1658 alloced < num_tqps; i++) { 1659 if (!hdev->htqp[i].alloced) { 1660 hdev->htqp[i].q.handle = &vport->nic; 1661 hdev->htqp[i].q.tqp_index = alloced; 1662 hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc; 1663 hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc; 1664 kinfo->tqp[alloced] = &hdev->htqp[i].q; 1665 hdev->htqp[i].alloced = true; 1666 alloced++; 1667 } 1668 } 1669 vport->alloc_tqps = alloced; 1670 kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max, 1671 vport->alloc_tqps / hdev->tm_info.num_tc); 1672 1673 /* ensure one to one mapping between irq and queue at default */ 1674 kinfo->rss_size = min_t(u16, kinfo->rss_size, 1675 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc); 1676 1677 return 0; 1678 } 1679 1680 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps, 1681 u16 num_tx_desc, u16 num_rx_desc) 1682 1683 { 1684 struct hnae3_handle *nic = &vport->nic; 1685 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1686 struct hclge_dev *hdev = vport->back; 1687 int ret; 1688 1689 kinfo->num_tx_desc = num_tx_desc; 1690 kinfo->num_rx_desc = num_rx_desc; 1691 1692 kinfo->rx_buf_len = hdev->rx_buf_len; 1693 kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size; 1694 1695 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps, 1696 sizeof(struct hnae3_queue *), GFP_KERNEL); 1697 if (!kinfo->tqp) 1698 return -ENOMEM; 1699 1700 ret = hclge_assign_tqp(vport, num_tqps); 1701 if (ret) 1702 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1703 1704 return ret; 1705 } 1706 1707 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1708 struct hclge_vport *vport) 1709 { 1710 struct hnae3_handle *nic = &vport->nic; 1711 struct hnae3_knic_private_info *kinfo; 1712 u16 i; 1713 1714 kinfo = &nic->kinfo; 1715 for (i = 0; i < vport->alloc_tqps; i++) { 1716 struct hclge_comm_tqp *q = 1717 container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); 1718 bool is_pf; 1719 int ret; 1720 1721 is_pf = !(vport->vport_id); 1722 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1723 i, is_pf); 1724 if (ret) 1725 return ret; 1726 } 1727 1728 return 0; 1729 } 1730 1731 static int hclge_map_tqp(struct hclge_dev *hdev) 1732 { 1733 struct hclge_vport *vport = hdev->vport; 1734 u16 i, num_vport; 1735 1736 num_vport = hdev->num_req_vfs + 1; 1737 for (i = 0; i < num_vport; i++) { 1738 int ret; 1739 1740 ret = hclge_map_tqp_to_vport(hdev, vport); 1741 if (ret) 1742 return ret; 1743 1744 vport++; 1745 } 1746 1747 return 0; 1748 } 1749 1750 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1751 { 1752 struct hnae3_handle *nic = &vport->nic; 1753 struct hclge_dev *hdev = vport->back; 1754 int ret; 1755 1756 nic->pdev = hdev->pdev; 1757 nic->ae_algo = &ae_algo; 1758 nic->numa_node_mask = hdev->numa_node_mask; 1759 nic->kinfo.io_base = hdev->hw.hw.io_base; 1760 1761 ret = hclge_knic_setup(vport, num_tqps, 1762 hdev->num_tx_desc, hdev->num_rx_desc); 1763 if (ret) 1764 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret); 1765 1766 return ret; 1767 } 1768 1769 static int hclge_alloc_vport(struct hclge_dev *hdev) 1770 { 1771 struct pci_dev *pdev = hdev->pdev; 1772 struct hclge_vport *vport; 1773 u32 tqp_main_vport; 1774 u32 tqp_per_vport; 1775 int num_vport, i; 1776 int ret; 1777 1778 /* We need to alloc a vport for main NIC of PF */ 1779 num_vport = hdev->num_req_vfs + 1; 1780 1781 if (hdev->num_tqps < num_vport) { 1782 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)", 1783 hdev->num_tqps, num_vport); 1784 return -EINVAL; 1785 } 1786 1787 /* Alloc the same number of TQPs for every vport */ 1788 tqp_per_vport = hdev->num_tqps / num_vport; 1789 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1790 1791 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1792 GFP_KERNEL); 1793 if (!vport) 1794 return -ENOMEM; 1795 1796 hdev->vport = vport; 1797 hdev->num_alloc_vport = num_vport; 1798 1799 if (IS_ENABLED(CONFIG_PCI_IOV)) 1800 hdev->num_alloc_vfs = hdev->num_req_vfs; 1801 1802 for (i = 0; i < num_vport; i++) { 1803 vport->back = hdev; 1804 vport->vport_id = i; 1805 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO; 1806 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 1807 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE; 1808 vport->port_base_vlan_cfg.tbl_sta = true; 1809 vport->rxvlan_cfg.rx_vlan_offload_en = true; 1810 vport->req_vlan_fltr_en = true; 1811 INIT_LIST_HEAD(&vport->vlan_list); 1812 INIT_LIST_HEAD(&vport->uc_mac_list); 1813 INIT_LIST_HEAD(&vport->mc_mac_list); 1814 spin_lock_init(&vport->mac_list_lock); 1815 1816 if (i == 0) 1817 ret = hclge_vport_setup(vport, tqp_main_vport); 1818 else 1819 ret = hclge_vport_setup(vport, tqp_per_vport); 1820 if (ret) { 1821 dev_err(&pdev->dev, 1822 "vport setup failed for vport %d, %d\n", 1823 i, ret); 1824 return ret; 1825 } 1826 1827 vport++; 1828 } 1829 1830 return 0; 1831 } 1832 1833 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1834 struct hclge_pkt_buf_alloc *buf_alloc) 1835 { 1836 /* TX buffer size is unit by 128 byte */ 1837 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1838 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1839 struct hclge_tx_buff_alloc_cmd *req; 1840 struct hclge_desc desc; 1841 int ret; 1842 u8 i; 1843 1844 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1845 1846 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1847 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1848 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1849 1850 req->tx_pkt_buff[i] = 1851 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1852 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1853 } 1854 1855 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1856 if (ret) 1857 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1858 ret); 1859 1860 return ret; 1861 } 1862 1863 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1864 struct hclge_pkt_buf_alloc *buf_alloc) 1865 { 1866 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1867 1868 if (ret) 1869 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1870 1871 return ret; 1872 } 1873 1874 static u32 hclge_get_tc_num(struct hclge_dev *hdev) 1875 { 1876 unsigned int i; 1877 u32 cnt = 0; 1878 1879 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1880 if (hdev->hw_tc_map & BIT(i)) 1881 cnt++; 1882 return cnt; 1883 } 1884 1885 /* Get the number of pfc enabled TCs, which have private buffer */ 1886 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1887 struct hclge_pkt_buf_alloc *buf_alloc) 1888 { 1889 struct hclge_priv_buf *priv; 1890 unsigned int i; 1891 int cnt = 0; 1892 1893 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1894 priv = &buf_alloc->priv_buf[i]; 1895 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1896 priv->enable) 1897 cnt++; 1898 } 1899 1900 return cnt; 1901 } 1902 1903 /* Get the number of pfc disabled TCs, which have private buffer */ 1904 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1905 struct hclge_pkt_buf_alloc *buf_alloc) 1906 { 1907 struct hclge_priv_buf *priv; 1908 unsigned int i; 1909 int cnt = 0; 1910 1911 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1912 priv = &buf_alloc->priv_buf[i]; 1913 if (hdev->hw_tc_map & BIT(i) && 1914 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 1915 priv->enable) 1916 cnt++; 1917 } 1918 1919 return cnt; 1920 } 1921 1922 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1923 { 1924 struct hclge_priv_buf *priv; 1925 u32 rx_priv = 0; 1926 int i; 1927 1928 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1929 priv = &buf_alloc->priv_buf[i]; 1930 if (priv->enable) 1931 rx_priv += priv->buf_size; 1932 } 1933 return rx_priv; 1934 } 1935 1936 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1937 { 1938 u32 i, total_tx_size = 0; 1939 1940 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1941 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 1942 1943 return total_tx_size; 1944 } 1945 1946 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 1947 struct hclge_pkt_buf_alloc *buf_alloc, 1948 u32 rx_all) 1949 { 1950 u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 1951 u32 tc_num = hclge_get_tc_num(hdev); 1952 u32 shared_buf, aligned_mps; 1953 u32 rx_priv; 1954 int i; 1955 1956 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT); 1957 1958 if (hnae3_dev_dcb_supported(hdev)) 1959 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps + 1960 hdev->dv_buf_size; 1961 else 1962 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF 1963 + hdev->dv_buf_size; 1964 1965 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 1966 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc), 1967 HCLGE_BUF_SIZE_UNIT); 1968 1969 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 1970 if (rx_all < rx_priv + shared_std) 1971 return false; 1972 1973 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT); 1974 buf_alloc->s_buf.buf_size = shared_buf; 1975 if (hnae3_dev_dcb_supported(hdev)) { 1976 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size; 1977 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 1978 - roundup(aligned_mps / HCLGE_BUF_DIV_BY, 1979 HCLGE_BUF_SIZE_UNIT); 1980 } else { 1981 buf_alloc->s_buf.self.high = aligned_mps + 1982 HCLGE_NON_DCB_ADDITIONAL_BUF; 1983 buf_alloc->s_buf.self.low = aligned_mps; 1984 } 1985 1986 if (hnae3_dev_dcb_supported(hdev)) { 1987 hi_thrd = shared_buf - hdev->dv_buf_size; 1988 1989 if (tc_num <= NEED_RESERVE_TC_NUM) 1990 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 1991 / BUF_MAX_PERCENT; 1992 1993 if (tc_num) 1994 hi_thrd = hi_thrd / tc_num; 1995 1996 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps); 1997 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT); 1998 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY; 1999 } else { 2000 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF; 2001 lo_thrd = aligned_mps; 2002 } 2003 2004 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2005 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 2006 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 2007 } 2008 2009 return true; 2010 } 2011 2012 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 2013 struct hclge_pkt_buf_alloc *buf_alloc) 2014 { 2015 u32 i, total_size; 2016 2017 total_size = hdev->pkt_buf_size; 2018 2019 /* alloc tx buffer for all enabled tc */ 2020 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2021 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2022 2023 if (hdev->hw_tc_map & BIT(i)) { 2024 if (total_size < hdev->tx_buf_size) 2025 return -ENOMEM; 2026 2027 priv->tx_buf_size = hdev->tx_buf_size; 2028 } else { 2029 priv->tx_buf_size = 0; 2030 } 2031 2032 total_size -= priv->tx_buf_size; 2033 } 2034 2035 return 0; 2036 } 2037 2038 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max, 2039 struct hclge_pkt_buf_alloc *buf_alloc) 2040 { 2041 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2042 u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2043 unsigned int i; 2044 2045 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2046 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2047 2048 priv->enable = 0; 2049 priv->wl.low = 0; 2050 priv->wl.high = 0; 2051 priv->buf_size = 0; 2052 2053 if (!(hdev->hw_tc_map & BIT(i))) 2054 continue; 2055 2056 priv->enable = 1; 2057 2058 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 2059 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT; 2060 priv->wl.high = roundup(priv->wl.low + aligned_mps, 2061 HCLGE_BUF_SIZE_UNIT); 2062 } else { 2063 priv->wl.low = 0; 2064 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) : 2065 aligned_mps; 2066 } 2067 2068 priv->buf_size = priv->wl.high + hdev->dv_buf_size; 2069 } 2070 2071 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2072 } 2073 2074 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev, 2075 struct hclge_pkt_buf_alloc *buf_alloc) 2076 { 2077 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2078 int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 2079 int i; 2080 2081 /* let the last to be cleared first */ 2082 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2083 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2084 unsigned int mask = BIT((unsigned int)i); 2085 2086 if (hdev->hw_tc_map & mask && 2087 !(hdev->tm_info.hw_pfc_map & mask)) { 2088 /* Clear the no pfc TC private buffer */ 2089 priv->wl.low = 0; 2090 priv->wl.high = 0; 2091 priv->buf_size = 0; 2092 priv->enable = 0; 2093 no_pfc_priv_num--; 2094 } 2095 2096 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2097 no_pfc_priv_num == 0) 2098 break; 2099 } 2100 2101 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2102 } 2103 2104 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev, 2105 struct hclge_pkt_buf_alloc *buf_alloc) 2106 { 2107 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2108 int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 2109 int i; 2110 2111 /* let the last to be cleared first */ 2112 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2113 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2114 unsigned int mask = BIT((unsigned int)i); 2115 2116 if (hdev->hw_tc_map & mask && 2117 hdev->tm_info.hw_pfc_map & mask) { 2118 /* Reduce the number of pfc TC with private buffer */ 2119 priv->wl.low = 0; 2120 priv->enable = 0; 2121 priv->wl.high = 0; 2122 priv->buf_size = 0; 2123 pfc_priv_num--; 2124 } 2125 2126 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2127 pfc_priv_num == 0) 2128 break; 2129 } 2130 2131 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2132 } 2133 2134 static int hclge_only_alloc_priv_buff(struct hclge_dev *hdev, 2135 struct hclge_pkt_buf_alloc *buf_alloc) 2136 { 2137 #define COMPENSATE_BUFFER 0x3C00 2138 #define COMPENSATE_HALF_MPS_NUM 5 2139 #define PRIV_WL_GAP 0x1800 2140 2141 u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2142 u32 tc_num = hclge_get_tc_num(hdev); 2143 u32 half_mps = hdev->mps >> 1; 2144 u32 min_rx_priv; 2145 unsigned int i; 2146 2147 if (tc_num) 2148 rx_priv = rx_priv / tc_num; 2149 2150 if (tc_num <= NEED_RESERVE_TC_NUM) 2151 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 2152 2153 min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER + 2154 COMPENSATE_HALF_MPS_NUM * half_mps; 2155 min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT); 2156 rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT); 2157 if (rx_priv < min_rx_priv) 2158 return false; 2159 2160 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2161 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2162 2163 priv->enable = 0; 2164 priv->wl.low = 0; 2165 priv->wl.high = 0; 2166 priv->buf_size = 0; 2167 2168 if (!(hdev->hw_tc_map & BIT(i))) 2169 continue; 2170 2171 priv->enable = 1; 2172 priv->buf_size = rx_priv; 2173 priv->wl.high = rx_priv - hdev->dv_buf_size; 2174 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 2175 } 2176 2177 buf_alloc->s_buf.buf_size = 0; 2178 2179 return true; 2180 } 2181 2182 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 2183 * @hdev: pointer to struct hclge_dev 2184 * @buf_alloc: pointer to buffer calculation data 2185 * @return: 0: calculate successful, negative: fail 2186 */ 2187 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 2188 struct hclge_pkt_buf_alloc *buf_alloc) 2189 { 2190 /* When DCB is not supported, rx private buffer is not allocated. */ 2191 if (!hnae3_dev_dcb_supported(hdev)) { 2192 u32 rx_all = hdev->pkt_buf_size; 2193 2194 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 2195 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 2196 return -ENOMEM; 2197 2198 return 0; 2199 } 2200 2201 if (hclge_only_alloc_priv_buff(hdev, buf_alloc)) 2202 return 0; 2203 2204 if (hclge_rx_buf_calc_all(hdev, true, buf_alloc)) 2205 return 0; 2206 2207 /* try to decrease the buffer size */ 2208 if (hclge_rx_buf_calc_all(hdev, false, buf_alloc)) 2209 return 0; 2210 2211 if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc)) 2212 return 0; 2213 2214 if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc)) 2215 return 0; 2216 2217 return -ENOMEM; 2218 } 2219 2220 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 2221 struct hclge_pkt_buf_alloc *buf_alloc) 2222 { 2223 struct hclge_rx_priv_buff_cmd *req; 2224 struct hclge_desc desc; 2225 int ret; 2226 int i; 2227 2228 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 2229 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 2230 2231 /* Alloc private buffer TCs */ 2232 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2233 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2234 2235 req->buf_num[i] = 2236 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 2237 req->buf_num[i] |= 2238 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 2239 } 2240 2241 req->shared_buf = 2242 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 2243 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 2244 2245 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2246 if (ret) 2247 dev_err(&hdev->pdev->dev, 2248 "rx private buffer alloc cmd failed %d\n", ret); 2249 2250 return ret; 2251 } 2252 2253 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 2254 struct hclge_pkt_buf_alloc *buf_alloc) 2255 { 2256 struct hclge_rx_priv_wl_buf *req; 2257 struct hclge_priv_buf *priv; 2258 struct hclge_desc desc[2]; 2259 int i, j; 2260 int ret; 2261 2262 for (i = 0; i < 2; i++) { 2263 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 2264 false); 2265 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 2266 2267 /* The first descriptor set the NEXT bit to 1 */ 2268 if (i == 0) 2269 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2270 else 2271 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2272 2273 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2274 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 2275 2276 priv = &buf_alloc->priv_buf[idx]; 2277 req->tc_wl[j].high = 2278 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 2279 req->tc_wl[j].high |= 2280 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2281 req->tc_wl[j].low = 2282 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 2283 req->tc_wl[j].low |= 2284 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2285 } 2286 } 2287 2288 /* Send 2 descriptor at one time */ 2289 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2290 if (ret) 2291 dev_err(&hdev->pdev->dev, 2292 "rx private waterline config cmd failed %d\n", 2293 ret); 2294 return ret; 2295 } 2296 2297 static int hclge_common_thrd_config(struct hclge_dev *hdev, 2298 struct hclge_pkt_buf_alloc *buf_alloc) 2299 { 2300 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 2301 struct hclge_rx_com_thrd *req; 2302 struct hclge_desc desc[2]; 2303 struct hclge_tc_thrd *tc; 2304 int i, j; 2305 int ret; 2306 2307 for (i = 0; i < 2; i++) { 2308 hclge_cmd_setup_basic_desc(&desc[i], 2309 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 2310 req = (struct hclge_rx_com_thrd *)&desc[i].data; 2311 2312 /* The first descriptor set the NEXT bit to 1 */ 2313 if (i == 0) 2314 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2315 else 2316 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2317 2318 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2319 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 2320 2321 req->com_thrd[j].high = 2322 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 2323 req->com_thrd[j].high |= 2324 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2325 req->com_thrd[j].low = 2326 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 2327 req->com_thrd[j].low |= 2328 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2329 } 2330 } 2331 2332 /* Send 2 descriptors at one time */ 2333 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2334 if (ret) 2335 dev_err(&hdev->pdev->dev, 2336 "common threshold config cmd failed %d\n", ret); 2337 return ret; 2338 } 2339 2340 static int hclge_common_wl_config(struct hclge_dev *hdev, 2341 struct hclge_pkt_buf_alloc *buf_alloc) 2342 { 2343 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 2344 struct hclge_rx_com_wl *req; 2345 struct hclge_desc desc; 2346 int ret; 2347 2348 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 2349 2350 req = (struct hclge_rx_com_wl *)desc.data; 2351 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 2352 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2353 2354 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 2355 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2356 2357 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2358 if (ret) 2359 dev_err(&hdev->pdev->dev, 2360 "common waterline config cmd failed %d\n", ret); 2361 2362 return ret; 2363 } 2364 2365 int hclge_buffer_alloc(struct hclge_dev *hdev) 2366 { 2367 struct hclge_pkt_buf_alloc *pkt_buf; 2368 int ret; 2369 2370 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 2371 if (!pkt_buf) 2372 return -ENOMEM; 2373 2374 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 2375 if (ret) { 2376 dev_err(&hdev->pdev->dev, 2377 "could not calc tx buffer size for all TCs %d\n", ret); 2378 goto out; 2379 } 2380 2381 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 2382 if (ret) { 2383 dev_err(&hdev->pdev->dev, 2384 "could not alloc tx buffers %d\n", ret); 2385 goto out; 2386 } 2387 2388 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 2389 if (ret) { 2390 dev_err(&hdev->pdev->dev, 2391 "could not calc rx priv buffer size for all TCs %d\n", 2392 ret); 2393 goto out; 2394 } 2395 2396 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 2397 if (ret) { 2398 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 2399 ret); 2400 goto out; 2401 } 2402 2403 if (hnae3_dev_dcb_supported(hdev)) { 2404 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2405 if (ret) { 2406 dev_err(&hdev->pdev->dev, 2407 "could not configure rx private waterline %d\n", 2408 ret); 2409 goto out; 2410 } 2411 2412 ret = hclge_common_thrd_config(hdev, pkt_buf); 2413 if (ret) { 2414 dev_err(&hdev->pdev->dev, 2415 "could not configure common threshold %d\n", 2416 ret); 2417 goto out; 2418 } 2419 } 2420 2421 ret = hclge_common_wl_config(hdev, pkt_buf); 2422 if (ret) 2423 dev_err(&hdev->pdev->dev, 2424 "could not configure common waterline %d\n", ret); 2425 2426 out: 2427 kfree(pkt_buf); 2428 return ret; 2429 } 2430 2431 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2432 { 2433 struct hnae3_handle *roce = &vport->roce; 2434 struct hnae3_handle *nic = &vport->nic; 2435 struct hclge_dev *hdev = vport->back; 2436 2437 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2438 2439 if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi) 2440 return -EINVAL; 2441 2442 roce->rinfo.base_vector = hdev->num_nic_msi; 2443 2444 roce->rinfo.netdev = nic->kinfo.netdev; 2445 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2446 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2447 2448 roce->pdev = nic->pdev; 2449 roce->ae_algo = nic->ae_algo; 2450 roce->numa_node_mask = nic->numa_node_mask; 2451 2452 return 0; 2453 } 2454 2455 static int hclge_init_msi(struct hclge_dev *hdev) 2456 { 2457 struct pci_dev *pdev = hdev->pdev; 2458 int vectors; 2459 int i; 2460 2461 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2462 hdev->num_msi, 2463 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2464 if (vectors < 0) { 2465 dev_err(&pdev->dev, 2466 "failed(%d) to allocate MSI/MSI-X vectors\n", 2467 vectors); 2468 return vectors; 2469 } 2470 if (vectors < hdev->num_msi) 2471 dev_warn(&hdev->pdev->dev, 2472 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2473 hdev->num_msi, vectors); 2474 2475 hdev->num_msi = vectors; 2476 hdev->num_msi_left = vectors; 2477 2478 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2479 sizeof(u16), GFP_KERNEL); 2480 if (!hdev->vector_status) { 2481 pci_free_irq_vectors(pdev); 2482 return -ENOMEM; 2483 } 2484 2485 for (i = 0; i < hdev->num_msi; i++) 2486 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2487 2488 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2489 sizeof(int), GFP_KERNEL); 2490 if (!hdev->vector_irq) { 2491 pci_free_irq_vectors(pdev); 2492 return -ENOMEM; 2493 } 2494 2495 return 0; 2496 } 2497 2498 static u8 hclge_check_speed_dup(u8 duplex, int speed) 2499 { 2500 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 2501 duplex = HCLGE_MAC_FULL; 2502 2503 return duplex; 2504 } 2505 2506 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = { 2507 {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M}, 2508 {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M}, 2509 {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G}, 2510 {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G}, 2511 {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G}, 2512 {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G}, 2513 {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G}, 2514 {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G}, 2515 {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G}, 2516 }; 2517 2518 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw) 2519 { 2520 u16 i; 2521 2522 for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) { 2523 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) { 2524 *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw; 2525 return 0; 2526 } 2527 } 2528 2529 return -EINVAL; 2530 } 2531 2532 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 2533 u8 duplex, u8 lane_num) 2534 { 2535 struct hclge_config_mac_speed_dup_cmd *req; 2536 struct hclge_desc desc; 2537 u32 speed_fw; 2538 int ret; 2539 2540 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2541 2542 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2543 2544 if (duplex) 2545 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1); 2546 2547 ret = hclge_convert_to_fw_speed(speed, &speed_fw); 2548 if (ret) { 2549 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2550 return ret; 2551 } 2552 2553 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S, 2554 speed_fw); 2555 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2556 1); 2557 req->lane_num = lane_num; 2558 2559 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2560 if (ret) { 2561 dev_err(&hdev->pdev->dev, 2562 "mac speed/duplex config cmd failed %d.\n", ret); 2563 return ret; 2564 } 2565 2566 return 0; 2567 } 2568 2569 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num) 2570 { 2571 struct hclge_mac *mac = &hdev->hw.mac; 2572 int ret; 2573 2574 duplex = hclge_check_speed_dup(duplex, speed); 2575 if (!mac->support_autoneg && mac->speed == speed && 2576 mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0)) 2577 return 0; 2578 2579 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num); 2580 if (ret) 2581 return ret; 2582 2583 hdev->hw.mac.speed = speed; 2584 hdev->hw.mac.duplex = duplex; 2585 if (!lane_num) 2586 hdev->hw.mac.lane_num = lane_num; 2587 2588 return 0; 2589 } 2590 2591 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2592 u8 duplex, u8 lane_num) 2593 { 2594 struct hclge_vport *vport = hclge_get_vport(handle); 2595 struct hclge_dev *hdev = vport->back; 2596 2597 return hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num); 2598 } 2599 2600 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2601 { 2602 struct hclge_config_auto_neg_cmd *req; 2603 struct hclge_desc desc; 2604 u32 flag = 0; 2605 int ret; 2606 2607 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2608 2609 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2610 if (enable) 2611 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U); 2612 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2613 2614 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2615 if (ret) 2616 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2617 ret); 2618 2619 return ret; 2620 } 2621 2622 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2623 { 2624 struct hclge_vport *vport = hclge_get_vport(handle); 2625 struct hclge_dev *hdev = vport->back; 2626 2627 if (!hdev->hw.mac.support_autoneg) { 2628 if (enable) { 2629 dev_err(&hdev->pdev->dev, 2630 "autoneg is not supported by current port\n"); 2631 return -EOPNOTSUPP; 2632 } else { 2633 return 0; 2634 } 2635 } 2636 2637 return hclge_set_autoneg_en(hdev, enable); 2638 } 2639 2640 static int hclge_get_autoneg(struct hnae3_handle *handle) 2641 { 2642 struct hclge_vport *vport = hclge_get_vport(handle); 2643 struct hclge_dev *hdev = vport->back; 2644 struct phy_device *phydev = hdev->hw.mac.phydev; 2645 2646 if (phydev) 2647 return phydev->autoneg; 2648 2649 return hdev->hw.mac.autoneg; 2650 } 2651 2652 static int hclge_restart_autoneg(struct hnae3_handle *handle) 2653 { 2654 struct hclge_vport *vport = hclge_get_vport(handle); 2655 struct hclge_dev *hdev = vport->back; 2656 int ret; 2657 2658 dev_dbg(&hdev->pdev->dev, "restart autoneg\n"); 2659 2660 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2661 if (ret) 2662 return ret; 2663 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2664 } 2665 2666 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt) 2667 { 2668 struct hclge_vport *vport = hclge_get_vport(handle); 2669 struct hclge_dev *hdev = vport->back; 2670 2671 if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) 2672 return hclge_set_autoneg_en(hdev, !halt); 2673 2674 return 0; 2675 } 2676 2677 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev, 2678 struct hclge_desc *desc, u32 desc_len) 2679 { 2680 u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2; 2681 u32 desc_index = 0; 2682 u32 data_index = 0; 2683 u32 i; 2684 2685 for (i = 0; i < lane_size; i++) { 2686 if (data_index >= HCLGE_DESC_DATA_LEN) { 2687 desc_index++; 2688 data_index = 0; 2689 } 2690 2691 if (desc_index >= desc_len) 2692 return; 2693 2694 hdev->fec_stats.per_lanes[i] += 2695 le32_to_cpu(desc[desc_index].data[data_index]); 2696 data_index++; 2697 } 2698 } 2699 2700 static void hclge_parse_fec_stats(struct hclge_dev *hdev, 2701 struct hclge_desc *desc, u32 desc_len) 2702 { 2703 struct hclge_query_fec_stats_cmd *req; 2704 2705 req = (struct hclge_query_fec_stats_cmd *)desc[0].data; 2706 2707 hdev->fec_stats.base_r_lane_num = req->base_r_lane_num; 2708 hdev->fec_stats.rs_corr_blocks += 2709 le32_to_cpu(req->rs_fec_corr_blocks); 2710 hdev->fec_stats.rs_uncorr_blocks += 2711 le32_to_cpu(req->rs_fec_uncorr_blocks); 2712 hdev->fec_stats.rs_error_blocks += 2713 le32_to_cpu(req->rs_fec_error_blocks); 2714 hdev->fec_stats.base_r_corr_blocks += 2715 le32_to_cpu(req->base_r_fec_corr_blocks); 2716 hdev->fec_stats.base_r_uncorr_blocks += 2717 le32_to_cpu(req->base_r_fec_uncorr_blocks); 2718 2719 hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1); 2720 } 2721 2722 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev) 2723 { 2724 struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM]; 2725 int ret; 2726 u32 i; 2727 2728 for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) { 2729 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS, 2730 true); 2731 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1)) 2732 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2733 } 2734 2735 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM); 2736 if (ret) 2737 return ret; 2738 2739 hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM); 2740 2741 return 0; 2742 } 2743 2744 static void hclge_update_fec_stats(struct hclge_dev *hdev) 2745 { 2746 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2747 int ret; 2748 2749 if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || 2750 test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state)) 2751 return; 2752 2753 ret = hclge_update_fec_stats_hw(hdev); 2754 if (ret) 2755 dev_err(&hdev->pdev->dev, 2756 "failed to update fec stats, ret = %d\n", ret); 2757 2758 clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state); 2759 } 2760 2761 static void hclge_get_fec_stats_total(struct hclge_dev *hdev, 2762 struct ethtool_fec_stats *fec_stats) 2763 { 2764 fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks; 2765 fec_stats->uncorrectable_blocks.total = 2766 hdev->fec_stats.rs_uncorr_blocks; 2767 } 2768 2769 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev, 2770 struct ethtool_fec_stats *fec_stats) 2771 { 2772 u32 i; 2773 2774 if (hdev->fec_stats.base_r_lane_num == 0 || 2775 hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) { 2776 dev_err(&hdev->pdev->dev, 2777 "fec stats lane number(%llu) is invalid\n", 2778 hdev->fec_stats.base_r_lane_num); 2779 return; 2780 } 2781 2782 for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) { 2783 fec_stats->corrected_blocks.lanes[i] = 2784 hdev->fec_stats.base_r_corr_per_lanes[i]; 2785 fec_stats->uncorrectable_blocks.lanes[i] = 2786 hdev->fec_stats.base_r_uncorr_per_lanes[i]; 2787 } 2788 } 2789 2790 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev, 2791 struct ethtool_fec_stats *fec_stats) 2792 { 2793 u32 fec_mode = hdev->hw.mac.fec_mode; 2794 2795 switch (fec_mode) { 2796 case BIT(HNAE3_FEC_RS): 2797 case BIT(HNAE3_FEC_LLRS): 2798 hclge_get_fec_stats_total(hdev, fec_stats); 2799 break; 2800 case BIT(HNAE3_FEC_BASER): 2801 hclge_get_fec_stats_lanes(hdev, fec_stats); 2802 break; 2803 default: 2804 dev_err(&hdev->pdev->dev, 2805 "fec stats is not supported by current fec mode(0x%x)\n", 2806 fec_mode); 2807 break; 2808 } 2809 } 2810 2811 static void hclge_get_fec_stats(struct hnae3_handle *handle, 2812 struct ethtool_fec_stats *fec_stats) 2813 { 2814 struct hclge_vport *vport = hclge_get_vport(handle); 2815 struct hclge_dev *hdev = vport->back; 2816 u32 fec_mode = hdev->hw.mac.fec_mode; 2817 2818 if (fec_mode == BIT(HNAE3_FEC_NONE) || 2819 fec_mode == BIT(HNAE3_FEC_AUTO) || 2820 fec_mode == BIT(HNAE3_FEC_USER_DEF)) 2821 return; 2822 2823 hclge_update_fec_stats(hdev); 2824 2825 hclge_comm_get_fec_stats(hdev, fec_stats); 2826 } 2827 2828 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode) 2829 { 2830 struct hclge_config_fec_cmd *req; 2831 struct hclge_desc desc; 2832 int ret; 2833 2834 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false); 2835 2836 req = (struct hclge_config_fec_cmd *)desc.data; 2837 if (fec_mode & BIT(HNAE3_FEC_AUTO)) 2838 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1); 2839 if (fec_mode & BIT(HNAE3_FEC_RS)) 2840 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2841 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS); 2842 if (fec_mode & BIT(HNAE3_FEC_LLRS)) 2843 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2844 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS); 2845 if (fec_mode & BIT(HNAE3_FEC_BASER)) 2846 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2847 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER); 2848 2849 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2850 if (ret) 2851 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret); 2852 2853 return ret; 2854 } 2855 2856 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode) 2857 { 2858 struct hclge_vport *vport = hclge_get_vport(handle); 2859 struct hclge_dev *hdev = vport->back; 2860 struct hclge_mac *mac = &hdev->hw.mac; 2861 int ret; 2862 2863 if (fec_mode && !(mac->fec_ability & fec_mode)) { 2864 dev_err(&hdev->pdev->dev, "unsupported fec mode\n"); 2865 return -EINVAL; 2866 } 2867 2868 ret = hclge_set_fec_hw(hdev, fec_mode); 2869 if (ret) 2870 return ret; 2871 2872 mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF); 2873 return 0; 2874 } 2875 2876 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability, 2877 u8 *fec_mode) 2878 { 2879 struct hclge_vport *vport = hclge_get_vport(handle); 2880 struct hclge_dev *hdev = vport->back; 2881 struct hclge_mac *mac = &hdev->hw.mac; 2882 2883 if (fec_ability) 2884 *fec_ability = mac->fec_ability; 2885 if (fec_mode) 2886 *fec_mode = mac->fec_mode; 2887 } 2888 2889 static int hclge_mac_init(struct hclge_dev *hdev) 2890 { 2891 struct hclge_mac *mac = &hdev->hw.mac; 2892 int ret; 2893 2894 hdev->support_sfp_query = true; 2895 2896 if (!test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 2897 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 2898 2899 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed, 2900 hdev->hw.mac.duplex, hdev->hw.mac.lane_num); 2901 if (ret) 2902 return ret; 2903 2904 if (hdev->hw.mac.support_autoneg) { 2905 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg); 2906 if (ret) 2907 return ret; 2908 } 2909 2910 mac->link = 0; 2911 2912 if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { 2913 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode); 2914 if (ret) 2915 return ret; 2916 } 2917 2918 ret = hclge_set_mac_mtu(hdev, hdev->mps); 2919 if (ret) { 2920 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret); 2921 return ret; 2922 } 2923 2924 ret = hclge_set_default_loopback(hdev); 2925 if (ret) 2926 return ret; 2927 2928 ret = hclge_buffer_alloc(hdev); 2929 if (ret) 2930 dev_err(&hdev->pdev->dev, 2931 "allocate buffer fail, ret=%d\n", ret); 2932 2933 return ret; 2934 } 2935 2936 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 2937 { 2938 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2939 !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) { 2940 hdev->last_mbx_scheduled = jiffies; 2941 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2942 } 2943 } 2944 2945 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 2946 { 2947 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2948 test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) && 2949 !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) { 2950 hdev->last_rst_scheduled = jiffies; 2951 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2952 } 2953 } 2954 2955 static void hclge_errhand_task_schedule(struct hclge_dev *hdev) 2956 { 2957 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2958 !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 2959 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2960 } 2961 2962 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time) 2963 { 2964 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2965 !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 2966 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time); 2967 } 2968 2969 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status) 2970 { 2971 struct hclge_link_status_cmd *req; 2972 struct hclge_desc desc; 2973 int ret; 2974 2975 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 2976 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2977 if (ret) { 2978 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 2979 ret); 2980 return ret; 2981 } 2982 2983 req = (struct hclge_link_status_cmd *)desc.data; 2984 *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ? 2985 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 2986 2987 return 0; 2988 } 2989 2990 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status) 2991 { 2992 struct phy_device *phydev = hdev->hw.mac.phydev; 2993 2994 *link_status = HCLGE_LINK_STATUS_DOWN; 2995 2996 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) 2997 return 0; 2998 2999 if (phydev && (phydev->state != PHY_RUNNING || !phydev->link)) 3000 return 0; 3001 3002 return hclge_get_mac_link_status(hdev, link_status); 3003 } 3004 3005 static void hclge_push_link_status(struct hclge_dev *hdev) 3006 { 3007 struct hclge_vport *vport; 3008 int ret; 3009 u16 i; 3010 3011 for (i = 0; i < pci_num_vf(hdev->pdev); i++) { 3012 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 3013 3014 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) || 3015 vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO) 3016 continue; 3017 3018 ret = hclge_push_vf_link_status(vport); 3019 if (ret) { 3020 dev_err(&hdev->pdev->dev, 3021 "failed to push link status to vf%u, ret = %d\n", 3022 i, ret); 3023 } 3024 } 3025 } 3026 3027 static void hclge_update_link_status(struct hclge_dev *hdev) 3028 { 3029 struct hnae3_handle *rhandle = &hdev->vport[0].roce; 3030 struct hnae3_handle *handle = &hdev->vport[0].nic; 3031 struct hnae3_client *rclient = hdev->roce_client; 3032 struct hnae3_client *client = hdev->nic_client; 3033 int state; 3034 int ret; 3035 3036 if (!client) 3037 return; 3038 3039 if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state)) 3040 return; 3041 3042 ret = hclge_get_mac_phy_link(hdev, &state); 3043 if (ret) { 3044 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3045 return; 3046 } 3047 3048 if (state != hdev->hw.mac.link) { 3049 hdev->hw.mac.link = state; 3050 if (state == HCLGE_LINK_STATUS_UP) 3051 hclge_update_port_info(hdev); 3052 3053 client->ops->link_status_change(handle, state); 3054 hclge_config_mac_tnl_int(hdev, state); 3055 if (rclient && rclient->ops->link_status_change) 3056 rclient->ops->link_status_change(rhandle, state); 3057 3058 hclge_push_link_status(hdev); 3059 } 3060 3061 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3062 } 3063 3064 static void hclge_update_speed_advertising(struct hclge_mac *mac) 3065 { 3066 u32 speed_ability; 3067 3068 if (hclge_get_speed_bit(mac->speed, &speed_ability)) 3069 return; 3070 3071 switch (mac->module_type) { 3072 case HNAE3_MODULE_TYPE_FIBRE_LR: 3073 hclge_convert_setting_lr(speed_ability, mac->advertising); 3074 break; 3075 case HNAE3_MODULE_TYPE_FIBRE_SR: 3076 case HNAE3_MODULE_TYPE_AOC: 3077 hclge_convert_setting_sr(speed_ability, mac->advertising); 3078 break; 3079 case HNAE3_MODULE_TYPE_CR: 3080 hclge_convert_setting_cr(speed_ability, mac->advertising); 3081 break; 3082 case HNAE3_MODULE_TYPE_KR: 3083 hclge_convert_setting_kr(speed_ability, mac->advertising); 3084 break; 3085 default: 3086 break; 3087 } 3088 } 3089 3090 static void hclge_update_fec_advertising(struct hclge_mac *mac) 3091 { 3092 if (mac->fec_mode & BIT(HNAE3_FEC_RS)) 3093 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 3094 mac->advertising); 3095 else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS)) 3096 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 3097 mac->advertising); 3098 else if (mac->fec_mode & BIT(HNAE3_FEC_BASER)) 3099 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 3100 mac->advertising); 3101 else 3102 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 3103 mac->advertising); 3104 } 3105 3106 static void hclge_update_pause_advertising(struct hclge_dev *hdev) 3107 { 3108 struct hclge_mac *mac = &hdev->hw.mac; 3109 bool rx_en, tx_en; 3110 3111 switch (hdev->fc_mode_last_time) { 3112 case HCLGE_FC_RX_PAUSE: 3113 rx_en = true; 3114 tx_en = false; 3115 break; 3116 case HCLGE_FC_TX_PAUSE: 3117 rx_en = false; 3118 tx_en = true; 3119 break; 3120 case HCLGE_FC_FULL: 3121 rx_en = true; 3122 tx_en = true; 3123 break; 3124 default: 3125 rx_en = false; 3126 tx_en = false; 3127 break; 3128 } 3129 3130 linkmode_set_pause(mac->advertising, tx_en, rx_en); 3131 } 3132 3133 static void hclge_update_advertising(struct hclge_dev *hdev) 3134 { 3135 struct hclge_mac *mac = &hdev->hw.mac; 3136 3137 linkmode_zero(mac->advertising); 3138 hclge_update_speed_advertising(mac); 3139 hclge_update_fec_advertising(mac); 3140 hclge_update_pause_advertising(hdev); 3141 } 3142 3143 static void hclge_update_port_capability(struct hclge_dev *hdev, 3144 struct hclge_mac *mac) 3145 { 3146 if (hnae3_dev_fec_supported(hdev)) 3147 hclge_convert_setting_fec(mac); 3148 3149 /* firmware can not identify back plane type, the media type 3150 * read from configuration can help deal it 3151 */ 3152 if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE && 3153 mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN) 3154 mac->module_type = HNAE3_MODULE_TYPE_KR; 3155 else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3156 mac->module_type = HNAE3_MODULE_TYPE_TP; 3157 3158 if (mac->support_autoneg) { 3159 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported); 3160 linkmode_copy(mac->advertising, mac->supported); 3161 } else { 3162 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3163 mac->supported); 3164 hclge_update_advertising(hdev); 3165 } 3166 } 3167 3168 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed) 3169 { 3170 struct hclge_sfp_info_cmd *resp; 3171 struct hclge_desc desc; 3172 int ret; 3173 3174 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3175 resp = (struct hclge_sfp_info_cmd *)desc.data; 3176 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3177 if (ret == -EOPNOTSUPP) { 3178 dev_warn(&hdev->pdev->dev, 3179 "IMP do not support get SFP speed %d\n", ret); 3180 return ret; 3181 } else if (ret) { 3182 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret); 3183 return ret; 3184 } 3185 3186 *speed = le32_to_cpu(resp->speed); 3187 3188 return 0; 3189 } 3190 3191 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac) 3192 { 3193 struct hclge_sfp_info_cmd *resp; 3194 struct hclge_desc desc; 3195 int ret; 3196 3197 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3198 resp = (struct hclge_sfp_info_cmd *)desc.data; 3199 3200 resp->query_type = QUERY_ACTIVE_SPEED; 3201 3202 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3203 if (ret == -EOPNOTSUPP) { 3204 dev_warn(&hdev->pdev->dev, 3205 "IMP does not support get SFP info %d\n", ret); 3206 return ret; 3207 } else if (ret) { 3208 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret); 3209 return ret; 3210 } 3211 3212 /* In some case, mac speed get from IMP may be 0, it shouldn't be 3213 * set to mac->speed. 3214 */ 3215 if (!le32_to_cpu(resp->speed)) 3216 return 0; 3217 3218 mac->speed = le32_to_cpu(resp->speed); 3219 /* if resp->speed_ability is 0, it means it's an old version 3220 * firmware, do not update these params 3221 */ 3222 if (resp->speed_ability) { 3223 mac->module_type = le32_to_cpu(resp->module_type); 3224 mac->speed_ability = le32_to_cpu(resp->speed_ability); 3225 mac->autoneg = resp->autoneg; 3226 mac->support_autoneg = resp->autoneg_ability; 3227 mac->speed_type = QUERY_ACTIVE_SPEED; 3228 mac->lane_num = resp->lane_num; 3229 if (!resp->active_fec) 3230 mac->fec_mode = 0; 3231 else 3232 mac->fec_mode = BIT(resp->active_fec); 3233 mac->fec_ability = resp->fec_ability; 3234 } else { 3235 mac->speed_type = QUERY_SFP_SPEED; 3236 } 3237 3238 return 0; 3239 } 3240 3241 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle, 3242 struct ethtool_link_ksettings *cmd) 3243 { 3244 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3245 struct hclge_vport *vport = hclge_get_vport(handle); 3246 struct hclge_phy_link_ksetting_0_cmd *req0; 3247 struct hclge_phy_link_ksetting_1_cmd *req1; 3248 u32 supported, advertising, lp_advertising; 3249 struct hclge_dev *hdev = vport->back; 3250 int ret; 3251 3252 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3253 true); 3254 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3255 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3256 true); 3257 3258 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3259 if (ret) { 3260 dev_err(&hdev->pdev->dev, 3261 "failed to get phy link ksetting, ret = %d.\n", ret); 3262 return ret; 3263 } 3264 3265 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3266 cmd->base.autoneg = req0->autoneg; 3267 cmd->base.speed = le32_to_cpu(req0->speed); 3268 cmd->base.duplex = req0->duplex; 3269 cmd->base.port = req0->port; 3270 cmd->base.transceiver = req0->transceiver; 3271 cmd->base.phy_address = req0->phy_address; 3272 cmd->base.eth_tp_mdix = req0->eth_tp_mdix; 3273 cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl; 3274 supported = le32_to_cpu(req0->supported); 3275 advertising = le32_to_cpu(req0->advertising); 3276 lp_advertising = le32_to_cpu(req0->lp_advertising); 3277 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3278 supported); 3279 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3280 advertising); 3281 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 3282 lp_advertising); 3283 3284 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3285 cmd->base.master_slave_cfg = req1->master_slave_cfg; 3286 cmd->base.master_slave_state = req1->master_slave_state; 3287 3288 return 0; 3289 } 3290 3291 static int 3292 hclge_set_phy_link_ksettings(struct hnae3_handle *handle, 3293 const struct ethtool_link_ksettings *cmd) 3294 { 3295 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3296 struct hclge_vport *vport = hclge_get_vport(handle); 3297 struct hclge_phy_link_ksetting_0_cmd *req0; 3298 struct hclge_phy_link_ksetting_1_cmd *req1; 3299 struct hclge_dev *hdev = vport->back; 3300 u32 advertising; 3301 int ret; 3302 3303 if (cmd->base.autoneg == AUTONEG_DISABLE && 3304 ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) || 3305 (cmd->base.duplex != DUPLEX_HALF && 3306 cmd->base.duplex != DUPLEX_FULL))) 3307 return -EINVAL; 3308 3309 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3310 false); 3311 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3312 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3313 false); 3314 3315 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3316 req0->autoneg = cmd->base.autoneg; 3317 req0->speed = cpu_to_le32(cmd->base.speed); 3318 req0->duplex = cmd->base.duplex; 3319 ethtool_convert_link_mode_to_legacy_u32(&advertising, 3320 cmd->link_modes.advertising); 3321 req0->advertising = cpu_to_le32(advertising); 3322 req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; 3323 3324 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3325 req1->master_slave_cfg = cmd->base.master_slave_cfg; 3326 3327 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3328 if (ret) { 3329 dev_err(&hdev->pdev->dev, 3330 "failed to set phy link ksettings, ret = %d.\n", ret); 3331 return ret; 3332 } 3333 3334 hdev->hw.mac.autoneg = cmd->base.autoneg; 3335 hdev->hw.mac.speed = cmd->base.speed; 3336 hdev->hw.mac.duplex = cmd->base.duplex; 3337 linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising); 3338 3339 return 0; 3340 } 3341 3342 static int hclge_update_tp_port_info(struct hclge_dev *hdev) 3343 { 3344 struct ethtool_link_ksettings cmd; 3345 int ret; 3346 3347 if (!hnae3_dev_phy_imp_supported(hdev)) 3348 return 0; 3349 3350 ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd); 3351 if (ret) 3352 return ret; 3353 3354 hdev->hw.mac.autoneg = cmd.base.autoneg; 3355 hdev->hw.mac.speed = cmd.base.speed; 3356 hdev->hw.mac.duplex = cmd.base.duplex; 3357 linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising); 3358 3359 return 0; 3360 } 3361 3362 static int hclge_tp_port_init(struct hclge_dev *hdev) 3363 { 3364 struct ethtool_link_ksettings cmd; 3365 3366 if (!hnae3_dev_phy_imp_supported(hdev)) 3367 return 0; 3368 3369 cmd.base.autoneg = hdev->hw.mac.autoneg; 3370 cmd.base.speed = hdev->hw.mac.speed; 3371 cmd.base.duplex = hdev->hw.mac.duplex; 3372 linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising); 3373 3374 return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd); 3375 } 3376 3377 static int hclge_update_port_info(struct hclge_dev *hdev) 3378 { 3379 struct hclge_mac *mac = &hdev->hw.mac; 3380 int speed; 3381 int ret; 3382 3383 /* get the port info from SFP cmd if not copper port */ 3384 if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3385 return hclge_update_tp_port_info(hdev); 3386 3387 /* if IMP does not support get SFP/qSFP info, return directly */ 3388 if (!hdev->support_sfp_query) 3389 return 0; 3390 3391 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3392 speed = mac->speed; 3393 ret = hclge_get_sfp_info(hdev, mac); 3394 } else { 3395 speed = HCLGE_MAC_SPEED_UNKNOWN; 3396 ret = hclge_get_sfp_speed(hdev, &speed); 3397 } 3398 3399 if (ret == -EOPNOTSUPP) { 3400 hdev->support_sfp_query = false; 3401 return ret; 3402 } else if (ret) { 3403 return ret; 3404 } 3405 3406 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3407 if (mac->speed_type == QUERY_ACTIVE_SPEED) { 3408 hclge_update_port_capability(hdev, mac); 3409 if (mac->speed != speed) 3410 (void)hclge_tm_port_shaper_cfg(hdev); 3411 return 0; 3412 } 3413 return hclge_cfg_mac_speed_dup(hdev, mac->speed, 3414 HCLGE_MAC_FULL, mac->lane_num); 3415 } else { 3416 if (speed == HCLGE_MAC_SPEED_UNKNOWN) 3417 return 0; /* do nothing if no SFP */ 3418 3419 /* must config full duplex for SFP */ 3420 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0); 3421 } 3422 } 3423 3424 static int hclge_get_status(struct hnae3_handle *handle) 3425 { 3426 struct hclge_vport *vport = hclge_get_vport(handle); 3427 struct hclge_dev *hdev = vport->back; 3428 3429 hclge_update_link_status(hdev); 3430 3431 return hdev->hw.mac.link; 3432 } 3433 3434 static struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf) 3435 { 3436 if (!pci_num_vf(hdev->pdev)) { 3437 dev_err(&hdev->pdev->dev, 3438 "SRIOV is disabled, can not get vport(%d) info.\n", vf); 3439 return NULL; 3440 } 3441 3442 if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) { 3443 dev_err(&hdev->pdev->dev, 3444 "vf id(%d) is out of range(0 <= vfid < %d)\n", 3445 vf, pci_num_vf(hdev->pdev)); 3446 return NULL; 3447 } 3448 3449 /* VF start from 1 in vport */ 3450 vf += HCLGE_VF_VPORT_START_NUM; 3451 return &hdev->vport[vf]; 3452 } 3453 3454 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf, 3455 struct ifla_vf_info *ivf) 3456 { 3457 struct hclge_vport *vport = hclge_get_vport(handle); 3458 struct hclge_dev *hdev = vport->back; 3459 3460 vport = hclge_get_vf_vport(hdev, vf); 3461 if (!vport) 3462 return -EINVAL; 3463 3464 ivf->vf = vf; 3465 ivf->linkstate = vport->vf_info.link_state; 3466 ivf->spoofchk = vport->vf_info.spoofchk; 3467 ivf->trusted = vport->vf_info.trusted; 3468 ivf->min_tx_rate = 0; 3469 ivf->max_tx_rate = vport->vf_info.max_tx_rate; 3470 ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag; 3471 ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto); 3472 ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos; 3473 ether_addr_copy(ivf->mac, vport->vf_info.mac); 3474 3475 return 0; 3476 } 3477 3478 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, 3479 int link_state) 3480 { 3481 struct hclge_vport *vport = hclge_get_vport(handle); 3482 struct hclge_dev *hdev = vport->back; 3483 int link_state_old; 3484 int ret; 3485 3486 vport = hclge_get_vf_vport(hdev, vf); 3487 if (!vport) 3488 return -EINVAL; 3489 3490 link_state_old = vport->vf_info.link_state; 3491 vport->vf_info.link_state = link_state; 3492 3493 /* return success directly if the VF is unalive, VF will 3494 * query link state itself when it starts work. 3495 */ 3496 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3497 return 0; 3498 3499 ret = hclge_push_vf_link_status(vport); 3500 if (ret) { 3501 vport->vf_info.link_state = link_state_old; 3502 dev_err(&hdev->pdev->dev, 3503 "failed to push vf%d link status, ret = %d\n", vf, ret); 3504 } 3505 3506 return ret; 3507 } 3508 3509 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 3510 { 3511 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; 3512 3513 /* fetch the events from their corresponding regs */ 3514 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 3515 msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 3516 hw_err_src_reg = hclge_read_dev(&hdev->hw, 3517 HCLGE_RAS_PF_OTHER_INT_STS_REG); 3518 3519 /* Assumption: If by any chance reset and mailbox events are reported 3520 * together then we will only process reset event in this go and will 3521 * defer the processing of the mailbox events. Since, we would have not 3522 * cleared RX CMDQ event this time we would receive again another 3523 * interrupt from H/W just for the mailbox. 3524 * 3525 * check for vector0 reset event sources 3526 */ 3527 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { 3528 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); 3529 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); 3530 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3531 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3532 hdev->rst_stats.imp_rst_cnt++; 3533 return HCLGE_VECTOR0_EVENT_RST; 3534 } 3535 3536 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { 3537 dev_info(&hdev->pdev->dev, "global reset interrupt\n"); 3538 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3539 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 3540 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3541 hdev->rst_stats.global_rst_cnt++; 3542 return HCLGE_VECTOR0_EVENT_RST; 3543 } 3544 3545 /* check for vector0 msix event and hardware error event source */ 3546 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK || 3547 hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK) 3548 return HCLGE_VECTOR0_EVENT_ERR; 3549 3550 /* check for vector0 ptp event source */ 3551 if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) { 3552 *clearval = msix_src_reg; 3553 return HCLGE_VECTOR0_EVENT_PTP; 3554 } 3555 3556 /* check for vector0 mailbox(=CMDQ RX) event source */ 3557 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 3558 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 3559 *clearval = cmdq_src_reg; 3560 return HCLGE_VECTOR0_EVENT_MBX; 3561 } 3562 3563 /* print other vector0 event source */ 3564 dev_info(&hdev->pdev->dev, 3565 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n", 3566 cmdq_src_reg, hw_err_src_reg, msix_src_reg); 3567 3568 return HCLGE_VECTOR0_EVENT_OTHER; 3569 } 3570 3571 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 3572 u32 regclr) 3573 { 3574 #define HCLGE_IMP_RESET_DELAY 5 3575 3576 switch (event_type) { 3577 case HCLGE_VECTOR0_EVENT_PTP: 3578 case HCLGE_VECTOR0_EVENT_RST: 3579 if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B)) 3580 mdelay(HCLGE_IMP_RESET_DELAY); 3581 3582 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 3583 break; 3584 case HCLGE_VECTOR0_EVENT_MBX: 3585 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 3586 break; 3587 default: 3588 break; 3589 } 3590 } 3591 3592 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 3593 { 3594 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 3595 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 3596 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 3597 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 3598 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 3599 } 3600 3601 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 3602 { 3603 writel(enable ? 1 : 0, vector->addr); 3604 } 3605 3606 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 3607 { 3608 struct hclge_dev *hdev = data; 3609 unsigned long flags; 3610 u32 clearval = 0; 3611 u32 event_cause; 3612 3613 hclge_enable_vector(&hdev->misc_vector, false); 3614 event_cause = hclge_check_event_cause(hdev, &clearval); 3615 3616 /* vector 0 interrupt is shared with reset and mailbox source events. */ 3617 switch (event_cause) { 3618 case HCLGE_VECTOR0_EVENT_ERR: 3619 hclge_errhand_task_schedule(hdev); 3620 break; 3621 case HCLGE_VECTOR0_EVENT_RST: 3622 hclge_reset_task_schedule(hdev); 3623 break; 3624 case HCLGE_VECTOR0_EVENT_PTP: 3625 spin_lock_irqsave(&hdev->ptp->lock, flags); 3626 hclge_ptp_clean_tx_hwts(hdev); 3627 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 3628 break; 3629 case HCLGE_VECTOR0_EVENT_MBX: 3630 /* If we are here then, 3631 * 1. Either we are not handling any mbx task and we are not 3632 * scheduled as well 3633 * OR 3634 * 2. We could be handling a mbx task but nothing more is 3635 * scheduled. 3636 * In both cases, we should schedule mbx task as there are more 3637 * mbx messages reported by this interrupt. 3638 */ 3639 hclge_mbx_task_schedule(hdev); 3640 break; 3641 default: 3642 dev_warn(&hdev->pdev->dev, 3643 "received unknown or unhandled event of vector0\n"); 3644 break; 3645 } 3646 3647 hclge_clear_event_cause(hdev, event_cause, clearval); 3648 3649 /* Enable interrupt if it is not caused by reset event or error event */ 3650 if (event_cause == HCLGE_VECTOR0_EVENT_PTP || 3651 event_cause == HCLGE_VECTOR0_EVENT_MBX || 3652 event_cause == HCLGE_VECTOR0_EVENT_OTHER) 3653 hclge_enable_vector(&hdev->misc_vector, true); 3654 3655 return IRQ_HANDLED; 3656 } 3657 3658 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 3659 { 3660 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 3661 dev_warn(&hdev->pdev->dev, 3662 "vector(vector_id %d) has been freed.\n", vector_id); 3663 return; 3664 } 3665 3666 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 3667 hdev->num_msi_left += 1; 3668 hdev->num_msi_used -= 1; 3669 } 3670 3671 static void hclge_get_misc_vector(struct hclge_dev *hdev) 3672 { 3673 struct hclge_misc_vector *vector = &hdev->misc_vector; 3674 3675 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 3676 3677 vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 3678 hdev->vector_status[0] = 0; 3679 3680 hdev->num_msi_left -= 1; 3681 hdev->num_msi_used += 1; 3682 } 3683 3684 static int hclge_misc_irq_init(struct hclge_dev *hdev) 3685 { 3686 int ret; 3687 3688 hclge_get_misc_vector(hdev); 3689 3690 /* this would be explicitly freed in the end */ 3691 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 3692 HCLGE_NAME, pci_name(hdev->pdev)); 3693 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 3694 0, hdev->misc_vector.name, hdev); 3695 if (ret) { 3696 hclge_free_vector(hdev, 0); 3697 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 3698 hdev->misc_vector.vector_irq); 3699 } 3700 3701 return ret; 3702 } 3703 3704 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 3705 { 3706 free_irq(hdev->misc_vector.vector_irq, hdev); 3707 hclge_free_vector(hdev, 0); 3708 } 3709 3710 int hclge_notify_client(struct hclge_dev *hdev, 3711 enum hnae3_reset_notify_type type) 3712 { 3713 struct hnae3_handle *handle = &hdev->vport[0].nic; 3714 struct hnae3_client *client = hdev->nic_client; 3715 int ret; 3716 3717 if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client) 3718 return 0; 3719 3720 if (!client->ops->reset_notify) 3721 return -EOPNOTSUPP; 3722 3723 ret = client->ops->reset_notify(handle, type); 3724 if (ret) 3725 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 3726 type, ret); 3727 3728 return ret; 3729 } 3730 3731 static int hclge_notify_roce_client(struct hclge_dev *hdev, 3732 enum hnae3_reset_notify_type type) 3733 { 3734 struct hnae3_handle *handle = &hdev->vport[0].roce; 3735 struct hnae3_client *client = hdev->roce_client; 3736 int ret; 3737 3738 if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client) 3739 return 0; 3740 3741 if (!client->ops->reset_notify) 3742 return -EOPNOTSUPP; 3743 3744 ret = client->ops->reset_notify(handle, type); 3745 if (ret) 3746 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 3747 type, ret); 3748 3749 return ret; 3750 } 3751 3752 static int hclge_reset_wait(struct hclge_dev *hdev) 3753 { 3754 #define HCLGE_RESET_WATI_MS 100 3755 #define HCLGE_RESET_WAIT_CNT 350 3756 3757 u32 val, reg, reg_bit; 3758 u32 cnt = 0; 3759 3760 switch (hdev->reset_type) { 3761 case HNAE3_IMP_RESET: 3762 reg = HCLGE_GLOBAL_RESET_REG; 3763 reg_bit = HCLGE_IMP_RESET_BIT; 3764 break; 3765 case HNAE3_GLOBAL_RESET: 3766 reg = HCLGE_GLOBAL_RESET_REG; 3767 reg_bit = HCLGE_GLOBAL_RESET_BIT; 3768 break; 3769 case HNAE3_FUNC_RESET: 3770 reg = HCLGE_FUN_RST_ING; 3771 reg_bit = HCLGE_FUN_RST_ING_B; 3772 break; 3773 default: 3774 dev_err(&hdev->pdev->dev, 3775 "Wait for unsupported reset type: %d\n", 3776 hdev->reset_type); 3777 return -EINVAL; 3778 } 3779 3780 val = hclge_read_dev(&hdev->hw, reg); 3781 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 3782 msleep(HCLGE_RESET_WATI_MS); 3783 val = hclge_read_dev(&hdev->hw, reg); 3784 cnt++; 3785 } 3786 3787 if (cnt >= HCLGE_RESET_WAIT_CNT) { 3788 dev_warn(&hdev->pdev->dev, 3789 "Wait for reset timeout: %d\n", hdev->reset_type); 3790 return -EBUSY; 3791 } 3792 3793 return 0; 3794 } 3795 3796 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset) 3797 { 3798 struct hclge_vf_rst_cmd *req; 3799 struct hclge_desc desc; 3800 3801 req = (struct hclge_vf_rst_cmd *)desc.data; 3802 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false); 3803 req->dest_vfid = func_id; 3804 3805 if (reset) 3806 req->vf_rst = 0x1; 3807 3808 return hclge_cmd_send(&hdev->hw, &desc, 1); 3809 } 3810 3811 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset) 3812 { 3813 int i; 3814 3815 for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) { 3816 struct hclge_vport *vport = &hdev->vport[i]; 3817 int ret; 3818 3819 /* Send cmd to set/clear VF's FUNC_RST_ING */ 3820 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset); 3821 if (ret) { 3822 dev_err(&hdev->pdev->dev, 3823 "set vf(%u) rst failed %d!\n", 3824 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3825 ret); 3826 return ret; 3827 } 3828 3829 if (!reset || 3830 !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state)) 3831 continue; 3832 3833 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) && 3834 hdev->reset_type == HNAE3_FUNC_RESET) { 3835 set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET, 3836 &vport->need_notify); 3837 continue; 3838 } 3839 3840 /* Inform VF to process the reset. 3841 * hclge_inform_reset_assert_to_vf may fail if VF 3842 * driver is not loaded. 3843 */ 3844 ret = hclge_inform_reset_assert_to_vf(vport); 3845 if (ret) 3846 dev_warn(&hdev->pdev->dev, 3847 "inform reset to vf(%u) failed %d!\n", 3848 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3849 ret); 3850 } 3851 3852 return 0; 3853 } 3854 3855 static void hclge_mailbox_service_task(struct hclge_dev *hdev) 3856 { 3857 if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) || 3858 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) || 3859 test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 3860 return; 3861 3862 if (time_is_before_jiffies(hdev->last_mbx_scheduled + 3863 HCLGE_MBX_SCHED_TIMEOUT)) 3864 dev_warn(&hdev->pdev->dev, 3865 "mbx service task is scheduled after %ums on cpu%u!\n", 3866 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled), 3867 smp_processor_id()); 3868 3869 hclge_mbx_handler(hdev); 3870 3871 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 3872 } 3873 3874 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev) 3875 { 3876 struct hclge_pf_rst_sync_cmd *req; 3877 struct hclge_desc desc; 3878 int cnt = 0; 3879 int ret; 3880 3881 req = (struct hclge_pf_rst_sync_cmd *)desc.data; 3882 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true); 3883 3884 do { 3885 /* vf need to down netdev by mbx during PF or FLR reset */ 3886 hclge_mailbox_service_task(hdev); 3887 3888 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3889 /* for compatible with old firmware, wait 3890 * 100 ms for VF to stop IO 3891 */ 3892 if (ret == -EOPNOTSUPP) { 3893 msleep(HCLGE_RESET_SYNC_TIME); 3894 return; 3895 } else if (ret) { 3896 dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n", 3897 ret); 3898 return; 3899 } else if (req->all_vf_ready) { 3900 return; 3901 } 3902 msleep(HCLGE_PF_RESET_SYNC_TIME); 3903 hclge_comm_cmd_reuse_desc(&desc, true); 3904 } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT); 3905 3906 dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n"); 3907 } 3908 3909 void hclge_report_hw_error(struct hclge_dev *hdev, 3910 enum hnae3_hw_error_type type) 3911 { 3912 struct hnae3_client *client = hdev->nic_client; 3913 3914 if (!client || !client->ops->process_hw_error || 3915 !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) 3916 return; 3917 3918 client->ops->process_hw_error(&hdev->vport[0].nic, type); 3919 } 3920 3921 static void hclge_handle_imp_error(struct hclge_dev *hdev) 3922 { 3923 u32 reg_val; 3924 3925 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 3926 if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { 3927 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); 3928 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); 3929 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 3930 } 3931 3932 if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { 3933 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); 3934 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); 3935 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 3936 } 3937 } 3938 3939 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 3940 { 3941 struct hclge_desc desc; 3942 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 3943 int ret; 3944 3945 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 3946 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 3947 req->fun_reset_vfid = func_id; 3948 3949 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3950 if (ret) 3951 dev_err(&hdev->pdev->dev, 3952 "send function reset cmd fail, status =%d\n", ret); 3953 3954 return ret; 3955 } 3956 3957 static void hclge_do_reset(struct hclge_dev *hdev) 3958 { 3959 struct hnae3_handle *handle = &hdev->vport[0].nic; 3960 struct pci_dev *pdev = hdev->pdev; 3961 u32 val; 3962 3963 if (hclge_get_hw_reset_stat(handle)) { 3964 dev_info(&pdev->dev, "hardware reset not finish\n"); 3965 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n", 3966 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING), 3967 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 3968 return; 3969 } 3970 3971 switch (hdev->reset_type) { 3972 case HNAE3_IMP_RESET: 3973 dev_info(&pdev->dev, "IMP reset requested\n"); 3974 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 3975 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1); 3976 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val); 3977 break; 3978 case HNAE3_GLOBAL_RESET: 3979 dev_info(&pdev->dev, "global reset requested\n"); 3980 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 3981 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 3982 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 3983 break; 3984 case HNAE3_FUNC_RESET: 3985 dev_info(&pdev->dev, "PF reset requested\n"); 3986 /* schedule again to check later */ 3987 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); 3988 hclge_reset_task_schedule(hdev); 3989 break; 3990 default: 3991 dev_warn(&pdev->dev, 3992 "unsupported reset type: %d\n", hdev->reset_type); 3993 break; 3994 } 3995 } 3996 3997 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 3998 unsigned long *addr) 3999 { 4000 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 4001 struct hclge_dev *hdev = ae_dev->priv; 4002 4003 /* return the highest priority reset level amongst all */ 4004 if (test_bit(HNAE3_IMP_RESET, addr)) { 4005 rst_level = HNAE3_IMP_RESET; 4006 clear_bit(HNAE3_IMP_RESET, addr); 4007 clear_bit(HNAE3_GLOBAL_RESET, addr); 4008 clear_bit(HNAE3_FUNC_RESET, addr); 4009 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) { 4010 rst_level = HNAE3_GLOBAL_RESET; 4011 clear_bit(HNAE3_GLOBAL_RESET, addr); 4012 clear_bit(HNAE3_FUNC_RESET, addr); 4013 } else if (test_bit(HNAE3_FUNC_RESET, addr)) { 4014 rst_level = HNAE3_FUNC_RESET; 4015 clear_bit(HNAE3_FUNC_RESET, addr); 4016 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 4017 rst_level = HNAE3_FLR_RESET; 4018 clear_bit(HNAE3_FLR_RESET, addr); 4019 } 4020 4021 if (hdev->reset_type != HNAE3_NONE_RESET && 4022 rst_level < hdev->reset_type) 4023 return HNAE3_NONE_RESET; 4024 4025 return rst_level; 4026 } 4027 4028 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 4029 { 4030 u32 clearval = 0; 4031 4032 switch (hdev->reset_type) { 4033 case HNAE3_IMP_RESET: 4034 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 4035 break; 4036 case HNAE3_GLOBAL_RESET: 4037 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 4038 break; 4039 default: 4040 break; 4041 } 4042 4043 if (!clearval) 4044 return; 4045 4046 /* For revision 0x20, the reset interrupt source 4047 * can only be cleared after hardware reset done 4048 */ 4049 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 4050 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, 4051 clearval); 4052 4053 hclge_enable_vector(&hdev->misc_vector, true); 4054 } 4055 4056 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable) 4057 { 4058 u32 reg_val; 4059 4060 reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 4061 if (enable) 4062 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY; 4063 else 4064 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY; 4065 4066 hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val); 4067 } 4068 4069 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev) 4070 { 4071 int ret; 4072 4073 ret = hclge_set_all_vf_rst(hdev, true); 4074 if (ret) 4075 return ret; 4076 4077 hclge_func_reset_sync_vf(hdev); 4078 4079 return 0; 4080 } 4081 4082 static int hclge_reset_prepare_wait(struct hclge_dev *hdev) 4083 { 4084 u32 reg_val; 4085 int ret = 0; 4086 4087 switch (hdev->reset_type) { 4088 case HNAE3_FUNC_RESET: 4089 ret = hclge_func_reset_notify_vf(hdev); 4090 if (ret) 4091 return ret; 4092 4093 ret = hclge_func_reset_cmd(hdev, 0); 4094 if (ret) { 4095 dev_err(&hdev->pdev->dev, 4096 "asserting function reset fail %d!\n", ret); 4097 return ret; 4098 } 4099 4100 /* After performaning pf reset, it is not necessary to do the 4101 * mailbox handling or send any command to firmware, because 4102 * any mailbox handling or command to firmware is only valid 4103 * after hclge_comm_cmd_init is called. 4104 */ 4105 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 4106 hdev->rst_stats.pf_rst_cnt++; 4107 break; 4108 case HNAE3_FLR_RESET: 4109 ret = hclge_func_reset_notify_vf(hdev); 4110 if (ret) 4111 return ret; 4112 break; 4113 case HNAE3_IMP_RESET: 4114 hclge_handle_imp_error(hdev); 4115 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4116 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, 4117 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); 4118 break; 4119 default: 4120 break; 4121 } 4122 4123 /* inform hardware that preparatory work is done */ 4124 msleep(HCLGE_RESET_SYNC_TIME); 4125 hclge_reset_handshake(hdev, true); 4126 dev_info(&hdev->pdev->dev, "prepare wait ok\n"); 4127 4128 return ret; 4129 } 4130 4131 static void hclge_show_rst_info(struct hclge_dev *hdev) 4132 { 4133 char *buf; 4134 4135 buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL); 4136 if (!buf) 4137 return; 4138 4139 hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN); 4140 4141 dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf); 4142 4143 kfree(buf); 4144 } 4145 4146 static bool hclge_reset_err_handle(struct hclge_dev *hdev) 4147 { 4148 #define MAX_RESET_FAIL_CNT 5 4149 4150 if (hdev->reset_pending) { 4151 dev_info(&hdev->pdev->dev, "Reset pending %lu\n", 4152 hdev->reset_pending); 4153 return true; 4154 } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) & 4155 HCLGE_RESET_INT_M) { 4156 dev_info(&hdev->pdev->dev, 4157 "reset failed because new reset interrupt\n"); 4158 hclge_clear_reset_cause(hdev); 4159 return false; 4160 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { 4161 hdev->rst_stats.reset_fail_cnt++; 4162 set_bit(hdev->reset_type, &hdev->reset_pending); 4163 dev_info(&hdev->pdev->dev, 4164 "re-schedule reset task(%u)\n", 4165 hdev->rst_stats.reset_fail_cnt); 4166 return true; 4167 } 4168 4169 hclge_clear_reset_cause(hdev); 4170 4171 /* recover the handshake status when reset fail */ 4172 hclge_reset_handshake(hdev, true); 4173 4174 dev_err(&hdev->pdev->dev, "Reset fail!\n"); 4175 4176 hclge_show_rst_info(hdev); 4177 4178 set_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4179 4180 return false; 4181 } 4182 4183 static void hclge_update_reset_level(struct hclge_dev *hdev) 4184 { 4185 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4186 enum hnae3_reset_type reset_level; 4187 4188 /* reset request will not be set during reset, so clear 4189 * pending reset request to avoid unnecessary reset 4190 * caused by the same reason. 4191 */ 4192 hclge_get_reset_level(ae_dev, &hdev->reset_request); 4193 4194 /* if default_reset_request has a higher level reset request, 4195 * it should be handled as soon as possible. since some errors 4196 * need this kind of reset to fix. 4197 */ 4198 reset_level = hclge_get_reset_level(ae_dev, 4199 &hdev->default_reset_request); 4200 if (reset_level != HNAE3_NONE_RESET) 4201 set_bit(reset_level, &hdev->reset_request); 4202 } 4203 4204 static int hclge_set_rst_done(struct hclge_dev *hdev) 4205 { 4206 struct hclge_pf_rst_done_cmd *req; 4207 struct hclge_desc desc; 4208 int ret; 4209 4210 req = (struct hclge_pf_rst_done_cmd *)desc.data; 4211 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false); 4212 req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT; 4213 4214 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4215 /* To be compatible with the old firmware, which does not support 4216 * command HCLGE_OPC_PF_RST_DONE, just print a warning and 4217 * return success 4218 */ 4219 if (ret == -EOPNOTSUPP) { 4220 dev_warn(&hdev->pdev->dev, 4221 "current firmware does not support command(0x%x)!\n", 4222 HCLGE_OPC_PF_RST_DONE); 4223 return 0; 4224 } else if (ret) { 4225 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n", 4226 ret); 4227 } 4228 4229 return ret; 4230 } 4231 4232 static int hclge_reset_prepare_up(struct hclge_dev *hdev) 4233 { 4234 int ret = 0; 4235 4236 switch (hdev->reset_type) { 4237 case HNAE3_FUNC_RESET: 4238 case HNAE3_FLR_RESET: 4239 ret = hclge_set_all_vf_rst(hdev, false); 4240 break; 4241 case HNAE3_GLOBAL_RESET: 4242 case HNAE3_IMP_RESET: 4243 ret = hclge_set_rst_done(hdev); 4244 break; 4245 default: 4246 break; 4247 } 4248 4249 /* clear up the handshake status after re-initialize done */ 4250 hclge_reset_handshake(hdev, false); 4251 4252 return ret; 4253 } 4254 4255 static int hclge_reset_stack(struct hclge_dev *hdev) 4256 { 4257 int ret; 4258 4259 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 4260 if (ret) 4261 return ret; 4262 4263 ret = hclge_reset_ae_dev(hdev->ae_dev); 4264 if (ret) 4265 return ret; 4266 4267 return hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 4268 } 4269 4270 static int hclge_reset_prepare(struct hclge_dev *hdev) 4271 { 4272 int ret; 4273 4274 hdev->rst_stats.reset_cnt++; 4275 /* perform reset of the stack & ae device for a client */ 4276 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 4277 if (ret) 4278 return ret; 4279 4280 rtnl_lock(); 4281 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 4282 rtnl_unlock(); 4283 if (ret) 4284 return ret; 4285 4286 return hclge_reset_prepare_wait(hdev); 4287 } 4288 4289 static int hclge_reset_rebuild(struct hclge_dev *hdev) 4290 { 4291 int ret; 4292 4293 hdev->rst_stats.hw_reset_done_cnt++; 4294 4295 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 4296 if (ret) 4297 return ret; 4298 4299 rtnl_lock(); 4300 ret = hclge_reset_stack(hdev); 4301 rtnl_unlock(); 4302 if (ret) 4303 return ret; 4304 4305 hclge_clear_reset_cause(hdev); 4306 4307 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 4308 /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1 4309 * times 4310 */ 4311 if (ret && 4312 hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1) 4313 return ret; 4314 4315 ret = hclge_reset_prepare_up(hdev); 4316 if (ret) 4317 return ret; 4318 4319 rtnl_lock(); 4320 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT); 4321 rtnl_unlock(); 4322 if (ret) 4323 return ret; 4324 4325 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT); 4326 if (ret) 4327 return ret; 4328 4329 hdev->last_reset_time = jiffies; 4330 hdev->rst_stats.reset_fail_cnt = 0; 4331 hdev->rst_stats.reset_done_cnt++; 4332 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4333 4334 hclge_update_reset_level(hdev); 4335 4336 return 0; 4337 } 4338 4339 static void hclge_reset(struct hclge_dev *hdev) 4340 { 4341 if (hclge_reset_prepare(hdev)) 4342 goto err_reset; 4343 4344 if (hclge_reset_wait(hdev)) 4345 goto err_reset; 4346 4347 if (hclge_reset_rebuild(hdev)) 4348 goto err_reset; 4349 4350 return; 4351 4352 err_reset: 4353 if (hclge_reset_err_handle(hdev)) 4354 hclge_reset_task_schedule(hdev); 4355 } 4356 4357 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) 4358 { 4359 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4360 struct hclge_dev *hdev = ae_dev->priv; 4361 4362 /* We might end up getting called broadly because of 2 below cases: 4363 * 1. Recoverable error was conveyed through APEI and only way to bring 4364 * normalcy is to reset. 4365 * 2. A new reset request from the stack due to timeout 4366 * 4367 * check if this is a new reset request and we are not here just because 4368 * last reset attempt did not succeed and watchdog hit us again. We will 4369 * know this if last reset request did not occur very recently (watchdog 4370 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 4371 * In case of new request we reset the "reset level" to PF reset. 4372 * And if it is a repeat reset request of the most recent one then we 4373 * want to make sure we throttle the reset request. Therefore, we will 4374 * not allow it again before 3*HZ times. 4375 */ 4376 4377 if (time_before(jiffies, (hdev->last_reset_time + 4378 HCLGE_RESET_INTERVAL))) { 4379 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 4380 return; 4381 } 4382 4383 if (hdev->default_reset_request) { 4384 hdev->reset_level = 4385 hclge_get_reset_level(ae_dev, 4386 &hdev->default_reset_request); 4387 } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) { 4388 hdev->reset_level = HNAE3_FUNC_RESET; 4389 } 4390 4391 dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n", 4392 hdev->reset_level); 4393 4394 /* request reset & schedule reset task */ 4395 set_bit(hdev->reset_level, &hdev->reset_request); 4396 hclge_reset_task_schedule(hdev); 4397 4398 if (hdev->reset_level < HNAE3_GLOBAL_RESET) 4399 hdev->reset_level++; 4400 } 4401 4402 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 4403 enum hnae3_reset_type rst_type) 4404 { 4405 struct hclge_dev *hdev = ae_dev->priv; 4406 4407 set_bit(rst_type, &hdev->default_reset_request); 4408 } 4409 4410 static void hclge_reset_timer(struct timer_list *t) 4411 { 4412 struct hclge_dev *hdev = from_timer(hdev, t, reset_timer); 4413 4414 /* if default_reset_request has no value, it means that this reset 4415 * request has already be handled, so just return here 4416 */ 4417 if (!hdev->default_reset_request) 4418 return; 4419 4420 dev_info(&hdev->pdev->dev, 4421 "triggering reset in reset timer\n"); 4422 hclge_reset_event(hdev->pdev, NULL); 4423 } 4424 4425 static void hclge_reset_subtask(struct hclge_dev *hdev) 4426 { 4427 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4428 4429 /* check if there is any ongoing reset in the hardware. This status can 4430 * be checked from reset_pending. If there is then, we need to wait for 4431 * hardware to complete reset. 4432 * a. If we are able to figure out in reasonable time that hardware 4433 * has fully resetted then, we can proceed with driver, client 4434 * reset. 4435 * b. else, we can come back later to check this status so re-sched 4436 * now. 4437 */ 4438 hdev->last_reset_time = jiffies; 4439 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending); 4440 if (hdev->reset_type != HNAE3_NONE_RESET) 4441 hclge_reset(hdev); 4442 4443 /* check if we got any *new* reset requests to be honored */ 4444 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request); 4445 if (hdev->reset_type != HNAE3_NONE_RESET) 4446 hclge_do_reset(hdev); 4447 4448 hdev->reset_type = HNAE3_NONE_RESET; 4449 } 4450 4451 static void hclge_handle_err_reset_request(struct hclge_dev *hdev) 4452 { 4453 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4454 enum hnae3_reset_type reset_type; 4455 4456 if (ae_dev->hw_err_reset_req) { 4457 reset_type = hclge_get_reset_level(ae_dev, 4458 &ae_dev->hw_err_reset_req); 4459 hclge_set_def_reset_request(ae_dev, reset_type); 4460 } 4461 4462 if (hdev->default_reset_request && ae_dev->ops->reset_event) 4463 ae_dev->ops->reset_event(hdev->pdev, NULL); 4464 4465 /* enable interrupt after error handling complete */ 4466 hclge_enable_vector(&hdev->misc_vector, true); 4467 } 4468 4469 static void hclge_handle_err_recovery(struct hclge_dev *hdev) 4470 { 4471 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4472 4473 ae_dev->hw_err_reset_req = 0; 4474 4475 if (hclge_find_error_source(hdev)) { 4476 hclge_handle_error_info_log(ae_dev); 4477 hclge_handle_mac_tnl(hdev); 4478 } 4479 4480 hclge_handle_err_reset_request(hdev); 4481 } 4482 4483 static void hclge_misc_err_recovery(struct hclge_dev *hdev) 4484 { 4485 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4486 struct device *dev = &hdev->pdev->dev; 4487 u32 msix_sts_reg; 4488 4489 msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 4490 if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) { 4491 if (hclge_handle_hw_msix_error 4492 (hdev, &hdev->default_reset_request)) 4493 dev_info(dev, "received msix interrupt 0x%x\n", 4494 msix_sts_reg); 4495 } 4496 4497 hclge_handle_hw_ras_error(ae_dev); 4498 4499 hclge_handle_err_reset_request(hdev); 4500 } 4501 4502 static void hclge_errhand_service_task(struct hclge_dev *hdev) 4503 { 4504 if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 4505 return; 4506 4507 if (hnae3_dev_ras_imp_supported(hdev)) 4508 hclge_handle_err_recovery(hdev); 4509 else 4510 hclge_misc_err_recovery(hdev); 4511 } 4512 4513 static void hclge_reset_service_task(struct hclge_dev *hdev) 4514 { 4515 if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 4516 return; 4517 4518 if (time_is_before_jiffies(hdev->last_rst_scheduled + 4519 HCLGE_RESET_SCHED_TIMEOUT)) 4520 dev_warn(&hdev->pdev->dev, 4521 "reset service task is scheduled after %ums on cpu%u!\n", 4522 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled), 4523 smp_processor_id()); 4524 4525 down(&hdev->reset_sem); 4526 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4527 4528 hclge_reset_subtask(hdev); 4529 4530 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4531 up(&hdev->reset_sem); 4532 } 4533 4534 static void hclge_update_vport_alive(struct hclge_dev *hdev) 4535 { 4536 #define HCLGE_ALIVE_SECONDS_NORMAL 8 4537 4538 unsigned long alive_time = HCLGE_ALIVE_SECONDS_NORMAL * HZ; 4539 int i; 4540 4541 /* start from vport 1 for PF is always alive */ 4542 for (i = 1; i < hdev->num_alloc_vport; i++) { 4543 struct hclge_vport *vport = &hdev->vport[i]; 4544 4545 if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) || 4546 !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 4547 continue; 4548 if (time_after(jiffies, vport->last_active_jiffies + 4549 alive_time)) { 4550 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 4551 dev_warn(&hdev->pdev->dev, 4552 "VF %u heartbeat timeout\n", 4553 i - HCLGE_VF_VPORT_START_NUM); 4554 } 4555 } 4556 } 4557 4558 static void hclge_periodic_service_task(struct hclge_dev *hdev) 4559 { 4560 unsigned long delta = round_jiffies_relative(HZ); 4561 4562 if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 4563 return; 4564 4565 /* Always handle the link updating to make sure link state is 4566 * updated when it is triggered by mbx. 4567 */ 4568 hclge_update_link_status(hdev); 4569 hclge_sync_mac_table(hdev); 4570 hclge_sync_promisc_mode(hdev); 4571 hclge_sync_fd_table(hdev); 4572 4573 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 4574 delta = jiffies - hdev->last_serv_processed; 4575 4576 if (delta < round_jiffies_relative(HZ)) { 4577 delta = round_jiffies_relative(HZ) - delta; 4578 goto out; 4579 } 4580 } 4581 4582 hdev->serv_processed_cnt++; 4583 hclge_update_vport_alive(hdev); 4584 4585 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) { 4586 hdev->last_serv_processed = jiffies; 4587 goto out; 4588 } 4589 4590 if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL)) 4591 hclge_update_stats_for_all(hdev); 4592 4593 hclge_update_port_info(hdev); 4594 hclge_sync_vlan_filter(hdev); 4595 4596 if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL)) 4597 hclge_rfs_filter_expire(hdev); 4598 4599 hdev->last_serv_processed = jiffies; 4600 4601 out: 4602 hclge_task_schedule(hdev, delta); 4603 } 4604 4605 static void hclge_ptp_service_task(struct hclge_dev *hdev) 4606 { 4607 unsigned long flags; 4608 4609 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) || 4610 !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) || 4611 !time_is_before_jiffies(hdev->ptp->tx_start + HZ)) 4612 return; 4613 4614 /* to prevent concurrence with the irq handler */ 4615 spin_lock_irqsave(&hdev->ptp->lock, flags); 4616 4617 /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq 4618 * handler may handle it just before spin_lock_irqsave(). 4619 */ 4620 if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) 4621 hclge_ptp_clean_tx_hwts(hdev); 4622 4623 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 4624 } 4625 4626 static void hclge_service_task(struct work_struct *work) 4627 { 4628 struct hclge_dev *hdev = 4629 container_of(work, struct hclge_dev, service_task.work); 4630 4631 hclge_errhand_service_task(hdev); 4632 hclge_reset_service_task(hdev); 4633 hclge_ptp_service_task(hdev); 4634 hclge_mailbox_service_task(hdev); 4635 hclge_periodic_service_task(hdev); 4636 4637 /* Handle error recovery, reset and mbx again in case periodical task 4638 * delays the handling by calling hclge_task_schedule() in 4639 * hclge_periodic_service_task(). 4640 */ 4641 hclge_errhand_service_task(hdev); 4642 hclge_reset_service_task(hdev); 4643 hclge_mailbox_service_task(hdev); 4644 } 4645 4646 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 4647 { 4648 /* VF handle has no client */ 4649 if (!handle->client) 4650 return container_of(handle, struct hclge_vport, nic); 4651 else if (handle->client->type == HNAE3_CLIENT_ROCE) 4652 return container_of(handle, struct hclge_vport, roce); 4653 else 4654 return container_of(handle, struct hclge_vport, nic); 4655 } 4656 4657 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx, 4658 struct hnae3_vector_info *vector_info) 4659 { 4660 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 64 4661 4662 vector_info->vector = pci_irq_vector(hdev->pdev, idx); 4663 4664 /* need an extend offset to config vector >= 64 */ 4665 if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2) 4666 vector_info->io_addr = hdev->hw.hw.io_base + 4667 HCLGE_VECTOR_REG_BASE + 4668 (idx - 1) * HCLGE_VECTOR_REG_OFFSET; 4669 else 4670 vector_info->io_addr = hdev->hw.hw.io_base + 4671 HCLGE_VECTOR_EXT_REG_BASE + 4672 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4673 HCLGE_VECTOR_REG_OFFSET_H + 4674 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4675 HCLGE_VECTOR_REG_OFFSET; 4676 4677 hdev->vector_status[idx] = hdev->vport[0].vport_id; 4678 hdev->vector_irq[idx] = vector_info->vector; 4679 } 4680 4681 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 4682 struct hnae3_vector_info *vector_info) 4683 { 4684 struct hclge_vport *vport = hclge_get_vport(handle); 4685 struct hnae3_vector_info *vector = vector_info; 4686 struct hclge_dev *hdev = vport->back; 4687 int alloc = 0; 4688 u16 i = 0; 4689 u16 j; 4690 4691 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num); 4692 vector_num = min(hdev->num_msi_left, vector_num); 4693 4694 for (j = 0; j < vector_num; j++) { 4695 while (++i < hdev->num_nic_msi) { 4696 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 4697 hclge_get_vector_info(hdev, i, vector); 4698 vector++; 4699 alloc++; 4700 4701 break; 4702 } 4703 } 4704 } 4705 hdev->num_msi_left -= alloc; 4706 hdev->num_msi_used += alloc; 4707 4708 return alloc; 4709 } 4710 4711 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 4712 { 4713 int i; 4714 4715 for (i = 0; i < hdev->num_msi; i++) 4716 if (vector == hdev->vector_irq[i]) 4717 return i; 4718 4719 return -EINVAL; 4720 } 4721 4722 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 4723 { 4724 struct hclge_vport *vport = hclge_get_vport(handle); 4725 struct hclge_dev *hdev = vport->back; 4726 int vector_id; 4727 4728 vector_id = hclge_get_vector_index(hdev, vector); 4729 if (vector_id < 0) { 4730 dev_err(&hdev->pdev->dev, 4731 "Get vector index fail. vector = %d\n", vector); 4732 return vector_id; 4733 } 4734 4735 hclge_free_vector(hdev, vector_id); 4736 4737 return 0; 4738 } 4739 4740 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 4741 u8 *key, u8 *hfunc) 4742 { 4743 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4744 struct hclge_vport *vport = hclge_get_vport(handle); 4745 struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg; 4746 4747 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 4748 4749 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 4750 ae_dev->dev_specs.rss_ind_tbl_size); 4751 4752 return 0; 4753 } 4754 4755 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 4756 const u8 *key, const u8 hfunc) 4757 { 4758 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4759 struct hclge_vport *vport = hclge_get_vport(handle); 4760 struct hclge_dev *hdev = vport->back; 4761 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 4762 int ret, i; 4763 4764 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc); 4765 if (ret) { 4766 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc); 4767 return ret; 4768 } 4769 4770 /* Update the shadow RSS table with user specified qids */ 4771 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 4772 rss_cfg->rss_indirection_tbl[i] = indir[i]; 4773 4774 /* Update the hardware */ 4775 return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw, 4776 rss_cfg->rss_indirection_tbl); 4777 } 4778 4779 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 4780 struct ethtool_rxnfc *nfc) 4781 { 4782 struct hclge_vport *vport = hclge_get_vport(handle); 4783 struct hclge_dev *hdev = vport->back; 4784 int ret; 4785 4786 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 4787 &hdev->rss_cfg, nfc); 4788 if (ret) { 4789 dev_err(&hdev->pdev->dev, 4790 "failed to set rss tuple, ret = %d.\n", ret); 4791 return ret; 4792 } 4793 4794 return 0; 4795 } 4796 4797 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 4798 struct ethtool_rxnfc *nfc) 4799 { 4800 struct hclge_vport *vport = hclge_get_vport(handle); 4801 u8 tuple_sets; 4802 int ret; 4803 4804 nfc->data = 0; 4805 4806 ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type, 4807 &tuple_sets); 4808 if (ret || !tuple_sets) 4809 return ret; 4810 4811 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 4812 4813 return 0; 4814 } 4815 4816 static int hclge_get_tc_size(struct hnae3_handle *handle) 4817 { 4818 struct hclge_vport *vport = hclge_get_vport(handle); 4819 struct hclge_dev *hdev = vport->back; 4820 4821 return hdev->pf_rss_size_max; 4822 } 4823 4824 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev) 4825 { 4826 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 4827 struct hclge_vport *vport = hdev->vport; 4828 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 4829 u16 tc_valid[HCLGE_MAX_TC_NUM] = {0}; 4830 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 4831 struct hnae3_tc_info *tc_info; 4832 u16 roundup_size; 4833 u16 rss_size; 4834 int i; 4835 4836 tc_info = &vport->nic.kinfo.tc_info; 4837 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 4838 rss_size = tc_info->tqp_count[i]; 4839 tc_valid[i] = 0; 4840 4841 if (!(hdev->hw_tc_map & BIT(i))) 4842 continue; 4843 4844 /* tc_size set to hardware is the log2 of roundup power of two 4845 * of rss_size, the acutal queue size is limited by indirection 4846 * table. 4847 */ 4848 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size || 4849 rss_size == 0) { 4850 dev_err(&hdev->pdev->dev, 4851 "Configure rss tc size failed, invalid TC_SIZE = %u\n", 4852 rss_size); 4853 return -EINVAL; 4854 } 4855 4856 roundup_size = roundup_pow_of_two(rss_size); 4857 roundup_size = ilog2(roundup_size); 4858 4859 tc_valid[i] = 1; 4860 tc_size[i] = roundup_size; 4861 tc_offset[i] = tc_info->tqp_offset[i]; 4862 } 4863 4864 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 4865 tc_size); 4866 } 4867 4868 int hclge_rss_init_hw(struct hclge_dev *hdev) 4869 { 4870 u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl; 4871 u8 *key = hdev->rss_cfg.rss_hash_key; 4872 u8 hfunc = hdev->rss_cfg.rss_algo; 4873 int ret; 4874 4875 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 4876 rss_indir); 4877 if (ret) 4878 return ret; 4879 4880 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key); 4881 if (ret) 4882 return ret; 4883 4884 ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, &hdev->rss_cfg); 4885 if (ret) 4886 return ret; 4887 4888 return hclge_init_rss_tc_mode(hdev); 4889 } 4890 4891 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 4892 int vector_id, bool en, 4893 struct hnae3_ring_chain_node *ring_chain) 4894 { 4895 struct hclge_dev *hdev = vport->back; 4896 struct hnae3_ring_chain_node *node; 4897 struct hclge_desc desc; 4898 struct hclge_ctrl_vector_chain_cmd *req = 4899 (struct hclge_ctrl_vector_chain_cmd *)desc.data; 4900 enum hclge_comm_cmd_status status; 4901 enum hclge_opcode_type op; 4902 u16 tqp_type_and_id; 4903 int i; 4904 4905 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 4906 hclge_cmd_setup_basic_desc(&desc, op, false); 4907 req->int_vector_id_l = hnae3_get_field(vector_id, 4908 HCLGE_VECTOR_ID_L_M, 4909 HCLGE_VECTOR_ID_L_S); 4910 req->int_vector_id_h = hnae3_get_field(vector_id, 4911 HCLGE_VECTOR_ID_H_M, 4912 HCLGE_VECTOR_ID_H_S); 4913 4914 i = 0; 4915 for (node = ring_chain; node; node = node->next) { 4916 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 4917 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 4918 HCLGE_INT_TYPE_S, 4919 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 4920 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 4921 HCLGE_TQP_ID_S, node->tqp_index); 4922 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 4923 HCLGE_INT_GL_IDX_S, 4924 hnae3_get_field(node->int_gl_idx, 4925 HNAE3_RING_GL_IDX_M, 4926 HNAE3_RING_GL_IDX_S)); 4927 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 4928 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 4929 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 4930 req->vfid = vport->vport_id; 4931 4932 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4933 if (status) { 4934 dev_err(&hdev->pdev->dev, 4935 "Map TQP fail, status is %d.\n", 4936 status); 4937 return -EIO; 4938 } 4939 i = 0; 4940 4941 hclge_cmd_setup_basic_desc(&desc, 4942 op, 4943 false); 4944 req->int_vector_id_l = 4945 hnae3_get_field(vector_id, 4946 HCLGE_VECTOR_ID_L_M, 4947 HCLGE_VECTOR_ID_L_S); 4948 req->int_vector_id_h = 4949 hnae3_get_field(vector_id, 4950 HCLGE_VECTOR_ID_H_M, 4951 HCLGE_VECTOR_ID_H_S); 4952 } 4953 } 4954 4955 if (i > 0) { 4956 req->int_cause_num = i; 4957 req->vfid = vport->vport_id; 4958 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4959 if (status) { 4960 dev_err(&hdev->pdev->dev, 4961 "Map TQP fail, status is %d.\n", status); 4962 return -EIO; 4963 } 4964 } 4965 4966 return 0; 4967 } 4968 4969 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector, 4970 struct hnae3_ring_chain_node *ring_chain) 4971 { 4972 struct hclge_vport *vport = hclge_get_vport(handle); 4973 struct hclge_dev *hdev = vport->back; 4974 int vector_id; 4975 4976 vector_id = hclge_get_vector_index(hdev, vector); 4977 if (vector_id < 0) { 4978 dev_err(&hdev->pdev->dev, 4979 "failed to get vector index. vector=%d\n", vector); 4980 return vector_id; 4981 } 4982 4983 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 4984 } 4985 4986 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector, 4987 struct hnae3_ring_chain_node *ring_chain) 4988 { 4989 struct hclge_vport *vport = hclge_get_vport(handle); 4990 struct hclge_dev *hdev = vport->back; 4991 int vector_id, ret; 4992 4993 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 4994 return 0; 4995 4996 vector_id = hclge_get_vector_index(hdev, vector); 4997 if (vector_id < 0) { 4998 dev_err(&handle->pdev->dev, 4999 "Get vector index fail. ret =%d\n", vector_id); 5000 return vector_id; 5001 } 5002 5003 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 5004 if (ret) 5005 dev_err(&handle->pdev->dev, 5006 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 5007 vector_id, ret); 5008 5009 return ret; 5010 } 5011 5012 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id, 5013 bool en_uc, bool en_mc, bool en_bc) 5014 { 5015 struct hclge_vport *vport = &hdev->vport[vf_id]; 5016 struct hnae3_handle *handle = &vport->nic; 5017 struct hclge_promisc_cfg_cmd *req; 5018 struct hclge_desc desc; 5019 bool uc_tx_en = en_uc; 5020 u8 promisc_cfg = 0; 5021 int ret; 5022 5023 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 5024 5025 req = (struct hclge_promisc_cfg_cmd *)desc.data; 5026 req->vf_id = vf_id; 5027 5028 if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags)) 5029 uc_tx_en = false; 5030 5031 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0); 5032 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0); 5033 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0); 5034 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0); 5035 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0); 5036 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0); 5037 req->extend_promisc = promisc_cfg; 5038 5039 /* to be compatible with DEVICE_VERSION_V1/2 */ 5040 promisc_cfg = 0; 5041 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0); 5042 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0); 5043 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0); 5044 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1); 5045 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1); 5046 req->promisc = promisc_cfg; 5047 5048 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5049 if (ret) 5050 dev_err(&hdev->pdev->dev, 5051 "failed to set vport %u promisc mode, ret = %d.\n", 5052 vf_id, ret); 5053 5054 return ret; 5055 } 5056 5057 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 5058 bool en_mc_pmc, bool en_bc_pmc) 5059 { 5060 return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id, 5061 en_uc_pmc, en_mc_pmc, en_bc_pmc); 5062 } 5063 5064 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 5065 bool en_mc_pmc) 5066 { 5067 struct hclge_vport *vport = hclge_get_vport(handle); 5068 struct hclge_dev *hdev = vport->back; 5069 bool en_bc_pmc = true; 5070 5071 /* For device whose version below V2, if broadcast promisc enabled, 5072 * vlan filter is always bypassed. So broadcast promisc should be 5073 * disabled until user enable promisc mode 5074 */ 5075 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 5076 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false; 5077 5078 return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc, 5079 en_bc_pmc); 5080 } 5081 5082 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle) 5083 { 5084 struct hclge_vport *vport = hclge_get_vport(handle); 5085 5086 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5087 } 5088 5089 static void hclge_sync_fd_state(struct hclge_dev *hdev) 5090 { 5091 if (hlist_empty(&hdev->fd_rule_list)) 5092 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 5093 } 5094 5095 static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location) 5096 { 5097 if (!test_bit(location, hdev->fd_bmap)) { 5098 set_bit(location, hdev->fd_bmap); 5099 hdev->hclge_fd_rule_num++; 5100 } 5101 } 5102 5103 static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location) 5104 { 5105 if (test_bit(location, hdev->fd_bmap)) { 5106 clear_bit(location, hdev->fd_bmap); 5107 hdev->hclge_fd_rule_num--; 5108 } 5109 } 5110 5111 static void hclge_fd_free_node(struct hclge_dev *hdev, 5112 struct hclge_fd_rule *rule) 5113 { 5114 hlist_del(&rule->rule_node); 5115 kfree(rule); 5116 hclge_sync_fd_state(hdev); 5117 } 5118 5119 static void hclge_update_fd_rule_node(struct hclge_dev *hdev, 5120 struct hclge_fd_rule *old_rule, 5121 struct hclge_fd_rule *new_rule, 5122 enum HCLGE_FD_NODE_STATE state) 5123 { 5124 switch (state) { 5125 case HCLGE_FD_TO_ADD: 5126 case HCLGE_FD_ACTIVE: 5127 /* 1) if the new state is TO_ADD, just replace the old rule 5128 * with the same location, no matter its state, because the 5129 * new rule will be configured to the hardware. 5130 * 2) if the new state is ACTIVE, it means the new rule 5131 * has been configured to the hardware, so just replace 5132 * the old rule node with the same location. 5133 * 3) for it doesn't add a new node to the list, so it's 5134 * unnecessary to update the rule number and fd_bmap. 5135 */ 5136 new_rule->rule_node.next = old_rule->rule_node.next; 5137 new_rule->rule_node.pprev = old_rule->rule_node.pprev; 5138 memcpy(old_rule, new_rule, sizeof(*old_rule)); 5139 kfree(new_rule); 5140 break; 5141 case HCLGE_FD_DELETED: 5142 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5143 hclge_fd_free_node(hdev, old_rule); 5144 break; 5145 case HCLGE_FD_TO_DEL: 5146 /* if new request is TO_DEL, and old rule is existent 5147 * 1) the state of old rule is TO_DEL, we need do nothing, 5148 * because we delete rule by location, other rule content 5149 * is unncessary. 5150 * 2) the state of old rule is ACTIVE, we need to change its 5151 * state to TO_DEL, so the rule will be deleted when periodic 5152 * task being scheduled. 5153 * 3) the state of old rule is TO_ADD, it means the rule hasn't 5154 * been added to hardware, so we just delete the rule node from 5155 * fd_rule_list directly. 5156 */ 5157 if (old_rule->state == HCLGE_FD_TO_ADD) { 5158 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5159 hclge_fd_free_node(hdev, old_rule); 5160 return; 5161 } 5162 old_rule->state = HCLGE_FD_TO_DEL; 5163 break; 5164 } 5165 } 5166 5167 static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist, 5168 u16 location, 5169 struct hclge_fd_rule **parent) 5170 { 5171 struct hclge_fd_rule *rule; 5172 struct hlist_node *node; 5173 5174 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 5175 if (rule->location == location) 5176 return rule; 5177 else if (rule->location > location) 5178 return NULL; 5179 /* record the parent node, use to keep the nodes in fd_rule_list 5180 * in ascend order. 5181 */ 5182 *parent = rule; 5183 } 5184 5185 return NULL; 5186 } 5187 5188 /* insert fd rule node in ascend order according to rule->location */ 5189 static void hclge_fd_insert_rule_node(struct hlist_head *hlist, 5190 struct hclge_fd_rule *rule, 5191 struct hclge_fd_rule *parent) 5192 { 5193 INIT_HLIST_NODE(&rule->rule_node); 5194 5195 if (parent) 5196 hlist_add_behind(&rule->rule_node, &parent->rule_node); 5197 else 5198 hlist_add_head(&rule->rule_node, hlist); 5199 } 5200 5201 static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev, 5202 struct hclge_fd_user_def_cfg *cfg) 5203 { 5204 struct hclge_fd_user_def_cfg_cmd *req; 5205 struct hclge_desc desc; 5206 u16 data = 0; 5207 int ret; 5208 5209 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false); 5210 5211 req = (struct hclge_fd_user_def_cfg_cmd *)desc.data; 5212 5213 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0); 5214 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5215 HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset); 5216 req->ol2_cfg = cpu_to_le16(data); 5217 5218 data = 0; 5219 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0); 5220 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5221 HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset); 5222 req->ol3_cfg = cpu_to_le16(data); 5223 5224 data = 0; 5225 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0); 5226 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5227 HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset); 5228 req->ol4_cfg = cpu_to_le16(data); 5229 5230 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5231 if (ret) 5232 dev_err(&hdev->pdev->dev, 5233 "failed to set fd user def data, ret= %d\n", ret); 5234 return ret; 5235 } 5236 5237 static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked) 5238 { 5239 int ret; 5240 5241 if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state)) 5242 return; 5243 5244 if (!locked) 5245 spin_lock_bh(&hdev->fd_rule_lock); 5246 5247 ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg); 5248 if (ret) 5249 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5250 5251 if (!locked) 5252 spin_unlock_bh(&hdev->fd_rule_lock); 5253 } 5254 5255 static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev, 5256 struct hclge_fd_rule *rule) 5257 { 5258 struct hlist_head *hlist = &hdev->fd_rule_list; 5259 struct hclge_fd_rule *fd_rule, *parent = NULL; 5260 struct hclge_fd_user_def_info *info, *old_info; 5261 struct hclge_fd_user_def_cfg *cfg; 5262 5263 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5264 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5265 return 0; 5266 5267 /* for valid layer is start from 1, so need minus 1 to get the cfg */ 5268 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5269 info = &rule->ep.user_def; 5270 5271 if (!cfg->ref_cnt || cfg->offset == info->offset) 5272 return 0; 5273 5274 if (cfg->ref_cnt > 1) 5275 goto error; 5276 5277 fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent); 5278 if (fd_rule) { 5279 old_info = &fd_rule->ep.user_def; 5280 if (info->layer == old_info->layer) 5281 return 0; 5282 } 5283 5284 error: 5285 dev_err(&hdev->pdev->dev, 5286 "No available offset for layer%d fd rule, each layer only support one user def offset.\n", 5287 info->layer + 1); 5288 return -ENOSPC; 5289 } 5290 5291 static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev, 5292 struct hclge_fd_rule *rule) 5293 { 5294 struct hclge_fd_user_def_cfg *cfg; 5295 5296 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5297 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5298 return; 5299 5300 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5301 if (!cfg->ref_cnt) { 5302 cfg->offset = rule->ep.user_def.offset; 5303 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5304 } 5305 cfg->ref_cnt++; 5306 } 5307 5308 static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev, 5309 struct hclge_fd_rule *rule) 5310 { 5311 struct hclge_fd_user_def_cfg *cfg; 5312 5313 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5314 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5315 return; 5316 5317 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5318 if (!cfg->ref_cnt) 5319 return; 5320 5321 cfg->ref_cnt--; 5322 if (!cfg->ref_cnt) { 5323 cfg->offset = 0; 5324 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5325 } 5326 } 5327 5328 static void hclge_update_fd_list(struct hclge_dev *hdev, 5329 enum HCLGE_FD_NODE_STATE state, u16 location, 5330 struct hclge_fd_rule *new_rule) 5331 { 5332 struct hlist_head *hlist = &hdev->fd_rule_list; 5333 struct hclge_fd_rule *fd_rule, *parent = NULL; 5334 5335 fd_rule = hclge_find_fd_rule(hlist, location, &parent); 5336 if (fd_rule) { 5337 hclge_fd_dec_user_def_refcnt(hdev, fd_rule); 5338 if (state == HCLGE_FD_ACTIVE) 5339 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5340 hclge_sync_fd_user_def_cfg(hdev, true); 5341 5342 hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state); 5343 return; 5344 } 5345 5346 /* it's unlikely to fail here, because we have checked the rule 5347 * exist before. 5348 */ 5349 if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) { 5350 dev_warn(&hdev->pdev->dev, 5351 "failed to delete fd rule %u, it's inexistent\n", 5352 location); 5353 return; 5354 } 5355 5356 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5357 hclge_sync_fd_user_def_cfg(hdev, true); 5358 5359 hclge_fd_insert_rule_node(hlist, new_rule, parent); 5360 hclge_fd_inc_rule_cnt(hdev, new_rule->location); 5361 5362 if (state == HCLGE_FD_TO_ADD) { 5363 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 5364 hclge_task_schedule(hdev, 0); 5365 } 5366 } 5367 5368 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode) 5369 { 5370 struct hclge_get_fd_mode_cmd *req; 5371 struct hclge_desc desc; 5372 int ret; 5373 5374 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true); 5375 5376 req = (struct hclge_get_fd_mode_cmd *)desc.data; 5377 5378 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5379 if (ret) { 5380 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret); 5381 return ret; 5382 } 5383 5384 *fd_mode = req->mode; 5385 5386 return ret; 5387 } 5388 5389 static int hclge_get_fd_allocation(struct hclge_dev *hdev, 5390 u32 *stage1_entry_num, 5391 u32 *stage2_entry_num, 5392 u16 *stage1_counter_num, 5393 u16 *stage2_counter_num) 5394 { 5395 struct hclge_get_fd_allocation_cmd *req; 5396 struct hclge_desc desc; 5397 int ret; 5398 5399 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true); 5400 5401 req = (struct hclge_get_fd_allocation_cmd *)desc.data; 5402 5403 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5404 if (ret) { 5405 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n", 5406 ret); 5407 return ret; 5408 } 5409 5410 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num); 5411 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num); 5412 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num); 5413 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num); 5414 5415 return ret; 5416 } 5417 5418 static int hclge_set_fd_key_config(struct hclge_dev *hdev, 5419 enum HCLGE_FD_STAGE stage_num) 5420 { 5421 struct hclge_set_fd_key_config_cmd *req; 5422 struct hclge_fd_key_cfg *stage; 5423 struct hclge_desc desc; 5424 int ret; 5425 5426 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false); 5427 5428 req = (struct hclge_set_fd_key_config_cmd *)desc.data; 5429 stage = &hdev->fd_cfg.key_cfg[stage_num]; 5430 req->stage = stage_num; 5431 req->key_select = stage->key_sel; 5432 req->inner_sipv6_word_en = stage->inner_sipv6_word_en; 5433 req->inner_dipv6_word_en = stage->inner_dipv6_word_en; 5434 req->outer_sipv6_word_en = stage->outer_sipv6_word_en; 5435 req->outer_dipv6_word_en = stage->outer_dipv6_word_en; 5436 req->tuple_mask = cpu_to_le32(~stage->tuple_active); 5437 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active); 5438 5439 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5440 if (ret) 5441 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret); 5442 5443 return ret; 5444 } 5445 5446 static void hclge_fd_disable_user_def(struct hclge_dev *hdev) 5447 { 5448 struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg; 5449 5450 spin_lock_bh(&hdev->fd_rule_lock); 5451 memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg)); 5452 spin_unlock_bh(&hdev->fd_rule_lock); 5453 5454 hclge_fd_set_user_def_cmd(hdev, cfg); 5455 } 5456 5457 static int hclge_init_fd_config(struct hclge_dev *hdev) 5458 { 5459 #define LOW_2_WORDS 0x03 5460 struct hclge_fd_key_cfg *key_cfg; 5461 int ret; 5462 5463 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 5464 return 0; 5465 5466 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode); 5467 if (ret) 5468 return ret; 5469 5470 switch (hdev->fd_cfg.fd_mode) { 5471 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1: 5472 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH; 5473 break; 5474 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1: 5475 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2; 5476 break; 5477 default: 5478 dev_err(&hdev->pdev->dev, 5479 "Unsupported flow director mode %u\n", 5480 hdev->fd_cfg.fd_mode); 5481 return -EOPNOTSUPP; 5482 } 5483 5484 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1]; 5485 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE; 5486 key_cfg->inner_sipv6_word_en = LOW_2_WORDS; 5487 key_cfg->inner_dipv6_word_en = LOW_2_WORDS; 5488 key_cfg->outer_sipv6_word_en = 0; 5489 key_cfg->outer_dipv6_word_en = 0; 5490 5491 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) | 5492 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) | 5493 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5494 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5495 5496 /* If use max 400bit key, we can support tuples for ether type */ 5497 if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 5498 key_cfg->tuple_active |= 5499 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC); 5500 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5501 key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 5502 } 5503 5504 /* roce_type is used to filter roce frames 5505 * dst_vport is used to specify the rule 5506 */ 5507 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT); 5508 5509 ret = hclge_get_fd_allocation(hdev, 5510 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1], 5511 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2], 5512 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1], 5513 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]); 5514 if (ret) 5515 return ret; 5516 5517 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1); 5518 } 5519 5520 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x, 5521 int loc, u8 *key, bool is_add) 5522 { 5523 struct hclge_fd_tcam_config_1_cmd *req1; 5524 struct hclge_fd_tcam_config_2_cmd *req2; 5525 struct hclge_fd_tcam_config_3_cmd *req3; 5526 struct hclge_desc desc[3]; 5527 int ret; 5528 5529 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false); 5530 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5531 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false); 5532 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5533 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false); 5534 5535 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 5536 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 5537 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 5538 5539 req1->stage = stage; 5540 req1->xy_sel = sel_x ? 1 : 0; 5541 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0); 5542 req1->index = cpu_to_le32(loc); 5543 req1->entry_vld = sel_x ? is_add : 0; 5544 5545 if (key) { 5546 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data)); 5547 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)], 5548 sizeof(req2->tcam_data)); 5549 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) + 5550 sizeof(req2->tcam_data)], sizeof(req3->tcam_data)); 5551 } 5552 5553 ret = hclge_cmd_send(&hdev->hw, desc, 3); 5554 if (ret) 5555 dev_err(&hdev->pdev->dev, 5556 "config tcam key fail, ret=%d\n", 5557 ret); 5558 5559 return ret; 5560 } 5561 5562 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc, 5563 struct hclge_fd_ad_data *action) 5564 { 5565 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 5566 struct hclge_fd_ad_config_cmd *req; 5567 struct hclge_desc desc; 5568 u64 ad_data = 0; 5569 int ret; 5570 5571 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false); 5572 5573 req = (struct hclge_fd_ad_config_cmd *)desc.data; 5574 req->index = cpu_to_le32(loc); 5575 req->stage = stage; 5576 5577 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B, 5578 action->write_rule_id_to_bd); 5579 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S, 5580 action->rule_id); 5581 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) { 5582 hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B, 5583 action->override_tc); 5584 hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M, 5585 HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size); 5586 } 5587 ad_data <<= 32; 5588 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet); 5589 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B, 5590 action->forward_to_direct_queue); 5591 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S, 5592 action->queue_id); 5593 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter); 5594 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M, 5595 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id); 5596 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage); 5597 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S, 5598 action->counter_id); 5599 5600 req->ad_data = cpu_to_le64(ad_data); 5601 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5602 if (ret) 5603 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret); 5604 5605 return ret; 5606 } 5607 5608 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y, 5609 struct hclge_fd_rule *rule) 5610 { 5611 int offset, moffset, ip_offset; 5612 enum HCLGE_FD_KEY_OPT key_opt; 5613 u16 tmp_x_s, tmp_y_s; 5614 u32 tmp_x_l, tmp_y_l; 5615 u8 *p = (u8 *)rule; 5616 int i; 5617 5618 if (rule->unused_tuple & BIT(tuple_bit)) 5619 return true; 5620 5621 key_opt = tuple_key_info[tuple_bit].key_opt; 5622 offset = tuple_key_info[tuple_bit].offset; 5623 moffset = tuple_key_info[tuple_bit].moffset; 5624 5625 switch (key_opt) { 5626 case KEY_OPT_U8: 5627 calc_x(*key_x, p[offset], p[moffset]); 5628 calc_y(*key_y, p[offset], p[moffset]); 5629 5630 return true; 5631 case KEY_OPT_LE16: 5632 calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5633 calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5634 *(__le16 *)key_x = cpu_to_le16(tmp_x_s); 5635 *(__le16 *)key_y = cpu_to_le16(tmp_y_s); 5636 5637 return true; 5638 case KEY_OPT_LE32: 5639 calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5640 calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5641 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5642 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5643 5644 return true; 5645 case KEY_OPT_MAC: 5646 for (i = 0; i < ETH_ALEN; i++) { 5647 calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i], 5648 p[moffset + i]); 5649 calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i], 5650 p[moffset + i]); 5651 } 5652 5653 return true; 5654 case KEY_OPT_IP: 5655 ip_offset = IPV4_INDEX * sizeof(u32); 5656 calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]), 5657 *(u32 *)(&p[moffset + ip_offset])); 5658 calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]), 5659 *(u32 *)(&p[moffset + ip_offset])); 5660 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5661 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5662 5663 return true; 5664 default: 5665 return false; 5666 } 5667 } 5668 5669 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 5670 u8 vf_id, u8 network_port_id) 5671 { 5672 u32 port_number = 0; 5673 5674 if (port_type == HOST_PORT) { 5675 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S, 5676 pf_id); 5677 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S, 5678 vf_id); 5679 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT); 5680 } else { 5681 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M, 5682 HCLGE_NETWORK_PORT_ID_S, network_port_id); 5683 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT); 5684 } 5685 5686 return port_number; 5687 } 5688 5689 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg, 5690 __le32 *key_x, __le32 *key_y, 5691 struct hclge_fd_rule *rule) 5692 { 5693 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number; 5694 u8 cur_pos = 0, tuple_size, shift_bits; 5695 unsigned int i; 5696 5697 for (i = 0; i < MAX_META_DATA; i++) { 5698 tuple_size = meta_data_key_info[i].key_length; 5699 tuple_bit = key_cfg->meta_data_active & BIT(i); 5700 5701 switch (tuple_bit) { 5702 case BIT(ROCE_TYPE): 5703 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET); 5704 cur_pos += tuple_size; 5705 break; 5706 case BIT(DST_VPORT): 5707 port_number = hclge_get_port_number(HOST_PORT, 0, 5708 rule->vf_id, 0); 5709 hnae3_set_field(meta_data, 5710 GENMASK(cur_pos + tuple_size, cur_pos), 5711 cur_pos, port_number); 5712 cur_pos += tuple_size; 5713 break; 5714 default: 5715 break; 5716 } 5717 } 5718 5719 calc_x(tmp_x, meta_data, 0xFFFFFFFF); 5720 calc_y(tmp_y, meta_data, 0xFFFFFFFF); 5721 shift_bits = sizeof(meta_data) * 8 - cur_pos; 5722 5723 *key_x = cpu_to_le32(tmp_x << shift_bits); 5724 *key_y = cpu_to_le32(tmp_y << shift_bits); 5725 } 5726 5727 /* A complete key is combined with meta data key and tuple key. 5728 * Meta data key is stored at the MSB region, and tuple key is stored at 5729 * the LSB region, unused bits will be filled 0. 5730 */ 5731 static int hclge_config_key(struct hclge_dev *hdev, u8 stage, 5732 struct hclge_fd_rule *rule) 5733 { 5734 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage]; 5735 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES]; 5736 u8 *cur_key_x, *cur_key_y; 5737 u8 meta_data_region; 5738 u8 tuple_size; 5739 int ret; 5740 u32 i; 5741 5742 memset(key_x, 0, sizeof(key_x)); 5743 memset(key_y, 0, sizeof(key_y)); 5744 cur_key_x = key_x; 5745 cur_key_y = key_y; 5746 5747 for (i = 0; i < MAX_TUPLE; i++) { 5748 bool tuple_valid; 5749 5750 tuple_size = tuple_key_info[i].key_length / 8; 5751 if (!(key_cfg->tuple_active & BIT(i))) 5752 continue; 5753 5754 tuple_valid = hclge_fd_convert_tuple(i, cur_key_x, 5755 cur_key_y, rule); 5756 if (tuple_valid) { 5757 cur_key_x += tuple_size; 5758 cur_key_y += tuple_size; 5759 } 5760 } 5761 5762 meta_data_region = hdev->fd_cfg.max_key_length / 8 - 5763 MAX_META_DATA_LENGTH / 8; 5764 5765 hclge_fd_convert_meta_data(key_cfg, 5766 (__le32 *)(key_x + meta_data_region), 5767 (__le32 *)(key_y + meta_data_region), 5768 rule); 5769 5770 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y, 5771 true); 5772 if (ret) { 5773 dev_err(&hdev->pdev->dev, 5774 "fd key_y config fail, loc=%u, ret=%d\n", 5775 rule->queue_id, ret); 5776 return ret; 5777 } 5778 5779 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x, 5780 true); 5781 if (ret) 5782 dev_err(&hdev->pdev->dev, 5783 "fd key_x config fail, loc=%u, ret=%d\n", 5784 rule->queue_id, ret); 5785 return ret; 5786 } 5787 5788 static int hclge_config_action(struct hclge_dev *hdev, u8 stage, 5789 struct hclge_fd_rule *rule) 5790 { 5791 struct hclge_vport *vport = hdev->vport; 5792 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5793 struct hclge_fd_ad_data ad_data; 5794 5795 memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data)); 5796 ad_data.ad_id = rule->location; 5797 5798 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 5799 ad_data.drop_packet = true; 5800 } else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) { 5801 ad_data.override_tc = true; 5802 ad_data.queue_id = 5803 kinfo->tc_info.tqp_offset[rule->cls_flower.tc]; 5804 ad_data.tc_size = 5805 ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]); 5806 } else { 5807 ad_data.forward_to_direct_queue = true; 5808 ad_data.queue_id = rule->queue_id; 5809 } 5810 5811 if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) { 5812 ad_data.use_counter = true; 5813 ad_data.counter_id = rule->vf_id % 5814 hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]; 5815 } else { 5816 ad_data.use_counter = false; 5817 ad_data.counter_id = 0; 5818 } 5819 5820 ad_data.use_next_stage = false; 5821 ad_data.next_input_key = 0; 5822 5823 ad_data.write_rule_id_to_bd = true; 5824 ad_data.rule_id = rule->location; 5825 5826 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data); 5827 } 5828 5829 static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec, 5830 u32 *unused_tuple) 5831 { 5832 if (!spec || !unused_tuple) 5833 return -EINVAL; 5834 5835 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5836 5837 if (!spec->ip4src) 5838 *unused_tuple |= BIT(INNER_SRC_IP); 5839 5840 if (!spec->ip4dst) 5841 *unused_tuple |= BIT(INNER_DST_IP); 5842 5843 if (!spec->psrc) 5844 *unused_tuple |= BIT(INNER_SRC_PORT); 5845 5846 if (!spec->pdst) 5847 *unused_tuple |= BIT(INNER_DST_PORT); 5848 5849 if (!spec->tos) 5850 *unused_tuple |= BIT(INNER_IP_TOS); 5851 5852 return 0; 5853 } 5854 5855 static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec, 5856 u32 *unused_tuple) 5857 { 5858 if (!spec || !unused_tuple) 5859 return -EINVAL; 5860 5861 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5862 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5863 5864 if (!spec->ip4src) 5865 *unused_tuple |= BIT(INNER_SRC_IP); 5866 5867 if (!spec->ip4dst) 5868 *unused_tuple |= BIT(INNER_DST_IP); 5869 5870 if (!spec->tos) 5871 *unused_tuple |= BIT(INNER_IP_TOS); 5872 5873 if (!spec->proto) 5874 *unused_tuple |= BIT(INNER_IP_PROTO); 5875 5876 if (spec->l4_4_bytes) 5877 return -EOPNOTSUPP; 5878 5879 if (spec->ip_ver != ETH_RX_NFC_IP4) 5880 return -EOPNOTSUPP; 5881 5882 return 0; 5883 } 5884 5885 static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec, 5886 u32 *unused_tuple) 5887 { 5888 if (!spec || !unused_tuple) 5889 return -EINVAL; 5890 5891 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5892 5893 /* check whether src/dst ip address used */ 5894 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5895 *unused_tuple |= BIT(INNER_SRC_IP); 5896 5897 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5898 *unused_tuple |= BIT(INNER_DST_IP); 5899 5900 if (!spec->psrc) 5901 *unused_tuple |= BIT(INNER_SRC_PORT); 5902 5903 if (!spec->pdst) 5904 *unused_tuple |= BIT(INNER_DST_PORT); 5905 5906 if (!spec->tclass) 5907 *unused_tuple |= BIT(INNER_IP_TOS); 5908 5909 return 0; 5910 } 5911 5912 static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec, 5913 u32 *unused_tuple) 5914 { 5915 if (!spec || !unused_tuple) 5916 return -EINVAL; 5917 5918 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5919 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5920 5921 /* check whether src/dst ip address used */ 5922 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5923 *unused_tuple |= BIT(INNER_SRC_IP); 5924 5925 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5926 *unused_tuple |= BIT(INNER_DST_IP); 5927 5928 if (!spec->l4_proto) 5929 *unused_tuple |= BIT(INNER_IP_PROTO); 5930 5931 if (!spec->tclass) 5932 *unused_tuple |= BIT(INNER_IP_TOS); 5933 5934 if (spec->l4_4_bytes) 5935 return -EOPNOTSUPP; 5936 5937 return 0; 5938 } 5939 5940 static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple) 5941 { 5942 if (!spec || !unused_tuple) 5943 return -EINVAL; 5944 5945 *unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5946 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) | 5947 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO); 5948 5949 if (is_zero_ether_addr(spec->h_source)) 5950 *unused_tuple |= BIT(INNER_SRC_MAC); 5951 5952 if (is_zero_ether_addr(spec->h_dest)) 5953 *unused_tuple |= BIT(INNER_DST_MAC); 5954 5955 if (!spec->h_proto) 5956 *unused_tuple |= BIT(INNER_ETH_TYPE); 5957 5958 return 0; 5959 } 5960 5961 static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev, 5962 struct ethtool_rx_flow_spec *fs, 5963 u32 *unused_tuple) 5964 { 5965 if (fs->flow_type & FLOW_EXT) { 5966 if (fs->h_ext.vlan_etype) { 5967 dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n"); 5968 return -EOPNOTSUPP; 5969 } 5970 5971 if (!fs->h_ext.vlan_tci) 5972 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 5973 5974 if (fs->m_ext.vlan_tci && 5975 be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) { 5976 dev_err(&hdev->pdev->dev, 5977 "failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n", 5978 ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1); 5979 return -EINVAL; 5980 } 5981 } else { 5982 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 5983 } 5984 5985 if (fs->flow_type & FLOW_MAC_EXT) { 5986 if (hdev->fd_cfg.fd_mode != 5987 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 5988 dev_err(&hdev->pdev->dev, 5989 "FLOW_MAC_EXT is not supported in current fd mode!\n"); 5990 return -EOPNOTSUPP; 5991 } 5992 5993 if (is_zero_ether_addr(fs->h_ext.h_dest)) 5994 *unused_tuple |= BIT(INNER_DST_MAC); 5995 else 5996 *unused_tuple &= ~BIT(INNER_DST_MAC); 5997 } 5998 5999 return 0; 6000 } 6001 6002 static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple, 6003 struct hclge_fd_user_def_info *info) 6004 { 6005 switch (flow_type) { 6006 case ETHER_FLOW: 6007 info->layer = HCLGE_FD_USER_DEF_L2; 6008 *unused_tuple &= ~BIT(INNER_L2_RSV); 6009 break; 6010 case IP_USER_FLOW: 6011 case IPV6_USER_FLOW: 6012 info->layer = HCLGE_FD_USER_DEF_L3; 6013 *unused_tuple &= ~BIT(INNER_L3_RSV); 6014 break; 6015 case TCP_V4_FLOW: 6016 case UDP_V4_FLOW: 6017 case TCP_V6_FLOW: 6018 case UDP_V6_FLOW: 6019 info->layer = HCLGE_FD_USER_DEF_L4; 6020 *unused_tuple &= ~BIT(INNER_L4_RSV); 6021 break; 6022 default: 6023 return -EOPNOTSUPP; 6024 } 6025 6026 return 0; 6027 } 6028 6029 static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs) 6030 { 6031 return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0; 6032 } 6033 6034 static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev, 6035 struct ethtool_rx_flow_spec *fs, 6036 u32 *unused_tuple, 6037 struct hclge_fd_user_def_info *info) 6038 { 6039 u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active; 6040 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6041 u16 data, offset, data_mask, offset_mask; 6042 int ret; 6043 6044 info->layer = HCLGE_FD_USER_DEF_NONE; 6045 *unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 6046 6047 if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs)) 6048 return 0; 6049 6050 /* user-def data from ethtool is 64 bit value, the bit0~15 is used 6051 * for data, and bit32~47 is used for offset. 6052 */ 6053 data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6054 data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6055 offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6056 offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6057 6058 if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) { 6059 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n"); 6060 return -EOPNOTSUPP; 6061 } 6062 6063 if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) { 6064 dev_err(&hdev->pdev->dev, 6065 "user-def offset[%u] should be no more than %u\n", 6066 offset, HCLGE_FD_MAX_USER_DEF_OFFSET); 6067 return -EINVAL; 6068 } 6069 6070 if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) { 6071 dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n"); 6072 return -EINVAL; 6073 } 6074 6075 ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info); 6076 if (ret) { 6077 dev_err(&hdev->pdev->dev, 6078 "unsupported flow type for user-def bytes, ret = %d\n", 6079 ret); 6080 return ret; 6081 } 6082 6083 info->data = data; 6084 info->data_mask = data_mask; 6085 info->offset = offset; 6086 6087 return 0; 6088 } 6089 6090 static int hclge_fd_check_spec(struct hclge_dev *hdev, 6091 struct ethtool_rx_flow_spec *fs, 6092 u32 *unused_tuple, 6093 struct hclge_fd_user_def_info *info) 6094 { 6095 u32 flow_type; 6096 int ret; 6097 6098 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 6099 dev_err(&hdev->pdev->dev, 6100 "failed to config fd rules, invalid rule location: %u, max is %u\n.", 6101 fs->location, 6102 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1); 6103 return -EINVAL; 6104 } 6105 6106 ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info); 6107 if (ret) 6108 return ret; 6109 6110 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6111 switch (flow_type) { 6112 case SCTP_V4_FLOW: 6113 case TCP_V4_FLOW: 6114 case UDP_V4_FLOW: 6115 ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec, 6116 unused_tuple); 6117 break; 6118 case IP_USER_FLOW: 6119 ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec, 6120 unused_tuple); 6121 break; 6122 case SCTP_V6_FLOW: 6123 case TCP_V6_FLOW: 6124 case UDP_V6_FLOW: 6125 ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec, 6126 unused_tuple); 6127 break; 6128 case IPV6_USER_FLOW: 6129 ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec, 6130 unused_tuple); 6131 break; 6132 case ETHER_FLOW: 6133 if (hdev->fd_cfg.fd_mode != 6134 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6135 dev_err(&hdev->pdev->dev, 6136 "ETHER_FLOW is not supported in current fd mode!\n"); 6137 return -EOPNOTSUPP; 6138 } 6139 6140 ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec, 6141 unused_tuple); 6142 break; 6143 default: 6144 dev_err(&hdev->pdev->dev, 6145 "unsupported protocol type, protocol type = %#x\n", 6146 flow_type); 6147 return -EOPNOTSUPP; 6148 } 6149 6150 if (ret) { 6151 dev_err(&hdev->pdev->dev, 6152 "failed to check flow union tuple, ret = %d\n", 6153 ret); 6154 return ret; 6155 } 6156 6157 return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple); 6158 } 6159 6160 static void hclge_fd_get_tcpip4_tuple(struct ethtool_rx_flow_spec *fs, 6161 struct hclge_fd_rule *rule, u8 ip_proto) 6162 { 6163 rule->tuples.src_ip[IPV4_INDEX] = 6164 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src); 6165 rule->tuples_mask.src_ip[IPV4_INDEX] = 6166 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src); 6167 6168 rule->tuples.dst_ip[IPV4_INDEX] = 6169 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst); 6170 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6171 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst); 6172 6173 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc); 6174 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc); 6175 6176 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst); 6177 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst); 6178 6179 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos; 6180 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos; 6181 6182 rule->tuples.ether_proto = ETH_P_IP; 6183 rule->tuples_mask.ether_proto = 0xFFFF; 6184 6185 rule->tuples.ip_proto = ip_proto; 6186 rule->tuples_mask.ip_proto = 0xFF; 6187 } 6188 6189 static void hclge_fd_get_ip4_tuple(struct ethtool_rx_flow_spec *fs, 6190 struct hclge_fd_rule *rule) 6191 { 6192 rule->tuples.src_ip[IPV4_INDEX] = 6193 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src); 6194 rule->tuples_mask.src_ip[IPV4_INDEX] = 6195 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src); 6196 6197 rule->tuples.dst_ip[IPV4_INDEX] = 6198 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst); 6199 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6200 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst); 6201 6202 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos; 6203 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos; 6204 6205 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto; 6206 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto; 6207 6208 rule->tuples.ether_proto = ETH_P_IP; 6209 rule->tuples_mask.ether_proto = 0xFFFF; 6210 } 6211 6212 static void hclge_fd_get_tcpip6_tuple(struct ethtool_rx_flow_spec *fs, 6213 struct hclge_fd_rule *rule, u8 ip_proto) 6214 { 6215 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.tcp_ip6_spec.ip6src, 6216 IPV6_SIZE); 6217 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.tcp_ip6_spec.ip6src, 6218 IPV6_SIZE); 6219 6220 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.tcp_ip6_spec.ip6dst, 6221 IPV6_SIZE); 6222 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.tcp_ip6_spec.ip6dst, 6223 IPV6_SIZE); 6224 6225 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc); 6226 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc); 6227 6228 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst); 6229 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst); 6230 6231 rule->tuples.ether_proto = ETH_P_IPV6; 6232 rule->tuples_mask.ether_proto = 0xFFFF; 6233 6234 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6235 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6236 6237 rule->tuples.ip_proto = ip_proto; 6238 rule->tuples_mask.ip_proto = 0xFF; 6239 } 6240 6241 static void hclge_fd_get_ip6_tuple(struct ethtool_rx_flow_spec *fs, 6242 struct hclge_fd_rule *rule) 6243 { 6244 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.usr_ip6_spec.ip6src, 6245 IPV6_SIZE); 6246 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.usr_ip6_spec.ip6src, 6247 IPV6_SIZE); 6248 6249 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.usr_ip6_spec.ip6dst, 6250 IPV6_SIZE); 6251 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.usr_ip6_spec.ip6dst, 6252 IPV6_SIZE); 6253 6254 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto; 6255 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto; 6256 6257 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6258 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6259 6260 rule->tuples.ether_proto = ETH_P_IPV6; 6261 rule->tuples_mask.ether_proto = 0xFFFF; 6262 } 6263 6264 static void hclge_fd_get_ether_tuple(struct ethtool_rx_flow_spec *fs, 6265 struct hclge_fd_rule *rule) 6266 { 6267 ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source); 6268 ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source); 6269 6270 ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest); 6271 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest); 6272 6273 rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto); 6274 rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto); 6275 } 6276 6277 static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info, 6278 struct hclge_fd_rule *rule) 6279 { 6280 switch (info->layer) { 6281 case HCLGE_FD_USER_DEF_L2: 6282 rule->tuples.l2_user_def = info->data; 6283 rule->tuples_mask.l2_user_def = info->data_mask; 6284 break; 6285 case HCLGE_FD_USER_DEF_L3: 6286 rule->tuples.l3_user_def = info->data; 6287 rule->tuples_mask.l3_user_def = info->data_mask; 6288 break; 6289 case HCLGE_FD_USER_DEF_L4: 6290 rule->tuples.l4_user_def = (u32)info->data << 16; 6291 rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16; 6292 break; 6293 default: 6294 break; 6295 } 6296 6297 rule->ep.user_def = *info; 6298 } 6299 6300 static int hclge_fd_get_tuple(struct ethtool_rx_flow_spec *fs, 6301 struct hclge_fd_rule *rule, 6302 struct hclge_fd_user_def_info *info) 6303 { 6304 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6305 6306 switch (flow_type) { 6307 case SCTP_V4_FLOW: 6308 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_SCTP); 6309 break; 6310 case TCP_V4_FLOW: 6311 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_TCP); 6312 break; 6313 case UDP_V4_FLOW: 6314 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_UDP); 6315 break; 6316 case IP_USER_FLOW: 6317 hclge_fd_get_ip4_tuple(fs, rule); 6318 break; 6319 case SCTP_V6_FLOW: 6320 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_SCTP); 6321 break; 6322 case TCP_V6_FLOW: 6323 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_TCP); 6324 break; 6325 case UDP_V6_FLOW: 6326 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_UDP); 6327 break; 6328 case IPV6_USER_FLOW: 6329 hclge_fd_get_ip6_tuple(fs, rule); 6330 break; 6331 case ETHER_FLOW: 6332 hclge_fd_get_ether_tuple(fs, rule); 6333 break; 6334 default: 6335 return -EOPNOTSUPP; 6336 } 6337 6338 if (fs->flow_type & FLOW_EXT) { 6339 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci); 6340 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci); 6341 hclge_fd_get_user_def_tuple(info, rule); 6342 } 6343 6344 if (fs->flow_type & FLOW_MAC_EXT) { 6345 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest); 6346 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest); 6347 } 6348 6349 return 0; 6350 } 6351 6352 static int hclge_fd_config_rule(struct hclge_dev *hdev, 6353 struct hclge_fd_rule *rule) 6354 { 6355 int ret; 6356 6357 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule); 6358 if (ret) 6359 return ret; 6360 6361 return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule); 6362 } 6363 6364 static int hclge_add_fd_entry_common(struct hclge_dev *hdev, 6365 struct hclge_fd_rule *rule) 6366 { 6367 int ret; 6368 6369 spin_lock_bh(&hdev->fd_rule_lock); 6370 6371 if (hdev->fd_active_type != rule->rule_type && 6372 (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6373 hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) { 6374 dev_err(&hdev->pdev->dev, 6375 "mode conflict(new type %d, active type %d), please delete existent rules first\n", 6376 rule->rule_type, hdev->fd_active_type); 6377 spin_unlock_bh(&hdev->fd_rule_lock); 6378 return -EINVAL; 6379 } 6380 6381 ret = hclge_fd_check_user_def_refcnt(hdev, rule); 6382 if (ret) 6383 goto out; 6384 6385 ret = hclge_clear_arfs_rules(hdev); 6386 if (ret) 6387 goto out; 6388 6389 ret = hclge_fd_config_rule(hdev, rule); 6390 if (ret) 6391 goto out; 6392 6393 rule->state = HCLGE_FD_ACTIVE; 6394 hdev->fd_active_type = rule->rule_type; 6395 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 6396 6397 out: 6398 spin_unlock_bh(&hdev->fd_rule_lock); 6399 return ret; 6400 } 6401 6402 static bool hclge_is_cls_flower_active(struct hnae3_handle *handle) 6403 { 6404 struct hclge_vport *vport = hclge_get_vport(handle); 6405 struct hclge_dev *hdev = vport->back; 6406 6407 return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE; 6408 } 6409 6410 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie, 6411 u16 *vport_id, u8 *action, u16 *queue_id) 6412 { 6413 struct hclge_vport *vport = hdev->vport; 6414 6415 if (ring_cookie == RX_CLS_FLOW_DISC) { 6416 *action = HCLGE_FD_ACTION_DROP_PACKET; 6417 } else { 6418 u32 ring = ethtool_get_flow_spec_ring(ring_cookie); 6419 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie); 6420 u16 tqps; 6421 6422 /* To keep consistent with user's configuration, minus 1 when 6423 * printing 'vf', because vf id from ethtool is added 1 for vf. 6424 */ 6425 if (vf > hdev->num_req_vfs) { 6426 dev_err(&hdev->pdev->dev, 6427 "Error: vf id (%u) should be less than %u\n", 6428 vf - 1U, hdev->num_req_vfs); 6429 return -EINVAL; 6430 } 6431 6432 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id; 6433 tqps = hdev->vport[vf].nic.kinfo.num_tqps; 6434 6435 if (ring >= tqps) { 6436 dev_err(&hdev->pdev->dev, 6437 "Error: queue id (%u) > max tqp num (%u)\n", 6438 ring, tqps - 1U); 6439 return -EINVAL; 6440 } 6441 6442 *action = HCLGE_FD_ACTION_SELECT_QUEUE; 6443 *queue_id = ring; 6444 } 6445 6446 return 0; 6447 } 6448 6449 static int hclge_add_fd_entry(struct hnae3_handle *handle, 6450 struct ethtool_rxnfc *cmd) 6451 { 6452 struct hclge_vport *vport = hclge_get_vport(handle); 6453 struct hclge_dev *hdev = vport->back; 6454 struct hclge_fd_user_def_info info; 6455 u16 dst_vport_id = 0, q_index = 0; 6456 struct ethtool_rx_flow_spec *fs; 6457 struct hclge_fd_rule *rule; 6458 u32 unused = 0; 6459 u8 action; 6460 int ret; 6461 6462 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 6463 dev_err(&hdev->pdev->dev, 6464 "flow table director is not supported\n"); 6465 return -EOPNOTSUPP; 6466 } 6467 6468 if (!hdev->fd_en) { 6469 dev_err(&hdev->pdev->dev, 6470 "please enable flow director first\n"); 6471 return -EOPNOTSUPP; 6472 } 6473 6474 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6475 6476 ret = hclge_fd_check_spec(hdev, fs, &unused, &info); 6477 if (ret) 6478 return ret; 6479 6480 ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id, 6481 &action, &q_index); 6482 if (ret) 6483 return ret; 6484 6485 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 6486 if (!rule) 6487 return -ENOMEM; 6488 6489 ret = hclge_fd_get_tuple(fs, rule, &info); 6490 if (ret) { 6491 kfree(rule); 6492 return ret; 6493 } 6494 6495 rule->flow_type = fs->flow_type; 6496 rule->location = fs->location; 6497 rule->unused_tuple = unused; 6498 rule->vf_id = dst_vport_id; 6499 rule->queue_id = q_index; 6500 rule->action = action; 6501 rule->rule_type = HCLGE_FD_EP_ACTIVE; 6502 6503 ret = hclge_add_fd_entry_common(hdev, rule); 6504 if (ret) 6505 kfree(rule); 6506 6507 return ret; 6508 } 6509 6510 static int hclge_del_fd_entry(struct hnae3_handle *handle, 6511 struct ethtool_rxnfc *cmd) 6512 { 6513 struct hclge_vport *vport = hclge_get_vport(handle); 6514 struct hclge_dev *hdev = vport->back; 6515 struct ethtool_rx_flow_spec *fs; 6516 int ret; 6517 6518 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6519 return -EOPNOTSUPP; 6520 6521 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6522 6523 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6524 return -EINVAL; 6525 6526 spin_lock_bh(&hdev->fd_rule_lock); 6527 if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6528 !test_bit(fs->location, hdev->fd_bmap)) { 6529 dev_err(&hdev->pdev->dev, 6530 "Delete fail, rule %u is inexistent\n", fs->location); 6531 spin_unlock_bh(&hdev->fd_rule_lock); 6532 return -ENOENT; 6533 } 6534 6535 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location, 6536 NULL, false); 6537 if (ret) 6538 goto out; 6539 6540 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL); 6541 6542 out: 6543 spin_unlock_bh(&hdev->fd_rule_lock); 6544 return ret; 6545 } 6546 6547 static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev, 6548 bool clear_list) 6549 { 6550 struct hclge_fd_rule *rule; 6551 struct hlist_node *node; 6552 u16 location; 6553 6554 spin_lock_bh(&hdev->fd_rule_lock); 6555 6556 for_each_set_bit(location, hdev->fd_bmap, 6557 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6558 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location, 6559 NULL, false); 6560 6561 if (clear_list) { 6562 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, 6563 rule_node) { 6564 hlist_del(&rule->rule_node); 6565 kfree(rule); 6566 } 6567 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 6568 hdev->hclge_fd_rule_num = 0; 6569 bitmap_zero(hdev->fd_bmap, 6570 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 6571 } 6572 6573 spin_unlock_bh(&hdev->fd_rule_lock); 6574 } 6575 6576 static void hclge_del_all_fd_entries(struct hclge_dev *hdev) 6577 { 6578 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6579 return; 6580 6581 hclge_clear_fd_rules_in_list(hdev, true); 6582 hclge_fd_disable_user_def(hdev); 6583 } 6584 6585 static int hclge_restore_fd_entries(struct hnae3_handle *handle) 6586 { 6587 struct hclge_vport *vport = hclge_get_vport(handle); 6588 struct hclge_dev *hdev = vport->back; 6589 struct hclge_fd_rule *rule; 6590 struct hlist_node *node; 6591 6592 /* Return ok here, because reset error handling will check this 6593 * return value. If error is returned here, the reset process will 6594 * fail. 6595 */ 6596 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6597 return 0; 6598 6599 /* if fd is disabled, should not restore it when reset */ 6600 if (!hdev->fd_en) 6601 return 0; 6602 6603 spin_lock_bh(&hdev->fd_rule_lock); 6604 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6605 if (rule->state == HCLGE_FD_ACTIVE) 6606 rule->state = HCLGE_FD_TO_ADD; 6607 } 6608 spin_unlock_bh(&hdev->fd_rule_lock); 6609 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 6610 6611 return 0; 6612 } 6613 6614 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle, 6615 struct ethtool_rxnfc *cmd) 6616 { 6617 struct hclge_vport *vport = hclge_get_vport(handle); 6618 struct hclge_dev *hdev = vport->back; 6619 6620 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev) || hclge_is_cls_flower_active(handle)) 6621 return -EOPNOTSUPP; 6622 6623 cmd->rule_cnt = hdev->hclge_fd_rule_num; 6624 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6625 6626 return 0; 6627 } 6628 6629 static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule, 6630 struct ethtool_tcpip4_spec *spec, 6631 struct ethtool_tcpip4_spec *spec_mask) 6632 { 6633 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6634 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6635 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6636 6637 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6638 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6639 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6640 6641 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6642 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6643 0 : cpu_to_be16(rule->tuples_mask.src_port); 6644 6645 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6646 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6647 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6648 6649 spec->tos = rule->tuples.ip_tos; 6650 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6651 0 : rule->tuples_mask.ip_tos; 6652 } 6653 6654 static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule, 6655 struct ethtool_usrip4_spec *spec, 6656 struct ethtool_usrip4_spec *spec_mask) 6657 { 6658 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6659 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6660 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6661 6662 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6663 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6664 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6665 6666 spec->tos = rule->tuples.ip_tos; 6667 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6668 0 : rule->tuples_mask.ip_tos; 6669 6670 spec->proto = rule->tuples.ip_proto; 6671 spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6672 0 : rule->tuples_mask.ip_proto; 6673 6674 spec->ip_ver = ETH_RX_NFC_IP4; 6675 } 6676 6677 static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule, 6678 struct ethtool_tcpip6_spec *spec, 6679 struct ethtool_tcpip6_spec *spec_mask) 6680 { 6681 cpu_to_be32_array(spec->ip6src, 6682 rule->tuples.src_ip, IPV6_SIZE); 6683 cpu_to_be32_array(spec->ip6dst, 6684 rule->tuples.dst_ip, IPV6_SIZE); 6685 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6686 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6687 else 6688 cpu_to_be32_array(spec_mask->ip6src, rule->tuples_mask.src_ip, 6689 IPV6_SIZE); 6690 6691 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6692 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6693 else 6694 cpu_to_be32_array(spec_mask->ip6dst, rule->tuples_mask.dst_ip, 6695 IPV6_SIZE); 6696 6697 spec->tclass = rule->tuples.ip_tos; 6698 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6699 0 : rule->tuples_mask.ip_tos; 6700 6701 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6702 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6703 0 : cpu_to_be16(rule->tuples_mask.src_port); 6704 6705 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6706 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6707 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6708 } 6709 6710 static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule, 6711 struct ethtool_usrip6_spec *spec, 6712 struct ethtool_usrip6_spec *spec_mask) 6713 { 6714 cpu_to_be32_array(spec->ip6src, rule->tuples.src_ip, IPV6_SIZE); 6715 cpu_to_be32_array(spec->ip6dst, rule->tuples.dst_ip, IPV6_SIZE); 6716 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6717 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6718 else 6719 cpu_to_be32_array(spec_mask->ip6src, 6720 rule->tuples_mask.src_ip, IPV6_SIZE); 6721 6722 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6723 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6724 else 6725 cpu_to_be32_array(spec_mask->ip6dst, 6726 rule->tuples_mask.dst_ip, IPV6_SIZE); 6727 6728 spec->tclass = rule->tuples.ip_tos; 6729 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6730 0 : rule->tuples_mask.ip_tos; 6731 6732 spec->l4_proto = rule->tuples.ip_proto; 6733 spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6734 0 : rule->tuples_mask.ip_proto; 6735 } 6736 6737 static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule, 6738 struct ethhdr *spec, 6739 struct ethhdr *spec_mask) 6740 { 6741 ether_addr_copy(spec->h_source, rule->tuples.src_mac); 6742 ether_addr_copy(spec->h_dest, rule->tuples.dst_mac); 6743 6744 if (rule->unused_tuple & BIT(INNER_SRC_MAC)) 6745 eth_zero_addr(spec_mask->h_source); 6746 else 6747 ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac); 6748 6749 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6750 eth_zero_addr(spec_mask->h_dest); 6751 else 6752 ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac); 6753 6754 spec->h_proto = cpu_to_be16(rule->tuples.ether_proto); 6755 spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ? 6756 0 : cpu_to_be16(rule->tuples_mask.ether_proto); 6757 } 6758 6759 static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs, 6760 struct hclge_fd_rule *rule) 6761 { 6762 if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) == 6763 HCLGE_FD_TUPLE_USER_DEF_TUPLES) { 6764 fs->h_ext.data[0] = 0; 6765 fs->h_ext.data[1] = 0; 6766 fs->m_ext.data[0] = 0; 6767 fs->m_ext.data[1] = 0; 6768 } else { 6769 fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset); 6770 fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data); 6771 fs->m_ext.data[0] = 6772 cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK); 6773 fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask); 6774 } 6775 } 6776 6777 static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs, 6778 struct hclge_fd_rule *rule) 6779 { 6780 if (fs->flow_type & FLOW_EXT) { 6781 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1); 6782 fs->m_ext.vlan_tci = 6783 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ? 6784 0 : cpu_to_be16(rule->tuples_mask.vlan_tag1); 6785 6786 hclge_fd_get_user_def_info(fs, rule); 6787 } 6788 6789 if (fs->flow_type & FLOW_MAC_EXT) { 6790 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac); 6791 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6792 eth_zero_addr(fs->m_u.ether_spec.h_dest); 6793 else 6794 ether_addr_copy(fs->m_u.ether_spec.h_dest, 6795 rule->tuples_mask.dst_mac); 6796 } 6797 } 6798 6799 static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev, 6800 u16 location) 6801 { 6802 struct hclge_fd_rule *rule = NULL; 6803 struct hlist_node *node2; 6804 6805 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) { 6806 if (rule->location == location) 6807 return rule; 6808 else if (rule->location > location) 6809 return NULL; 6810 } 6811 6812 return NULL; 6813 } 6814 6815 static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs, 6816 struct hclge_fd_rule *rule) 6817 { 6818 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 6819 fs->ring_cookie = RX_CLS_FLOW_DISC; 6820 } else { 6821 u64 vf_id; 6822 6823 fs->ring_cookie = rule->queue_id; 6824 vf_id = rule->vf_id; 6825 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 6826 fs->ring_cookie |= vf_id; 6827 } 6828 } 6829 6830 static int hclge_get_fd_rule_info(struct hnae3_handle *handle, 6831 struct ethtool_rxnfc *cmd) 6832 { 6833 struct hclge_vport *vport = hclge_get_vport(handle); 6834 struct hclge_fd_rule *rule = NULL; 6835 struct hclge_dev *hdev = vport->back; 6836 struct ethtool_rx_flow_spec *fs; 6837 6838 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6839 return -EOPNOTSUPP; 6840 6841 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6842 6843 spin_lock_bh(&hdev->fd_rule_lock); 6844 6845 rule = hclge_get_fd_rule(hdev, fs->location); 6846 if (!rule) { 6847 spin_unlock_bh(&hdev->fd_rule_lock); 6848 return -ENOENT; 6849 } 6850 6851 fs->flow_type = rule->flow_type; 6852 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 6853 case SCTP_V4_FLOW: 6854 case TCP_V4_FLOW: 6855 case UDP_V4_FLOW: 6856 hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec, 6857 &fs->m_u.tcp_ip4_spec); 6858 break; 6859 case IP_USER_FLOW: 6860 hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec, 6861 &fs->m_u.usr_ip4_spec); 6862 break; 6863 case SCTP_V6_FLOW: 6864 case TCP_V6_FLOW: 6865 case UDP_V6_FLOW: 6866 hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec, 6867 &fs->m_u.tcp_ip6_spec); 6868 break; 6869 case IPV6_USER_FLOW: 6870 hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec, 6871 &fs->m_u.usr_ip6_spec); 6872 break; 6873 /* The flow type of fd rule has been checked before adding in to rule 6874 * list. As other flow types have been handled, it must be ETHER_FLOW 6875 * for the default case 6876 */ 6877 default: 6878 hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec, 6879 &fs->m_u.ether_spec); 6880 break; 6881 } 6882 6883 hclge_fd_get_ext_info(fs, rule); 6884 6885 hclge_fd_get_ring_cookie(fs, rule); 6886 6887 spin_unlock_bh(&hdev->fd_rule_lock); 6888 6889 return 0; 6890 } 6891 6892 static int hclge_get_all_rules(struct hnae3_handle *handle, 6893 struct ethtool_rxnfc *cmd, u32 *rule_locs) 6894 { 6895 struct hclge_vport *vport = hclge_get_vport(handle); 6896 struct hclge_dev *hdev = vport->back; 6897 struct hclge_fd_rule *rule; 6898 struct hlist_node *node2; 6899 int cnt = 0; 6900 6901 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6902 return -EOPNOTSUPP; 6903 6904 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6905 6906 spin_lock_bh(&hdev->fd_rule_lock); 6907 hlist_for_each_entry_safe(rule, node2, 6908 &hdev->fd_rule_list, rule_node) { 6909 if (cnt == cmd->rule_cnt) { 6910 spin_unlock_bh(&hdev->fd_rule_lock); 6911 return -EMSGSIZE; 6912 } 6913 6914 if (rule->state == HCLGE_FD_TO_DEL) 6915 continue; 6916 6917 rule_locs[cnt] = rule->location; 6918 cnt++; 6919 } 6920 6921 spin_unlock_bh(&hdev->fd_rule_lock); 6922 6923 cmd->rule_cnt = cnt; 6924 6925 return 0; 6926 } 6927 6928 static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys, 6929 struct hclge_fd_rule_tuples *tuples) 6930 { 6931 #define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32 6932 #define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32 6933 6934 tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto); 6935 tuples->ip_proto = fkeys->basic.ip_proto; 6936 tuples->dst_port = be16_to_cpu(fkeys->ports.dst); 6937 6938 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 6939 tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src); 6940 tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst); 6941 } else { 6942 int i; 6943 6944 for (i = 0; i < IPV6_SIZE; i++) { 6945 tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]); 6946 tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]); 6947 } 6948 } 6949 } 6950 6951 /* traverse all rules, check whether an existed rule has the same tuples */ 6952 static struct hclge_fd_rule * 6953 hclge_fd_search_flow_keys(struct hclge_dev *hdev, 6954 const struct hclge_fd_rule_tuples *tuples) 6955 { 6956 struct hclge_fd_rule *rule = NULL; 6957 struct hlist_node *node; 6958 6959 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6960 if (!memcmp(tuples, &rule->tuples, sizeof(*tuples))) 6961 return rule; 6962 } 6963 6964 return NULL; 6965 } 6966 6967 static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples, 6968 struct hclge_fd_rule *rule) 6969 { 6970 rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 6971 BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) | 6972 BIT(INNER_SRC_PORT); 6973 rule->action = 0; 6974 rule->vf_id = 0; 6975 rule->rule_type = HCLGE_FD_ARFS_ACTIVE; 6976 rule->state = HCLGE_FD_TO_ADD; 6977 if (tuples->ether_proto == ETH_P_IP) { 6978 if (tuples->ip_proto == IPPROTO_TCP) 6979 rule->flow_type = TCP_V4_FLOW; 6980 else 6981 rule->flow_type = UDP_V4_FLOW; 6982 } else { 6983 if (tuples->ip_proto == IPPROTO_TCP) 6984 rule->flow_type = TCP_V6_FLOW; 6985 else 6986 rule->flow_type = UDP_V6_FLOW; 6987 } 6988 memcpy(&rule->tuples, tuples, sizeof(rule->tuples)); 6989 memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask)); 6990 } 6991 6992 static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id, 6993 u16 flow_id, struct flow_keys *fkeys) 6994 { 6995 struct hclge_vport *vport = hclge_get_vport(handle); 6996 struct hclge_fd_rule_tuples new_tuples = {}; 6997 struct hclge_dev *hdev = vport->back; 6998 struct hclge_fd_rule *rule; 6999 u16 bit_id; 7000 7001 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7002 return -EOPNOTSUPP; 7003 7004 /* when there is already fd rule existed add by user, 7005 * arfs should not work 7006 */ 7007 spin_lock_bh(&hdev->fd_rule_lock); 7008 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE && 7009 hdev->fd_active_type != HCLGE_FD_RULE_NONE) { 7010 spin_unlock_bh(&hdev->fd_rule_lock); 7011 return -EOPNOTSUPP; 7012 } 7013 7014 hclge_fd_get_flow_tuples(fkeys, &new_tuples); 7015 7016 /* check is there flow director filter existed for this flow, 7017 * if not, create a new filter for it; 7018 * if filter exist with different queue id, modify the filter; 7019 * if filter exist with same queue id, do nothing 7020 */ 7021 rule = hclge_fd_search_flow_keys(hdev, &new_tuples); 7022 if (!rule) { 7023 bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM); 7024 if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7025 spin_unlock_bh(&hdev->fd_rule_lock); 7026 return -ENOSPC; 7027 } 7028 7029 rule = kzalloc(sizeof(*rule), GFP_ATOMIC); 7030 if (!rule) { 7031 spin_unlock_bh(&hdev->fd_rule_lock); 7032 return -ENOMEM; 7033 } 7034 7035 rule->location = bit_id; 7036 rule->arfs.flow_id = flow_id; 7037 rule->queue_id = queue_id; 7038 hclge_fd_build_arfs_rule(&new_tuples, rule); 7039 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 7040 hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE; 7041 } else if (rule->queue_id != queue_id) { 7042 rule->queue_id = queue_id; 7043 rule->state = HCLGE_FD_TO_ADD; 7044 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7045 hclge_task_schedule(hdev, 0); 7046 } 7047 spin_unlock_bh(&hdev->fd_rule_lock); 7048 return rule->location; 7049 } 7050 7051 static void hclge_rfs_filter_expire(struct hclge_dev *hdev) 7052 { 7053 #ifdef CONFIG_RFS_ACCEL 7054 struct hnae3_handle *handle = &hdev->vport[0].nic; 7055 struct hclge_fd_rule *rule; 7056 struct hlist_node *node; 7057 7058 spin_lock_bh(&hdev->fd_rule_lock); 7059 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) { 7060 spin_unlock_bh(&hdev->fd_rule_lock); 7061 return; 7062 } 7063 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7064 if (rule->state != HCLGE_FD_ACTIVE) 7065 continue; 7066 if (rps_may_expire_flow(handle->netdev, rule->queue_id, 7067 rule->arfs.flow_id, rule->location)) { 7068 rule->state = HCLGE_FD_TO_DEL; 7069 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7070 } 7071 } 7072 spin_unlock_bh(&hdev->fd_rule_lock); 7073 #endif 7074 } 7075 7076 /* make sure being called after lock up with fd_rule_lock */ 7077 static int hclge_clear_arfs_rules(struct hclge_dev *hdev) 7078 { 7079 #ifdef CONFIG_RFS_ACCEL 7080 struct hclge_fd_rule *rule; 7081 struct hlist_node *node; 7082 int ret; 7083 7084 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) 7085 return 0; 7086 7087 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7088 switch (rule->state) { 7089 case HCLGE_FD_TO_DEL: 7090 case HCLGE_FD_ACTIVE: 7091 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7092 rule->location, NULL, false); 7093 if (ret) 7094 return ret; 7095 fallthrough; 7096 case HCLGE_FD_TO_ADD: 7097 hclge_fd_dec_rule_cnt(hdev, rule->location); 7098 hlist_del(&rule->rule_node); 7099 kfree(rule); 7100 break; 7101 default: 7102 break; 7103 } 7104 } 7105 hclge_sync_fd_state(hdev); 7106 7107 #endif 7108 return 0; 7109 } 7110 7111 static void hclge_get_cls_key_basic(const struct flow_rule *flow, 7112 struct hclge_fd_rule *rule) 7113 { 7114 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) { 7115 struct flow_match_basic match; 7116 u16 ethtype_key, ethtype_mask; 7117 7118 flow_rule_match_basic(flow, &match); 7119 ethtype_key = ntohs(match.key->n_proto); 7120 ethtype_mask = ntohs(match.mask->n_proto); 7121 7122 if (ethtype_key == ETH_P_ALL) { 7123 ethtype_key = 0; 7124 ethtype_mask = 0; 7125 } 7126 rule->tuples.ether_proto = ethtype_key; 7127 rule->tuples_mask.ether_proto = ethtype_mask; 7128 rule->tuples.ip_proto = match.key->ip_proto; 7129 rule->tuples_mask.ip_proto = match.mask->ip_proto; 7130 } else { 7131 rule->unused_tuple |= BIT(INNER_IP_PROTO); 7132 rule->unused_tuple |= BIT(INNER_ETH_TYPE); 7133 } 7134 } 7135 7136 static void hclge_get_cls_key_mac(const struct flow_rule *flow, 7137 struct hclge_fd_rule *rule) 7138 { 7139 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 7140 struct flow_match_eth_addrs match; 7141 7142 flow_rule_match_eth_addrs(flow, &match); 7143 ether_addr_copy(rule->tuples.dst_mac, match.key->dst); 7144 ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst); 7145 ether_addr_copy(rule->tuples.src_mac, match.key->src); 7146 ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src); 7147 } else { 7148 rule->unused_tuple |= BIT(INNER_DST_MAC); 7149 rule->unused_tuple |= BIT(INNER_SRC_MAC); 7150 } 7151 } 7152 7153 static void hclge_get_cls_key_vlan(const struct flow_rule *flow, 7154 struct hclge_fd_rule *rule) 7155 { 7156 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) { 7157 struct flow_match_vlan match; 7158 7159 flow_rule_match_vlan(flow, &match); 7160 rule->tuples.vlan_tag1 = match.key->vlan_id | 7161 (match.key->vlan_priority << VLAN_PRIO_SHIFT); 7162 rule->tuples_mask.vlan_tag1 = match.mask->vlan_id | 7163 (match.mask->vlan_priority << VLAN_PRIO_SHIFT); 7164 } else { 7165 rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST); 7166 } 7167 } 7168 7169 static void hclge_get_cls_key_ip(const struct flow_rule *flow, 7170 struct hclge_fd_rule *rule) 7171 { 7172 u16 addr_type = 0; 7173 7174 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) { 7175 struct flow_match_control match; 7176 7177 flow_rule_match_control(flow, &match); 7178 addr_type = match.key->addr_type; 7179 } 7180 7181 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { 7182 struct flow_match_ipv4_addrs match; 7183 7184 flow_rule_match_ipv4_addrs(flow, &match); 7185 rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src); 7186 rule->tuples_mask.src_ip[IPV4_INDEX] = 7187 be32_to_cpu(match.mask->src); 7188 rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst); 7189 rule->tuples_mask.dst_ip[IPV4_INDEX] = 7190 be32_to_cpu(match.mask->dst); 7191 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { 7192 struct flow_match_ipv6_addrs match; 7193 7194 flow_rule_match_ipv6_addrs(flow, &match); 7195 be32_to_cpu_array(rule->tuples.src_ip, match.key->src.s6_addr32, 7196 IPV6_SIZE); 7197 be32_to_cpu_array(rule->tuples_mask.src_ip, 7198 match.mask->src.s6_addr32, IPV6_SIZE); 7199 be32_to_cpu_array(rule->tuples.dst_ip, match.key->dst.s6_addr32, 7200 IPV6_SIZE); 7201 be32_to_cpu_array(rule->tuples_mask.dst_ip, 7202 match.mask->dst.s6_addr32, IPV6_SIZE); 7203 } else { 7204 rule->unused_tuple |= BIT(INNER_SRC_IP); 7205 rule->unused_tuple |= BIT(INNER_DST_IP); 7206 } 7207 } 7208 7209 static void hclge_get_cls_key_port(const struct flow_rule *flow, 7210 struct hclge_fd_rule *rule) 7211 { 7212 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) { 7213 struct flow_match_ports match; 7214 7215 flow_rule_match_ports(flow, &match); 7216 7217 rule->tuples.src_port = be16_to_cpu(match.key->src); 7218 rule->tuples_mask.src_port = be16_to_cpu(match.mask->src); 7219 rule->tuples.dst_port = be16_to_cpu(match.key->dst); 7220 rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst); 7221 } else { 7222 rule->unused_tuple |= BIT(INNER_SRC_PORT); 7223 rule->unused_tuple |= BIT(INNER_DST_PORT); 7224 } 7225 } 7226 7227 static int hclge_parse_cls_flower(struct hclge_dev *hdev, 7228 struct flow_cls_offload *cls_flower, 7229 struct hclge_fd_rule *rule) 7230 { 7231 struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower); 7232 struct flow_dissector *dissector = flow->match.dissector; 7233 7234 if (dissector->used_keys & 7235 ~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 7236 BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 7237 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 7238 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) | 7239 BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | 7240 BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | 7241 BIT_ULL(FLOW_DISSECTOR_KEY_PORTS))) { 7242 dev_err(&hdev->pdev->dev, "unsupported key set: %#llx\n", 7243 dissector->used_keys); 7244 return -EOPNOTSUPP; 7245 } 7246 7247 hclge_get_cls_key_basic(flow, rule); 7248 hclge_get_cls_key_mac(flow, rule); 7249 hclge_get_cls_key_vlan(flow, rule); 7250 hclge_get_cls_key_ip(flow, rule); 7251 hclge_get_cls_key_port(flow, rule); 7252 7253 return 0; 7254 } 7255 7256 static int hclge_check_cls_flower(struct hclge_dev *hdev, 7257 struct flow_cls_offload *cls_flower, int tc) 7258 { 7259 u32 prio = cls_flower->common.prio; 7260 7261 if (tc < 0 || tc > hdev->tc_max) { 7262 dev_err(&hdev->pdev->dev, "invalid traffic class\n"); 7263 return -EINVAL; 7264 } 7265 7266 if (prio == 0 || 7267 prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7268 dev_err(&hdev->pdev->dev, 7269 "prio %u should be in range[1, %u]\n", 7270 prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 7271 return -EINVAL; 7272 } 7273 7274 if (test_bit(prio - 1, hdev->fd_bmap)) { 7275 dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio); 7276 return -EINVAL; 7277 } 7278 return 0; 7279 } 7280 7281 static int hclge_add_cls_flower(struct hnae3_handle *handle, 7282 struct flow_cls_offload *cls_flower, 7283 int tc) 7284 { 7285 struct hclge_vport *vport = hclge_get_vport(handle); 7286 struct hclge_dev *hdev = vport->back; 7287 struct hclge_fd_rule *rule; 7288 int ret; 7289 7290 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 7291 dev_err(&hdev->pdev->dev, 7292 "cls flower is not supported\n"); 7293 return -EOPNOTSUPP; 7294 } 7295 7296 ret = hclge_check_cls_flower(hdev, cls_flower, tc); 7297 if (ret) { 7298 dev_err(&hdev->pdev->dev, 7299 "failed to check cls flower params, ret = %d\n", ret); 7300 return ret; 7301 } 7302 7303 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 7304 if (!rule) 7305 return -ENOMEM; 7306 7307 ret = hclge_parse_cls_flower(hdev, cls_flower, rule); 7308 if (ret) { 7309 kfree(rule); 7310 return ret; 7311 } 7312 7313 rule->action = HCLGE_FD_ACTION_SELECT_TC; 7314 rule->cls_flower.tc = tc; 7315 rule->location = cls_flower->common.prio - 1; 7316 rule->vf_id = 0; 7317 rule->cls_flower.cookie = cls_flower->cookie; 7318 rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE; 7319 7320 ret = hclge_add_fd_entry_common(hdev, rule); 7321 if (ret) 7322 kfree(rule); 7323 7324 return ret; 7325 } 7326 7327 static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev, 7328 unsigned long cookie) 7329 { 7330 struct hclge_fd_rule *rule; 7331 struct hlist_node *node; 7332 7333 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7334 if (rule->cls_flower.cookie == cookie) 7335 return rule; 7336 } 7337 7338 return NULL; 7339 } 7340 7341 static int hclge_del_cls_flower(struct hnae3_handle *handle, 7342 struct flow_cls_offload *cls_flower) 7343 { 7344 struct hclge_vport *vport = hclge_get_vport(handle); 7345 struct hclge_dev *hdev = vport->back; 7346 struct hclge_fd_rule *rule; 7347 int ret; 7348 7349 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7350 return -EOPNOTSUPP; 7351 7352 spin_lock_bh(&hdev->fd_rule_lock); 7353 7354 rule = hclge_find_cls_flower(hdev, cls_flower->cookie); 7355 if (!rule) { 7356 spin_unlock_bh(&hdev->fd_rule_lock); 7357 return -EINVAL; 7358 } 7359 7360 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location, 7361 NULL, false); 7362 if (ret) { 7363 /* if tcam config fail, set rule state to TO_DEL, 7364 * so the rule will be deleted when periodic 7365 * task being scheduled. 7366 */ 7367 hclge_update_fd_list(hdev, HCLGE_FD_TO_DEL, rule->location, NULL); 7368 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7369 spin_unlock_bh(&hdev->fd_rule_lock); 7370 return ret; 7371 } 7372 7373 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL); 7374 spin_unlock_bh(&hdev->fd_rule_lock); 7375 7376 return 0; 7377 } 7378 7379 static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist) 7380 { 7381 struct hclge_fd_rule *rule; 7382 struct hlist_node *node; 7383 int ret = 0; 7384 7385 if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state)) 7386 return; 7387 7388 spin_lock_bh(&hdev->fd_rule_lock); 7389 7390 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 7391 switch (rule->state) { 7392 case HCLGE_FD_TO_ADD: 7393 ret = hclge_fd_config_rule(hdev, rule); 7394 if (ret) 7395 goto out; 7396 rule->state = HCLGE_FD_ACTIVE; 7397 break; 7398 case HCLGE_FD_TO_DEL: 7399 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7400 rule->location, NULL, false); 7401 if (ret) 7402 goto out; 7403 hclge_fd_dec_rule_cnt(hdev, rule->location); 7404 hclge_fd_free_node(hdev, rule); 7405 break; 7406 default: 7407 break; 7408 } 7409 } 7410 7411 out: 7412 if (ret) 7413 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7414 7415 spin_unlock_bh(&hdev->fd_rule_lock); 7416 } 7417 7418 static void hclge_sync_fd_table(struct hclge_dev *hdev) 7419 { 7420 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7421 return; 7422 7423 if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) { 7424 bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE; 7425 7426 hclge_clear_fd_rules_in_list(hdev, clear_list); 7427 } 7428 7429 hclge_sync_fd_user_def_cfg(hdev, false); 7430 7431 hclge_sync_fd_list(hdev, &hdev->fd_rule_list); 7432 } 7433 7434 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle) 7435 { 7436 struct hclge_vport *vport = hclge_get_vport(handle); 7437 struct hclge_dev *hdev = vport->back; 7438 7439 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) || 7440 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING); 7441 } 7442 7443 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle) 7444 { 7445 struct hclge_vport *vport = hclge_get_vport(handle); 7446 struct hclge_dev *hdev = vport->back; 7447 7448 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 7449 } 7450 7451 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle) 7452 { 7453 struct hclge_vport *vport = hclge_get_vport(handle); 7454 struct hclge_dev *hdev = vport->back; 7455 7456 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 7457 } 7458 7459 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle) 7460 { 7461 struct hclge_vport *vport = hclge_get_vport(handle); 7462 struct hclge_dev *hdev = vport->back; 7463 7464 return hdev->rst_stats.hw_reset_done_cnt; 7465 } 7466 7467 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable) 7468 { 7469 struct hclge_vport *vport = hclge_get_vport(handle); 7470 struct hclge_dev *hdev = vport->back; 7471 7472 hdev->fd_en = enable; 7473 7474 if (!enable) 7475 set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state); 7476 else 7477 hclge_restore_fd_entries(handle); 7478 7479 hclge_task_schedule(hdev, 0); 7480 } 7481 7482 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 7483 { 7484 #define HCLGE_LINK_STATUS_WAIT_CNT 3 7485 7486 struct hclge_desc desc; 7487 struct hclge_config_mac_mode_cmd *req = 7488 (struct hclge_config_mac_mode_cmd *)desc.data; 7489 u32 loop_en = 0; 7490 int ret; 7491 7492 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 7493 7494 if (enable) { 7495 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U); 7496 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U); 7497 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U); 7498 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U); 7499 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U); 7500 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U); 7501 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U); 7502 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U); 7503 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U); 7504 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U); 7505 } 7506 7507 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7508 7509 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7510 if (ret) { 7511 dev_err(&hdev->pdev->dev, 7512 "mac enable fail, ret =%d.\n", ret); 7513 return; 7514 } 7515 7516 if (!enable) 7517 hclge_mac_link_status_wait(hdev, HCLGE_LINK_STATUS_DOWN, 7518 HCLGE_LINK_STATUS_WAIT_CNT); 7519 } 7520 7521 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid, 7522 u8 switch_param, u8 param_mask) 7523 { 7524 struct hclge_mac_vlan_switch_cmd *req; 7525 struct hclge_desc desc; 7526 u32 func_id; 7527 int ret; 7528 7529 func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0); 7530 req = (struct hclge_mac_vlan_switch_cmd *)desc.data; 7531 7532 /* read current config parameter */ 7533 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM, 7534 true); 7535 req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL; 7536 req->func_id = cpu_to_le32(func_id); 7537 7538 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7539 if (ret) { 7540 dev_err(&hdev->pdev->dev, 7541 "read mac vlan switch parameter fail, ret = %d\n", ret); 7542 return ret; 7543 } 7544 7545 /* modify and write new config parameter */ 7546 hclge_comm_cmd_reuse_desc(&desc, false); 7547 req->switch_param = (req->switch_param & param_mask) | switch_param; 7548 req->param_mask = param_mask; 7549 7550 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7551 if (ret) 7552 dev_err(&hdev->pdev->dev, 7553 "set mac vlan switch parameter fail, ret = %d\n", ret); 7554 return ret; 7555 } 7556 7557 static void hclge_phy_link_status_wait(struct hclge_dev *hdev, 7558 int link_ret) 7559 { 7560 #define HCLGE_PHY_LINK_STATUS_NUM 200 7561 7562 struct phy_device *phydev = hdev->hw.mac.phydev; 7563 int i = 0; 7564 int ret; 7565 7566 do { 7567 ret = phy_read_status(phydev); 7568 if (ret) { 7569 dev_err(&hdev->pdev->dev, 7570 "phy update link status fail, ret = %d\n", ret); 7571 return; 7572 } 7573 7574 if (phydev->link == link_ret) 7575 break; 7576 7577 msleep(HCLGE_LINK_STATUS_MS); 7578 } while (++i < HCLGE_PHY_LINK_STATUS_NUM); 7579 } 7580 7581 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 7582 int wait_cnt) 7583 { 7584 int link_status; 7585 int i = 0; 7586 int ret; 7587 7588 do { 7589 ret = hclge_get_mac_link_status(hdev, &link_status); 7590 if (ret) 7591 return ret; 7592 if (link_status == link_ret) 7593 return 0; 7594 7595 msleep(HCLGE_LINK_STATUS_MS); 7596 } while (++i < wait_cnt); 7597 return -EBUSY; 7598 } 7599 7600 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en, 7601 bool is_phy) 7602 { 7603 #define HCLGE_MAC_LINK_STATUS_NUM 100 7604 7605 int link_ret; 7606 7607 link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 7608 7609 if (is_phy) 7610 hclge_phy_link_status_wait(hdev, link_ret); 7611 7612 return hclge_mac_link_status_wait(hdev, link_ret, 7613 HCLGE_MAC_LINK_STATUS_NUM); 7614 } 7615 7616 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) 7617 { 7618 struct hclge_config_mac_mode_cmd *req; 7619 struct hclge_desc desc; 7620 u32 loop_en; 7621 int ret; 7622 7623 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 7624 /* 1 Read out the MAC mode config at first */ 7625 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 7626 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7627 if (ret) { 7628 dev_err(&hdev->pdev->dev, 7629 "mac loopback get fail, ret =%d.\n", ret); 7630 return ret; 7631 } 7632 7633 /* 2 Then setup the loopback flag */ 7634 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 7635 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 7636 7637 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7638 7639 /* 3 Config mac work mode with loopback flag 7640 * and its original configure parameters 7641 */ 7642 hclge_comm_cmd_reuse_desc(&desc, false); 7643 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7644 if (ret) 7645 dev_err(&hdev->pdev->dev, 7646 "mac loopback set fail, ret =%d.\n", ret); 7647 return ret; 7648 } 7649 7650 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en, 7651 enum hnae3_loop loop_mode) 7652 { 7653 struct hclge_common_lb_cmd *req; 7654 struct hclge_desc desc; 7655 u8 loop_mode_b; 7656 int ret; 7657 7658 req = (struct hclge_common_lb_cmd *)desc.data; 7659 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false); 7660 7661 switch (loop_mode) { 7662 case HNAE3_LOOP_SERIAL_SERDES: 7663 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 7664 break; 7665 case HNAE3_LOOP_PARALLEL_SERDES: 7666 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B; 7667 break; 7668 case HNAE3_LOOP_PHY: 7669 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B; 7670 break; 7671 default: 7672 dev_err(&hdev->pdev->dev, 7673 "unsupported loopback mode %d\n", loop_mode); 7674 return -ENOTSUPP; 7675 } 7676 7677 req->mask = loop_mode_b; 7678 if (en) 7679 req->enable = loop_mode_b; 7680 7681 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7682 if (ret) 7683 dev_err(&hdev->pdev->dev, 7684 "failed to send loopback cmd, loop_mode = %d, ret = %d\n", 7685 loop_mode, ret); 7686 7687 return ret; 7688 } 7689 7690 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev) 7691 { 7692 #define HCLGE_COMMON_LB_RETRY_MS 10 7693 #define HCLGE_COMMON_LB_RETRY_NUM 100 7694 7695 struct hclge_common_lb_cmd *req; 7696 struct hclge_desc desc; 7697 u32 i = 0; 7698 int ret; 7699 7700 req = (struct hclge_common_lb_cmd *)desc.data; 7701 7702 do { 7703 msleep(HCLGE_COMMON_LB_RETRY_MS); 7704 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, 7705 true); 7706 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7707 if (ret) { 7708 dev_err(&hdev->pdev->dev, 7709 "failed to get loopback done status, ret = %d\n", 7710 ret); 7711 return ret; 7712 } 7713 } while (++i < HCLGE_COMMON_LB_RETRY_NUM && 7714 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B)); 7715 7716 if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) { 7717 dev_err(&hdev->pdev->dev, "wait loopback timeout\n"); 7718 return -EBUSY; 7719 } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) { 7720 dev_err(&hdev->pdev->dev, "failed to do loopback test\n"); 7721 return -EIO; 7722 } 7723 7724 return 0; 7725 } 7726 7727 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en, 7728 enum hnae3_loop loop_mode) 7729 { 7730 int ret; 7731 7732 ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode); 7733 if (ret) 7734 return ret; 7735 7736 return hclge_cfg_common_loopback_wait(hdev); 7737 } 7738 7739 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en, 7740 enum hnae3_loop loop_mode) 7741 { 7742 int ret; 7743 7744 ret = hclge_cfg_common_loopback(hdev, en, loop_mode); 7745 if (ret) 7746 return ret; 7747 7748 hclge_cfg_mac_mode(hdev, en); 7749 7750 ret = hclge_mac_phy_link_status_wait(hdev, en, false); 7751 if (ret) 7752 dev_err(&hdev->pdev->dev, 7753 "serdes loopback config mac mode timeout\n"); 7754 7755 return ret; 7756 } 7757 7758 static int hclge_enable_phy_loopback(struct hclge_dev *hdev, 7759 struct phy_device *phydev) 7760 { 7761 int ret; 7762 7763 if (!phydev->suspended) { 7764 ret = phy_suspend(phydev); 7765 if (ret) 7766 return ret; 7767 } 7768 7769 ret = phy_resume(phydev); 7770 if (ret) 7771 return ret; 7772 7773 return phy_loopback(phydev, true); 7774 } 7775 7776 static int hclge_disable_phy_loopback(struct hclge_dev *hdev, 7777 struct phy_device *phydev) 7778 { 7779 int ret; 7780 7781 ret = phy_loopback(phydev, false); 7782 if (ret) 7783 return ret; 7784 7785 return phy_suspend(phydev); 7786 } 7787 7788 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en) 7789 { 7790 struct phy_device *phydev = hdev->hw.mac.phydev; 7791 int ret; 7792 7793 if (!phydev) { 7794 if (hnae3_dev_phy_imp_supported(hdev)) 7795 return hclge_set_common_loopback(hdev, en, 7796 HNAE3_LOOP_PHY); 7797 return -ENOTSUPP; 7798 } 7799 7800 if (en) 7801 ret = hclge_enable_phy_loopback(hdev, phydev); 7802 else 7803 ret = hclge_disable_phy_loopback(hdev, phydev); 7804 if (ret) { 7805 dev_err(&hdev->pdev->dev, 7806 "set phy loopback fail, ret = %d\n", ret); 7807 return ret; 7808 } 7809 7810 hclge_cfg_mac_mode(hdev, en); 7811 7812 ret = hclge_mac_phy_link_status_wait(hdev, en, true); 7813 if (ret) 7814 dev_err(&hdev->pdev->dev, 7815 "phy loopback config mac mode timeout\n"); 7816 7817 return ret; 7818 } 7819 7820 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id, 7821 u16 stream_id, bool enable) 7822 { 7823 struct hclge_desc desc; 7824 struct hclge_cfg_com_tqp_queue_cmd *req = 7825 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 7826 7827 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 7828 req->tqp_id = cpu_to_le16(tqp_id); 7829 req->stream_id = cpu_to_le16(stream_id); 7830 if (enable) 7831 req->enable |= 1U << HCLGE_TQP_ENABLE_B; 7832 7833 return hclge_cmd_send(&hdev->hw, &desc, 1); 7834 } 7835 7836 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable) 7837 { 7838 struct hclge_vport *vport = hclge_get_vport(handle); 7839 struct hclge_dev *hdev = vport->back; 7840 int ret; 7841 u16 i; 7842 7843 for (i = 0; i < handle->kinfo.num_tqps; i++) { 7844 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable); 7845 if (ret) 7846 return ret; 7847 } 7848 return 0; 7849 } 7850 7851 static int hclge_set_loopback(struct hnae3_handle *handle, 7852 enum hnae3_loop loop_mode, bool en) 7853 { 7854 struct hclge_vport *vport = hclge_get_vport(handle); 7855 struct hclge_dev *hdev = vport->back; 7856 int ret = 0; 7857 7858 /* Loopback can be enabled in three places: SSU, MAC, and serdes. By 7859 * default, SSU loopback is enabled, so if the SMAC and the DMAC are 7860 * the same, the packets are looped back in the SSU. If SSU loopback 7861 * is disabled, packets can reach MAC even if SMAC is the same as DMAC. 7862 */ 7863 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 7864 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B); 7865 7866 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param, 7867 HCLGE_SWITCH_ALW_LPBK_MASK); 7868 if (ret) 7869 return ret; 7870 } 7871 7872 switch (loop_mode) { 7873 case HNAE3_LOOP_APP: 7874 ret = hclge_set_app_loopback(hdev, en); 7875 break; 7876 case HNAE3_LOOP_SERIAL_SERDES: 7877 case HNAE3_LOOP_PARALLEL_SERDES: 7878 ret = hclge_set_common_loopback(hdev, en, loop_mode); 7879 break; 7880 case HNAE3_LOOP_PHY: 7881 ret = hclge_set_phy_loopback(hdev, en); 7882 break; 7883 case HNAE3_LOOP_EXTERNAL: 7884 break; 7885 default: 7886 ret = -ENOTSUPP; 7887 dev_err(&hdev->pdev->dev, 7888 "loop_mode %d is not supported\n", loop_mode); 7889 break; 7890 } 7891 7892 if (ret) 7893 return ret; 7894 7895 ret = hclge_tqp_enable(handle, en); 7896 if (ret) 7897 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n", 7898 en ? "enable" : "disable", ret); 7899 7900 return ret; 7901 } 7902 7903 static int hclge_set_default_loopback(struct hclge_dev *hdev) 7904 { 7905 int ret; 7906 7907 ret = hclge_set_app_loopback(hdev, false); 7908 if (ret) 7909 return ret; 7910 7911 ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES); 7912 if (ret) 7913 return ret; 7914 7915 return hclge_cfg_common_loopback(hdev, false, 7916 HNAE3_LOOP_PARALLEL_SERDES); 7917 } 7918 7919 static void hclge_flush_link_update(struct hclge_dev *hdev) 7920 { 7921 #define HCLGE_FLUSH_LINK_TIMEOUT 100000 7922 7923 unsigned long last = hdev->serv_processed_cnt; 7924 int i = 0; 7925 7926 while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) && 7927 i++ < HCLGE_FLUSH_LINK_TIMEOUT && 7928 last == hdev->serv_processed_cnt) 7929 usleep_range(1, 1); 7930 } 7931 7932 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable) 7933 { 7934 struct hclge_vport *vport = hclge_get_vport(handle); 7935 struct hclge_dev *hdev = vport->back; 7936 7937 if (enable) { 7938 hclge_task_schedule(hdev, 0); 7939 } else { 7940 /* Set the DOWN flag here to disable link updating */ 7941 set_bit(HCLGE_STATE_DOWN, &hdev->state); 7942 7943 /* flush memory to make sure DOWN is seen by service task */ 7944 smp_mb__before_atomic(); 7945 hclge_flush_link_update(hdev); 7946 } 7947 } 7948 7949 static int hclge_ae_start(struct hnae3_handle *handle) 7950 { 7951 struct hclge_vport *vport = hclge_get_vport(handle); 7952 struct hclge_dev *hdev = vport->back; 7953 7954 /* mac enable */ 7955 hclge_cfg_mac_mode(hdev, true); 7956 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 7957 hdev->hw.mac.link = 0; 7958 7959 /* reset tqp stats */ 7960 hclge_comm_reset_tqp_stats(handle); 7961 7962 hclge_mac_start_phy(hdev); 7963 7964 return 0; 7965 } 7966 7967 static void hclge_ae_stop(struct hnae3_handle *handle) 7968 { 7969 struct hclge_vport *vport = hclge_get_vport(handle); 7970 struct hclge_dev *hdev = vport->back; 7971 7972 set_bit(HCLGE_STATE_DOWN, &hdev->state); 7973 spin_lock_bh(&hdev->fd_rule_lock); 7974 hclge_clear_arfs_rules(hdev); 7975 spin_unlock_bh(&hdev->fd_rule_lock); 7976 7977 /* If it is not PF reset or FLR, the firmware will disable the MAC, 7978 * so it only need to stop phy here. 7979 */ 7980 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { 7981 hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE, 7982 HCLGE_PFC_DISABLE); 7983 if (hdev->reset_type != HNAE3_FUNC_RESET && 7984 hdev->reset_type != HNAE3_FLR_RESET) { 7985 hclge_mac_stop_phy(hdev); 7986 hclge_update_link_status(hdev); 7987 return; 7988 } 7989 } 7990 7991 hclge_reset_tqp(handle); 7992 7993 hclge_config_mac_tnl_int(hdev, false); 7994 7995 /* Mac disable */ 7996 hclge_cfg_mac_mode(hdev, false); 7997 7998 hclge_mac_stop_phy(hdev); 7999 8000 /* reset tqp stats */ 8001 hclge_comm_reset_tqp_stats(handle); 8002 hclge_update_link_status(hdev); 8003 } 8004 8005 int hclge_vport_start(struct hclge_vport *vport) 8006 { 8007 struct hclge_dev *hdev = vport->back; 8008 8009 set_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8010 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8011 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 8012 vport->last_active_jiffies = jiffies; 8013 vport->need_notify = 0; 8014 8015 if (test_bit(vport->vport_id, hdev->vport_config_block)) { 8016 if (vport->vport_id) { 8017 hclge_restore_mac_table_common(vport); 8018 hclge_restore_vport_vlan_table(vport); 8019 } else { 8020 hclge_restore_hw_table(hdev); 8021 } 8022 } 8023 8024 clear_bit(vport->vport_id, hdev->vport_config_block); 8025 8026 return 0; 8027 } 8028 8029 void hclge_vport_stop(struct hclge_vport *vport) 8030 { 8031 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8032 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8033 vport->need_notify = 0; 8034 } 8035 8036 static int hclge_client_start(struct hnae3_handle *handle) 8037 { 8038 struct hclge_vport *vport = hclge_get_vport(handle); 8039 8040 return hclge_vport_start(vport); 8041 } 8042 8043 static void hclge_client_stop(struct hnae3_handle *handle) 8044 { 8045 struct hclge_vport *vport = hclge_get_vport(handle); 8046 8047 hclge_vport_stop(vport); 8048 } 8049 8050 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 8051 u16 cmdq_resp, u8 resp_code, 8052 enum hclge_mac_vlan_tbl_opcode op) 8053 { 8054 struct hclge_dev *hdev = vport->back; 8055 8056 if (cmdq_resp) { 8057 dev_err(&hdev->pdev->dev, 8058 "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n", 8059 cmdq_resp); 8060 return -EIO; 8061 } 8062 8063 if (op == HCLGE_MAC_VLAN_ADD) { 8064 if (!resp_code || resp_code == 1) 8065 return 0; 8066 else if (resp_code == HCLGE_ADD_UC_OVERFLOW || 8067 resp_code == HCLGE_ADD_MC_OVERFLOW) 8068 return -ENOSPC; 8069 8070 dev_err(&hdev->pdev->dev, 8071 "add mac addr failed for undefined, code=%u.\n", 8072 resp_code); 8073 return -EIO; 8074 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 8075 if (!resp_code) { 8076 return 0; 8077 } else if (resp_code == 1) { 8078 dev_dbg(&hdev->pdev->dev, 8079 "remove mac addr failed for miss.\n"); 8080 return -ENOENT; 8081 } 8082 8083 dev_err(&hdev->pdev->dev, 8084 "remove mac addr failed for undefined, code=%u.\n", 8085 resp_code); 8086 return -EIO; 8087 } else if (op == HCLGE_MAC_VLAN_LKUP) { 8088 if (!resp_code) { 8089 return 0; 8090 } else if (resp_code == 1) { 8091 dev_dbg(&hdev->pdev->dev, 8092 "lookup mac addr failed for miss.\n"); 8093 return -ENOENT; 8094 } 8095 8096 dev_err(&hdev->pdev->dev, 8097 "lookup mac addr failed for undefined, code=%u.\n", 8098 resp_code); 8099 return -EIO; 8100 } 8101 8102 dev_err(&hdev->pdev->dev, 8103 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op); 8104 8105 return -EINVAL; 8106 } 8107 8108 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 8109 { 8110 #define HCLGE_VF_NUM_IN_FIRST_DESC 192 8111 8112 unsigned int word_num; 8113 unsigned int bit_num; 8114 8115 if (vfid > 255 || vfid < 0) 8116 return -EIO; 8117 8118 if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) { 8119 word_num = vfid / 32; 8120 bit_num = vfid % 32; 8121 if (clr) 8122 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8123 else 8124 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 8125 } else { 8126 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32; 8127 bit_num = vfid % 32; 8128 if (clr) 8129 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8130 else 8131 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 8132 } 8133 8134 return 0; 8135 } 8136 8137 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 8138 { 8139 #define HCLGE_DESC_NUMBER 3 8140 #define HCLGE_FUNC_NUMBER_PER_DESC 6 8141 int i, j; 8142 8143 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 8144 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 8145 if (desc[i].data[j]) 8146 return false; 8147 8148 return true; 8149 } 8150 8151 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 8152 const u8 *addr, bool is_mc) 8153 { 8154 const unsigned char *mac_addr = addr; 8155 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 8156 (mac_addr[0]) | (mac_addr[1] << 8); 8157 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 8158 8159 hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8160 if (is_mc) { 8161 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 8162 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8163 } 8164 8165 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 8166 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 8167 } 8168 8169 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 8170 struct hclge_mac_vlan_tbl_entry_cmd *req) 8171 { 8172 struct hclge_dev *hdev = vport->back; 8173 struct hclge_desc desc; 8174 u8 resp_code; 8175 u16 retval; 8176 int ret; 8177 8178 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 8179 8180 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8181 8182 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8183 if (ret) { 8184 dev_err(&hdev->pdev->dev, 8185 "del mac addr failed for cmd_send, ret =%d.\n", 8186 ret); 8187 return ret; 8188 } 8189 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8190 retval = le16_to_cpu(desc.retval); 8191 8192 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8193 HCLGE_MAC_VLAN_REMOVE); 8194 } 8195 8196 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 8197 struct hclge_mac_vlan_tbl_entry_cmd *req, 8198 struct hclge_desc *desc, 8199 bool is_mc) 8200 { 8201 struct hclge_dev *hdev = vport->back; 8202 u8 resp_code; 8203 u16 retval; 8204 int ret; 8205 8206 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 8207 if (is_mc) { 8208 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8209 memcpy(desc[0].data, 8210 req, 8211 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8212 hclge_cmd_setup_basic_desc(&desc[1], 8213 HCLGE_OPC_MAC_VLAN_ADD, 8214 true); 8215 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8216 hclge_cmd_setup_basic_desc(&desc[2], 8217 HCLGE_OPC_MAC_VLAN_ADD, 8218 true); 8219 ret = hclge_cmd_send(&hdev->hw, desc, 3); 8220 } else { 8221 memcpy(desc[0].data, 8222 req, 8223 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8224 ret = hclge_cmd_send(&hdev->hw, desc, 1); 8225 } 8226 if (ret) { 8227 dev_err(&hdev->pdev->dev, 8228 "lookup mac addr failed for cmd_send, ret =%d.\n", 8229 ret); 8230 return ret; 8231 } 8232 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 8233 retval = le16_to_cpu(desc[0].retval); 8234 8235 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8236 HCLGE_MAC_VLAN_LKUP); 8237 } 8238 8239 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 8240 struct hclge_mac_vlan_tbl_entry_cmd *req, 8241 struct hclge_desc *mc_desc) 8242 { 8243 struct hclge_dev *hdev = vport->back; 8244 int cfg_status; 8245 u8 resp_code; 8246 u16 retval; 8247 int ret; 8248 8249 if (!mc_desc) { 8250 struct hclge_desc desc; 8251 8252 hclge_cmd_setup_basic_desc(&desc, 8253 HCLGE_OPC_MAC_VLAN_ADD, 8254 false); 8255 memcpy(desc.data, req, 8256 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8257 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8258 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8259 retval = le16_to_cpu(desc.retval); 8260 8261 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8262 resp_code, 8263 HCLGE_MAC_VLAN_ADD); 8264 } else { 8265 hclge_comm_cmd_reuse_desc(&mc_desc[0], false); 8266 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8267 hclge_comm_cmd_reuse_desc(&mc_desc[1], false); 8268 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8269 hclge_comm_cmd_reuse_desc(&mc_desc[2], false); 8270 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT); 8271 memcpy(mc_desc[0].data, req, 8272 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8273 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 8274 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 8275 retval = le16_to_cpu(mc_desc[0].retval); 8276 8277 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8278 resp_code, 8279 HCLGE_MAC_VLAN_ADD); 8280 } 8281 8282 if (ret) { 8283 dev_err(&hdev->pdev->dev, 8284 "add mac addr failed for cmd_send, ret =%d.\n", 8285 ret); 8286 return ret; 8287 } 8288 8289 return cfg_status; 8290 } 8291 8292 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 8293 u16 *allocated_size) 8294 { 8295 struct hclge_umv_spc_alc_cmd *req; 8296 struct hclge_desc desc; 8297 int ret; 8298 8299 req = (struct hclge_umv_spc_alc_cmd *)desc.data; 8300 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false); 8301 8302 req->space_size = cpu_to_le32(space_size); 8303 8304 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8305 if (ret) { 8306 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n", 8307 ret); 8308 return ret; 8309 } 8310 8311 *allocated_size = le32_to_cpu(desc.data[1]); 8312 8313 return 0; 8314 } 8315 8316 static int hclge_init_umv_space(struct hclge_dev *hdev) 8317 { 8318 u16 allocated_size = 0; 8319 int ret; 8320 8321 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size); 8322 if (ret) 8323 return ret; 8324 8325 if (allocated_size < hdev->wanted_umv_size) 8326 dev_warn(&hdev->pdev->dev, 8327 "failed to alloc umv space, want %u, get %u\n", 8328 hdev->wanted_umv_size, allocated_size); 8329 8330 hdev->max_umv_size = allocated_size; 8331 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1); 8332 hdev->share_umv_size = hdev->priv_umv_size + 8333 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8334 8335 if (hdev->ae_dev->dev_specs.mc_mac_size) 8336 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps); 8337 8338 return 0; 8339 } 8340 8341 static void hclge_reset_umv_space(struct hclge_dev *hdev) 8342 { 8343 struct hclge_vport *vport; 8344 int i; 8345 8346 for (i = 0; i < hdev->num_alloc_vport; i++) { 8347 vport = &hdev->vport[i]; 8348 vport->used_umv_num = 0; 8349 } 8350 8351 mutex_lock(&hdev->vport_lock); 8352 hdev->share_umv_size = hdev->priv_umv_size + 8353 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8354 mutex_unlock(&hdev->vport_lock); 8355 8356 hdev->used_mc_mac_num = 0; 8357 } 8358 8359 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock) 8360 { 8361 struct hclge_dev *hdev = vport->back; 8362 bool is_full; 8363 8364 if (need_lock) 8365 mutex_lock(&hdev->vport_lock); 8366 8367 is_full = (vport->used_umv_num >= hdev->priv_umv_size && 8368 hdev->share_umv_size == 0); 8369 8370 if (need_lock) 8371 mutex_unlock(&hdev->vport_lock); 8372 8373 return is_full; 8374 } 8375 8376 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free) 8377 { 8378 struct hclge_dev *hdev = vport->back; 8379 8380 if (is_free) { 8381 if (vport->used_umv_num > hdev->priv_umv_size) 8382 hdev->share_umv_size++; 8383 8384 if (vport->used_umv_num > 0) 8385 vport->used_umv_num--; 8386 } else { 8387 if (vport->used_umv_num >= hdev->priv_umv_size && 8388 hdev->share_umv_size > 0) 8389 hdev->share_umv_size--; 8390 vport->used_umv_num++; 8391 } 8392 } 8393 8394 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list, 8395 const u8 *mac_addr) 8396 { 8397 struct hclge_mac_node *mac_node, *tmp; 8398 8399 list_for_each_entry_safe(mac_node, tmp, list, node) 8400 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 8401 return mac_node; 8402 8403 return NULL; 8404 } 8405 8406 static void hclge_update_mac_node(struct hclge_mac_node *mac_node, 8407 enum HCLGE_MAC_NODE_STATE state) 8408 { 8409 switch (state) { 8410 /* from set_rx_mode or tmp_add_list */ 8411 case HCLGE_MAC_TO_ADD: 8412 if (mac_node->state == HCLGE_MAC_TO_DEL) 8413 mac_node->state = HCLGE_MAC_ACTIVE; 8414 break; 8415 /* only from set_rx_mode */ 8416 case HCLGE_MAC_TO_DEL: 8417 if (mac_node->state == HCLGE_MAC_TO_ADD) { 8418 list_del(&mac_node->node); 8419 kfree(mac_node); 8420 } else { 8421 mac_node->state = HCLGE_MAC_TO_DEL; 8422 } 8423 break; 8424 /* only from tmp_add_list, the mac_node->state won't be 8425 * ACTIVE. 8426 */ 8427 case HCLGE_MAC_ACTIVE: 8428 if (mac_node->state == HCLGE_MAC_TO_ADD) 8429 mac_node->state = HCLGE_MAC_ACTIVE; 8430 8431 break; 8432 } 8433 } 8434 8435 int hclge_update_mac_list(struct hclge_vport *vport, 8436 enum HCLGE_MAC_NODE_STATE state, 8437 enum HCLGE_MAC_ADDR_TYPE mac_type, 8438 const unsigned char *addr) 8439 { 8440 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8441 struct hclge_dev *hdev = vport->back; 8442 struct hclge_mac_node *mac_node; 8443 struct list_head *list; 8444 8445 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8446 &vport->uc_mac_list : &vport->mc_mac_list; 8447 8448 spin_lock_bh(&vport->mac_list_lock); 8449 8450 /* if the mac addr is already in the mac list, no need to add a new 8451 * one into it, just check the mac addr state, convert it to a new 8452 * state, or just remove it, or do nothing. 8453 */ 8454 mac_node = hclge_find_mac_node(list, addr); 8455 if (mac_node) { 8456 hclge_update_mac_node(mac_node, state); 8457 spin_unlock_bh(&vport->mac_list_lock); 8458 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8459 return 0; 8460 } 8461 8462 /* if this address is never added, unnecessary to delete */ 8463 if (state == HCLGE_MAC_TO_DEL) { 8464 spin_unlock_bh(&vport->mac_list_lock); 8465 hnae3_format_mac_addr(format_mac_addr, addr); 8466 dev_err(&hdev->pdev->dev, 8467 "failed to delete address %s from mac list\n", 8468 format_mac_addr); 8469 return -ENOENT; 8470 } 8471 8472 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 8473 if (!mac_node) { 8474 spin_unlock_bh(&vport->mac_list_lock); 8475 return -ENOMEM; 8476 } 8477 8478 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8479 8480 mac_node->state = state; 8481 ether_addr_copy(mac_node->mac_addr, addr); 8482 list_add_tail(&mac_node->node, list); 8483 8484 spin_unlock_bh(&vport->mac_list_lock); 8485 8486 return 0; 8487 } 8488 8489 static int hclge_add_uc_addr(struct hnae3_handle *handle, 8490 const unsigned char *addr) 8491 { 8492 struct hclge_vport *vport = hclge_get_vport(handle); 8493 8494 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC, 8495 addr); 8496 } 8497 8498 int hclge_add_uc_addr_common(struct hclge_vport *vport, 8499 const unsigned char *addr) 8500 { 8501 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8502 struct hclge_dev *hdev = vport->back; 8503 struct hclge_mac_vlan_tbl_entry_cmd req; 8504 struct hclge_desc desc; 8505 u16 egress_port = 0; 8506 int ret; 8507 8508 /* mac addr check */ 8509 if (is_zero_ether_addr(addr) || 8510 is_broadcast_ether_addr(addr) || 8511 is_multicast_ether_addr(addr)) { 8512 hnae3_format_mac_addr(format_mac_addr, addr); 8513 dev_err(&hdev->pdev->dev, 8514 "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n", 8515 format_mac_addr, is_zero_ether_addr(addr), 8516 is_broadcast_ether_addr(addr), 8517 is_multicast_ether_addr(addr)); 8518 return -EINVAL; 8519 } 8520 8521 memset(&req, 0, sizeof(req)); 8522 8523 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 8524 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 8525 8526 req.egress_port = cpu_to_le16(egress_port); 8527 8528 hclge_prepare_mac_addr(&req, addr, false); 8529 8530 /* Lookup the mac address in the mac_vlan table, and add 8531 * it if the entry is inexistent. Repeated unicast entry 8532 * is not allowed in the mac vlan table. 8533 */ 8534 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 8535 if (ret == -ENOENT) { 8536 mutex_lock(&hdev->vport_lock); 8537 if (!hclge_is_umv_space_full(vport, false)) { 8538 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL); 8539 if (!ret) 8540 hclge_update_umv_space(vport, false); 8541 mutex_unlock(&hdev->vport_lock); 8542 return ret; 8543 } 8544 mutex_unlock(&hdev->vport_lock); 8545 8546 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE)) 8547 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n", 8548 hdev->priv_umv_size); 8549 8550 return -ENOSPC; 8551 } 8552 8553 /* check if we just hit the duplicate */ 8554 if (!ret) 8555 return -EEXIST; 8556 8557 return ret; 8558 } 8559 8560 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 8561 const unsigned char *addr) 8562 { 8563 struct hclge_vport *vport = hclge_get_vport(handle); 8564 8565 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC, 8566 addr); 8567 } 8568 8569 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 8570 const unsigned char *addr) 8571 { 8572 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8573 struct hclge_dev *hdev = vport->back; 8574 struct hclge_mac_vlan_tbl_entry_cmd req; 8575 int ret; 8576 8577 /* mac addr check */ 8578 if (is_zero_ether_addr(addr) || 8579 is_broadcast_ether_addr(addr) || 8580 is_multicast_ether_addr(addr)) { 8581 hnae3_format_mac_addr(format_mac_addr, addr); 8582 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n", 8583 format_mac_addr); 8584 return -EINVAL; 8585 } 8586 8587 memset(&req, 0, sizeof(req)); 8588 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 8589 hclge_prepare_mac_addr(&req, addr, false); 8590 ret = hclge_remove_mac_vlan_tbl(vport, &req); 8591 if (!ret || ret == -ENOENT) { 8592 mutex_lock(&hdev->vport_lock); 8593 hclge_update_umv_space(vport, true); 8594 mutex_unlock(&hdev->vport_lock); 8595 return 0; 8596 } 8597 8598 return ret; 8599 } 8600 8601 static int hclge_add_mc_addr(struct hnae3_handle *handle, 8602 const unsigned char *addr) 8603 { 8604 struct hclge_vport *vport = hclge_get_vport(handle); 8605 8606 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC, 8607 addr); 8608 } 8609 8610 int hclge_add_mc_addr_common(struct hclge_vport *vport, 8611 const unsigned char *addr) 8612 { 8613 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8614 struct hclge_dev *hdev = vport->back; 8615 struct hclge_mac_vlan_tbl_entry_cmd req; 8616 struct hclge_desc desc[3]; 8617 bool is_new_addr = false; 8618 int status; 8619 8620 /* mac addr check */ 8621 if (!is_multicast_ether_addr(addr)) { 8622 hnae3_format_mac_addr(format_mac_addr, addr); 8623 dev_err(&hdev->pdev->dev, 8624 "Add mc mac err! invalid mac:%s.\n", 8625 format_mac_addr); 8626 return -EINVAL; 8627 } 8628 memset(&req, 0, sizeof(req)); 8629 hclge_prepare_mac_addr(&req, addr, true); 8630 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8631 if (status) { 8632 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) && 8633 hdev->used_mc_mac_num >= 8634 hdev->ae_dev->dev_specs.mc_mac_size) 8635 goto err_no_space; 8636 8637 is_new_addr = true; 8638 8639 /* This mac addr do not exist, add new entry for it */ 8640 memset(desc[0].data, 0, sizeof(desc[0].data)); 8641 memset(desc[1].data, 0, sizeof(desc[0].data)); 8642 memset(desc[2].data, 0, sizeof(desc[0].data)); 8643 } 8644 status = hclge_update_desc_vfid(desc, vport->vport_id, false); 8645 if (status) 8646 return status; 8647 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8648 if (status == -ENOSPC) 8649 goto err_no_space; 8650 else if (!status && is_new_addr) 8651 hdev->used_mc_mac_num++; 8652 8653 return status; 8654 8655 err_no_space: 8656 /* if already overflow, not to print each time */ 8657 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) { 8658 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8659 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n"); 8660 } 8661 8662 return -ENOSPC; 8663 } 8664 8665 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 8666 const unsigned char *addr) 8667 { 8668 struct hclge_vport *vport = hclge_get_vport(handle); 8669 8670 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC, 8671 addr); 8672 } 8673 8674 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 8675 const unsigned char *addr) 8676 { 8677 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8678 struct hclge_dev *hdev = vport->back; 8679 struct hclge_mac_vlan_tbl_entry_cmd req; 8680 enum hclge_comm_cmd_status status; 8681 struct hclge_desc desc[3]; 8682 8683 /* mac addr check */ 8684 if (!is_multicast_ether_addr(addr)) { 8685 hnae3_format_mac_addr(format_mac_addr, addr); 8686 dev_dbg(&hdev->pdev->dev, 8687 "Remove mc mac err! invalid mac:%s.\n", 8688 format_mac_addr); 8689 return -EINVAL; 8690 } 8691 8692 memset(&req, 0, sizeof(req)); 8693 hclge_prepare_mac_addr(&req, addr, true); 8694 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8695 if (!status) { 8696 /* This mac addr exist, remove this handle's VFID for it */ 8697 status = hclge_update_desc_vfid(desc, vport->vport_id, true); 8698 if (status) 8699 return status; 8700 8701 if (hclge_is_all_function_id_zero(desc)) { 8702 /* All the vfid is zero, so need to delete this entry */ 8703 status = hclge_remove_mac_vlan_tbl(vport, &req); 8704 if (!status) 8705 hdev->used_mc_mac_num--; 8706 } else { 8707 /* Not all the vfid is zero, update the vfid */ 8708 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8709 } 8710 } else if (status == -ENOENT) { 8711 status = 0; 8712 } 8713 8714 return status; 8715 } 8716 8717 static void hclge_sync_vport_mac_list(struct hclge_vport *vport, 8718 struct list_head *list, 8719 enum HCLGE_MAC_ADDR_TYPE mac_type) 8720 { 8721 int (*sync)(struct hclge_vport *vport, const unsigned char *addr); 8722 struct hclge_mac_node *mac_node, *tmp; 8723 int ret; 8724 8725 if (mac_type == HCLGE_MAC_ADDR_UC) 8726 sync = hclge_add_uc_addr_common; 8727 else 8728 sync = hclge_add_mc_addr_common; 8729 8730 list_for_each_entry_safe(mac_node, tmp, list, node) { 8731 ret = sync(vport, mac_node->mac_addr); 8732 if (!ret) { 8733 mac_node->state = HCLGE_MAC_ACTIVE; 8734 } else { 8735 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8736 &vport->state); 8737 8738 /* If one unicast mac address is existing in hardware, 8739 * we need to try whether other unicast mac addresses 8740 * are new addresses that can be added. 8741 * Multicast mac address can be reusable, even though 8742 * there is no space to add new multicast mac address, 8743 * we should check whether other mac addresses are 8744 * existing in hardware for reuse. 8745 */ 8746 if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) || 8747 (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC)) 8748 break; 8749 } 8750 } 8751 } 8752 8753 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport, 8754 struct list_head *list, 8755 enum HCLGE_MAC_ADDR_TYPE mac_type) 8756 { 8757 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 8758 struct hclge_mac_node *mac_node, *tmp; 8759 int ret; 8760 8761 if (mac_type == HCLGE_MAC_ADDR_UC) 8762 unsync = hclge_rm_uc_addr_common; 8763 else 8764 unsync = hclge_rm_mc_addr_common; 8765 8766 list_for_each_entry_safe(mac_node, tmp, list, node) { 8767 ret = unsync(vport, mac_node->mac_addr); 8768 if (!ret || ret == -ENOENT) { 8769 list_del(&mac_node->node); 8770 kfree(mac_node); 8771 } else { 8772 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8773 &vport->state); 8774 break; 8775 } 8776 } 8777 } 8778 8779 static bool hclge_sync_from_add_list(struct list_head *add_list, 8780 struct list_head *mac_list) 8781 { 8782 struct hclge_mac_node *mac_node, *tmp, *new_node; 8783 bool all_added = true; 8784 8785 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 8786 if (mac_node->state == HCLGE_MAC_TO_ADD) 8787 all_added = false; 8788 8789 /* if the mac address from tmp_add_list is not in the 8790 * uc/mc_mac_list, it means have received a TO_DEL request 8791 * during the time window of adding the mac address into mac 8792 * table. if mac_node state is ACTIVE, then change it to TO_DEL, 8793 * then it will be removed at next time. else it must be TO_ADD, 8794 * this address hasn't been added into mac table, 8795 * so just remove the mac node. 8796 */ 8797 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8798 if (new_node) { 8799 hclge_update_mac_node(new_node, mac_node->state); 8800 list_del(&mac_node->node); 8801 kfree(mac_node); 8802 } else if (mac_node->state == HCLGE_MAC_ACTIVE) { 8803 mac_node->state = HCLGE_MAC_TO_DEL; 8804 list_move_tail(&mac_node->node, mac_list); 8805 } else { 8806 list_del(&mac_node->node); 8807 kfree(mac_node); 8808 } 8809 } 8810 8811 return all_added; 8812 } 8813 8814 static void hclge_sync_from_del_list(struct list_head *del_list, 8815 struct list_head *mac_list) 8816 { 8817 struct hclge_mac_node *mac_node, *tmp, *new_node; 8818 8819 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 8820 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8821 if (new_node) { 8822 /* If the mac addr exists in the mac list, it means 8823 * received a new TO_ADD request during the time window 8824 * of configuring the mac address. For the mac node 8825 * state is TO_ADD, and the address is already in the 8826 * in the hardware(due to delete fail), so we just need 8827 * to change the mac node state to ACTIVE. 8828 */ 8829 new_node->state = HCLGE_MAC_ACTIVE; 8830 list_del(&mac_node->node); 8831 kfree(mac_node); 8832 } else { 8833 list_move_tail(&mac_node->node, mac_list); 8834 } 8835 } 8836 } 8837 8838 static void hclge_update_overflow_flags(struct hclge_vport *vport, 8839 enum HCLGE_MAC_ADDR_TYPE mac_type, 8840 bool is_all_added) 8841 { 8842 if (mac_type == HCLGE_MAC_ADDR_UC) { 8843 if (is_all_added) 8844 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE; 8845 else if (hclge_is_umv_space_full(vport, true)) 8846 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE; 8847 } else { 8848 if (is_all_added) 8849 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE; 8850 else 8851 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8852 } 8853 } 8854 8855 static void hclge_sync_vport_mac_table(struct hclge_vport *vport, 8856 enum HCLGE_MAC_ADDR_TYPE mac_type) 8857 { 8858 struct hclge_mac_node *mac_node, *tmp, *new_node; 8859 struct list_head tmp_add_list, tmp_del_list; 8860 struct list_head *list; 8861 bool all_added; 8862 8863 INIT_LIST_HEAD(&tmp_add_list); 8864 INIT_LIST_HEAD(&tmp_del_list); 8865 8866 /* move the mac addr to the tmp_add_list and tmp_del_list, then 8867 * we can add/delete these mac addr outside the spin lock 8868 */ 8869 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8870 &vport->uc_mac_list : &vport->mc_mac_list; 8871 8872 spin_lock_bh(&vport->mac_list_lock); 8873 8874 list_for_each_entry_safe(mac_node, tmp, list, node) { 8875 switch (mac_node->state) { 8876 case HCLGE_MAC_TO_DEL: 8877 list_move_tail(&mac_node->node, &tmp_del_list); 8878 break; 8879 case HCLGE_MAC_TO_ADD: 8880 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 8881 if (!new_node) 8882 goto stop_traverse; 8883 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 8884 new_node->state = mac_node->state; 8885 list_add_tail(&new_node->node, &tmp_add_list); 8886 break; 8887 default: 8888 break; 8889 } 8890 } 8891 8892 stop_traverse: 8893 spin_unlock_bh(&vport->mac_list_lock); 8894 8895 /* delete first, in order to get max mac table space for adding */ 8896 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 8897 hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type); 8898 8899 /* if some mac addresses were added/deleted fail, move back to the 8900 * mac_list, and retry at next time. 8901 */ 8902 spin_lock_bh(&vport->mac_list_lock); 8903 8904 hclge_sync_from_del_list(&tmp_del_list, list); 8905 all_added = hclge_sync_from_add_list(&tmp_add_list, list); 8906 8907 spin_unlock_bh(&vport->mac_list_lock); 8908 8909 hclge_update_overflow_flags(vport, mac_type, all_added); 8910 } 8911 8912 static bool hclge_need_sync_mac_table(struct hclge_vport *vport) 8913 { 8914 struct hclge_dev *hdev = vport->back; 8915 8916 if (test_bit(vport->vport_id, hdev->vport_config_block)) 8917 return false; 8918 8919 if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state)) 8920 return true; 8921 8922 return false; 8923 } 8924 8925 static void hclge_sync_mac_table(struct hclge_dev *hdev) 8926 { 8927 int i; 8928 8929 for (i = 0; i < hdev->num_alloc_vport; i++) { 8930 struct hclge_vport *vport = &hdev->vport[i]; 8931 8932 if (!hclge_need_sync_mac_table(vport)) 8933 continue; 8934 8935 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC); 8936 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC); 8937 } 8938 } 8939 8940 static void hclge_build_del_list(struct list_head *list, 8941 bool is_del_list, 8942 struct list_head *tmp_del_list) 8943 { 8944 struct hclge_mac_node *mac_cfg, *tmp; 8945 8946 list_for_each_entry_safe(mac_cfg, tmp, list, node) { 8947 switch (mac_cfg->state) { 8948 case HCLGE_MAC_TO_DEL: 8949 case HCLGE_MAC_ACTIVE: 8950 list_move_tail(&mac_cfg->node, tmp_del_list); 8951 break; 8952 case HCLGE_MAC_TO_ADD: 8953 if (is_del_list) { 8954 list_del(&mac_cfg->node); 8955 kfree(mac_cfg); 8956 } 8957 break; 8958 } 8959 } 8960 } 8961 8962 static void hclge_unsync_del_list(struct hclge_vport *vport, 8963 int (*unsync)(struct hclge_vport *vport, 8964 const unsigned char *addr), 8965 bool is_del_list, 8966 struct list_head *tmp_del_list) 8967 { 8968 struct hclge_mac_node *mac_cfg, *tmp; 8969 int ret; 8970 8971 list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) { 8972 ret = unsync(vport, mac_cfg->mac_addr); 8973 if (!ret || ret == -ENOENT) { 8974 /* clear all mac addr from hardware, but remain these 8975 * mac addr in the mac list, and restore them after 8976 * vf reset finished. 8977 */ 8978 if (!is_del_list && 8979 mac_cfg->state == HCLGE_MAC_ACTIVE) { 8980 mac_cfg->state = HCLGE_MAC_TO_ADD; 8981 } else { 8982 list_del(&mac_cfg->node); 8983 kfree(mac_cfg); 8984 } 8985 } else if (is_del_list) { 8986 mac_cfg->state = HCLGE_MAC_TO_DEL; 8987 } 8988 } 8989 } 8990 8991 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 8992 enum HCLGE_MAC_ADDR_TYPE mac_type) 8993 { 8994 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 8995 struct hclge_dev *hdev = vport->back; 8996 struct list_head tmp_del_list, *list; 8997 8998 if (mac_type == HCLGE_MAC_ADDR_UC) { 8999 list = &vport->uc_mac_list; 9000 unsync = hclge_rm_uc_addr_common; 9001 } else { 9002 list = &vport->mc_mac_list; 9003 unsync = hclge_rm_mc_addr_common; 9004 } 9005 9006 INIT_LIST_HEAD(&tmp_del_list); 9007 9008 if (!is_del_list) 9009 set_bit(vport->vport_id, hdev->vport_config_block); 9010 9011 spin_lock_bh(&vport->mac_list_lock); 9012 9013 hclge_build_del_list(list, is_del_list, &tmp_del_list); 9014 9015 spin_unlock_bh(&vport->mac_list_lock); 9016 9017 hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list); 9018 9019 spin_lock_bh(&vport->mac_list_lock); 9020 9021 hclge_sync_from_del_list(&tmp_del_list, list); 9022 9023 spin_unlock_bh(&vport->mac_list_lock); 9024 } 9025 9026 /* remove all mac address when uninitailize */ 9027 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport, 9028 enum HCLGE_MAC_ADDR_TYPE mac_type) 9029 { 9030 struct hclge_mac_node *mac_node, *tmp; 9031 struct hclge_dev *hdev = vport->back; 9032 struct list_head tmp_del_list, *list; 9033 9034 INIT_LIST_HEAD(&tmp_del_list); 9035 9036 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 9037 &vport->uc_mac_list : &vport->mc_mac_list; 9038 9039 spin_lock_bh(&vport->mac_list_lock); 9040 9041 list_for_each_entry_safe(mac_node, tmp, list, node) { 9042 switch (mac_node->state) { 9043 case HCLGE_MAC_TO_DEL: 9044 case HCLGE_MAC_ACTIVE: 9045 list_move_tail(&mac_node->node, &tmp_del_list); 9046 break; 9047 case HCLGE_MAC_TO_ADD: 9048 list_del(&mac_node->node); 9049 kfree(mac_node); 9050 break; 9051 } 9052 } 9053 9054 spin_unlock_bh(&vport->mac_list_lock); 9055 9056 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 9057 9058 if (!list_empty(&tmp_del_list)) 9059 dev_warn(&hdev->pdev->dev, 9060 "uninit %s mac list for vport %u not completely.\n", 9061 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc", 9062 vport->vport_id); 9063 9064 list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) { 9065 list_del(&mac_node->node); 9066 kfree(mac_node); 9067 } 9068 } 9069 9070 static void hclge_uninit_mac_table(struct hclge_dev *hdev) 9071 { 9072 struct hclge_vport *vport; 9073 int i; 9074 9075 for (i = 0; i < hdev->num_alloc_vport; i++) { 9076 vport = &hdev->vport[i]; 9077 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC); 9078 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC); 9079 } 9080 } 9081 9082 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 9083 u16 cmdq_resp, u8 resp_code) 9084 { 9085 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 9086 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 9087 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 9088 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 9089 9090 int return_status; 9091 9092 if (cmdq_resp) { 9093 dev_err(&hdev->pdev->dev, 9094 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 9095 cmdq_resp); 9096 return -EIO; 9097 } 9098 9099 switch (resp_code) { 9100 case HCLGE_ETHERTYPE_SUCCESS_ADD: 9101 case HCLGE_ETHERTYPE_ALREADY_ADD: 9102 return_status = 0; 9103 break; 9104 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 9105 dev_err(&hdev->pdev->dev, 9106 "add mac ethertype failed for manager table overflow.\n"); 9107 return_status = -EIO; 9108 break; 9109 case HCLGE_ETHERTYPE_KEY_CONFLICT: 9110 dev_err(&hdev->pdev->dev, 9111 "add mac ethertype failed for key conflict.\n"); 9112 return_status = -EIO; 9113 break; 9114 default: 9115 dev_err(&hdev->pdev->dev, 9116 "add mac ethertype failed for undefined, code=%u.\n", 9117 resp_code); 9118 return_status = -EIO; 9119 } 9120 9121 return return_status; 9122 } 9123 9124 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf, 9125 u8 *mac_addr) 9126 { 9127 struct hclge_vport *vport = hclge_get_vport(handle); 9128 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9129 struct hclge_dev *hdev = vport->back; 9130 9131 vport = hclge_get_vf_vport(hdev, vf); 9132 if (!vport) 9133 return -EINVAL; 9134 9135 hnae3_format_mac_addr(format_mac_addr, mac_addr); 9136 if (ether_addr_equal(mac_addr, vport->vf_info.mac)) { 9137 dev_info(&hdev->pdev->dev, 9138 "Specified MAC(=%s) is same as before, no change committed!\n", 9139 format_mac_addr); 9140 return 0; 9141 } 9142 9143 ether_addr_copy(vport->vf_info.mac, mac_addr); 9144 9145 /* there is a timewindow for PF to know VF unalive, it may 9146 * cause send mailbox fail, but it doesn't matter, VF will 9147 * query it when reinit. 9148 */ 9149 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) { 9150 dev_info(&hdev->pdev->dev, 9151 "MAC of VF %d has been set to %s, and it will be reinitialized!\n", 9152 vf, format_mac_addr); 9153 (void)hclge_inform_reset_assert_to_vf(vport); 9154 return 0; 9155 } 9156 9157 dev_info(&hdev->pdev->dev, 9158 "MAC of VF %d has been set to %s, will be active after VF reset\n", 9159 vf, format_mac_addr); 9160 return 0; 9161 } 9162 9163 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 9164 const struct hclge_mac_mgr_tbl_entry_cmd *req) 9165 { 9166 struct hclge_desc desc; 9167 u8 resp_code; 9168 u16 retval; 9169 int ret; 9170 9171 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 9172 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 9173 9174 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9175 if (ret) { 9176 dev_err(&hdev->pdev->dev, 9177 "add mac ethertype failed for cmd_send, ret =%d.\n", 9178 ret); 9179 return ret; 9180 } 9181 9182 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 9183 retval = le16_to_cpu(desc.retval); 9184 9185 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 9186 } 9187 9188 static int init_mgr_tbl(struct hclge_dev *hdev) 9189 { 9190 int ret; 9191 int i; 9192 9193 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 9194 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 9195 if (ret) { 9196 dev_err(&hdev->pdev->dev, 9197 "add mac ethertype failed, ret =%d.\n", 9198 ret); 9199 return ret; 9200 } 9201 } 9202 9203 return 0; 9204 } 9205 9206 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 9207 { 9208 struct hclge_vport *vport = hclge_get_vport(handle); 9209 struct hclge_dev *hdev = vport->back; 9210 9211 ether_addr_copy(p, hdev->hw.mac.mac_addr); 9212 } 9213 9214 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 9215 const u8 *old_addr, const u8 *new_addr) 9216 { 9217 struct list_head *list = &vport->uc_mac_list; 9218 struct hclge_mac_node *old_node, *new_node; 9219 9220 new_node = hclge_find_mac_node(list, new_addr); 9221 if (!new_node) { 9222 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 9223 if (!new_node) 9224 return -ENOMEM; 9225 9226 new_node->state = HCLGE_MAC_TO_ADD; 9227 ether_addr_copy(new_node->mac_addr, new_addr); 9228 list_add(&new_node->node, list); 9229 } else { 9230 if (new_node->state == HCLGE_MAC_TO_DEL) 9231 new_node->state = HCLGE_MAC_ACTIVE; 9232 9233 /* make sure the new addr is in the list head, avoid dev 9234 * addr may be not re-added into mac table for the umv space 9235 * limitation after global/imp reset which will clear mac 9236 * table by hardware. 9237 */ 9238 list_move(&new_node->node, list); 9239 } 9240 9241 if (old_addr && !ether_addr_equal(old_addr, new_addr)) { 9242 old_node = hclge_find_mac_node(list, old_addr); 9243 if (old_node) { 9244 if (old_node->state == HCLGE_MAC_TO_ADD) { 9245 list_del(&old_node->node); 9246 kfree(old_node); 9247 } else { 9248 old_node->state = HCLGE_MAC_TO_DEL; 9249 } 9250 } 9251 } 9252 9253 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 9254 9255 return 0; 9256 } 9257 9258 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p, 9259 bool is_first) 9260 { 9261 const unsigned char *new_addr = (const unsigned char *)p; 9262 struct hclge_vport *vport = hclge_get_vport(handle); 9263 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9264 struct hclge_dev *hdev = vport->back; 9265 unsigned char *old_addr = NULL; 9266 int ret; 9267 9268 /* mac addr check */ 9269 if (is_zero_ether_addr(new_addr) || 9270 is_broadcast_ether_addr(new_addr) || 9271 is_multicast_ether_addr(new_addr)) { 9272 hnae3_format_mac_addr(format_mac_addr, new_addr); 9273 dev_err(&hdev->pdev->dev, 9274 "change uc mac err! invalid mac: %s.\n", 9275 format_mac_addr); 9276 return -EINVAL; 9277 } 9278 9279 ret = hclge_pause_addr_cfg(hdev, new_addr); 9280 if (ret) { 9281 dev_err(&hdev->pdev->dev, 9282 "failed to configure mac pause address, ret = %d\n", 9283 ret); 9284 return ret; 9285 } 9286 9287 if (!is_first) 9288 old_addr = hdev->hw.mac.mac_addr; 9289 9290 spin_lock_bh(&vport->mac_list_lock); 9291 ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr); 9292 if (ret) { 9293 hnae3_format_mac_addr(format_mac_addr, new_addr); 9294 dev_err(&hdev->pdev->dev, 9295 "failed to change the mac addr:%s, ret = %d\n", 9296 format_mac_addr, ret); 9297 spin_unlock_bh(&vport->mac_list_lock); 9298 9299 if (!is_first) 9300 hclge_pause_addr_cfg(hdev, old_addr); 9301 9302 return ret; 9303 } 9304 /* we must update dev addr with spin lock protect, preventing dev addr 9305 * being removed by set_rx_mode path. 9306 */ 9307 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 9308 spin_unlock_bh(&vport->mac_list_lock); 9309 9310 hclge_task_schedule(hdev, 0); 9311 9312 return 0; 9313 } 9314 9315 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd) 9316 { 9317 struct mii_ioctl_data *data = if_mii(ifr); 9318 9319 if (!hnae3_dev_phy_imp_supported(hdev)) 9320 return -EOPNOTSUPP; 9321 9322 switch (cmd) { 9323 case SIOCGMIIPHY: 9324 data->phy_id = hdev->hw.mac.phy_addr; 9325 /* this command reads phy id and register at the same time */ 9326 fallthrough; 9327 case SIOCGMIIREG: 9328 data->val_out = hclge_read_phy_reg(hdev, data->reg_num); 9329 return 0; 9330 9331 case SIOCSMIIREG: 9332 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in); 9333 default: 9334 return -EOPNOTSUPP; 9335 } 9336 } 9337 9338 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr, 9339 int cmd) 9340 { 9341 struct hclge_vport *vport = hclge_get_vport(handle); 9342 struct hclge_dev *hdev = vport->back; 9343 9344 switch (cmd) { 9345 case SIOCGHWTSTAMP: 9346 return hclge_ptp_get_cfg(hdev, ifr); 9347 case SIOCSHWTSTAMP: 9348 return hclge_ptp_set_cfg(hdev, ifr); 9349 default: 9350 if (!hdev->hw.mac.phydev) 9351 return hclge_mii_ioctl(hdev, ifr, cmd); 9352 } 9353 9354 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd); 9355 } 9356 9357 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id, 9358 bool bypass_en) 9359 { 9360 struct hclge_port_vlan_filter_bypass_cmd *req; 9361 struct hclge_desc desc; 9362 int ret; 9363 9364 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false); 9365 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 9366 req->vf_id = vf_id; 9367 hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B, 9368 bypass_en ? 1 : 0); 9369 9370 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9371 if (ret) 9372 dev_err(&hdev->pdev->dev, 9373 "failed to set vport%u port vlan filter bypass state, ret = %d.\n", 9374 vf_id, ret); 9375 9376 return ret; 9377 } 9378 9379 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 9380 u8 fe_type, bool filter_en, u8 vf_id) 9381 { 9382 struct hclge_vlan_filter_ctrl_cmd *req; 9383 struct hclge_desc desc; 9384 int ret; 9385 9386 /* read current vlan filter parameter */ 9387 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 9388 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 9389 req->vlan_type = vlan_type; 9390 req->vf_id = vf_id; 9391 9392 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9393 if (ret) { 9394 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n", 9395 vf_id, ret); 9396 return ret; 9397 } 9398 9399 /* modify and write new config parameter */ 9400 hclge_comm_cmd_reuse_desc(&desc, false); 9401 req->vlan_fe = filter_en ? 9402 (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type); 9403 9404 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9405 if (ret) 9406 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n", 9407 vf_id, ret); 9408 9409 return ret; 9410 } 9411 9412 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable) 9413 { 9414 struct hclge_dev *hdev = vport->back; 9415 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 9416 int ret; 9417 9418 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9419 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9420 HCLGE_FILTER_FE_EGRESS_V1_B, 9421 enable, vport->vport_id); 9422 9423 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9424 HCLGE_FILTER_FE_EGRESS, enable, 9425 vport->vport_id); 9426 if (ret) 9427 return ret; 9428 9429 if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) { 9430 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id, 9431 !enable); 9432 } else if (!vport->vport_id) { 9433 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 9434 enable = false; 9435 9436 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9437 HCLGE_FILTER_FE_INGRESS, 9438 enable, 0); 9439 } 9440 9441 return ret; 9442 } 9443 9444 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport) 9445 { 9446 struct hnae3_handle *handle = &vport->nic; 9447 struct hclge_vport_vlan_cfg *vlan, *tmp; 9448 struct hclge_dev *hdev = vport->back; 9449 9450 if (vport->vport_id) { 9451 if (vport->port_base_vlan_cfg.state != 9452 HNAE3_PORT_BASE_VLAN_DISABLE) 9453 return true; 9454 9455 if (vport->vf_info.trusted && vport->vf_info.request_uc_en) 9456 return false; 9457 } else if (handle->netdev_flags & HNAE3_USER_UPE) { 9458 return false; 9459 } 9460 9461 if (!vport->req_vlan_fltr_en) 9462 return false; 9463 9464 /* compatible with former device, always enable vlan filter */ 9465 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 9466 return true; 9467 9468 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) 9469 if (vlan->vlan_id != 0) 9470 return true; 9471 9472 return false; 9473 } 9474 9475 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) 9476 { 9477 struct hclge_dev *hdev = vport->back; 9478 bool need_en; 9479 int ret; 9480 9481 mutex_lock(&hdev->vport_lock); 9482 9483 vport->req_vlan_fltr_en = request_en; 9484 9485 need_en = hclge_need_enable_vport_vlan_filter(vport); 9486 if (need_en == vport->cur_vlan_fltr_en) { 9487 mutex_unlock(&hdev->vport_lock); 9488 return 0; 9489 } 9490 9491 ret = hclge_set_vport_vlan_filter(vport, need_en); 9492 if (ret) { 9493 mutex_unlock(&hdev->vport_lock); 9494 return ret; 9495 } 9496 9497 vport->cur_vlan_fltr_en = need_en; 9498 9499 mutex_unlock(&hdev->vport_lock); 9500 9501 return 0; 9502 } 9503 9504 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 9505 { 9506 struct hclge_vport *vport = hclge_get_vport(handle); 9507 9508 return hclge_enable_vport_vlan_filter(vport, enable); 9509 } 9510 9511 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid, 9512 bool is_kill, u16 vlan, 9513 struct hclge_desc *desc) 9514 { 9515 struct hclge_vlan_filter_vf_cfg_cmd *req0; 9516 struct hclge_vlan_filter_vf_cfg_cmd *req1; 9517 u8 vf_byte_val; 9518 u8 vf_byte_off; 9519 int ret; 9520 9521 hclge_cmd_setup_basic_desc(&desc[0], 9522 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9523 hclge_cmd_setup_basic_desc(&desc[1], 9524 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9525 9526 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 9527 9528 vf_byte_off = vfid / 8; 9529 vf_byte_val = 1 << (vfid % 8); 9530 9531 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9532 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 9533 9534 req0->vlan_id = cpu_to_le16(vlan); 9535 req0->vlan_cfg = is_kill; 9536 9537 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 9538 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 9539 else 9540 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 9541 9542 ret = hclge_cmd_send(&hdev->hw, desc, 2); 9543 if (ret) { 9544 dev_err(&hdev->pdev->dev, 9545 "Send vf vlan command fail, ret =%d.\n", 9546 ret); 9547 return ret; 9548 } 9549 9550 return 0; 9551 } 9552 9553 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid, 9554 bool is_kill, struct hclge_desc *desc) 9555 { 9556 struct hclge_vlan_filter_vf_cfg_cmd *req; 9557 9558 req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9559 9560 if (!is_kill) { 9561 #define HCLGE_VF_VLAN_NO_ENTRY 2 9562 if (!req->resp_code || req->resp_code == 1) 9563 return 0; 9564 9565 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 9566 set_bit(vfid, hdev->vf_vlan_full); 9567 dev_warn(&hdev->pdev->dev, 9568 "vf vlan table is full, vf vlan filter is disabled\n"); 9569 return 0; 9570 } 9571 9572 dev_err(&hdev->pdev->dev, 9573 "Add vf vlan filter fail, ret =%u.\n", 9574 req->resp_code); 9575 } else { 9576 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 9577 if (!req->resp_code) 9578 return 0; 9579 9580 /* vf vlan filter is disabled when vf vlan table is full, 9581 * then new vlan id will not be added into vf vlan table. 9582 * Just return 0 without warning, avoid massive verbose 9583 * print logs when unload. 9584 */ 9585 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) 9586 return 0; 9587 9588 dev_err(&hdev->pdev->dev, 9589 "Kill vf vlan filter fail, ret =%u.\n", 9590 req->resp_code); 9591 } 9592 9593 return -EIO; 9594 } 9595 9596 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid, 9597 bool is_kill, u16 vlan) 9598 { 9599 struct hclge_vport *vport = &hdev->vport[vfid]; 9600 struct hclge_desc desc[2]; 9601 int ret; 9602 9603 /* if vf vlan table is full, firmware will close vf vlan filter, it 9604 * is unable and unnecessary to add new vlan id to vf vlan filter. 9605 * If spoof check is enable, and vf vlan is full, it shouldn't add 9606 * new vlan, because tx packets with these vlan id will be dropped. 9607 */ 9608 if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) { 9609 if (vport->vf_info.spoofchk && vlan) { 9610 dev_err(&hdev->pdev->dev, 9611 "Can't add vlan due to spoof check is on and vf vlan table is full\n"); 9612 return -EPERM; 9613 } 9614 return 0; 9615 } 9616 9617 ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc); 9618 if (ret) 9619 return ret; 9620 9621 return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc); 9622 } 9623 9624 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 9625 u16 vlan_id, bool is_kill) 9626 { 9627 struct hclge_vlan_filter_pf_cfg_cmd *req; 9628 struct hclge_desc desc; 9629 u8 vlan_offset_byte_val; 9630 u8 vlan_offset_byte; 9631 u8 vlan_offset_160; 9632 int ret; 9633 9634 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 9635 9636 vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP; 9637 vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) / 9638 HCLGE_VLAN_BYTE_SIZE; 9639 vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE); 9640 9641 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 9642 req->vlan_offset = vlan_offset_160; 9643 req->vlan_cfg = is_kill; 9644 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 9645 9646 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9647 if (ret) 9648 dev_err(&hdev->pdev->dev, 9649 "port vlan command, send fail, ret =%d.\n", ret); 9650 return ret; 9651 } 9652 9653 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id, 9654 u16 vlan_id, bool is_kill) 9655 { 9656 /* vlan 0 may be added twice when 8021q module is enabled */ 9657 if (!is_kill && !vlan_id && 9658 test_bit(vport_id, hdev->vlan_table[vlan_id])) 9659 return false; 9660 9661 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 9662 dev_warn(&hdev->pdev->dev, 9663 "Add port vlan failed, vport %u is already in vlan %u\n", 9664 vport_id, vlan_id); 9665 return false; 9666 } 9667 9668 if (is_kill && 9669 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 9670 dev_warn(&hdev->pdev->dev, 9671 "Delete port vlan failed, vport %u is not in vlan %u\n", 9672 vport_id, vlan_id); 9673 return false; 9674 } 9675 9676 return true; 9677 } 9678 9679 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 9680 u16 vport_id, u16 vlan_id, 9681 bool is_kill) 9682 { 9683 u16 vport_idx, vport_num = 0; 9684 int ret; 9685 9686 if (is_kill && !vlan_id) 9687 return 0; 9688 9689 if (vlan_id >= VLAN_N_VID) 9690 return -EINVAL; 9691 9692 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id); 9693 if (ret) { 9694 dev_err(&hdev->pdev->dev, 9695 "Set %u vport vlan filter config fail, ret =%d.\n", 9696 vport_id, ret); 9697 return ret; 9698 } 9699 9700 if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill)) 9701 return 0; 9702 9703 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 9704 vport_num++; 9705 9706 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 9707 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 9708 is_kill); 9709 9710 return ret; 9711 } 9712 9713 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 9714 { 9715 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 9716 struct hclge_vport_vtag_tx_cfg_cmd *req; 9717 struct hclge_dev *hdev = vport->back; 9718 struct hclge_desc desc; 9719 u16 bmap_index; 9720 int status; 9721 9722 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 9723 9724 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 9725 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 9726 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 9727 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 9728 vcfg->accept_tag1 ? 1 : 0); 9729 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 9730 vcfg->accept_untag1 ? 1 : 0); 9731 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 9732 vcfg->accept_tag2 ? 1 : 0); 9733 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 9734 vcfg->accept_untag2 ? 1 : 0); 9735 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 9736 vcfg->insert_tag1_en ? 1 : 0); 9737 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 9738 vcfg->insert_tag2_en ? 1 : 0); 9739 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B, 9740 vcfg->tag_shift_mode_en ? 1 : 0); 9741 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 9742 9743 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9744 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9745 HCLGE_VF_NUM_PER_BYTE; 9746 req->vf_bitmap[bmap_index] = 9747 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9748 9749 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9750 if (status) 9751 dev_err(&hdev->pdev->dev, 9752 "Send port txvlan cfg command fail, ret =%d\n", 9753 status); 9754 9755 return status; 9756 } 9757 9758 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 9759 { 9760 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 9761 struct hclge_vport_vtag_rx_cfg_cmd *req; 9762 struct hclge_dev *hdev = vport->back; 9763 struct hclge_desc desc; 9764 u16 bmap_index; 9765 int status; 9766 9767 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 9768 9769 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 9770 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 9771 vcfg->strip_tag1_en ? 1 : 0); 9772 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 9773 vcfg->strip_tag2_en ? 1 : 0); 9774 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 9775 vcfg->vlan1_vlan_prionly ? 1 : 0); 9776 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 9777 vcfg->vlan2_vlan_prionly ? 1 : 0); 9778 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B, 9779 vcfg->strip_tag1_discard_en ? 1 : 0); 9780 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B, 9781 vcfg->strip_tag2_discard_en ? 1 : 0); 9782 9783 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9784 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9785 HCLGE_VF_NUM_PER_BYTE; 9786 req->vf_bitmap[bmap_index] = 9787 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9788 9789 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9790 if (status) 9791 dev_err(&hdev->pdev->dev, 9792 "Send port rxvlan cfg command fail, ret =%d\n", 9793 status); 9794 9795 return status; 9796 } 9797 9798 static int hclge_vlan_offload_cfg(struct hclge_vport *vport, 9799 u16 port_base_vlan_state, 9800 u16 vlan_tag, u8 qos) 9801 { 9802 int ret; 9803 9804 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9805 vport->txvlan_cfg.accept_tag1 = true; 9806 vport->txvlan_cfg.insert_tag1_en = false; 9807 vport->txvlan_cfg.default_tag1 = 0; 9808 } else { 9809 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev); 9810 9811 vport->txvlan_cfg.accept_tag1 = 9812 ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3; 9813 vport->txvlan_cfg.insert_tag1_en = true; 9814 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) | 9815 vlan_tag; 9816 } 9817 9818 vport->txvlan_cfg.accept_untag1 = true; 9819 9820 /* accept_tag2 and accept_untag2 are not supported on 9821 * pdev revision(0x20), new revision support them, 9822 * this two fields can not be configured by user. 9823 */ 9824 vport->txvlan_cfg.accept_tag2 = true; 9825 vport->txvlan_cfg.accept_untag2 = true; 9826 vport->txvlan_cfg.insert_tag2_en = false; 9827 vport->txvlan_cfg.default_tag2 = 0; 9828 vport->txvlan_cfg.tag_shift_mode_en = true; 9829 9830 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9831 vport->rxvlan_cfg.strip_tag1_en = false; 9832 vport->rxvlan_cfg.strip_tag2_en = 9833 vport->rxvlan_cfg.rx_vlan_offload_en; 9834 vport->rxvlan_cfg.strip_tag2_discard_en = false; 9835 } else { 9836 vport->rxvlan_cfg.strip_tag1_en = 9837 vport->rxvlan_cfg.rx_vlan_offload_en; 9838 vport->rxvlan_cfg.strip_tag2_en = true; 9839 vport->rxvlan_cfg.strip_tag2_discard_en = true; 9840 } 9841 9842 vport->rxvlan_cfg.strip_tag1_discard_en = false; 9843 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 9844 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 9845 9846 ret = hclge_set_vlan_tx_offload_cfg(vport); 9847 if (ret) 9848 return ret; 9849 9850 return hclge_set_vlan_rx_offload_cfg(vport); 9851 } 9852 9853 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 9854 { 9855 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 9856 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 9857 struct hclge_desc desc; 9858 int status; 9859 9860 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 9861 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 9862 rx_req->ot_fst_vlan_type = 9863 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 9864 rx_req->ot_sec_vlan_type = 9865 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 9866 rx_req->in_fst_vlan_type = 9867 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 9868 rx_req->in_sec_vlan_type = 9869 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 9870 9871 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9872 if (status) { 9873 dev_err(&hdev->pdev->dev, 9874 "Send rxvlan protocol type command fail, ret =%d\n", 9875 status); 9876 return status; 9877 } 9878 9879 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 9880 9881 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data; 9882 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 9883 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 9884 9885 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9886 if (status) 9887 dev_err(&hdev->pdev->dev, 9888 "Send txvlan protocol type command fail, ret =%d\n", 9889 status); 9890 9891 return status; 9892 } 9893 9894 static int hclge_init_vlan_filter(struct hclge_dev *hdev) 9895 { 9896 struct hclge_vport *vport; 9897 int ret; 9898 int i; 9899 9900 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9901 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9902 HCLGE_FILTER_FE_EGRESS_V1_B, 9903 true, 0); 9904 9905 /* for revision 0x21, vf vlan filter is per function */ 9906 for (i = 0; i < hdev->num_alloc_vport; i++) { 9907 vport = &hdev->vport[i]; 9908 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9909 HCLGE_FILTER_FE_EGRESS, true, 9910 vport->vport_id); 9911 if (ret) 9912 return ret; 9913 vport->cur_vlan_fltr_en = true; 9914 } 9915 9916 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9917 HCLGE_FILTER_FE_INGRESS, true, 0); 9918 } 9919 9920 static int hclge_init_vlan_type(struct hclge_dev *hdev) 9921 { 9922 hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q; 9923 hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q; 9924 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q; 9925 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q; 9926 hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q; 9927 hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q; 9928 9929 return hclge_set_vlan_protocol_type(hdev); 9930 } 9931 9932 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev) 9933 { 9934 struct hclge_port_base_vlan_config *cfg; 9935 struct hclge_vport *vport; 9936 int ret; 9937 int i; 9938 9939 for (i = 0; i < hdev->num_alloc_vport; i++) { 9940 vport = &hdev->vport[i]; 9941 cfg = &vport->port_base_vlan_cfg; 9942 9943 ret = hclge_vlan_offload_cfg(vport, cfg->state, 9944 cfg->vlan_info.vlan_tag, 9945 cfg->vlan_info.qos); 9946 if (ret) 9947 return ret; 9948 } 9949 return 0; 9950 } 9951 9952 static int hclge_init_vlan_config(struct hclge_dev *hdev) 9953 { 9954 struct hnae3_handle *handle = &hdev->vport[0].nic; 9955 int ret; 9956 9957 ret = hclge_init_vlan_filter(hdev); 9958 if (ret) 9959 return ret; 9960 9961 ret = hclge_init_vlan_type(hdev); 9962 if (ret) 9963 return ret; 9964 9965 ret = hclge_init_vport_vlan_offload(hdev); 9966 if (ret) 9967 return ret; 9968 9969 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 9970 } 9971 9972 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 9973 bool writen_to_tbl) 9974 { 9975 struct hclge_vport_vlan_cfg *vlan, *tmp; 9976 struct hclge_dev *hdev = vport->back; 9977 9978 mutex_lock(&hdev->vport_lock); 9979 9980 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 9981 if (vlan->vlan_id == vlan_id) { 9982 mutex_unlock(&hdev->vport_lock); 9983 return; 9984 } 9985 } 9986 9987 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 9988 if (!vlan) { 9989 mutex_unlock(&hdev->vport_lock); 9990 return; 9991 } 9992 9993 vlan->hd_tbl_status = writen_to_tbl; 9994 vlan->vlan_id = vlan_id; 9995 9996 list_add_tail(&vlan->node, &vport->vlan_list); 9997 mutex_unlock(&hdev->vport_lock); 9998 } 9999 10000 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport) 10001 { 10002 struct hclge_vport_vlan_cfg *vlan, *tmp; 10003 struct hclge_dev *hdev = vport->back; 10004 int ret; 10005 10006 mutex_lock(&hdev->vport_lock); 10007 10008 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10009 if (!vlan->hd_tbl_status) { 10010 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10011 vport->vport_id, 10012 vlan->vlan_id, false); 10013 if (ret) { 10014 dev_err(&hdev->pdev->dev, 10015 "restore vport vlan list failed, ret=%d\n", 10016 ret); 10017 10018 mutex_unlock(&hdev->vport_lock); 10019 return ret; 10020 } 10021 } 10022 vlan->hd_tbl_status = true; 10023 } 10024 10025 mutex_unlock(&hdev->vport_lock); 10026 10027 return 0; 10028 } 10029 10030 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10031 bool is_write_tbl) 10032 { 10033 struct hclge_vport_vlan_cfg *vlan, *tmp; 10034 struct hclge_dev *hdev = vport->back; 10035 10036 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10037 if (vlan->vlan_id == vlan_id) { 10038 if (is_write_tbl && vlan->hd_tbl_status) 10039 hclge_set_vlan_filter_hw(hdev, 10040 htons(ETH_P_8021Q), 10041 vport->vport_id, 10042 vlan_id, 10043 true); 10044 10045 list_del(&vlan->node); 10046 kfree(vlan); 10047 break; 10048 } 10049 } 10050 } 10051 10052 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list) 10053 { 10054 struct hclge_vport_vlan_cfg *vlan, *tmp; 10055 struct hclge_dev *hdev = vport->back; 10056 10057 mutex_lock(&hdev->vport_lock); 10058 10059 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10060 if (vlan->hd_tbl_status) 10061 hclge_set_vlan_filter_hw(hdev, 10062 htons(ETH_P_8021Q), 10063 vport->vport_id, 10064 vlan->vlan_id, 10065 true); 10066 10067 vlan->hd_tbl_status = false; 10068 if (is_del_list) { 10069 list_del(&vlan->node); 10070 kfree(vlan); 10071 } 10072 } 10073 clear_bit(vport->vport_id, hdev->vf_vlan_full); 10074 mutex_unlock(&hdev->vport_lock); 10075 } 10076 10077 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev) 10078 { 10079 struct hclge_vport_vlan_cfg *vlan, *tmp; 10080 struct hclge_vport *vport; 10081 int i; 10082 10083 mutex_lock(&hdev->vport_lock); 10084 10085 for (i = 0; i < hdev->num_alloc_vport; i++) { 10086 vport = &hdev->vport[i]; 10087 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10088 list_del(&vlan->node); 10089 kfree(vlan); 10090 } 10091 } 10092 10093 mutex_unlock(&hdev->vport_lock); 10094 } 10095 10096 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev) 10097 { 10098 struct hclge_vlan_info *vlan_info; 10099 struct hclge_vport *vport; 10100 u16 vlan_proto; 10101 u16 vlan_id; 10102 u16 state; 10103 int vf_id; 10104 int ret; 10105 10106 /* PF should restore all vfs port base vlan */ 10107 for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) { 10108 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM]; 10109 vlan_info = vport->port_base_vlan_cfg.tbl_sta ? 10110 &vport->port_base_vlan_cfg.vlan_info : 10111 &vport->port_base_vlan_cfg.old_vlan_info; 10112 10113 vlan_id = vlan_info->vlan_tag; 10114 vlan_proto = vlan_info->vlan_proto; 10115 state = vport->port_base_vlan_cfg.state; 10116 10117 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) { 10118 clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]); 10119 ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto), 10120 vport->vport_id, 10121 vlan_id, false); 10122 vport->port_base_vlan_cfg.tbl_sta = ret == 0; 10123 } 10124 } 10125 } 10126 10127 void hclge_restore_vport_vlan_table(struct hclge_vport *vport) 10128 { 10129 struct hclge_vport_vlan_cfg *vlan, *tmp; 10130 struct hclge_dev *hdev = vport->back; 10131 int ret; 10132 10133 mutex_lock(&hdev->vport_lock); 10134 10135 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10136 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10137 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10138 vport->vport_id, 10139 vlan->vlan_id, false); 10140 if (ret) 10141 break; 10142 vlan->hd_tbl_status = true; 10143 } 10144 } 10145 10146 mutex_unlock(&hdev->vport_lock); 10147 } 10148 10149 /* For global reset and imp reset, hardware will clear the mac table, 10150 * so we change the mac address state from ACTIVE to TO_ADD, then they 10151 * can be restored in the service task after reset complete. Furtherly, 10152 * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to 10153 * be restored after reset, so just remove these mac nodes from mac_list. 10154 */ 10155 static void hclge_mac_node_convert_for_reset(struct list_head *list) 10156 { 10157 struct hclge_mac_node *mac_node, *tmp; 10158 10159 list_for_each_entry_safe(mac_node, tmp, list, node) { 10160 if (mac_node->state == HCLGE_MAC_ACTIVE) { 10161 mac_node->state = HCLGE_MAC_TO_ADD; 10162 } else if (mac_node->state == HCLGE_MAC_TO_DEL) { 10163 list_del(&mac_node->node); 10164 kfree(mac_node); 10165 } 10166 } 10167 } 10168 10169 void hclge_restore_mac_table_common(struct hclge_vport *vport) 10170 { 10171 spin_lock_bh(&vport->mac_list_lock); 10172 10173 hclge_mac_node_convert_for_reset(&vport->uc_mac_list); 10174 hclge_mac_node_convert_for_reset(&vport->mc_mac_list); 10175 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 10176 10177 spin_unlock_bh(&vport->mac_list_lock); 10178 } 10179 10180 static void hclge_restore_hw_table(struct hclge_dev *hdev) 10181 { 10182 struct hclge_vport *vport = &hdev->vport[0]; 10183 struct hnae3_handle *handle = &vport->nic; 10184 10185 hclge_restore_mac_table_common(vport); 10186 hclge_restore_vport_port_base_vlan_config(hdev); 10187 hclge_restore_vport_vlan_table(vport); 10188 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 10189 hclge_restore_fd_entries(handle); 10190 } 10191 10192 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 10193 { 10194 struct hclge_vport *vport = hclge_get_vport(handle); 10195 10196 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10197 vport->rxvlan_cfg.strip_tag1_en = false; 10198 vport->rxvlan_cfg.strip_tag2_en = enable; 10199 vport->rxvlan_cfg.strip_tag2_discard_en = false; 10200 } else { 10201 vport->rxvlan_cfg.strip_tag1_en = enable; 10202 vport->rxvlan_cfg.strip_tag2_en = true; 10203 vport->rxvlan_cfg.strip_tag2_discard_en = true; 10204 } 10205 10206 vport->rxvlan_cfg.strip_tag1_discard_en = false; 10207 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 10208 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 10209 vport->rxvlan_cfg.rx_vlan_offload_en = enable; 10210 10211 return hclge_set_vlan_rx_offload_cfg(vport); 10212 } 10213 10214 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport) 10215 { 10216 struct hclge_dev *hdev = vport->back; 10217 10218 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 10219 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state); 10220 } 10221 10222 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport, 10223 u16 port_base_vlan_state, 10224 struct hclge_vlan_info *new_info, 10225 struct hclge_vlan_info *old_info) 10226 { 10227 struct hclge_dev *hdev = vport->back; 10228 int ret; 10229 10230 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) { 10231 hclge_rm_vport_all_vlan_table(vport, false); 10232 /* force clear VLAN 0 */ 10233 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0); 10234 if (ret) 10235 return ret; 10236 return hclge_set_vlan_filter_hw(hdev, 10237 htons(new_info->vlan_proto), 10238 vport->vport_id, 10239 new_info->vlan_tag, 10240 false); 10241 } 10242 10243 vport->port_base_vlan_cfg.tbl_sta = false; 10244 10245 /* force add VLAN 0 */ 10246 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0); 10247 if (ret) 10248 return ret; 10249 10250 ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto), 10251 vport->vport_id, old_info->vlan_tag, 10252 true); 10253 if (ret) 10254 return ret; 10255 10256 return hclge_add_vport_all_vlan_table(vport); 10257 } 10258 10259 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg, 10260 const struct hclge_vlan_info *old_cfg) 10261 { 10262 if (new_cfg->vlan_tag != old_cfg->vlan_tag) 10263 return true; 10264 10265 if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0)) 10266 return true; 10267 10268 return false; 10269 } 10270 10271 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport, 10272 struct hclge_vlan_info *new_info, 10273 struct hclge_vlan_info *old_info) 10274 { 10275 struct hclge_dev *hdev = vport->back; 10276 int ret; 10277 10278 /* add new VLAN tag */ 10279 ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto), 10280 vport->vport_id, new_info->vlan_tag, 10281 false); 10282 if (ret) 10283 return ret; 10284 10285 vport->port_base_vlan_cfg.tbl_sta = false; 10286 /* remove old VLAN tag */ 10287 if (old_info->vlan_tag == 0) 10288 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, 10289 true, 0); 10290 else 10291 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10292 vport->vport_id, 10293 old_info->vlan_tag, true); 10294 if (ret) 10295 dev_err(&hdev->pdev->dev, 10296 "failed to clear vport%u port base vlan %u, ret = %d.\n", 10297 vport->vport_id, old_info->vlan_tag, ret); 10298 10299 return ret; 10300 } 10301 10302 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 10303 struct hclge_vlan_info *vlan_info) 10304 { 10305 struct hnae3_handle *nic = &vport->nic; 10306 struct hclge_vlan_info *old_vlan_info; 10307 int ret; 10308 10309 old_vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10310 10311 ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag, 10312 vlan_info->qos); 10313 if (ret) 10314 return ret; 10315 10316 if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info)) 10317 goto out; 10318 10319 if (state == HNAE3_PORT_BASE_VLAN_MODIFY) 10320 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info, 10321 old_vlan_info); 10322 else 10323 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info, 10324 old_vlan_info); 10325 if (ret) 10326 return ret; 10327 10328 out: 10329 vport->port_base_vlan_cfg.state = state; 10330 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 10331 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 10332 else 10333 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 10334 10335 vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info; 10336 vport->port_base_vlan_cfg.vlan_info = *vlan_info; 10337 vport->port_base_vlan_cfg.tbl_sta = true; 10338 hclge_set_vport_vlan_fltr_change(vport); 10339 10340 return 0; 10341 } 10342 10343 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport, 10344 enum hnae3_port_base_vlan_state state, 10345 u16 vlan, u8 qos) 10346 { 10347 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10348 if (!vlan && !qos) 10349 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10350 10351 return HNAE3_PORT_BASE_VLAN_ENABLE; 10352 } 10353 10354 if (!vlan && !qos) 10355 return HNAE3_PORT_BASE_VLAN_DISABLE; 10356 10357 if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan && 10358 vport->port_base_vlan_cfg.vlan_info.qos == qos) 10359 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10360 10361 return HNAE3_PORT_BASE_VLAN_MODIFY; 10362 } 10363 10364 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 10365 u16 vlan, u8 qos, __be16 proto) 10366 { 10367 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 10368 struct hclge_vport *vport = hclge_get_vport(handle); 10369 struct hclge_dev *hdev = vport->back; 10370 struct hclge_vlan_info vlan_info; 10371 u16 state; 10372 int ret; 10373 10374 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 10375 return -EOPNOTSUPP; 10376 10377 vport = hclge_get_vf_vport(hdev, vfid); 10378 if (!vport) 10379 return -EINVAL; 10380 10381 /* qos is a 3 bits value, so can not be bigger than 7 */ 10382 if (vlan > VLAN_N_VID - 1 || qos > 7) 10383 return -EINVAL; 10384 if (proto != htons(ETH_P_8021Q)) 10385 return -EPROTONOSUPPORT; 10386 10387 state = hclge_get_port_base_vlan_state(vport, 10388 vport->port_base_vlan_cfg.state, 10389 vlan, qos); 10390 if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE) 10391 return 0; 10392 10393 vlan_info.vlan_tag = vlan; 10394 vlan_info.qos = qos; 10395 vlan_info.vlan_proto = ntohs(proto); 10396 10397 ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info); 10398 if (ret) { 10399 dev_err(&hdev->pdev->dev, 10400 "failed to update port base vlan for vf %d, ret = %d\n", 10401 vfid, ret); 10402 return ret; 10403 } 10404 10405 /* there is a timewindow for PF to know VF unalive, it may 10406 * cause send mailbox fail, but it doesn't matter, VF will 10407 * query it when reinit. 10408 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based 10409 * VLAN state. 10410 */ 10411 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 10412 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 10413 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0], 10414 vport->vport_id, 10415 state, 10416 &vlan_info); 10417 else 10418 set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, 10419 &vport->need_notify); 10420 } 10421 return 0; 10422 } 10423 10424 static void hclge_clear_vf_vlan(struct hclge_dev *hdev) 10425 { 10426 struct hclge_vlan_info *vlan_info; 10427 struct hclge_vport *vport; 10428 int ret; 10429 int vf; 10430 10431 /* clear port base vlan for all vf */ 10432 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 10433 vport = &hdev->vport[vf]; 10434 vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10435 10436 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10437 vport->vport_id, 10438 vlan_info->vlan_tag, true); 10439 if (ret) 10440 dev_err(&hdev->pdev->dev, 10441 "failed to clear vf vlan for vf%d, ret = %d\n", 10442 vf - HCLGE_VF_VPORT_START_NUM, ret); 10443 } 10444 } 10445 10446 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 10447 u16 vlan_id, bool is_kill) 10448 { 10449 struct hclge_vport *vport = hclge_get_vport(handle); 10450 struct hclge_dev *hdev = vport->back; 10451 bool writen_to_tbl = false; 10452 int ret = 0; 10453 10454 /* When device is resetting or reset failed, firmware is unable to 10455 * handle mailbox. Just record the vlan id, and remove it after 10456 * reset finished. 10457 */ 10458 mutex_lock(&hdev->vport_lock); 10459 if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 10460 test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) { 10461 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10462 mutex_unlock(&hdev->vport_lock); 10463 return -EBUSY; 10464 } else if (!is_kill && test_bit(vlan_id, vport->vlan_del_fail_bmap)) { 10465 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10466 } 10467 mutex_unlock(&hdev->vport_lock); 10468 10469 /* when port base vlan enabled, we use port base vlan as the vlan 10470 * filter entry. In this case, we don't update vlan filter table 10471 * when user add new vlan or remove exist vlan, just update the vport 10472 * vlan list. The vlan id in vlan list will be writen in vlan filter 10473 * table until port base vlan disabled 10474 */ 10475 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10476 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, 10477 vlan_id, is_kill); 10478 writen_to_tbl = true; 10479 } 10480 10481 if (!ret) { 10482 if (!is_kill) { 10483 hclge_add_vport_vlan_table(vport, vlan_id, 10484 writen_to_tbl); 10485 } else if (is_kill && vlan_id != 0) { 10486 mutex_lock(&hdev->vport_lock); 10487 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10488 mutex_unlock(&hdev->vport_lock); 10489 } 10490 } else if (is_kill) { 10491 /* when remove hw vlan filter failed, record the vlan id, 10492 * and try to remove it from hw later, to be consistence 10493 * with stack 10494 */ 10495 mutex_lock(&hdev->vport_lock); 10496 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10497 mutex_unlock(&hdev->vport_lock); 10498 } 10499 10500 hclge_set_vport_vlan_fltr_change(vport); 10501 10502 return ret; 10503 } 10504 10505 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev) 10506 { 10507 struct hclge_vport *vport; 10508 int ret; 10509 u16 i; 10510 10511 for (i = 0; i < hdev->num_alloc_vport; i++) { 10512 vport = &hdev->vport[i]; 10513 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10514 &vport->state)) 10515 continue; 10516 10517 ret = hclge_enable_vport_vlan_filter(vport, 10518 vport->req_vlan_fltr_en); 10519 if (ret) { 10520 dev_err(&hdev->pdev->dev, 10521 "failed to sync vlan filter state for vport%u, ret = %d\n", 10522 vport->vport_id, ret); 10523 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10524 &vport->state); 10525 return; 10526 } 10527 } 10528 } 10529 10530 static void hclge_sync_vlan_filter(struct hclge_dev *hdev) 10531 { 10532 #define HCLGE_MAX_SYNC_COUNT 60 10533 10534 int i, ret, sync_cnt = 0; 10535 u16 vlan_id; 10536 10537 mutex_lock(&hdev->vport_lock); 10538 /* start from vport 1 for PF is always alive */ 10539 for (i = 0; i < hdev->num_alloc_vport; i++) { 10540 struct hclge_vport *vport = &hdev->vport[i]; 10541 10542 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10543 VLAN_N_VID); 10544 while (vlan_id != VLAN_N_VID) { 10545 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10546 vport->vport_id, vlan_id, 10547 true); 10548 if (ret && ret != -EINVAL) { 10549 mutex_unlock(&hdev->vport_lock); 10550 return; 10551 } 10552 10553 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10554 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10555 hclge_set_vport_vlan_fltr_change(vport); 10556 10557 sync_cnt++; 10558 if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) { 10559 mutex_unlock(&hdev->vport_lock); 10560 return; 10561 } 10562 10563 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10564 VLAN_N_VID); 10565 } 10566 } 10567 mutex_unlock(&hdev->vport_lock); 10568 10569 hclge_sync_vlan_fltr_state(hdev); 10570 } 10571 10572 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps) 10573 { 10574 struct hclge_config_max_frm_size_cmd *req; 10575 struct hclge_desc desc; 10576 10577 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 10578 10579 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 10580 req->max_frm_size = cpu_to_le16(new_mps); 10581 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 10582 10583 return hclge_cmd_send(&hdev->hw, &desc, 1); 10584 } 10585 10586 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 10587 { 10588 struct hclge_vport *vport = hclge_get_vport(handle); 10589 10590 return hclge_set_vport_mtu(vport, new_mtu); 10591 } 10592 10593 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) 10594 { 10595 struct hclge_dev *hdev = vport->back; 10596 int i, max_frm_size, ret; 10597 10598 /* HW supprt 2 layer vlan */ 10599 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 10600 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 10601 max_frm_size > hdev->ae_dev->dev_specs.max_frm_size) 10602 return -EINVAL; 10603 10604 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 10605 mutex_lock(&hdev->vport_lock); 10606 /* VF's mps must fit within hdev->mps */ 10607 if (vport->vport_id && max_frm_size > hdev->mps) { 10608 mutex_unlock(&hdev->vport_lock); 10609 return -EINVAL; 10610 } else if (vport->vport_id) { 10611 vport->mps = max_frm_size; 10612 mutex_unlock(&hdev->vport_lock); 10613 return 0; 10614 } 10615 10616 /* PF's mps must be greater then VF's mps */ 10617 for (i = 1; i < hdev->num_alloc_vport; i++) 10618 if (max_frm_size < hdev->vport[i].mps) { 10619 dev_err(&hdev->pdev->dev, 10620 "failed to set pf mtu for less than vport %d, mps = %u.\n", 10621 i, hdev->vport[i].mps); 10622 mutex_unlock(&hdev->vport_lock); 10623 return -EINVAL; 10624 } 10625 10626 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 10627 10628 ret = hclge_set_mac_mtu(hdev, max_frm_size); 10629 if (ret) { 10630 dev_err(&hdev->pdev->dev, 10631 "Change mtu fail, ret =%d\n", ret); 10632 goto out; 10633 } 10634 10635 hdev->mps = max_frm_size; 10636 vport->mps = max_frm_size; 10637 10638 ret = hclge_buffer_alloc(hdev); 10639 if (ret) 10640 dev_err(&hdev->pdev->dev, 10641 "Allocate buffer fail, ret =%d\n", ret); 10642 10643 out: 10644 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 10645 mutex_unlock(&hdev->vport_lock); 10646 return ret; 10647 } 10648 10649 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id, 10650 bool enable) 10651 { 10652 struct hclge_reset_tqp_queue_cmd *req; 10653 struct hclge_desc desc; 10654 int ret; 10655 10656 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 10657 10658 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10659 req->tqp_id = cpu_to_le16(queue_id); 10660 if (enable) 10661 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U); 10662 10663 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10664 if (ret) { 10665 dev_err(&hdev->pdev->dev, 10666 "Send tqp reset cmd error, status =%d\n", ret); 10667 return ret; 10668 } 10669 10670 return 0; 10671 } 10672 10673 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id, 10674 u8 *reset_status) 10675 { 10676 struct hclge_reset_tqp_queue_cmd *req; 10677 struct hclge_desc desc; 10678 int ret; 10679 10680 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 10681 10682 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10683 req->tqp_id = cpu_to_le16(queue_id); 10684 10685 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10686 if (ret) { 10687 dev_err(&hdev->pdev->dev, 10688 "Get reset status error, status =%d\n", ret); 10689 return ret; 10690 } 10691 10692 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 10693 10694 return 0; 10695 } 10696 10697 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id) 10698 { 10699 struct hclge_comm_tqp *tqp; 10700 struct hnae3_queue *queue; 10701 10702 queue = handle->kinfo.tqp[queue_id]; 10703 tqp = container_of(queue, struct hclge_comm_tqp, q); 10704 10705 return tqp->index; 10706 } 10707 10708 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle) 10709 { 10710 struct hclge_vport *vport = hclge_get_vport(handle); 10711 struct hclge_dev *hdev = vport->back; 10712 u16 reset_try_times = 0; 10713 u8 reset_status; 10714 u16 queue_gid; 10715 int ret; 10716 u16 i; 10717 10718 for (i = 0; i < handle->kinfo.num_tqps; i++) { 10719 queue_gid = hclge_covert_handle_qid_global(handle, i); 10720 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true); 10721 if (ret) { 10722 dev_err(&hdev->pdev->dev, 10723 "failed to send reset tqp cmd, ret = %d\n", 10724 ret); 10725 return ret; 10726 } 10727 10728 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 10729 ret = hclge_get_reset_status(hdev, queue_gid, 10730 &reset_status); 10731 if (ret) 10732 return ret; 10733 10734 if (reset_status) 10735 break; 10736 10737 /* Wait for tqp hw reset */ 10738 usleep_range(1000, 1200); 10739 } 10740 10741 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 10742 dev_err(&hdev->pdev->dev, 10743 "wait for tqp hw reset timeout\n"); 10744 return -ETIME; 10745 } 10746 10747 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false); 10748 if (ret) { 10749 dev_err(&hdev->pdev->dev, 10750 "failed to deassert soft reset, ret = %d\n", 10751 ret); 10752 return ret; 10753 } 10754 reset_try_times = 0; 10755 } 10756 return 0; 10757 } 10758 10759 static int hclge_reset_rcb(struct hnae3_handle *handle) 10760 { 10761 #define HCLGE_RESET_RCB_NOT_SUPPORT 0U 10762 #define HCLGE_RESET_RCB_SUCCESS 1U 10763 10764 struct hclge_vport *vport = hclge_get_vport(handle); 10765 struct hclge_dev *hdev = vport->back; 10766 struct hclge_reset_cmd *req; 10767 struct hclge_desc desc; 10768 u8 return_status; 10769 u16 queue_gid; 10770 int ret; 10771 10772 queue_gid = hclge_covert_handle_qid_global(handle, 0); 10773 10774 req = (struct hclge_reset_cmd *)desc.data; 10775 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 10776 hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1); 10777 req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid); 10778 req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps); 10779 10780 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10781 if (ret) { 10782 dev_err(&hdev->pdev->dev, 10783 "failed to send rcb reset cmd, ret = %d\n", ret); 10784 return ret; 10785 } 10786 10787 return_status = req->fun_reset_rcb_return_status; 10788 if (return_status == HCLGE_RESET_RCB_SUCCESS) 10789 return 0; 10790 10791 if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) { 10792 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n", 10793 return_status); 10794 return -EIO; 10795 } 10796 10797 /* if reset rcb cmd is unsupported, we need to send reset tqp cmd 10798 * again to reset all tqps 10799 */ 10800 return hclge_reset_tqp_cmd(handle); 10801 } 10802 10803 int hclge_reset_tqp(struct hnae3_handle *handle) 10804 { 10805 struct hclge_vport *vport = hclge_get_vport(handle); 10806 struct hclge_dev *hdev = vport->back; 10807 int ret; 10808 10809 /* only need to disable PF's tqp */ 10810 if (!vport->vport_id) { 10811 ret = hclge_tqp_enable(handle, false); 10812 if (ret) { 10813 dev_err(&hdev->pdev->dev, 10814 "failed to disable tqp, ret = %d\n", ret); 10815 return ret; 10816 } 10817 } 10818 10819 return hclge_reset_rcb(handle); 10820 } 10821 10822 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 10823 { 10824 struct hclge_vport *vport = hclge_get_vport(handle); 10825 struct hclge_dev *hdev = vport->back; 10826 10827 return hdev->fw_version; 10828 } 10829 10830 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10831 { 10832 struct phy_device *phydev = hdev->hw.mac.phydev; 10833 10834 if (!phydev) 10835 return; 10836 10837 phy_set_asym_pause(phydev, rx_en, tx_en); 10838 } 10839 10840 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10841 { 10842 int ret; 10843 10844 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 10845 return 0; 10846 10847 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 10848 if (ret) 10849 dev_err(&hdev->pdev->dev, 10850 "configure pauseparam error, ret = %d.\n", ret); 10851 10852 return ret; 10853 } 10854 10855 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 10856 { 10857 struct phy_device *phydev = hdev->hw.mac.phydev; 10858 u16 remote_advertising = 0; 10859 u16 local_advertising; 10860 u32 rx_pause, tx_pause; 10861 u8 flowctl; 10862 10863 if (!phydev->link) 10864 return 0; 10865 10866 if (!phydev->autoneg) 10867 return hclge_mac_pause_setup_hw(hdev); 10868 10869 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising); 10870 10871 if (phydev->pause) 10872 remote_advertising = LPA_PAUSE_CAP; 10873 10874 if (phydev->asym_pause) 10875 remote_advertising |= LPA_PAUSE_ASYM; 10876 10877 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 10878 remote_advertising); 10879 tx_pause = flowctl & FLOW_CTRL_TX; 10880 rx_pause = flowctl & FLOW_CTRL_RX; 10881 10882 if (phydev->duplex == HCLGE_MAC_HALF) { 10883 tx_pause = 0; 10884 rx_pause = 0; 10885 } 10886 10887 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 10888 } 10889 10890 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 10891 u32 *rx_en, u32 *tx_en) 10892 { 10893 struct hclge_vport *vport = hclge_get_vport(handle); 10894 struct hclge_dev *hdev = vport->back; 10895 u8 media_type = hdev->hw.mac.media_type; 10896 10897 *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ? 10898 hclge_get_autoneg(handle) : 0; 10899 10900 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 10901 *rx_en = 0; 10902 *tx_en = 0; 10903 return; 10904 } 10905 10906 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 10907 *rx_en = 1; 10908 *tx_en = 0; 10909 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 10910 *tx_en = 1; 10911 *rx_en = 0; 10912 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 10913 *rx_en = 1; 10914 *tx_en = 1; 10915 } else { 10916 *rx_en = 0; 10917 *tx_en = 0; 10918 } 10919 } 10920 10921 static void hclge_record_user_pauseparam(struct hclge_dev *hdev, 10922 u32 rx_en, u32 tx_en) 10923 { 10924 if (rx_en && tx_en) 10925 hdev->fc_mode_last_time = HCLGE_FC_FULL; 10926 else if (rx_en && !tx_en) 10927 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 10928 else if (!rx_en && tx_en) 10929 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 10930 else 10931 hdev->fc_mode_last_time = HCLGE_FC_NONE; 10932 10933 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 10934 } 10935 10936 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 10937 u32 rx_en, u32 tx_en) 10938 { 10939 struct hclge_vport *vport = hclge_get_vport(handle); 10940 struct hclge_dev *hdev = vport->back; 10941 struct phy_device *phydev = hdev->hw.mac.phydev; 10942 u32 fc_autoneg; 10943 10944 if (phydev || hnae3_dev_phy_imp_supported(hdev)) { 10945 fc_autoneg = hclge_get_autoneg(handle); 10946 if (auto_neg != fc_autoneg) { 10947 dev_info(&hdev->pdev->dev, 10948 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 10949 return -EOPNOTSUPP; 10950 } 10951 } 10952 10953 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 10954 dev_info(&hdev->pdev->dev, 10955 "Priority flow control enabled. Cannot set link flow control.\n"); 10956 return -EOPNOTSUPP; 10957 } 10958 10959 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 10960 10961 hclge_record_user_pauseparam(hdev, rx_en, tx_en); 10962 10963 if (!auto_neg || hnae3_dev_phy_imp_supported(hdev)) 10964 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 10965 10966 if (phydev) 10967 return phy_start_aneg(phydev); 10968 10969 return -EOPNOTSUPP; 10970 } 10971 10972 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 10973 u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num) 10974 { 10975 struct hclge_vport *vport = hclge_get_vport(handle); 10976 struct hclge_dev *hdev = vport->back; 10977 10978 if (speed) 10979 *speed = hdev->hw.mac.speed; 10980 if (duplex) 10981 *duplex = hdev->hw.mac.duplex; 10982 if (auto_neg) 10983 *auto_neg = hdev->hw.mac.autoneg; 10984 if (lane_num) 10985 *lane_num = hdev->hw.mac.lane_num; 10986 } 10987 10988 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type, 10989 u8 *module_type) 10990 { 10991 struct hclge_vport *vport = hclge_get_vport(handle); 10992 struct hclge_dev *hdev = vport->back; 10993 10994 /* When nic is down, the service task is not running, doesn't update 10995 * the port information per second. Query the port information before 10996 * return the media type, ensure getting the correct media information. 10997 */ 10998 hclge_update_port_info(hdev); 10999 11000 if (media_type) 11001 *media_type = hdev->hw.mac.media_type; 11002 11003 if (module_type) 11004 *module_type = hdev->hw.mac.module_type; 11005 } 11006 11007 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 11008 u8 *tp_mdix_ctrl, u8 *tp_mdix) 11009 { 11010 struct hclge_vport *vport = hclge_get_vport(handle); 11011 struct hclge_dev *hdev = vport->back; 11012 struct phy_device *phydev = hdev->hw.mac.phydev; 11013 int mdix_ctrl, mdix, is_resolved; 11014 unsigned int retval; 11015 11016 if (!phydev) { 11017 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11018 *tp_mdix = ETH_TP_MDI_INVALID; 11019 return; 11020 } 11021 11022 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 11023 11024 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 11025 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 11026 HCLGE_PHY_MDIX_CTRL_S); 11027 11028 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 11029 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 11030 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 11031 11032 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 11033 11034 switch (mdix_ctrl) { 11035 case 0x0: 11036 *tp_mdix_ctrl = ETH_TP_MDI; 11037 break; 11038 case 0x1: 11039 *tp_mdix_ctrl = ETH_TP_MDI_X; 11040 break; 11041 case 0x3: 11042 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 11043 break; 11044 default: 11045 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11046 break; 11047 } 11048 11049 if (!is_resolved) 11050 *tp_mdix = ETH_TP_MDI_INVALID; 11051 else if (mdix) 11052 *tp_mdix = ETH_TP_MDI_X; 11053 else 11054 *tp_mdix = ETH_TP_MDI; 11055 } 11056 11057 static void hclge_info_show(struct hclge_dev *hdev) 11058 { 11059 struct hnae3_handle *handle = &hdev->vport->nic; 11060 struct device *dev = &hdev->pdev->dev; 11061 11062 dev_info(dev, "PF info begin:\n"); 11063 11064 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 11065 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 11066 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 11067 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 11068 dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs); 11069 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 11070 dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size); 11071 dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size); 11072 dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size); 11073 dev_info(dev, "This is %s PF\n", 11074 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main"); 11075 dev_info(dev, "DCB %s\n", 11076 handle->kinfo.tc_info.dcb_ets_active ? "enable" : "disable"); 11077 dev_info(dev, "MQPRIO %s\n", 11078 handle->kinfo.tc_info.mqprio_active ? "enable" : "disable"); 11079 dev_info(dev, "Default tx spare buffer size: %u\n", 11080 hdev->tx_spare_buf_size); 11081 11082 dev_info(dev, "PF info end.\n"); 11083 } 11084 11085 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 11086 struct hclge_vport *vport) 11087 { 11088 struct hnae3_client *client = vport->nic.client; 11089 struct hclge_dev *hdev = ae_dev->priv; 11090 int rst_cnt = hdev->rst_stats.reset_cnt; 11091 int ret; 11092 11093 ret = client->ops->init_instance(&vport->nic); 11094 if (ret) 11095 return ret; 11096 11097 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11098 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11099 rst_cnt != hdev->rst_stats.reset_cnt) { 11100 ret = -EBUSY; 11101 goto init_nic_err; 11102 } 11103 11104 /* Enable nic hw error interrupts */ 11105 ret = hclge_config_nic_hw_error(hdev, true); 11106 if (ret) { 11107 dev_err(&ae_dev->pdev->dev, 11108 "fail(%d) to enable hw error interrupts\n", ret); 11109 goto init_nic_err; 11110 } 11111 11112 hnae3_set_client_init_flag(client, ae_dev, 1); 11113 11114 if (netif_msg_drv(&hdev->vport->nic)) 11115 hclge_info_show(hdev); 11116 11117 return ret; 11118 11119 init_nic_err: 11120 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11121 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11122 msleep(HCLGE_WAIT_RESET_DONE); 11123 11124 client->ops->uninit_instance(&vport->nic, 0); 11125 11126 return ret; 11127 } 11128 11129 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 11130 struct hclge_vport *vport) 11131 { 11132 struct hclge_dev *hdev = ae_dev->priv; 11133 struct hnae3_client *client; 11134 int rst_cnt; 11135 int ret; 11136 11137 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 11138 !hdev->nic_client) 11139 return 0; 11140 11141 client = hdev->roce_client; 11142 ret = hclge_init_roce_base_info(vport); 11143 if (ret) 11144 return ret; 11145 11146 rst_cnt = hdev->rst_stats.reset_cnt; 11147 ret = client->ops->init_instance(&vport->roce); 11148 if (ret) 11149 return ret; 11150 11151 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11152 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11153 rst_cnt != hdev->rst_stats.reset_cnt) { 11154 ret = -EBUSY; 11155 goto init_roce_err; 11156 } 11157 11158 /* Enable roce ras interrupts */ 11159 ret = hclge_config_rocee_ras_interrupt(hdev, true); 11160 if (ret) { 11161 dev_err(&ae_dev->pdev->dev, 11162 "fail(%d) to enable roce ras interrupts\n", ret); 11163 goto init_roce_err; 11164 } 11165 11166 hnae3_set_client_init_flag(client, ae_dev, 1); 11167 11168 return 0; 11169 11170 init_roce_err: 11171 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11172 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11173 msleep(HCLGE_WAIT_RESET_DONE); 11174 11175 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11176 11177 return ret; 11178 } 11179 11180 static int hclge_init_client_instance(struct hnae3_client *client, 11181 struct hnae3_ae_dev *ae_dev) 11182 { 11183 struct hclge_dev *hdev = ae_dev->priv; 11184 struct hclge_vport *vport = &hdev->vport[0]; 11185 int ret; 11186 11187 switch (client->type) { 11188 case HNAE3_CLIENT_KNIC: 11189 hdev->nic_client = client; 11190 vport->nic.client = client; 11191 ret = hclge_init_nic_client_instance(ae_dev, vport); 11192 if (ret) 11193 goto clear_nic; 11194 11195 ret = hclge_init_roce_client_instance(ae_dev, vport); 11196 if (ret) 11197 goto clear_roce; 11198 11199 break; 11200 case HNAE3_CLIENT_ROCE: 11201 if (hnae3_dev_roce_supported(hdev)) { 11202 hdev->roce_client = client; 11203 vport->roce.client = client; 11204 } 11205 11206 ret = hclge_init_roce_client_instance(ae_dev, vport); 11207 if (ret) 11208 goto clear_roce; 11209 11210 break; 11211 default: 11212 return -EINVAL; 11213 } 11214 11215 return 0; 11216 11217 clear_nic: 11218 hdev->nic_client = NULL; 11219 vport->nic.client = NULL; 11220 return ret; 11221 clear_roce: 11222 hdev->roce_client = NULL; 11223 vport->roce.client = NULL; 11224 return ret; 11225 } 11226 11227 static void hclge_uninit_client_instance(struct hnae3_client *client, 11228 struct hnae3_ae_dev *ae_dev) 11229 { 11230 struct hclge_dev *hdev = ae_dev->priv; 11231 struct hclge_vport *vport = &hdev->vport[0]; 11232 11233 if (hdev->roce_client) { 11234 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11235 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11236 msleep(HCLGE_WAIT_RESET_DONE); 11237 11238 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11239 hdev->roce_client = NULL; 11240 vport->roce.client = NULL; 11241 } 11242 if (client->type == HNAE3_CLIENT_ROCE) 11243 return; 11244 if (hdev->nic_client && client->ops->uninit_instance) { 11245 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11246 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11247 msleep(HCLGE_WAIT_RESET_DONE); 11248 11249 client->ops->uninit_instance(&vport->nic, 0); 11250 hdev->nic_client = NULL; 11251 vport->nic.client = NULL; 11252 } 11253 } 11254 11255 static int hclge_dev_mem_map(struct hclge_dev *hdev) 11256 { 11257 struct pci_dev *pdev = hdev->pdev; 11258 struct hclge_hw *hw = &hdev->hw; 11259 11260 /* for device does not have device memory, return directly */ 11261 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR))) 11262 return 0; 11263 11264 hw->hw.mem_base = 11265 devm_ioremap_wc(&pdev->dev, 11266 pci_resource_start(pdev, HCLGE_MEM_BAR), 11267 pci_resource_len(pdev, HCLGE_MEM_BAR)); 11268 if (!hw->hw.mem_base) { 11269 dev_err(&pdev->dev, "failed to map device memory\n"); 11270 return -EFAULT; 11271 } 11272 11273 return 0; 11274 } 11275 11276 static int hclge_pci_init(struct hclge_dev *hdev) 11277 { 11278 struct pci_dev *pdev = hdev->pdev; 11279 struct hclge_hw *hw; 11280 int ret; 11281 11282 ret = pci_enable_device(pdev); 11283 if (ret) { 11284 dev_err(&pdev->dev, "failed to enable PCI device\n"); 11285 return ret; 11286 } 11287 11288 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 11289 if (ret) { 11290 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 11291 if (ret) { 11292 dev_err(&pdev->dev, 11293 "can't set consistent PCI DMA"); 11294 goto err_disable_device; 11295 } 11296 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 11297 } 11298 11299 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 11300 if (ret) { 11301 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 11302 goto err_disable_device; 11303 } 11304 11305 pci_set_master(pdev); 11306 hw = &hdev->hw; 11307 hw->hw.io_base = pcim_iomap(pdev, 2, 0); 11308 if (!hw->hw.io_base) { 11309 dev_err(&pdev->dev, "Can't map configuration register space\n"); 11310 ret = -ENOMEM; 11311 goto err_release_regions; 11312 } 11313 11314 ret = hclge_dev_mem_map(hdev); 11315 if (ret) 11316 goto err_unmap_io_base; 11317 11318 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 11319 11320 return 0; 11321 11322 err_unmap_io_base: 11323 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11324 err_release_regions: 11325 pci_release_regions(pdev); 11326 err_disable_device: 11327 pci_disable_device(pdev); 11328 11329 return ret; 11330 } 11331 11332 static void hclge_pci_uninit(struct hclge_dev *hdev) 11333 { 11334 struct pci_dev *pdev = hdev->pdev; 11335 11336 if (hdev->hw.hw.mem_base) 11337 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 11338 11339 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11340 pci_free_irq_vectors(pdev); 11341 pci_release_mem_regions(pdev); 11342 pci_disable_device(pdev); 11343 } 11344 11345 static void hclge_state_init(struct hclge_dev *hdev) 11346 { 11347 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 11348 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11349 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 11350 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11351 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 11352 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 11353 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 11354 } 11355 11356 static void hclge_state_uninit(struct hclge_dev *hdev) 11357 { 11358 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11359 set_bit(HCLGE_STATE_REMOVING, &hdev->state); 11360 11361 if (hdev->reset_timer.function) 11362 del_timer_sync(&hdev->reset_timer); 11363 if (hdev->service_task.work.func) 11364 cancel_delayed_work_sync(&hdev->service_task); 11365 } 11366 11367 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 11368 enum hnae3_reset_type rst_type) 11369 { 11370 #define HCLGE_RESET_RETRY_WAIT_MS 500 11371 #define HCLGE_RESET_RETRY_CNT 5 11372 11373 struct hclge_dev *hdev = ae_dev->priv; 11374 int retry_cnt = 0; 11375 int ret; 11376 11377 while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) { 11378 down(&hdev->reset_sem); 11379 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11380 hdev->reset_type = rst_type; 11381 ret = hclge_reset_prepare(hdev); 11382 if (!ret && !hdev->reset_pending) 11383 break; 11384 11385 dev_err(&hdev->pdev->dev, 11386 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 11387 ret, hdev->reset_pending, retry_cnt); 11388 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11389 up(&hdev->reset_sem); 11390 msleep(HCLGE_RESET_RETRY_WAIT_MS); 11391 } 11392 11393 /* disable misc vector before reset done */ 11394 hclge_enable_vector(&hdev->misc_vector, false); 11395 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 11396 11397 if (hdev->reset_type == HNAE3_FLR_RESET) 11398 hdev->rst_stats.flr_rst_cnt++; 11399 } 11400 11401 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev) 11402 { 11403 struct hclge_dev *hdev = ae_dev->priv; 11404 int ret; 11405 11406 hclge_enable_vector(&hdev->misc_vector, true); 11407 11408 ret = hclge_reset_rebuild(hdev); 11409 if (ret) 11410 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret); 11411 11412 hdev->reset_type = HNAE3_NONE_RESET; 11413 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11414 up(&hdev->reset_sem); 11415 } 11416 11417 static void hclge_clear_resetting_state(struct hclge_dev *hdev) 11418 { 11419 u16 i; 11420 11421 for (i = 0; i < hdev->num_alloc_vport; i++) { 11422 struct hclge_vport *vport = &hdev->vport[i]; 11423 int ret; 11424 11425 /* Send cmd to clear vport's FUNC_RST_ING */ 11426 ret = hclge_set_vf_rst(hdev, vport->vport_id, false); 11427 if (ret) 11428 dev_warn(&hdev->pdev->dev, 11429 "clear vport(%u) rst failed %d!\n", 11430 vport->vport_id, ret); 11431 } 11432 } 11433 11434 static int hclge_clear_hw_resource(struct hclge_dev *hdev) 11435 { 11436 struct hclge_desc desc; 11437 int ret; 11438 11439 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false); 11440 11441 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11442 /* This new command is only supported by new firmware, it will 11443 * fail with older firmware. Error value -EOPNOSUPP can only be 11444 * returned by older firmware running this command, to keep code 11445 * backward compatible we will override this value and return 11446 * success. 11447 */ 11448 if (ret && ret != -EOPNOTSUPP) { 11449 dev_err(&hdev->pdev->dev, 11450 "failed to clear hw resource, ret = %d\n", ret); 11451 return ret; 11452 } 11453 return 0; 11454 } 11455 11456 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev) 11457 { 11458 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11459 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1); 11460 } 11461 11462 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev) 11463 { 11464 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11465 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0); 11466 } 11467 11468 static struct hclge_wol_info *hclge_get_wol_info(struct hnae3_handle *handle) 11469 { 11470 struct hclge_vport *vport = hclge_get_vport(handle); 11471 11472 return &vport->back->hw.mac.wol; 11473 } 11474 11475 static int hclge_get_wol_supported_mode(struct hclge_dev *hdev, 11476 u32 *wol_supported) 11477 { 11478 struct hclge_query_wol_supported_cmd *wol_supported_cmd; 11479 struct hclge_desc desc; 11480 int ret; 11481 11482 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_GET_SUPPORTED_MODE, 11483 true); 11484 wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)desc.data; 11485 11486 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11487 if (ret) { 11488 dev_err(&hdev->pdev->dev, 11489 "failed to query wol supported, ret = %d\n", ret); 11490 return ret; 11491 } 11492 11493 *wol_supported = le32_to_cpu(wol_supported_cmd->supported_wake_mode); 11494 11495 return 0; 11496 } 11497 11498 static int hclge_set_wol_cfg(struct hclge_dev *hdev, 11499 struct hclge_wol_info *wol_info) 11500 { 11501 struct hclge_wol_cfg_cmd *wol_cfg_cmd; 11502 struct hclge_desc desc; 11503 int ret; 11504 11505 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, false); 11506 wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)desc.data; 11507 wol_cfg_cmd->wake_on_lan_mode = cpu_to_le32(wol_info->wol_current_mode); 11508 wol_cfg_cmd->sopass_size = wol_info->wol_sopass_size; 11509 memcpy(wol_cfg_cmd->sopass, wol_info->wol_sopass, SOPASS_MAX); 11510 11511 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11512 if (ret) 11513 dev_err(&hdev->pdev->dev, 11514 "failed to set wol config, ret = %d\n", ret); 11515 11516 return ret; 11517 } 11518 11519 static int hclge_update_wol(struct hclge_dev *hdev) 11520 { 11521 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11522 11523 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11524 return 0; 11525 11526 return hclge_set_wol_cfg(hdev, wol_info); 11527 } 11528 11529 static int hclge_init_wol(struct hclge_dev *hdev) 11530 { 11531 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11532 int ret; 11533 11534 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11535 return 0; 11536 11537 memset(wol_info, 0, sizeof(struct hclge_wol_info)); 11538 ret = hclge_get_wol_supported_mode(hdev, 11539 &wol_info->wol_support_mode); 11540 if (ret) { 11541 wol_info->wol_support_mode = 0; 11542 return ret; 11543 } 11544 11545 return hclge_update_wol(hdev); 11546 } 11547 11548 static void hclge_get_wol(struct hnae3_handle *handle, 11549 struct ethtool_wolinfo *wol) 11550 { 11551 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11552 11553 wol->supported = wol_info->wol_support_mode; 11554 wol->wolopts = wol_info->wol_current_mode; 11555 if (wol_info->wol_current_mode & WAKE_MAGICSECURE) 11556 memcpy(wol->sopass, wol_info->wol_sopass, SOPASS_MAX); 11557 } 11558 11559 static int hclge_set_wol(struct hnae3_handle *handle, 11560 struct ethtool_wolinfo *wol) 11561 { 11562 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11563 struct hclge_vport *vport = hclge_get_vport(handle); 11564 u32 wol_mode; 11565 int ret; 11566 11567 wol_mode = wol->wolopts; 11568 if (wol_mode & ~wol_info->wol_support_mode) 11569 return -EINVAL; 11570 11571 wol_info->wol_current_mode = wol_mode; 11572 if (wol_mode & WAKE_MAGICSECURE) { 11573 memcpy(wol_info->wol_sopass, wol->sopass, SOPASS_MAX); 11574 wol_info->wol_sopass_size = SOPASS_MAX; 11575 } else { 11576 wol_info->wol_sopass_size = 0; 11577 } 11578 11579 ret = hclge_set_wol_cfg(vport->back, wol_info); 11580 if (ret) 11581 wol_info->wol_current_mode = 0; 11582 11583 return ret; 11584 } 11585 11586 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 11587 { 11588 struct pci_dev *pdev = ae_dev->pdev; 11589 struct hclge_dev *hdev; 11590 int ret; 11591 11592 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 11593 if (!hdev) 11594 return -ENOMEM; 11595 11596 hdev->pdev = pdev; 11597 hdev->ae_dev = ae_dev; 11598 hdev->reset_type = HNAE3_NONE_RESET; 11599 hdev->reset_level = HNAE3_FUNC_RESET; 11600 ae_dev->priv = hdev; 11601 11602 /* HW supprt 2 layer vlan */ 11603 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 11604 11605 mutex_init(&hdev->vport_lock); 11606 spin_lock_init(&hdev->fd_rule_lock); 11607 sema_init(&hdev->reset_sem, 1); 11608 11609 ret = hclge_pci_init(hdev); 11610 if (ret) 11611 goto out; 11612 11613 ret = hclge_devlink_init(hdev); 11614 if (ret) 11615 goto err_pci_uninit; 11616 11617 /* Firmware command queue initialize */ 11618 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 11619 if (ret) 11620 goto err_devlink_uninit; 11621 11622 /* Firmware command initialize */ 11623 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 11624 true, hdev->reset_pending); 11625 if (ret) 11626 goto err_cmd_uninit; 11627 11628 ret = hclge_clear_hw_resource(hdev); 11629 if (ret) 11630 goto err_cmd_uninit; 11631 11632 ret = hclge_get_cap(hdev); 11633 if (ret) 11634 goto err_cmd_uninit; 11635 11636 ret = hclge_query_dev_specs(hdev); 11637 if (ret) { 11638 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n", 11639 ret); 11640 goto err_cmd_uninit; 11641 } 11642 11643 ret = hclge_configure(hdev); 11644 if (ret) { 11645 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 11646 goto err_cmd_uninit; 11647 } 11648 11649 ret = hclge_init_msi(hdev); 11650 if (ret) { 11651 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 11652 goto err_cmd_uninit; 11653 } 11654 11655 ret = hclge_misc_irq_init(hdev); 11656 if (ret) 11657 goto err_msi_uninit; 11658 11659 ret = hclge_alloc_tqps(hdev); 11660 if (ret) { 11661 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 11662 goto err_msi_irq_uninit; 11663 } 11664 11665 ret = hclge_alloc_vport(hdev); 11666 if (ret) 11667 goto err_msi_irq_uninit; 11668 11669 ret = hclge_map_tqp(hdev); 11670 if (ret) 11671 goto err_msi_irq_uninit; 11672 11673 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { 11674 clear_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps); 11675 if (hnae3_dev_phy_imp_supported(hdev)) 11676 ret = hclge_update_tp_port_info(hdev); 11677 else 11678 ret = hclge_mac_mdio_config(hdev); 11679 11680 if (ret) 11681 goto err_msi_irq_uninit; 11682 } 11683 11684 ret = hclge_init_umv_space(hdev); 11685 if (ret) 11686 goto err_mdiobus_unreg; 11687 11688 ret = hclge_mac_init(hdev); 11689 if (ret) { 11690 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 11691 goto err_mdiobus_unreg; 11692 } 11693 11694 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 11695 if (ret) { 11696 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 11697 goto err_mdiobus_unreg; 11698 } 11699 11700 ret = hclge_config_gro(hdev); 11701 if (ret) 11702 goto err_mdiobus_unreg; 11703 11704 ret = hclge_init_vlan_config(hdev); 11705 if (ret) { 11706 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 11707 goto err_mdiobus_unreg; 11708 } 11709 11710 ret = hclge_tm_schd_init(hdev); 11711 if (ret) { 11712 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 11713 goto err_mdiobus_unreg; 11714 } 11715 11716 ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev, 11717 &hdev->rss_cfg); 11718 if (ret) { 11719 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 11720 goto err_mdiobus_unreg; 11721 } 11722 11723 ret = hclge_rss_init_hw(hdev); 11724 if (ret) { 11725 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 11726 goto err_mdiobus_unreg; 11727 } 11728 11729 ret = init_mgr_tbl(hdev); 11730 if (ret) { 11731 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 11732 goto err_mdiobus_unreg; 11733 } 11734 11735 ret = hclge_init_fd_config(hdev); 11736 if (ret) { 11737 dev_err(&pdev->dev, 11738 "fd table init fail, ret=%d\n", ret); 11739 goto err_mdiobus_unreg; 11740 } 11741 11742 ret = hclge_ptp_init(hdev); 11743 if (ret) 11744 goto err_mdiobus_unreg; 11745 11746 ret = hclge_update_port_info(hdev); 11747 if (ret) 11748 goto err_mdiobus_unreg; 11749 11750 INIT_KFIFO(hdev->mac_tnl_log); 11751 11752 hclge_dcb_ops_set(hdev); 11753 11754 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0); 11755 INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task); 11756 11757 hclge_clear_all_event_cause(hdev); 11758 hclge_clear_resetting_state(hdev); 11759 11760 /* Log and clear the hw errors those already occurred */ 11761 if (hnae3_dev_ras_imp_supported(hdev)) 11762 hclge_handle_occurred_error(hdev); 11763 else 11764 hclge_handle_all_hns_hw_errors(ae_dev); 11765 11766 /* request delayed reset for the error recovery because an immediate 11767 * global reset on a PF affecting pending initialization of other PFs 11768 */ 11769 if (ae_dev->hw_err_reset_req) { 11770 enum hnae3_reset_type reset_level; 11771 11772 reset_level = hclge_get_reset_level(ae_dev, 11773 &ae_dev->hw_err_reset_req); 11774 hclge_set_def_reset_request(ae_dev, reset_level); 11775 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 11776 } 11777 11778 hclge_init_rxd_adv_layout(hdev); 11779 11780 /* Enable MISC vector(vector0) */ 11781 hclge_enable_vector(&hdev->misc_vector, true); 11782 11783 ret = hclge_init_wol(hdev); 11784 if (ret) 11785 dev_warn(&pdev->dev, 11786 "failed to wake on lan init, ret = %d\n", ret); 11787 11788 hclge_state_init(hdev); 11789 hdev->last_reset_time = jiffies; 11790 11791 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", 11792 HCLGE_DRIVER_NAME); 11793 11794 hclge_task_schedule(hdev, round_jiffies_relative(HZ)); 11795 11796 return 0; 11797 11798 err_mdiobus_unreg: 11799 if (hdev->hw.mac.phydev) 11800 mdiobus_unregister(hdev->hw.mac.mdio_bus); 11801 err_msi_irq_uninit: 11802 hclge_misc_irq_uninit(hdev); 11803 err_msi_uninit: 11804 pci_free_irq_vectors(pdev); 11805 err_cmd_uninit: 11806 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 11807 err_devlink_uninit: 11808 hclge_devlink_uninit(hdev); 11809 err_pci_uninit: 11810 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11811 pci_release_regions(pdev); 11812 pci_disable_device(pdev); 11813 out: 11814 mutex_destroy(&hdev->vport_lock); 11815 return ret; 11816 } 11817 11818 static void hclge_stats_clear(struct hclge_dev *hdev) 11819 { 11820 memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats)); 11821 memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats)); 11822 } 11823 11824 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11825 { 11826 return hclge_config_switch_param(hdev, vf, enable, 11827 HCLGE_SWITCH_ANTI_SPOOF_MASK); 11828 } 11829 11830 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11831 { 11832 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 11833 HCLGE_FILTER_FE_NIC_INGRESS_B, 11834 enable, vf); 11835 } 11836 11837 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) 11838 { 11839 int ret; 11840 11841 ret = hclge_set_mac_spoofchk(hdev, vf, enable); 11842 if (ret) { 11843 dev_err(&hdev->pdev->dev, 11844 "Set vf %d mac spoof check %s failed, ret=%d\n", 11845 vf, enable ? "on" : "off", ret); 11846 return ret; 11847 } 11848 11849 ret = hclge_set_vlan_spoofchk(hdev, vf, enable); 11850 if (ret) 11851 dev_err(&hdev->pdev->dev, 11852 "Set vf %d vlan spoof check %s failed, ret=%d\n", 11853 vf, enable ? "on" : "off", ret); 11854 11855 return ret; 11856 } 11857 11858 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf, 11859 bool enable) 11860 { 11861 struct hclge_vport *vport = hclge_get_vport(handle); 11862 struct hclge_dev *hdev = vport->back; 11863 u32 new_spoofchk = enable ? 1 : 0; 11864 int ret; 11865 11866 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11867 return -EOPNOTSUPP; 11868 11869 vport = hclge_get_vf_vport(hdev, vf); 11870 if (!vport) 11871 return -EINVAL; 11872 11873 if (vport->vf_info.spoofchk == new_spoofchk) 11874 return 0; 11875 11876 if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full)) 11877 dev_warn(&hdev->pdev->dev, 11878 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n", 11879 vf); 11880 else if (enable && hclge_is_umv_space_full(vport, true)) 11881 dev_warn(&hdev->pdev->dev, 11882 "vf %d mac table is full, enable spoof check may cause its packet send fail\n", 11883 vf); 11884 11885 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable); 11886 if (ret) 11887 return ret; 11888 11889 vport->vf_info.spoofchk = new_spoofchk; 11890 return 0; 11891 } 11892 11893 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev) 11894 { 11895 struct hclge_vport *vport = hdev->vport; 11896 int ret; 11897 int i; 11898 11899 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11900 return 0; 11901 11902 /* resume the vf spoof check state after reset */ 11903 for (i = 0; i < hdev->num_alloc_vport; i++) { 11904 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, 11905 vport->vf_info.spoofchk); 11906 if (ret) 11907 return ret; 11908 11909 vport++; 11910 } 11911 11912 return 0; 11913 } 11914 11915 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable) 11916 { 11917 struct hclge_vport *vport = hclge_get_vport(handle); 11918 struct hclge_dev *hdev = vport->back; 11919 u32 new_trusted = enable ? 1 : 0; 11920 11921 vport = hclge_get_vf_vport(hdev, vf); 11922 if (!vport) 11923 return -EINVAL; 11924 11925 if (vport->vf_info.trusted == new_trusted) 11926 return 0; 11927 11928 vport->vf_info.trusted = new_trusted; 11929 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 11930 hclge_task_schedule(hdev, 0); 11931 11932 return 0; 11933 } 11934 11935 static void hclge_reset_vf_rate(struct hclge_dev *hdev) 11936 { 11937 int ret; 11938 int vf; 11939 11940 /* reset vf rate to default value */ 11941 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 11942 struct hclge_vport *vport = &hdev->vport[vf]; 11943 11944 vport->vf_info.max_tx_rate = 0; 11945 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); 11946 if (ret) 11947 dev_err(&hdev->pdev->dev, 11948 "vf%d failed to reset to default, ret=%d\n", 11949 vf - HCLGE_VF_VPORT_START_NUM, ret); 11950 } 11951 } 11952 11953 static int hclge_vf_rate_param_check(struct hclge_dev *hdev, 11954 int min_tx_rate, int max_tx_rate) 11955 { 11956 if (min_tx_rate != 0 || 11957 max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) { 11958 dev_err(&hdev->pdev->dev, 11959 "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n", 11960 min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed); 11961 return -EINVAL; 11962 } 11963 11964 return 0; 11965 } 11966 11967 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf, 11968 int min_tx_rate, int max_tx_rate, bool force) 11969 { 11970 struct hclge_vport *vport = hclge_get_vport(handle); 11971 struct hclge_dev *hdev = vport->back; 11972 int ret; 11973 11974 ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate); 11975 if (ret) 11976 return ret; 11977 11978 vport = hclge_get_vf_vport(hdev, vf); 11979 if (!vport) 11980 return -EINVAL; 11981 11982 if (!force && max_tx_rate == vport->vf_info.max_tx_rate) 11983 return 0; 11984 11985 ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); 11986 if (ret) 11987 return ret; 11988 11989 vport->vf_info.max_tx_rate = max_tx_rate; 11990 11991 return 0; 11992 } 11993 11994 static int hclge_resume_vf_rate(struct hclge_dev *hdev) 11995 { 11996 struct hnae3_handle *handle = &hdev->vport->nic; 11997 struct hclge_vport *vport; 11998 int ret; 11999 int vf; 12000 12001 /* resume the vf max_tx_rate after reset */ 12002 for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) { 12003 vport = hclge_get_vf_vport(hdev, vf); 12004 if (!vport) 12005 return -EINVAL; 12006 12007 /* zero means max rate, after reset, firmware already set it to 12008 * max rate, so just continue. 12009 */ 12010 if (!vport->vf_info.max_tx_rate) 12011 continue; 12012 12013 ret = hclge_set_vf_rate(handle, vf, 0, 12014 vport->vf_info.max_tx_rate, true); 12015 if (ret) { 12016 dev_err(&hdev->pdev->dev, 12017 "vf%d failed to resume tx_rate:%u, ret=%d\n", 12018 vf, vport->vf_info.max_tx_rate, ret); 12019 return ret; 12020 } 12021 } 12022 12023 return 0; 12024 } 12025 12026 static void hclge_reset_vport_state(struct hclge_dev *hdev) 12027 { 12028 struct hclge_vport *vport = hdev->vport; 12029 int i; 12030 12031 for (i = 0; i < hdev->num_alloc_vport; i++) { 12032 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12033 vport++; 12034 } 12035 } 12036 12037 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 12038 { 12039 struct hclge_dev *hdev = ae_dev->priv; 12040 struct pci_dev *pdev = ae_dev->pdev; 12041 int ret; 12042 12043 set_bit(HCLGE_STATE_DOWN, &hdev->state); 12044 12045 hclge_stats_clear(hdev); 12046 /* NOTE: pf reset needn't to clear or restore pf and vf table entry. 12047 * so here should not clean table in memory. 12048 */ 12049 if (hdev->reset_type == HNAE3_IMP_RESET || 12050 hdev->reset_type == HNAE3_GLOBAL_RESET) { 12051 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 12052 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full)); 12053 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport); 12054 hclge_reset_umv_space(hdev); 12055 } 12056 12057 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 12058 true, hdev->reset_pending); 12059 if (ret) { 12060 dev_err(&pdev->dev, "Cmd queue init failed\n"); 12061 return ret; 12062 } 12063 12064 ret = hclge_map_tqp(hdev); 12065 if (ret) { 12066 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 12067 return ret; 12068 } 12069 12070 ret = hclge_mac_init(hdev); 12071 if (ret) { 12072 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 12073 return ret; 12074 } 12075 12076 ret = hclge_tp_port_init(hdev); 12077 if (ret) { 12078 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n", 12079 ret); 12080 return ret; 12081 } 12082 12083 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 12084 if (ret) { 12085 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 12086 return ret; 12087 } 12088 12089 ret = hclge_config_gro(hdev); 12090 if (ret) 12091 return ret; 12092 12093 ret = hclge_init_vlan_config(hdev); 12094 if (ret) { 12095 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 12096 return ret; 12097 } 12098 12099 ret = hclge_tm_init_hw(hdev, true); 12100 if (ret) { 12101 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 12102 return ret; 12103 } 12104 12105 ret = hclge_rss_init_hw(hdev); 12106 if (ret) { 12107 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 12108 return ret; 12109 } 12110 12111 ret = init_mgr_tbl(hdev); 12112 if (ret) { 12113 dev_err(&pdev->dev, 12114 "failed to reinit manager table, ret = %d\n", ret); 12115 return ret; 12116 } 12117 12118 ret = hclge_init_fd_config(hdev); 12119 if (ret) { 12120 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret); 12121 return ret; 12122 } 12123 12124 ret = hclge_ptp_init(hdev); 12125 if (ret) 12126 return ret; 12127 12128 /* Log and clear the hw errors those already occurred */ 12129 if (hnae3_dev_ras_imp_supported(hdev)) 12130 hclge_handle_occurred_error(hdev); 12131 else 12132 hclge_handle_all_hns_hw_errors(ae_dev); 12133 12134 /* Re-enable the hw error interrupts because 12135 * the interrupts get disabled on global reset. 12136 */ 12137 ret = hclge_config_nic_hw_error(hdev, true); 12138 if (ret) { 12139 dev_err(&pdev->dev, 12140 "fail(%d) to re-enable NIC hw error interrupts\n", 12141 ret); 12142 return ret; 12143 } 12144 12145 if (hdev->roce_client) { 12146 ret = hclge_config_rocee_ras_interrupt(hdev, true); 12147 if (ret) { 12148 dev_err(&pdev->dev, 12149 "fail(%d) to re-enable roce ras interrupts\n", 12150 ret); 12151 return ret; 12152 } 12153 } 12154 12155 hclge_reset_vport_state(hdev); 12156 ret = hclge_reset_vport_spoofchk(hdev); 12157 if (ret) 12158 return ret; 12159 12160 ret = hclge_resume_vf_rate(hdev); 12161 if (ret) 12162 return ret; 12163 12164 hclge_init_rxd_adv_layout(hdev); 12165 12166 ret = hclge_update_wol(hdev); 12167 if (ret) 12168 dev_warn(&pdev->dev, 12169 "failed to update wol config, ret = %d\n", ret); 12170 12171 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 12172 HCLGE_DRIVER_NAME); 12173 12174 return 0; 12175 } 12176 12177 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 12178 { 12179 struct hclge_dev *hdev = ae_dev->priv; 12180 struct hclge_mac *mac = &hdev->hw.mac; 12181 12182 hclge_reset_vf_rate(hdev); 12183 hclge_clear_vf_vlan(hdev); 12184 hclge_state_uninit(hdev); 12185 hclge_ptp_uninit(hdev); 12186 hclge_uninit_rxd_adv_layout(hdev); 12187 hclge_uninit_mac_table(hdev); 12188 hclge_del_all_fd_entries(hdev); 12189 12190 if (mac->phydev) 12191 mdiobus_unregister(mac->mdio_bus); 12192 12193 /* Disable MISC vector(vector0) */ 12194 hclge_enable_vector(&hdev->misc_vector, false); 12195 synchronize_irq(hdev->misc_vector.vector_irq); 12196 12197 /* Disable all hw interrupts */ 12198 hclge_config_mac_tnl_int(hdev, false); 12199 hclge_config_nic_hw_error(hdev, false); 12200 hclge_config_rocee_ras_interrupt(hdev, false); 12201 12202 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 12203 hclge_misc_irq_uninit(hdev); 12204 hclge_devlink_uninit(hdev); 12205 hclge_pci_uninit(hdev); 12206 hclge_uninit_vport_vlan_table(hdev); 12207 mutex_destroy(&hdev->vport_lock); 12208 ae_dev->priv = NULL; 12209 } 12210 12211 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 12212 { 12213 struct hclge_vport *vport = hclge_get_vport(handle); 12214 struct hclge_dev *hdev = vport->back; 12215 12216 return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps); 12217 } 12218 12219 static void hclge_get_channels(struct hnae3_handle *handle, 12220 struct ethtool_channels *ch) 12221 { 12222 ch->max_combined = hclge_get_max_channels(handle); 12223 ch->other_count = 1; 12224 ch->max_other = 1; 12225 ch->combined_count = handle->kinfo.rss_size; 12226 } 12227 12228 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 12229 u16 *alloc_tqps, u16 *max_rss_size) 12230 { 12231 struct hclge_vport *vport = hclge_get_vport(handle); 12232 struct hclge_dev *hdev = vport->back; 12233 12234 *alloc_tqps = vport->alloc_tqps; 12235 *max_rss_size = hdev->pf_rss_size_max; 12236 } 12237 12238 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle) 12239 { 12240 struct hclge_vport *vport = hclge_get_vport(handle); 12241 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 12242 struct hclge_dev *hdev = vport->back; 12243 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 12244 u16 tc_valid[HCLGE_MAX_TC_NUM]; 12245 u16 roundup_size; 12246 unsigned int i; 12247 12248 roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size); 12249 roundup_size = ilog2(roundup_size); 12250 /* Set the RSS TC mode according to the new RSS size */ 12251 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 12252 tc_valid[i] = 0; 12253 12254 if (!(hdev->hw_tc_map & BIT(i))) 12255 continue; 12256 12257 tc_valid[i] = 1; 12258 tc_size[i] = roundup_size; 12259 tc_offset[i] = vport->nic.kinfo.rss_size * i; 12260 } 12261 12262 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 12263 tc_size); 12264 } 12265 12266 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 12267 bool rxfh_configured) 12268 { 12269 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 12270 struct hclge_vport *vport = hclge_get_vport(handle); 12271 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 12272 struct hclge_dev *hdev = vport->back; 12273 u16 cur_rss_size = kinfo->rss_size; 12274 u16 cur_tqps = kinfo->num_tqps; 12275 u32 *rss_indir; 12276 unsigned int i; 12277 int ret; 12278 12279 kinfo->req_rss_size = new_tqps_num; 12280 12281 ret = hclge_tm_vport_map_update(hdev); 12282 if (ret) { 12283 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret); 12284 return ret; 12285 } 12286 12287 ret = hclge_set_rss_tc_mode_cfg(handle); 12288 if (ret) 12289 return ret; 12290 12291 /* RSS indirection table has been configured by user */ 12292 if (rxfh_configured) 12293 goto out; 12294 12295 /* Reinitializes the rss indirect table according to the new RSS size */ 12296 rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32), 12297 GFP_KERNEL); 12298 if (!rss_indir) 12299 return -ENOMEM; 12300 12301 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 12302 rss_indir[i] = i % kinfo->rss_size; 12303 12304 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 12305 if (ret) 12306 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 12307 ret); 12308 12309 kfree(rss_indir); 12310 12311 out: 12312 if (!ret) 12313 dev_info(&hdev->pdev->dev, 12314 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 12315 cur_rss_size, kinfo->rss_size, 12316 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 12317 12318 return ret; 12319 } 12320 12321 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 12322 { 12323 struct hclge_set_led_state_cmd *req; 12324 struct hclge_desc desc; 12325 int ret; 12326 12327 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 12328 12329 req = (struct hclge_set_led_state_cmd *)desc.data; 12330 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 12331 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 12332 12333 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12334 if (ret) 12335 dev_err(&hdev->pdev->dev, 12336 "Send set led state cmd error, ret =%d\n", ret); 12337 12338 return ret; 12339 } 12340 12341 enum hclge_led_status { 12342 HCLGE_LED_OFF, 12343 HCLGE_LED_ON, 12344 HCLGE_LED_NO_CHANGE = 0xFF, 12345 }; 12346 12347 static int hclge_set_led_id(struct hnae3_handle *handle, 12348 enum ethtool_phys_id_state status) 12349 { 12350 struct hclge_vport *vport = hclge_get_vport(handle); 12351 struct hclge_dev *hdev = vport->back; 12352 12353 switch (status) { 12354 case ETHTOOL_ID_ACTIVE: 12355 return hclge_set_led_status(hdev, HCLGE_LED_ON); 12356 case ETHTOOL_ID_INACTIVE: 12357 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 12358 default: 12359 return -EINVAL; 12360 } 12361 } 12362 12363 static void hclge_get_link_mode(struct hnae3_handle *handle, 12364 unsigned long *supported, 12365 unsigned long *advertising) 12366 { 12367 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 12368 struct hclge_vport *vport = hclge_get_vport(handle); 12369 struct hclge_dev *hdev = vport->back; 12370 unsigned int idx = 0; 12371 12372 for (; idx < size; idx++) { 12373 supported[idx] = hdev->hw.mac.supported[idx]; 12374 advertising[idx] = hdev->hw.mac.advertising[idx]; 12375 } 12376 } 12377 12378 static int hclge_gro_en(struct hnae3_handle *handle, bool enable) 12379 { 12380 struct hclge_vport *vport = hclge_get_vport(handle); 12381 struct hclge_dev *hdev = vport->back; 12382 bool gro_en_old = hdev->gro_en; 12383 int ret; 12384 12385 hdev->gro_en = enable; 12386 ret = hclge_config_gro(hdev); 12387 if (ret) 12388 hdev->gro_en = gro_en_old; 12389 12390 return ret; 12391 } 12392 12393 static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport) 12394 { 12395 struct hnae3_handle *handle = &vport->nic; 12396 struct hclge_dev *hdev = vport->back; 12397 bool uc_en = false; 12398 bool mc_en = false; 12399 u8 tmp_flags; 12400 bool bc_en; 12401 int ret; 12402 12403 if (vport->last_promisc_flags != vport->overflow_promisc_flags) { 12404 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12405 vport->last_promisc_flags = vport->overflow_promisc_flags; 12406 } 12407 12408 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12409 &vport->state)) 12410 return 0; 12411 12412 /* for PF */ 12413 if (!vport->vport_id) { 12414 tmp_flags = handle->netdev_flags | vport->last_promisc_flags; 12415 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE, 12416 tmp_flags & HNAE3_MPE); 12417 if (!ret) 12418 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 12419 &vport->state); 12420 else 12421 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12422 &vport->state); 12423 return ret; 12424 } 12425 12426 /* for VF */ 12427 if (vport->vf_info.trusted) { 12428 uc_en = vport->vf_info.request_uc_en > 0 || 12429 vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE; 12430 mc_en = vport->vf_info.request_mc_en > 0 || 12431 vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE; 12432 } 12433 bc_en = vport->vf_info.request_bc_en > 0; 12434 12435 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en, 12436 mc_en, bc_en); 12437 if (ret) { 12438 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12439 return ret; 12440 } 12441 hclge_set_vport_vlan_fltr_change(vport); 12442 12443 return 0; 12444 } 12445 12446 static void hclge_sync_promisc_mode(struct hclge_dev *hdev) 12447 { 12448 struct hclge_vport *vport; 12449 int ret; 12450 u16 i; 12451 12452 for (i = 0; i < hdev->num_alloc_vport; i++) { 12453 vport = &hdev->vport[i]; 12454 12455 ret = hclge_sync_vport_promisc_mode(vport); 12456 if (ret) 12457 return; 12458 } 12459 } 12460 12461 static bool hclge_module_existed(struct hclge_dev *hdev) 12462 { 12463 struct hclge_desc desc; 12464 u32 existed; 12465 int ret; 12466 12467 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true); 12468 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12469 if (ret) { 12470 dev_err(&hdev->pdev->dev, 12471 "failed to get SFP exist state, ret = %d\n", ret); 12472 return false; 12473 } 12474 12475 existed = le32_to_cpu(desc.data[0]); 12476 12477 return existed != 0; 12478 } 12479 12480 /* need 6 bds(total 140 bytes) in one reading 12481 * return the number of bytes actually read, 0 means read failed. 12482 */ 12483 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset, 12484 u32 len, u8 *data) 12485 { 12486 struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM]; 12487 struct hclge_sfp_info_bd0_cmd *sfp_info_bd0; 12488 u16 read_len; 12489 u16 copy_len; 12490 int ret; 12491 int i; 12492 12493 /* setup all 6 bds to read module eeprom info. */ 12494 for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12495 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM, 12496 true); 12497 12498 /* bd0~bd4 need next flag */ 12499 if (i < HCLGE_SFP_INFO_CMD_NUM - 1) 12500 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12501 } 12502 12503 /* setup bd0, this bd contains offset and read length. */ 12504 sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data; 12505 sfp_info_bd0->offset = cpu_to_le16((u16)offset); 12506 read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN); 12507 sfp_info_bd0->read_len = cpu_to_le16(read_len); 12508 12509 ret = hclge_cmd_send(&hdev->hw, desc, i); 12510 if (ret) { 12511 dev_err(&hdev->pdev->dev, 12512 "failed to get SFP eeprom info, ret = %d\n", ret); 12513 return 0; 12514 } 12515 12516 /* copy sfp info from bd0 to out buffer. */ 12517 copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN); 12518 memcpy(data, sfp_info_bd0->data, copy_len); 12519 read_len = copy_len; 12520 12521 /* copy sfp info from bd1~bd5 to out buffer if needed. */ 12522 for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12523 if (read_len >= len) 12524 return read_len; 12525 12526 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN); 12527 memcpy(data + read_len, desc[i].data, copy_len); 12528 read_len += copy_len; 12529 } 12530 12531 return read_len; 12532 } 12533 12534 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset, 12535 u32 len, u8 *data) 12536 { 12537 struct hclge_vport *vport = hclge_get_vport(handle); 12538 struct hclge_dev *hdev = vport->back; 12539 u32 read_len = 0; 12540 u16 data_len; 12541 12542 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 12543 return -EOPNOTSUPP; 12544 12545 if (!hclge_module_existed(hdev)) 12546 return -ENXIO; 12547 12548 while (read_len < len) { 12549 data_len = hclge_get_sfp_eeprom_info(hdev, 12550 offset + read_len, 12551 len - read_len, 12552 data + read_len); 12553 if (!data_len) 12554 return -EIO; 12555 12556 read_len += data_len; 12557 } 12558 12559 return 0; 12560 } 12561 12562 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle, 12563 u32 *status_code) 12564 { 12565 struct hclge_vport *vport = hclge_get_vport(handle); 12566 struct hclge_dev *hdev = vport->back; 12567 struct hclge_desc desc; 12568 int ret; 12569 12570 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 12571 return -EOPNOTSUPP; 12572 12573 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true); 12574 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12575 if (ret) { 12576 dev_err(&hdev->pdev->dev, 12577 "failed to query link diagnosis info, ret = %d\n", ret); 12578 return ret; 12579 } 12580 12581 *status_code = le32_to_cpu(desc.data[0]); 12582 return 0; 12583 } 12584 12585 /* After disable sriov, VF still has some config and info need clean, 12586 * which configed by PF. 12587 */ 12588 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid) 12589 { 12590 struct hclge_dev *hdev = vport->back; 12591 struct hclge_vlan_info vlan_info; 12592 int ret; 12593 12594 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 12595 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12596 vport->need_notify = 0; 12597 vport->mps = 0; 12598 12599 /* after disable sriov, clean VF rate configured by PF */ 12600 ret = hclge_tm_qs_shaper_cfg(vport, 0); 12601 if (ret) 12602 dev_err(&hdev->pdev->dev, 12603 "failed to clean vf%d rate config, ret = %d\n", 12604 vfid, ret); 12605 12606 vlan_info.vlan_tag = 0; 12607 vlan_info.qos = 0; 12608 vlan_info.vlan_proto = ETH_P_8021Q; 12609 ret = hclge_update_port_base_vlan_cfg(vport, 12610 HNAE3_PORT_BASE_VLAN_DISABLE, 12611 &vlan_info); 12612 if (ret) 12613 dev_err(&hdev->pdev->dev, 12614 "failed to clean vf%d port base vlan, ret = %d\n", 12615 vfid, ret); 12616 12617 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false); 12618 if (ret) 12619 dev_err(&hdev->pdev->dev, 12620 "failed to clean vf%d spoof config, ret = %d\n", 12621 vfid, ret); 12622 12623 memset(&vport->vf_info, 0, sizeof(vport->vf_info)); 12624 } 12625 12626 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs) 12627 { 12628 struct hclge_dev *hdev = ae_dev->priv; 12629 struct hclge_vport *vport; 12630 int i; 12631 12632 for (i = 0; i < num_vfs; i++) { 12633 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 12634 12635 hclge_clear_vport_vf_info(vport, i); 12636 } 12637 } 12638 12639 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode, 12640 u8 *priority) 12641 { 12642 struct hclge_vport *vport = hclge_get_vport(h); 12643 12644 if (dscp >= HNAE3_MAX_DSCP) 12645 return -EINVAL; 12646 12647 if (tc_mode) 12648 *tc_mode = vport->nic.kinfo.tc_map_mode; 12649 if (priority) 12650 *priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 : 12651 vport->nic.kinfo.dscp_prio[dscp]; 12652 12653 return 0; 12654 } 12655 12656 static const struct hnae3_ae_ops hclge_ops = { 12657 .init_ae_dev = hclge_init_ae_dev, 12658 .uninit_ae_dev = hclge_uninit_ae_dev, 12659 .reset_prepare = hclge_reset_prepare_general, 12660 .reset_done = hclge_reset_done, 12661 .init_client_instance = hclge_init_client_instance, 12662 .uninit_client_instance = hclge_uninit_client_instance, 12663 .map_ring_to_vector = hclge_map_ring_to_vector, 12664 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 12665 .get_vector = hclge_get_vector, 12666 .put_vector = hclge_put_vector, 12667 .set_promisc_mode = hclge_set_promisc_mode, 12668 .request_update_promisc_mode = hclge_request_update_promisc_mode, 12669 .set_loopback = hclge_set_loopback, 12670 .start = hclge_ae_start, 12671 .stop = hclge_ae_stop, 12672 .client_start = hclge_client_start, 12673 .client_stop = hclge_client_stop, 12674 .get_status = hclge_get_status, 12675 .get_ksettings_an_result = hclge_get_ksettings_an_result, 12676 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 12677 .get_media_type = hclge_get_media_type, 12678 .check_port_speed = hclge_check_port_speed, 12679 .get_fec_stats = hclge_get_fec_stats, 12680 .get_fec = hclge_get_fec, 12681 .set_fec = hclge_set_fec, 12682 .get_rss_key_size = hclge_comm_get_rss_key_size, 12683 .get_rss = hclge_get_rss, 12684 .set_rss = hclge_set_rss, 12685 .set_rss_tuple = hclge_set_rss_tuple, 12686 .get_rss_tuple = hclge_get_rss_tuple, 12687 .get_tc_size = hclge_get_tc_size, 12688 .get_mac_addr = hclge_get_mac_addr, 12689 .set_mac_addr = hclge_set_mac_addr, 12690 .do_ioctl = hclge_do_ioctl, 12691 .add_uc_addr = hclge_add_uc_addr, 12692 .rm_uc_addr = hclge_rm_uc_addr, 12693 .add_mc_addr = hclge_add_mc_addr, 12694 .rm_mc_addr = hclge_rm_mc_addr, 12695 .set_autoneg = hclge_set_autoneg, 12696 .get_autoneg = hclge_get_autoneg, 12697 .restart_autoneg = hclge_restart_autoneg, 12698 .halt_autoneg = hclge_halt_autoneg, 12699 .get_pauseparam = hclge_get_pauseparam, 12700 .set_pauseparam = hclge_set_pauseparam, 12701 .set_mtu = hclge_set_mtu, 12702 .reset_queue = hclge_reset_tqp, 12703 .get_stats = hclge_get_stats, 12704 .get_mac_stats = hclge_get_mac_stat, 12705 .update_stats = hclge_update_stats, 12706 .get_strings = hclge_get_strings, 12707 .get_sset_count = hclge_get_sset_count, 12708 .get_fw_version = hclge_get_fw_version, 12709 .get_mdix_mode = hclge_get_mdix_mode, 12710 .enable_vlan_filter = hclge_enable_vlan_filter, 12711 .set_vlan_filter = hclge_set_vlan_filter, 12712 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 12713 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 12714 .reset_event = hclge_reset_event, 12715 .get_reset_level = hclge_get_reset_level, 12716 .set_default_reset_request = hclge_set_def_reset_request, 12717 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 12718 .set_channels = hclge_set_channels, 12719 .get_channels = hclge_get_channels, 12720 .get_regs_len = hclge_get_regs_len, 12721 .get_regs = hclge_get_regs, 12722 .set_led_id = hclge_set_led_id, 12723 .get_link_mode = hclge_get_link_mode, 12724 .add_fd_entry = hclge_add_fd_entry, 12725 .del_fd_entry = hclge_del_fd_entry, 12726 .get_fd_rule_cnt = hclge_get_fd_rule_cnt, 12727 .get_fd_rule_info = hclge_get_fd_rule_info, 12728 .get_fd_all_rules = hclge_get_all_rules, 12729 .enable_fd = hclge_enable_fd, 12730 .add_arfs_entry = hclge_add_fd_entry_by_arfs, 12731 .dbg_read_cmd = hclge_dbg_read_cmd, 12732 .handle_hw_ras_error = hclge_handle_hw_ras_error, 12733 .get_hw_reset_stat = hclge_get_hw_reset_stat, 12734 .ae_dev_resetting = hclge_ae_dev_resetting, 12735 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt, 12736 .set_gro_en = hclge_gro_en, 12737 .get_global_queue_id = hclge_covert_handle_qid_global, 12738 .set_timer_task = hclge_set_timer_task, 12739 .mac_connect_phy = hclge_mac_connect_phy, 12740 .mac_disconnect_phy = hclge_mac_disconnect_phy, 12741 .get_vf_config = hclge_get_vf_config, 12742 .set_vf_link_state = hclge_set_vf_link_state, 12743 .set_vf_spoofchk = hclge_set_vf_spoofchk, 12744 .set_vf_trust = hclge_set_vf_trust, 12745 .set_vf_rate = hclge_set_vf_rate, 12746 .set_vf_mac = hclge_set_vf_mac, 12747 .get_module_eeprom = hclge_get_module_eeprom, 12748 .get_cmdq_stat = hclge_get_cmdq_stat, 12749 .add_cls_flower = hclge_add_cls_flower, 12750 .del_cls_flower = hclge_del_cls_flower, 12751 .cls_flower_active = hclge_is_cls_flower_active, 12752 .get_phy_link_ksettings = hclge_get_phy_link_ksettings, 12753 .set_phy_link_ksettings = hclge_set_phy_link_ksettings, 12754 .set_tx_hwts_info = hclge_ptp_set_tx_info, 12755 .get_rx_hwts = hclge_ptp_get_rx_hwts, 12756 .get_ts_info = hclge_ptp_get_ts_info, 12757 .get_link_diagnosis_info = hclge_get_link_diagnosis_info, 12758 .clean_vf_config = hclge_clean_vport_config, 12759 .get_dscp_prio = hclge_get_dscp_prio, 12760 .get_wol = hclge_get_wol, 12761 .set_wol = hclge_set_wol, 12762 }; 12763 12764 static struct hnae3_ae_algo ae_algo = { 12765 .ops = &hclge_ops, 12766 .pdev_id_table = ae_algo_pci_tbl, 12767 }; 12768 12769 static int __init hclge_init(void) 12770 { 12771 pr_info("%s is initializing\n", HCLGE_NAME); 12772 12773 hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGE_NAME); 12774 if (!hclge_wq) { 12775 pr_err("%s: failed to create workqueue\n", HCLGE_NAME); 12776 return -ENOMEM; 12777 } 12778 12779 hnae3_register_ae_algo(&ae_algo); 12780 12781 return 0; 12782 } 12783 12784 static void __exit hclge_exit(void) 12785 { 12786 hnae3_unregister_ae_algo_prepare(&ae_algo); 12787 hnae3_unregister_ae_algo(&ae_algo); 12788 destroy_workqueue(hclge_wq); 12789 } 12790 module_init(hclge_init); 12791 module_exit(hclge_exit); 12792 12793 MODULE_LICENSE("GPL"); 12794 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 12795 MODULE_DESCRIPTION("HCLGE Driver"); 12796 MODULE_VERSION(HCLGE_MOD_VERSION); 12797