1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/pci.h> 13 #include <linux/platform_device.h> 14 #include <linux/if_vlan.h> 15 #include <linux/crash_dump.h> 16 #include <net/ipv6.h> 17 #include <net/rtnetlink.h> 18 #include "hclge_cmd.h" 19 #include "hclge_dcb.h" 20 #include "hclge_main.h" 21 #include "hclge_mbx.h" 22 #include "hclge_mdio.h" 23 #include "hclge_regs.h" 24 #include "hclge_tm.h" 25 #include "hclge_err.h" 26 #include "hnae3.h" 27 #include "hclge_devlink.h" 28 #include "hclge_comm_cmd.h" 29 30 #define HCLGE_NAME "hclge" 31 32 #define HCLGE_BUF_SIZE_UNIT 256U 33 #define HCLGE_BUF_MUL_BY 2 34 #define HCLGE_BUF_DIV_BY 2 35 #define NEED_RESERVE_TC_NUM 2 36 #define BUF_MAX_PERCENT 100 37 #define BUF_RESERVE_PERCENT 90 38 39 #define HCLGE_RESET_MAX_FAIL_CNT 5 40 #define HCLGE_RESET_SYNC_TIME 100 41 #define HCLGE_PF_RESET_SYNC_TIME 20 42 #define HCLGE_PF_RESET_SYNC_CNT 1500 43 44 #define HCLGE_LINK_STATUS_MS 10 45 46 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps); 47 static int hclge_init_vlan_config(struct hclge_dev *hdev); 48 static void hclge_sync_vlan_filter(struct hclge_dev *hdev); 49 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 50 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle); 51 static void hclge_rfs_filter_expire(struct hclge_dev *hdev); 52 static int hclge_clear_arfs_rules(struct hclge_dev *hdev); 53 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 54 unsigned long *addr); 55 static int hclge_set_default_loopback(struct hclge_dev *hdev); 56 57 static void hclge_sync_mac_table(struct hclge_dev *hdev); 58 static void hclge_restore_hw_table(struct hclge_dev *hdev); 59 static void hclge_sync_promisc_mode(struct hclge_dev *hdev); 60 static void hclge_sync_fd_table(struct hclge_dev *hdev); 61 static void hclge_update_fec_stats(struct hclge_dev *hdev); 62 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 63 int wait_cnt); 64 static int hclge_update_port_info(struct hclge_dev *hdev); 65 66 static struct hnae3_ae_algo ae_algo; 67 68 static struct workqueue_struct *hclge_wq; 69 70 static const struct pci_device_id ae_algo_pci_tbl[] = { 71 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 72 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 75 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 77 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 79 /* required last entry */ 80 {0, } 81 }; 82 83 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 84 85 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 86 "External Loopback test", 87 "App Loopback test", 88 "Serdes serial Loopback test", 89 "Serdes parallel Loopback test", 90 "Phy Loopback test" 91 }; 92 93 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 94 {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 95 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 96 {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 97 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 98 {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 99 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)}, 100 {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 101 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)}, 102 {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 103 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)}, 104 {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 105 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)}, 106 {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 107 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)}, 108 {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 109 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 110 {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 111 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 112 {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 113 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 114 {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 115 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 116 {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 117 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 118 {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 119 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 120 {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 121 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 122 {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 123 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 124 {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 125 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)}, 126 {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 127 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)}, 128 {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 129 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)}, 130 {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 131 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)}, 132 {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 133 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)}, 134 {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 135 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)}, 136 {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 137 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)}, 138 {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 139 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)}, 140 {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 141 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)}, 142 {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 143 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 144 {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 145 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 146 {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 147 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 148 {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 149 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 150 {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 151 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 152 {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 153 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 154 {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 155 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 156 {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 157 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 158 {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 159 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)}, 160 {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 161 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)}, 162 {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 163 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)}, 164 {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 165 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)}, 166 {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 167 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)}, 168 {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 169 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)}, 170 {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 171 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)}, 172 {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 173 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)}, 174 {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 175 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 176 {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 177 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 178 {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 179 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 180 {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 181 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 182 {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 183 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 184 {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 185 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 186 {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 187 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 188 {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 189 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 190 {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 191 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 192 {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 193 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 194 {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 195 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 196 {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 197 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 198 {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 199 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 200 {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 201 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 202 {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 203 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 204 {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 205 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 206 {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 207 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 208 {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 209 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 210 {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 211 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 212 {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 213 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 214 {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 215 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 216 {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 217 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 218 {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 219 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 220 {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 221 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 222 {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 223 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 224 {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 225 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 226 {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 228 {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 230 {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 231 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 232 {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 234 {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 235 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 236 {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 237 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 238 {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 239 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 240 {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 241 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 242 {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 243 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 244 {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 246 {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 248 {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 250 {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 252 {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 254 {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 256 {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 258 {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 260 {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 262 {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 264 {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 265 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 266 {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 267 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 268 {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 269 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 270 {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 271 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 272 {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 273 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 274 275 {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 277 {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 279 {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 281 {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 283 {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 285 {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 287 {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 288 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 289 {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 290 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 291 {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 292 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 293 {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 294 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 295 {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 296 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 297 {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 298 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 299 }; 300 301 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 302 { 303 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 304 .ethter_type = cpu_to_le16(ETH_P_LLDP), 305 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e}, 306 .i_port_bitmap = 0x1, 307 }, 308 }; 309 310 static const struct key_info meta_data_key_info[] = { 311 { PACKET_TYPE_ID, 6 }, 312 { IP_FRAGEMENT, 1 }, 313 { ROCE_TYPE, 1 }, 314 { NEXT_KEY, 5 }, 315 { VLAN_NUMBER, 2 }, 316 { SRC_VPORT, 12 }, 317 { DST_VPORT, 12 }, 318 { TUNNEL_PACKET, 1 }, 319 }; 320 321 static const struct key_info tuple_key_info[] = { 322 { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 }, 323 { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 }, 324 { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 }, 325 { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 326 { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 }, 327 { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 }, 328 { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 }, 329 { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 }, 330 { OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 }, 331 { OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 }, 332 { OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 }, 333 { OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 }, 334 { OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 }, 335 { OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 }, 336 { OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 }, 337 { OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 }, 338 { INNER_DST_MAC, 48, KEY_OPT_MAC, 339 offsetof(struct hclge_fd_rule, tuples.dst_mac), 340 offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) }, 341 { INNER_SRC_MAC, 48, KEY_OPT_MAC, 342 offsetof(struct hclge_fd_rule, tuples.src_mac), 343 offsetof(struct hclge_fd_rule, tuples_mask.src_mac) }, 344 { INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16, 345 offsetof(struct hclge_fd_rule, tuples.vlan_tag1), 346 offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) }, 347 { INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 348 { INNER_ETH_TYPE, 16, KEY_OPT_LE16, 349 offsetof(struct hclge_fd_rule, tuples.ether_proto), 350 offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) }, 351 { INNER_L2_RSV, 16, KEY_OPT_LE16, 352 offsetof(struct hclge_fd_rule, tuples.l2_user_def), 353 offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) }, 354 { INNER_IP_TOS, 8, KEY_OPT_U8, 355 offsetof(struct hclge_fd_rule, tuples.ip_tos), 356 offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) }, 357 { INNER_IP_PROTO, 8, KEY_OPT_U8, 358 offsetof(struct hclge_fd_rule, tuples.ip_proto), 359 offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) }, 360 { INNER_SRC_IP, 32, KEY_OPT_IP, 361 offsetof(struct hclge_fd_rule, tuples.src_ip), 362 offsetof(struct hclge_fd_rule, tuples_mask.src_ip) }, 363 { INNER_DST_IP, 32, KEY_OPT_IP, 364 offsetof(struct hclge_fd_rule, tuples.dst_ip), 365 offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) }, 366 { INNER_L3_RSV, 16, KEY_OPT_LE16, 367 offsetof(struct hclge_fd_rule, tuples.l3_user_def), 368 offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) }, 369 { INNER_SRC_PORT, 16, KEY_OPT_LE16, 370 offsetof(struct hclge_fd_rule, tuples.src_port), 371 offsetof(struct hclge_fd_rule, tuples_mask.src_port) }, 372 { INNER_DST_PORT, 16, KEY_OPT_LE16, 373 offsetof(struct hclge_fd_rule, tuples.dst_port), 374 offsetof(struct hclge_fd_rule, tuples_mask.dst_port) }, 375 { INNER_L4_RSV, 32, KEY_OPT_LE32, 376 offsetof(struct hclge_fd_rule, tuples.l4_user_def), 377 offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) }, 378 }; 379 380 /** 381 * hclge_cmd_send - send command to command queue 382 * @hw: pointer to the hw struct 383 * @desc: prefilled descriptor for describing the command 384 * @num : the number of descriptors to be sent 385 * 386 * This is the main send command for command queue, it 387 * sends the queue, cleans the queue, etc 388 **/ 389 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 390 { 391 return hclge_comm_cmd_send(&hw->hw, desc, num); 392 } 393 394 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev) 395 { 396 #define HCLGE_MAC_CMD_NUM 21 397 398 u64 *data = (u64 *)(&hdev->mac_stats); 399 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 400 __le64 *desc_data; 401 u32 data_size; 402 int ret; 403 u32 i; 404 405 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 406 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 407 if (ret) { 408 dev_err(&hdev->pdev->dev, 409 "Get MAC pkt stats fail, status = %d.\n", ret); 410 411 return ret; 412 } 413 414 /* The first desc has a 64-bit header, so data size need to minus 1 */ 415 data_size = sizeof(desc) / (sizeof(u64)) - 1; 416 417 desc_data = (__le64 *)(&desc[0].data[0]); 418 for (i = 0; i < data_size; i++) { 419 /* data memory is continuous becase only the first desc has a 420 * header in this command 421 */ 422 *data += le64_to_cpu(*desc_data); 423 data++; 424 desc_data++; 425 } 426 427 return 0; 428 } 429 430 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev) 431 { 432 #define HCLGE_REG_NUM_PER_DESC 4 433 434 u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num; 435 u64 *data = (u64 *)(&hdev->mac_stats); 436 struct hclge_desc *desc; 437 __le64 *desc_data; 438 u32 data_size; 439 u32 desc_num; 440 int ret; 441 u32 i; 442 443 /* The first desc has a 64-bit header, so need to consider it */ 444 desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1; 445 446 /* This may be called inside atomic sections, 447 * so GFP_ATOMIC is more suitalbe here 448 */ 449 desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC); 450 if (!desc) 451 return -ENOMEM; 452 453 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true); 454 ret = hclge_cmd_send(&hdev->hw, desc, desc_num); 455 if (ret) { 456 kfree(desc); 457 return ret; 458 } 459 460 data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num); 461 462 desc_data = (__le64 *)(&desc[0].data[0]); 463 for (i = 0; i < data_size; i++) { 464 /* data memory is continuous becase only the first desc has a 465 * header in this command 466 */ 467 *data += le64_to_cpu(*desc_data); 468 data++; 469 desc_data++; 470 } 471 472 kfree(desc); 473 474 return 0; 475 } 476 477 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num) 478 { 479 struct hclge_desc desc; 480 int ret; 481 482 /* Driver needs total register number of both valid registers and 483 * reserved registers, but the old firmware only returns number 484 * of valid registers in device V2. To be compatible with these 485 * devices, driver uses a fixed value. 486 */ 487 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) { 488 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1; 489 return 0; 490 } 491 492 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true); 493 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 494 if (ret) { 495 dev_err(&hdev->pdev->dev, 496 "failed to query mac statistic reg number, ret = %d\n", 497 ret); 498 return ret; 499 } 500 501 *reg_num = le32_to_cpu(desc.data[0]); 502 if (*reg_num == 0) { 503 dev_err(&hdev->pdev->dev, 504 "mac statistic reg number is invalid!\n"); 505 return -ENODATA; 506 } 507 508 return 0; 509 } 510 511 int hclge_mac_update_stats(struct hclge_dev *hdev) 512 { 513 /* The firmware supports the new statistics acquisition method */ 514 if (hdev->ae_dev->dev_specs.mac_stats_num) 515 return hclge_mac_update_stats_complete(hdev); 516 else 517 return hclge_mac_update_stats_defective(hdev); 518 } 519 520 static int hclge_comm_get_count(struct hclge_dev *hdev, 521 const struct hclge_comm_stats_str strs[], 522 u32 size) 523 { 524 int count = 0; 525 u32 i; 526 527 for (i = 0; i < size; i++) 528 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num) 529 count++; 530 531 return count; 532 } 533 534 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, 535 const struct hclge_comm_stats_str strs[], 536 int size, u64 *data) 537 { 538 u64 *buf = data; 539 u32 i; 540 541 for (i = 0; i < size; i++) { 542 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 543 continue; 544 545 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset); 546 buf++; 547 } 548 549 return buf; 550 } 551 552 static u8 *hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, 553 const struct hclge_comm_stats_str strs[], 554 int size, u8 *data) 555 { 556 char *buff = (char *)data; 557 u32 i; 558 559 if (stringset != ETH_SS_STATS) 560 return buff; 561 562 for (i = 0; i < size; i++) { 563 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 564 continue; 565 566 snprintf(buff, ETH_GSTRING_LEN, "%s", strs[i].desc); 567 buff = buff + ETH_GSTRING_LEN; 568 } 569 570 return (u8 *)buff; 571 } 572 573 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 574 { 575 struct hnae3_handle *handle; 576 int status; 577 578 handle = &hdev->vport[0].nic; 579 if (handle->client) { 580 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 581 if (status) { 582 dev_err(&hdev->pdev->dev, 583 "Update TQPS stats fail, status = %d.\n", 584 status); 585 } 586 } 587 588 hclge_update_fec_stats(hdev); 589 590 status = hclge_mac_update_stats(hdev); 591 if (status) 592 dev_err(&hdev->pdev->dev, 593 "Update MAC stats fail, status = %d.\n", status); 594 } 595 596 static void hclge_update_stats(struct hnae3_handle *handle) 597 { 598 struct hclge_vport *vport = hclge_get_vport(handle); 599 struct hclge_dev *hdev = vport->back; 600 int status; 601 602 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 603 return; 604 605 status = hclge_mac_update_stats(hdev); 606 if (status) 607 dev_err(&hdev->pdev->dev, 608 "Update MAC stats fail, status = %d.\n", 609 status); 610 611 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 612 if (status) 613 dev_err(&hdev->pdev->dev, 614 "Update TQPS stats fail, status = %d.\n", 615 status); 616 617 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 618 } 619 620 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 621 { 622 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \ 623 HNAE3_SUPPORT_PHY_LOOPBACK | \ 624 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \ 625 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \ 626 HNAE3_SUPPORT_EXTERNAL_LOOPBACK) 627 628 struct hclge_vport *vport = hclge_get_vport(handle); 629 struct hclge_dev *hdev = vport->back; 630 int count = 0; 631 632 /* Loopback test support rules: 633 * mac: only GE mode support 634 * serdes: all mac mode will support include GE/XGE/LGE/CGE 635 * phy: only support when phy device exist on board 636 */ 637 if (stringset == ETH_SS_TEST) { 638 /* clear loopback bit flags at first */ 639 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 640 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 || 641 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 642 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 643 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 644 count += 1; 645 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; 646 } 647 648 count += 1; 649 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; 650 count += 1; 651 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; 652 count += 1; 653 handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK; 654 655 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv && 656 hdev->hw.mac.phydev->drv->set_loopback) || 657 hnae3_dev_phy_imp_supported(hdev)) { 658 count += 1; 659 handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK; 660 } 661 } else if (stringset == ETH_SS_STATS) { 662 count = hclge_comm_get_count(hdev, g_mac_stats_string, 663 ARRAY_SIZE(g_mac_stats_string)) + 664 hclge_comm_tqps_get_sset_count(handle); 665 } 666 667 return count; 668 } 669 670 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset, 671 u8 *data) 672 { 673 struct hclge_vport *vport = hclge_get_vport(handle); 674 struct hclge_dev *hdev = vport->back; 675 u8 *p = (char *)data; 676 int size; 677 678 if (stringset == ETH_SS_STATS) { 679 size = ARRAY_SIZE(g_mac_stats_string); 680 p = hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, 681 size, p); 682 p = hclge_comm_tqps_get_strings(handle, p); 683 } else if (stringset == ETH_SS_TEST) { 684 if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) { 685 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL], 686 ETH_GSTRING_LEN); 687 p += ETH_GSTRING_LEN; 688 } 689 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { 690 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_APP], 691 ETH_GSTRING_LEN); 692 p += ETH_GSTRING_LEN; 693 } 694 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { 695 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES], 696 ETH_GSTRING_LEN); 697 p += ETH_GSTRING_LEN; 698 } 699 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { 700 memcpy(p, 701 hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES], 702 ETH_GSTRING_LEN); 703 p += ETH_GSTRING_LEN; 704 } 705 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 706 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_PHY], 707 ETH_GSTRING_LEN); 708 p += ETH_GSTRING_LEN; 709 } 710 } 711 } 712 713 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 714 { 715 struct hclge_vport *vport = hclge_get_vport(handle); 716 struct hclge_dev *hdev = vport->back; 717 u64 *p; 718 719 p = hclge_comm_get_stats(hdev, g_mac_stats_string, 720 ARRAY_SIZE(g_mac_stats_string), data); 721 p = hclge_comm_tqps_get_stats(handle, p); 722 } 723 724 static void hclge_get_mac_stat(struct hnae3_handle *handle, 725 struct hns3_mac_stats *mac_stats) 726 { 727 struct hclge_vport *vport = hclge_get_vport(handle); 728 struct hclge_dev *hdev = vport->back; 729 730 hclge_update_stats(handle); 731 732 mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num; 733 mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num; 734 } 735 736 static int hclge_parse_func_status(struct hclge_dev *hdev, 737 struct hclge_func_status_cmd *status) 738 { 739 #define HCLGE_MAC_ID_MASK 0xF 740 741 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 742 return -EINVAL; 743 744 /* Set the pf to main pf */ 745 if (status->pf_state & HCLGE_PF_STATE_MAIN) 746 hdev->flag |= HCLGE_FLAG_MAIN; 747 else 748 hdev->flag &= ~HCLGE_FLAG_MAIN; 749 750 hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK; 751 return 0; 752 } 753 754 static int hclge_query_function_status(struct hclge_dev *hdev) 755 { 756 #define HCLGE_QUERY_MAX_CNT 5 757 758 struct hclge_func_status_cmd *req; 759 struct hclge_desc desc; 760 int timeout = 0; 761 int ret; 762 763 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 764 req = (struct hclge_func_status_cmd *)desc.data; 765 766 do { 767 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 768 if (ret) { 769 dev_err(&hdev->pdev->dev, 770 "query function status failed %d.\n", ret); 771 return ret; 772 } 773 774 /* Check pf reset is done */ 775 if (req->pf_state) 776 break; 777 usleep_range(1000, 2000); 778 } while (timeout++ < HCLGE_QUERY_MAX_CNT); 779 780 return hclge_parse_func_status(hdev, req); 781 } 782 783 static int hclge_query_pf_resource(struct hclge_dev *hdev) 784 { 785 struct hclge_pf_res_cmd *req; 786 struct hclge_desc desc; 787 int ret; 788 789 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 790 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 791 if (ret) { 792 dev_err(&hdev->pdev->dev, 793 "query pf resource failed %d.\n", ret); 794 return ret; 795 } 796 797 req = (struct hclge_pf_res_cmd *)desc.data; 798 hdev->num_tqps = le16_to_cpu(req->tqp_num) + 799 le16_to_cpu(req->ext_tqp_num); 800 hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 801 802 if (req->tx_buf_size) 803 hdev->tx_buf_size = 804 le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S; 805 else 806 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 807 808 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT); 809 810 if (req->dv_buf_size) 811 hdev->dv_buf_size = 812 le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S; 813 else 814 hdev->dv_buf_size = HCLGE_DEFAULT_DV; 815 816 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT); 817 818 hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic); 819 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) { 820 dev_err(&hdev->pdev->dev, 821 "only %u msi resources available, not enough for pf(min:2).\n", 822 hdev->num_nic_msi); 823 return -EINVAL; 824 } 825 826 if (hnae3_dev_roce_supported(hdev)) { 827 hdev->num_roce_msi = 828 le16_to_cpu(req->pf_intr_vector_number_roce); 829 830 /* PF should have NIC vectors and Roce vectors, 831 * NIC vectors are queued before Roce vectors. 832 */ 833 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi; 834 } else { 835 hdev->num_msi = hdev->num_nic_msi; 836 } 837 838 return 0; 839 } 840 841 static int hclge_parse_speed(u8 speed_cmd, u32 *speed) 842 { 843 switch (speed_cmd) { 844 case HCLGE_FW_MAC_SPEED_10M: 845 *speed = HCLGE_MAC_SPEED_10M; 846 break; 847 case HCLGE_FW_MAC_SPEED_100M: 848 *speed = HCLGE_MAC_SPEED_100M; 849 break; 850 case HCLGE_FW_MAC_SPEED_1G: 851 *speed = HCLGE_MAC_SPEED_1G; 852 break; 853 case HCLGE_FW_MAC_SPEED_10G: 854 *speed = HCLGE_MAC_SPEED_10G; 855 break; 856 case HCLGE_FW_MAC_SPEED_25G: 857 *speed = HCLGE_MAC_SPEED_25G; 858 break; 859 case HCLGE_FW_MAC_SPEED_40G: 860 *speed = HCLGE_MAC_SPEED_40G; 861 break; 862 case HCLGE_FW_MAC_SPEED_50G: 863 *speed = HCLGE_MAC_SPEED_50G; 864 break; 865 case HCLGE_FW_MAC_SPEED_100G: 866 *speed = HCLGE_MAC_SPEED_100G; 867 break; 868 case HCLGE_FW_MAC_SPEED_200G: 869 *speed = HCLGE_MAC_SPEED_200G; 870 break; 871 default: 872 return -EINVAL; 873 } 874 875 return 0; 876 } 877 878 static const struct hclge_speed_bit_map speed_bit_map[] = { 879 {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT}, 880 {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT}, 881 {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT}, 882 {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT}, 883 {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT}, 884 {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT}, 885 {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BIT}, 886 {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BIT}, 887 {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT}, 888 }; 889 890 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit) 891 { 892 u16 i; 893 894 for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) { 895 if (speed == speed_bit_map[i].speed) { 896 *speed_bit = speed_bit_map[i].speed_bit; 897 return 0; 898 } 899 } 900 901 return -EINVAL; 902 } 903 904 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed) 905 { 906 struct hclge_vport *vport = hclge_get_vport(handle); 907 struct hclge_dev *hdev = vport->back; 908 u32 speed_ability = hdev->hw.mac.speed_ability; 909 u32 speed_bit = 0; 910 int ret; 911 912 ret = hclge_get_speed_bit(speed, &speed_bit); 913 if (ret) 914 return ret; 915 916 if (speed_bit & speed_ability) 917 return 0; 918 919 return -EINVAL; 920 } 921 922 static void hclge_update_fec_support(struct hclge_mac *mac) 923 { 924 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported); 925 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported); 926 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported); 927 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 928 929 if (mac->fec_ability & BIT(HNAE3_FEC_BASER)) 930 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 931 mac->supported); 932 if (mac->fec_ability & BIT(HNAE3_FEC_RS)) 933 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 934 mac->supported); 935 if (mac->fec_ability & BIT(HNAE3_FEC_LLRS)) 936 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 937 mac->supported); 938 if (mac->fec_ability & BIT(HNAE3_FEC_NONE)) 939 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 940 mac->supported); 941 } 942 943 static void hclge_convert_setting_sr(u16 speed_ability, 944 unsigned long *link_mode) 945 { 946 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 947 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 948 link_mode); 949 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 950 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 951 link_mode); 952 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 953 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 954 link_mode); 955 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 956 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 957 link_mode); 958 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 959 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 960 link_mode); 961 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 962 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 963 link_mode); 964 } 965 966 static void hclge_convert_setting_lr(u16 speed_ability, 967 unsigned long *link_mode) 968 { 969 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 970 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 971 link_mode); 972 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 973 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 974 link_mode); 975 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 976 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 977 link_mode); 978 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 979 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 980 link_mode); 981 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 982 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 983 link_mode); 984 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 985 linkmode_set_bit( 986 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 987 link_mode); 988 } 989 990 static void hclge_convert_setting_cr(u16 speed_ability, 991 unsigned long *link_mode) 992 { 993 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 994 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 995 link_mode); 996 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 997 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 998 link_mode); 999 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1000 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 1001 link_mode); 1002 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1003 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 1004 link_mode); 1005 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1006 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 1007 link_mode); 1008 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1009 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 1010 link_mode); 1011 } 1012 1013 static void hclge_convert_setting_kr(u16 speed_ability, 1014 unsigned long *link_mode) 1015 { 1016 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1017 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1018 link_mode); 1019 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1020 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1021 link_mode); 1022 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1023 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 1024 link_mode); 1025 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1026 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 1027 link_mode); 1028 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1029 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 1030 link_mode); 1031 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1032 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 1033 link_mode); 1034 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1035 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 1036 link_mode); 1037 } 1038 1039 static void hclge_convert_setting_fec(struct hclge_mac *mac) 1040 { 1041 /* If firmware has reported fec_ability, don't need to convert by speed */ 1042 if (mac->fec_ability) 1043 goto out; 1044 1045 switch (mac->speed) { 1046 case HCLGE_MAC_SPEED_10G: 1047 case HCLGE_MAC_SPEED_40G: 1048 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) | 1049 BIT(HNAE3_FEC_NONE); 1050 break; 1051 case HCLGE_MAC_SPEED_25G: 1052 case HCLGE_MAC_SPEED_50G: 1053 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) | 1054 BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE); 1055 break; 1056 case HCLGE_MAC_SPEED_100G: 1057 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1058 BIT(HNAE3_FEC_NONE); 1059 break; 1060 case HCLGE_MAC_SPEED_200G: 1061 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1062 BIT(HNAE3_FEC_LLRS); 1063 break; 1064 default: 1065 mac->fec_ability = 0; 1066 break; 1067 } 1068 1069 out: 1070 hclge_update_fec_support(mac); 1071 } 1072 1073 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 1074 u16 speed_ability) 1075 { 1076 struct hclge_mac *mac = &hdev->hw.mac; 1077 1078 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1079 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1080 mac->supported); 1081 1082 hclge_convert_setting_sr(speed_ability, mac->supported); 1083 hclge_convert_setting_lr(speed_ability, mac->supported); 1084 hclge_convert_setting_cr(speed_ability, mac->supported); 1085 if (hnae3_dev_fec_supported(hdev)) 1086 hclge_convert_setting_fec(mac); 1087 1088 if (hnae3_dev_pause_supported(hdev)) 1089 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1090 1091 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported); 1092 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1093 } 1094 1095 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev, 1096 u16 speed_ability) 1097 { 1098 struct hclge_mac *mac = &hdev->hw.mac; 1099 1100 hclge_convert_setting_kr(speed_ability, mac->supported); 1101 if (hnae3_dev_fec_supported(hdev)) 1102 hclge_convert_setting_fec(mac); 1103 1104 if (hnae3_dev_pause_supported(hdev)) 1105 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1106 1107 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported); 1108 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1109 } 1110 1111 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev, 1112 u16 speed_ability) 1113 { 1114 unsigned long *supported = hdev->hw.mac.supported; 1115 1116 /* default to support all speed for GE port */ 1117 if (!speed_ability) 1118 speed_ability = HCLGE_SUPPORT_GE; 1119 1120 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1121 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1122 supported); 1123 1124 if (speed_ability & HCLGE_SUPPORT_100M_BIT) { 1125 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1126 supported); 1127 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1128 supported); 1129 } 1130 1131 if (speed_ability & HCLGE_SUPPORT_10M_BIT) { 1132 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported); 1133 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported); 1134 } 1135 1136 if (hnae3_dev_pause_supported(hdev)) { 1137 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1138 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 1139 } 1140 1141 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 1142 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 1143 } 1144 1145 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 1146 { 1147 u8 media_type = hdev->hw.mac.media_type; 1148 1149 if (media_type == HNAE3_MEDIA_TYPE_FIBER) 1150 hclge_parse_fiber_link_mode(hdev, speed_ability); 1151 else if (media_type == HNAE3_MEDIA_TYPE_COPPER) 1152 hclge_parse_copper_link_mode(hdev, speed_ability); 1153 else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE) 1154 hclge_parse_backplane_link_mode(hdev, speed_ability); 1155 } 1156 1157 static u32 hclge_get_max_speed(u16 speed_ability) 1158 { 1159 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1160 return HCLGE_MAC_SPEED_200G; 1161 1162 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1163 return HCLGE_MAC_SPEED_100G; 1164 1165 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1166 return HCLGE_MAC_SPEED_50G; 1167 1168 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1169 return HCLGE_MAC_SPEED_40G; 1170 1171 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1172 return HCLGE_MAC_SPEED_25G; 1173 1174 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1175 return HCLGE_MAC_SPEED_10G; 1176 1177 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1178 return HCLGE_MAC_SPEED_1G; 1179 1180 if (speed_ability & HCLGE_SUPPORT_100M_BIT) 1181 return HCLGE_MAC_SPEED_100M; 1182 1183 if (speed_ability & HCLGE_SUPPORT_10M_BIT) 1184 return HCLGE_MAC_SPEED_10M; 1185 1186 return HCLGE_MAC_SPEED_1G; 1187 } 1188 1189 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1190 { 1191 #define HCLGE_TX_SPARE_SIZE_UNIT 4096 1192 #define SPEED_ABILITY_EXT_SHIFT 8 1193 1194 struct hclge_cfg_param_cmd *req; 1195 u64 mac_addr_tmp_high; 1196 u16 speed_ability_ext; 1197 u64 mac_addr_tmp; 1198 unsigned int i; 1199 1200 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1201 1202 /* get the configuration */ 1203 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1204 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1205 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1206 HCLGE_CFG_TQP_DESC_N_M, 1207 HCLGE_CFG_TQP_DESC_N_S); 1208 1209 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1210 HCLGE_CFG_PHY_ADDR_M, 1211 HCLGE_CFG_PHY_ADDR_S); 1212 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1213 HCLGE_CFG_MEDIA_TP_M, 1214 HCLGE_CFG_MEDIA_TP_S); 1215 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1216 HCLGE_CFG_RX_BUF_LEN_M, 1217 HCLGE_CFG_RX_BUF_LEN_S); 1218 /* get mac_address */ 1219 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1220 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1221 HCLGE_CFG_MAC_ADDR_H_M, 1222 HCLGE_CFG_MAC_ADDR_H_S); 1223 1224 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1225 1226 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1227 HCLGE_CFG_DEFAULT_SPEED_M, 1228 HCLGE_CFG_DEFAULT_SPEED_S); 1229 cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1230 HCLGE_CFG_RSS_SIZE_M, 1231 HCLGE_CFG_RSS_SIZE_S); 1232 1233 for (i = 0; i < ETH_ALEN; i++) 1234 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1235 1236 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1237 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1238 1239 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1240 HCLGE_CFG_SPEED_ABILITY_M, 1241 HCLGE_CFG_SPEED_ABILITY_S); 1242 speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]), 1243 HCLGE_CFG_SPEED_ABILITY_EXT_M, 1244 HCLGE_CFG_SPEED_ABILITY_EXT_S); 1245 cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT; 1246 1247 cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]), 1248 HCLGE_CFG_VLAN_FLTR_CAP_M, 1249 HCLGE_CFG_VLAN_FLTR_CAP_S); 1250 1251 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]), 1252 HCLGE_CFG_UMV_TBL_SPACE_M, 1253 HCLGE_CFG_UMV_TBL_SPACE_S); 1254 1255 cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]), 1256 HCLGE_CFG_PF_RSS_SIZE_M, 1257 HCLGE_CFG_PF_RSS_SIZE_S); 1258 1259 /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a 1260 * power of 2, instead of reading out directly. This would 1261 * be more flexible for future changes and expansions. 1262 * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S, 1263 * it does not make sense if PF's field is 0. In this case, PF and VF 1264 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S. 1265 */ 1266 cfg->pf_rss_size_max = cfg->pf_rss_size_max ? 1267 1U << cfg->pf_rss_size_max : 1268 cfg->vf_rss_size_max; 1269 1270 /* The unit of the tx spare buffer size queried from configuration 1271 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is 1272 * needed here. 1273 */ 1274 cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]), 1275 HCLGE_CFG_TX_SPARE_BUF_SIZE_M, 1276 HCLGE_CFG_TX_SPARE_BUF_SIZE_S); 1277 cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT; 1278 } 1279 1280 /* hclge_get_cfg: query the static parameter from flash 1281 * @hdev: pointer to struct hclge_dev 1282 * @hcfg: the config structure to be getted 1283 */ 1284 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1285 { 1286 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1287 struct hclge_cfg_param_cmd *req; 1288 unsigned int i; 1289 int ret; 1290 1291 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1292 u32 offset = 0; 1293 1294 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1295 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1296 true); 1297 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1298 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1299 /* Len should be united by 4 bytes when send to hardware */ 1300 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1301 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1302 req->offset = cpu_to_le32(offset); 1303 } 1304 1305 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1306 if (ret) { 1307 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1308 return ret; 1309 } 1310 1311 hclge_parse_cfg(hcfg, desc); 1312 1313 return 0; 1314 } 1315 1316 static void hclge_set_default_dev_specs(struct hclge_dev *hdev) 1317 { 1318 #define HCLGE_MAX_NON_TSO_BD_NUM 8U 1319 1320 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1321 1322 ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1323 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1324 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1325 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE; 1326 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL; 1327 ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME; 1328 ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM; 1329 ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1330 ae_dev->dev_specs.tnl_num = 0; 1331 } 1332 1333 static void hclge_parse_dev_specs(struct hclge_dev *hdev, 1334 struct hclge_desc *desc) 1335 { 1336 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1337 struct hclge_dev_specs_0_cmd *req0; 1338 struct hclge_dev_specs_1_cmd *req1; 1339 1340 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data; 1341 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data; 1342 1343 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 1344 ae_dev->dev_specs.rss_ind_tbl_size = 1345 le16_to_cpu(req0->rss_ind_tbl_size); 1346 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 1347 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 1348 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate); 1349 ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num); 1350 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 1351 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 1352 ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size); 1353 ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size); 1354 ae_dev->dev_specs.tnl_num = req1->tnl_num; 1355 } 1356 1357 static void hclge_check_dev_specs(struct hclge_dev *hdev) 1358 { 1359 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 1360 1361 if (!dev_specs->max_non_tso_bd_num) 1362 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1363 if (!dev_specs->rss_ind_tbl_size) 1364 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1365 if (!dev_specs->rss_key_size) 1366 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1367 if (!dev_specs->max_tm_rate) 1368 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE; 1369 if (!dev_specs->max_qset_num) 1370 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM; 1371 if (!dev_specs->max_int_gl) 1372 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL; 1373 if (!dev_specs->max_frm_size) 1374 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME; 1375 if (!dev_specs->umv_size) 1376 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1377 } 1378 1379 static int hclge_query_mac_stats_num(struct hclge_dev *hdev) 1380 { 1381 u32 reg_num = 0; 1382 int ret; 1383 1384 ret = hclge_mac_query_reg_num(hdev, ®_num); 1385 if (ret && ret != -EOPNOTSUPP) 1386 return ret; 1387 1388 hdev->ae_dev->dev_specs.mac_stats_num = reg_num; 1389 return 0; 1390 } 1391 1392 static int hclge_query_dev_specs(struct hclge_dev *hdev) 1393 { 1394 struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM]; 1395 int ret; 1396 int i; 1397 1398 ret = hclge_query_mac_stats_num(hdev); 1399 if (ret) 1400 return ret; 1401 1402 /* set default specifications as devices lower than version V3 do not 1403 * support querying specifications from firmware. 1404 */ 1405 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 1406 hclge_set_default_dev_specs(hdev); 1407 return 0; 1408 } 1409 1410 for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1411 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, 1412 true); 1413 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 1414 } 1415 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 1416 1417 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM); 1418 if (ret) 1419 return ret; 1420 1421 hclge_parse_dev_specs(hdev, desc); 1422 hclge_check_dev_specs(hdev); 1423 1424 return 0; 1425 } 1426 1427 static int hclge_get_cap(struct hclge_dev *hdev) 1428 { 1429 int ret; 1430 1431 ret = hclge_query_function_status(hdev); 1432 if (ret) { 1433 dev_err(&hdev->pdev->dev, 1434 "query function status error %d.\n", ret); 1435 return ret; 1436 } 1437 1438 /* get pf resource */ 1439 return hclge_query_pf_resource(hdev); 1440 } 1441 1442 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev) 1443 { 1444 #define HCLGE_MIN_TX_DESC 64 1445 #define HCLGE_MIN_RX_DESC 64 1446 1447 if (!is_kdump_kernel()) 1448 return; 1449 1450 dev_info(&hdev->pdev->dev, 1451 "Running kdump kernel. Using minimal resources\n"); 1452 1453 /* minimal queue pairs equals to the number of vports */ 1454 hdev->num_tqps = hdev->num_req_vfs + 1; 1455 hdev->num_tx_desc = HCLGE_MIN_TX_DESC; 1456 hdev->num_rx_desc = HCLGE_MIN_RX_DESC; 1457 } 1458 1459 static void hclge_init_tc_config(struct hclge_dev *hdev) 1460 { 1461 unsigned int i; 1462 1463 if (hdev->tc_max > HNAE3_MAX_TC || 1464 hdev->tc_max < 1) { 1465 dev_warn(&hdev->pdev->dev, "TC num = %u.\n", 1466 hdev->tc_max); 1467 hdev->tc_max = 1; 1468 } 1469 1470 /* Dev does not support DCB */ 1471 if (!hnae3_dev_dcb_supported(hdev)) { 1472 hdev->tc_max = 1; 1473 hdev->pfc_max = 0; 1474 } else { 1475 hdev->pfc_max = hdev->tc_max; 1476 } 1477 1478 hdev->tm_info.num_tc = 1; 1479 1480 /* Currently not support uncontiuous tc */ 1481 for (i = 0; i < hdev->tm_info.num_tc; i++) 1482 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1483 1484 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1485 } 1486 1487 static int hclge_configure(struct hclge_dev *hdev) 1488 { 1489 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1490 struct hclge_cfg cfg; 1491 int ret; 1492 1493 ret = hclge_get_cfg(hdev, &cfg); 1494 if (ret) 1495 return ret; 1496 1497 hdev->base_tqp_pid = 0; 1498 hdev->vf_rss_size_max = cfg.vf_rss_size_max; 1499 hdev->pf_rss_size_max = cfg.pf_rss_size_max; 1500 hdev->rx_buf_len = cfg.rx_buf_len; 1501 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1502 hdev->hw.mac.media_type = cfg.media_type; 1503 hdev->hw.mac.phy_addr = cfg.phy_addr; 1504 hdev->num_tx_desc = cfg.tqp_desc_num; 1505 hdev->num_rx_desc = cfg.tqp_desc_num; 1506 hdev->tm_info.num_pg = 1; 1507 hdev->tc_max = cfg.tc_num; 1508 hdev->tm_info.hw_pfc_map = 0; 1509 if (cfg.umv_space) 1510 hdev->wanted_umv_size = cfg.umv_space; 1511 else 1512 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size; 1513 hdev->tx_spare_buf_size = cfg.tx_spare_buf_size; 1514 hdev->gro_en = true; 1515 if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF) 1516 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 1517 1518 if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 1519 hdev->fd_en = true; 1520 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 1521 } 1522 1523 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1524 if (ret) { 1525 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n", 1526 cfg.default_speed, ret); 1527 return ret; 1528 } 1529 hdev->hw.mac.req_speed = hdev->hw.mac.speed; 1530 hdev->hw.mac.req_autoneg = AUTONEG_ENABLE; 1531 hdev->hw.mac.req_duplex = DUPLEX_FULL; 1532 1533 hclge_parse_link_mode(hdev, cfg.speed_ability); 1534 1535 hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability); 1536 1537 hclge_init_tc_config(hdev); 1538 hclge_init_kdump_kernel_config(hdev); 1539 1540 return ret; 1541 } 1542 1543 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min, 1544 u16 tso_mss_max) 1545 { 1546 struct hclge_cfg_tso_status_cmd *req; 1547 struct hclge_desc desc; 1548 1549 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1550 1551 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1552 req->tso_mss_min = cpu_to_le16(tso_mss_min); 1553 req->tso_mss_max = cpu_to_le16(tso_mss_max); 1554 1555 return hclge_cmd_send(&hdev->hw, &desc, 1); 1556 } 1557 1558 static int hclge_config_gro(struct hclge_dev *hdev) 1559 { 1560 struct hclge_cfg_gro_status_cmd *req; 1561 struct hclge_desc desc; 1562 int ret; 1563 1564 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 1565 return 0; 1566 1567 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false); 1568 req = (struct hclge_cfg_gro_status_cmd *)desc.data; 1569 1570 req->gro_en = hdev->gro_en ? 1 : 0; 1571 1572 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1573 if (ret) 1574 dev_err(&hdev->pdev->dev, 1575 "GRO hardware config cmd failed, ret = %d\n", ret); 1576 1577 return ret; 1578 } 1579 1580 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1581 { 1582 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1583 struct hclge_comm_tqp *tqp; 1584 int i; 1585 1586 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1587 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 1588 if (!hdev->htqp) 1589 return -ENOMEM; 1590 1591 tqp = hdev->htqp; 1592 1593 for (i = 0; i < hdev->num_tqps; i++) { 1594 tqp->dev = &hdev->pdev->dev; 1595 tqp->index = i; 1596 1597 tqp->q.ae_algo = &ae_algo; 1598 tqp->q.buf_size = hdev->rx_buf_len; 1599 tqp->q.tx_desc_num = hdev->num_tx_desc; 1600 tqp->q.rx_desc_num = hdev->num_rx_desc; 1601 1602 /* need an extended offset to configure queues >= 1603 * HCLGE_TQP_MAX_SIZE_DEV_V2 1604 */ 1605 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2) 1606 tqp->q.io_base = hdev->hw.hw.io_base + 1607 HCLGE_TQP_REG_OFFSET + 1608 i * HCLGE_TQP_REG_SIZE; 1609 else 1610 tqp->q.io_base = hdev->hw.hw.io_base + 1611 HCLGE_TQP_REG_OFFSET + 1612 HCLGE_TQP_EXT_REG_OFFSET + 1613 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) * 1614 HCLGE_TQP_REG_SIZE; 1615 1616 /* when device supports tx push and has device memory, 1617 * the queue can execute push mode or doorbell mode on 1618 * device memory. 1619 */ 1620 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 1621 tqp->q.mem_base = hdev->hw.hw.mem_base + 1622 HCLGE_TQP_MEM_OFFSET(hdev, i); 1623 1624 tqp++; 1625 } 1626 1627 return 0; 1628 } 1629 1630 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1631 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1632 { 1633 struct hclge_tqp_map_cmd *req; 1634 struct hclge_desc desc; 1635 int ret; 1636 1637 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1638 1639 req = (struct hclge_tqp_map_cmd *)desc.data; 1640 req->tqp_id = cpu_to_le16(tqp_pid); 1641 req->tqp_vf = func_id; 1642 req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B; 1643 if (!is_pf) 1644 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B; 1645 req->tqp_vid = cpu_to_le16(tqp_vid); 1646 1647 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1648 if (ret) 1649 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1650 1651 return ret; 1652 } 1653 1654 static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) 1655 { 1656 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1657 struct hclge_dev *hdev = vport->back; 1658 int i, alloced; 1659 1660 for (i = 0, alloced = 0; i < hdev->num_tqps && 1661 alloced < num_tqps; i++) { 1662 if (!hdev->htqp[i].alloced) { 1663 hdev->htqp[i].q.handle = &vport->nic; 1664 hdev->htqp[i].q.tqp_index = alloced; 1665 hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc; 1666 hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc; 1667 kinfo->tqp[alloced] = &hdev->htqp[i].q; 1668 hdev->htqp[i].alloced = true; 1669 alloced++; 1670 } 1671 } 1672 vport->alloc_tqps = alloced; 1673 kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max, 1674 vport->alloc_tqps / hdev->tm_info.num_tc); 1675 1676 /* ensure one to one mapping between irq and queue at default */ 1677 kinfo->rss_size = min_t(u16, kinfo->rss_size, 1678 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc); 1679 1680 return 0; 1681 } 1682 1683 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps, 1684 u16 num_tx_desc, u16 num_rx_desc) 1685 1686 { 1687 struct hnae3_handle *nic = &vport->nic; 1688 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1689 struct hclge_dev *hdev = vport->back; 1690 int ret; 1691 1692 kinfo->num_tx_desc = num_tx_desc; 1693 kinfo->num_rx_desc = num_rx_desc; 1694 1695 kinfo->rx_buf_len = hdev->rx_buf_len; 1696 kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size; 1697 1698 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps, 1699 sizeof(struct hnae3_queue *), GFP_KERNEL); 1700 if (!kinfo->tqp) 1701 return -ENOMEM; 1702 1703 ret = hclge_assign_tqp(vport, num_tqps); 1704 if (ret) 1705 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1706 1707 return ret; 1708 } 1709 1710 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1711 struct hclge_vport *vport) 1712 { 1713 struct hnae3_handle *nic = &vport->nic; 1714 struct hnae3_knic_private_info *kinfo; 1715 u16 i; 1716 1717 kinfo = &nic->kinfo; 1718 for (i = 0; i < vport->alloc_tqps; i++) { 1719 struct hclge_comm_tqp *q = 1720 container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); 1721 bool is_pf; 1722 int ret; 1723 1724 is_pf = !(vport->vport_id); 1725 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1726 i, is_pf); 1727 if (ret) 1728 return ret; 1729 } 1730 1731 return 0; 1732 } 1733 1734 static int hclge_map_tqp(struct hclge_dev *hdev) 1735 { 1736 struct hclge_vport *vport = hdev->vport; 1737 u16 i, num_vport; 1738 1739 num_vport = hdev->num_req_vfs + 1; 1740 for (i = 0; i < num_vport; i++) { 1741 int ret; 1742 1743 ret = hclge_map_tqp_to_vport(hdev, vport); 1744 if (ret) 1745 return ret; 1746 1747 vport++; 1748 } 1749 1750 return 0; 1751 } 1752 1753 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1754 { 1755 struct hnae3_handle *nic = &vport->nic; 1756 struct hclge_dev *hdev = vport->back; 1757 int ret; 1758 1759 nic->pdev = hdev->pdev; 1760 nic->ae_algo = &ae_algo; 1761 bitmap_copy(nic->numa_node_mask.bits, hdev->numa_node_mask.bits, 1762 MAX_NUMNODES); 1763 nic->kinfo.io_base = hdev->hw.hw.io_base; 1764 1765 ret = hclge_knic_setup(vport, num_tqps, 1766 hdev->num_tx_desc, hdev->num_rx_desc); 1767 if (ret) 1768 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret); 1769 1770 return ret; 1771 } 1772 1773 static int hclge_alloc_vport(struct hclge_dev *hdev) 1774 { 1775 struct pci_dev *pdev = hdev->pdev; 1776 struct hclge_vport *vport; 1777 u32 tqp_main_vport; 1778 u32 tqp_per_vport; 1779 int num_vport, i; 1780 int ret; 1781 1782 /* We need to alloc a vport for main NIC of PF */ 1783 num_vport = hdev->num_req_vfs + 1; 1784 1785 if (hdev->num_tqps < num_vport) { 1786 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)", 1787 hdev->num_tqps, num_vport); 1788 return -EINVAL; 1789 } 1790 1791 /* Alloc the same number of TQPs for every vport */ 1792 tqp_per_vport = hdev->num_tqps / num_vport; 1793 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1794 1795 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1796 GFP_KERNEL); 1797 if (!vport) 1798 return -ENOMEM; 1799 1800 hdev->vport = vport; 1801 hdev->num_alloc_vport = num_vport; 1802 1803 if (IS_ENABLED(CONFIG_PCI_IOV)) 1804 hdev->num_alloc_vfs = hdev->num_req_vfs; 1805 1806 for (i = 0; i < num_vport; i++) { 1807 vport->back = hdev; 1808 vport->vport_id = i; 1809 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO; 1810 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 1811 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE; 1812 vport->port_base_vlan_cfg.tbl_sta = true; 1813 vport->rxvlan_cfg.rx_vlan_offload_en = true; 1814 vport->req_vlan_fltr_en = true; 1815 INIT_LIST_HEAD(&vport->vlan_list); 1816 INIT_LIST_HEAD(&vport->uc_mac_list); 1817 INIT_LIST_HEAD(&vport->mc_mac_list); 1818 spin_lock_init(&vport->mac_list_lock); 1819 1820 if (i == 0) 1821 ret = hclge_vport_setup(vport, tqp_main_vport); 1822 else 1823 ret = hclge_vport_setup(vport, tqp_per_vport); 1824 if (ret) { 1825 dev_err(&pdev->dev, 1826 "vport setup failed for vport %d, %d\n", 1827 i, ret); 1828 return ret; 1829 } 1830 1831 vport++; 1832 } 1833 1834 return 0; 1835 } 1836 1837 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1838 struct hclge_pkt_buf_alloc *buf_alloc) 1839 { 1840 /* TX buffer size is unit by 128 byte */ 1841 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1842 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1843 struct hclge_tx_buff_alloc_cmd *req; 1844 struct hclge_desc desc; 1845 int ret; 1846 u8 i; 1847 1848 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1849 1850 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1851 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1852 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1853 1854 req->tx_pkt_buff[i] = 1855 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1856 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1857 } 1858 1859 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1860 if (ret) 1861 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1862 ret); 1863 1864 return ret; 1865 } 1866 1867 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1868 struct hclge_pkt_buf_alloc *buf_alloc) 1869 { 1870 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1871 1872 if (ret) 1873 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1874 1875 return ret; 1876 } 1877 1878 static u32 hclge_get_tc_num(struct hclge_dev *hdev) 1879 { 1880 unsigned int i; 1881 u32 cnt = 0; 1882 1883 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1884 if (hdev->hw_tc_map & BIT(i)) 1885 cnt++; 1886 return cnt; 1887 } 1888 1889 /* Get the number of pfc enabled TCs, which have private buffer */ 1890 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1891 struct hclge_pkt_buf_alloc *buf_alloc) 1892 { 1893 struct hclge_priv_buf *priv; 1894 unsigned int i; 1895 int cnt = 0; 1896 1897 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1898 priv = &buf_alloc->priv_buf[i]; 1899 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1900 priv->enable) 1901 cnt++; 1902 } 1903 1904 return cnt; 1905 } 1906 1907 /* Get the number of pfc disabled TCs, which have private buffer */ 1908 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1909 struct hclge_pkt_buf_alloc *buf_alloc) 1910 { 1911 struct hclge_priv_buf *priv; 1912 unsigned int i; 1913 int cnt = 0; 1914 1915 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1916 priv = &buf_alloc->priv_buf[i]; 1917 if (hdev->hw_tc_map & BIT(i) && 1918 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 1919 priv->enable) 1920 cnt++; 1921 } 1922 1923 return cnt; 1924 } 1925 1926 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1927 { 1928 struct hclge_priv_buf *priv; 1929 u32 rx_priv = 0; 1930 int i; 1931 1932 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1933 priv = &buf_alloc->priv_buf[i]; 1934 if (priv->enable) 1935 rx_priv += priv->buf_size; 1936 } 1937 return rx_priv; 1938 } 1939 1940 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1941 { 1942 u32 i, total_tx_size = 0; 1943 1944 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1945 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 1946 1947 return total_tx_size; 1948 } 1949 1950 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 1951 struct hclge_pkt_buf_alloc *buf_alloc, 1952 u32 rx_all) 1953 { 1954 u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 1955 u32 tc_num = hclge_get_tc_num(hdev); 1956 u32 shared_buf, aligned_mps; 1957 u32 rx_priv; 1958 int i; 1959 1960 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT); 1961 1962 if (hnae3_dev_dcb_supported(hdev)) 1963 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps + 1964 hdev->dv_buf_size; 1965 else 1966 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF 1967 + hdev->dv_buf_size; 1968 1969 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 1970 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc), 1971 HCLGE_BUF_SIZE_UNIT); 1972 1973 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 1974 if (rx_all < rx_priv + shared_std) 1975 return false; 1976 1977 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT); 1978 buf_alloc->s_buf.buf_size = shared_buf; 1979 if (hnae3_dev_dcb_supported(hdev)) { 1980 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size; 1981 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 1982 - roundup(aligned_mps / HCLGE_BUF_DIV_BY, 1983 HCLGE_BUF_SIZE_UNIT); 1984 } else { 1985 buf_alloc->s_buf.self.high = aligned_mps + 1986 HCLGE_NON_DCB_ADDITIONAL_BUF; 1987 buf_alloc->s_buf.self.low = aligned_mps; 1988 } 1989 1990 if (hnae3_dev_dcb_supported(hdev)) { 1991 hi_thrd = shared_buf - hdev->dv_buf_size; 1992 1993 if (tc_num <= NEED_RESERVE_TC_NUM) 1994 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 1995 / BUF_MAX_PERCENT; 1996 1997 if (tc_num) 1998 hi_thrd = hi_thrd / tc_num; 1999 2000 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps); 2001 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT); 2002 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY; 2003 } else { 2004 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF; 2005 lo_thrd = aligned_mps; 2006 } 2007 2008 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2009 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 2010 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 2011 } 2012 2013 return true; 2014 } 2015 2016 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 2017 struct hclge_pkt_buf_alloc *buf_alloc) 2018 { 2019 u32 i, total_size; 2020 2021 total_size = hdev->pkt_buf_size; 2022 2023 /* alloc tx buffer for all enabled tc */ 2024 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2025 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2026 2027 if (hdev->hw_tc_map & BIT(i)) { 2028 if (total_size < hdev->tx_buf_size) 2029 return -ENOMEM; 2030 2031 priv->tx_buf_size = hdev->tx_buf_size; 2032 } else { 2033 priv->tx_buf_size = 0; 2034 } 2035 2036 total_size -= priv->tx_buf_size; 2037 } 2038 2039 return 0; 2040 } 2041 2042 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max, 2043 struct hclge_pkt_buf_alloc *buf_alloc) 2044 { 2045 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2046 u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2047 unsigned int i; 2048 2049 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2050 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2051 2052 priv->enable = 0; 2053 priv->wl.low = 0; 2054 priv->wl.high = 0; 2055 priv->buf_size = 0; 2056 2057 if (!(hdev->hw_tc_map & BIT(i))) 2058 continue; 2059 2060 priv->enable = 1; 2061 2062 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 2063 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT; 2064 priv->wl.high = roundup(priv->wl.low + aligned_mps, 2065 HCLGE_BUF_SIZE_UNIT); 2066 } else { 2067 priv->wl.low = 0; 2068 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) : 2069 aligned_mps; 2070 } 2071 2072 priv->buf_size = priv->wl.high + hdev->dv_buf_size; 2073 } 2074 2075 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2076 } 2077 2078 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev, 2079 struct hclge_pkt_buf_alloc *buf_alloc) 2080 { 2081 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2082 int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 2083 int i; 2084 2085 /* let the last to be cleared first */ 2086 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2087 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2088 unsigned int mask = BIT((unsigned int)i); 2089 2090 if (hdev->hw_tc_map & mask && 2091 !(hdev->tm_info.hw_pfc_map & mask)) { 2092 /* Clear the no pfc TC private buffer */ 2093 priv->wl.low = 0; 2094 priv->wl.high = 0; 2095 priv->buf_size = 0; 2096 priv->enable = 0; 2097 no_pfc_priv_num--; 2098 } 2099 2100 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2101 no_pfc_priv_num == 0) 2102 break; 2103 } 2104 2105 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2106 } 2107 2108 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev, 2109 struct hclge_pkt_buf_alloc *buf_alloc) 2110 { 2111 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2112 int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 2113 int i; 2114 2115 /* let the last to be cleared first */ 2116 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2117 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2118 unsigned int mask = BIT((unsigned int)i); 2119 2120 if (hdev->hw_tc_map & mask && 2121 hdev->tm_info.hw_pfc_map & mask) { 2122 /* Reduce the number of pfc TC with private buffer */ 2123 priv->wl.low = 0; 2124 priv->enable = 0; 2125 priv->wl.high = 0; 2126 priv->buf_size = 0; 2127 pfc_priv_num--; 2128 } 2129 2130 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2131 pfc_priv_num == 0) 2132 break; 2133 } 2134 2135 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2136 } 2137 2138 static int hclge_only_alloc_priv_buff(struct hclge_dev *hdev, 2139 struct hclge_pkt_buf_alloc *buf_alloc) 2140 { 2141 #define COMPENSATE_BUFFER 0x3C00 2142 #define COMPENSATE_HALF_MPS_NUM 5 2143 #define PRIV_WL_GAP 0x1800 2144 2145 u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2146 u32 tc_num = hclge_get_tc_num(hdev); 2147 u32 half_mps = hdev->mps >> 1; 2148 u32 min_rx_priv; 2149 unsigned int i; 2150 2151 if (tc_num) 2152 rx_priv = rx_priv / tc_num; 2153 2154 if (tc_num <= NEED_RESERVE_TC_NUM) 2155 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 2156 2157 min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER + 2158 COMPENSATE_HALF_MPS_NUM * half_mps; 2159 min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT); 2160 rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT); 2161 if (rx_priv < min_rx_priv) 2162 return false; 2163 2164 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2165 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2166 2167 priv->enable = 0; 2168 priv->wl.low = 0; 2169 priv->wl.high = 0; 2170 priv->buf_size = 0; 2171 2172 if (!(hdev->hw_tc_map & BIT(i))) 2173 continue; 2174 2175 priv->enable = 1; 2176 priv->buf_size = rx_priv; 2177 priv->wl.high = rx_priv - hdev->dv_buf_size; 2178 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 2179 } 2180 2181 buf_alloc->s_buf.buf_size = 0; 2182 2183 return true; 2184 } 2185 2186 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 2187 * @hdev: pointer to struct hclge_dev 2188 * @buf_alloc: pointer to buffer calculation data 2189 * @return: 0: calculate successful, negative: fail 2190 */ 2191 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 2192 struct hclge_pkt_buf_alloc *buf_alloc) 2193 { 2194 /* When DCB is not supported, rx private buffer is not allocated. */ 2195 if (!hnae3_dev_dcb_supported(hdev)) { 2196 u32 rx_all = hdev->pkt_buf_size; 2197 2198 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 2199 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 2200 return -ENOMEM; 2201 2202 return 0; 2203 } 2204 2205 if (hclge_only_alloc_priv_buff(hdev, buf_alloc)) 2206 return 0; 2207 2208 if (hclge_rx_buf_calc_all(hdev, true, buf_alloc)) 2209 return 0; 2210 2211 /* try to decrease the buffer size */ 2212 if (hclge_rx_buf_calc_all(hdev, false, buf_alloc)) 2213 return 0; 2214 2215 if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc)) 2216 return 0; 2217 2218 if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc)) 2219 return 0; 2220 2221 return -ENOMEM; 2222 } 2223 2224 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 2225 struct hclge_pkt_buf_alloc *buf_alloc) 2226 { 2227 struct hclge_rx_priv_buff_cmd *req; 2228 struct hclge_desc desc; 2229 int ret; 2230 int i; 2231 2232 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 2233 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 2234 2235 /* Alloc private buffer TCs */ 2236 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2237 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2238 2239 req->buf_num[i] = 2240 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 2241 req->buf_num[i] |= 2242 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 2243 } 2244 2245 req->shared_buf = 2246 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 2247 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 2248 2249 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2250 if (ret) 2251 dev_err(&hdev->pdev->dev, 2252 "rx private buffer alloc cmd failed %d\n", ret); 2253 2254 return ret; 2255 } 2256 2257 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 2258 struct hclge_pkt_buf_alloc *buf_alloc) 2259 { 2260 struct hclge_rx_priv_wl_buf *req; 2261 struct hclge_priv_buf *priv; 2262 struct hclge_desc desc[2]; 2263 int i, j; 2264 int ret; 2265 2266 for (i = 0; i < 2; i++) { 2267 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 2268 false); 2269 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 2270 2271 /* The first descriptor set the NEXT bit to 1 */ 2272 if (i == 0) 2273 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2274 else 2275 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2276 2277 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2278 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 2279 2280 priv = &buf_alloc->priv_buf[idx]; 2281 req->tc_wl[j].high = 2282 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 2283 req->tc_wl[j].high |= 2284 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2285 req->tc_wl[j].low = 2286 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 2287 req->tc_wl[j].low |= 2288 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2289 } 2290 } 2291 2292 /* Send 2 descriptor at one time */ 2293 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2294 if (ret) 2295 dev_err(&hdev->pdev->dev, 2296 "rx private waterline config cmd failed %d\n", 2297 ret); 2298 return ret; 2299 } 2300 2301 static int hclge_common_thrd_config(struct hclge_dev *hdev, 2302 struct hclge_pkt_buf_alloc *buf_alloc) 2303 { 2304 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 2305 struct hclge_rx_com_thrd *req; 2306 struct hclge_desc desc[2]; 2307 struct hclge_tc_thrd *tc; 2308 int i, j; 2309 int ret; 2310 2311 for (i = 0; i < 2; i++) { 2312 hclge_cmd_setup_basic_desc(&desc[i], 2313 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 2314 req = (struct hclge_rx_com_thrd *)&desc[i].data; 2315 2316 /* The first descriptor set the NEXT bit to 1 */ 2317 if (i == 0) 2318 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2319 else 2320 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2321 2322 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2323 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 2324 2325 req->com_thrd[j].high = 2326 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 2327 req->com_thrd[j].high |= 2328 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2329 req->com_thrd[j].low = 2330 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 2331 req->com_thrd[j].low |= 2332 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2333 } 2334 } 2335 2336 /* Send 2 descriptors at one time */ 2337 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2338 if (ret) 2339 dev_err(&hdev->pdev->dev, 2340 "common threshold config cmd failed %d\n", ret); 2341 return ret; 2342 } 2343 2344 static int hclge_common_wl_config(struct hclge_dev *hdev, 2345 struct hclge_pkt_buf_alloc *buf_alloc) 2346 { 2347 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 2348 struct hclge_rx_com_wl *req; 2349 struct hclge_desc desc; 2350 int ret; 2351 2352 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 2353 2354 req = (struct hclge_rx_com_wl *)desc.data; 2355 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 2356 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2357 2358 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 2359 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2360 2361 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2362 if (ret) 2363 dev_err(&hdev->pdev->dev, 2364 "common waterline config cmd failed %d\n", ret); 2365 2366 return ret; 2367 } 2368 2369 int hclge_buffer_alloc(struct hclge_dev *hdev) 2370 { 2371 struct hclge_pkt_buf_alloc *pkt_buf; 2372 int ret; 2373 2374 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 2375 if (!pkt_buf) 2376 return -ENOMEM; 2377 2378 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 2379 if (ret) { 2380 dev_err(&hdev->pdev->dev, 2381 "could not calc tx buffer size for all TCs %d\n", ret); 2382 goto out; 2383 } 2384 2385 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 2386 if (ret) { 2387 dev_err(&hdev->pdev->dev, 2388 "could not alloc tx buffers %d\n", ret); 2389 goto out; 2390 } 2391 2392 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 2393 if (ret) { 2394 dev_err(&hdev->pdev->dev, 2395 "could not calc rx priv buffer size for all TCs %d\n", 2396 ret); 2397 goto out; 2398 } 2399 2400 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 2401 if (ret) { 2402 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 2403 ret); 2404 goto out; 2405 } 2406 2407 if (hnae3_dev_dcb_supported(hdev)) { 2408 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2409 if (ret) { 2410 dev_err(&hdev->pdev->dev, 2411 "could not configure rx private waterline %d\n", 2412 ret); 2413 goto out; 2414 } 2415 2416 ret = hclge_common_thrd_config(hdev, pkt_buf); 2417 if (ret) { 2418 dev_err(&hdev->pdev->dev, 2419 "could not configure common threshold %d\n", 2420 ret); 2421 goto out; 2422 } 2423 } 2424 2425 ret = hclge_common_wl_config(hdev, pkt_buf); 2426 if (ret) 2427 dev_err(&hdev->pdev->dev, 2428 "could not configure common waterline %d\n", ret); 2429 2430 out: 2431 kfree(pkt_buf); 2432 return ret; 2433 } 2434 2435 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2436 { 2437 struct hnae3_handle *roce = &vport->roce; 2438 struct hnae3_handle *nic = &vport->nic; 2439 struct hclge_dev *hdev = vport->back; 2440 2441 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2442 2443 if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi) 2444 return -EINVAL; 2445 2446 roce->rinfo.base_vector = hdev->num_nic_msi; 2447 2448 roce->rinfo.netdev = nic->kinfo.netdev; 2449 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2450 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2451 2452 roce->pdev = nic->pdev; 2453 roce->ae_algo = nic->ae_algo; 2454 bitmap_copy(roce->numa_node_mask.bits, nic->numa_node_mask.bits, 2455 MAX_NUMNODES); 2456 2457 return 0; 2458 } 2459 2460 static int hclge_init_msi(struct hclge_dev *hdev) 2461 { 2462 struct pci_dev *pdev = hdev->pdev; 2463 int vectors; 2464 int i; 2465 2466 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2467 hdev->num_msi, 2468 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2469 if (vectors < 0) { 2470 dev_err(&pdev->dev, 2471 "failed(%d) to allocate MSI/MSI-X vectors\n", 2472 vectors); 2473 return vectors; 2474 } 2475 if (vectors < hdev->num_msi) 2476 dev_warn(&hdev->pdev->dev, 2477 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2478 hdev->num_msi, vectors); 2479 2480 hdev->num_msi = vectors; 2481 hdev->num_msi_left = vectors; 2482 2483 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2484 sizeof(u16), GFP_KERNEL); 2485 if (!hdev->vector_status) { 2486 pci_free_irq_vectors(pdev); 2487 return -ENOMEM; 2488 } 2489 2490 for (i = 0; i < hdev->num_msi; i++) 2491 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2492 2493 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2494 sizeof(int), GFP_KERNEL); 2495 if (!hdev->vector_irq) { 2496 pci_free_irq_vectors(pdev); 2497 return -ENOMEM; 2498 } 2499 2500 return 0; 2501 } 2502 2503 static u8 hclge_check_speed_dup(u8 duplex, int speed) 2504 { 2505 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 2506 duplex = HCLGE_MAC_FULL; 2507 2508 return duplex; 2509 } 2510 2511 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = { 2512 {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M}, 2513 {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M}, 2514 {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G}, 2515 {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G}, 2516 {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G}, 2517 {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G}, 2518 {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G}, 2519 {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G}, 2520 {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G}, 2521 }; 2522 2523 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw) 2524 { 2525 u16 i; 2526 2527 for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) { 2528 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) { 2529 *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw; 2530 return 0; 2531 } 2532 } 2533 2534 return -EINVAL; 2535 } 2536 2537 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 2538 u8 duplex, u8 lane_num) 2539 { 2540 struct hclge_config_mac_speed_dup_cmd *req; 2541 struct hclge_desc desc; 2542 u32 speed_fw; 2543 int ret; 2544 2545 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2546 2547 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2548 2549 if (duplex) 2550 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1); 2551 2552 ret = hclge_convert_to_fw_speed(speed, &speed_fw); 2553 if (ret) { 2554 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2555 return ret; 2556 } 2557 2558 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S, 2559 speed_fw); 2560 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2561 1); 2562 req->lane_num = lane_num; 2563 2564 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2565 if (ret) { 2566 dev_err(&hdev->pdev->dev, 2567 "mac speed/duplex config cmd failed %d.\n", ret); 2568 return ret; 2569 } 2570 2571 return 0; 2572 } 2573 2574 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num) 2575 { 2576 struct hclge_mac *mac = &hdev->hw.mac; 2577 int ret; 2578 2579 duplex = hclge_check_speed_dup(duplex, speed); 2580 if (!mac->support_autoneg && mac->speed == speed && 2581 mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0)) 2582 return 0; 2583 2584 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num); 2585 if (ret) 2586 return ret; 2587 2588 hdev->hw.mac.speed = speed; 2589 hdev->hw.mac.duplex = duplex; 2590 if (!lane_num) 2591 hdev->hw.mac.lane_num = lane_num; 2592 2593 return 0; 2594 } 2595 2596 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2597 u8 duplex, u8 lane_num) 2598 { 2599 struct hclge_vport *vport = hclge_get_vport(handle); 2600 struct hclge_dev *hdev = vport->back; 2601 2602 return hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num); 2603 } 2604 2605 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2606 { 2607 struct hclge_config_auto_neg_cmd *req; 2608 struct hclge_desc desc; 2609 u32 flag = 0; 2610 int ret; 2611 2612 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2613 2614 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2615 if (enable) 2616 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U); 2617 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2618 2619 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2620 if (ret) 2621 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2622 ret); 2623 2624 return ret; 2625 } 2626 2627 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2628 { 2629 struct hclge_vport *vport = hclge_get_vport(handle); 2630 struct hclge_dev *hdev = vport->back; 2631 2632 if (!hdev->hw.mac.support_autoneg) { 2633 if (enable) { 2634 dev_err(&hdev->pdev->dev, 2635 "autoneg is not supported by current port\n"); 2636 return -EOPNOTSUPP; 2637 } else { 2638 return 0; 2639 } 2640 } 2641 2642 return hclge_set_autoneg_en(hdev, enable); 2643 } 2644 2645 static int hclge_get_autoneg(struct hnae3_handle *handle) 2646 { 2647 struct hclge_vport *vport = hclge_get_vport(handle); 2648 struct hclge_dev *hdev = vport->back; 2649 struct phy_device *phydev = hdev->hw.mac.phydev; 2650 2651 if (phydev) 2652 return phydev->autoneg; 2653 2654 return hdev->hw.mac.autoneg; 2655 } 2656 2657 static int hclge_restart_autoneg(struct hnae3_handle *handle) 2658 { 2659 struct hclge_vport *vport = hclge_get_vport(handle); 2660 struct hclge_dev *hdev = vport->back; 2661 int ret; 2662 2663 dev_dbg(&hdev->pdev->dev, "restart autoneg\n"); 2664 2665 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2666 if (ret) 2667 return ret; 2668 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2669 } 2670 2671 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt) 2672 { 2673 struct hclge_vport *vport = hclge_get_vport(handle); 2674 struct hclge_dev *hdev = vport->back; 2675 2676 if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) 2677 return hclge_set_autoneg_en(hdev, !halt); 2678 2679 return 0; 2680 } 2681 2682 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev, 2683 struct hclge_desc *desc, u32 desc_len) 2684 { 2685 u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2; 2686 u32 desc_index = 0; 2687 u32 data_index = 0; 2688 u32 i; 2689 2690 for (i = 0; i < lane_size; i++) { 2691 if (data_index >= HCLGE_DESC_DATA_LEN) { 2692 desc_index++; 2693 data_index = 0; 2694 } 2695 2696 if (desc_index >= desc_len) 2697 return; 2698 2699 hdev->fec_stats.per_lanes[i] += 2700 le32_to_cpu(desc[desc_index].data[data_index]); 2701 data_index++; 2702 } 2703 } 2704 2705 static void hclge_parse_fec_stats(struct hclge_dev *hdev, 2706 struct hclge_desc *desc, u32 desc_len) 2707 { 2708 struct hclge_query_fec_stats_cmd *req; 2709 2710 req = (struct hclge_query_fec_stats_cmd *)desc[0].data; 2711 2712 hdev->fec_stats.base_r_lane_num = req->base_r_lane_num; 2713 hdev->fec_stats.rs_corr_blocks += 2714 le32_to_cpu(req->rs_fec_corr_blocks); 2715 hdev->fec_stats.rs_uncorr_blocks += 2716 le32_to_cpu(req->rs_fec_uncorr_blocks); 2717 hdev->fec_stats.rs_error_blocks += 2718 le32_to_cpu(req->rs_fec_error_blocks); 2719 hdev->fec_stats.base_r_corr_blocks += 2720 le32_to_cpu(req->base_r_fec_corr_blocks); 2721 hdev->fec_stats.base_r_uncorr_blocks += 2722 le32_to_cpu(req->base_r_fec_uncorr_blocks); 2723 2724 hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1); 2725 } 2726 2727 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev) 2728 { 2729 struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM]; 2730 int ret; 2731 u32 i; 2732 2733 for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) { 2734 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS, 2735 true); 2736 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1)) 2737 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2738 } 2739 2740 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM); 2741 if (ret) 2742 return ret; 2743 2744 hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM); 2745 2746 return 0; 2747 } 2748 2749 static void hclge_update_fec_stats(struct hclge_dev *hdev) 2750 { 2751 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2752 int ret; 2753 2754 if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || 2755 test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state)) 2756 return; 2757 2758 ret = hclge_update_fec_stats_hw(hdev); 2759 if (ret) 2760 dev_err(&hdev->pdev->dev, 2761 "failed to update fec stats, ret = %d\n", ret); 2762 2763 clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state); 2764 } 2765 2766 static void hclge_get_fec_stats_total(struct hclge_dev *hdev, 2767 struct ethtool_fec_stats *fec_stats) 2768 { 2769 fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks; 2770 fec_stats->uncorrectable_blocks.total = 2771 hdev->fec_stats.rs_uncorr_blocks; 2772 } 2773 2774 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev, 2775 struct ethtool_fec_stats *fec_stats) 2776 { 2777 u32 i; 2778 2779 if (hdev->fec_stats.base_r_lane_num == 0 || 2780 hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) { 2781 dev_err(&hdev->pdev->dev, 2782 "fec stats lane number(%llu) is invalid\n", 2783 hdev->fec_stats.base_r_lane_num); 2784 return; 2785 } 2786 2787 for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) { 2788 fec_stats->corrected_blocks.lanes[i] = 2789 hdev->fec_stats.base_r_corr_per_lanes[i]; 2790 fec_stats->uncorrectable_blocks.lanes[i] = 2791 hdev->fec_stats.base_r_uncorr_per_lanes[i]; 2792 } 2793 } 2794 2795 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev, 2796 struct ethtool_fec_stats *fec_stats) 2797 { 2798 u32 fec_mode = hdev->hw.mac.fec_mode; 2799 2800 switch (fec_mode) { 2801 case BIT(HNAE3_FEC_RS): 2802 case BIT(HNAE3_FEC_LLRS): 2803 hclge_get_fec_stats_total(hdev, fec_stats); 2804 break; 2805 case BIT(HNAE3_FEC_BASER): 2806 hclge_get_fec_stats_lanes(hdev, fec_stats); 2807 break; 2808 default: 2809 dev_err(&hdev->pdev->dev, 2810 "fec stats is not supported by current fec mode(0x%x)\n", 2811 fec_mode); 2812 break; 2813 } 2814 } 2815 2816 static void hclge_get_fec_stats(struct hnae3_handle *handle, 2817 struct ethtool_fec_stats *fec_stats) 2818 { 2819 struct hclge_vport *vport = hclge_get_vport(handle); 2820 struct hclge_dev *hdev = vport->back; 2821 u32 fec_mode = hdev->hw.mac.fec_mode; 2822 2823 if (fec_mode == BIT(HNAE3_FEC_NONE) || 2824 fec_mode == BIT(HNAE3_FEC_AUTO) || 2825 fec_mode == BIT(HNAE3_FEC_USER_DEF)) 2826 return; 2827 2828 hclge_update_fec_stats(hdev); 2829 2830 hclge_comm_get_fec_stats(hdev, fec_stats); 2831 } 2832 2833 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode) 2834 { 2835 struct hclge_config_fec_cmd *req; 2836 struct hclge_desc desc; 2837 int ret; 2838 2839 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false); 2840 2841 req = (struct hclge_config_fec_cmd *)desc.data; 2842 if (fec_mode & BIT(HNAE3_FEC_AUTO)) 2843 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1); 2844 if (fec_mode & BIT(HNAE3_FEC_RS)) 2845 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2846 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS); 2847 if (fec_mode & BIT(HNAE3_FEC_LLRS)) 2848 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2849 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS); 2850 if (fec_mode & BIT(HNAE3_FEC_BASER)) 2851 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2852 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER); 2853 2854 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2855 if (ret) 2856 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret); 2857 2858 return ret; 2859 } 2860 2861 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode) 2862 { 2863 struct hclge_vport *vport = hclge_get_vport(handle); 2864 struct hclge_dev *hdev = vport->back; 2865 struct hclge_mac *mac = &hdev->hw.mac; 2866 int ret; 2867 2868 if (fec_mode && !(mac->fec_ability & fec_mode)) { 2869 dev_err(&hdev->pdev->dev, "unsupported fec mode\n"); 2870 return -EINVAL; 2871 } 2872 2873 ret = hclge_set_fec_hw(hdev, fec_mode); 2874 if (ret) 2875 return ret; 2876 2877 mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF); 2878 return 0; 2879 } 2880 2881 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability, 2882 u8 *fec_mode) 2883 { 2884 struct hclge_vport *vport = hclge_get_vport(handle); 2885 struct hclge_dev *hdev = vport->back; 2886 struct hclge_mac *mac = &hdev->hw.mac; 2887 2888 if (fec_ability) 2889 *fec_ability = mac->fec_ability; 2890 if (fec_mode) 2891 *fec_mode = mac->fec_mode; 2892 } 2893 2894 static int hclge_mac_init(struct hclge_dev *hdev) 2895 { 2896 struct hclge_mac *mac = &hdev->hw.mac; 2897 int ret; 2898 2899 hdev->support_sfp_query = true; 2900 2901 if (!test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 2902 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 2903 2904 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed, 2905 hdev->hw.mac.duplex, hdev->hw.mac.lane_num); 2906 if (ret) 2907 return ret; 2908 2909 if (hdev->hw.mac.support_autoneg) { 2910 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg); 2911 if (ret) 2912 return ret; 2913 } 2914 2915 mac->link = 0; 2916 2917 if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { 2918 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode); 2919 if (ret) 2920 return ret; 2921 } 2922 2923 ret = hclge_set_mac_mtu(hdev, hdev->mps); 2924 if (ret) { 2925 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret); 2926 return ret; 2927 } 2928 2929 ret = hclge_set_default_loopback(hdev); 2930 if (ret) 2931 return ret; 2932 2933 ret = hclge_buffer_alloc(hdev); 2934 if (ret) 2935 dev_err(&hdev->pdev->dev, 2936 "allocate buffer fail, ret=%d\n", ret); 2937 2938 return ret; 2939 } 2940 2941 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 2942 { 2943 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2944 !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) { 2945 hdev->last_mbx_scheduled = jiffies; 2946 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2947 } 2948 } 2949 2950 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 2951 { 2952 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2953 test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) && 2954 !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) { 2955 hdev->last_rst_scheduled = jiffies; 2956 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2957 } 2958 } 2959 2960 static void hclge_errhand_task_schedule(struct hclge_dev *hdev) 2961 { 2962 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2963 !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 2964 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2965 } 2966 2967 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time) 2968 { 2969 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2970 !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 2971 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time); 2972 } 2973 2974 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status) 2975 { 2976 struct hclge_link_status_cmd *req; 2977 struct hclge_desc desc; 2978 int ret; 2979 2980 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 2981 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2982 if (ret) { 2983 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 2984 ret); 2985 return ret; 2986 } 2987 2988 req = (struct hclge_link_status_cmd *)desc.data; 2989 *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ? 2990 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 2991 2992 return 0; 2993 } 2994 2995 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status) 2996 { 2997 struct phy_device *phydev = hdev->hw.mac.phydev; 2998 2999 *link_status = HCLGE_LINK_STATUS_DOWN; 3000 3001 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) 3002 return 0; 3003 3004 if (phydev && (phydev->state != PHY_RUNNING || !phydev->link)) 3005 return 0; 3006 3007 return hclge_get_mac_link_status(hdev, link_status); 3008 } 3009 3010 static void hclge_push_link_status(struct hclge_dev *hdev) 3011 { 3012 struct hclge_vport *vport; 3013 int ret; 3014 u16 i; 3015 3016 for (i = 0; i < pci_num_vf(hdev->pdev); i++) { 3017 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 3018 3019 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) || 3020 vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO) 3021 continue; 3022 3023 ret = hclge_push_vf_link_status(vport); 3024 if (ret) { 3025 dev_err(&hdev->pdev->dev, 3026 "failed to push link status to vf%u, ret = %d\n", 3027 i, ret); 3028 } 3029 } 3030 } 3031 3032 static void hclge_update_link_status(struct hclge_dev *hdev) 3033 { 3034 struct hnae3_handle *rhandle = &hdev->vport[0].roce; 3035 struct hnae3_handle *handle = &hdev->vport[0].nic; 3036 struct hnae3_client *rclient = hdev->roce_client; 3037 struct hnae3_client *client = hdev->nic_client; 3038 int state; 3039 int ret; 3040 3041 if (!client) 3042 return; 3043 3044 if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state)) 3045 return; 3046 3047 ret = hclge_get_mac_phy_link(hdev, &state); 3048 if (ret) { 3049 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3050 return; 3051 } 3052 3053 if (state != hdev->hw.mac.link) { 3054 hdev->hw.mac.link = state; 3055 if (state == HCLGE_LINK_STATUS_UP) 3056 hclge_update_port_info(hdev); 3057 3058 client->ops->link_status_change(handle, state); 3059 hclge_config_mac_tnl_int(hdev, state); 3060 if (rclient && rclient->ops->link_status_change) 3061 rclient->ops->link_status_change(rhandle, state); 3062 3063 hclge_push_link_status(hdev); 3064 } 3065 3066 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3067 } 3068 3069 static void hclge_update_speed_advertising(struct hclge_mac *mac) 3070 { 3071 u32 speed_ability; 3072 3073 if (hclge_get_speed_bit(mac->speed, &speed_ability)) 3074 return; 3075 3076 switch (mac->module_type) { 3077 case HNAE3_MODULE_TYPE_FIBRE_LR: 3078 hclge_convert_setting_lr(speed_ability, mac->advertising); 3079 break; 3080 case HNAE3_MODULE_TYPE_FIBRE_SR: 3081 case HNAE3_MODULE_TYPE_AOC: 3082 hclge_convert_setting_sr(speed_ability, mac->advertising); 3083 break; 3084 case HNAE3_MODULE_TYPE_CR: 3085 hclge_convert_setting_cr(speed_ability, mac->advertising); 3086 break; 3087 case HNAE3_MODULE_TYPE_KR: 3088 hclge_convert_setting_kr(speed_ability, mac->advertising); 3089 break; 3090 default: 3091 break; 3092 } 3093 } 3094 3095 static void hclge_update_fec_advertising(struct hclge_mac *mac) 3096 { 3097 if (mac->fec_mode & BIT(HNAE3_FEC_RS)) 3098 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 3099 mac->advertising); 3100 else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS)) 3101 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 3102 mac->advertising); 3103 else if (mac->fec_mode & BIT(HNAE3_FEC_BASER)) 3104 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 3105 mac->advertising); 3106 else 3107 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 3108 mac->advertising); 3109 } 3110 3111 static void hclge_update_pause_advertising(struct hclge_dev *hdev) 3112 { 3113 struct hclge_mac *mac = &hdev->hw.mac; 3114 bool rx_en, tx_en; 3115 3116 switch (hdev->fc_mode_last_time) { 3117 case HCLGE_FC_RX_PAUSE: 3118 rx_en = true; 3119 tx_en = false; 3120 break; 3121 case HCLGE_FC_TX_PAUSE: 3122 rx_en = false; 3123 tx_en = true; 3124 break; 3125 case HCLGE_FC_FULL: 3126 rx_en = true; 3127 tx_en = true; 3128 break; 3129 default: 3130 rx_en = false; 3131 tx_en = false; 3132 break; 3133 } 3134 3135 linkmode_set_pause(mac->advertising, tx_en, rx_en); 3136 } 3137 3138 static void hclge_update_advertising(struct hclge_dev *hdev) 3139 { 3140 struct hclge_mac *mac = &hdev->hw.mac; 3141 3142 linkmode_zero(mac->advertising); 3143 hclge_update_speed_advertising(mac); 3144 hclge_update_fec_advertising(mac); 3145 hclge_update_pause_advertising(hdev); 3146 } 3147 3148 static void hclge_update_port_capability(struct hclge_dev *hdev, 3149 struct hclge_mac *mac) 3150 { 3151 if (hnae3_dev_fec_supported(hdev)) 3152 hclge_convert_setting_fec(mac); 3153 3154 /* firmware can not identify back plane type, the media type 3155 * read from configuration can help deal it 3156 */ 3157 if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE && 3158 mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN) 3159 mac->module_type = HNAE3_MODULE_TYPE_KR; 3160 else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3161 mac->module_type = HNAE3_MODULE_TYPE_TP; 3162 3163 if (mac->support_autoneg) { 3164 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported); 3165 linkmode_copy(mac->advertising, mac->supported); 3166 } else { 3167 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3168 mac->supported); 3169 hclge_update_advertising(hdev); 3170 } 3171 } 3172 3173 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed) 3174 { 3175 struct hclge_sfp_info_cmd *resp; 3176 struct hclge_desc desc; 3177 int ret; 3178 3179 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3180 resp = (struct hclge_sfp_info_cmd *)desc.data; 3181 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3182 if (ret == -EOPNOTSUPP) { 3183 dev_warn(&hdev->pdev->dev, 3184 "IMP do not support get SFP speed %d\n", ret); 3185 return ret; 3186 } else if (ret) { 3187 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret); 3188 return ret; 3189 } 3190 3191 *speed = le32_to_cpu(resp->speed); 3192 3193 return 0; 3194 } 3195 3196 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac) 3197 { 3198 struct hclge_sfp_info_cmd *resp; 3199 struct hclge_desc desc; 3200 int ret; 3201 3202 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3203 resp = (struct hclge_sfp_info_cmd *)desc.data; 3204 3205 resp->query_type = QUERY_ACTIVE_SPEED; 3206 3207 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3208 if (ret == -EOPNOTSUPP) { 3209 dev_warn(&hdev->pdev->dev, 3210 "IMP does not support get SFP info %d\n", ret); 3211 return ret; 3212 } else if (ret) { 3213 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret); 3214 return ret; 3215 } 3216 3217 /* In some case, mac speed get from IMP may be 0, it shouldn't be 3218 * set to mac->speed. 3219 */ 3220 if (!le32_to_cpu(resp->speed)) 3221 return 0; 3222 3223 mac->speed = le32_to_cpu(resp->speed); 3224 /* if resp->speed_ability is 0, it means it's an old version 3225 * firmware, do not update these params 3226 */ 3227 if (resp->speed_ability) { 3228 mac->module_type = le32_to_cpu(resp->module_type); 3229 mac->speed_ability = le32_to_cpu(resp->speed_ability); 3230 mac->autoneg = resp->autoneg; 3231 mac->support_autoneg = resp->autoneg_ability; 3232 mac->speed_type = QUERY_ACTIVE_SPEED; 3233 mac->lane_num = resp->lane_num; 3234 if (!resp->active_fec) 3235 mac->fec_mode = 0; 3236 else 3237 mac->fec_mode = BIT(resp->active_fec); 3238 mac->fec_ability = resp->fec_ability; 3239 } else { 3240 mac->speed_type = QUERY_SFP_SPEED; 3241 } 3242 3243 return 0; 3244 } 3245 3246 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle, 3247 struct ethtool_link_ksettings *cmd) 3248 { 3249 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3250 struct hclge_vport *vport = hclge_get_vport(handle); 3251 struct hclge_phy_link_ksetting_0_cmd *req0; 3252 struct hclge_phy_link_ksetting_1_cmd *req1; 3253 u32 supported, advertising, lp_advertising; 3254 struct hclge_dev *hdev = vport->back; 3255 int ret; 3256 3257 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3258 true); 3259 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3260 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3261 true); 3262 3263 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3264 if (ret) { 3265 dev_err(&hdev->pdev->dev, 3266 "failed to get phy link ksetting, ret = %d.\n", ret); 3267 return ret; 3268 } 3269 3270 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3271 cmd->base.autoneg = req0->autoneg; 3272 cmd->base.speed = le32_to_cpu(req0->speed); 3273 cmd->base.duplex = req0->duplex; 3274 cmd->base.port = req0->port; 3275 cmd->base.transceiver = req0->transceiver; 3276 cmd->base.phy_address = req0->phy_address; 3277 cmd->base.eth_tp_mdix = req0->eth_tp_mdix; 3278 cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl; 3279 supported = le32_to_cpu(req0->supported); 3280 advertising = le32_to_cpu(req0->advertising); 3281 lp_advertising = le32_to_cpu(req0->lp_advertising); 3282 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3283 supported); 3284 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3285 advertising); 3286 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 3287 lp_advertising); 3288 3289 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3290 cmd->base.master_slave_cfg = req1->master_slave_cfg; 3291 cmd->base.master_slave_state = req1->master_slave_state; 3292 3293 return 0; 3294 } 3295 3296 static int 3297 hclge_set_phy_link_ksettings(struct hnae3_handle *handle, 3298 const struct ethtool_link_ksettings *cmd) 3299 { 3300 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3301 struct hclge_vport *vport = hclge_get_vport(handle); 3302 struct hclge_phy_link_ksetting_0_cmd *req0; 3303 struct hclge_phy_link_ksetting_1_cmd *req1; 3304 struct hclge_dev *hdev = vport->back; 3305 u32 advertising; 3306 int ret; 3307 3308 if (cmd->base.autoneg == AUTONEG_DISABLE && 3309 ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) || 3310 (cmd->base.duplex != DUPLEX_HALF && 3311 cmd->base.duplex != DUPLEX_FULL))) 3312 return -EINVAL; 3313 3314 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3315 false); 3316 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3317 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3318 false); 3319 3320 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3321 req0->autoneg = cmd->base.autoneg; 3322 req0->speed = cpu_to_le32(cmd->base.speed); 3323 req0->duplex = cmd->base.duplex; 3324 ethtool_convert_link_mode_to_legacy_u32(&advertising, 3325 cmd->link_modes.advertising); 3326 req0->advertising = cpu_to_le32(advertising); 3327 req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; 3328 3329 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3330 req1->master_slave_cfg = cmd->base.master_slave_cfg; 3331 3332 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3333 if (ret) { 3334 dev_err(&hdev->pdev->dev, 3335 "failed to set phy link ksettings, ret = %d.\n", ret); 3336 return ret; 3337 } 3338 3339 hdev->hw.mac.req_autoneg = cmd->base.autoneg; 3340 hdev->hw.mac.req_speed = cmd->base.speed; 3341 hdev->hw.mac.req_duplex = cmd->base.duplex; 3342 linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising); 3343 3344 return 0; 3345 } 3346 3347 static int hclge_update_tp_port_info(struct hclge_dev *hdev) 3348 { 3349 struct ethtool_link_ksettings cmd; 3350 int ret; 3351 3352 if (!hnae3_dev_phy_imp_supported(hdev)) 3353 return 0; 3354 3355 ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd); 3356 if (ret) 3357 return ret; 3358 3359 hdev->hw.mac.autoneg = cmd.base.autoneg; 3360 hdev->hw.mac.speed = cmd.base.speed; 3361 hdev->hw.mac.duplex = cmd.base.duplex; 3362 linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising); 3363 3364 return 0; 3365 } 3366 3367 static int hclge_tp_port_init(struct hclge_dev *hdev) 3368 { 3369 struct ethtool_link_ksettings cmd; 3370 3371 if (!hnae3_dev_phy_imp_supported(hdev)) 3372 return 0; 3373 3374 cmd.base.autoneg = hdev->hw.mac.req_autoneg; 3375 cmd.base.speed = hdev->hw.mac.req_speed; 3376 cmd.base.duplex = hdev->hw.mac.req_duplex; 3377 linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising); 3378 3379 return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd); 3380 } 3381 3382 static int hclge_update_port_info(struct hclge_dev *hdev) 3383 { 3384 struct hclge_mac *mac = &hdev->hw.mac; 3385 int speed; 3386 int ret; 3387 3388 /* get the port info from SFP cmd if not copper port */ 3389 if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3390 return hclge_update_tp_port_info(hdev); 3391 3392 /* if IMP does not support get SFP/qSFP info, return directly */ 3393 if (!hdev->support_sfp_query) 3394 return 0; 3395 3396 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3397 speed = mac->speed; 3398 ret = hclge_get_sfp_info(hdev, mac); 3399 } else { 3400 speed = HCLGE_MAC_SPEED_UNKNOWN; 3401 ret = hclge_get_sfp_speed(hdev, &speed); 3402 } 3403 3404 if (ret == -EOPNOTSUPP) { 3405 hdev->support_sfp_query = false; 3406 return ret; 3407 } else if (ret) { 3408 return ret; 3409 } 3410 3411 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3412 if (mac->speed_type == QUERY_ACTIVE_SPEED) { 3413 hclge_update_port_capability(hdev, mac); 3414 if (mac->speed != speed) 3415 (void)hclge_tm_port_shaper_cfg(hdev); 3416 return 0; 3417 } 3418 return hclge_cfg_mac_speed_dup(hdev, mac->speed, 3419 HCLGE_MAC_FULL, mac->lane_num); 3420 } else { 3421 if (speed == HCLGE_MAC_SPEED_UNKNOWN) 3422 return 0; /* do nothing if no SFP */ 3423 3424 /* must config full duplex for SFP */ 3425 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0); 3426 } 3427 } 3428 3429 static int hclge_get_status(struct hnae3_handle *handle) 3430 { 3431 struct hclge_vport *vport = hclge_get_vport(handle); 3432 struct hclge_dev *hdev = vport->back; 3433 3434 hclge_update_link_status(hdev); 3435 3436 return hdev->hw.mac.link; 3437 } 3438 3439 static struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf) 3440 { 3441 if (!pci_num_vf(hdev->pdev)) { 3442 dev_err(&hdev->pdev->dev, 3443 "SRIOV is disabled, can not get vport(%d) info.\n", vf); 3444 return NULL; 3445 } 3446 3447 if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) { 3448 dev_err(&hdev->pdev->dev, 3449 "vf id(%d) is out of range(0 <= vfid < %d)\n", 3450 vf, pci_num_vf(hdev->pdev)); 3451 return NULL; 3452 } 3453 3454 /* VF start from 1 in vport */ 3455 vf += HCLGE_VF_VPORT_START_NUM; 3456 return &hdev->vport[vf]; 3457 } 3458 3459 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf, 3460 struct ifla_vf_info *ivf) 3461 { 3462 struct hclge_vport *vport = hclge_get_vport(handle); 3463 struct hclge_dev *hdev = vport->back; 3464 3465 vport = hclge_get_vf_vport(hdev, vf); 3466 if (!vport) 3467 return -EINVAL; 3468 3469 ivf->vf = vf; 3470 ivf->linkstate = vport->vf_info.link_state; 3471 ivf->spoofchk = vport->vf_info.spoofchk; 3472 ivf->trusted = vport->vf_info.trusted; 3473 ivf->min_tx_rate = 0; 3474 ivf->max_tx_rate = vport->vf_info.max_tx_rate; 3475 ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag; 3476 ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto); 3477 ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos; 3478 ether_addr_copy(ivf->mac, vport->vf_info.mac); 3479 3480 return 0; 3481 } 3482 3483 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, 3484 int link_state) 3485 { 3486 struct hclge_vport *vport = hclge_get_vport(handle); 3487 struct hclge_dev *hdev = vport->back; 3488 int link_state_old; 3489 int ret; 3490 3491 vport = hclge_get_vf_vport(hdev, vf); 3492 if (!vport) 3493 return -EINVAL; 3494 3495 link_state_old = vport->vf_info.link_state; 3496 vport->vf_info.link_state = link_state; 3497 3498 /* return success directly if the VF is unalive, VF will 3499 * query link state itself when it starts work. 3500 */ 3501 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3502 return 0; 3503 3504 ret = hclge_push_vf_link_status(vport); 3505 if (ret) { 3506 vport->vf_info.link_state = link_state_old; 3507 dev_err(&hdev->pdev->dev, 3508 "failed to push vf%d link status, ret = %d\n", vf, ret); 3509 } 3510 3511 return ret; 3512 } 3513 3514 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 3515 { 3516 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; 3517 3518 /* fetch the events from their corresponding regs */ 3519 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 3520 msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 3521 hw_err_src_reg = hclge_read_dev(&hdev->hw, 3522 HCLGE_RAS_PF_OTHER_INT_STS_REG); 3523 3524 /* Assumption: If by any chance reset and mailbox events are reported 3525 * together then we will only process reset event in this go and will 3526 * defer the processing of the mailbox events. Since, we would have not 3527 * cleared RX CMDQ event this time we would receive again another 3528 * interrupt from H/W just for the mailbox. 3529 * 3530 * check for vector0 reset event sources 3531 */ 3532 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { 3533 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); 3534 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); 3535 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3536 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3537 hdev->rst_stats.imp_rst_cnt++; 3538 return HCLGE_VECTOR0_EVENT_RST; 3539 } 3540 3541 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { 3542 dev_info(&hdev->pdev->dev, "global reset interrupt\n"); 3543 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3544 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 3545 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3546 hdev->rst_stats.global_rst_cnt++; 3547 return HCLGE_VECTOR0_EVENT_RST; 3548 } 3549 3550 /* check for vector0 msix event and hardware error event source */ 3551 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK || 3552 hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK) 3553 return HCLGE_VECTOR0_EVENT_ERR; 3554 3555 /* check for vector0 ptp event source */ 3556 if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) { 3557 *clearval = msix_src_reg; 3558 return HCLGE_VECTOR0_EVENT_PTP; 3559 } 3560 3561 /* check for vector0 mailbox(=CMDQ RX) event source */ 3562 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 3563 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 3564 *clearval = cmdq_src_reg; 3565 return HCLGE_VECTOR0_EVENT_MBX; 3566 } 3567 3568 /* print other vector0 event source */ 3569 dev_info(&hdev->pdev->dev, 3570 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n", 3571 cmdq_src_reg, hw_err_src_reg, msix_src_reg); 3572 3573 return HCLGE_VECTOR0_EVENT_OTHER; 3574 } 3575 3576 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 3577 u32 regclr) 3578 { 3579 #define HCLGE_IMP_RESET_DELAY 5 3580 3581 switch (event_type) { 3582 case HCLGE_VECTOR0_EVENT_PTP: 3583 case HCLGE_VECTOR0_EVENT_RST: 3584 if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B)) 3585 mdelay(HCLGE_IMP_RESET_DELAY); 3586 3587 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 3588 break; 3589 case HCLGE_VECTOR0_EVENT_MBX: 3590 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 3591 break; 3592 default: 3593 break; 3594 } 3595 } 3596 3597 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 3598 { 3599 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 3600 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 3601 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 3602 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 3603 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 3604 } 3605 3606 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 3607 { 3608 writel(enable ? 1 : 0, vector->addr); 3609 } 3610 3611 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 3612 { 3613 struct hclge_dev *hdev = data; 3614 unsigned long flags; 3615 u32 clearval = 0; 3616 u32 event_cause; 3617 3618 hclge_enable_vector(&hdev->misc_vector, false); 3619 event_cause = hclge_check_event_cause(hdev, &clearval); 3620 3621 /* vector 0 interrupt is shared with reset and mailbox source events. */ 3622 switch (event_cause) { 3623 case HCLGE_VECTOR0_EVENT_ERR: 3624 hclge_errhand_task_schedule(hdev); 3625 break; 3626 case HCLGE_VECTOR0_EVENT_RST: 3627 hclge_reset_task_schedule(hdev); 3628 break; 3629 case HCLGE_VECTOR0_EVENT_PTP: 3630 spin_lock_irqsave(&hdev->ptp->lock, flags); 3631 hclge_ptp_clean_tx_hwts(hdev); 3632 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 3633 break; 3634 case HCLGE_VECTOR0_EVENT_MBX: 3635 /* If we are here then, 3636 * 1. Either we are not handling any mbx task and we are not 3637 * scheduled as well 3638 * OR 3639 * 2. We could be handling a mbx task but nothing more is 3640 * scheduled. 3641 * In both cases, we should schedule mbx task as there are more 3642 * mbx messages reported by this interrupt. 3643 */ 3644 hclge_mbx_task_schedule(hdev); 3645 break; 3646 default: 3647 dev_warn(&hdev->pdev->dev, 3648 "received unknown or unhandled event of vector0\n"); 3649 break; 3650 } 3651 3652 hclge_clear_event_cause(hdev, event_cause, clearval); 3653 3654 /* Enable interrupt if it is not caused by reset event or error event */ 3655 if (event_cause == HCLGE_VECTOR0_EVENT_PTP || 3656 event_cause == HCLGE_VECTOR0_EVENT_MBX || 3657 event_cause == HCLGE_VECTOR0_EVENT_OTHER) 3658 hclge_enable_vector(&hdev->misc_vector, true); 3659 3660 return IRQ_HANDLED; 3661 } 3662 3663 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 3664 { 3665 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 3666 dev_warn(&hdev->pdev->dev, 3667 "vector(vector_id %d) has been freed.\n", vector_id); 3668 return; 3669 } 3670 3671 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 3672 hdev->num_msi_left += 1; 3673 hdev->num_msi_used -= 1; 3674 } 3675 3676 static void hclge_get_misc_vector(struct hclge_dev *hdev) 3677 { 3678 struct hclge_misc_vector *vector = &hdev->misc_vector; 3679 3680 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 3681 3682 vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 3683 hdev->vector_status[0] = 0; 3684 3685 hdev->num_msi_left -= 1; 3686 hdev->num_msi_used += 1; 3687 } 3688 3689 static int hclge_misc_irq_init(struct hclge_dev *hdev) 3690 { 3691 int ret; 3692 3693 hclge_get_misc_vector(hdev); 3694 3695 /* this would be explicitly freed in the end */ 3696 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 3697 HCLGE_NAME, pci_name(hdev->pdev)); 3698 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 3699 0, hdev->misc_vector.name, hdev); 3700 if (ret) { 3701 hclge_free_vector(hdev, 0); 3702 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 3703 hdev->misc_vector.vector_irq); 3704 } 3705 3706 return ret; 3707 } 3708 3709 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 3710 { 3711 free_irq(hdev->misc_vector.vector_irq, hdev); 3712 hclge_free_vector(hdev, 0); 3713 } 3714 3715 int hclge_notify_client(struct hclge_dev *hdev, 3716 enum hnae3_reset_notify_type type) 3717 { 3718 struct hnae3_handle *handle = &hdev->vport[0].nic; 3719 struct hnae3_client *client = hdev->nic_client; 3720 int ret; 3721 3722 if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client) 3723 return 0; 3724 3725 if (!client->ops->reset_notify) 3726 return -EOPNOTSUPP; 3727 3728 ret = client->ops->reset_notify(handle, type); 3729 if (ret) 3730 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 3731 type, ret); 3732 3733 return ret; 3734 } 3735 3736 static int hclge_notify_roce_client(struct hclge_dev *hdev, 3737 enum hnae3_reset_notify_type type) 3738 { 3739 struct hnae3_handle *handle = &hdev->vport[0].roce; 3740 struct hnae3_client *client = hdev->roce_client; 3741 int ret; 3742 3743 if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client) 3744 return 0; 3745 3746 if (!client->ops->reset_notify) 3747 return -EOPNOTSUPP; 3748 3749 ret = client->ops->reset_notify(handle, type); 3750 if (ret) 3751 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 3752 type, ret); 3753 3754 return ret; 3755 } 3756 3757 static int hclge_reset_wait(struct hclge_dev *hdev) 3758 { 3759 #define HCLGE_RESET_WATI_MS 100 3760 #define HCLGE_RESET_WAIT_CNT 350 3761 3762 u32 val, reg, reg_bit; 3763 u32 cnt = 0; 3764 3765 switch (hdev->reset_type) { 3766 case HNAE3_IMP_RESET: 3767 reg = HCLGE_GLOBAL_RESET_REG; 3768 reg_bit = HCLGE_IMP_RESET_BIT; 3769 break; 3770 case HNAE3_GLOBAL_RESET: 3771 reg = HCLGE_GLOBAL_RESET_REG; 3772 reg_bit = HCLGE_GLOBAL_RESET_BIT; 3773 break; 3774 case HNAE3_FUNC_RESET: 3775 reg = HCLGE_FUN_RST_ING; 3776 reg_bit = HCLGE_FUN_RST_ING_B; 3777 break; 3778 default: 3779 dev_err(&hdev->pdev->dev, 3780 "Wait for unsupported reset type: %d\n", 3781 hdev->reset_type); 3782 return -EINVAL; 3783 } 3784 3785 val = hclge_read_dev(&hdev->hw, reg); 3786 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 3787 msleep(HCLGE_RESET_WATI_MS); 3788 val = hclge_read_dev(&hdev->hw, reg); 3789 cnt++; 3790 } 3791 3792 if (cnt >= HCLGE_RESET_WAIT_CNT) { 3793 dev_warn(&hdev->pdev->dev, 3794 "Wait for reset timeout: %d\n", hdev->reset_type); 3795 return -EBUSY; 3796 } 3797 3798 return 0; 3799 } 3800 3801 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset) 3802 { 3803 struct hclge_vf_rst_cmd *req; 3804 struct hclge_desc desc; 3805 3806 req = (struct hclge_vf_rst_cmd *)desc.data; 3807 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false); 3808 req->dest_vfid = func_id; 3809 3810 if (reset) 3811 req->vf_rst = 0x1; 3812 3813 return hclge_cmd_send(&hdev->hw, &desc, 1); 3814 } 3815 3816 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset) 3817 { 3818 int i; 3819 3820 for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) { 3821 struct hclge_vport *vport = &hdev->vport[i]; 3822 int ret; 3823 3824 /* Send cmd to set/clear VF's FUNC_RST_ING */ 3825 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset); 3826 if (ret) { 3827 dev_err(&hdev->pdev->dev, 3828 "set vf(%u) rst failed %d!\n", 3829 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3830 ret); 3831 return ret; 3832 } 3833 3834 if (!reset || 3835 !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state)) 3836 continue; 3837 3838 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) && 3839 hdev->reset_type == HNAE3_FUNC_RESET) { 3840 set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET, 3841 &vport->need_notify); 3842 continue; 3843 } 3844 3845 /* Inform VF to process the reset. 3846 * hclge_inform_reset_assert_to_vf may fail if VF 3847 * driver is not loaded. 3848 */ 3849 ret = hclge_inform_reset_assert_to_vf(vport); 3850 if (ret) 3851 dev_warn(&hdev->pdev->dev, 3852 "inform reset to vf(%u) failed %d!\n", 3853 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3854 ret); 3855 } 3856 3857 return 0; 3858 } 3859 3860 static void hclge_mailbox_service_task(struct hclge_dev *hdev) 3861 { 3862 if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) || 3863 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) || 3864 test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 3865 return; 3866 3867 if (time_is_before_jiffies(hdev->last_mbx_scheduled + 3868 HCLGE_MBX_SCHED_TIMEOUT)) 3869 dev_warn(&hdev->pdev->dev, 3870 "mbx service task is scheduled after %ums on cpu%u!\n", 3871 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled), 3872 smp_processor_id()); 3873 3874 hclge_mbx_handler(hdev); 3875 3876 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 3877 } 3878 3879 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev) 3880 { 3881 struct hclge_pf_rst_sync_cmd *req; 3882 struct hclge_desc desc; 3883 int cnt = 0; 3884 int ret; 3885 3886 req = (struct hclge_pf_rst_sync_cmd *)desc.data; 3887 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true); 3888 3889 do { 3890 /* vf need to down netdev by mbx during PF or FLR reset */ 3891 hclge_mailbox_service_task(hdev); 3892 3893 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3894 /* for compatible with old firmware, wait 3895 * 100 ms for VF to stop IO 3896 */ 3897 if (ret == -EOPNOTSUPP) { 3898 msleep(HCLGE_RESET_SYNC_TIME); 3899 return; 3900 } else if (ret) { 3901 dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n", 3902 ret); 3903 return; 3904 } else if (req->all_vf_ready) { 3905 return; 3906 } 3907 msleep(HCLGE_PF_RESET_SYNC_TIME); 3908 hclge_comm_cmd_reuse_desc(&desc, true); 3909 } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT); 3910 3911 dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n"); 3912 } 3913 3914 void hclge_report_hw_error(struct hclge_dev *hdev, 3915 enum hnae3_hw_error_type type) 3916 { 3917 struct hnae3_client *client = hdev->nic_client; 3918 3919 if (!client || !client->ops->process_hw_error || 3920 !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) 3921 return; 3922 3923 client->ops->process_hw_error(&hdev->vport[0].nic, type); 3924 } 3925 3926 static void hclge_handle_imp_error(struct hclge_dev *hdev) 3927 { 3928 u32 reg_val; 3929 3930 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 3931 if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { 3932 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); 3933 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); 3934 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 3935 } 3936 3937 if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { 3938 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); 3939 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); 3940 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 3941 } 3942 } 3943 3944 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 3945 { 3946 struct hclge_desc desc; 3947 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 3948 int ret; 3949 3950 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 3951 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 3952 req->fun_reset_vfid = func_id; 3953 3954 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3955 if (ret) 3956 dev_err(&hdev->pdev->dev, 3957 "send function reset cmd fail, status =%d\n", ret); 3958 3959 return ret; 3960 } 3961 3962 static void hclge_do_reset(struct hclge_dev *hdev) 3963 { 3964 struct hnae3_handle *handle = &hdev->vport[0].nic; 3965 struct pci_dev *pdev = hdev->pdev; 3966 u32 val; 3967 3968 if (hclge_get_hw_reset_stat(handle)) { 3969 dev_info(&pdev->dev, "hardware reset not finish\n"); 3970 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n", 3971 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING), 3972 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 3973 return; 3974 } 3975 3976 switch (hdev->reset_type) { 3977 case HNAE3_IMP_RESET: 3978 dev_info(&pdev->dev, "IMP reset requested\n"); 3979 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 3980 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1); 3981 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val); 3982 break; 3983 case HNAE3_GLOBAL_RESET: 3984 dev_info(&pdev->dev, "global reset requested\n"); 3985 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 3986 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 3987 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 3988 break; 3989 case HNAE3_FUNC_RESET: 3990 dev_info(&pdev->dev, "PF reset requested\n"); 3991 /* schedule again to check later */ 3992 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); 3993 hclge_reset_task_schedule(hdev); 3994 break; 3995 default: 3996 dev_warn(&pdev->dev, 3997 "unsupported reset type: %d\n", hdev->reset_type); 3998 break; 3999 } 4000 } 4001 4002 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 4003 unsigned long *addr) 4004 { 4005 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 4006 struct hclge_dev *hdev = ae_dev->priv; 4007 4008 /* return the highest priority reset level amongst all */ 4009 if (test_bit(HNAE3_IMP_RESET, addr)) { 4010 rst_level = HNAE3_IMP_RESET; 4011 clear_bit(HNAE3_IMP_RESET, addr); 4012 clear_bit(HNAE3_GLOBAL_RESET, addr); 4013 clear_bit(HNAE3_FUNC_RESET, addr); 4014 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) { 4015 rst_level = HNAE3_GLOBAL_RESET; 4016 clear_bit(HNAE3_GLOBAL_RESET, addr); 4017 clear_bit(HNAE3_FUNC_RESET, addr); 4018 } else if (test_bit(HNAE3_FUNC_RESET, addr)) { 4019 rst_level = HNAE3_FUNC_RESET; 4020 clear_bit(HNAE3_FUNC_RESET, addr); 4021 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 4022 rst_level = HNAE3_FLR_RESET; 4023 clear_bit(HNAE3_FLR_RESET, addr); 4024 } 4025 4026 if (hdev->reset_type != HNAE3_NONE_RESET && 4027 rst_level < hdev->reset_type) 4028 return HNAE3_NONE_RESET; 4029 4030 return rst_level; 4031 } 4032 4033 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 4034 { 4035 u32 clearval = 0; 4036 4037 switch (hdev->reset_type) { 4038 case HNAE3_IMP_RESET: 4039 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 4040 break; 4041 case HNAE3_GLOBAL_RESET: 4042 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 4043 break; 4044 default: 4045 break; 4046 } 4047 4048 if (!clearval) 4049 return; 4050 4051 /* For revision 0x20, the reset interrupt source 4052 * can only be cleared after hardware reset done 4053 */ 4054 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 4055 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, 4056 clearval); 4057 4058 hclge_enable_vector(&hdev->misc_vector, true); 4059 } 4060 4061 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable) 4062 { 4063 u32 reg_val; 4064 4065 reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 4066 if (enable) 4067 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY; 4068 else 4069 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY; 4070 4071 hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val); 4072 } 4073 4074 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev) 4075 { 4076 int ret; 4077 4078 ret = hclge_set_all_vf_rst(hdev, true); 4079 if (ret) 4080 return ret; 4081 4082 hclge_func_reset_sync_vf(hdev); 4083 4084 return 0; 4085 } 4086 4087 static int hclge_reset_prepare_wait(struct hclge_dev *hdev) 4088 { 4089 u32 reg_val; 4090 int ret = 0; 4091 4092 switch (hdev->reset_type) { 4093 case HNAE3_FUNC_RESET: 4094 ret = hclge_func_reset_notify_vf(hdev); 4095 if (ret) 4096 return ret; 4097 4098 ret = hclge_func_reset_cmd(hdev, 0); 4099 if (ret) { 4100 dev_err(&hdev->pdev->dev, 4101 "asserting function reset fail %d!\n", ret); 4102 return ret; 4103 } 4104 4105 /* After performaning pf reset, it is not necessary to do the 4106 * mailbox handling or send any command to firmware, because 4107 * any mailbox handling or command to firmware is only valid 4108 * after hclge_comm_cmd_init is called. 4109 */ 4110 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 4111 hdev->rst_stats.pf_rst_cnt++; 4112 break; 4113 case HNAE3_FLR_RESET: 4114 ret = hclge_func_reset_notify_vf(hdev); 4115 if (ret) 4116 return ret; 4117 break; 4118 case HNAE3_IMP_RESET: 4119 hclge_handle_imp_error(hdev); 4120 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4121 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, 4122 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); 4123 break; 4124 default: 4125 break; 4126 } 4127 4128 /* inform hardware that preparatory work is done */ 4129 msleep(HCLGE_RESET_SYNC_TIME); 4130 hclge_reset_handshake(hdev, true); 4131 dev_info(&hdev->pdev->dev, "prepare wait ok\n"); 4132 4133 return ret; 4134 } 4135 4136 static void hclge_show_rst_info(struct hclge_dev *hdev) 4137 { 4138 char *buf; 4139 4140 buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL); 4141 if (!buf) 4142 return; 4143 4144 hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN); 4145 4146 dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf); 4147 4148 kfree(buf); 4149 } 4150 4151 static bool hclge_reset_err_handle(struct hclge_dev *hdev) 4152 { 4153 #define MAX_RESET_FAIL_CNT 5 4154 4155 if (hdev->reset_pending) { 4156 dev_info(&hdev->pdev->dev, "Reset pending %lu\n", 4157 hdev->reset_pending); 4158 return true; 4159 } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) & 4160 HCLGE_RESET_INT_M) { 4161 dev_info(&hdev->pdev->dev, 4162 "reset failed because new reset interrupt\n"); 4163 hclge_clear_reset_cause(hdev); 4164 return false; 4165 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { 4166 hdev->rst_stats.reset_fail_cnt++; 4167 set_bit(hdev->reset_type, &hdev->reset_pending); 4168 dev_info(&hdev->pdev->dev, 4169 "re-schedule reset task(%u)\n", 4170 hdev->rst_stats.reset_fail_cnt); 4171 return true; 4172 } 4173 4174 hclge_clear_reset_cause(hdev); 4175 4176 /* recover the handshake status when reset fail */ 4177 hclge_reset_handshake(hdev, true); 4178 4179 dev_err(&hdev->pdev->dev, "Reset fail!\n"); 4180 4181 hclge_show_rst_info(hdev); 4182 4183 set_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4184 4185 return false; 4186 } 4187 4188 static void hclge_update_reset_level(struct hclge_dev *hdev) 4189 { 4190 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4191 enum hnae3_reset_type reset_level; 4192 4193 /* reset request will not be set during reset, so clear 4194 * pending reset request to avoid unnecessary reset 4195 * caused by the same reason. 4196 */ 4197 hclge_get_reset_level(ae_dev, &hdev->reset_request); 4198 4199 /* if default_reset_request has a higher level reset request, 4200 * it should be handled as soon as possible. since some errors 4201 * need this kind of reset to fix. 4202 */ 4203 reset_level = hclge_get_reset_level(ae_dev, 4204 &hdev->default_reset_request); 4205 if (reset_level != HNAE3_NONE_RESET) 4206 set_bit(reset_level, &hdev->reset_request); 4207 } 4208 4209 static int hclge_set_rst_done(struct hclge_dev *hdev) 4210 { 4211 struct hclge_pf_rst_done_cmd *req; 4212 struct hclge_desc desc; 4213 int ret; 4214 4215 req = (struct hclge_pf_rst_done_cmd *)desc.data; 4216 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false); 4217 req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT; 4218 4219 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4220 /* To be compatible with the old firmware, which does not support 4221 * command HCLGE_OPC_PF_RST_DONE, just print a warning and 4222 * return success 4223 */ 4224 if (ret == -EOPNOTSUPP) { 4225 dev_warn(&hdev->pdev->dev, 4226 "current firmware does not support command(0x%x)!\n", 4227 HCLGE_OPC_PF_RST_DONE); 4228 return 0; 4229 } else if (ret) { 4230 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n", 4231 ret); 4232 } 4233 4234 return ret; 4235 } 4236 4237 static int hclge_reset_prepare_up(struct hclge_dev *hdev) 4238 { 4239 int ret = 0; 4240 4241 switch (hdev->reset_type) { 4242 case HNAE3_FUNC_RESET: 4243 case HNAE3_FLR_RESET: 4244 ret = hclge_set_all_vf_rst(hdev, false); 4245 break; 4246 case HNAE3_GLOBAL_RESET: 4247 case HNAE3_IMP_RESET: 4248 ret = hclge_set_rst_done(hdev); 4249 break; 4250 default: 4251 break; 4252 } 4253 4254 /* clear up the handshake status after re-initialize done */ 4255 hclge_reset_handshake(hdev, false); 4256 4257 return ret; 4258 } 4259 4260 static int hclge_reset_stack(struct hclge_dev *hdev) 4261 { 4262 int ret; 4263 4264 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 4265 if (ret) 4266 return ret; 4267 4268 ret = hclge_reset_ae_dev(hdev->ae_dev); 4269 if (ret) 4270 return ret; 4271 4272 return hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 4273 } 4274 4275 static int hclge_reset_prepare(struct hclge_dev *hdev) 4276 { 4277 int ret; 4278 4279 hdev->rst_stats.reset_cnt++; 4280 /* perform reset of the stack & ae device for a client */ 4281 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 4282 if (ret) 4283 return ret; 4284 4285 rtnl_lock(); 4286 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 4287 rtnl_unlock(); 4288 if (ret) 4289 return ret; 4290 4291 return hclge_reset_prepare_wait(hdev); 4292 } 4293 4294 static int hclge_reset_rebuild(struct hclge_dev *hdev) 4295 { 4296 int ret; 4297 4298 hdev->rst_stats.hw_reset_done_cnt++; 4299 4300 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 4301 if (ret) 4302 return ret; 4303 4304 rtnl_lock(); 4305 ret = hclge_reset_stack(hdev); 4306 rtnl_unlock(); 4307 if (ret) 4308 return ret; 4309 4310 hclge_clear_reset_cause(hdev); 4311 4312 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 4313 /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1 4314 * times 4315 */ 4316 if (ret && 4317 hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1) 4318 return ret; 4319 4320 ret = hclge_reset_prepare_up(hdev); 4321 if (ret) 4322 return ret; 4323 4324 rtnl_lock(); 4325 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT); 4326 rtnl_unlock(); 4327 if (ret) 4328 return ret; 4329 4330 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT); 4331 if (ret) 4332 return ret; 4333 4334 hdev->last_reset_time = jiffies; 4335 hdev->rst_stats.reset_fail_cnt = 0; 4336 hdev->rst_stats.reset_done_cnt++; 4337 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4338 4339 hclge_update_reset_level(hdev); 4340 4341 return 0; 4342 } 4343 4344 static void hclge_reset(struct hclge_dev *hdev) 4345 { 4346 if (hclge_reset_prepare(hdev)) 4347 goto err_reset; 4348 4349 if (hclge_reset_wait(hdev)) 4350 goto err_reset; 4351 4352 if (hclge_reset_rebuild(hdev)) 4353 goto err_reset; 4354 4355 return; 4356 4357 err_reset: 4358 if (hclge_reset_err_handle(hdev)) 4359 hclge_reset_task_schedule(hdev); 4360 } 4361 4362 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) 4363 { 4364 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4365 struct hclge_dev *hdev = ae_dev->priv; 4366 4367 /* We might end up getting called broadly because of 2 below cases: 4368 * 1. Recoverable error was conveyed through APEI and only way to bring 4369 * normalcy is to reset. 4370 * 2. A new reset request from the stack due to timeout 4371 * 4372 * check if this is a new reset request and we are not here just because 4373 * last reset attempt did not succeed and watchdog hit us again. We will 4374 * know this if last reset request did not occur very recently (watchdog 4375 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 4376 * In case of new request we reset the "reset level" to PF reset. 4377 * And if it is a repeat reset request of the most recent one then we 4378 * want to make sure we throttle the reset request. Therefore, we will 4379 * not allow it again before 3*HZ times. 4380 */ 4381 4382 if (time_before(jiffies, (hdev->last_reset_time + 4383 HCLGE_RESET_INTERVAL))) { 4384 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 4385 return; 4386 } 4387 4388 if (hdev->default_reset_request) { 4389 hdev->reset_level = 4390 hclge_get_reset_level(ae_dev, 4391 &hdev->default_reset_request); 4392 } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) { 4393 hdev->reset_level = HNAE3_FUNC_RESET; 4394 } 4395 4396 dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n", 4397 hdev->reset_level); 4398 4399 /* request reset & schedule reset task */ 4400 set_bit(hdev->reset_level, &hdev->reset_request); 4401 hclge_reset_task_schedule(hdev); 4402 4403 if (hdev->reset_level < HNAE3_GLOBAL_RESET) 4404 hdev->reset_level++; 4405 } 4406 4407 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 4408 enum hnae3_reset_type rst_type) 4409 { 4410 struct hclge_dev *hdev = ae_dev->priv; 4411 4412 set_bit(rst_type, &hdev->default_reset_request); 4413 } 4414 4415 static void hclge_reset_timer(struct timer_list *t) 4416 { 4417 struct hclge_dev *hdev = from_timer(hdev, t, reset_timer); 4418 4419 /* if default_reset_request has no value, it means that this reset 4420 * request has already be handled, so just return here 4421 */ 4422 if (!hdev->default_reset_request) 4423 return; 4424 4425 dev_info(&hdev->pdev->dev, 4426 "triggering reset in reset timer\n"); 4427 hclge_reset_event(hdev->pdev, NULL); 4428 } 4429 4430 static void hclge_reset_subtask(struct hclge_dev *hdev) 4431 { 4432 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4433 4434 /* check if there is any ongoing reset in the hardware. This status can 4435 * be checked from reset_pending. If there is then, we need to wait for 4436 * hardware to complete reset. 4437 * a. If we are able to figure out in reasonable time that hardware 4438 * has fully resetted then, we can proceed with driver, client 4439 * reset. 4440 * b. else, we can come back later to check this status so re-sched 4441 * now. 4442 */ 4443 hdev->last_reset_time = jiffies; 4444 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending); 4445 if (hdev->reset_type != HNAE3_NONE_RESET) 4446 hclge_reset(hdev); 4447 4448 /* check if we got any *new* reset requests to be honored */ 4449 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request); 4450 if (hdev->reset_type != HNAE3_NONE_RESET) 4451 hclge_do_reset(hdev); 4452 4453 hdev->reset_type = HNAE3_NONE_RESET; 4454 } 4455 4456 static void hclge_handle_err_reset_request(struct hclge_dev *hdev) 4457 { 4458 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4459 enum hnae3_reset_type reset_type; 4460 4461 if (ae_dev->hw_err_reset_req) { 4462 reset_type = hclge_get_reset_level(ae_dev, 4463 &ae_dev->hw_err_reset_req); 4464 hclge_set_def_reset_request(ae_dev, reset_type); 4465 } 4466 4467 if (hdev->default_reset_request && ae_dev->ops->reset_event) 4468 ae_dev->ops->reset_event(hdev->pdev, NULL); 4469 4470 /* enable interrupt after error handling complete */ 4471 hclge_enable_vector(&hdev->misc_vector, true); 4472 } 4473 4474 static void hclge_handle_err_recovery(struct hclge_dev *hdev) 4475 { 4476 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4477 4478 ae_dev->hw_err_reset_req = 0; 4479 4480 if (hclge_find_error_source(hdev)) { 4481 hclge_handle_error_info_log(ae_dev); 4482 hclge_handle_mac_tnl(hdev); 4483 } 4484 4485 hclge_handle_err_reset_request(hdev); 4486 } 4487 4488 static void hclge_misc_err_recovery(struct hclge_dev *hdev) 4489 { 4490 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4491 struct device *dev = &hdev->pdev->dev; 4492 u32 msix_sts_reg; 4493 4494 msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 4495 if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) { 4496 if (hclge_handle_hw_msix_error 4497 (hdev, &hdev->default_reset_request)) 4498 dev_info(dev, "received msix interrupt 0x%x\n", 4499 msix_sts_reg); 4500 } 4501 4502 hclge_handle_hw_ras_error(ae_dev); 4503 4504 hclge_handle_err_reset_request(hdev); 4505 } 4506 4507 static void hclge_errhand_service_task(struct hclge_dev *hdev) 4508 { 4509 if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 4510 return; 4511 4512 if (hnae3_dev_ras_imp_supported(hdev)) 4513 hclge_handle_err_recovery(hdev); 4514 else 4515 hclge_misc_err_recovery(hdev); 4516 } 4517 4518 static void hclge_reset_service_task(struct hclge_dev *hdev) 4519 { 4520 if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 4521 return; 4522 4523 if (time_is_before_jiffies(hdev->last_rst_scheduled + 4524 HCLGE_RESET_SCHED_TIMEOUT)) 4525 dev_warn(&hdev->pdev->dev, 4526 "reset service task is scheduled after %ums on cpu%u!\n", 4527 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled), 4528 smp_processor_id()); 4529 4530 down(&hdev->reset_sem); 4531 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4532 4533 hclge_reset_subtask(hdev); 4534 4535 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4536 up(&hdev->reset_sem); 4537 } 4538 4539 static void hclge_update_vport_alive(struct hclge_dev *hdev) 4540 { 4541 #define HCLGE_ALIVE_SECONDS_NORMAL 8 4542 4543 unsigned long alive_time = HCLGE_ALIVE_SECONDS_NORMAL * HZ; 4544 int i; 4545 4546 /* start from vport 1 for PF is always alive */ 4547 for (i = 1; i < hdev->num_alloc_vport; i++) { 4548 struct hclge_vport *vport = &hdev->vport[i]; 4549 4550 if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) || 4551 !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 4552 continue; 4553 if (time_after(jiffies, vport->last_active_jiffies + 4554 alive_time)) { 4555 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 4556 dev_warn(&hdev->pdev->dev, 4557 "VF %u heartbeat timeout\n", 4558 i - HCLGE_VF_VPORT_START_NUM); 4559 } 4560 } 4561 } 4562 4563 static void hclge_periodic_service_task(struct hclge_dev *hdev) 4564 { 4565 unsigned long delta = round_jiffies_relative(HZ); 4566 4567 if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 4568 return; 4569 4570 /* Always handle the link updating to make sure link state is 4571 * updated when it is triggered by mbx. 4572 */ 4573 hclge_update_link_status(hdev); 4574 hclge_sync_mac_table(hdev); 4575 hclge_sync_promisc_mode(hdev); 4576 hclge_sync_fd_table(hdev); 4577 4578 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 4579 delta = jiffies - hdev->last_serv_processed; 4580 4581 if (delta < round_jiffies_relative(HZ)) { 4582 delta = round_jiffies_relative(HZ) - delta; 4583 goto out; 4584 } 4585 } 4586 4587 hdev->serv_processed_cnt++; 4588 hclge_update_vport_alive(hdev); 4589 4590 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) { 4591 hdev->last_serv_processed = jiffies; 4592 goto out; 4593 } 4594 4595 if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL)) 4596 hclge_update_stats_for_all(hdev); 4597 4598 hclge_update_port_info(hdev); 4599 hclge_sync_vlan_filter(hdev); 4600 4601 if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL)) 4602 hclge_rfs_filter_expire(hdev); 4603 4604 hdev->last_serv_processed = jiffies; 4605 4606 out: 4607 hclge_task_schedule(hdev, delta); 4608 } 4609 4610 static void hclge_ptp_service_task(struct hclge_dev *hdev) 4611 { 4612 unsigned long flags; 4613 4614 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) || 4615 !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) || 4616 !time_is_before_jiffies(hdev->ptp->tx_start + HZ)) 4617 return; 4618 4619 /* to prevent concurrence with the irq handler */ 4620 spin_lock_irqsave(&hdev->ptp->lock, flags); 4621 4622 /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq 4623 * handler may handle it just before spin_lock_irqsave(). 4624 */ 4625 if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) 4626 hclge_ptp_clean_tx_hwts(hdev); 4627 4628 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 4629 } 4630 4631 static void hclge_service_task(struct work_struct *work) 4632 { 4633 struct hclge_dev *hdev = 4634 container_of(work, struct hclge_dev, service_task.work); 4635 4636 hclge_errhand_service_task(hdev); 4637 hclge_reset_service_task(hdev); 4638 hclge_ptp_service_task(hdev); 4639 hclge_mailbox_service_task(hdev); 4640 hclge_periodic_service_task(hdev); 4641 4642 /* Handle error recovery, reset and mbx again in case periodical task 4643 * delays the handling by calling hclge_task_schedule() in 4644 * hclge_periodic_service_task(). 4645 */ 4646 hclge_errhand_service_task(hdev); 4647 hclge_reset_service_task(hdev); 4648 hclge_mailbox_service_task(hdev); 4649 } 4650 4651 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 4652 { 4653 /* VF handle has no client */ 4654 if (!handle->client) 4655 return container_of(handle, struct hclge_vport, nic); 4656 else if (handle->client->type == HNAE3_CLIENT_ROCE) 4657 return container_of(handle, struct hclge_vport, roce); 4658 else 4659 return container_of(handle, struct hclge_vport, nic); 4660 } 4661 4662 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx, 4663 struct hnae3_vector_info *vector_info) 4664 { 4665 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 64 4666 4667 vector_info->vector = pci_irq_vector(hdev->pdev, idx); 4668 4669 /* need an extend offset to config vector >= 64 */ 4670 if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2) 4671 vector_info->io_addr = hdev->hw.hw.io_base + 4672 HCLGE_VECTOR_REG_BASE + 4673 (idx - 1) * HCLGE_VECTOR_REG_OFFSET; 4674 else 4675 vector_info->io_addr = hdev->hw.hw.io_base + 4676 HCLGE_VECTOR_EXT_REG_BASE + 4677 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4678 HCLGE_VECTOR_REG_OFFSET_H + 4679 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4680 HCLGE_VECTOR_REG_OFFSET; 4681 4682 hdev->vector_status[idx] = hdev->vport[0].vport_id; 4683 hdev->vector_irq[idx] = vector_info->vector; 4684 } 4685 4686 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 4687 struct hnae3_vector_info *vector_info) 4688 { 4689 struct hclge_vport *vport = hclge_get_vport(handle); 4690 struct hnae3_vector_info *vector = vector_info; 4691 struct hclge_dev *hdev = vport->back; 4692 int alloc = 0; 4693 u16 i = 0; 4694 u16 j; 4695 4696 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num); 4697 vector_num = min(hdev->num_msi_left, vector_num); 4698 4699 for (j = 0; j < vector_num; j++) { 4700 while (++i < hdev->num_nic_msi) { 4701 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 4702 hclge_get_vector_info(hdev, i, vector); 4703 vector++; 4704 alloc++; 4705 4706 break; 4707 } 4708 } 4709 } 4710 hdev->num_msi_left -= alloc; 4711 hdev->num_msi_used += alloc; 4712 4713 return alloc; 4714 } 4715 4716 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 4717 { 4718 int i; 4719 4720 for (i = 0; i < hdev->num_msi; i++) 4721 if (vector == hdev->vector_irq[i]) 4722 return i; 4723 4724 return -EINVAL; 4725 } 4726 4727 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 4728 { 4729 struct hclge_vport *vport = hclge_get_vport(handle); 4730 struct hclge_dev *hdev = vport->back; 4731 int vector_id; 4732 4733 vector_id = hclge_get_vector_index(hdev, vector); 4734 if (vector_id < 0) { 4735 dev_err(&hdev->pdev->dev, 4736 "Get vector index fail. vector = %d\n", vector); 4737 return vector_id; 4738 } 4739 4740 hclge_free_vector(hdev, vector_id); 4741 4742 return 0; 4743 } 4744 4745 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 4746 u8 *key, u8 *hfunc) 4747 { 4748 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4749 struct hclge_vport *vport = hclge_get_vport(handle); 4750 struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg; 4751 4752 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 4753 4754 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 4755 ae_dev->dev_specs.rss_ind_tbl_size); 4756 4757 return 0; 4758 } 4759 4760 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 4761 const u8 *key, const u8 hfunc) 4762 { 4763 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4764 struct hclge_vport *vport = hclge_get_vport(handle); 4765 struct hclge_dev *hdev = vport->back; 4766 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 4767 int ret, i; 4768 4769 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc); 4770 if (ret) { 4771 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc); 4772 return ret; 4773 } 4774 4775 /* Update the shadow RSS table with user specified qids */ 4776 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 4777 rss_cfg->rss_indirection_tbl[i] = indir[i]; 4778 4779 /* Update the hardware */ 4780 return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw, 4781 rss_cfg->rss_indirection_tbl); 4782 } 4783 4784 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 4785 struct ethtool_rxnfc *nfc) 4786 { 4787 struct hclge_vport *vport = hclge_get_vport(handle); 4788 struct hclge_dev *hdev = vport->back; 4789 int ret; 4790 4791 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 4792 &hdev->rss_cfg, nfc); 4793 if (ret) { 4794 dev_err(&hdev->pdev->dev, 4795 "failed to set rss tuple, ret = %d.\n", ret); 4796 return ret; 4797 } 4798 4799 return 0; 4800 } 4801 4802 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 4803 struct ethtool_rxnfc *nfc) 4804 { 4805 struct hclge_vport *vport = hclge_get_vport(handle); 4806 u8 tuple_sets; 4807 int ret; 4808 4809 nfc->data = 0; 4810 4811 ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type, 4812 &tuple_sets); 4813 if (ret || !tuple_sets) 4814 return ret; 4815 4816 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 4817 4818 return 0; 4819 } 4820 4821 static int hclge_get_tc_size(struct hnae3_handle *handle) 4822 { 4823 struct hclge_vport *vport = hclge_get_vport(handle); 4824 struct hclge_dev *hdev = vport->back; 4825 4826 return hdev->pf_rss_size_max; 4827 } 4828 4829 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev) 4830 { 4831 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 4832 struct hclge_vport *vport = hdev->vport; 4833 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 4834 u16 tc_valid[HCLGE_MAX_TC_NUM] = {0}; 4835 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 4836 struct hnae3_tc_info *tc_info; 4837 u16 roundup_size; 4838 u16 rss_size; 4839 int i; 4840 4841 tc_info = &vport->nic.kinfo.tc_info; 4842 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 4843 rss_size = tc_info->tqp_count[i]; 4844 tc_valid[i] = 0; 4845 4846 if (!(hdev->hw_tc_map & BIT(i))) 4847 continue; 4848 4849 /* tc_size set to hardware is the log2 of roundup power of two 4850 * of rss_size, the acutal queue size is limited by indirection 4851 * table. 4852 */ 4853 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size || 4854 rss_size == 0) { 4855 dev_err(&hdev->pdev->dev, 4856 "Configure rss tc size failed, invalid TC_SIZE = %u\n", 4857 rss_size); 4858 return -EINVAL; 4859 } 4860 4861 roundup_size = roundup_pow_of_two(rss_size); 4862 roundup_size = ilog2(roundup_size); 4863 4864 tc_valid[i] = 1; 4865 tc_size[i] = roundup_size; 4866 tc_offset[i] = tc_info->tqp_offset[i]; 4867 } 4868 4869 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 4870 tc_size); 4871 } 4872 4873 int hclge_rss_init_hw(struct hclge_dev *hdev) 4874 { 4875 u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl; 4876 u8 *key = hdev->rss_cfg.rss_hash_key; 4877 u8 hfunc = hdev->rss_cfg.rss_algo; 4878 int ret; 4879 4880 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 4881 rss_indir); 4882 if (ret) 4883 return ret; 4884 4885 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key); 4886 if (ret) 4887 return ret; 4888 4889 ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, &hdev->rss_cfg); 4890 if (ret) 4891 return ret; 4892 4893 return hclge_init_rss_tc_mode(hdev); 4894 } 4895 4896 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 4897 int vector_id, bool en, 4898 struct hnae3_ring_chain_node *ring_chain) 4899 { 4900 struct hclge_dev *hdev = vport->back; 4901 struct hnae3_ring_chain_node *node; 4902 struct hclge_desc desc; 4903 struct hclge_ctrl_vector_chain_cmd *req = 4904 (struct hclge_ctrl_vector_chain_cmd *)desc.data; 4905 enum hclge_comm_cmd_status status; 4906 enum hclge_opcode_type op; 4907 u16 tqp_type_and_id; 4908 int i; 4909 4910 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 4911 hclge_cmd_setup_basic_desc(&desc, op, false); 4912 req->int_vector_id_l = hnae3_get_field(vector_id, 4913 HCLGE_VECTOR_ID_L_M, 4914 HCLGE_VECTOR_ID_L_S); 4915 req->int_vector_id_h = hnae3_get_field(vector_id, 4916 HCLGE_VECTOR_ID_H_M, 4917 HCLGE_VECTOR_ID_H_S); 4918 4919 i = 0; 4920 for (node = ring_chain; node; node = node->next) { 4921 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 4922 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 4923 HCLGE_INT_TYPE_S, 4924 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 4925 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 4926 HCLGE_TQP_ID_S, node->tqp_index); 4927 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 4928 HCLGE_INT_GL_IDX_S, 4929 hnae3_get_field(node->int_gl_idx, 4930 HNAE3_RING_GL_IDX_M, 4931 HNAE3_RING_GL_IDX_S)); 4932 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 4933 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 4934 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 4935 req->vfid = vport->vport_id; 4936 4937 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4938 if (status) { 4939 dev_err(&hdev->pdev->dev, 4940 "Map TQP fail, status is %d.\n", 4941 status); 4942 return -EIO; 4943 } 4944 i = 0; 4945 4946 hclge_cmd_setup_basic_desc(&desc, 4947 op, 4948 false); 4949 req->int_vector_id_l = 4950 hnae3_get_field(vector_id, 4951 HCLGE_VECTOR_ID_L_M, 4952 HCLGE_VECTOR_ID_L_S); 4953 req->int_vector_id_h = 4954 hnae3_get_field(vector_id, 4955 HCLGE_VECTOR_ID_H_M, 4956 HCLGE_VECTOR_ID_H_S); 4957 } 4958 } 4959 4960 if (i > 0) { 4961 req->int_cause_num = i; 4962 req->vfid = vport->vport_id; 4963 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4964 if (status) { 4965 dev_err(&hdev->pdev->dev, 4966 "Map TQP fail, status is %d.\n", status); 4967 return -EIO; 4968 } 4969 } 4970 4971 return 0; 4972 } 4973 4974 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector, 4975 struct hnae3_ring_chain_node *ring_chain) 4976 { 4977 struct hclge_vport *vport = hclge_get_vport(handle); 4978 struct hclge_dev *hdev = vport->back; 4979 int vector_id; 4980 4981 vector_id = hclge_get_vector_index(hdev, vector); 4982 if (vector_id < 0) { 4983 dev_err(&hdev->pdev->dev, 4984 "failed to get vector index. vector=%d\n", vector); 4985 return vector_id; 4986 } 4987 4988 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 4989 } 4990 4991 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector, 4992 struct hnae3_ring_chain_node *ring_chain) 4993 { 4994 struct hclge_vport *vport = hclge_get_vport(handle); 4995 struct hclge_dev *hdev = vport->back; 4996 int vector_id, ret; 4997 4998 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 4999 return 0; 5000 5001 vector_id = hclge_get_vector_index(hdev, vector); 5002 if (vector_id < 0) { 5003 dev_err(&handle->pdev->dev, 5004 "Get vector index fail. ret =%d\n", vector_id); 5005 return vector_id; 5006 } 5007 5008 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 5009 if (ret) 5010 dev_err(&handle->pdev->dev, 5011 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 5012 vector_id, ret); 5013 5014 return ret; 5015 } 5016 5017 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id, 5018 bool en_uc, bool en_mc, bool en_bc) 5019 { 5020 struct hclge_vport *vport = &hdev->vport[vf_id]; 5021 struct hnae3_handle *handle = &vport->nic; 5022 struct hclge_promisc_cfg_cmd *req; 5023 struct hclge_desc desc; 5024 bool uc_tx_en = en_uc; 5025 u8 promisc_cfg = 0; 5026 int ret; 5027 5028 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 5029 5030 req = (struct hclge_promisc_cfg_cmd *)desc.data; 5031 req->vf_id = vf_id; 5032 5033 if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags)) 5034 uc_tx_en = false; 5035 5036 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0); 5037 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0); 5038 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0); 5039 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0); 5040 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0); 5041 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0); 5042 req->extend_promisc = promisc_cfg; 5043 5044 /* to be compatible with DEVICE_VERSION_V1/2 */ 5045 promisc_cfg = 0; 5046 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0); 5047 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0); 5048 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0); 5049 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1); 5050 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1); 5051 req->promisc = promisc_cfg; 5052 5053 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5054 if (ret) 5055 dev_err(&hdev->pdev->dev, 5056 "failed to set vport %u promisc mode, ret = %d.\n", 5057 vf_id, ret); 5058 5059 return ret; 5060 } 5061 5062 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 5063 bool en_mc_pmc, bool en_bc_pmc) 5064 { 5065 return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id, 5066 en_uc_pmc, en_mc_pmc, en_bc_pmc); 5067 } 5068 5069 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 5070 bool en_mc_pmc) 5071 { 5072 struct hclge_vport *vport = hclge_get_vport(handle); 5073 struct hclge_dev *hdev = vport->back; 5074 bool en_bc_pmc = true; 5075 5076 /* For device whose version below V2, if broadcast promisc enabled, 5077 * vlan filter is always bypassed. So broadcast promisc should be 5078 * disabled until user enable promisc mode 5079 */ 5080 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 5081 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false; 5082 5083 return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc, 5084 en_bc_pmc); 5085 } 5086 5087 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle) 5088 { 5089 struct hclge_vport *vport = hclge_get_vport(handle); 5090 5091 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5092 } 5093 5094 static void hclge_sync_fd_state(struct hclge_dev *hdev) 5095 { 5096 if (hlist_empty(&hdev->fd_rule_list)) 5097 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 5098 } 5099 5100 static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location) 5101 { 5102 if (!test_bit(location, hdev->fd_bmap)) { 5103 set_bit(location, hdev->fd_bmap); 5104 hdev->hclge_fd_rule_num++; 5105 } 5106 } 5107 5108 static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location) 5109 { 5110 if (test_bit(location, hdev->fd_bmap)) { 5111 clear_bit(location, hdev->fd_bmap); 5112 hdev->hclge_fd_rule_num--; 5113 } 5114 } 5115 5116 static void hclge_fd_free_node(struct hclge_dev *hdev, 5117 struct hclge_fd_rule *rule) 5118 { 5119 hlist_del(&rule->rule_node); 5120 kfree(rule); 5121 hclge_sync_fd_state(hdev); 5122 } 5123 5124 static void hclge_update_fd_rule_node(struct hclge_dev *hdev, 5125 struct hclge_fd_rule *old_rule, 5126 struct hclge_fd_rule *new_rule, 5127 enum HCLGE_FD_NODE_STATE state) 5128 { 5129 switch (state) { 5130 case HCLGE_FD_TO_ADD: 5131 case HCLGE_FD_ACTIVE: 5132 /* 1) if the new state is TO_ADD, just replace the old rule 5133 * with the same location, no matter its state, because the 5134 * new rule will be configured to the hardware. 5135 * 2) if the new state is ACTIVE, it means the new rule 5136 * has been configured to the hardware, so just replace 5137 * the old rule node with the same location. 5138 * 3) for it doesn't add a new node to the list, so it's 5139 * unnecessary to update the rule number and fd_bmap. 5140 */ 5141 new_rule->rule_node.next = old_rule->rule_node.next; 5142 new_rule->rule_node.pprev = old_rule->rule_node.pprev; 5143 memcpy(old_rule, new_rule, sizeof(*old_rule)); 5144 kfree(new_rule); 5145 break; 5146 case HCLGE_FD_DELETED: 5147 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5148 hclge_fd_free_node(hdev, old_rule); 5149 break; 5150 case HCLGE_FD_TO_DEL: 5151 /* if new request is TO_DEL, and old rule is existent 5152 * 1) the state of old rule is TO_DEL, we need do nothing, 5153 * because we delete rule by location, other rule content 5154 * is unncessary. 5155 * 2) the state of old rule is ACTIVE, we need to change its 5156 * state to TO_DEL, so the rule will be deleted when periodic 5157 * task being scheduled. 5158 * 3) the state of old rule is TO_ADD, it means the rule hasn't 5159 * been added to hardware, so we just delete the rule node from 5160 * fd_rule_list directly. 5161 */ 5162 if (old_rule->state == HCLGE_FD_TO_ADD) { 5163 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5164 hclge_fd_free_node(hdev, old_rule); 5165 return; 5166 } 5167 old_rule->state = HCLGE_FD_TO_DEL; 5168 break; 5169 } 5170 } 5171 5172 static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist, 5173 u16 location, 5174 struct hclge_fd_rule **parent) 5175 { 5176 struct hclge_fd_rule *rule; 5177 struct hlist_node *node; 5178 5179 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 5180 if (rule->location == location) 5181 return rule; 5182 else if (rule->location > location) 5183 return NULL; 5184 /* record the parent node, use to keep the nodes in fd_rule_list 5185 * in ascend order. 5186 */ 5187 *parent = rule; 5188 } 5189 5190 return NULL; 5191 } 5192 5193 /* insert fd rule node in ascend order according to rule->location */ 5194 static void hclge_fd_insert_rule_node(struct hlist_head *hlist, 5195 struct hclge_fd_rule *rule, 5196 struct hclge_fd_rule *parent) 5197 { 5198 INIT_HLIST_NODE(&rule->rule_node); 5199 5200 if (parent) 5201 hlist_add_behind(&rule->rule_node, &parent->rule_node); 5202 else 5203 hlist_add_head(&rule->rule_node, hlist); 5204 } 5205 5206 static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev, 5207 struct hclge_fd_user_def_cfg *cfg) 5208 { 5209 struct hclge_fd_user_def_cfg_cmd *req; 5210 struct hclge_desc desc; 5211 u16 data = 0; 5212 int ret; 5213 5214 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false); 5215 5216 req = (struct hclge_fd_user_def_cfg_cmd *)desc.data; 5217 5218 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0); 5219 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5220 HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset); 5221 req->ol2_cfg = cpu_to_le16(data); 5222 5223 data = 0; 5224 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0); 5225 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5226 HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset); 5227 req->ol3_cfg = cpu_to_le16(data); 5228 5229 data = 0; 5230 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0); 5231 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5232 HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset); 5233 req->ol4_cfg = cpu_to_le16(data); 5234 5235 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5236 if (ret) 5237 dev_err(&hdev->pdev->dev, 5238 "failed to set fd user def data, ret= %d\n", ret); 5239 return ret; 5240 } 5241 5242 static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked) 5243 { 5244 int ret; 5245 5246 if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state)) 5247 return; 5248 5249 if (!locked) 5250 spin_lock_bh(&hdev->fd_rule_lock); 5251 5252 ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg); 5253 if (ret) 5254 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5255 5256 if (!locked) 5257 spin_unlock_bh(&hdev->fd_rule_lock); 5258 } 5259 5260 static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev, 5261 struct hclge_fd_rule *rule) 5262 { 5263 struct hlist_head *hlist = &hdev->fd_rule_list; 5264 struct hclge_fd_rule *fd_rule, *parent = NULL; 5265 struct hclge_fd_user_def_info *info, *old_info; 5266 struct hclge_fd_user_def_cfg *cfg; 5267 5268 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5269 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5270 return 0; 5271 5272 /* for valid layer is start from 1, so need minus 1 to get the cfg */ 5273 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5274 info = &rule->ep.user_def; 5275 5276 if (!cfg->ref_cnt || cfg->offset == info->offset) 5277 return 0; 5278 5279 if (cfg->ref_cnt > 1) 5280 goto error; 5281 5282 fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent); 5283 if (fd_rule) { 5284 old_info = &fd_rule->ep.user_def; 5285 if (info->layer == old_info->layer) 5286 return 0; 5287 } 5288 5289 error: 5290 dev_err(&hdev->pdev->dev, 5291 "No available offset for layer%d fd rule, each layer only support one user def offset.\n", 5292 info->layer + 1); 5293 return -ENOSPC; 5294 } 5295 5296 static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev, 5297 struct hclge_fd_rule *rule) 5298 { 5299 struct hclge_fd_user_def_cfg *cfg; 5300 5301 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5302 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5303 return; 5304 5305 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5306 if (!cfg->ref_cnt) { 5307 cfg->offset = rule->ep.user_def.offset; 5308 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5309 } 5310 cfg->ref_cnt++; 5311 } 5312 5313 static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev, 5314 struct hclge_fd_rule *rule) 5315 { 5316 struct hclge_fd_user_def_cfg *cfg; 5317 5318 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5319 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5320 return; 5321 5322 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5323 if (!cfg->ref_cnt) 5324 return; 5325 5326 cfg->ref_cnt--; 5327 if (!cfg->ref_cnt) { 5328 cfg->offset = 0; 5329 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5330 } 5331 } 5332 5333 static void hclge_update_fd_list(struct hclge_dev *hdev, 5334 enum HCLGE_FD_NODE_STATE state, u16 location, 5335 struct hclge_fd_rule *new_rule) 5336 { 5337 struct hlist_head *hlist = &hdev->fd_rule_list; 5338 struct hclge_fd_rule *fd_rule, *parent = NULL; 5339 5340 fd_rule = hclge_find_fd_rule(hlist, location, &parent); 5341 if (fd_rule) { 5342 hclge_fd_dec_user_def_refcnt(hdev, fd_rule); 5343 if (state == HCLGE_FD_ACTIVE) 5344 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5345 hclge_sync_fd_user_def_cfg(hdev, true); 5346 5347 hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state); 5348 return; 5349 } 5350 5351 /* it's unlikely to fail here, because we have checked the rule 5352 * exist before. 5353 */ 5354 if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) { 5355 dev_warn(&hdev->pdev->dev, 5356 "failed to delete fd rule %u, it's inexistent\n", 5357 location); 5358 return; 5359 } 5360 5361 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5362 hclge_sync_fd_user_def_cfg(hdev, true); 5363 5364 hclge_fd_insert_rule_node(hlist, new_rule, parent); 5365 hclge_fd_inc_rule_cnt(hdev, new_rule->location); 5366 5367 if (state == HCLGE_FD_TO_ADD) { 5368 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 5369 hclge_task_schedule(hdev, 0); 5370 } 5371 } 5372 5373 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode) 5374 { 5375 struct hclge_get_fd_mode_cmd *req; 5376 struct hclge_desc desc; 5377 int ret; 5378 5379 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true); 5380 5381 req = (struct hclge_get_fd_mode_cmd *)desc.data; 5382 5383 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5384 if (ret) { 5385 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret); 5386 return ret; 5387 } 5388 5389 *fd_mode = req->mode; 5390 5391 return ret; 5392 } 5393 5394 static int hclge_get_fd_allocation(struct hclge_dev *hdev, 5395 u32 *stage1_entry_num, 5396 u32 *stage2_entry_num, 5397 u16 *stage1_counter_num, 5398 u16 *stage2_counter_num) 5399 { 5400 struct hclge_get_fd_allocation_cmd *req; 5401 struct hclge_desc desc; 5402 int ret; 5403 5404 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true); 5405 5406 req = (struct hclge_get_fd_allocation_cmd *)desc.data; 5407 5408 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5409 if (ret) { 5410 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n", 5411 ret); 5412 return ret; 5413 } 5414 5415 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num); 5416 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num); 5417 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num); 5418 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num); 5419 5420 return ret; 5421 } 5422 5423 static int hclge_set_fd_key_config(struct hclge_dev *hdev, 5424 enum HCLGE_FD_STAGE stage_num) 5425 { 5426 struct hclge_set_fd_key_config_cmd *req; 5427 struct hclge_fd_key_cfg *stage; 5428 struct hclge_desc desc; 5429 int ret; 5430 5431 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false); 5432 5433 req = (struct hclge_set_fd_key_config_cmd *)desc.data; 5434 stage = &hdev->fd_cfg.key_cfg[stage_num]; 5435 req->stage = stage_num; 5436 req->key_select = stage->key_sel; 5437 req->inner_sipv6_word_en = stage->inner_sipv6_word_en; 5438 req->inner_dipv6_word_en = stage->inner_dipv6_word_en; 5439 req->outer_sipv6_word_en = stage->outer_sipv6_word_en; 5440 req->outer_dipv6_word_en = stage->outer_dipv6_word_en; 5441 req->tuple_mask = cpu_to_le32(~stage->tuple_active); 5442 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active); 5443 5444 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5445 if (ret) 5446 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret); 5447 5448 return ret; 5449 } 5450 5451 static void hclge_fd_disable_user_def(struct hclge_dev *hdev) 5452 { 5453 struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg; 5454 5455 spin_lock_bh(&hdev->fd_rule_lock); 5456 memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg)); 5457 spin_unlock_bh(&hdev->fd_rule_lock); 5458 5459 hclge_fd_set_user_def_cmd(hdev, cfg); 5460 } 5461 5462 static int hclge_init_fd_config(struct hclge_dev *hdev) 5463 { 5464 #define LOW_2_WORDS 0x03 5465 struct hclge_fd_key_cfg *key_cfg; 5466 int ret; 5467 5468 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 5469 return 0; 5470 5471 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode); 5472 if (ret) 5473 return ret; 5474 5475 switch (hdev->fd_cfg.fd_mode) { 5476 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1: 5477 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH; 5478 break; 5479 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1: 5480 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2; 5481 break; 5482 default: 5483 dev_err(&hdev->pdev->dev, 5484 "Unsupported flow director mode %u\n", 5485 hdev->fd_cfg.fd_mode); 5486 return -EOPNOTSUPP; 5487 } 5488 5489 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1]; 5490 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE; 5491 key_cfg->inner_sipv6_word_en = LOW_2_WORDS; 5492 key_cfg->inner_dipv6_word_en = LOW_2_WORDS; 5493 key_cfg->outer_sipv6_word_en = 0; 5494 key_cfg->outer_dipv6_word_en = 0; 5495 5496 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) | 5497 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) | 5498 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5499 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5500 5501 /* If use max 400bit key, we can support tuples for ether type */ 5502 if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 5503 key_cfg->tuple_active |= 5504 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC); 5505 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5506 key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 5507 } 5508 5509 /* roce_type is used to filter roce frames 5510 * dst_vport is used to specify the rule 5511 */ 5512 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT); 5513 5514 ret = hclge_get_fd_allocation(hdev, 5515 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1], 5516 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2], 5517 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1], 5518 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]); 5519 if (ret) 5520 return ret; 5521 5522 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1); 5523 } 5524 5525 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x, 5526 int loc, u8 *key, bool is_add) 5527 { 5528 struct hclge_fd_tcam_config_1_cmd *req1; 5529 struct hclge_fd_tcam_config_2_cmd *req2; 5530 struct hclge_fd_tcam_config_3_cmd *req3; 5531 struct hclge_desc desc[3]; 5532 int ret; 5533 5534 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false); 5535 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5536 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false); 5537 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5538 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false); 5539 5540 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 5541 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 5542 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 5543 5544 req1->stage = stage; 5545 req1->xy_sel = sel_x ? 1 : 0; 5546 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0); 5547 req1->index = cpu_to_le32(loc); 5548 req1->entry_vld = sel_x ? is_add : 0; 5549 5550 if (key) { 5551 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data)); 5552 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)], 5553 sizeof(req2->tcam_data)); 5554 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) + 5555 sizeof(req2->tcam_data)], sizeof(req3->tcam_data)); 5556 } 5557 5558 ret = hclge_cmd_send(&hdev->hw, desc, 3); 5559 if (ret) 5560 dev_err(&hdev->pdev->dev, 5561 "config tcam key fail, ret=%d\n", 5562 ret); 5563 5564 return ret; 5565 } 5566 5567 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc, 5568 struct hclge_fd_ad_data *action) 5569 { 5570 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 5571 struct hclge_fd_ad_config_cmd *req; 5572 struct hclge_desc desc; 5573 u64 ad_data = 0; 5574 int ret; 5575 5576 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false); 5577 5578 req = (struct hclge_fd_ad_config_cmd *)desc.data; 5579 req->index = cpu_to_le32(loc); 5580 req->stage = stage; 5581 5582 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B, 5583 action->write_rule_id_to_bd); 5584 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S, 5585 action->rule_id); 5586 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) { 5587 hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B, 5588 action->override_tc); 5589 hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M, 5590 HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size); 5591 } 5592 ad_data <<= 32; 5593 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet); 5594 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B, 5595 action->forward_to_direct_queue); 5596 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S, 5597 action->queue_id); 5598 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter); 5599 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M, 5600 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id); 5601 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage); 5602 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S, 5603 action->counter_id); 5604 5605 req->ad_data = cpu_to_le64(ad_data); 5606 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5607 if (ret) 5608 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret); 5609 5610 return ret; 5611 } 5612 5613 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y, 5614 struct hclge_fd_rule *rule) 5615 { 5616 int offset, moffset, ip_offset; 5617 enum HCLGE_FD_KEY_OPT key_opt; 5618 u16 tmp_x_s, tmp_y_s; 5619 u32 tmp_x_l, tmp_y_l; 5620 u8 *p = (u8 *)rule; 5621 int i; 5622 5623 if (rule->unused_tuple & BIT(tuple_bit)) 5624 return true; 5625 5626 key_opt = tuple_key_info[tuple_bit].key_opt; 5627 offset = tuple_key_info[tuple_bit].offset; 5628 moffset = tuple_key_info[tuple_bit].moffset; 5629 5630 switch (key_opt) { 5631 case KEY_OPT_U8: 5632 calc_x(*key_x, p[offset], p[moffset]); 5633 calc_y(*key_y, p[offset], p[moffset]); 5634 5635 return true; 5636 case KEY_OPT_LE16: 5637 calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5638 calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5639 *(__le16 *)key_x = cpu_to_le16(tmp_x_s); 5640 *(__le16 *)key_y = cpu_to_le16(tmp_y_s); 5641 5642 return true; 5643 case KEY_OPT_LE32: 5644 calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5645 calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5646 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5647 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5648 5649 return true; 5650 case KEY_OPT_MAC: 5651 for (i = 0; i < ETH_ALEN; i++) { 5652 calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i], 5653 p[moffset + i]); 5654 calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i], 5655 p[moffset + i]); 5656 } 5657 5658 return true; 5659 case KEY_OPT_IP: 5660 ip_offset = IPV4_INDEX * sizeof(u32); 5661 calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]), 5662 *(u32 *)(&p[moffset + ip_offset])); 5663 calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]), 5664 *(u32 *)(&p[moffset + ip_offset])); 5665 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5666 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5667 5668 return true; 5669 default: 5670 return false; 5671 } 5672 } 5673 5674 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 5675 u8 vf_id, u8 network_port_id) 5676 { 5677 u32 port_number = 0; 5678 5679 if (port_type == HOST_PORT) { 5680 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S, 5681 pf_id); 5682 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S, 5683 vf_id); 5684 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT); 5685 } else { 5686 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M, 5687 HCLGE_NETWORK_PORT_ID_S, network_port_id); 5688 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT); 5689 } 5690 5691 return port_number; 5692 } 5693 5694 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg, 5695 __le32 *key_x, __le32 *key_y, 5696 struct hclge_fd_rule *rule) 5697 { 5698 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number; 5699 u8 cur_pos = 0, tuple_size, shift_bits; 5700 unsigned int i; 5701 5702 for (i = 0; i < MAX_META_DATA; i++) { 5703 tuple_size = meta_data_key_info[i].key_length; 5704 tuple_bit = key_cfg->meta_data_active & BIT(i); 5705 5706 switch (tuple_bit) { 5707 case BIT(ROCE_TYPE): 5708 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET); 5709 cur_pos += tuple_size; 5710 break; 5711 case BIT(DST_VPORT): 5712 port_number = hclge_get_port_number(HOST_PORT, 0, 5713 rule->vf_id, 0); 5714 hnae3_set_field(meta_data, 5715 GENMASK(cur_pos + tuple_size, cur_pos), 5716 cur_pos, port_number); 5717 cur_pos += tuple_size; 5718 break; 5719 default: 5720 break; 5721 } 5722 } 5723 5724 calc_x(tmp_x, meta_data, 0xFFFFFFFF); 5725 calc_y(tmp_y, meta_data, 0xFFFFFFFF); 5726 shift_bits = sizeof(meta_data) * 8 - cur_pos; 5727 5728 *key_x = cpu_to_le32(tmp_x << shift_bits); 5729 *key_y = cpu_to_le32(tmp_y << shift_bits); 5730 } 5731 5732 /* A complete key is combined with meta data key and tuple key. 5733 * Meta data key is stored at the MSB region, and tuple key is stored at 5734 * the LSB region, unused bits will be filled 0. 5735 */ 5736 static int hclge_config_key(struct hclge_dev *hdev, u8 stage, 5737 struct hclge_fd_rule *rule) 5738 { 5739 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage]; 5740 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES]; 5741 u8 *cur_key_x, *cur_key_y; 5742 u8 meta_data_region; 5743 u8 tuple_size; 5744 int ret; 5745 u32 i; 5746 5747 memset(key_x, 0, sizeof(key_x)); 5748 memset(key_y, 0, sizeof(key_y)); 5749 cur_key_x = key_x; 5750 cur_key_y = key_y; 5751 5752 for (i = 0; i < MAX_TUPLE; i++) { 5753 bool tuple_valid; 5754 5755 tuple_size = tuple_key_info[i].key_length / 8; 5756 if (!(key_cfg->tuple_active & BIT(i))) 5757 continue; 5758 5759 tuple_valid = hclge_fd_convert_tuple(i, cur_key_x, 5760 cur_key_y, rule); 5761 if (tuple_valid) { 5762 cur_key_x += tuple_size; 5763 cur_key_y += tuple_size; 5764 } 5765 } 5766 5767 meta_data_region = hdev->fd_cfg.max_key_length / 8 - 5768 MAX_META_DATA_LENGTH / 8; 5769 5770 hclge_fd_convert_meta_data(key_cfg, 5771 (__le32 *)(key_x + meta_data_region), 5772 (__le32 *)(key_y + meta_data_region), 5773 rule); 5774 5775 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y, 5776 true); 5777 if (ret) { 5778 dev_err(&hdev->pdev->dev, 5779 "fd key_y config fail, loc=%u, ret=%d\n", 5780 rule->queue_id, ret); 5781 return ret; 5782 } 5783 5784 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x, 5785 true); 5786 if (ret) 5787 dev_err(&hdev->pdev->dev, 5788 "fd key_x config fail, loc=%u, ret=%d\n", 5789 rule->queue_id, ret); 5790 return ret; 5791 } 5792 5793 static int hclge_config_action(struct hclge_dev *hdev, u8 stage, 5794 struct hclge_fd_rule *rule) 5795 { 5796 struct hclge_vport *vport = hdev->vport; 5797 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5798 struct hclge_fd_ad_data ad_data; 5799 5800 memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data)); 5801 ad_data.ad_id = rule->location; 5802 5803 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 5804 ad_data.drop_packet = true; 5805 } else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) { 5806 ad_data.override_tc = true; 5807 ad_data.queue_id = 5808 kinfo->tc_info.tqp_offset[rule->cls_flower.tc]; 5809 ad_data.tc_size = 5810 ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]); 5811 } else { 5812 ad_data.forward_to_direct_queue = true; 5813 ad_data.queue_id = rule->queue_id; 5814 } 5815 5816 if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) { 5817 ad_data.use_counter = true; 5818 ad_data.counter_id = rule->vf_id % 5819 hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]; 5820 } else { 5821 ad_data.use_counter = false; 5822 ad_data.counter_id = 0; 5823 } 5824 5825 ad_data.use_next_stage = false; 5826 ad_data.next_input_key = 0; 5827 5828 ad_data.write_rule_id_to_bd = true; 5829 ad_data.rule_id = rule->location; 5830 5831 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data); 5832 } 5833 5834 static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec, 5835 u32 *unused_tuple) 5836 { 5837 if (!spec || !unused_tuple) 5838 return -EINVAL; 5839 5840 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5841 5842 if (!spec->ip4src) 5843 *unused_tuple |= BIT(INNER_SRC_IP); 5844 5845 if (!spec->ip4dst) 5846 *unused_tuple |= BIT(INNER_DST_IP); 5847 5848 if (!spec->psrc) 5849 *unused_tuple |= BIT(INNER_SRC_PORT); 5850 5851 if (!spec->pdst) 5852 *unused_tuple |= BIT(INNER_DST_PORT); 5853 5854 if (!spec->tos) 5855 *unused_tuple |= BIT(INNER_IP_TOS); 5856 5857 return 0; 5858 } 5859 5860 static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec, 5861 u32 *unused_tuple) 5862 { 5863 if (!spec || !unused_tuple) 5864 return -EINVAL; 5865 5866 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5867 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5868 5869 if (!spec->ip4src) 5870 *unused_tuple |= BIT(INNER_SRC_IP); 5871 5872 if (!spec->ip4dst) 5873 *unused_tuple |= BIT(INNER_DST_IP); 5874 5875 if (!spec->tos) 5876 *unused_tuple |= BIT(INNER_IP_TOS); 5877 5878 if (!spec->proto) 5879 *unused_tuple |= BIT(INNER_IP_PROTO); 5880 5881 if (spec->l4_4_bytes) 5882 return -EOPNOTSUPP; 5883 5884 if (spec->ip_ver != ETH_RX_NFC_IP4) 5885 return -EOPNOTSUPP; 5886 5887 return 0; 5888 } 5889 5890 static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec, 5891 u32 *unused_tuple) 5892 { 5893 if (!spec || !unused_tuple) 5894 return -EINVAL; 5895 5896 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5897 5898 /* check whether src/dst ip address used */ 5899 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5900 *unused_tuple |= BIT(INNER_SRC_IP); 5901 5902 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5903 *unused_tuple |= BIT(INNER_DST_IP); 5904 5905 if (!spec->psrc) 5906 *unused_tuple |= BIT(INNER_SRC_PORT); 5907 5908 if (!spec->pdst) 5909 *unused_tuple |= BIT(INNER_DST_PORT); 5910 5911 if (!spec->tclass) 5912 *unused_tuple |= BIT(INNER_IP_TOS); 5913 5914 return 0; 5915 } 5916 5917 static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec, 5918 u32 *unused_tuple) 5919 { 5920 if (!spec || !unused_tuple) 5921 return -EINVAL; 5922 5923 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5924 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5925 5926 /* check whether src/dst ip address used */ 5927 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5928 *unused_tuple |= BIT(INNER_SRC_IP); 5929 5930 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5931 *unused_tuple |= BIT(INNER_DST_IP); 5932 5933 if (!spec->l4_proto) 5934 *unused_tuple |= BIT(INNER_IP_PROTO); 5935 5936 if (!spec->tclass) 5937 *unused_tuple |= BIT(INNER_IP_TOS); 5938 5939 if (spec->l4_4_bytes) 5940 return -EOPNOTSUPP; 5941 5942 return 0; 5943 } 5944 5945 static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple) 5946 { 5947 if (!spec || !unused_tuple) 5948 return -EINVAL; 5949 5950 *unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5951 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) | 5952 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO); 5953 5954 if (is_zero_ether_addr(spec->h_source)) 5955 *unused_tuple |= BIT(INNER_SRC_MAC); 5956 5957 if (is_zero_ether_addr(spec->h_dest)) 5958 *unused_tuple |= BIT(INNER_DST_MAC); 5959 5960 if (!spec->h_proto) 5961 *unused_tuple |= BIT(INNER_ETH_TYPE); 5962 5963 return 0; 5964 } 5965 5966 static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev, 5967 struct ethtool_rx_flow_spec *fs, 5968 u32 *unused_tuple) 5969 { 5970 if (fs->flow_type & FLOW_EXT) { 5971 if (fs->h_ext.vlan_etype) { 5972 dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n"); 5973 return -EOPNOTSUPP; 5974 } 5975 5976 if (!fs->h_ext.vlan_tci) 5977 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 5978 5979 if (fs->m_ext.vlan_tci && 5980 be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) { 5981 dev_err(&hdev->pdev->dev, 5982 "failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n", 5983 ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1); 5984 return -EINVAL; 5985 } 5986 } else { 5987 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 5988 } 5989 5990 if (fs->flow_type & FLOW_MAC_EXT) { 5991 if (hdev->fd_cfg.fd_mode != 5992 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 5993 dev_err(&hdev->pdev->dev, 5994 "FLOW_MAC_EXT is not supported in current fd mode!\n"); 5995 return -EOPNOTSUPP; 5996 } 5997 5998 if (is_zero_ether_addr(fs->h_ext.h_dest)) 5999 *unused_tuple |= BIT(INNER_DST_MAC); 6000 else 6001 *unused_tuple &= ~BIT(INNER_DST_MAC); 6002 } 6003 6004 return 0; 6005 } 6006 6007 static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple, 6008 struct hclge_fd_user_def_info *info) 6009 { 6010 switch (flow_type) { 6011 case ETHER_FLOW: 6012 info->layer = HCLGE_FD_USER_DEF_L2; 6013 *unused_tuple &= ~BIT(INNER_L2_RSV); 6014 break; 6015 case IP_USER_FLOW: 6016 case IPV6_USER_FLOW: 6017 info->layer = HCLGE_FD_USER_DEF_L3; 6018 *unused_tuple &= ~BIT(INNER_L3_RSV); 6019 break; 6020 case TCP_V4_FLOW: 6021 case UDP_V4_FLOW: 6022 case TCP_V6_FLOW: 6023 case UDP_V6_FLOW: 6024 info->layer = HCLGE_FD_USER_DEF_L4; 6025 *unused_tuple &= ~BIT(INNER_L4_RSV); 6026 break; 6027 default: 6028 return -EOPNOTSUPP; 6029 } 6030 6031 return 0; 6032 } 6033 6034 static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs) 6035 { 6036 return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0; 6037 } 6038 6039 static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev, 6040 struct ethtool_rx_flow_spec *fs, 6041 u32 *unused_tuple, 6042 struct hclge_fd_user_def_info *info) 6043 { 6044 u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active; 6045 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6046 u16 data, offset, data_mask, offset_mask; 6047 int ret; 6048 6049 info->layer = HCLGE_FD_USER_DEF_NONE; 6050 *unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 6051 6052 if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs)) 6053 return 0; 6054 6055 /* user-def data from ethtool is 64 bit value, the bit0~15 is used 6056 * for data, and bit32~47 is used for offset. 6057 */ 6058 data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6059 data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6060 offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6061 offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6062 6063 if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) { 6064 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n"); 6065 return -EOPNOTSUPP; 6066 } 6067 6068 if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) { 6069 dev_err(&hdev->pdev->dev, 6070 "user-def offset[%u] should be no more than %u\n", 6071 offset, HCLGE_FD_MAX_USER_DEF_OFFSET); 6072 return -EINVAL; 6073 } 6074 6075 if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) { 6076 dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n"); 6077 return -EINVAL; 6078 } 6079 6080 ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info); 6081 if (ret) { 6082 dev_err(&hdev->pdev->dev, 6083 "unsupported flow type for user-def bytes, ret = %d\n", 6084 ret); 6085 return ret; 6086 } 6087 6088 info->data = data; 6089 info->data_mask = data_mask; 6090 info->offset = offset; 6091 6092 return 0; 6093 } 6094 6095 static int hclge_fd_check_spec(struct hclge_dev *hdev, 6096 struct ethtool_rx_flow_spec *fs, 6097 u32 *unused_tuple, 6098 struct hclge_fd_user_def_info *info) 6099 { 6100 u32 flow_type; 6101 int ret; 6102 6103 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 6104 dev_err(&hdev->pdev->dev, 6105 "failed to config fd rules, invalid rule location: %u, max is %u\n.", 6106 fs->location, 6107 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1); 6108 return -EINVAL; 6109 } 6110 6111 ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info); 6112 if (ret) 6113 return ret; 6114 6115 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6116 switch (flow_type) { 6117 case SCTP_V4_FLOW: 6118 case TCP_V4_FLOW: 6119 case UDP_V4_FLOW: 6120 ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec, 6121 unused_tuple); 6122 break; 6123 case IP_USER_FLOW: 6124 ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec, 6125 unused_tuple); 6126 break; 6127 case SCTP_V6_FLOW: 6128 case TCP_V6_FLOW: 6129 case UDP_V6_FLOW: 6130 ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec, 6131 unused_tuple); 6132 break; 6133 case IPV6_USER_FLOW: 6134 ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec, 6135 unused_tuple); 6136 break; 6137 case ETHER_FLOW: 6138 if (hdev->fd_cfg.fd_mode != 6139 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6140 dev_err(&hdev->pdev->dev, 6141 "ETHER_FLOW is not supported in current fd mode!\n"); 6142 return -EOPNOTSUPP; 6143 } 6144 6145 ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec, 6146 unused_tuple); 6147 break; 6148 default: 6149 dev_err(&hdev->pdev->dev, 6150 "unsupported protocol type, protocol type = %#x\n", 6151 flow_type); 6152 return -EOPNOTSUPP; 6153 } 6154 6155 if (ret) { 6156 dev_err(&hdev->pdev->dev, 6157 "failed to check flow union tuple, ret = %d\n", 6158 ret); 6159 return ret; 6160 } 6161 6162 return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple); 6163 } 6164 6165 static void hclge_fd_get_tcpip4_tuple(struct ethtool_rx_flow_spec *fs, 6166 struct hclge_fd_rule *rule, u8 ip_proto) 6167 { 6168 rule->tuples.src_ip[IPV4_INDEX] = 6169 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src); 6170 rule->tuples_mask.src_ip[IPV4_INDEX] = 6171 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src); 6172 6173 rule->tuples.dst_ip[IPV4_INDEX] = 6174 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst); 6175 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6176 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst); 6177 6178 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc); 6179 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc); 6180 6181 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst); 6182 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst); 6183 6184 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos; 6185 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos; 6186 6187 rule->tuples.ether_proto = ETH_P_IP; 6188 rule->tuples_mask.ether_proto = 0xFFFF; 6189 6190 rule->tuples.ip_proto = ip_proto; 6191 rule->tuples_mask.ip_proto = 0xFF; 6192 } 6193 6194 static void hclge_fd_get_ip4_tuple(struct ethtool_rx_flow_spec *fs, 6195 struct hclge_fd_rule *rule) 6196 { 6197 rule->tuples.src_ip[IPV4_INDEX] = 6198 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src); 6199 rule->tuples_mask.src_ip[IPV4_INDEX] = 6200 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src); 6201 6202 rule->tuples.dst_ip[IPV4_INDEX] = 6203 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst); 6204 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6205 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst); 6206 6207 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos; 6208 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos; 6209 6210 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto; 6211 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto; 6212 6213 rule->tuples.ether_proto = ETH_P_IP; 6214 rule->tuples_mask.ether_proto = 0xFFFF; 6215 } 6216 6217 static void hclge_fd_get_tcpip6_tuple(struct ethtool_rx_flow_spec *fs, 6218 struct hclge_fd_rule *rule, u8 ip_proto) 6219 { 6220 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.tcp_ip6_spec.ip6src, 6221 IPV6_SIZE); 6222 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.tcp_ip6_spec.ip6src, 6223 IPV6_SIZE); 6224 6225 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.tcp_ip6_spec.ip6dst, 6226 IPV6_SIZE); 6227 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.tcp_ip6_spec.ip6dst, 6228 IPV6_SIZE); 6229 6230 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc); 6231 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc); 6232 6233 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst); 6234 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst); 6235 6236 rule->tuples.ether_proto = ETH_P_IPV6; 6237 rule->tuples_mask.ether_proto = 0xFFFF; 6238 6239 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6240 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6241 6242 rule->tuples.ip_proto = ip_proto; 6243 rule->tuples_mask.ip_proto = 0xFF; 6244 } 6245 6246 static void hclge_fd_get_ip6_tuple(struct ethtool_rx_flow_spec *fs, 6247 struct hclge_fd_rule *rule) 6248 { 6249 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.usr_ip6_spec.ip6src, 6250 IPV6_SIZE); 6251 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.usr_ip6_spec.ip6src, 6252 IPV6_SIZE); 6253 6254 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.usr_ip6_spec.ip6dst, 6255 IPV6_SIZE); 6256 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.usr_ip6_spec.ip6dst, 6257 IPV6_SIZE); 6258 6259 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto; 6260 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto; 6261 6262 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6263 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6264 6265 rule->tuples.ether_proto = ETH_P_IPV6; 6266 rule->tuples_mask.ether_proto = 0xFFFF; 6267 } 6268 6269 static void hclge_fd_get_ether_tuple(struct ethtool_rx_flow_spec *fs, 6270 struct hclge_fd_rule *rule) 6271 { 6272 ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source); 6273 ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source); 6274 6275 ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest); 6276 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest); 6277 6278 rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto); 6279 rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto); 6280 } 6281 6282 static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info, 6283 struct hclge_fd_rule *rule) 6284 { 6285 switch (info->layer) { 6286 case HCLGE_FD_USER_DEF_L2: 6287 rule->tuples.l2_user_def = info->data; 6288 rule->tuples_mask.l2_user_def = info->data_mask; 6289 break; 6290 case HCLGE_FD_USER_DEF_L3: 6291 rule->tuples.l3_user_def = info->data; 6292 rule->tuples_mask.l3_user_def = info->data_mask; 6293 break; 6294 case HCLGE_FD_USER_DEF_L4: 6295 rule->tuples.l4_user_def = (u32)info->data << 16; 6296 rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16; 6297 break; 6298 default: 6299 break; 6300 } 6301 6302 rule->ep.user_def = *info; 6303 } 6304 6305 static int hclge_fd_get_tuple(struct ethtool_rx_flow_spec *fs, 6306 struct hclge_fd_rule *rule, 6307 struct hclge_fd_user_def_info *info) 6308 { 6309 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6310 6311 switch (flow_type) { 6312 case SCTP_V4_FLOW: 6313 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_SCTP); 6314 break; 6315 case TCP_V4_FLOW: 6316 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_TCP); 6317 break; 6318 case UDP_V4_FLOW: 6319 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_UDP); 6320 break; 6321 case IP_USER_FLOW: 6322 hclge_fd_get_ip4_tuple(fs, rule); 6323 break; 6324 case SCTP_V6_FLOW: 6325 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_SCTP); 6326 break; 6327 case TCP_V6_FLOW: 6328 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_TCP); 6329 break; 6330 case UDP_V6_FLOW: 6331 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_UDP); 6332 break; 6333 case IPV6_USER_FLOW: 6334 hclge_fd_get_ip6_tuple(fs, rule); 6335 break; 6336 case ETHER_FLOW: 6337 hclge_fd_get_ether_tuple(fs, rule); 6338 break; 6339 default: 6340 return -EOPNOTSUPP; 6341 } 6342 6343 if (fs->flow_type & FLOW_EXT) { 6344 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci); 6345 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci); 6346 hclge_fd_get_user_def_tuple(info, rule); 6347 } 6348 6349 if (fs->flow_type & FLOW_MAC_EXT) { 6350 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest); 6351 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest); 6352 } 6353 6354 return 0; 6355 } 6356 6357 static int hclge_fd_config_rule(struct hclge_dev *hdev, 6358 struct hclge_fd_rule *rule) 6359 { 6360 int ret; 6361 6362 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule); 6363 if (ret) 6364 return ret; 6365 6366 return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule); 6367 } 6368 6369 static int hclge_add_fd_entry_common(struct hclge_dev *hdev, 6370 struct hclge_fd_rule *rule) 6371 { 6372 int ret; 6373 6374 spin_lock_bh(&hdev->fd_rule_lock); 6375 6376 if (hdev->fd_active_type != rule->rule_type && 6377 (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6378 hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) { 6379 dev_err(&hdev->pdev->dev, 6380 "mode conflict(new type %d, active type %d), please delete existent rules first\n", 6381 rule->rule_type, hdev->fd_active_type); 6382 spin_unlock_bh(&hdev->fd_rule_lock); 6383 return -EINVAL; 6384 } 6385 6386 ret = hclge_fd_check_user_def_refcnt(hdev, rule); 6387 if (ret) 6388 goto out; 6389 6390 ret = hclge_clear_arfs_rules(hdev); 6391 if (ret) 6392 goto out; 6393 6394 ret = hclge_fd_config_rule(hdev, rule); 6395 if (ret) 6396 goto out; 6397 6398 rule->state = HCLGE_FD_ACTIVE; 6399 hdev->fd_active_type = rule->rule_type; 6400 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 6401 6402 out: 6403 spin_unlock_bh(&hdev->fd_rule_lock); 6404 return ret; 6405 } 6406 6407 static bool hclge_is_cls_flower_active(struct hnae3_handle *handle) 6408 { 6409 struct hclge_vport *vport = hclge_get_vport(handle); 6410 struct hclge_dev *hdev = vport->back; 6411 6412 return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE; 6413 } 6414 6415 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie, 6416 u16 *vport_id, u8 *action, u16 *queue_id) 6417 { 6418 struct hclge_vport *vport = hdev->vport; 6419 6420 if (ring_cookie == RX_CLS_FLOW_DISC) { 6421 *action = HCLGE_FD_ACTION_DROP_PACKET; 6422 } else { 6423 u32 ring = ethtool_get_flow_spec_ring(ring_cookie); 6424 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie); 6425 u16 tqps; 6426 6427 /* To keep consistent with user's configuration, minus 1 when 6428 * printing 'vf', because vf id from ethtool is added 1 for vf. 6429 */ 6430 if (vf > hdev->num_req_vfs) { 6431 dev_err(&hdev->pdev->dev, 6432 "Error: vf id (%u) should be less than %u\n", 6433 vf - 1U, hdev->num_req_vfs); 6434 return -EINVAL; 6435 } 6436 6437 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id; 6438 tqps = hdev->vport[vf].nic.kinfo.num_tqps; 6439 6440 if (ring >= tqps) { 6441 dev_err(&hdev->pdev->dev, 6442 "Error: queue id (%u) > max tqp num (%u)\n", 6443 ring, tqps - 1U); 6444 return -EINVAL; 6445 } 6446 6447 *action = HCLGE_FD_ACTION_SELECT_QUEUE; 6448 *queue_id = ring; 6449 } 6450 6451 return 0; 6452 } 6453 6454 static int hclge_add_fd_entry(struct hnae3_handle *handle, 6455 struct ethtool_rxnfc *cmd) 6456 { 6457 struct hclge_vport *vport = hclge_get_vport(handle); 6458 struct hclge_dev *hdev = vport->back; 6459 struct hclge_fd_user_def_info info; 6460 u16 dst_vport_id = 0, q_index = 0; 6461 struct ethtool_rx_flow_spec *fs; 6462 struct hclge_fd_rule *rule; 6463 u32 unused = 0; 6464 u8 action; 6465 int ret; 6466 6467 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 6468 dev_err(&hdev->pdev->dev, 6469 "flow table director is not supported\n"); 6470 return -EOPNOTSUPP; 6471 } 6472 6473 if (!hdev->fd_en) { 6474 dev_err(&hdev->pdev->dev, 6475 "please enable flow director first\n"); 6476 return -EOPNOTSUPP; 6477 } 6478 6479 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6480 6481 ret = hclge_fd_check_spec(hdev, fs, &unused, &info); 6482 if (ret) 6483 return ret; 6484 6485 ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id, 6486 &action, &q_index); 6487 if (ret) 6488 return ret; 6489 6490 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 6491 if (!rule) 6492 return -ENOMEM; 6493 6494 ret = hclge_fd_get_tuple(fs, rule, &info); 6495 if (ret) { 6496 kfree(rule); 6497 return ret; 6498 } 6499 6500 rule->flow_type = fs->flow_type; 6501 rule->location = fs->location; 6502 rule->unused_tuple = unused; 6503 rule->vf_id = dst_vport_id; 6504 rule->queue_id = q_index; 6505 rule->action = action; 6506 rule->rule_type = HCLGE_FD_EP_ACTIVE; 6507 6508 ret = hclge_add_fd_entry_common(hdev, rule); 6509 if (ret) 6510 kfree(rule); 6511 6512 return ret; 6513 } 6514 6515 static int hclge_del_fd_entry(struct hnae3_handle *handle, 6516 struct ethtool_rxnfc *cmd) 6517 { 6518 struct hclge_vport *vport = hclge_get_vport(handle); 6519 struct hclge_dev *hdev = vport->back; 6520 struct ethtool_rx_flow_spec *fs; 6521 int ret; 6522 6523 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6524 return -EOPNOTSUPP; 6525 6526 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6527 6528 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6529 return -EINVAL; 6530 6531 spin_lock_bh(&hdev->fd_rule_lock); 6532 if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6533 !test_bit(fs->location, hdev->fd_bmap)) { 6534 dev_err(&hdev->pdev->dev, 6535 "Delete fail, rule %u is inexistent\n", fs->location); 6536 spin_unlock_bh(&hdev->fd_rule_lock); 6537 return -ENOENT; 6538 } 6539 6540 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location, 6541 NULL, false); 6542 if (ret) 6543 goto out; 6544 6545 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL); 6546 6547 out: 6548 spin_unlock_bh(&hdev->fd_rule_lock); 6549 return ret; 6550 } 6551 6552 static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev, 6553 bool clear_list) 6554 { 6555 struct hclge_fd_rule *rule; 6556 struct hlist_node *node; 6557 u16 location; 6558 6559 spin_lock_bh(&hdev->fd_rule_lock); 6560 6561 for_each_set_bit(location, hdev->fd_bmap, 6562 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6563 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location, 6564 NULL, false); 6565 6566 if (clear_list) { 6567 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, 6568 rule_node) { 6569 hlist_del(&rule->rule_node); 6570 kfree(rule); 6571 } 6572 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 6573 hdev->hclge_fd_rule_num = 0; 6574 bitmap_zero(hdev->fd_bmap, 6575 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 6576 } 6577 6578 spin_unlock_bh(&hdev->fd_rule_lock); 6579 } 6580 6581 static void hclge_del_all_fd_entries(struct hclge_dev *hdev) 6582 { 6583 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6584 return; 6585 6586 hclge_clear_fd_rules_in_list(hdev, true); 6587 hclge_fd_disable_user_def(hdev); 6588 } 6589 6590 static int hclge_restore_fd_entries(struct hnae3_handle *handle) 6591 { 6592 struct hclge_vport *vport = hclge_get_vport(handle); 6593 struct hclge_dev *hdev = vport->back; 6594 struct hclge_fd_rule *rule; 6595 struct hlist_node *node; 6596 6597 /* Return ok here, because reset error handling will check this 6598 * return value. If error is returned here, the reset process will 6599 * fail. 6600 */ 6601 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6602 return 0; 6603 6604 /* if fd is disabled, should not restore it when reset */ 6605 if (!hdev->fd_en) 6606 return 0; 6607 6608 spin_lock_bh(&hdev->fd_rule_lock); 6609 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6610 if (rule->state == HCLGE_FD_ACTIVE) 6611 rule->state = HCLGE_FD_TO_ADD; 6612 } 6613 spin_unlock_bh(&hdev->fd_rule_lock); 6614 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 6615 6616 return 0; 6617 } 6618 6619 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle, 6620 struct ethtool_rxnfc *cmd) 6621 { 6622 struct hclge_vport *vport = hclge_get_vport(handle); 6623 struct hclge_dev *hdev = vport->back; 6624 6625 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev) || hclge_is_cls_flower_active(handle)) 6626 return -EOPNOTSUPP; 6627 6628 cmd->rule_cnt = hdev->hclge_fd_rule_num; 6629 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6630 6631 return 0; 6632 } 6633 6634 static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule, 6635 struct ethtool_tcpip4_spec *spec, 6636 struct ethtool_tcpip4_spec *spec_mask) 6637 { 6638 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6639 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6640 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6641 6642 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6643 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6644 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6645 6646 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6647 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6648 0 : cpu_to_be16(rule->tuples_mask.src_port); 6649 6650 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6651 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6652 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6653 6654 spec->tos = rule->tuples.ip_tos; 6655 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6656 0 : rule->tuples_mask.ip_tos; 6657 } 6658 6659 static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule, 6660 struct ethtool_usrip4_spec *spec, 6661 struct ethtool_usrip4_spec *spec_mask) 6662 { 6663 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6664 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6665 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6666 6667 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6668 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6669 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6670 6671 spec->tos = rule->tuples.ip_tos; 6672 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6673 0 : rule->tuples_mask.ip_tos; 6674 6675 spec->proto = rule->tuples.ip_proto; 6676 spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6677 0 : rule->tuples_mask.ip_proto; 6678 6679 spec->ip_ver = ETH_RX_NFC_IP4; 6680 } 6681 6682 static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule, 6683 struct ethtool_tcpip6_spec *spec, 6684 struct ethtool_tcpip6_spec *spec_mask) 6685 { 6686 cpu_to_be32_array(spec->ip6src, 6687 rule->tuples.src_ip, IPV6_SIZE); 6688 cpu_to_be32_array(spec->ip6dst, 6689 rule->tuples.dst_ip, IPV6_SIZE); 6690 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6691 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6692 else 6693 cpu_to_be32_array(spec_mask->ip6src, rule->tuples_mask.src_ip, 6694 IPV6_SIZE); 6695 6696 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6697 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6698 else 6699 cpu_to_be32_array(spec_mask->ip6dst, rule->tuples_mask.dst_ip, 6700 IPV6_SIZE); 6701 6702 spec->tclass = rule->tuples.ip_tos; 6703 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6704 0 : rule->tuples_mask.ip_tos; 6705 6706 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6707 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6708 0 : cpu_to_be16(rule->tuples_mask.src_port); 6709 6710 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6711 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6712 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6713 } 6714 6715 static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule, 6716 struct ethtool_usrip6_spec *spec, 6717 struct ethtool_usrip6_spec *spec_mask) 6718 { 6719 cpu_to_be32_array(spec->ip6src, rule->tuples.src_ip, IPV6_SIZE); 6720 cpu_to_be32_array(spec->ip6dst, rule->tuples.dst_ip, IPV6_SIZE); 6721 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6722 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6723 else 6724 cpu_to_be32_array(spec_mask->ip6src, 6725 rule->tuples_mask.src_ip, IPV6_SIZE); 6726 6727 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6728 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6729 else 6730 cpu_to_be32_array(spec_mask->ip6dst, 6731 rule->tuples_mask.dst_ip, IPV6_SIZE); 6732 6733 spec->tclass = rule->tuples.ip_tos; 6734 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6735 0 : rule->tuples_mask.ip_tos; 6736 6737 spec->l4_proto = rule->tuples.ip_proto; 6738 spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6739 0 : rule->tuples_mask.ip_proto; 6740 } 6741 6742 static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule, 6743 struct ethhdr *spec, 6744 struct ethhdr *spec_mask) 6745 { 6746 ether_addr_copy(spec->h_source, rule->tuples.src_mac); 6747 ether_addr_copy(spec->h_dest, rule->tuples.dst_mac); 6748 6749 if (rule->unused_tuple & BIT(INNER_SRC_MAC)) 6750 eth_zero_addr(spec_mask->h_source); 6751 else 6752 ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac); 6753 6754 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6755 eth_zero_addr(spec_mask->h_dest); 6756 else 6757 ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac); 6758 6759 spec->h_proto = cpu_to_be16(rule->tuples.ether_proto); 6760 spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ? 6761 0 : cpu_to_be16(rule->tuples_mask.ether_proto); 6762 } 6763 6764 static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs, 6765 struct hclge_fd_rule *rule) 6766 { 6767 if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) == 6768 HCLGE_FD_TUPLE_USER_DEF_TUPLES) { 6769 fs->h_ext.data[0] = 0; 6770 fs->h_ext.data[1] = 0; 6771 fs->m_ext.data[0] = 0; 6772 fs->m_ext.data[1] = 0; 6773 } else { 6774 fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset); 6775 fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data); 6776 fs->m_ext.data[0] = 6777 cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK); 6778 fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask); 6779 } 6780 } 6781 6782 static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs, 6783 struct hclge_fd_rule *rule) 6784 { 6785 if (fs->flow_type & FLOW_EXT) { 6786 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1); 6787 fs->m_ext.vlan_tci = 6788 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ? 6789 0 : cpu_to_be16(rule->tuples_mask.vlan_tag1); 6790 6791 hclge_fd_get_user_def_info(fs, rule); 6792 } 6793 6794 if (fs->flow_type & FLOW_MAC_EXT) { 6795 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac); 6796 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6797 eth_zero_addr(fs->m_u.ether_spec.h_dest); 6798 else 6799 ether_addr_copy(fs->m_u.ether_spec.h_dest, 6800 rule->tuples_mask.dst_mac); 6801 } 6802 } 6803 6804 static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev, 6805 u16 location) 6806 { 6807 struct hclge_fd_rule *rule = NULL; 6808 struct hlist_node *node2; 6809 6810 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) { 6811 if (rule->location == location) 6812 return rule; 6813 else if (rule->location > location) 6814 return NULL; 6815 } 6816 6817 return NULL; 6818 } 6819 6820 static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs, 6821 struct hclge_fd_rule *rule) 6822 { 6823 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 6824 fs->ring_cookie = RX_CLS_FLOW_DISC; 6825 } else { 6826 u64 vf_id; 6827 6828 fs->ring_cookie = rule->queue_id; 6829 vf_id = rule->vf_id; 6830 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 6831 fs->ring_cookie |= vf_id; 6832 } 6833 } 6834 6835 static int hclge_get_fd_rule_info(struct hnae3_handle *handle, 6836 struct ethtool_rxnfc *cmd) 6837 { 6838 struct hclge_vport *vport = hclge_get_vport(handle); 6839 struct hclge_fd_rule *rule = NULL; 6840 struct hclge_dev *hdev = vport->back; 6841 struct ethtool_rx_flow_spec *fs; 6842 6843 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6844 return -EOPNOTSUPP; 6845 6846 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6847 6848 spin_lock_bh(&hdev->fd_rule_lock); 6849 6850 rule = hclge_get_fd_rule(hdev, fs->location); 6851 if (!rule) { 6852 spin_unlock_bh(&hdev->fd_rule_lock); 6853 return -ENOENT; 6854 } 6855 6856 fs->flow_type = rule->flow_type; 6857 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 6858 case SCTP_V4_FLOW: 6859 case TCP_V4_FLOW: 6860 case UDP_V4_FLOW: 6861 hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec, 6862 &fs->m_u.tcp_ip4_spec); 6863 break; 6864 case IP_USER_FLOW: 6865 hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec, 6866 &fs->m_u.usr_ip4_spec); 6867 break; 6868 case SCTP_V6_FLOW: 6869 case TCP_V6_FLOW: 6870 case UDP_V6_FLOW: 6871 hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec, 6872 &fs->m_u.tcp_ip6_spec); 6873 break; 6874 case IPV6_USER_FLOW: 6875 hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec, 6876 &fs->m_u.usr_ip6_spec); 6877 break; 6878 /* The flow type of fd rule has been checked before adding in to rule 6879 * list. As other flow types have been handled, it must be ETHER_FLOW 6880 * for the default case 6881 */ 6882 default: 6883 hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec, 6884 &fs->m_u.ether_spec); 6885 break; 6886 } 6887 6888 hclge_fd_get_ext_info(fs, rule); 6889 6890 hclge_fd_get_ring_cookie(fs, rule); 6891 6892 spin_unlock_bh(&hdev->fd_rule_lock); 6893 6894 return 0; 6895 } 6896 6897 static int hclge_get_all_rules(struct hnae3_handle *handle, 6898 struct ethtool_rxnfc *cmd, u32 *rule_locs) 6899 { 6900 struct hclge_vport *vport = hclge_get_vport(handle); 6901 struct hclge_dev *hdev = vport->back; 6902 struct hclge_fd_rule *rule; 6903 struct hlist_node *node2; 6904 int cnt = 0; 6905 6906 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6907 return -EOPNOTSUPP; 6908 6909 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6910 6911 spin_lock_bh(&hdev->fd_rule_lock); 6912 hlist_for_each_entry_safe(rule, node2, 6913 &hdev->fd_rule_list, rule_node) { 6914 if (cnt == cmd->rule_cnt) { 6915 spin_unlock_bh(&hdev->fd_rule_lock); 6916 return -EMSGSIZE; 6917 } 6918 6919 if (rule->state == HCLGE_FD_TO_DEL) 6920 continue; 6921 6922 rule_locs[cnt] = rule->location; 6923 cnt++; 6924 } 6925 6926 spin_unlock_bh(&hdev->fd_rule_lock); 6927 6928 cmd->rule_cnt = cnt; 6929 6930 return 0; 6931 } 6932 6933 static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys, 6934 struct hclge_fd_rule_tuples *tuples) 6935 { 6936 #define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32 6937 #define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32 6938 6939 tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto); 6940 tuples->ip_proto = fkeys->basic.ip_proto; 6941 tuples->dst_port = be16_to_cpu(fkeys->ports.dst); 6942 6943 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 6944 tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src); 6945 tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst); 6946 } else { 6947 int i; 6948 6949 for (i = 0; i < IPV6_SIZE; i++) { 6950 tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]); 6951 tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]); 6952 } 6953 } 6954 } 6955 6956 /* traverse all rules, check whether an existed rule has the same tuples */ 6957 static struct hclge_fd_rule * 6958 hclge_fd_search_flow_keys(struct hclge_dev *hdev, 6959 const struct hclge_fd_rule_tuples *tuples) 6960 { 6961 struct hclge_fd_rule *rule = NULL; 6962 struct hlist_node *node; 6963 6964 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6965 if (!memcmp(tuples, &rule->tuples, sizeof(*tuples))) 6966 return rule; 6967 } 6968 6969 return NULL; 6970 } 6971 6972 static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples, 6973 struct hclge_fd_rule *rule) 6974 { 6975 rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 6976 BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) | 6977 BIT(INNER_SRC_PORT); 6978 rule->action = 0; 6979 rule->vf_id = 0; 6980 rule->rule_type = HCLGE_FD_ARFS_ACTIVE; 6981 rule->state = HCLGE_FD_TO_ADD; 6982 if (tuples->ether_proto == ETH_P_IP) { 6983 if (tuples->ip_proto == IPPROTO_TCP) 6984 rule->flow_type = TCP_V4_FLOW; 6985 else 6986 rule->flow_type = UDP_V4_FLOW; 6987 } else { 6988 if (tuples->ip_proto == IPPROTO_TCP) 6989 rule->flow_type = TCP_V6_FLOW; 6990 else 6991 rule->flow_type = UDP_V6_FLOW; 6992 } 6993 memcpy(&rule->tuples, tuples, sizeof(rule->tuples)); 6994 memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask)); 6995 } 6996 6997 static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id, 6998 u16 flow_id, struct flow_keys *fkeys) 6999 { 7000 struct hclge_vport *vport = hclge_get_vport(handle); 7001 struct hclge_fd_rule_tuples new_tuples = {}; 7002 struct hclge_dev *hdev = vport->back; 7003 struct hclge_fd_rule *rule; 7004 u16 bit_id; 7005 7006 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7007 return -EOPNOTSUPP; 7008 7009 /* when there is already fd rule existed add by user, 7010 * arfs should not work 7011 */ 7012 spin_lock_bh(&hdev->fd_rule_lock); 7013 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE && 7014 hdev->fd_active_type != HCLGE_FD_RULE_NONE) { 7015 spin_unlock_bh(&hdev->fd_rule_lock); 7016 return -EOPNOTSUPP; 7017 } 7018 7019 hclge_fd_get_flow_tuples(fkeys, &new_tuples); 7020 7021 /* check is there flow director filter existed for this flow, 7022 * if not, create a new filter for it; 7023 * if filter exist with different queue id, modify the filter; 7024 * if filter exist with same queue id, do nothing 7025 */ 7026 rule = hclge_fd_search_flow_keys(hdev, &new_tuples); 7027 if (!rule) { 7028 bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM); 7029 if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7030 spin_unlock_bh(&hdev->fd_rule_lock); 7031 return -ENOSPC; 7032 } 7033 7034 rule = kzalloc(sizeof(*rule), GFP_ATOMIC); 7035 if (!rule) { 7036 spin_unlock_bh(&hdev->fd_rule_lock); 7037 return -ENOMEM; 7038 } 7039 7040 rule->location = bit_id; 7041 rule->arfs.flow_id = flow_id; 7042 rule->queue_id = queue_id; 7043 hclge_fd_build_arfs_rule(&new_tuples, rule); 7044 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 7045 hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE; 7046 } else if (rule->queue_id != queue_id) { 7047 rule->queue_id = queue_id; 7048 rule->state = HCLGE_FD_TO_ADD; 7049 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7050 hclge_task_schedule(hdev, 0); 7051 } 7052 spin_unlock_bh(&hdev->fd_rule_lock); 7053 return rule->location; 7054 } 7055 7056 static void hclge_rfs_filter_expire(struct hclge_dev *hdev) 7057 { 7058 #ifdef CONFIG_RFS_ACCEL 7059 struct hnae3_handle *handle = &hdev->vport[0].nic; 7060 struct hclge_fd_rule *rule; 7061 struct hlist_node *node; 7062 7063 spin_lock_bh(&hdev->fd_rule_lock); 7064 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) { 7065 spin_unlock_bh(&hdev->fd_rule_lock); 7066 return; 7067 } 7068 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7069 if (rule->state != HCLGE_FD_ACTIVE) 7070 continue; 7071 if (rps_may_expire_flow(handle->netdev, rule->queue_id, 7072 rule->arfs.flow_id, rule->location)) { 7073 rule->state = HCLGE_FD_TO_DEL; 7074 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7075 } 7076 } 7077 spin_unlock_bh(&hdev->fd_rule_lock); 7078 #endif 7079 } 7080 7081 /* make sure being called after lock up with fd_rule_lock */ 7082 static int hclge_clear_arfs_rules(struct hclge_dev *hdev) 7083 { 7084 #ifdef CONFIG_RFS_ACCEL 7085 struct hclge_fd_rule *rule; 7086 struct hlist_node *node; 7087 int ret; 7088 7089 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) 7090 return 0; 7091 7092 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7093 switch (rule->state) { 7094 case HCLGE_FD_TO_DEL: 7095 case HCLGE_FD_ACTIVE: 7096 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7097 rule->location, NULL, false); 7098 if (ret) 7099 return ret; 7100 fallthrough; 7101 case HCLGE_FD_TO_ADD: 7102 hclge_fd_dec_rule_cnt(hdev, rule->location); 7103 hlist_del(&rule->rule_node); 7104 kfree(rule); 7105 break; 7106 default: 7107 break; 7108 } 7109 } 7110 hclge_sync_fd_state(hdev); 7111 7112 #endif 7113 return 0; 7114 } 7115 7116 static void hclge_get_cls_key_basic(const struct flow_rule *flow, 7117 struct hclge_fd_rule *rule) 7118 { 7119 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) { 7120 struct flow_match_basic match; 7121 u16 ethtype_key, ethtype_mask; 7122 7123 flow_rule_match_basic(flow, &match); 7124 ethtype_key = ntohs(match.key->n_proto); 7125 ethtype_mask = ntohs(match.mask->n_proto); 7126 7127 if (ethtype_key == ETH_P_ALL) { 7128 ethtype_key = 0; 7129 ethtype_mask = 0; 7130 } 7131 rule->tuples.ether_proto = ethtype_key; 7132 rule->tuples_mask.ether_proto = ethtype_mask; 7133 rule->tuples.ip_proto = match.key->ip_proto; 7134 rule->tuples_mask.ip_proto = match.mask->ip_proto; 7135 } else { 7136 rule->unused_tuple |= BIT(INNER_IP_PROTO); 7137 rule->unused_tuple |= BIT(INNER_ETH_TYPE); 7138 } 7139 } 7140 7141 static void hclge_get_cls_key_mac(const struct flow_rule *flow, 7142 struct hclge_fd_rule *rule) 7143 { 7144 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 7145 struct flow_match_eth_addrs match; 7146 7147 flow_rule_match_eth_addrs(flow, &match); 7148 ether_addr_copy(rule->tuples.dst_mac, match.key->dst); 7149 ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst); 7150 ether_addr_copy(rule->tuples.src_mac, match.key->src); 7151 ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src); 7152 } else { 7153 rule->unused_tuple |= BIT(INNER_DST_MAC); 7154 rule->unused_tuple |= BIT(INNER_SRC_MAC); 7155 } 7156 } 7157 7158 static void hclge_get_cls_key_vlan(const struct flow_rule *flow, 7159 struct hclge_fd_rule *rule) 7160 { 7161 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) { 7162 struct flow_match_vlan match; 7163 7164 flow_rule_match_vlan(flow, &match); 7165 rule->tuples.vlan_tag1 = match.key->vlan_id | 7166 (match.key->vlan_priority << VLAN_PRIO_SHIFT); 7167 rule->tuples_mask.vlan_tag1 = match.mask->vlan_id | 7168 (match.mask->vlan_priority << VLAN_PRIO_SHIFT); 7169 } else { 7170 rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST); 7171 } 7172 } 7173 7174 static void hclge_get_cls_key_ip(const struct flow_rule *flow, 7175 struct hclge_fd_rule *rule) 7176 { 7177 u16 addr_type = 0; 7178 7179 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) { 7180 struct flow_match_control match; 7181 7182 flow_rule_match_control(flow, &match); 7183 addr_type = match.key->addr_type; 7184 } 7185 7186 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { 7187 struct flow_match_ipv4_addrs match; 7188 7189 flow_rule_match_ipv4_addrs(flow, &match); 7190 rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src); 7191 rule->tuples_mask.src_ip[IPV4_INDEX] = 7192 be32_to_cpu(match.mask->src); 7193 rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst); 7194 rule->tuples_mask.dst_ip[IPV4_INDEX] = 7195 be32_to_cpu(match.mask->dst); 7196 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { 7197 struct flow_match_ipv6_addrs match; 7198 7199 flow_rule_match_ipv6_addrs(flow, &match); 7200 be32_to_cpu_array(rule->tuples.src_ip, match.key->src.s6_addr32, 7201 IPV6_SIZE); 7202 be32_to_cpu_array(rule->tuples_mask.src_ip, 7203 match.mask->src.s6_addr32, IPV6_SIZE); 7204 be32_to_cpu_array(rule->tuples.dst_ip, match.key->dst.s6_addr32, 7205 IPV6_SIZE); 7206 be32_to_cpu_array(rule->tuples_mask.dst_ip, 7207 match.mask->dst.s6_addr32, IPV6_SIZE); 7208 } else { 7209 rule->unused_tuple |= BIT(INNER_SRC_IP); 7210 rule->unused_tuple |= BIT(INNER_DST_IP); 7211 } 7212 } 7213 7214 static void hclge_get_cls_key_port(const struct flow_rule *flow, 7215 struct hclge_fd_rule *rule) 7216 { 7217 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) { 7218 struct flow_match_ports match; 7219 7220 flow_rule_match_ports(flow, &match); 7221 7222 rule->tuples.src_port = be16_to_cpu(match.key->src); 7223 rule->tuples_mask.src_port = be16_to_cpu(match.mask->src); 7224 rule->tuples.dst_port = be16_to_cpu(match.key->dst); 7225 rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst); 7226 } else { 7227 rule->unused_tuple |= BIT(INNER_SRC_PORT); 7228 rule->unused_tuple |= BIT(INNER_DST_PORT); 7229 } 7230 } 7231 7232 static int hclge_parse_cls_flower(struct hclge_dev *hdev, 7233 struct flow_cls_offload *cls_flower, 7234 struct hclge_fd_rule *rule) 7235 { 7236 struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower); 7237 struct flow_dissector *dissector = flow->match.dissector; 7238 7239 if (dissector->used_keys & 7240 ~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 7241 BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 7242 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 7243 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) | 7244 BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | 7245 BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | 7246 BIT_ULL(FLOW_DISSECTOR_KEY_PORTS))) { 7247 dev_err(&hdev->pdev->dev, "unsupported key set: %#llx\n", 7248 dissector->used_keys); 7249 return -EOPNOTSUPP; 7250 } 7251 7252 hclge_get_cls_key_basic(flow, rule); 7253 hclge_get_cls_key_mac(flow, rule); 7254 hclge_get_cls_key_vlan(flow, rule); 7255 hclge_get_cls_key_ip(flow, rule); 7256 hclge_get_cls_key_port(flow, rule); 7257 7258 return 0; 7259 } 7260 7261 static int hclge_check_cls_flower(struct hclge_dev *hdev, 7262 struct flow_cls_offload *cls_flower, int tc) 7263 { 7264 u32 prio = cls_flower->common.prio; 7265 7266 if (tc < 0 || tc > hdev->tc_max) { 7267 dev_err(&hdev->pdev->dev, "invalid traffic class\n"); 7268 return -EINVAL; 7269 } 7270 7271 if (prio == 0 || 7272 prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7273 dev_err(&hdev->pdev->dev, 7274 "prio %u should be in range[1, %u]\n", 7275 prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 7276 return -EINVAL; 7277 } 7278 7279 if (test_bit(prio - 1, hdev->fd_bmap)) { 7280 dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio); 7281 return -EINVAL; 7282 } 7283 return 0; 7284 } 7285 7286 static int hclge_add_cls_flower(struct hnae3_handle *handle, 7287 struct flow_cls_offload *cls_flower, 7288 int tc) 7289 { 7290 struct hclge_vport *vport = hclge_get_vport(handle); 7291 struct hclge_dev *hdev = vport->back; 7292 struct hclge_fd_rule *rule; 7293 int ret; 7294 7295 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 7296 dev_err(&hdev->pdev->dev, 7297 "cls flower is not supported\n"); 7298 return -EOPNOTSUPP; 7299 } 7300 7301 ret = hclge_check_cls_flower(hdev, cls_flower, tc); 7302 if (ret) { 7303 dev_err(&hdev->pdev->dev, 7304 "failed to check cls flower params, ret = %d\n", ret); 7305 return ret; 7306 } 7307 7308 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 7309 if (!rule) 7310 return -ENOMEM; 7311 7312 ret = hclge_parse_cls_flower(hdev, cls_flower, rule); 7313 if (ret) { 7314 kfree(rule); 7315 return ret; 7316 } 7317 7318 rule->action = HCLGE_FD_ACTION_SELECT_TC; 7319 rule->cls_flower.tc = tc; 7320 rule->location = cls_flower->common.prio - 1; 7321 rule->vf_id = 0; 7322 rule->cls_flower.cookie = cls_flower->cookie; 7323 rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE; 7324 7325 ret = hclge_add_fd_entry_common(hdev, rule); 7326 if (ret) 7327 kfree(rule); 7328 7329 return ret; 7330 } 7331 7332 static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev, 7333 unsigned long cookie) 7334 { 7335 struct hclge_fd_rule *rule; 7336 struct hlist_node *node; 7337 7338 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7339 if (rule->cls_flower.cookie == cookie) 7340 return rule; 7341 } 7342 7343 return NULL; 7344 } 7345 7346 static int hclge_del_cls_flower(struct hnae3_handle *handle, 7347 struct flow_cls_offload *cls_flower) 7348 { 7349 struct hclge_vport *vport = hclge_get_vport(handle); 7350 struct hclge_dev *hdev = vport->back; 7351 struct hclge_fd_rule *rule; 7352 int ret; 7353 7354 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7355 return -EOPNOTSUPP; 7356 7357 spin_lock_bh(&hdev->fd_rule_lock); 7358 7359 rule = hclge_find_cls_flower(hdev, cls_flower->cookie); 7360 if (!rule) { 7361 spin_unlock_bh(&hdev->fd_rule_lock); 7362 return -EINVAL; 7363 } 7364 7365 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location, 7366 NULL, false); 7367 if (ret) { 7368 /* if tcam config fail, set rule state to TO_DEL, 7369 * so the rule will be deleted when periodic 7370 * task being scheduled. 7371 */ 7372 hclge_update_fd_list(hdev, HCLGE_FD_TO_DEL, rule->location, NULL); 7373 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7374 spin_unlock_bh(&hdev->fd_rule_lock); 7375 return ret; 7376 } 7377 7378 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL); 7379 spin_unlock_bh(&hdev->fd_rule_lock); 7380 7381 return 0; 7382 } 7383 7384 static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist) 7385 { 7386 struct hclge_fd_rule *rule; 7387 struct hlist_node *node; 7388 int ret = 0; 7389 7390 if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state)) 7391 return; 7392 7393 spin_lock_bh(&hdev->fd_rule_lock); 7394 7395 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 7396 switch (rule->state) { 7397 case HCLGE_FD_TO_ADD: 7398 ret = hclge_fd_config_rule(hdev, rule); 7399 if (ret) 7400 goto out; 7401 rule->state = HCLGE_FD_ACTIVE; 7402 break; 7403 case HCLGE_FD_TO_DEL: 7404 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7405 rule->location, NULL, false); 7406 if (ret) 7407 goto out; 7408 hclge_fd_dec_rule_cnt(hdev, rule->location); 7409 hclge_fd_free_node(hdev, rule); 7410 break; 7411 default: 7412 break; 7413 } 7414 } 7415 7416 out: 7417 if (ret) 7418 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7419 7420 spin_unlock_bh(&hdev->fd_rule_lock); 7421 } 7422 7423 static void hclge_sync_fd_table(struct hclge_dev *hdev) 7424 { 7425 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7426 return; 7427 7428 if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) { 7429 bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE; 7430 7431 hclge_clear_fd_rules_in_list(hdev, clear_list); 7432 } 7433 7434 hclge_sync_fd_user_def_cfg(hdev, false); 7435 7436 hclge_sync_fd_list(hdev, &hdev->fd_rule_list); 7437 } 7438 7439 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle) 7440 { 7441 struct hclge_vport *vport = hclge_get_vport(handle); 7442 struct hclge_dev *hdev = vport->back; 7443 7444 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) || 7445 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING); 7446 } 7447 7448 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle) 7449 { 7450 struct hclge_vport *vport = hclge_get_vport(handle); 7451 struct hclge_dev *hdev = vport->back; 7452 7453 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 7454 } 7455 7456 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle) 7457 { 7458 struct hclge_vport *vport = hclge_get_vport(handle); 7459 struct hclge_dev *hdev = vport->back; 7460 7461 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 7462 } 7463 7464 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle) 7465 { 7466 struct hclge_vport *vport = hclge_get_vport(handle); 7467 struct hclge_dev *hdev = vport->back; 7468 7469 return hdev->rst_stats.hw_reset_done_cnt; 7470 } 7471 7472 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable) 7473 { 7474 struct hclge_vport *vport = hclge_get_vport(handle); 7475 struct hclge_dev *hdev = vport->back; 7476 7477 hdev->fd_en = enable; 7478 7479 if (!enable) 7480 set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state); 7481 else 7482 hclge_restore_fd_entries(handle); 7483 7484 hclge_task_schedule(hdev, 0); 7485 } 7486 7487 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 7488 { 7489 #define HCLGE_LINK_STATUS_WAIT_CNT 3 7490 7491 struct hclge_desc desc; 7492 struct hclge_config_mac_mode_cmd *req = 7493 (struct hclge_config_mac_mode_cmd *)desc.data; 7494 u32 loop_en = 0; 7495 int ret; 7496 7497 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 7498 7499 if (enable) { 7500 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U); 7501 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U); 7502 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U); 7503 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U); 7504 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U); 7505 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U); 7506 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U); 7507 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U); 7508 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U); 7509 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U); 7510 } 7511 7512 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7513 7514 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7515 if (ret) { 7516 dev_err(&hdev->pdev->dev, 7517 "mac enable fail, ret =%d.\n", ret); 7518 return; 7519 } 7520 7521 if (!enable) 7522 hclge_mac_link_status_wait(hdev, HCLGE_LINK_STATUS_DOWN, 7523 HCLGE_LINK_STATUS_WAIT_CNT); 7524 } 7525 7526 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid, 7527 u8 switch_param, u8 param_mask) 7528 { 7529 struct hclge_mac_vlan_switch_cmd *req; 7530 struct hclge_desc desc; 7531 u32 func_id; 7532 int ret; 7533 7534 func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0); 7535 req = (struct hclge_mac_vlan_switch_cmd *)desc.data; 7536 7537 /* read current config parameter */ 7538 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM, 7539 true); 7540 req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL; 7541 req->func_id = cpu_to_le32(func_id); 7542 7543 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7544 if (ret) { 7545 dev_err(&hdev->pdev->dev, 7546 "read mac vlan switch parameter fail, ret = %d\n", ret); 7547 return ret; 7548 } 7549 7550 /* modify and write new config parameter */ 7551 hclge_comm_cmd_reuse_desc(&desc, false); 7552 req->switch_param = (req->switch_param & param_mask) | switch_param; 7553 req->param_mask = param_mask; 7554 7555 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7556 if (ret) 7557 dev_err(&hdev->pdev->dev, 7558 "set mac vlan switch parameter fail, ret = %d\n", ret); 7559 return ret; 7560 } 7561 7562 static void hclge_phy_link_status_wait(struct hclge_dev *hdev, 7563 int link_ret) 7564 { 7565 #define HCLGE_PHY_LINK_STATUS_NUM 200 7566 7567 struct phy_device *phydev = hdev->hw.mac.phydev; 7568 int i = 0; 7569 int ret; 7570 7571 do { 7572 ret = phy_read_status(phydev); 7573 if (ret) { 7574 dev_err(&hdev->pdev->dev, 7575 "phy update link status fail, ret = %d\n", ret); 7576 return; 7577 } 7578 7579 if (phydev->link == link_ret) 7580 break; 7581 7582 msleep(HCLGE_LINK_STATUS_MS); 7583 } while (++i < HCLGE_PHY_LINK_STATUS_NUM); 7584 } 7585 7586 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 7587 int wait_cnt) 7588 { 7589 int link_status; 7590 int i = 0; 7591 int ret; 7592 7593 do { 7594 ret = hclge_get_mac_link_status(hdev, &link_status); 7595 if (ret) 7596 return ret; 7597 if (link_status == link_ret) 7598 return 0; 7599 7600 msleep(HCLGE_LINK_STATUS_MS); 7601 } while (++i < wait_cnt); 7602 return -EBUSY; 7603 } 7604 7605 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en, 7606 bool is_phy) 7607 { 7608 #define HCLGE_MAC_LINK_STATUS_NUM 100 7609 7610 int link_ret; 7611 7612 link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 7613 7614 if (is_phy) 7615 hclge_phy_link_status_wait(hdev, link_ret); 7616 7617 return hclge_mac_link_status_wait(hdev, link_ret, 7618 HCLGE_MAC_LINK_STATUS_NUM); 7619 } 7620 7621 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) 7622 { 7623 struct hclge_config_mac_mode_cmd *req; 7624 struct hclge_desc desc; 7625 u32 loop_en; 7626 int ret; 7627 7628 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 7629 /* 1 Read out the MAC mode config at first */ 7630 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 7631 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7632 if (ret) { 7633 dev_err(&hdev->pdev->dev, 7634 "mac loopback get fail, ret =%d.\n", ret); 7635 return ret; 7636 } 7637 7638 /* 2 Then setup the loopback flag */ 7639 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 7640 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 7641 7642 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7643 7644 /* 3 Config mac work mode with loopback flag 7645 * and its original configure parameters 7646 */ 7647 hclge_comm_cmd_reuse_desc(&desc, false); 7648 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7649 if (ret) 7650 dev_err(&hdev->pdev->dev, 7651 "mac loopback set fail, ret =%d.\n", ret); 7652 return ret; 7653 } 7654 7655 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en, 7656 enum hnae3_loop loop_mode) 7657 { 7658 struct hclge_common_lb_cmd *req; 7659 struct hclge_desc desc; 7660 u8 loop_mode_b; 7661 int ret; 7662 7663 req = (struct hclge_common_lb_cmd *)desc.data; 7664 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false); 7665 7666 switch (loop_mode) { 7667 case HNAE3_LOOP_SERIAL_SERDES: 7668 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 7669 break; 7670 case HNAE3_LOOP_PARALLEL_SERDES: 7671 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B; 7672 break; 7673 case HNAE3_LOOP_PHY: 7674 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B; 7675 break; 7676 default: 7677 dev_err(&hdev->pdev->dev, 7678 "unsupported loopback mode %d\n", loop_mode); 7679 return -ENOTSUPP; 7680 } 7681 7682 req->mask = loop_mode_b; 7683 if (en) 7684 req->enable = loop_mode_b; 7685 7686 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7687 if (ret) 7688 dev_err(&hdev->pdev->dev, 7689 "failed to send loopback cmd, loop_mode = %d, ret = %d\n", 7690 loop_mode, ret); 7691 7692 return ret; 7693 } 7694 7695 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev) 7696 { 7697 #define HCLGE_COMMON_LB_RETRY_MS 10 7698 #define HCLGE_COMMON_LB_RETRY_NUM 100 7699 7700 struct hclge_common_lb_cmd *req; 7701 struct hclge_desc desc; 7702 u32 i = 0; 7703 int ret; 7704 7705 req = (struct hclge_common_lb_cmd *)desc.data; 7706 7707 do { 7708 msleep(HCLGE_COMMON_LB_RETRY_MS); 7709 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, 7710 true); 7711 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7712 if (ret) { 7713 dev_err(&hdev->pdev->dev, 7714 "failed to get loopback done status, ret = %d\n", 7715 ret); 7716 return ret; 7717 } 7718 } while (++i < HCLGE_COMMON_LB_RETRY_NUM && 7719 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B)); 7720 7721 if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) { 7722 dev_err(&hdev->pdev->dev, "wait loopback timeout\n"); 7723 return -EBUSY; 7724 } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) { 7725 dev_err(&hdev->pdev->dev, "failed to do loopback test\n"); 7726 return -EIO; 7727 } 7728 7729 return 0; 7730 } 7731 7732 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en, 7733 enum hnae3_loop loop_mode) 7734 { 7735 int ret; 7736 7737 ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode); 7738 if (ret) 7739 return ret; 7740 7741 return hclge_cfg_common_loopback_wait(hdev); 7742 } 7743 7744 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en, 7745 enum hnae3_loop loop_mode) 7746 { 7747 int ret; 7748 7749 ret = hclge_cfg_common_loopback(hdev, en, loop_mode); 7750 if (ret) 7751 return ret; 7752 7753 hclge_cfg_mac_mode(hdev, en); 7754 7755 ret = hclge_mac_phy_link_status_wait(hdev, en, false); 7756 if (ret) 7757 dev_err(&hdev->pdev->dev, 7758 "serdes loopback config mac mode timeout\n"); 7759 7760 return ret; 7761 } 7762 7763 static int hclge_enable_phy_loopback(struct hclge_dev *hdev, 7764 struct phy_device *phydev) 7765 { 7766 int ret; 7767 7768 if (!phydev->suspended) { 7769 ret = phy_suspend(phydev); 7770 if (ret) 7771 return ret; 7772 } 7773 7774 ret = phy_resume(phydev); 7775 if (ret) 7776 return ret; 7777 7778 return phy_loopback(phydev, true); 7779 } 7780 7781 static int hclge_disable_phy_loopback(struct hclge_dev *hdev, 7782 struct phy_device *phydev) 7783 { 7784 int ret; 7785 7786 ret = phy_loopback(phydev, false); 7787 if (ret) 7788 return ret; 7789 7790 return phy_suspend(phydev); 7791 } 7792 7793 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en) 7794 { 7795 struct phy_device *phydev = hdev->hw.mac.phydev; 7796 int ret; 7797 7798 if (!phydev) { 7799 if (hnae3_dev_phy_imp_supported(hdev)) 7800 return hclge_set_common_loopback(hdev, en, 7801 HNAE3_LOOP_PHY); 7802 return -ENOTSUPP; 7803 } 7804 7805 if (en) 7806 ret = hclge_enable_phy_loopback(hdev, phydev); 7807 else 7808 ret = hclge_disable_phy_loopback(hdev, phydev); 7809 if (ret) { 7810 dev_err(&hdev->pdev->dev, 7811 "set phy loopback fail, ret = %d\n", ret); 7812 return ret; 7813 } 7814 7815 hclge_cfg_mac_mode(hdev, en); 7816 7817 ret = hclge_mac_phy_link_status_wait(hdev, en, true); 7818 if (ret) 7819 dev_err(&hdev->pdev->dev, 7820 "phy loopback config mac mode timeout\n"); 7821 7822 return ret; 7823 } 7824 7825 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id, 7826 u16 stream_id, bool enable) 7827 { 7828 struct hclge_desc desc; 7829 struct hclge_cfg_com_tqp_queue_cmd *req = 7830 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 7831 7832 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 7833 req->tqp_id = cpu_to_le16(tqp_id); 7834 req->stream_id = cpu_to_le16(stream_id); 7835 if (enable) 7836 req->enable |= 1U << HCLGE_TQP_ENABLE_B; 7837 7838 return hclge_cmd_send(&hdev->hw, &desc, 1); 7839 } 7840 7841 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable) 7842 { 7843 struct hclge_vport *vport = hclge_get_vport(handle); 7844 struct hclge_dev *hdev = vport->back; 7845 int ret; 7846 u16 i; 7847 7848 for (i = 0; i < handle->kinfo.num_tqps; i++) { 7849 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable); 7850 if (ret) 7851 return ret; 7852 } 7853 return 0; 7854 } 7855 7856 static int hclge_set_loopback(struct hnae3_handle *handle, 7857 enum hnae3_loop loop_mode, bool en) 7858 { 7859 struct hclge_vport *vport = hclge_get_vport(handle); 7860 struct hclge_dev *hdev = vport->back; 7861 int ret = 0; 7862 7863 /* Loopback can be enabled in three places: SSU, MAC, and serdes. By 7864 * default, SSU loopback is enabled, so if the SMAC and the DMAC are 7865 * the same, the packets are looped back in the SSU. If SSU loopback 7866 * is disabled, packets can reach MAC even if SMAC is the same as DMAC. 7867 */ 7868 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 7869 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B); 7870 7871 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param, 7872 HCLGE_SWITCH_ALW_LPBK_MASK); 7873 if (ret) 7874 return ret; 7875 } 7876 7877 switch (loop_mode) { 7878 case HNAE3_LOOP_APP: 7879 ret = hclge_set_app_loopback(hdev, en); 7880 break; 7881 case HNAE3_LOOP_SERIAL_SERDES: 7882 case HNAE3_LOOP_PARALLEL_SERDES: 7883 ret = hclge_set_common_loopback(hdev, en, loop_mode); 7884 break; 7885 case HNAE3_LOOP_PHY: 7886 ret = hclge_set_phy_loopback(hdev, en); 7887 break; 7888 case HNAE3_LOOP_EXTERNAL: 7889 break; 7890 default: 7891 ret = -ENOTSUPP; 7892 dev_err(&hdev->pdev->dev, 7893 "loop_mode %d is not supported\n", loop_mode); 7894 break; 7895 } 7896 7897 if (ret) 7898 return ret; 7899 7900 ret = hclge_tqp_enable(handle, en); 7901 if (ret) 7902 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n", 7903 en ? "enable" : "disable", ret); 7904 7905 return ret; 7906 } 7907 7908 static int hclge_set_default_loopback(struct hclge_dev *hdev) 7909 { 7910 int ret; 7911 7912 ret = hclge_set_app_loopback(hdev, false); 7913 if (ret) 7914 return ret; 7915 7916 ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES); 7917 if (ret) 7918 return ret; 7919 7920 return hclge_cfg_common_loopback(hdev, false, 7921 HNAE3_LOOP_PARALLEL_SERDES); 7922 } 7923 7924 static void hclge_flush_link_update(struct hclge_dev *hdev) 7925 { 7926 #define HCLGE_FLUSH_LINK_TIMEOUT 100000 7927 7928 unsigned long last = hdev->serv_processed_cnt; 7929 int i = 0; 7930 7931 while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) && 7932 i++ < HCLGE_FLUSH_LINK_TIMEOUT && 7933 last == hdev->serv_processed_cnt) 7934 usleep_range(1, 1); 7935 } 7936 7937 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable) 7938 { 7939 struct hclge_vport *vport = hclge_get_vport(handle); 7940 struct hclge_dev *hdev = vport->back; 7941 7942 if (enable) { 7943 hclge_task_schedule(hdev, 0); 7944 } else { 7945 /* Set the DOWN flag here to disable link updating */ 7946 set_bit(HCLGE_STATE_DOWN, &hdev->state); 7947 7948 smp_mb__after_atomic(); /* flush memory to make sure DOWN is seen by service task */ 7949 hclge_flush_link_update(hdev); 7950 } 7951 } 7952 7953 static int hclge_ae_start(struct hnae3_handle *handle) 7954 { 7955 struct hclge_vport *vport = hclge_get_vport(handle); 7956 struct hclge_dev *hdev = vport->back; 7957 7958 /* mac enable */ 7959 hclge_cfg_mac_mode(hdev, true); 7960 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 7961 hdev->hw.mac.link = 0; 7962 7963 /* reset tqp stats */ 7964 hclge_comm_reset_tqp_stats(handle); 7965 7966 hclge_mac_start_phy(hdev); 7967 7968 return 0; 7969 } 7970 7971 static void hclge_ae_stop(struct hnae3_handle *handle) 7972 { 7973 struct hclge_vport *vport = hclge_get_vport(handle); 7974 struct hclge_dev *hdev = vport->back; 7975 7976 set_bit(HCLGE_STATE_DOWN, &hdev->state); 7977 spin_lock_bh(&hdev->fd_rule_lock); 7978 hclge_clear_arfs_rules(hdev); 7979 spin_unlock_bh(&hdev->fd_rule_lock); 7980 7981 /* If it is not PF reset or FLR, the firmware will disable the MAC, 7982 * so it only need to stop phy here. 7983 */ 7984 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { 7985 hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE, 7986 HCLGE_PFC_DISABLE); 7987 if (hdev->reset_type != HNAE3_FUNC_RESET && 7988 hdev->reset_type != HNAE3_FLR_RESET) { 7989 hclge_mac_stop_phy(hdev); 7990 hclge_update_link_status(hdev); 7991 return; 7992 } 7993 } 7994 7995 hclge_reset_tqp(handle); 7996 7997 hclge_config_mac_tnl_int(hdev, false); 7998 7999 /* Mac disable */ 8000 hclge_cfg_mac_mode(hdev, false); 8001 8002 hclge_mac_stop_phy(hdev); 8003 8004 /* reset tqp stats */ 8005 hclge_comm_reset_tqp_stats(handle); 8006 hclge_update_link_status(hdev); 8007 } 8008 8009 int hclge_vport_start(struct hclge_vport *vport) 8010 { 8011 struct hclge_dev *hdev = vport->back; 8012 8013 set_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8014 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8015 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 8016 vport->last_active_jiffies = jiffies; 8017 vport->need_notify = 0; 8018 8019 if (test_bit(vport->vport_id, hdev->vport_config_block)) { 8020 if (vport->vport_id) { 8021 hclge_restore_mac_table_common(vport); 8022 hclge_restore_vport_vlan_table(vport); 8023 } else { 8024 hclge_restore_hw_table(hdev); 8025 } 8026 } 8027 8028 clear_bit(vport->vport_id, hdev->vport_config_block); 8029 8030 return 0; 8031 } 8032 8033 void hclge_vport_stop(struct hclge_vport *vport) 8034 { 8035 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8036 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8037 vport->need_notify = 0; 8038 } 8039 8040 static int hclge_client_start(struct hnae3_handle *handle) 8041 { 8042 struct hclge_vport *vport = hclge_get_vport(handle); 8043 8044 return hclge_vport_start(vport); 8045 } 8046 8047 static void hclge_client_stop(struct hnae3_handle *handle) 8048 { 8049 struct hclge_vport *vport = hclge_get_vport(handle); 8050 8051 hclge_vport_stop(vport); 8052 } 8053 8054 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 8055 u16 cmdq_resp, u8 resp_code, 8056 enum hclge_mac_vlan_tbl_opcode op) 8057 { 8058 struct hclge_dev *hdev = vport->back; 8059 8060 if (cmdq_resp) { 8061 dev_err(&hdev->pdev->dev, 8062 "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n", 8063 cmdq_resp); 8064 return -EIO; 8065 } 8066 8067 if (op == HCLGE_MAC_VLAN_ADD) { 8068 if (!resp_code || resp_code == 1) 8069 return 0; 8070 else if (resp_code == HCLGE_ADD_UC_OVERFLOW || 8071 resp_code == HCLGE_ADD_MC_OVERFLOW) 8072 return -ENOSPC; 8073 8074 dev_err(&hdev->pdev->dev, 8075 "add mac addr failed for undefined, code=%u.\n", 8076 resp_code); 8077 return -EIO; 8078 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 8079 if (!resp_code) { 8080 return 0; 8081 } else if (resp_code == 1) { 8082 dev_dbg(&hdev->pdev->dev, 8083 "remove mac addr failed for miss.\n"); 8084 return -ENOENT; 8085 } 8086 8087 dev_err(&hdev->pdev->dev, 8088 "remove mac addr failed for undefined, code=%u.\n", 8089 resp_code); 8090 return -EIO; 8091 } else if (op == HCLGE_MAC_VLAN_LKUP) { 8092 if (!resp_code) { 8093 return 0; 8094 } else if (resp_code == 1) { 8095 dev_dbg(&hdev->pdev->dev, 8096 "lookup mac addr failed for miss.\n"); 8097 return -ENOENT; 8098 } 8099 8100 dev_err(&hdev->pdev->dev, 8101 "lookup mac addr failed for undefined, code=%u.\n", 8102 resp_code); 8103 return -EIO; 8104 } 8105 8106 dev_err(&hdev->pdev->dev, 8107 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op); 8108 8109 return -EINVAL; 8110 } 8111 8112 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 8113 { 8114 #define HCLGE_VF_NUM_IN_FIRST_DESC 192 8115 8116 unsigned int word_num; 8117 unsigned int bit_num; 8118 8119 if (vfid > 255 || vfid < 0) 8120 return -EIO; 8121 8122 if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) { 8123 word_num = vfid / 32; 8124 bit_num = vfid % 32; 8125 if (clr) 8126 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8127 else 8128 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 8129 } else { 8130 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32; 8131 bit_num = vfid % 32; 8132 if (clr) 8133 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8134 else 8135 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 8136 } 8137 8138 return 0; 8139 } 8140 8141 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 8142 { 8143 #define HCLGE_DESC_NUMBER 3 8144 #define HCLGE_FUNC_NUMBER_PER_DESC 6 8145 int i, j; 8146 8147 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 8148 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 8149 if (desc[i].data[j]) 8150 return false; 8151 8152 return true; 8153 } 8154 8155 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 8156 const u8 *addr, bool is_mc) 8157 { 8158 const unsigned char *mac_addr = addr; 8159 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 8160 (mac_addr[0]) | (mac_addr[1] << 8); 8161 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 8162 8163 hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8164 if (is_mc) { 8165 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 8166 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8167 } 8168 8169 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 8170 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 8171 } 8172 8173 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 8174 struct hclge_mac_vlan_tbl_entry_cmd *req) 8175 { 8176 struct hclge_dev *hdev = vport->back; 8177 struct hclge_desc desc; 8178 u8 resp_code; 8179 u16 retval; 8180 int ret; 8181 8182 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 8183 8184 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8185 8186 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8187 if (ret) { 8188 dev_err(&hdev->pdev->dev, 8189 "del mac addr failed for cmd_send, ret =%d.\n", 8190 ret); 8191 return ret; 8192 } 8193 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8194 retval = le16_to_cpu(desc.retval); 8195 8196 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8197 HCLGE_MAC_VLAN_REMOVE); 8198 } 8199 8200 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 8201 struct hclge_mac_vlan_tbl_entry_cmd *req, 8202 struct hclge_desc *desc, 8203 bool is_mc) 8204 { 8205 struct hclge_dev *hdev = vport->back; 8206 u8 resp_code; 8207 u16 retval; 8208 int ret; 8209 8210 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 8211 if (is_mc) { 8212 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8213 memcpy(desc[0].data, 8214 req, 8215 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8216 hclge_cmd_setup_basic_desc(&desc[1], 8217 HCLGE_OPC_MAC_VLAN_ADD, 8218 true); 8219 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8220 hclge_cmd_setup_basic_desc(&desc[2], 8221 HCLGE_OPC_MAC_VLAN_ADD, 8222 true); 8223 ret = hclge_cmd_send(&hdev->hw, desc, 3); 8224 } else { 8225 memcpy(desc[0].data, 8226 req, 8227 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8228 ret = hclge_cmd_send(&hdev->hw, desc, 1); 8229 } 8230 if (ret) { 8231 dev_err(&hdev->pdev->dev, 8232 "lookup mac addr failed for cmd_send, ret =%d.\n", 8233 ret); 8234 return ret; 8235 } 8236 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 8237 retval = le16_to_cpu(desc[0].retval); 8238 8239 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8240 HCLGE_MAC_VLAN_LKUP); 8241 } 8242 8243 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 8244 struct hclge_mac_vlan_tbl_entry_cmd *req, 8245 struct hclge_desc *mc_desc) 8246 { 8247 struct hclge_dev *hdev = vport->back; 8248 int cfg_status; 8249 u8 resp_code; 8250 u16 retval; 8251 int ret; 8252 8253 if (!mc_desc) { 8254 struct hclge_desc desc; 8255 8256 hclge_cmd_setup_basic_desc(&desc, 8257 HCLGE_OPC_MAC_VLAN_ADD, 8258 false); 8259 memcpy(desc.data, req, 8260 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8261 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8262 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8263 retval = le16_to_cpu(desc.retval); 8264 8265 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8266 resp_code, 8267 HCLGE_MAC_VLAN_ADD); 8268 } else { 8269 hclge_comm_cmd_reuse_desc(&mc_desc[0], false); 8270 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8271 hclge_comm_cmd_reuse_desc(&mc_desc[1], false); 8272 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8273 hclge_comm_cmd_reuse_desc(&mc_desc[2], false); 8274 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT); 8275 memcpy(mc_desc[0].data, req, 8276 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8277 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 8278 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 8279 retval = le16_to_cpu(mc_desc[0].retval); 8280 8281 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8282 resp_code, 8283 HCLGE_MAC_VLAN_ADD); 8284 } 8285 8286 if (ret) { 8287 dev_err(&hdev->pdev->dev, 8288 "add mac addr failed for cmd_send, ret =%d.\n", 8289 ret); 8290 return ret; 8291 } 8292 8293 return cfg_status; 8294 } 8295 8296 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 8297 u16 *allocated_size) 8298 { 8299 struct hclge_umv_spc_alc_cmd *req; 8300 struct hclge_desc desc; 8301 int ret; 8302 8303 req = (struct hclge_umv_spc_alc_cmd *)desc.data; 8304 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false); 8305 8306 req->space_size = cpu_to_le32(space_size); 8307 8308 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8309 if (ret) { 8310 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n", 8311 ret); 8312 return ret; 8313 } 8314 8315 *allocated_size = le32_to_cpu(desc.data[1]); 8316 8317 return 0; 8318 } 8319 8320 static int hclge_init_umv_space(struct hclge_dev *hdev) 8321 { 8322 u16 allocated_size = 0; 8323 int ret; 8324 8325 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size); 8326 if (ret) 8327 return ret; 8328 8329 if (allocated_size < hdev->wanted_umv_size) 8330 dev_warn(&hdev->pdev->dev, 8331 "failed to alloc umv space, want %u, get %u\n", 8332 hdev->wanted_umv_size, allocated_size); 8333 8334 hdev->max_umv_size = allocated_size; 8335 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1); 8336 hdev->share_umv_size = hdev->priv_umv_size + 8337 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8338 8339 if (hdev->ae_dev->dev_specs.mc_mac_size) 8340 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps); 8341 8342 return 0; 8343 } 8344 8345 static void hclge_reset_umv_space(struct hclge_dev *hdev) 8346 { 8347 struct hclge_vport *vport; 8348 int i; 8349 8350 for (i = 0; i < hdev->num_alloc_vport; i++) { 8351 vport = &hdev->vport[i]; 8352 vport->used_umv_num = 0; 8353 } 8354 8355 mutex_lock(&hdev->vport_lock); 8356 hdev->share_umv_size = hdev->priv_umv_size + 8357 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8358 mutex_unlock(&hdev->vport_lock); 8359 8360 hdev->used_mc_mac_num = 0; 8361 } 8362 8363 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock) 8364 { 8365 struct hclge_dev *hdev = vport->back; 8366 bool is_full; 8367 8368 if (need_lock) 8369 mutex_lock(&hdev->vport_lock); 8370 8371 is_full = (vport->used_umv_num >= hdev->priv_umv_size && 8372 hdev->share_umv_size == 0); 8373 8374 if (need_lock) 8375 mutex_unlock(&hdev->vport_lock); 8376 8377 return is_full; 8378 } 8379 8380 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free) 8381 { 8382 struct hclge_dev *hdev = vport->back; 8383 8384 if (is_free) { 8385 if (vport->used_umv_num > hdev->priv_umv_size) 8386 hdev->share_umv_size++; 8387 8388 if (vport->used_umv_num > 0) 8389 vport->used_umv_num--; 8390 } else { 8391 if (vport->used_umv_num >= hdev->priv_umv_size && 8392 hdev->share_umv_size > 0) 8393 hdev->share_umv_size--; 8394 vport->used_umv_num++; 8395 } 8396 } 8397 8398 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list, 8399 const u8 *mac_addr) 8400 { 8401 struct hclge_mac_node *mac_node, *tmp; 8402 8403 list_for_each_entry_safe(mac_node, tmp, list, node) 8404 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 8405 return mac_node; 8406 8407 return NULL; 8408 } 8409 8410 static void hclge_update_mac_node(struct hclge_mac_node *mac_node, 8411 enum HCLGE_MAC_NODE_STATE state) 8412 { 8413 switch (state) { 8414 /* from set_rx_mode or tmp_add_list */ 8415 case HCLGE_MAC_TO_ADD: 8416 if (mac_node->state == HCLGE_MAC_TO_DEL) 8417 mac_node->state = HCLGE_MAC_ACTIVE; 8418 break; 8419 /* only from set_rx_mode */ 8420 case HCLGE_MAC_TO_DEL: 8421 if (mac_node->state == HCLGE_MAC_TO_ADD) { 8422 list_del(&mac_node->node); 8423 kfree(mac_node); 8424 } else { 8425 mac_node->state = HCLGE_MAC_TO_DEL; 8426 } 8427 break; 8428 /* only from tmp_add_list, the mac_node->state won't be 8429 * ACTIVE. 8430 */ 8431 case HCLGE_MAC_ACTIVE: 8432 if (mac_node->state == HCLGE_MAC_TO_ADD) 8433 mac_node->state = HCLGE_MAC_ACTIVE; 8434 8435 break; 8436 } 8437 } 8438 8439 int hclge_update_mac_list(struct hclge_vport *vport, 8440 enum HCLGE_MAC_NODE_STATE state, 8441 enum HCLGE_MAC_ADDR_TYPE mac_type, 8442 const unsigned char *addr) 8443 { 8444 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8445 struct hclge_dev *hdev = vport->back; 8446 struct hclge_mac_node *mac_node; 8447 struct list_head *list; 8448 8449 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8450 &vport->uc_mac_list : &vport->mc_mac_list; 8451 8452 spin_lock_bh(&vport->mac_list_lock); 8453 8454 /* if the mac addr is already in the mac list, no need to add a new 8455 * one into it, just check the mac addr state, convert it to a new 8456 * state, or just remove it, or do nothing. 8457 */ 8458 mac_node = hclge_find_mac_node(list, addr); 8459 if (mac_node) { 8460 hclge_update_mac_node(mac_node, state); 8461 spin_unlock_bh(&vport->mac_list_lock); 8462 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8463 return 0; 8464 } 8465 8466 /* if this address is never added, unnecessary to delete */ 8467 if (state == HCLGE_MAC_TO_DEL) { 8468 spin_unlock_bh(&vport->mac_list_lock); 8469 hnae3_format_mac_addr(format_mac_addr, addr); 8470 dev_err(&hdev->pdev->dev, 8471 "failed to delete address %s from mac list\n", 8472 format_mac_addr); 8473 return -ENOENT; 8474 } 8475 8476 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 8477 if (!mac_node) { 8478 spin_unlock_bh(&vport->mac_list_lock); 8479 return -ENOMEM; 8480 } 8481 8482 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8483 8484 mac_node->state = state; 8485 ether_addr_copy(mac_node->mac_addr, addr); 8486 list_add_tail(&mac_node->node, list); 8487 8488 spin_unlock_bh(&vport->mac_list_lock); 8489 8490 return 0; 8491 } 8492 8493 static int hclge_add_uc_addr(struct hnae3_handle *handle, 8494 const unsigned char *addr) 8495 { 8496 struct hclge_vport *vport = hclge_get_vport(handle); 8497 8498 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC, 8499 addr); 8500 } 8501 8502 int hclge_add_uc_addr_common(struct hclge_vport *vport, 8503 const unsigned char *addr) 8504 { 8505 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8506 struct hclge_dev *hdev = vport->back; 8507 struct hclge_mac_vlan_tbl_entry_cmd req; 8508 struct hclge_desc desc; 8509 u16 egress_port = 0; 8510 int ret; 8511 8512 /* mac addr check */ 8513 if (is_zero_ether_addr(addr) || 8514 is_broadcast_ether_addr(addr) || 8515 is_multicast_ether_addr(addr)) { 8516 hnae3_format_mac_addr(format_mac_addr, addr); 8517 dev_err(&hdev->pdev->dev, 8518 "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n", 8519 format_mac_addr, is_zero_ether_addr(addr), 8520 is_broadcast_ether_addr(addr), 8521 is_multicast_ether_addr(addr)); 8522 return -EINVAL; 8523 } 8524 8525 memset(&req, 0, sizeof(req)); 8526 8527 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 8528 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 8529 8530 req.egress_port = cpu_to_le16(egress_port); 8531 8532 hclge_prepare_mac_addr(&req, addr, false); 8533 8534 /* Lookup the mac address in the mac_vlan table, and add 8535 * it if the entry is inexistent. Repeated unicast entry 8536 * is not allowed in the mac vlan table. 8537 */ 8538 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 8539 if (ret == -ENOENT) { 8540 mutex_lock(&hdev->vport_lock); 8541 if (!hclge_is_umv_space_full(vport, false)) { 8542 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL); 8543 if (!ret) 8544 hclge_update_umv_space(vport, false); 8545 mutex_unlock(&hdev->vport_lock); 8546 return ret; 8547 } 8548 mutex_unlock(&hdev->vport_lock); 8549 8550 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE)) 8551 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n", 8552 hdev->priv_umv_size); 8553 8554 return -ENOSPC; 8555 } 8556 8557 /* check if we just hit the duplicate */ 8558 if (!ret) 8559 return -EEXIST; 8560 8561 return ret; 8562 } 8563 8564 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 8565 const unsigned char *addr) 8566 { 8567 struct hclge_vport *vport = hclge_get_vport(handle); 8568 8569 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC, 8570 addr); 8571 } 8572 8573 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 8574 const unsigned char *addr) 8575 { 8576 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8577 struct hclge_dev *hdev = vport->back; 8578 struct hclge_mac_vlan_tbl_entry_cmd req; 8579 int ret; 8580 8581 /* mac addr check */ 8582 if (is_zero_ether_addr(addr) || 8583 is_broadcast_ether_addr(addr) || 8584 is_multicast_ether_addr(addr)) { 8585 hnae3_format_mac_addr(format_mac_addr, addr); 8586 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n", 8587 format_mac_addr); 8588 return -EINVAL; 8589 } 8590 8591 memset(&req, 0, sizeof(req)); 8592 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 8593 hclge_prepare_mac_addr(&req, addr, false); 8594 ret = hclge_remove_mac_vlan_tbl(vport, &req); 8595 if (!ret || ret == -ENOENT) { 8596 mutex_lock(&hdev->vport_lock); 8597 hclge_update_umv_space(vport, true); 8598 mutex_unlock(&hdev->vport_lock); 8599 return 0; 8600 } 8601 8602 return ret; 8603 } 8604 8605 static int hclge_add_mc_addr(struct hnae3_handle *handle, 8606 const unsigned char *addr) 8607 { 8608 struct hclge_vport *vport = hclge_get_vport(handle); 8609 8610 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC, 8611 addr); 8612 } 8613 8614 int hclge_add_mc_addr_common(struct hclge_vport *vport, 8615 const unsigned char *addr) 8616 { 8617 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8618 struct hclge_dev *hdev = vport->back; 8619 struct hclge_mac_vlan_tbl_entry_cmd req; 8620 struct hclge_desc desc[3]; 8621 bool is_new_addr = false; 8622 int status; 8623 8624 /* mac addr check */ 8625 if (!is_multicast_ether_addr(addr)) { 8626 hnae3_format_mac_addr(format_mac_addr, addr); 8627 dev_err(&hdev->pdev->dev, 8628 "Add mc mac err! invalid mac:%s.\n", 8629 format_mac_addr); 8630 return -EINVAL; 8631 } 8632 memset(&req, 0, sizeof(req)); 8633 hclge_prepare_mac_addr(&req, addr, true); 8634 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8635 if (status) { 8636 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) && 8637 hdev->used_mc_mac_num >= 8638 hdev->ae_dev->dev_specs.mc_mac_size) 8639 goto err_no_space; 8640 8641 is_new_addr = true; 8642 8643 /* This mac addr do not exist, add new entry for it */ 8644 memset(desc[0].data, 0, sizeof(desc[0].data)); 8645 memset(desc[1].data, 0, sizeof(desc[0].data)); 8646 memset(desc[2].data, 0, sizeof(desc[0].data)); 8647 } 8648 status = hclge_update_desc_vfid(desc, vport->vport_id, false); 8649 if (status) 8650 return status; 8651 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8652 if (status == -ENOSPC) 8653 goto err_no_space; 8654 else if (!status && is_new_addr) 8655 hdev->used_mc_mac_num++; 8656 8657 return status; 8658 8659 err_no_space: 8660 /* if already overflow, not to print each time */ 8661 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) { 8662 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8663 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n"); 8664 } 8665 8666 return -ENOSPC; 8667 } 8668 8669 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 8670 const unsigned char *addr) 8671 { 8672 struct hclge_vport *vport = hclge_get_vport(handle); 8673 8674 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC, 8675 addr); 8676 } 8677 8678 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 8679 const unsigned char *addr) 8680 { 8681 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8682 struct hclge_dev *hdev = vport->back; 8683 struct hclge_mac_vlan_tbl_entry_cmd req; 8684 enum hclge_comm_cmd_status status; 8685 struct hclge_desc desc[3]; 8686 8687 /* mac addr check */ 8688 if (!is_multicast_ether_addr(addr)) { 8689 hnae3_format_mac_addr(format_mac_addr, addr); 8690 dev_dbg(&hdev->pdev->dev, 8691 "Remove mc mac err! invalid mac:%s.\n", 8692 format_mac_addr); 8693 return -EINVAL; 8694 } 8695 8696 memset(&req, 0, sizeof(req)); 8697 hclge_prepare_mac_addr(&req, addr, true); 8698 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8699 if (!status) { 8700 /* This mac addr exist, remove this handle's VFID for it */ 8701 status = hclge_update_desc_vfid(desc, vport->vport_id, true); 8702 if (status) 8703 return status; 8704 8705 if (hclge_is_all_function_id_zero(desc)) { 8706 /* All the vfid is zero, so need to delete this entry */ 8707 status = hclge_remove_mac_vlan_tbl(vport, &req); 8708 if (!status) 8709 hdev->used_mc_mac_num--; 8710 } else { 8711 /* Not all the vfid is zero, update the vfid */ 8712 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8713 } 8714 } else if (status == -ENOENT) { 8715 status = 0; 8716 } 8717 8718 return status; 8719 } 8720 8721 static void hclge_sync_vport_mac_list(struct hclge_vport *vport, 8722 struct list_head *list, 8723 enum HCLGE_MAC_ADDR_TYPE mac_type) 8724 { 8725 int (*sync)(struct hclge_vport *vport, const unsigned char *addr); 8726 struct hclge_mac_node *mac_node, *tmp; 8727 int ret; 8728 8729 if (mac_type == HCLGE_MAC_ADDR_UC) 8730 sync = hclge_add_uc_addr_common; 8731 else 8732 sync = hclge_add_mc_addr_common; 8733 8734 list_for_each_entry_safe(mac_node, tmp, list, node) { 8735 ret = sync(vport, mac_node->mac_addr); 8736 if (!ret) { 8737 mac_node->state = HCLGE_MAC_ACTIVE; 8738 } else { 8739 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8740 &vport->state); 8741 8742 /* If one unicast mac address is existing in hardware, 8743 * we need to try whether other unicast mac addresses 8744 * are new addresses that can be added. 8745 * Multicast mac address can be reusable, even though 8746 * there is no space to add new multicast mac address, 8747 * we should check whether other mac addresses are 8748 * existing in hardware for reuse. 8749 */ 8750 if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) || 8751 (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC)) 8752 break; 8753 } 8754 } 8755 } 8756 8757 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport, 8758 struct list_head *list, 8759 enum HCLGE_MAC_ADDR_TYPE mac_type) 8760 { 8761 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 8762 struct hclge_mac_node *mac_node, *tmp; 8763 int ret; 8764 8765 if (mac_type == HCLGE_MAC_ADDR_UC) 8766 unsync = hclge_rm_uc_addr_common; 8767 else 8768 unsync = hclge_rm_mc_addr_common; 8769 8770 list_for_each_entry_safe(mac_node, tmp, list, node) { 8771 ret = unsync(vport, mac_node->mac_addr); 8772 if (!ret || ret == -ENOENT) { 8773 list_del(&mac_node->node); 8774 kfree(mac_node); 8775 } else { 8776 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8777 &vport->state); 8778 break; 8779 } 8780 } 8781 } 8782 8783 static bool hclge_sync_from_add_list(struct list_head *add_list, 8784 struct list_head *mac_list) 8785 { 8786 struct hclge_mac_node *mac_node, *tmp, *new_node; 8787 bool all_added = true; 8788 8789 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 8790 if (mac_node->state == HCLGE_MAC_TO_ADD) 8791 all_added = false; 8792 8793 /* if the mac address from tmp_add_list is not in the 8794 * uc/mc_mac_list, it means have received a TO_DEL request 8795 * during the time window of adding the mac address into mac 8796 * table. if mac_node state is ACTIVE, then change it to TO_DEL, 8797 * then it will be removed at next time. else it must be TO_ADD, 8798 * this address hasn't been added into mac table, 8799 * so just remove the mac node. 8800 */ 8801 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8802 if (new_node) { 8803 hclge_update_mac_node(new_node, mac_node->state); 8804 list_del(&mac_node->node); 8805 kfree(mac_node); 8806 } else if (mac_node->state == HCLGE_MAC_ACTIVE) { 8807 mac_node->state = HCLGE_MAC_TO_DEL; 8808 list_move_tail(&mac_node->node, mac_list); 8809 } else { 8810 list_del(&mac_node->node); 8811 kfree(mac_node); 8812 } 8813 } 8814 8815 return all_added; 8816 } 8817 8818 static void hclge_sync_from_del_list(struct list_head *del_list, 8819 struct list_head *mac_list) 8820 { 8821 struct hclge_mac_node *mac_node, *tmp, *new_node; 8822 8823 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 8824 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8825 if (new_node) { 8826 /* If the mac addr exists in the mac list, it means 8827 * received a new TO_ADD request during the time window 8828 * of configuring the mac address. For the mac node 8829 * state is TO_ADD, and the address is already in the 8830 * in the hardware(due to delete fail), so we just need 8831 * to change the mac node state to ACTIVE. 8832 */ 8833 new_node->state = HCLGE_MAC_ACTIVE; 8834 list_del(&mac_node->node); 8835 kfree(mac_node); 8836 } else { 8837 list_move_tail(&mac_node->node, mac_list); 8838 } 8839 } 8840 } 8841 8842 static void hclge_update_overflow_flags(struct hclge_vport *vport, 8843 enum HCLGE_MAC_ADDR_TYPE mac_type, 8844 bool is_all_added) 8845 { 8846 if (mac_type == HCLGE_MAC_ADDR_UC) { 8847 if (is_all_added) 8848 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE; 8849 else if (hclge_is_umv_space_full(vport, true)) 8850 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE; 8851 } else { 8852 if (is_all_added) 8853 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE; 8854 else 8855 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8856 } 8857 } 8858 8859 static void hclge_sync_vport_mac_table(struct hclge_vport *vport, 8860 enum HCLGE_MAC_ADDR_TYPE mac_type) 8861 { 8862 struct hclge_mac_node *mac_node, *tmp, *new_node; 8863 struct list_head tmp_add_list, tmp_del_list; 8864 struct list_head *list; 8865 bool all_added; 8866 8867 INIT_LIST_HEAD(&tmp_add_list); 8868 INIT_LIST_HEAD(&tmp_del_list); 8869 8870 /* move the mac addr to the tmp_add_list and tmp_del_list, then 8871 * we can add/delete these mac addr outside the spin lock 8872 */ 8873 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8874 &vport->uc_mac_list : &vport->mc_mac_list; 8875 8876 spin_lock_bh(&vport->mac_list_lock); 8877 8878 list_for_each_entry_safe(mac_node, tmp, list, node) { 8879 switch (mac_node->state) { 8880 case HCLGE_MAC_TO_DEL: 8881 list_move_tail(&mac_node->node, &tmp_del_list); 8882 break; 8883 case HCLGE_MAC_TO_ADD: 8884 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 8885 if (!new_node) 8886 goto stop_traverse; 8887 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 8888 new_node->state = mac_node->state; 8889 list_add_tail(&new_node->node, &tmp_add_list); 8890 break; 8891 default: 8892 break; 8893 } 8894 } 8895 8896 stop_traverse: 8897 spin_unlock_bh(&vport->mac_list_lock); 8898 8899 /* delete first, in order to get max mac table space for adding */ 8900 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 8901 hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type); 8902 8903 /* if some mac addresses were added/deleted fail, move back to the 8904 * mac_list, and retry at next time. 8905 */ 8906 spin_lock_bh(&vport->mac_list_lock); 8907 8908 hclge_sync_from_del_list(&tmp_del_list, list); 8909 all_added = hclge_sync_from_add_list(&tmp_add_list, list); 8910 8911 spin_unlock_bh(&vport->mac_list_lock); 8912 8913 hclge_update_overflow_flags(vport, mac_type, all_added); 8914 } 8915 8916 static bool hclge_need_sync_mac_table(struct hclge_vport *vport) 8917 { 8918 struct hclge_dev *hdev = vport->back; 8919 8920 if (test_bit(vport->vport_id, hdev->vport_config_block)) 8921 return false; 8922 8923 if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state)) 8924 return true; 8925 8926 return false; 8927 } 8928 8929 static void hclge_sync_mac_table(struct hclge_dev *hdev) 8930 { 8931 int i; 8932 8933 for (i = 0; i < hdev->num_alloc_vport; i++) { 8934 struct hclge_vport *vport = &hdev->vport[i]; 8935 8936 if (!hclge_need_sync_mac_table(vport)) 8937 continue; 8938 8939 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC); 8940 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC); 8941 } 8942 } 8943 8944 static void hclge_build_del_list(struct list_head *list, 8945 bool is_del_list, 8946 struct list_head *tmp_del_list) 8947 { 8948 struct hclge_mac_node *mac_cfg, *tmp; 8949 8950 list_for_each_entry_safe(mac_cfg, tmp, list, node) { 8951 switch (mac_cfg->state) { 8952 case HCLGE_MAC_TO_DEL: 8953 case HCLGE_MAC_ACTIVE: 8954 list_move_tail(&mac_cfg->node, tmp_del_list); 8955 break; 8956 case HCLGE_MAC_TO_ADD: 8957 if (is_del_list) { 8958 list_del(&mac_cfg->node); 8959 kfree(mac_cfg); 8960 } 8961 break; 8962 } 8963 } 8964 } 8965 8966 static void hclge_unsync_del_list(struct hclge_vport *vport, 8967 int (*unsync)(struct hclge_vport *vport, 8968 const unsigned char *addr), 8969 bool is_del_list, 8970 struct list_head *tmp_del_list) 8971 { 8972 struct hclge_mac_node *mac_cfg, *tmp; 8973 int ret; 8974 8975 list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) { 8976 ret = unsync(vport, mac_cfg->mac_addr); 8977 if (!ret || ret == -ENOENT) { 8978 /* clear all mac addr from hardware, but remain these 8979 * mac addr in the mac list, and restore them after 8980 * vf reset finished. 8981 */ 8982 if (!is_del_list && 8983 mac_cfg->state == HCLGE_MAC_ACTIVE) { 8984 mac_cfg->state = HCLGE_MAC_TO_ADD; 8985 } else { 8986 list_del(&mac_cfg->node); 8987 kfree(mac_cfg); 8988 } 8989 } else if (is_del_list) { 8990 mac_cfg->state = HCLGE_MAC_TO_DEL; 8991 } 8992 } 8993 } 8994 8995 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 8996 enum HCLGE_MAC_ADDR_TYPE mac_type) 8997 { 8998 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 8999 struct hclge_dev *hdev = vport->back; 9000 struct list_head tmp_del_list, *list; 9001 9002 if (mac_type == HCLGE_MAC_ADDR_UC) { 9003 list = &vport->uc_mac_list; 9004 unsync = hclge_rm_uc_addr_common; 9005 } else { 9006 list = &vport->mc_mac_list; 9007 unsync = hclge_rm_mc_addr_common; 9008 } 9009 9010 INIT_LIST_HEAD(&tmp_del_list); 9011 9012 if (!is_del_list) 9013 set_bit(vport->vport_id, hdev->vport_config_block); 9014 9015 spin_lock_bh(&vport->mac_list_lock); 9016 9017 hclge_build_del_list(list, is_del_list, &tmp_del_list); 9018 9019 spin_unlock_bh(&vport->mac_list_lock); 9020 9021 hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list); 9022 9023 spin_lock_bh(&vport->mac_list_lock); 9024 9025 hclge_sync_from_del_list(&tmp_del_list, list); 9026 9027 spin_unlock_bh(&vport->mac_list_lock); 9028 } 9029 9030 /* remove all mac address when uninitailize */ 9031 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport, 9032 enum HCLGE_MAC_ADDR_TYPE mac_type) 9033 { 9034 struct hclge_mac_node *mac_node, *tmp; 9035 struct hclge_dev *hdev = vport->back; 9036 struct list_head tmp_del_list, *list; 9037 9038 INIT_LIST_HEAD(&tmp_del_list); 9039 9040 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 9041 &vport->uc_mac_list : &vport->mc_mac_list; 9042 9043 spin_lock_bh(&vport->mac_list_lock); 9044 9045 list_for_each_entry_safe(mac_node, tmp, list, node) { 9046 switch (mac_node->state) { 9047 case HCLGE_MAC_TO_DEL: 9048 case HCLGE_MAC_ACTIVE: 9049 list_move_tail(&mac_node->node, &tmp_del_list); 9050 break; 9051 case HCLGE_MAC_TO_ADD: 9052 list_del(&mac_node->node); 9053 kfree(mac_node); 9054 break; 9055 } 9056 } 9057 9058 spin_unlock_bh(&vport->mac_list_lock); 9059 9060 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 9061 9062 if (!list_empty(&tmp_del_list)) 9063 dev_warn(&hdev->pdev->dev, 9064 "uninit %s mac list for vport %u not completely.\n", 9065 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc", 9066 vport->vport_id); 9067 9068 list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) { 9069 list_del(&mac_node->node); 9070 kfree(mac_node); 9071 } 9072 } 9073 9074 static void hclge_uninit_mac_table(struct hclge_dev *hdev) 9075 { 9076 struct hclge_vport *vport; 9077 int i; 9078 9079 for (i = 0; i < hdev->num_alloc_vport; i++) { 9080 vport = &hdev->vport[i]; 9081 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC); 9082 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC); 9083 } 9084 } 9085 9086 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 9087 u16 cmdq_resp, u8 resp_code) 9088 { 9089 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 9090 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 9091 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 9092 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 9093 9094 int return_status; 9095 9096 if (cmdq_resp) { 9097 dev_err(&hdev->pdev->dev, 9098 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 9099 cmdq_resp); 9100 return -EIO; 9101 } 9102 9103 switch (resp_code) { 9104 case HCLGE_ETHERTYPE_SUCCESS_ADD: 9105 case HCLGE_ETHERTYPE_ALREADY_ADD: 9106 return_status = 0; 9107 break; 9108 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 9109 dev_err(&hdev->pdev->dev, 9110 "add mac ethertype failed for manager table overflow.\n"); 9111 return_status = -EIO; 9112 break; 9113 case HCLGE_ETHERTYPE_KEY_CONFLICT: 9114 dev_err(&hdev->pdev->dev, 9115 "add mac ethertype failed for key conflict.\n"); 9116 return_status = -EIO; 9117 break; 9118 default: 9119 dev_err(&hdev->pdev->dev, 9120 "add mac ethertype failed for undefined, code=%u.\n", 9121 resp_code); 9122 return_status = -EIO; 9123 } 9124 9125 return return_status; 9126 } 9127 9128 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf, 9129 u8 *mac_addr) 9130 { 9131 struct hclge_vport *vport = hclge_get_vport(handle); 9132 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9133 struct hclge_dev *hdev = vport->back; 9134 9135 vport = hclge_get_vf_vport(hdev, vf); 9136 if (!vport) 9137 return -EINVAL; 9138 9139 hnae3_format_mac_addr(format_mac_addr, mac_addr); 9140 if (ether_addr_equal(mac_addr, vport->vf_info.mac)) { 9141 dev_info(&hdev->pdev->dev, 9142 "Specified MAC(=%s) is same as before, no change committed!\n", 9143 format_mac_addr); 9144 return 0; 9145 } 9146 9147 ether_addr_copy(vport->vf_info.mac, mac_addr); 9148 9149 /* there is a timewindow for PF to know VF unalive, it may 9150 * cause send mailbox fail, but it doesn't matter, VF will 9151 * query it when reinit. 9152 */ 9153 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) { 9154 dev_info(&hdev->pdev->dev, 9155 "MAC of VF %d has been set to %s, and it will be reinitialized!\n", 9156 vf, format_mac_addr); 9157 (void)hclge_inform_reset_assert_to_vf(vport); 9158 return 0; 9159 } 9160 9161 dev_info(&hdev->pdev->dev, 9162 "MAC of VF %d has been set to %s, will be active after VF reset\n", 9163 vf, format_mac_addr); 9164 return 0; 9165 } 9166 9167 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 9168 const struct hclge_mac_mgr_tbl_entry_cmd *req) 9169 { 9170 struct hclge_desc desc; 9171 u8 resp_code; 9172 u16 retval; 9173 int ret; 9174 9175 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 9176 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 9177 9178 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9179 if (ret) { 9180 dev_err(&hdev->pdev->dev, 9181 "add mac ethertype failed for cmd_send, ret =%d.\n", 9182 ret); 9183 return ret; 9184 } 9185 9186 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 9187 retval = le16_to_cpu(desc.retval); 9188 9189 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 9190 } 9191 9192 static int init_mgr_tbl(struct hclge_dev *hdev) 9193 { 9194 int ret; 9195 int i; 9196 9197 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 9198 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 9199 if (ret) { 9200 dev_err(&hdev->pdev->dev, 9201 "add mac ethertype failed, ret =%d.\n", 9202 ret); 9203 return ret; 9204 } 9205 } 9206 9207 return 0; 9208 } 9209 9210 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 9211 { 9212 struct hclge_vport *vport = hclge_get_vport(handle); 9213 struct hclge_dev *hdev = vport->back; 9214 9215 ether_addr_copy(p, hdev->hw.mac.mac_addr); 9216 } 9217 9218 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 9219 const u8 *old_addr, const u8 *new_addr) 9220 { 9221 struct list_head *list = &vport->uc_mac_list; 9222 struct hclge_mac_node *old_node, *new_node; 9223 9224 new_node = hclge_find_mac_node(list, new_addr); 9225 if (!new_node) { 9226 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 9227 if (!new_node) 9228 return -ENOMEM; 9229 9230 new_node->state = HCLGE_MAC_TO_ADD; 9231 ether_addr_copy(new_node->mac_addr, new_addr); 9232 list_add(&new_node->node, list); 9233 } else { 9234 if (new_node->state == HCLGE_MAC_TO_DEL) 9235 new_node->state = HCLGE_MAC_ACTIVE; 9236 9237 /* make sure the new addr is in the list head, avoid dev 9238 * addr may be not re-added into mac table for the umv space 9239 * limitation after global/imp reset which will clear mac 9240 * table by hardware. 9241 */ 9242 list_move(&new_node->node, list); 9243 } 9244 9245 if (old_addr && !ether_addr_equal(old_addr, new_addr)) { 9246 old_node = hclge_find_mac_node(list, old_addr); 9247 if (old_node) { 9248 if (old_node->state == HCLGE_MAC_TO_ADD) { 9249 list_del(&old_node->node); 9250 kfree(old_node); 9251 } else { 9252 old_node->state = HCLGE_MAC_TO_DEL; 9253 } 9254 } 9255 } 9256 9257 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 9258 9259 return 0; 9260 } 9261 9262 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p, 9263 bool is_first) 9264 { 9265 const unsigned char *new_addr = (const unsigned char *)p; 9266 struct hclge_vport *vport = hclge_get_vport(handle); 9267 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9268 struct hclge_dev *hdev = vport->back; 9269 unsigned char *old_addr = NULL; 9270 int ret; 9271 9272 /* mac addr check */ 9273 if (is_zero_ether_addr(new_addr) || 9274 is_broadcast_ether_addr(new_addr) || 9275 is_multicast_ether_addr(new_addr)) { 9276 hnae3_format_mac_addr(format_mac_addr, new_addr); 9277 dev_err(&hdev->pdev->dev, 9278 "change uc mac err! invalid mac: %s.\n", 9279 format_mac_addr); 9280 return -EINVAL; 9281 } 9282 9283 ret = hclge_pause_addr_cfg(hdev, new_addr); 9284 if (ret) { 9285 dev_err(&hdev->pdev->dev, 9286 "failed to configure mac pause address, ret = %d\n", 9287 ret); 9288 return ret; 9289 } 9290 9291 if (!is_first) 9292 old_addr = hdev->hw.mac.mac_addr; 9293 9294 spin_lock_bh(&vport->mac_list_lock); 9295 ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr); 9296 if (ret) { 9297 hnae3_format_mac_addr(format_mac_addr, new_addr); 9298 dev_err(&hdev->pdev->dev, 9299 "failed to change the mac addr:%s, ret = %d\n", 9300 format_mac_addr, ret); 9301 spin_unlock_bh(&vport->mac_list_lock); 9302 9303 if (!is_first) 9304 hclge_pause_addr_cfg(hdev, old_addr); 9305 9306 return ret; 9307 } 9308 /* we must update dev addr with spin lock protect, preventing dev addr 9309 * being removed by set_rx_mode path. 9310 */ 9311 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 9312 spin_unlock_bh(&vport->mac_list_lock); 9313 9314 hclge_task_schedule(hdev, 0); 9315 9316 return 0; 9317 } 9318 9319 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd) 9320 { 9321 struct mii_ioctl_data *data = if_mii(ifr); 9322 9323 if (!hnae3_dev_phy_imp_supported(hdev)) 9324 return -EOPNOTSUPP; 9325 9326 switch (cmd) { 9327 case SIOCGMIIPHY: 9328 data->phy_id = hdev->hw.mac.phy_addr; 9329 /* this command reads phy id and register at the same time */ 9330 fallthrough; 9331 case SIOCGMIIREG: 9332 data->val_out = hclge_read_phy_reg(hdev, data->reg_num); 9333 return 0; 9334 9335 case SIOCSMIIREG: 9336 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in); 9337 default: 9338 return -EOPNOTSUPP; 9339 } 9340 } 9341 9342 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr, 9343 int cmd) 9344 { 9345 struct hclge_vport *vport = hclge_get_vport(handle); 9346 struct hclge_dev *hdev = vport->back; 9347 9348 switch (cmd) { 9349 case SIOCGHWTSTAMP: 9350 return hclge_ptp_get_cfg(hdev, ifr); 9351 case SIOCSHWTSTAMP: 9352 return hclge_ptp_set_cfg(hdev, ifr); 9353 default: 9354 if (!hdev->hw.mac.phydev) 9355 return hclge_mii_ioctl(hdev, ifr, cmd); 9356 } 9357 9358 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd); 9359 } 9360 9361 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id, 9362 bool bypass_en) 9363 { 9364 struct hclge_port_vlan_filter_bypass_cmd *req; 9365 struct hclge_desc desc; 9366 int ret; 9367 9368 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false); 9369 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 9370 req->vf_id = vf_id; 9371 hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B, 9372 bypass_en ? 1 : 0); 9373 9374 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9375 if (ret) 9376 dev_err(&hdev->pdev->dev, 9377 "failed to set vport%u port vlan filter bypass state, ret = %d.\n", 9378 vf_id, ret); 9379 9380 return ret; 9381 } 9382 9383 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 9384 u8 fe_type, bool filter_en, u8 vf_id) 9385 { 9386 struct hclge_vlan_filter_ctrl_cmd *req; 9387 struct hclge_desc desc; 9388 int ret; 9389 9390 /* read current vlan filter parameter */ 9391 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 9392 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 9393 req->vlan_type = vlan_type; 9394 req->vf_id = vf_id; 9395 9396 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9397 if (ret) { 9398 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n", 9399 vf_id, ret); 9400 return ret; 9401 } 9402 9403 /* modify and write new config parameter */ 9404 hclge_comm_cmd_reuse_desc(&desc, false); 9405 req->vlan_fe = filter_en ? 9406 (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type); 9407 9408 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9409 if (ret) 9410 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n", 9411 vf_id, ret); 9412 9413 return ret; 9414 } 9415 9416 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable) 9417 { 9418 struct hclge_dev *hdev = vport->back; 9419 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 9420 int ret; 9421 9422 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9423 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9424 HCLGE_FILTER_FE_EGRESS_V1_B, 9425 enable, vport->vport_id); 9426 9427 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9428 HCLGE_FILTER_FE_EGRESS, enable, 9429 vport->vport_id); 9430 if (ret) 9431 return ret; 9432 9433 if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) { 9434 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id, 9435 !enable); 9436 } else if (!vport->vport_id) { 9437 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 9438 enable = false; 9439 9440 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9441 HCLGE_FILTER_FE_INGRESS, 9442 enable, 0); 9443 } 9444 9445 return ret; 9446 } 9447 9448 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport) 9449 { 9450 struct hnae3_handle *handle = &vport->nic; 9451 struct hclge_vport_vlan_cfg *vlan, *tmp; 9452 struct hclge_dev *hdev = vport->back; 9453 9454 if (vport->vport_id) { 9455 if (vport->port_base_vlan_cfg.state != 9456 HNAE3_PORT_BASE_VLAN_DISABLE) 9457 return true; 9458 9459 if (vport->vf_info.trusted && vport->vf_info.request_uc_en) 9460 return false; 9461 } else if (handle->netdev_flags & HNAE3_USER_UPE) { 9462 return false; 9463 } 9464 9465 if (!vport->req_vlan_fltr_en) 9466 return false; 9467 9468 /* compatible with former device, always enable vlan filter */ 9469 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 9470 return true; 9471 9472 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) 9473 if (vlan->vlan_id != 0) 9474 return true; 9475 9476 return false; 9477 } 9478 9479 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) 9480 { 9481 struct hclge_dev *hdev = vport->back; 9482 bool need_en; 9483 int ret; 9484 9485 mutex_lock(&hdev->vport_lock); 9486 9487 vport->req_vlan_fltr_en = request_en; 9488 9489 need_en = hclge_need_enable_vport_vlan_filter(vport); 9490 if (need_en == vport->cur_vlan_fltr_en) { 9491 mutex_unlock(&hdev->vport_lock); 9492 return 0; 9493 } 9494 9495 ret = hclge_set_vport_vlan_filter(vport, need_en); 9496 if (ret) { 9497 mutex_unlock(&hdev->vport_lock); 9498 return ret; 9499 } 9500 9501 vport->cur_vlan_fltr_en = need_en; 9502 9503 mutex_unlock(&hdev->vport_lock); 9504 9505 return 0; 9506 } 9507 9508 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 9509 { 9510 struct hclge_vport *vport = hclge_get_vport(handle); 9511 9512 return hclge_enable_vport_vlan_filter(vport, enable); 9513 } 9514 9515 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid, 9516 bool is_kill, u16 vlan, 9517 struct hclge_desc *desc) 9518 { 9519 struct hclge_vlan_filter_vf_cfg_cmd *req0; 9520 struct hclge_vlan_filter_vf_cfg_cmd *req1; 9521 u8 vf_byte_val; 9522 u8 vf_byte_off; 9523 int ret; 9524 9525 hclge_cmd_setup_basic_desc(&desc[0], 9526 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9527 hclge_cmd_setup_basic_desc(&desc[1], 9528 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9529 9530 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 9531 9532 vf_byte_off = vfid / 8; 9533 vf_byte_val = 1 << (vfid % 8); 9534 9535 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9536 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 9537 9538 req0->vlan_id = cpu_to_le16(vlan); 9539 req0->vlan_cfg = is_kill; 9540 9541 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 9542 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 9543 else 9544 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 9545 9546 ret = hclge_cmd_send(&hdev->hw, desc, 2); 9547 if (ret) { 9548 dev_err(&hdev->pdev->dev, 9549 "Send vf vlan command fail, ret =%d.\n", 9550 ret); 9551 return ret; 9552 } 9553 9554 return 0; 9555 } 9556 9557 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid, 9558 bool is_kill, struct hclge_desc *desc) 9559 { 9560 struct hclge_vlan_filter_vf_cfg_cmd *req; 9561 9562 req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9563 9564 if (!is_kill) { 9565 #define HCLGE_VF_VLAN_NO_ENTRY 2 9566 if (!req->resp_code || req->resp_code == 1) 9567 return 0; 9568 9569 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 9570 set_bit(vfid, hdev->vf_vlan_full); 9571 dev_warn(&hdev->pdev->dev, 9572 "vf vlan table is full, vf vlan filter is disabled\n"); 9573 return 0; 9574 } 9575 9576 dev_err(&hdev->pdev->dev, 9577 "Add vf vlan filter fail, ret =%u.\n", 9578 req->resp_code); 9579 } else { 9580 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 9581 if (!req->resp_code) 9582 return 0; 9583 9584 /* vf vlan filter is disabled when vf vlan table is full, 9585 * then new vlan id will not be added into vf vlan table. 9586 * Just return 0 without warning, avoid massive verbose 9587 * print logs when unload. 9588 */ 9589 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) 9590 return 0; 9591 9592 dev_err(&hdev->pdev->dev, 9593 "Kill vf vlan filter fail, ret =%u.\n", 9594 req->resp_code); 9595 } 9596 9597 return -EIO; 9598 } 9599 9600 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid, 9601 bool is_kill, u16 vlan) 9602 { 9603 struct hclge_vport *vport = &hdev->vport[vfid]; 9604 struct hclge_desc desc[2]; 9605 int ret; 9606 9607 /* if vf vlan table is full, firmware will close vf vlan filter, it 9608 * is unable and unnecessary to add new vlan id to vf vlan filter. 9609 * If spoof check is enable, and vf vlan is full, it shouldn't add 9610 * new vlan, because tx packets with these vlan id will be dropped. 9611 */ 9612 if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) { 9613 if (vport->vf_info.spoofchk && vlan) { 9614 dev_err(&hdev->pdev->dev, 9615 "Can't add vlan due to spoof check is on and vf vlan table is full\n"); 9616 return -EPERM; 9617 } 9618 return 0; 9619 } 9620 9621 ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc); 9622 if (ret) 9623 return ret; 9624 9625 return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc); 9626 } 9627 9628 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 9629 u16 vlan_id, bool is_kill) 9630 { 9631 struct hclge_vlan_filter_pf_cfg_cmd *req; 9632 struct hclge_desc desc; 9633 u8 vlan_offset_byte_val; 9634 u8 vlan_offset_byte; 9635 u8 vlan_offset_160; 9636 int ret; 9637 9638 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 9639 9640 vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP; 9641 vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) / 9642 HCLGE_VLAN_BYTE_SIZE; 9643 vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE); 9644 9645 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 9646 req->vlan_offset = vlan_offset_160; 9647 req->vlan_cfg = is_kill; 9648 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 9649 9650 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9651 if (ret) 9652 dev_err(&hdev->pdev->dev, 9653 "port vlan command, send fail, ret =%d.\n", ret); 9654 return ret; 9655 } 9656 9657 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id, 9658 u16 vlan_id, bool is_kill) 9659 { 9660 /* vlan 0 may be added twice when 8021q module is enabled */ 9661 if (!is_kill && !vlan_id && 9662 test_bit(vport_id, hdev->vlan_table[vlan_id])) 9663 return false; 9664 9665 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 9666 dev_warn(&hdev->pdev->dev, 9667 "Add port vlan failed, vport %u is already in vlan %u\n", 9668 vport_id, vlan_id); 9669 return false; 9670 } 9671 9672 if (is_kill && 9673 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 9674 dev_warn(&hdev->pdev->dev, 9675 "Delete port vlan failed, vport %u is not in vlan %u\n", 9676 vport_id, vlan_id); 9677 return false; 9678 } 9679 9680 return true; 9681 } 9682 9683 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 9684 u16 vport_id, u16 vlan_id, 9685 bool is_kill) 9686 { 9687 u16 vport_idx, vport_num = 0; 9688 int ret; 9689 9690 if (is_kill && !vlan_id) 9691 return 0; 9692 9693 if (vlan_id >= VLAN_N_VID) 9694 return -EINVAL; 9695 9696 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id); 9697 if (ret) { 9698 dev_err(&hdev->pdev->dev, 9699 "Set %u vport vlan filter config fail, ret =%d.\n", 9700 vport_id, ret); 9701 return ret; 9702 } 9703 9704 if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill)) 9705 return 0; 9706 9707 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 9708 vport_num++; 9709 9710 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 9711 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 9712 is_kill); 9713 9714 return ret; 9715 } 9716 9717 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 9718 { 9719 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 9720 struct hclge_vport_vtag_tx_cfg_cmd *req; 9721 struct hclge_dev *hdev = vport->back; 9722 struct hclge_desc desc; 9723 u16 bmap_index; 9724 int status; 9725 9726 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 9727 9728 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 9729 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 9730 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 9731 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 9732 vcfg->accept_tag1 ? 1 : 0); 9733 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 9734 vcfg->accept_untag1 ? 1 : 0); 9735 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 9736 vcfg->accept_tag2 ? 1 : 0); 9737 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 9738 vcfg->accept_untag2 ? 1 : 0); 9739 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 9740 vcfg->insert_tag1_en ? 1 : 0); 9741 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 9742 vcfg->insert_tag2_en ? 1 : 0); 9743 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B, 9744 vcfg->tag_shift_mode_en ? 1 : 0); 9745 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 9746 9747 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9748 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9749 HCLGE_VF_NUM_PER_BYTE; 9750 req->vf_bitmap[bmap_index] = 9751 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9752 9753 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9754 if (status) 9755 dev_err(&hdev->pdev->dev, 9756 "Send port txvlan cfg command fail, ret =%d\n", 9757 status); 9758 9759 return status; 9760 } 9761 9762 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 9763 { 9764 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 9765 struct hclge_vport_vtag_rx_cfg_cmd *req; 9766 struct hclge_dev *hdev = vport->back; 9767 struct hclge_desc desc; 9768 u16 bmap_index; 9769 int status; 9770 9771 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 9772 9773 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 9774 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 9775 vcfg->strip_tag1_en ? 1 : 0); 9776 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 9777 vcfg->strip_tag2_en ? 1 : 0); 9778 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 9779 vcfg->vlan1_vlan_prionly ? 1 : 0); 9780 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 9781 vcfg->vlan2_vlan_prionly ? 1 : 0); 9782 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B, 9783 vcfg->strip_tag1_discard_en ? 1 : 0); 9784 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B, 9785 vcfg->strip_tag2_discard_en ? 1 : 0); 9786 9787 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9788 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9789 HCLGE_VF_NUM_PER_BYTE; 9790 req->vf_bitmap[bmap_index] = 9791 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9792 9793 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9794 if (status) 9795 dev_err(&hdev->pdev->dev, 9796 "Send port rxvlan cfg command fail, ret =%d\n", 9797 status); 9798 9799 return status; 9800 } 9801 9802 static int hclge_vlan_offload_cfg(struct hclge_vport *vport, 9803 u16 port_base_vlan_state, 9804 u16 vlan_tag, u8 qos) 9805 { 9806 int ret; 9807 9808 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9809 vport->txvlan_cfg.accept_tag1 = true; 9810 vport->txvlan_cfg.insert_tag1_en = false; 9811 vport->txvlan_cfg.default_tag1 = 0; 9812 } else { 9813 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev); 9814 9815 vport->txvlan_cfg.accept_tag1 = 9816 ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3; 9817 vport->txvlan_cfg.insert_tag1_en = true; 9818 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) | 9819 vlan_tag; 9820 } 9821 9822 vport->txvlan_cfg.accept_untag1 = true; 9823 9824 /* accept_tag2 and accept_untag2 are not supported on 9825 * pdev revision(0x20), new revision support them, 9826 * this two fields can not be configured by user. 9827 */ 9828 vport->txvlan_cfg.accept_tag2 = true; 9829 vport->txvlan_cfg.accept_untag2 = true; 9830 vport->txvlan_cfg.insert_tag2_en = false; 9831 vport->txvlan_cfg.default_tag2 = 0; 9832 vport->txvlan_cfg.tag_shift_mode_en = true; 9833 9834 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9835 vport->rxvlan_cfg.strip_tag1_en = false; 9836 vport->rxvlan_cfg.strip_tag2_en = 9837 vport->rxvlan_cfg.rx_vlan_offload_en; 9838 vport->rxvlan_cfg.strip_tag2_discard_en = false; 9839 } else { 9840 vport->rxvlan_cfg.strip_tag1_en = 9841 vport->rxvlan_cfg.rx_vlan_offload_en; 9842 vport->rxvlan_cfg.strip_tag2_en = true; 9843 vport->rxvlan_cfg.strip_tag2_discard_en = true; 9844 } 9845 9846 vport->rxvlan_cfg.strip_tag1_discard_en = false; 9847 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 9848 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 9849 9850 ret = hclge_set_vlan_tx_offload_cfg(vport); 9851 if (ret) 9852 return ret; 9853 9854 return hclge_set_vlan_rx_offload_cfg(vport); 9855 } 9856 9857 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 9858 { 9859 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 9860 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 9861 struct hclge_desc desc; 9862 int status; 9863 9864 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 9865 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 9866 rx_req->ot_fst_vlan_type = 9867 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 9868 rx_req->ot_sec_vlan_type = 9869 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 9870 rx_req->in_fst_vlan_type = 9871 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 9872 rx_req->in_sec_vlan_type = 9873 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 9874 9875 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9876 if (status) { 9877 dev_err(&hdev->pdev->dev, 9878 "Send rxvlan protocol type command fail, ret =%d\n", 9879 status); 9880 return status; 9881 } 9882 9883 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 9884 9885 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data; 9886 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 9887 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 9888 9889 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9890 if (status) 9891 dev_err(&hdev->pdev->dev, 9892 "Send txvlan protocol type command fail, ret =%d\n", 9893 status); 9894 9895 return status; 9896 } 9897 9898 static int hclge_init_vlan_filter(struct hclge_dev *hdev) 9899 { 9900 struct hclge_vport *vport; 9901 bool enable = true; 9902 int ret; 9903 int i; 9904 9905 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9906 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9907 HCLGE_FILTER_FE_EGRESS_V1_B, 9908 true, 0); 9909 9910 /* for revision 0x21, vf vlan filter is per function */ 9911 for (i = 0; i < hdev->num_alloc_vport; i++) { 9912 vport = &hdev->vport[i]; 9913 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9914 HCLGE_FILTER_FE_EGRESS, true, 9915 vport->vport_id); 9916 if (ret) 9917 return ret; 9918 vport->cur_vlan_fltr_en = true; 9919 } 9920 9921 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps) && 9922 !test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, hdev->ae_dev->caps)) 9923 enable = false; 9924 9925 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9926 HCLGE_FILTER_FE_INGRESS, enable, 0); 9927 } 9928 9929 static int hclge_init_vlan_type(struct hclge_dev *hdev) 9930 { 9931 hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q; 9932 hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q; 9933 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q; 9934 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q; 9935 hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q; 9936 hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q; 9937 9938 return hclge_set_vlan_protocol_type(hdev); 9939 } 9940 9941 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev) 9942 { 9943 struct hclge_port_base_vlan_config *cfg; 9944 struct hclge_vport *vport; 9945 int ret; 9946 int i; 9947 9948 for (i = 0; i < hdev->num_alloc_vport; i++) { 9949 vport = &hdev->vport[i]; 9950 cfg = &vport->port_base_vlan_cfg; 9951 9952 ret = hclge_vlan_offload_cfg(vport, cfg->state, 9953 cfg->vlan_info.vlan_tag, 9954 cfg->vlan_info.qos); 9955 if (ret) 9956 return ret; 9957 } 9958 return 0; 9959 } 9960 9961 static int hclge_init_vlan_config(struct hclge_dev *hdev) 9962 { 9963 struct hnae3_handle *handle = &hdev->vport[0].nic; 9964 int ret; 9965 9966 ret = hclge_init_vlan_filter(hdev); 9967 if (ret) 9968 return ret; 9969 9970 ret = hclge_init_vlan_type(hdev); 9971 if (ret) 9972 return ret; 9973 9974 ret = hclge_init_vport_vlan_offload(hdev); 9975 if (ret) 9976 return ret; 9977 9978 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 9979 } 9980 9981 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 9982 bool writen_to_tbl) 9983 { 9984 struct hclge_vport_vlan_cfg *vlan, *tmp; 9985 struct hclge_dev *hdev = vport->back; 9986 9987 mutex_lock(&hdev->vport_lock); 9988 9989 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 9990 if (vlan->vlan_id == vlan_id) { 9991 mutex_unlock(&hdev->vport_lock); 9992 return; 9993 } 9994 } 9995 9996 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 9997 if (!vlan) { 9998 mutex_unlock(&hdev->vport_lock); 9999 return; 10000 } 10001 10002 vlan->hd_tbl_status = writen_to_tbl; 10003 vlan->vlan_id = vlan_id; 10004 10005 list_add_tail(&vlan->node, &vport->vlan_list); 10006 mutex_unlock(&hdev->vport_lock); 10007 } 10008 10009 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport) 10010 { 10011 struct hclge_vport_vlan_cfg *vlan, *tmp; 10012 struct hclge_dev *hdev = vport->back; 10013 int ret; 10014 10015 mutex_lock(&hdev->vport_lock); 10016 10017 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10018 if (!vlan->hd_tbl_status) { 10019 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10020 vport->vport_id, 10021 vlan->vlan_id, false); 10022 if (ret) { 10023 dev_err(&hdev->pdev->dev, 10024 "restore vport vlan list failed, ret=%d\n", 10025 ret); 10026 10027 mutex_unlock(&hdev->vport_lock); 10028 return ret; 10029 } 10030 } 10031 vlan->hd_tbl_status = true; 10032 } 10033 10034 mutex_unlock(&hdev->vport_lock); 10035 10036 return 0; 10037 } 10038 10039 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10040 bool is_write_tbl) 10041 { 10042 struct hclge_vport_vlan_cfg *vlan, *tmp; 10043 struct hclge_dev *hdev = vport->back; 10044 10045 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10046 if (vlan->vlan_id == vlan_id) { 10047 if (is_write_tbl && vlan->hd_tbl_status) 10048 hclge_set_vlan_filter_hw(hdev, 10049 htons(ETH_P_8021Q), 10050 vport->vport_id, 10051 vlan_id, 10052 true); 10053 10054 list_del(&vlan->node); 10055 kfree(vlan); 10056 break; 10057 } 10058 } 10059 } 10060 10061 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list) 10062 { 10063 struct hclge_vport_vlan_cfg *vlan, *tmp; 10064 struct hclge_dev *hdev = vport->back; 10065 10066 mutex_lock(&hdev->vport_lock); 10067 10068 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10069 if (vlan->hd_tbl_status) 10070 hclge_set_vlan_filter_hw(hdev, 10071 htons(ETH_P_8021Q), 10072 vport->vport_id, 10073 vlan->vlan_id, 10074 true); 10075 10076 vlan->hd_tbl_status = false; 10077 if (is_del_list) { 10078 list_del(&vlan->node); 10079 kfree(vlan); 10080 } 10081 } 10082 clear_bit(vport->vport_id, hdev->vf_vlan_full); 10083 mutex_unlock(&hdev->vport_lock); 10084 } 10085 10086 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev) 10087 { 10088 struct hclge_vport_vlan_cfg *vlan, *tmp; 10089 struct hclge_vport *vport; 10090 int i; 10091 10092 mutex_lock(&hdev->vport_lock); 10093 10094 for (i = 0; i < hdev->num_alloc_vport; i++) { 10095 vport = &hdev->vport[i]; 10096 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10097 list_del(&vlan->node); 10098 kfree(vlan); 10099 } 10100 } 10101 10102 mutex_unlock(&hdev->vport_lock); 10103 } 10104 10105 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev) 10106 { 10107 struct hclge_vlan_info *vlan_info; 10108 struct hclge_vport *vport; 10109 u16 vlan_proto; 10110 u16 vlan_id; 10111 u16 state; 10112 int vf_id; 10113 int ret; 10114 10115 /* PF should restore all vfs port base vlan */ 10116 for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) { 10117 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM]; 10118 vlan_info = vport->port_base_vlan_cfg.tbl_sta ? 10119 &vport->port_base_vlan_cfg.vlan_info : 10120 &vport->port_base_vlan_cfg.old_vlan_info; 10121 10122 vlan_id = vlan_info->vlan_tag; 10123 vlan_proto = vlan_info->vlan_proto; 10124 state = vport->port_base_vlan_cfg.state; 10125 10126 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) { 10127 clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]); 10128 ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto), 10129 vport->vport_id, 10130 vlan_id, false); 10131 vport->port_base_vlan_cfg.tbl_sta = ret == 0; 10132 } 10133 } 10134 } 10135 10136 void hclge_restore_vport_vlan_table(struct hclge_vport *vport) 10137 { 10138 struct hclge_vport_vlan_cfg *vlan, *tmp; 10139 struct hclge_dev *hdev = vport->back; 10140 int ret; 10141 10142 mutex_lock(&hdev->vport_lock); 10143 10144 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10145 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10146 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10147 vport->vport_id, 10148 vlan->vlan_id, false); 10149 if (ret) 10150 break; 10151 vlan->hd_tbl_status = true; 10152 } 10153 } 10154 10155 mutex_unlock(&hdev->vport_lock); 10156 } 10157 10158 /* For global reset and imp reset, hardware will clear the mac table, 10159 * so we change the mac address state from ACTIVE to TO_ADD, then they 10160 * can be restored in the service task after reset complete. Furtherly, 10161 * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to 10162 * be restored after reset, so just remove these mac nodes from mac_list. 10163 */ 10164 static void hclge_mac_node_convert_for_reset(struct list_head *list) 10165 { 10166 struct hclge_mac_node *mac_node, *tmp; 10167 10168 list_for_each_entry_safe(mac_node, tmp, list, node) { 10169 if (mac_node->state == HCLGE_MAC_ACTIVE) { 10170 mac_node->state = HCLGE_MAC_TO_ADD; 10171 } else if (mac_node->state == HCLGE_MAC_TO_DEL) { 10172 list_del(&mac_node->node); 10173 kfree(mac_node); 10174 } 10175 } 10176 } 10177 10178 void hclge_restore_mac_table_common(struct hclge_vport *vport) 10179 { 10180 spin_lock_bh(&vport->mac_list_lock); 10181 10182 hclge_mac_node_convert_for_reset(&vport->uc_mac_list); 10183 hclge_mac_node_convert_for_reset(&vport->mc_mac_list); 10184 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 10185 10186 spin_unlock_bh(&vport->mac_list_lock); 10187 } 10188 10189 static void hclge_restore_hw_table(struct hclge_dev *hdev) 10190 { 10191 struct hclge_vport *vport = &hdev->vport[0]; 10192 struct hnae3_handle *handle = &vport->nic; 10193 10194 hclge_restore_mac_table_common(vport); 10195 hclge_restore_vport_port_base_vlan_config(hdev); 10196 hclge_restore_vport_vlan_table(vport); 10197 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 10198 hclge_restore_fd_entries(handle); 10199 } 10200 10201 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 10202 { 10203 struct hclge_vport *vport = hclge_get_vport(handle); 10204 10205 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10206 vport->rxvlan_cfg.strip_tag1_en = false; 10207 vport->rxvlan_cfg.strip_tag2_en = enable; 10208 vport->rxvlan_cfg.strip_tag2_discard_en = false; 10209 } else { 10210 vport->rxvlan_cfg.strip_tag1_en = enable; 10211 vport->rxvlan_cfg.strip_tag2_en = true; 10212 vport->rxvlan_cfg.strip_tag2_discard_en = true; 10213 } 10214 10215 vport->rxvlan_cfg.strip_tag1_discard_en = false; 10216 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 10217 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 10218 vport->rxvlan_cfg.rx_vlan_offload_en = enable; 10219 10220 return hclge_set_vlan_rx_offload_cfg(vport); 10221 } 10222 10223 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport) 10224 { 10225 struct hclge_dev *hdev = vport->back; 10226 10227 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 10228 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state); 10229 } 10230 10231 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport, 10232 u16 port_base_vlan_state, 10233 struct hclge_vlan_info *new_info, 10234 struct hclge_vlan_info *old_info) 10235 { 10236 struct hclge_dev *hdev = vport->back; 10237 int ret; 10238 10239 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) { 10240 hclge_rm_vport_all_vlan_table(vport, false); 10241 /* force clear VLAN 0 */ 10242 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0); 10243 if (ret) 10244 return ret; 10245 return hclge_set_vlan_filter_hw(hdev, 10246 htons(new_info->vlan_proto), 10247 vport->vport_id, 10248 new_info->vlan_tag, 10249 false); 10250 } 10251 10252 vport->port_base_vlan_cfg.tbl_sta = false; 10253 10254 /* force add VLAN 0 */ 10255 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0); 10256 if (ret) 10257 return ret; 10258 10259 ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto), 10260 vport->vport_id, old_info->vlan_tag, 10261 true); 10262 if (ret) 10263 return ret; 10264 10265 return hclge_add_vport_all_vlan_table(vport); 10266 } 10267 10268 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg, 10269 const struct hclge_vlan_info *old_cfg) 10270 { 10271 if (new_cfg->vlan_tag != old_cfg->vlan_tag) 10272 return true; 10273 10274 if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0)) 10275 return true; 10276 10277 return false; 10278 } 10279 10280 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport, 10281 struct hclge_vlan_info *new_info, 10282 struct hclge_vlan_info *old_info) 10283 { 10284 struct hclge_dev *hdev = vport->back; 10285 int ret; 10286 10287 /* add new VLAN tag */ 10288 ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto), 10289 vport->vport_id, new_info->vlan_tag, 10290 false); 10291 if (ret) 10292 return ret; 10293 10294 vport->port_base_vlan_cfg.tbl_sta = false; 10295 /* remove old VLAN tag */ 10296 if (old_info->vlan_tag == 0) 10297 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, 10298 true, 0); 10299 else 10300 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10301 vport->vport_id, 10302 old_info->vlan_tag, true); 10303 if (ret) 10304 dev_err(&hdev->pdev->dev, 10305 "failed to clear vport%u port base vlan %u, ret = %d.\n", 10306 vport->vport_id, old_info->vlan_tag, ret); 10307 10308 return ret; 10309 } 10310 10311 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 10312 struct hclge_vlan_info *vlan_info) 10313 { 10314 struct hnae3_handle *nic = &vport->nic; 10315 struct hclge_vlan_info *old_vlan_info; 10316 int ret; 10317 10318 old_vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10319 10320 ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag, 10321 vlan_info->qos); 10322 if (ret) 10323 return ret; 10324 10325 if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info)) 10326 goto out; 10327 10328 if (state == HNAE3_PORT_BASE_VLAN_MODIFY) 10329 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info, 10330 old_vlan_info); 10331 else 10332 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info, 10333 old_vlan_info); 10334 if (ret) 10335 return ret; 10336 10337 out: 10338 vport->port_base_vlan_cfg.state = state; 10339 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 10340 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 10341 else 10342 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 10343 10344 vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info; 10345 vport->port_base_vlan_cfg.vlan_info = *vlan_info; 10346 vport->port_base_vlan_cfg.tbl_sta = true; 10347 hclge_set_vport_vlan_fltr_change(vport); 10348 10349 return 0; 10350 } 10351 10352 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport, 10353 enum hnae3_port_base_vlan_state state, 10354 u16 vlan, u8 qos) 10355 { 10356 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10357 if (!vlan && !qos) 10358 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10359 10360 return HNAE3_PORT_BASE_VLAN_ENABLE; 10361 } 10362 10363 if (!vlan && !qos) 10364 return HNAE3_PORT_BASE_VLAN_DISABLE; 10365 10366 if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan && 10367 vport->port_base_vlan_cfg.vlan_info.qos == qos) 10368 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10369 10370 return HNAE3_PORT_BASE_VLAN_MODIFY; 10371 } 10372 10373 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 10374 u16 vlan, u8 qos, __be16 proto) 10375 { 10376 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 10377 struct hclge_vport *vport = hclge_get_vport(handle); 10378 struct hclge_dev *hdev = vport->back; 10379 struct hclge_vlan_info vlan_info; 10380 u16 state; 10381 int ret; 10382 10383 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 10384 return -EOPNOTSUPP; 10385 10386 vport = hclge_get_vf_vport(hdev, vfid); 10387 if (!vport) 10388 return -EINVAL; 10389 10390 /* qos is a 3 bits value, so can not be bigger than 7 */ 10391 if (vlan > VLAN_N_VID - 1 || qos > 7) 10392 return -EINVAL; 10393 if (proto != htons(ETH_P_8021Q)) 10394 return -EPROTONOSUPPORT; 10395 10396 state = hclge_get_port_base_vlan_state(vport, 10397 vport->port_base_vlan_cfg.state, 10398 vlan, qos); 10399 if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE) 10400 return 0; 10401 10402 vlan_info.vlan_tag = vlan; 10403 vlan_info.qos = qos; 10404 vlan_info.vlan_proto = ntohs(proto); 10405 10406 ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info); 10407 if (ret) { 10408 dev_err(&hdev->pdev->dev, 10409 "failed to update port base vlan for vf %d, ret = %d\n", 10410 vfid, ret); 10411 return ret; 10412 } 10413 10414 /* there is a timewindow for PF to know VF unalive, it may 10415 * cause send mailbox fail, but it doesn't matter, VF will 10416 * query it when reinit. 10417 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based 10418 * VLAN state. 10419 */ 10420 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 10421 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 10422 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0], 10423 vport->vport_id, 10424 state, 10425 &vlan_info); 10426 else 10427 set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, 10428 &vport->need_notify); 10429 } 10430 return 0; 10431 } 10432 10433 static void hclge_clear_vf_vlan(struct hclge_dev *hdev) 10434 { 10435 struct hclge_vlan_info *vlan_info; 10436 struct hclge_vport *vport; 10437 int ret; 10438 int vf; 10439 10440 /* clear port base vlan for all vf */ 10441 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 10442 vport = &hdev->vport[vf]; 10443 vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10444 10445 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10446 vport->vport_id, 10447 vlan_info->vlan_tag, true); 10448 if (ret) 10449 dev_err(&hdev->pdev->dev, 10450 "failed to clear vf vlan for vf%d, ret = %d\n", 10451 vf - HCLGE_VF_VPORT_START_NUM, ret); 10452 } 10453 } 10454 10455 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 10456 u16 vlan_id, bool is_kill) 10457 { 10458 struct hclge_vport *vport = hclge_get_vport(handle); 10459 struct hclge_dev *hdev = vport->back; 10460 bool writen_to_tbl = false; 10461 int ret = 0; 10462 10463 /* When device is resetting or reset failed, firmware is unable to 10464 * handle mailbox. Just record the vlan id, and remove it after 10465 * reset finished. 10466 */ 10467 mutex_lock(&hdev->vport_lock); 10468 if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 10469 test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) { 10470 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10471 mutex_unlock(&hdev->vport_lock); 10472 return -EBUSY; 10473 } else if (!is_kill && test_bit(vlan_id, vport->vlan_del_fail_bmap)) { 10474 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10475 } 10476 mutex_unlock(&hdev->vport_lock); 10477 10478 /* when port base vlan enabled, we use port base vlan as the vlan 10479 * filter entry. In this case, we don't update vlan filter table 10480 * when user add new vlan or remove exist vlan, just update the vport 10481 * vlan list. The vlan id in vlan list will be writen in vlan filter 10482 * table until port base vlan disabled 10483 */ 10484 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10485 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, 10486 vlan_id, is_kill); 10487 writen_to_tbl = true; 10488 } 10489 10490 if (!ret) { 10491 if (!is_kill) { 10492 hclge_add_vport_vlan_table(vport, vlan_id, 10493 writen_to_tbl); 10494 } else if (is_kill && vlan_id != 0) { 10495 mutex_lock(&hdev->vport_lock); 10496 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10497 mutex_unlock(&hdev->vport_lock); 10498 } 10499 } else if (is_kill) { 10500 /* when remove hw vlan filter failed, record the vlan id, 10501 * and try to remove it from hw later, to be consistence 10502 * with stack 10503 */ 10504 mutex_lock(&hdev->vport_lock); 10505 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10506 mutex_unlock(&hdev->vport_lock); 10507 } 10508 10509 hclge_set_vport_vlan_fltr_change(vport); 10510 10511 return ret; 10512 } 10513 10514 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev) 10515 { 10516 struct hclge_vport *vport; 10517 int ret; 10518 u16 i; 10519 10520 for (i = 0; i < hdev->num_alloc_vport; i++) { 10521 vport = &hdev->vport[i]; 10522 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10523 &vport->state)) 10524 continue; 10525 10526 ret = hclge_enable_vport_vlan_filter(vport, 10527 vport->req_vlan_fltr_en); 10528 if (ret) { 10529 dev_err(&hdev->pdev->dev, 10530 "failed to sync vlan filter state for vport%u, ret = %d\n", 10531 vport->vport_id, ret); 10532 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10533 &vport->state); 10534 return; 10535 } 10536 } 10537 } 10538 10539 static void hclge_sync_vlan_filter(struct hclge_dev *hdev) 10540 { 10541 #define HCLGE_MAX_SYNC_COUNT 60 10542 10543 int i, ret, sync_cnt = 0; 10544 u16 vlan_id; 10545 10546 mutex_lock(&hdev->vport_lock); 10547 /* start from vport 1 for PF is always alive */ 10548 for (i = 0; i < hdev->num_alloc_vport; i++) { 10549 struct hclge_vport *vport = &hdev->vport[i]; 10550 10551 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10552 VLAN_N_VID); 10553 while (vlan_id != VLAN_N_VID) { 10554 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10555 vport->vport_id, vlan_id, 10556 true); 10557 if (ret && ret != -EINVAL) { 10558 mutex_unlock(&hdev->vport_lock); 10559 return; 10560 } 10561 10562 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10563 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10564 hclge_set_vport_vlan_fltr_change(vport); 10565 10566 sync_cnt++; 10567 if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) { 10568 mutex_unlock(&hdev->vport_lock); 10569 return; 10570 } 10571 10572 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10573 VLAN_N_VID); 10574 } 10575 } 10576 mutex_unlock(&hdev->vport_lock); 10577 10578 hclge_sync_vlan_fltr_state(hdev); 10579 } 10580 10581 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps) 10582 { 10583 struct hclge_config_max_frm_size_cmd *req; 10584 struct hclge_desc desc; 10585 10586 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 10587 10588 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 10589 req->max_frm_size = cpu_to_le16(new_mps); 10590 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 10591 10592 return hclge_cmd_send(&hdev->hw, &desc, 1); 10593 } 10594 10595 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 10596 { 10597 struct hclge_vport *vport = hclge_get_vport(handle); 10598 10599 return hclge_set_vport_mtu(vport, new_mtu); 10600 } 10601 10602 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) 10603 { 10604 struct hclge_dev *hdev = vport->back; 10605 int i, max_frm_size, ret; 10606 10607 /* HW supprt 2 layer vlan */ 10608 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 10609 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 10610 max_frm_size > hdev->ae_dev->dev_specs.max_frm_size) 10611 return -EINVAL; 10612 10613 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 10614 mutex_lock(&hdev->vport_lock); 10615 /* VF's mps must fit within hdev->mps */ 10616 if (vport->vport_id && max_frm_size > hdev->mps) { 10617 mutex_unlock(&hdev->vport_lock); 10618 return -EINVAL; 10619 } else if (vport->vport_id) { 10620 vport->mps = max_frm_size; 10621 mutex_unlock(&hdev->vport_lock); 10622 return 0; 10623 } 10624 10625 /* PF's mps must be greater then VF's mps */ 10626 for (i = 1; i < hdev->num_alloc_vport; i++) 10627 if (max_frm_size < hdev->vport[i].mps) { 10628 dev_err(&hdev->pdev->dev, 10629 "failed to set pf mtu for less than vport %d, mps = %u.\n", 10630 i, hdev->vport[i].mps); 10631 mutex_unlock(&hdev->vport_lock); 10632 return -EINVAL; 10633 } 10634 10635 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 10636 10637 ret = hclge_set_mac_mtu(hdev, max_frm_size); 10638 if (ret) { 10639 dev_err(&hdev->pdev->dev, 10640 "Change mtu fail, ret =%d\n", ret); 10641 goto out; 10642 } 10643 10644 hdev->mps = max_frm_size; 10645 vport->mps = max_frm_size; 10646 10647 ret = hclge_buffer_alloc(hdev); 10648 if (ret) 10649 dev_err(&hdev->pdev->dev, 10650 "Allocate buffer fail, ret =%d\n", ret); 10651 10652 out: 10653 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 10654 mutex_unlock(&hdev->vport_lock); 10655 return ret; 10656 } 10657 10658 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id, 10659 bool enable) 10660 { 10661 struct hclge_reset_tqp_queue_cmd *req; 10662 struct hclge_desc desc; 10663 int ret; 10664 10665 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 10666 10667 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10668 req->tqp_id = cpu_to_le16(queue_id); 10669 if (enable) 10670 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U); 10671 10672 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10673 if (ret) { 10674 dev_err(&hdev->pdev->dev, 10675 "Send tqp reset cmd error, status =%d\n", ret); 10676 return ret; 10677 } 10678 10679 return 0; 10680 } 10681 10682 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id, 10683 u8 *reset_status) 10684 { 10685 struct hclge_reset_tqp_queue_cmd *req; 10686 struct hclge_desc desc; 10687 int ret; 10688 10689 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 10690 10691 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10692 req->tqp_id = cpu_to_le16(queue_id); 10693 10694 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10695 if (ret) { 10696 dev_err(&hdev->pdev->dev, 10697 "Get reset status error, status =%d\n", ret); 10698 return ret; 10699 } 10700 10701 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 10702 10703 return 0; 10704 } 10705 10706 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id) 10707 { 10708 struct hclge_comm_tqp *tqp; 10709 struct hnae3_queue *queue; 10710 10711 queue = handle->kinfo.tqp[queue_id]; 10712 tqp = container_of(queue, struct hclge_comm_tqp, q); 10713 10714 return tqp->index; 10715 } 10716 10717 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle) 10718 { 10719 struct hclge_vport *vport = hclge_get_vport(handle); 10720 struct hclge_dev *hdev = vport->back; 10721 u16 reset_try_times = 0; 10722 u8 reset_status; 10723 u16 queue_gid; 10724 int ret; 10725 u16 i; 10726 10727 for (i = 0; i < handle->kinfo.num_tqps; i++) { 10728 queue_gid = hclge_covert_handle_qid_global(handle, i); 10729 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true); 10730 if (ret) { 10731 dev_err(&hdev->pdev->dev, 10732 "failed to send reset tqp cmd, ret = %d\n", 10733 ret); 10734 return ret; 10735 } 10736 10737 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 10738 ret = hclge_get_reset_status(hdev, queue_gid, 10739 &reset_status); 10740 if (ret) 10741 return ret; 10742 10743 if (reset_status) 10744 break; 10745 10746 /* Wait for tqp hw reset */ 10747 usleep_range(1000, 1200); 10748 } 10749 10750 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 10751 dev_err(&hdev->pdev->dev, 10752 "wait for tqp hw reset timeout\n"); 10753 return -ETIME; 10754 } 10755 10756 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false); 10757 if (ret) { 10758 dev_err(&hdev->pdev->dev, 10759 "failed to deassert soft reset, ret = %d\n", 10760 ret); 10761 return ret; 10762 } 10763 reset_try_times = 0; 10764 } 10765 return 0; 10766 } 10767 10768 static int hclge_reset_rcb(struct hnae3_handle *handle) 10769 { 10770 #define HCLGE_RESET_RCB_NOT_SUPPORT 0U 10771 #define HCLGE_RESET_RCB_SUCCESS 1U 10772 10773 struct hclge_vport *vport = hclge_get_vport(handle); 10774 struct hclge_dev *hdev = vport->back; 10775 struct hclge_reset_cmd *req; 10776 struct hclge_desc desc; 10777 u8 return_status; 10778 u16 queue_gid; 10779 int ret; 10780 10781 queue_gid = hclge_covert_handle_qid_global(handle, 0); 10782 10783 req = (struct hclge_reset_cmd *)desc.data; 10784 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 10785 hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1); 10786 req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid); 10787 req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps); 10788 10789 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10790 if (ret) { 10791 dev_err(&hdev->pdev->dev, 10792 "failed to send rcb reset cmd, ret = %d\n", ret); 10793 return ret; 10794 } 10795 10796 return_status = req->fun_reset_rcb_return_status; 10797 if (return_status == HCLGE_RESET_RCB_SUCCESS) 10798 return 0; 10799 10800 if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) { 10801 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n", 10802 return_status); 10803 return -EIO; 10804 } 10805 10806 /* if reset rcb cmd is unsupported, we need to send reset tqp cmd 10807 * again to reset all tqps 10808 */ 10809 return hclge_reset_tqp_cmd(handle); 10810 } 10811 10812 int hclge_reset_tqp(struct hnae3_handle *handle) 10813 { 10814 struct hclge_vport *vport = hclge_get_vport(handle); 10815 struct hclge_dev *hdev = vport->back; 10816 int ret; 10817 10818 /* only need to disable PF's tqp */ 10819 if (!vport->vport_id) { 10820 ret = hclge_tqp_enable(handle, false); 10821 if (ret) { 10822 dev_err(&hdev->pdev->dev, 10823 "failed to disable tqp, ret = %d\n", ret); 10824 return ret; 10825 } 10826 } 10827 10828 return hclge_reset_rcb(handle); 10829 } 10830 10831 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 10832 { 10833 struct hclge_vport *vport = hclge_get_vport(handle); 10834 struct hclge_dev *hdev = vport->back; 10835 10836 return hdev->fw_version; 10837 } 10838 10839 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10840 { 10841 struct phy_device *phydev = hdev->hw.mac.phydev; 10842 10843 if (!phydev) 10844 return; 10845 10846 phy_set_asym_pause(phydev, rx_en, tx_en); 10847 } 10848 10849 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10850 { 10851 int ret; 10852 10853 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 10854 return 0; 10855 10856 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 10857 if (ret) 10858 dev_err(&hdev->pdev->dev, 10859 "configure pauseparam error, ret = %d.\n", ret); 10860 10861 return ret; 10862 } 10863 10864 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 10865 { 10866 struct phy_device *phydev = hdev->hw.mac.phydev; 10867 u16 remote_advertising = 0; 10868 u16 local_advertising; 10869 u32 rx_pause, tx_pause; 10870 u8 flowctl; 10871 10872 if (!phydev->link) 10873 return 0; 10874 10875 if (!phydev->autoneg) 10876 return hclge_mac_pause_setup_hw(hdev); 10877 10878 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising); 10879 10880 if (phydev->pause) 10881 remote_advertising = LPA_PAUSE_CAP; 10882 10883 if (phydev->asym_pause) 10884 remote_advertising |= LPA_PAUSE_ASYM; 10885 10886 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 10887 remote_advertising); 10888 tx_pause = flowctl & FLOW_CTRL_TX; 10889 rx_pause = flowctl & FLOW_CTRL_RX; 10890 10891 if (phydev->duplex == HCLGE_MAC_HALF) { 10892 tx_pause = 0; 10893 rx_pause = 0; 10894 } 10895 10896 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 10897 } 10898 10899 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 10900 u32 *rx_en, u32 *tx_en) 10901 { 10902 struct hclge_vport *vport = hclge_get_vport(handle); 10903 struct hclge_dev *hdev = vport->back; 10904 u8 media_type = hdev->hw.mac.media_type; 10905 10906 *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ? 10907 hclge_get_autoneg(handle) : 0; 10908 10909 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 10910 *rx_en = 0; 10911 *tx_en = 0; 10912 return; 10913 } 10914 10915 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 10916 *rx_en = 1; 10917 *tx_en = 0; 10918 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 10919 *tx_en = 1; 10920 *rx_en = 0; 10921 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 10922 *rx_en = 1; 10923 *tx_en = 1; 10924 } else { 10925 *rx_en = 0; 10926 *tx_en = 0; 10927 } 10928 } 10929 10930 static void hclge_record_user_pauseparam(struct hclge_dev *hdev, 10931 u32 rx_en, u32 tx_en) 10932 { 10933 if (rx_en && tx_en) 10934 hdev->fc_mode_last_time = HCLGE_FC_FULL; 10935 else if (rx_en && !tx_en) 10936 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 10937 else if (!rx_en && tx_en) 10938 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 10939 else 10940 hdev->fc_mode_last_time = HCLGE_FC_NONE; 10941 10942 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 10943 } 10944 10945 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 10946 u32 rx_en, u32 tx_en) 10947 { 10948 struct hclge_vport *vport = hclge_get_vport(handle); 10949 struct hclge_dev *hdev = vport->back; 10950 struct phy_device *phydev = hdev->hw.mac.phydev; 10951 u32 fc_autoneg; 10952 10953 if (phydev || hnae3_dev_phy_imp_supported(hdev)) { 10954 fc_autoneg = hclge_get_autoneg(handle); 10955 if (auto_neg != fc_autoneg) { 10956 dev_info(&hdev->pdev->dev, 10957 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 10958 return -EOPNOTSUPP; 10959 } 10960 } 10961 10962 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 10963 dev_info(&hdev->pdev->dev, 10964 "Priority flow control enabled. Cannot set link flow control.\n"); 10965 return -EOPNOTSUPP; 10966 } 10967 10968 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 10969 10970 hclge_record_user_pauseparam(hdev, rx_en, tx_en); 10971 10972 if (!auto_neg || hnae3_dev_phy_imp_supported(hdev)) 10973 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 10974 10975 if (phydev) 10976 return phy_start_aneg(phydev); 10977 10978 return -EOPNOTSUPP; 10979 } 10980 10981 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 10982 u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num) 10983 { 10984 struct hclge_vport *vport = hclge_get_vport(handle); 10985 struct hclge_dev *hdev = vport->back; 10986 10987 if (speed) 10988 *speed = hdev->hw.mac.speed; 10989 if (duplex) 10990 *duplex = hdev->hw.mac.duplex; 10991 if (auto_neg) 10992 *auto_neg = hdev->hw.mac.autoneg; 10993 if (lane_num) 10994 *lane_num = hdev->hw.mac.lane_num; 10995 } 10996 10997 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type, 10998 u8 *module_type) 10999 { 11000 struct hclge_vport *vport = hclge_get_vport(handle); 11001 struct hclge_dev *hdev = vport->back; 11002 11003 /* When nic is down, the service task is not running, doesn't update 11004 * the port information per second. Query the port information before 11005 * return the media type, ensure getting the correct media information. 11006 */ 11007 hclge_update_port_info(hdev); 11008 11009 if (media_type) 11010 *media_type = hdev->hw.mac.media_type; 11011 11012 if (module_type) 11013 *module_type = hdev->hw.mac.module_type; 11014 } 11015 11016 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 11017 u8 *tp_mdix_ctrl, u8 *tp_mdix) 11018 { 11019 struct hclge_vport *vport = hclge_get_vport(handle); 11020 struct hclge_dev *hdev = vport->back; 11021 struct phy_device *phydev = hdev->hw.mac.phydev; 11022 int mdix_ctrl, mdix, is_resolved; 11023 unsigned int retval; 11024 11025 if (!phydev) { 11026 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11027 *tp_mdix = ETH_TP_MDI_INVALID; 11028 return; 11029 } 11030 11031 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 11032 11033 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 11034 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 11035 HCLGE_PHY_MDIX_CTRL_S); 11036 11037 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 11038 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 11039 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 11040 11041 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 11042 11043 switch (mdix_ctrl) { 11044 case 0x0: 11045 *tp_mdix_ctrl = ETH_TP_MDI; 11046 break; 11047 case 0x1: 11048 *tp_mdix_ctrl = ETH_TP_MDI_X; 11049 break; 11050 case 0x3: 11051 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 11052 break; 11053 default: 11054 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11055 break; 11056 } 11057 11058 if (!is_resolved) 11059 *tp_mdix = ETH_TP_MDI_INVALID; 11060 else if (mdix) 11061 *tp_mdix = ETH_TP_MDI_X; 11062 else 11063 *tp_mdix = ETH_TP_MDI; 11064 } 11065 11066 static void hclge_info_show(struct hclge_dev *hdev) 11067 { 11068 struct hnae3_handle *handle = &hdev->vport->nic; 11069 struct device *dev = &hdev->pdev->dev; 11070 11071 dev_info(dev, "PF info begin:\n"); 11072 11073 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 11074 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 11075 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 11076 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 11077 dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs); 11078 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 11079 dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size); 11080 dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size); 11081 dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size); 11082 dev_info(dev, "This is %s PF\n", 11083 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main"); 11084 dev_info(dev, "DCB %s\n", 11085 handle->kinfo.tc_info.dcb_ets_active ? "enable" : "disable"); 11086 dev_info(dev, "MQPRIO %s\n", 11087 handle->kinfo.tc_info.mqprio_active ? "enable" : "disable"); 11088 dev_info(dev, "Default tx spare buffer size: %u\n", 11089 hdev->tx_spare_buf_size); 11090 11091 dev_info(dev, "PF info end.\n"); 11092 } 11093 11094 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 11095 struct hclge_vport *vport) 11096 { 11097 struct hnae3_client *client = vport->nic.client; 11098 struct hclge_dev *hdev = ae_dev->priv; 11099 int rst_cnt = hdev->rst_stats.reset_cnt; 11100 int ret; 11101 11102 ret = client->ops->init_instance(&vport->nic); 11103 if (ret) 11104 return ret; 11105 11106 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11107 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11108 rst_cnt != hdev->rst_stats.reset_cnt) { 11109 ret = -EBUSY; 11110 goto init_nic_err; 11111 } 11112 11113 /* Enable nic hw error interrupts */ 11114 ret = hclge_config_nic_hw_error(hdev, true); 11115 if (ret) { 11116 dev_err(&ae_dev->pdev->dev, 11117 "fail(%d) to enable hw error interrupts\n", ret); 11118 goto init_nic_err; 11119 } 11120 11121 hnae3_set_client_init_flag(client, ae_dev, 1); 11122 11123 if (netif_msg_drv(&hdev->vport->nic)) 11124 hclge_info_show(hdev); 11125 11126 return ret; 11127 11128 init_nic_err: 11129 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11130 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11131 msleep(HCLGE_WAIT_RESET_DONE); 11132 11133 client->ops->uninit_instance(&vport->nic, 0); 11134 11135 return ret; 11136 } 11137 11138 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 11139 struct hclge_vport *vport) 11140 { 11141 struct hclge_dev *hdev = ae_dev->priv; 11142 struct hnae3_client *client; 11143 int rst_cnt; 11144 int ret; 11145 11146 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 11147 !hdev->nic_client) 11148 return 0; 11149 11150 client = hdev->roce_client; 11151 ret = hclge_init_roce_base_info(vport); 11152 if (ret) 11153 return ret; 11154 11155 rst_cnt = hdev->rst_stats.reset_cnt; 11156 ret = client->ops->init_instance(&vport->roce); 11157 if (ret) 11158 return ret; 11159 11160 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11161 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11162 rst_cnt != hdev->rst_stats.reset_cnt) { 11163 ret = -EBUSY; 11164 goto init_roce_err; 11165 } 11166 11167 /* Enable roce ras interrupts */ 11168 ret = hclge_config_rocee_ras_interrupt(hdev, true); 11169 if (ret) { 11170 dev_err(&ae_dev->pdev->dev, 11171 "fail(%d) to enable roce ras interrupts\n", ret); 11172 goto init_roce_err; 11173 } 11174 11175 hnae3_set_client_init_flag(client, ae_dev, 1); 11176 11177 return 0; 11178 11179 init_roce_err: 11180 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11181 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11182 msleep(HCLGE_WAIT_RESET_DONE); 11183 11184 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11185 11186 return ret; 11187 } 11188 11189 static int hclge_init_client_instance(struct hnae3_client *client, 11190 struct hnae3_ae_dev *ae_dev) 11191 { 11192 struct hclge_dev *hdev = ae_dev->priv; 11193 struct hclge_vport *vport = &hdev->vport[0]; 11194 int ret; 11195 11196 switch (client->type) { 11197 case HNAE3_CLIENT_KNIC: 11198 hdev->nic_client = client; 11199 vport->nic.client = client; 11200 ret = hclge_init_nic_client_instance(ae_dev, vport); 11201 if (ret) 11202 goto clear_nic; 11203 11204 ret = hclge_init_roce_client_instance(ae_dev, vport); 11205 if (ret) 11206 goto clear_roce; 11207 11208 break; 11209 case HNAE3_CLIENT_ROCE: 11210 if (hnae3_dev_roce_supported(hdev)) { 11211 hdev->roce_client = client; 11212 vport->roce.client = client; 11213 } 11214 11215 ret = hclge_init_roce_client_instance(ae_dev, vport); 11216 if (ret) 11217 goto clear_roce; 11218 11219 break; 11220 default: 11221 return -EINVAL; 11222 } 11223 11224 return 0; 11225 11226 clear_nic: 11227 hdev->nic_client = NULL; 11228 vport->nic.client = NULL; 11229 return ret; 11230 clear_roce: 11231 hdev->roce_client = NULL; 11232 vport->roce.client = NULL; 11233 return ret; 11234 } 11235 11236 static void hclge_uninit_client_instance(struct hnae3_client *client, 11237 struct hnae3_ae_dev *ae_dev) 11238 { 11239 struct hclge_dev *hdev = ae_dev->priv; 11240 struct hclge_vport *vport = &hdev->vport[0]; 11241 11242 if (hdev->roce_client) { 11243 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11244 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11245 msleep(HCLGE_WAIT_RESET_DONE); 11246 11247 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11248 hdev->roce_client = NULL; 11249 vport->roce.client = NULL; 11250 } 11251 if (client->type == HNAE3_CLIENT_ROCE) 11252 return; 11253 if (hdev->nic_client && client->ops->uninit_instance) { 11254 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11255 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11256 msleep(HCLGE_WAIT_RESET_DONE); 11257 11258 client->ops->uninit_instance(&vport->nic, 0); 11259 hdev->nic_client = NULL; 11260 vport->nic.client = NULL; 11261 } 11262 } 11263 11264 static int hclge_dev_mem_map(struct hclge_dev *hdev) 11265 { 11266 struct pci_dev *pdev = hdev->pdev; 11267 struct hclge_hw *hw = &hdev->hw; 11268 11269 /* for device does not have device memory, return directly */ 11270 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR))) 11271 return 0; 11272 11273 hw->hw.mem_base = 11274 devm_ioremap_wc(&pdev->dev, 11275 pci_resource_start(pdev, HCLGE_MEM_BAR), 11276 pci_resource_len(pdev, HCLGE_MEM_BAR)); 11277 if (!hw->hw.mem_base) { 11278 dev_err(&pdev->dev, "failed to map device memory\n"); 11279 return -EFAULT; 11280 } 11281 11282 return 0; 11283 } 11284 11285 static int hclge_pci_init(struct hclge_dev *hdev) 11286 { 11287 struct pci_dev *pdev = hdev->pdev; 11288 struct hclge_hw *hw; 11289 int ret; 11290 11291 ret = pci_enable_device(pdev); 11292 if (ret) { 11293 dev_err(&pdev->dev, "failed to enable PCI device\n"); 11294 return ret; 11295 } 11296 11297 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 11298 if (ret) { 11299 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 11300 if (ret) { 11301 dev_err(&pdev->dev, 11302 "can't set consistent PCI DMA"); 11303 goto err_disable_device; 11304 } 11305 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 11306 } 11307 11308 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 11309 if (ret) { 11310 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 11311 goto err_disable_device; 11312 } 11313 11314 pci_set_master(pdev); 11315 hw = &hdev->hw; 11316 hw->hw.io_base = pcim_iomap(pdev, 2, 0); 11317 if (!hw->hw.io_base) { 11318 dev_err(&pdev->dev, "Can't map configuration register space\n"); 11319 ret = -ENOMEM; 11320 goto err_release_regions; 11321 } 11322 11323 ret = hclge_dev_mem_map(hdev); 11324 if (ret) 11325 goto err_unmap_io_base; 11326 11327 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 11328 11329 return 0; 11330 11331 err_unmap_io_base: 11332 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11333 err_release_regions: 11334 pci_release_regions(pdev); 11335 err_disable_device: 11336 pci_disable_device(pdev); 11337 11338 return ret; 11339 } 11340 11341 static void hclge_pci_uninit(struct hclge_dev *hdev) 11342 { 11343 struct pci_dev *pdev = hdev->pdev; 11344 11345 if (hdev->hw.hw.mem_base) 11346 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 11347 11348 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11349 pci_free_irq_vectors(pdev); 11350 pci_release_mem_regions(pdev); 11351 pci_disable_device(pdev); 11352 } 11353 11354 static void hclge_state_init(struct hclge_dev *hdev) 11355 { 11356 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 11357 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11358 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 11359 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11360 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 11361 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 11362 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 11363 } 11364 11365 static void hclge_state_uninit(struct hclge_dev *hdev) 11366 { 11367 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11368 set_bit(HCLGE_STATE_REMOVING, &hdev->state); 11369 11370 if (hdev->reset_timer.function) 11371 del_timer_sync(&hdev->reset_timer); 11372 if (hdev->service_task.work.func) 11373 cancel_delayed_work_sync(&hdev->service_task); 11374 } 11375 11376 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 11377 enum hnae3_reset_type rst_type) 11378 { 11379 #define HCLGE_RESET_RETRY_WAIT_MS 500 11380 #define HCLGE_RESET_RETRY_CNT 5 11381 11382 struct hclge_dev *hdev = ae_dev->priv; 11383 int retry_cnt = 0; 11384 int ret; 11385 11386 while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) { 11387 down(&hdev->reset_sem); 11388 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11389 hdev->reset_type = rst_type; 11390 ret = hclge_reset_prepare(hdev); 11391 if (!ret && !hdev->reset_pending) 11392 break; 11393 11394 dev_err(&hdev->pdev->dev, 11395 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 11396 ret, hdev->reset_pending, retry_cnt); 11397 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11398 up(&hdev->reset_sem); 11399 msleep(HCLGE_RESET_RETRY_WAIT_MS); 11400 } 11401 11402 /* disable misc vector before reset done */ 11403 hclge_enable_vector(&hdev->misc_vector, false); 11404 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 11405 11406 if (hdev->reset_type == HNAE3_FLR_RESET) 11407 hdev->rst_stats.flr_rst_cnt++; 11408 } 11409 11410 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev) 11411 { 11412 struct hclge_dev *hdev = ae_dev->priv; 11413 int ret; 11414 11415 hclge_enable_vector(&hdev->misc_vector, true); 11416 11417 ret = hclge_reset_rebuild(hdev); 11418 if (ret) 11419 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret); 11420 11421 hdev->reset_type = HNAE3_NONE_RESET; 11422 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11423 up(&hdev->reset_sem); 11424 } 11425 11426 static void hclge_clear_resetting_state(struct hclge_dev *hdev) 11427 { 11428 u16 i; 11429 11430 for (i = 0; i < hdev->num_alloc_vport; i++) { 11431 struct hclge_vport *vport = &hdev->vport[i]; 11432 int ret; 11433 11434 /* Send cmd to clear vport's FUNC_RST_ING */ 11435 ret = hclge_set_vf_rst(hdev, vport->vport_id, false); 11436 if (ret) 11437 dev_warn(&hdev->pdev->dev, 11438 "clear vport(%u) rst failed %d!\n", 11439 vport->vport_id, ret); 11440 } 11441 } 11442 11443 static int hclge_clear_hw_resource(struct hclge_dev *hdev) 11444 { 11445 struct hclge_desc desc; 11446 int ret; 11447 11448 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false); 11449 11450 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11451 /* This new command is only supported by new firmware, it will 11452 * fail with older firmware. Error value -EOPNOSUPP can only be 11453 * returned by older firmware running this command, to keep code 11454 * backward compatible we will override this value and return 11455 * success. 11456 */ 11457 if (ret && ret != -EOPNOTSUPP) { 11458 dev_err(&hdev->pdev->dev, 11459 "failed to clear hw resource, ret = %d\n", ret); 11460 return ret; 11461 } 11462 return 0; 11463 } 11464 11465 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev) 11466 { 11467 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11468 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1); 11469 } 11470 11471 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev) 11472 { 11473 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11474 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0); 11475 } 11476 11477 static struct hclge_wol_info *hclge_get_wol_info(struct hnae3_handle *handle) 11478 { 11479 struct hclge_vport *vport = hclge_get_vport(handle); 11480 11481 return &vport->back->hw.mac.wol; 11482 } 11483 11484 static int hclge_get_wol_supported_mode(struct hclge_dev *hdev, 11485 u32 *wol_supported) 11486 { 11487 struct hclge_query_wol_supported_cmd *wol_supported_cmd; 11488 struct hclge_desc desc; 11489 int ret; 11490 11491 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_GET_SUPPORTED_MODE, 11492 true); 11493 wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)desc.data; 11494 11495 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11496 if (ret) { 11497 dev_err(&hdev->pdev->dev, 11498 "failed to query wol supported, ret = %d\n", ret); 11499 return ret; 11500 } 11501 11502 *wol_supported = le32_to_cpu(wol_supported_cmd->supported_wake_mode); 11503 11504 return 0; 11505 } 11506 11507 static int hclge_set_wol_cfg(struct hclge_dev *hdev, 11508 struct hclge_wol_info *wol_info) 11509 { 11510 struct hclge_wol_cfg_cmd *wol_cfg_cmd; 11511 struct hclge_desc desc; 11512 int ret; 11513 11514 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, false); 11515 wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)desc.data; 11516 wol_cfg_cmd->wake_on_lan_mode = cpu_to_le32(wol_info->wol_current_mode); 11517 wol_cfg_cmd->sopass_size = wol_info->wol_sopass_size; 11518 memcpy(wol_cfg_cmd->sopass, wol_info->wol_sopass, SOPASS_MAX); 11519 11520 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11521 if (ret) 11522 dev_err(&hdev->pdev->dev, 11523 "failed to set wol config, ret = %d\n", ret); 11524 11525 return ret; 11526 } 11527 11528 static int hclge_update_wol(struct hclge_dev *hdev) 11529 { 11530 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11531 11532 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11533 return 0; 11534 11535 return hclge_set_wol_cfg(hdev, wol_info); 11536 } 11537 11538 static int hclge_init_wol(struct hclge_dev *hdev) 11539 { 11540 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11541 int ret; 11542 11543 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11544 return 0; 11545 11546 memset(wol_info, 0, sizeof(struct hclge_wol_info)); 11547 ret = hclge_get_wol_supported_mode(hdev, 11548 &wol_info->wol_support_mode); 11549 if (ret) { 11550 wol_info->wol_support_mode = 0; 11551 return ret; 11552 } 11553 11554 return hclge_update_wol(hdev); 11555 } 11556 11557 static void hclge_get_wol(struct hnae3_handle *handle, 11558 struct ethtool_wolinfo *wol) 11559 { 11560 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11561 11562 wol->supported = wol_info->wol_support_mode; 11563 wol->wolopts = wol_info->wol_current_mode; 11564 if (wol_info->wol_current_mode & WAKE_MAGICSECURE) 11565 memcpy(wol->sopass, wol_info->wol_sopass, SOPASS_MAX); 11566 } 11567 11568 static int hclge_set_wol(struct hnae3_handle *handle, 11569 struct ethtool_wolinfo *wol) 11570 { 11571 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11572 struct hclge_vport *vport = hclge_get_vport(handle); 11573 u32 wol_mode; 11574 int ret; 11575 11576 wol_mode = wol->wolopts; 11577 if (wol_mode & ~wol_info->wol_support_mode) 11578 return -EINVAL; 11579 11580 wol_info->wol_current_mode = wol_mode; 11581 if (wol_mode & WAKE_MAGICSECURE) { 11582 memcpy(wol_info->wol_sopass, wol->sopass, SOPASS_MAX); 11583 wol_info->wol_sopass_size = SOPASS_MAX; 11584 } else { 11585 wol_info->wol_sopass_size = 0; 11586 } 11587 11588 ret = hclge_set_wol_cfg(vport->back, wol_info); 11589 if (ret) 11590 wol_info->wol_current_mode = 0; 11591 11592 return ret; 11593 } 11594 11595 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 11596 { 11597 struct pci_dev *pdev = ae_dev->pdev; 11598 struct hclge_dev *hdev; 11599 int ret; 11600 11601 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 11602 if (!hdev) 11603 return -ENOMEM; 11604 11605 hdev->pdev = pdev; 11606 hdev->ae_dev = ae_dev; 11607 hdev->reset_type = HNAE3_NONE_RESET; 11608 hdev->reset_level = HNAE3_FUNC_RESET; 11609 ae_dev->priv = hdev; 11610 11611 /* HW supprt 2 layer vlan */ 11612 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 11613 11614 mutex_init(&hdev->vport_lock); 11615 spin_lock_init(&hdev->fd_rule_lock); 11616 sema_init(&hdev->reset_sem, 1); 11617 11618 ret = hclge_pci_init(hdev); 11619 if (ret) 11620 goto out; 11621 11622 /* Firmware command queue initialize */ 11623 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 11624 if (ret) 11625 goto err_pci_uninit; 11626 11627 /* Firmware command initialize */ 11628 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 11629 true, hdev->reset_pending); 11630 if (ret) 11631 goto err_cmd_uninit; 11632 11633 ret = hclge_clear_hw_resource(hdev); 11634 if (ret) 11635 goto err_cmd_uninit; 11636 11637 ret = hclge_get_cap(hdev); 11638 if (ret) 11639 goto err_cmd_uninit; 11640 11641 ret = hclge_query_dev_specs(hdev); 11642 if (ret) { 11643 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n", 11644 ret); 11645 goto err_cmd_uninit; 11646 } 11647 11648 ret = hclge_configure(hdev); 11649 if (ret) { 11650 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 11651 goto err_cmd_uninit; 11652 } 11653 11654 ret = hclge_init_msi(hdev); 11655 if (ret) { 11656 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 11657 goto err_cmd_uninit; 11658 } 11659 11660 ret = hclge_misc_irq_init(hdev); 11661 if (ret) 11662 goto err_msi_uninit; 11663 11664 ret = hclge_alloc_tqps(hdev); 11665 if (ret) { 11666 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 11667 goto err_msi_irq_uninit; 11668 } 11669 11670 ret = hclge_alloc_vport(hdev); 11671 if (ret) 11672 goto err_msi_irq_uninit; 11673 11674 ret = hclge_map_tqp(hdev); 11675 if (ret) 11676 goto err_msi_irq_uninit; 11677 11678 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { 11679 clear_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps); 11680 if (hnae3_dev_phy_imp_supported(hdev)) 11681 ret = hclge_update_tp_port_info(hdev); 11682 else 11683 ret = hclge_mac_mdio_config(hdev); 11684 11685 if (ret) 11686 goto err_msi_irq_uninit; 11687 } 11688 11689 ret = hclge_init_umv_space(hdev); 11690 if (ret) 11691 goto err_mdiobus_unreg; 11692 11693 ret = hclge_mac_init(hdev); 11694 if (ret) { 11695 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 11696 goto err_mdiobus_unreg; 11697 } 11698 11699 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 11700 if (ret) { 11701 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 11702 goto err_mdiobus_unreg; 11703 } 11704 11705 ret = hclge_config_gro(hdev); 11706 if (ret) 11707 goto err_mdiobus_unreg; 11708 11709 ret = hclge_init_vlan_config(hdev); 11710 if (ret) { 11711 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 11712 goto err_mdiobus_unreg; 11713 } 11714 11715 ret = hclge_tm_schd_init(hdev); 11716 if (ret) { 11717 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 11718 goto err_mdiobus_unreg; 11719 } 11720 11721 ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev, 11722 &hdev->rss_cfg); 11723 if (ret) { 11724 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 11725 goto err_mdiobus_unreg; 11726 } 11727 11728 ret = hclge_rss_init_hw(hdev); 11729 if (ret) { 11730 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 11731 goto err_mdiobus_unreg; 11732 } 11733 11734 ret = init_mgr_tbl(hdev); 11735 if (ret) { 11736 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 11737 goto err_mdiobus_unreg; 11738 } 11739 11740 ret = hclge_init_fd_config(hdev); 11741 if (ret) { 11742 dev_err(&pdev->dev, 11743 "fd table init fail, ret=%d\n", ret); 11744 goto err_mdiobus_unreg; 11745 } 11746 11747 ret = hclge_ptp_init(hdev); 11748 if (ret) 11749 goto err_mdiobus_unreg; 11750 11751 ret = hclge_update_port_info(hdev); 11752 if (ret) 11753 goto err_ptp_uninit; 11754 11755 INIT_KFIFO(hdev->mac_tnl_log); 11756 11757 hclge_dcb_ops_set(hdev); 11758 11759 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0); 11760 INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task); 11761 11762 hclge_clear_all_event_cause(hdev); 11763 hclge_clear_resetting_state(hdev); 11764 11765 /* Log and clear the hw errors those already occurred */ 11766 if (hnae3_dev_ras_imp_supported(hdev)) 11767 hclge_handle_occurred_error(hdev); 11768 else 11769 hclge_handle_all_hns_hw_errors(ae_dev); 11770 11771 /* request delayed reset for the error recovery because an immediate 11772 * global reset on a PF affecting pending initialization of other PFs 11773 */ 11774 if (ae_dev->hw_err_reset_req) { 11775 enum hnae3_reset_type reset_level; 11776 11777 reset_level = hclge_get_reset_level(ae_dev, 11778 &ae_dev->hw_err_reset_req); 11779 hclge_set_def_reset_request(ae_dev, reset_level); 11780 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 11781 } 11782 11783 hclge_init_rxd_adv_layout(hdev); 11784 11785 /* Enable MISC vector(vector0) */ 11786 hclge_enable_vector(&hdev->misc_vector, true); 11787 11788 ret = hclge_init_wol(hdev); 11789 if (ret) 11790 dev_warn(&pdev->dev, 11791 "failed to wake on lan init, ret = %d\n", ret); 11792 11793 ret = hclge_devlink_init(hdev); 11794 if (ret) 11795 goto err_ptp_uninit; 11796 11797 hclge_state_init(hdev); 11798 hdev->last_reset_time = jiffies; 11799 11800 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", 11801 HCLGE_DRIVER_NAME); 11802 11803 hclge_task_schedule(hdev, round_jiffies_relative(HZ)); 11804 return 0; 11805 11806 err_ptp_uninit: 11807 hclge_ptp_uninit(hdev); 11808 err_mdiobus_unreg: 11809 if (hdev->hw.mac.phydev) 11810 mdiobus_unregister(hdev->hw.mac.mdio_bus); 11811 err_msi_irq_uninit: 11812 hclge_misc_irq_uninit(hdev); 11813 err_msi_uninit: 11814 pci_free_irq_vectors(pdev); 11815 err_cmd_uninit: 11816 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 11817 err_pci_uninit: 11818 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11819 pci_release_regions(pdev); 11820 pci_disable_device(pdev); 11821 out: 11822 mutex_destroy(&hdev->vport_lock); 11823 return ret; 11824 } 11825 11826 static void hclge_stats_clear(struct hclge_dev *hdev) 11827 { 11828 memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats)); 11829 memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats)); 11830 } 11831 11832 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11833 { 11834 return hclge_config_switch_param(hdev, vf, enable, 11835 HCLGE_SWITCH_ANTI_SPOOF_MASK); 11836 } 11837 11838 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11839 { 11840 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 11841 HCLGE_FILTER_FE_NIC_INGRESS_B, 11842 enable, vf); 11843 } 11844 11845 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) 11846 { 11847 int ret; 11848 11849 ret = hclge_set_mac_spoofchk(hdev, vf, enable); 11850 if (ret) { 11851 dev_err(&hdev->pdev->dev, 11852 "Set vf %d mac spoof check %s failed, ret=%d\n", 11853 vf, enable ? "on" : "off", ret); 11854 return ret; 11855 } 11856 11857 ret = hclge_set_vlan_spoofchk(hdev, vf, enable); 11858 if (ret) 11859 dev_err(&hdev->pdev->dev, 11860 "Set vf %d vlan spoof check %s failed, ret=%d\n", 11861 vf, enable ? "on" : "off", ret); 11862 11863 return ret; 11864 } 11865 11866 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf, 11867 bool enable) 11868 { 11869 struct hclge_vport *vport = hclge_get_vport(handle); 11870 struct hclge_dev *hdev = vport->back; 11871 u32 new_spoofchk = enable ? 1 : 0; 11872 int ret; 11873 11874 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11875 return -EOPNOTSUPP; 11876 11877 vport = hclge_get_vf_vport(hdev, vf); 11878 if (!vport) 11879 return -EINVAL; 11880 11881 if (vport->vf_info.spoofchk == new_spoofchk) 11882 return 0; 11883 11884 if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full)) 11885 dev_warn(&hdev->pdev->dev, 11886 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n", 11887 vf); 11888 else if (enable && hclge_is_umv_space_full(vport, true)) 11889 dev_warn(&hdev->pdev->dev, 11890 "vf %d mac table is full, enable spoof check may cause its packet send fail\n", 11891 vf); 11892 11893 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable); 11894 if (ret) 11895 return ret; 11896 11897 vport->vf_info.spoofchk = new_spoofchk; 11898 return 0; 11899 } 11900 11901 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev) 11902 { 11903 struct hclge_vport *vport = hdev->vport; 11904 int ret; 11905 int i; 11906 11907 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11908 return 0; 11909 11910 /* resume the vf spoof check state after reset */ 11911 for (i = 0; i < hdev->num_alloc_vport; i++) { 11912 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, 11913 vport->vf_info.spoofchk); 11914 if (ret) 11915 return ret; 11916 11917 vport++; 11918 } 11919 11920 return 0; 11921 } 11922 11923 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable) 11924 { 11925 struct hclge_vport *vport = hclge_get_vport(handle); 11926 struct hclge_dev *hdev = vport->back; 11927 u32 new_trusted = enable ? 1 : 0; 11928 11929 vport = hclge_get_vf_vport(hdev, vf); 11930 if (!vport) 11931 return -EINVAL; 11932 11933 if (vport->vf_info.trusted == new_trusted) 11934 return 0; 11935 11936 vport->vf_info.trusted = new_trusted; 11937 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 11938 hclge_task_schedule(hdev, 0); 11939 11940 return 0; 11941 } 11942 11943 static void hclge_reset_vf_rate(struct hclge_dev *hdev) 11944 { 11945 int ret; 11946 int vf; 11947 11948 /* reset vf rate to default value */ 11949 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 11950 struct hclge_vport *vport = &hdev->vport[vf]; 11951 11952 vport->vf_info.max_tx_rate = 0; 11953 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); 11954 if (ret) 11955 dev_err(&hdev->pdev->dev, 11956 "vf%d failed to reset to default, ret=%d\n", 11957 vf - HCLGE_VF_VPORT_START_NUM, ret); 11958 } 11959 } 11960 11961 static int hclge_vf_rate_param_check(struct hclge_dev *hdev, 11962 int min_tx_rate, int max_tx_rate) 11963 { 11964 if (min_tx_rate != 0 || 11965 max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) { 11966 dev_err(&hdev->pdev->dev, 11967 "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n", 11968 min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed); 11969 return -EINVAL; 11970 } 11971 11972 return 0; 11973 } 11974 11975 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf, 11976 int min_tx_rate, int max_tx_rate, bool force) 11977 { 11978 struct hclge_vport *vport = hclge_get_vport(handle); 11979 struct hclge_dev *hdev = vport->back; 11980 int ret; 11981 11982 ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate); 11983 if (ret) 11984 return ret; 11985 11986 vport = hclge_get_vf_vport(hdev, vf); 11987 if (!vport) 11988 return -EINVAL; 11989 11990 if (!force && max_tx_rate == vport->vf_info.max_tx_rate) 11991 return 0; 11992 11993 ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); 11994 if (ret) 11995 return ret; 11996 11997 vport->vf_info.max_tx_rate = max_tx_rate; 11998 11999 return 0; 12000 } 12001 12002 static int hclge_resume_vf_rate(struct hclge_dev *hdev) 12003 { 12004 struct hnae3_handle *handle = &hdev->vport->nic; 12005 struct hclge_vport *vport; 12006 int ret; 12007 int vf; 12008 12009 /* resume the vf max_tx_rate after reset */ 12010 for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) { 12011 vport = hclge_get_vf_vport(hdev, vf); 12012 if (!vport) 12013 return -EINVAL; 12014 12015 /* zero means max rate, after reset, firmware already set it to 12016 * max rate, so just continue. 12017 */ 12018 if (!vport->vf_info.max_tx_rate) 12019 continue; 12020 12021 ret = hclge_set_vf_rate(handle, vf, 0, 12022 vport->vf_info.max_tx_rate, true); 12023 if (ret) { 12024 dev_err(&hdev->pdev->dev, 12025 "vf%d failed to resume tx_rate:%u, ret=%d\n", 12026 vf, vport->vf_info.max_tx_rate, ret); 12027 return ret; 12028 } 12029 } 12030 12031 return 0; 12032 } 12033 12034 static void hclge_reset_vport_state(struct hclge_dev *hdev) 12035 { 12036 struct hclge_vport *vport = hdev->vport; 12037 int i; 12038 12039 for (i = 0; i < hdev->num_alloc_vport; i++) { 12040 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12041 vport++; 12042 } 12043 } 12044 12045 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 12046 { 12047 struct hclge_dev *hdev = ae_dev->priv; 12048 struct pci_dev *pdev = ae_dev->pdev; 12049 int ret; 12050 12051 set_bit(HCLGE_STATE_DOWN, &hdev->state); 12052 12053 hclge_stats_clear(hdev); 12054 /* NOTE: pf reset needn't to clear or restore pf and vf table entry. 12055 * so here should not clean table in memory. 12056 */ 12057 if (hdev->reset_type == HNAE3_IMP_RESET || 12058 hdev->reset_type == HNAE3_GLOBAL_RESET) { 12059 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 12060 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full)); 12061 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport); 12062 hclge_reset_umv_space(hdev); 12063 } 12064 12065 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 12066 true, hdev->reset_pending); 12067 if (ret) { 12068 dev_err(&pdev->dev, "Cmd queue init failed\n"); 12069 return ret; 12070 } 12071 12072 ret = hclge_map_tqp(hdev); 12073 if (ret) { 12074 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 12075 return ret; 12076 } 12077 12078 ret = hclge_mac_init(hdev); 12079 if (ret) { 12080 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 12081 return ret; 12082 } 12083 12084 ret = hclge_tp_port_init(hdev); 12085 if (ret) { 12086 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n", 12087 ret); 12088 return ret; 12089 } 12090 12091 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 12092 if (ret) { 12093 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 12094 return ret; 12095 } 12096 12097 ret = hclge_config_gro(hdev); 12098 if (ret) 12099 return ret; 12100 12101 ret = hclge_init_vlan_config(hdev); 12102 if (ret) { 12103 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 12104 return ret; 12105 } 12106 12107 ret = hclge_tm_init_hw(hdev, true); 12108 if (ret) { 12109 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 12110 return ret; 12111 } 12112 12113 ret = hclge_rss_init_hw(hdev); 12114 if (ret) { 12115 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 12116 return ret; 12117 } 12118 12119 ret = init_mgr_tbl(hdev); 12120 if (ret) { 12121 dev_err(&pdev->dev, 12122 "failed to reinit manager table, ret = %d\n", ret); 12123 return ret; 12124 } 12125 12126 ret = hclge_init_fd_config(hdev); 12127 if (ret) { 12128 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret); 12129 return ret; 12130 } 12131 12132 ret = hclge_ptp_init(hdev); 12133 if (ret) 12134 return ret; 12135 12136 /* Log and clear the hw errors those already occurred */ 12137 if (hnae3_dev_ras_imp_supported(hdev)) 12138 hclge_handle_occurred_error(hdev); 12139 else 12140 hclge_handle_all_hns_hw_errors(ae_dev); 12141 12142 /* Re-enable the hw error interrupts because 12143 * the interrupts get disabled on global reset. 12144 */ 12145 ret = hclge_config_nic_hw_error(hdev, true); 12146 if (ret) { 12147 dev_err(&pdev->dev, 12148 "fail(%d) to re-enable NIC hw error interrupts\n", 12149 ret); 12150 return ret; 12151 } 12152 12153 if (hdev->roce_client) { 12154 ret = hclge_config_rocee_ras_interrupt(hdev, true); 12155 if (ret) { 12156 dev_err(&pdev->dev, 12157 "fail(%d) to re-enable roce ras interrupts\n", 12158 ret); 12159 return ret; 12160 } 12161 } 12162 12163 hclge_reset_vport_state(hdev); 12164 ret = hclge_reset_vport_spoofchk(hdev); 12165 if (ret) 12166 return ret; 12167 12168 ret = hclge_resume_vf_rate(hdev); 12169 if (ret) 12170 return ret; 12171 12172 hclge_init_rxd_adv_layout(hdev); 12173 12174 ret = hclge_update_wol(hdev); 12175 if (ret) 12176 dev_warn(&pdev->dev, 12177 "failed to update wol config, ret = %d\n", ret); 12178 12179 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 12180 HCLGE_DRIVER_NAME); 12181 12182 return 0; 12183 } 12184 12185 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 12186 { 12187 struct hclge_dev *hdev = ae_dev->priv; 12188 struct hclge_mac *mac = &hdev->hw.mac; 12189 12190 hclge_reset_vf_rate(hdev); 12191 hclge_clear_vf_vlan(hdev); 12192 hclge_state_uninit(hdev); 12193 hclge_ptp_uninit(hdev); 12194 hclge_uninit_rxd_adv_layout(hdev); 12195 hclge_uninit_mac_table(hdev); 12196 hclge_del_all_fd_entries(hdev); 12197 12198 if (mac->phydev) 12199 mdiobus_unregister(mac->mdio_bus); 12200 12201 /* Disable MISC vector(vector0) */ 12202 hclge_enable_vector(&hdev->misc_vector, false); 12203 synchronize_irq(hdev->misc_vector.vector_irq); 12204 12205 /* Disable all hw interrupts */ 12206 hclge_config_mac_tnl_int(hdev, false); 12207 hclge_config_nic_hw_error(hdev, false); 12208 hclge_config_rocee_ras_interrupt(hdev, false); 12209 12210 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 12211 hclge_misc_irq_uninit(hdev); 12212 hclge_devlink_uninit(hdev); 12213 hclge_pci_uninit(hdev); 12214 hclge_uninit_vport_vlan_table(hdev); 12215 mutex_destroy(&hdev->vport_lock); 12216 ae_dev->priv = NULL; 12217 } 12218 12219 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 12220 { 12221 struct hclge_vport *vport = hclge_get_vport(handle); 12222 struct hclge_dev *hdev = vport->back; 12223 12224 return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps); 12225 } 12226 12227 static void hclge_get_channels(struct hnae3_handle *handle, 12228 struct ethtool_channels *ch) 12229 { 12230 ch->max_combined = hclge_get_max_channels(handle); 12231 ch->other_count = 1; 12232 ch->max_other = 1; 12233 ch->combined_count = handle->kinfo.rss_size; 12234 } 12235 12236 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 12237 u16 *alloc_tqps, u16 *max_rss_size) 12238 { 12239 struct hclge_vport *vport = hclge_get_vport(handle); 12240 struct hclge_dev *hdev = vport->back; 12241 12242 *alloc_tqps = vport->alloc_tqps; 12243 *max_rss_size = hdev->pf_rss_size_max; 12244 } 12245 12246 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle) 12247 { 12248 struct hclge_vport *vport = hclge_get_vport(handle); 12249 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 12250 struct hclge_dev *hdev = vport->back; 12251 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 12252 u16 tc_valid[HCLGE_MAX_TC_NUM]; 12253 u16 roundup_size; 12254 unsigned int i; 12255 12256 roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size); 12257 roundup_size = ilog2(roundup_size); 12258 /* Set the RSS TC mode according to the new RSS size */ 12259 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 12260 tc_valid[i] = 0; 12261 12262 if (!(hdev->hw_tc_map & BIT(i))) 12263 continue; 12264 12265 tc_valid[i] = 1; 12266 tc_size[i] = roundup_size; 12267 tc_offset[i] = vport->nic.kinfo.rss_size * i; 12268 } 12269 12270 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 12271 tc_size); 12272 } 12273 12274 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 12275 bool rxfh_configured) 12276 { 12277 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 12278 struct hclge_vport *vport = hclge_get_vport(handle); 12279 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 12280 struct hclge_dev *hdev = vport->back; 12281 u16 cur_rss_size = kinfo->rss_size; 12282 u16 cur_tqps = kinfo->num_tqps; 12283 u32 *rss_indir; 12284 unsigned int i; 12285 int ret; 12286 12287 kinfo->req_rss_size = new_tqps_num; 12288 12289 ret = hclge_tm_vport_map_update(hdev); 12290 if (ret) { 12291 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret); 12292 return ret; 12293 } 12294 12295 ret = hclge_set_rss_tc_mode_cfg(handle); 12296 if (ret) 12297 return ret; 12298 12299 /* RSS indirection table has been configured by user */ 12300 if (rxfh_configured) 12301 goto out; 12302 12303 /* Reinitializes the rss indirect table according to the new RSS size */ 12304 rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32), 12305 GFP_KERNEL); 12306 if (!rss_indir) 12307 return -ENOMEM; 12308 12309 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 12310 rss_indir[i] = i % kinfo->rss_size; 12311 12312 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 12313 if (ret) 12314 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 12315 ret); 12316 12317 kfree(rss_indir); 12318 12319 out: 12320 if (!ret) 12321 dev_info(&hdev->pdev->dev, 12322 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 12323 cur_rss_size, kinfo->rss_size, 12324 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 12325 12326 return ret; 12327 } 12328 12329 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 12330 { 12331 struct hclge_set_led_state_cmd *req; 12332 struct hclge_desc desc; 12333 int ret; 12334 12335 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 12336 12337 req = (struct hclge_set_led_state_cmd *)desc.data; 12338 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 12339 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 12340 12341 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12342 if (ret) 12343 dev_err(&hdev->pdev->dev, 12344 "Send set led state cmd error, ret =%d\n", ret); 12345 12346 return ret; 12347 } 12348 12349 enum hclge_led_status { 12350 HCLGE_LED_OFF, 12351 HCLGE_LED_ON, 12352 HCLGE_LED_NO_CHANGE = 0xFF, 12353 }; 12354 12355 static int hclge_set_led_id(struct hnae3_handle *handle, 12356 enum ethtool_phys_id_state status) 12357 { 12358 struct hclge_vport *vport = hclge_get_vport(handle); 12359 struct hclge_dev *hdev = vport->back; 12360 12361 switch (status) { 12362 case ETHTOOL_ID_ACTIVE: 12363 return hclge_set_led_status(hdev, HCLGE_LED_ON); 12364 case ETHTOOL_ID_INACTIVE: 12365 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 12366 default: 12367 return -EINVAL; 12368 } 12369 } 12370 12371 static void hclge_get_link_mode(struct hnae3_handle *handle, 12372 unsigned long *supported, 12373 unsigned long *advertising) 12374 { 12375 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 12376 struct hclge_vport *vport = hclge_get_vport(handle); 12377 struct hclge_dev *hdev = vport->back; 12378 unsigned int idx = 0; 12379 12380 for (; idx < size; idx++) { 12381 supported[idx] = hdev->hw.mac.supported[idx]; 12382 advertising[idx] = hdev->hw.mac.advertising[idx]; 12383 } 12384 } 12385 12386 static int hclge_gro_en(struct hnae3_handle *handle, bool enable) 12387 { 12388 struct hclge_vport *vport = hclge_get_vport(handle); 12389 struct hclge_dev *hdev = vport->back; 12390 bool gro_en_old = hdev->gro_en; 12391 int ret; 12392 12393 hdev->gro_en = enable; 12394 ret = hclge_config_gro(hdev); 12395 if (ret) 12396 hdev->gro_en = gro_en_old; 12397 12398 return ret; 12399 } 12400 12401 static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport) 12402 { 12403 struct hnae3_handle *handle = &vport->nic; 12404 struct hclge_dev *hdev = vport->back; 12405 bool uc_en = false; 12406 bool mc_en = false; 12407 u8 tmp_flags; 12408 bool bc_en; 12409 int ret; 12410 12411 if (vport->last_promisc_flags != vport->overflow_promisc_flags) { 12412 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12413 vport->last_promisc_flags = vport->overflow_promisc_flags; 12414 } 12415 12416 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12417 &vport->state)) 12418 return 0; 12419 12420 /* for PF */ 12421 if (!vport->vport_id) { 12422 tmp_flags = handle->netdev_flags | vport->last_promisc_flags; 12423 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE, 12424 tmp_flags & HNAE3_MPE); 12425 if (!ret) 12426 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 12427 &vport->state); 12428 else 12429 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12430 &vport->state); 12431 return ret; 12432 } 12433 12434 /* for VF */ 12435 if (vport->vf_info.trusted) { 12436 uc_en = vport->vf_info.request_uc_en > 0 || 12437 vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE; 12438 mc_en = vport->vf_info.request_mc_en > 0 || 12439 vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE; 12440 } 12441 bc_en = vport->vf_info.request_bc_en > 0; 12442 12443 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en, 12444 mc_en, bc_en); 12445 if (ret) { 12446 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12447 return ret; 12448 } 12449 hclge_set_vport_vlan_fltr_change(vport); 12450 12451 return 0; 12452 } 12453 12454 static void hclge_sync_promisc_mode(struct hclge_dev *hdev) 12455 { 12456 struct hclge_vport *vport; 12457 int ret; 12458 u16 i; 12459 12460 for (i = 0; i < hdev->num_alloc_vport; i++) { 12461 vport = &hdev->vport[i]; 12462 12463 ret = hclge_sync_vport_promisc_mode(vport); 12464 if (ret) 12465 return; 12466 } 12467 } 12468 12469 static bool hclge_module_existed(struct hclge_dev *hdev) 12470 { 12471 struct hclge_desc desc; 12472 u32 existed; 12473 int ret; 12474 12475 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true); 12476 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12477 if (ret) { 12478 dev_err(&hdev->pdev->dev, 12479 "failed to get SFP exist state, ret = %d\n", ret); 12480 return false; 12481 } 12482 12483 existed = le32_to_cpu(desc.data[0]); 12484 12485 return existed != 0; 12486 } 12487 12488 /* need 6 bds(total 140 bytes) in one reading 12489 * return the number of bytes actually read, 0 means read failed. 12490 */ 12491 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset, 12492 u32 len, u8 *data) 12493 { 12494 struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM]; 12495 struct hclge_sfp_info_bd0_cmd *sfp_info_bd0; 12496 u16 read_len; 12497 u16 copy_len; 12498 int ret; 12499 int i; 12500 12501 /* setup all 6 bds to read module eeprom info. */ 12502 for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12503 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM, 12504 true); 12505 12506 /* bd0~bd4 need next flag */ 12507 if (i < HCLGE_SFP_INFO_CMD_NUM - 1) 12508 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12509 } 12510 12511 /* setup bd0, this bd contains offset and read length. */ 12512 sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data; 12513 sfp_info_bd0->offset = cpu_to_le16((u16)offset); 12514 read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN); 12515 sfp_info_bd0->read_len = cpu_to_le16(read_len); 12516 12517 ret = hclge_cmd_send(&hdev->hw, desc, i); 12518 if (ret) { 12519 dev_err(&hdev->pdev->dev, 12520 "failed to get SFP eeprom info, ret = %d\n", ret); 12521 return 0; 12522 } 12523 12524 /* copy sfp info from bd0 to out buffer. */ 12525 copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN); 12526 memcpy(data, sfp_info_bd0->data, copy_len); 12527 read_len = copy_len; 12528 12529 /* copy sfp info from bd1~bd5 to out buffer if needed. */ 12530 for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12531 if (read_len >= len) 12532 return read_len; 12533 12534 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN); 12535 memcpy(data + read_len, desc[i].data, copy_len); 12536 read_len += copy_len; 12537 } 12538 12539 return read_len; 12540 } 12541 12542 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset, 12543 u32 len, u8 *data) 12544 { 12545 struct hclge_vport *vport = hclge_get_vport(handle); 12546 struct hclge_dev *hdev = vport->back; 12547 u32 read_len = 0; 12548 u16 data_len; 12549 12550 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 12551 return -EOPNOTSUPP; 12552 12553 if (!hclge_module_existed(hdev)) 12554 return -ENXIO; 12555 12556 while (read_len < len) { 12557 data_len = hclge_get_sfp_eeprom_info(hdev, 12558 offset + read_len, 12559 len - read_len, 12560 data + read_len); 12561 if (!data_len) 12562 return -EIO; 12563 12564 read_len += data_len; 12565 } 12566 12567 return 0; 12568 } 12569 12570 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle, 12571 u32 *status_code) 12572 { 12573 struct hclge_vport *vport = hclge_get_vport(handle); 12574 struct hclge_dev *hdev = vport->back; 12575 struct hclge_desc desc; 12576 int ret; 12577 12578 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 12579 return -EOPNOTSUPP; 12580 12581 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true); 12582 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12583 if (ret) { 12584 dev_err(&hdev->pdev->dev, 12585 "failed to query link diagnosis info, ret = %d\n", ret); 12586 return ret; 12587 } 12588 12589 *status_code = le32_to_cpu(desc.data[0]); 12590 return 0; 12591 } 12592 12593 /* After disable sriov, VF still has some config and info need clean, 12594 * which configed by PF. 12595 */ 12596 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid) 12597 { 12598 struct hclge_dev *hdev = vport->back; 12599 struct hclge_vlan_info vlan_info; 12600 int ret; 12601 12602 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 12603 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12604 vport->need_notify = 0; 12605 vport->mps = 0; 12606 12607 /* after disable sriov, clean VF rate configured by PF */ 12608 ret = hclge_tm_qs_shaper_cfg(vport, 0); 12609 if (ret) 12610 dev_err(&hdev->pdev->dev, 12611 "failed to clean vf%d rate config, ret = %d\n", 12612 vfid, ret); 12613 12614 vlan_info.vlan_tag = 0; 12615 vlan_info.qos = 0; 12616 vlan_info.vlan_proto = ETH_P_8021Q; 12617 ret = hclge_update_port_base_vlan_cfg(vport, 12618 HNAE3_PORT_BASE_VLAN_DISABLE, 12619 &vlan_info); 12620 if (ret) 12621 dev_err(&hdev->pdev->dev, 12622 "failed to clean vf%d port base vlan, ret = %d\n", 12623 vfid, ret); 12624 12625 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false); 12626 if (ret) 12627 dev_err(&hdev->pdev->dev, 12628 "failed to clean vf%d spoof config, ret = %d\n", 12629 vfid, ret); 12630 12631 memset(&vport->vf_info, 0, sizeof(vport->vf_info)); 12632 } 12633 12634 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs) 12635 { 12636 struct hclge_dev *hdev = ae_dev->priv; 12637 struct hclge_vport *vport; 12638 int i; 12639 12640 for (i = 0; i < num_vfs; i++) { 12641 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 12642 12643 hclge_clear_vport_vf_info(vport, i); 12644 } 12645 } 12646 12647 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode, 12648 u8 *priority) 12649 { 12650 struct hclge_vport *vport = hclge_get_vport(h); 12651 12652 if (dscp >= HNAE3_MAX_DSCP) 12653 return -EINVAL; 12654 12655 if (tc_mode) 12656 *tc_mode = vport->nic.kinfo.tc_map_mode; 12657 if (priority) 12658 *priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 : 12659 vport->nic.kinfo.dscp_prio[dscp]; 12660 12661 return 0; 12662 } 12663 12664 static const struct hnae3_ae_ops hclge_ops = { 12665 .init_ae_dev = hclge_init_ae_dev, 12666 .uninit_ae_dev = hclge_uninit_ae_dev, 12667 .reset_prepare = hclge_reset_prepare_general, 12668 .reset_done = hclge_reset_done, 12669 .init_client_instance = hclge_init_client_instance, 12670 .uninit_client_instance = hclge_uninit_client_instance, 12671 .map_ring_to_vector = hclge_map_ring_to_vector, 12672 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 12673 .get_vector = hclge_get_vector, 12674 .put_vector = hclge_put_vector, 12675 .set_promisc_mode = hclge_set_promisc_mode, 12676 .request_update_promisc_mode = hclge_request_update_promisc_mode, 12677 .set_loopback = hclge_set_loopback, 12678 .start = hclge_ae_start, 12679 .stop = hclge_ae_stop, 12680 .client_start = hclge_client_start, 12681 .client_stop = hclge_client_stop, 12682 .get_status = hclge_get_status, 12683 .get_ksettings_an_result = hclge_get_ksettings_an_result, 12684 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 12685 .get_media_type = hclge_get_media_type, 12686 .check_port_speed = hclge_check_port_speed, 12687 .get_fec_stats = hclge_get_fec_stats, 12688 .get_fec = hclge_get_fec, 12689 .set_fec = hclge_set_fec, 12690 .get_rss_key_size = hclge_comm_get_rss_key_size, 12691 .get_rss = hclge_get_rss, 12692 .set_rss = hclge_set_rss, 12693 .set_rss_tuple = hclge_set_rss_tuple, 12694 .get_rss_tuple = hclge_get_rss_tuple, 12695 .get_tc_size = hclge_get_tc_size, 12696 .get_mac_addr = hclge_get_mac_addr, 12697 .set_mac_addr = hclge_set_mac_addr, 12698 .do_ioctl = hclge_do_ioctl, 12699 .add_uc_addr = hclge_add_uc_addr, 12700 .rm_uc_addr = hclge_rm_uc_addr, 12701 .add_mc_addr = hclge_add_mc_addr, 12702 .rm_mc_addr = hclge_rm_mc_addr, 12703 .set_autoneg = hclge_set_autoneg, 12704 .get_autoneg = hclge_get_autoneg, 12705 .restart_autoneg = hclge_restart_autoneg, 12706 .halt_autoneg = hclge_halt_autoneg, 12707 .get_pauseparam = hclge_get_pauseparam, 12708 .set_pauseparam = hclge_set_pauseparam, 12709 .set_mtu = hclge_set_mtu, 12710 .reset_queue = hclge_reset_tqp, 12711 .get_stats = hclge_get_stats, 12712 .get_mac_stats = hclge_get_mac_stat, 12713 .update_stats = hclge_update_stats, 12714 .get_strings = hclge_get_strings, 12715 .get_sset_count = hclge_get_sset_count, 12716 .get_fw_version = hclge_get_fw_version, 12717 .get_mdix_mode = hclge_get_mdix_mode, 12718 .enable_vlan_filter = hclge_enable_vlan_filter, 12719 .set_vlan_filter = hclge_set_vlan_filter, 12720 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 12721 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 12722 .reset_event = hclge_reset_event, 12723 .get_reset_level = hclge_get_reset_level, 12724 .set_default_reset_request = hclge_set_def_reset_request, 12725 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 12726 .set_channels = hclge_set_channels, 12727 .get_channels = hclge_get_channels, 12728 .get_regs_len = hclge_get_regs_len, 12729 .get_regs = hclge_get_regs, 12730 .set_led_id = hclge_set_led_id, 12731 .get_link_mode = hclge_get_link_mode, 12732 .add_fd_entry = hclge_add_fd_entry, 12733 .del_fd_entry = hclge_del_fd_entry, 12734 .get_fd_rule_cnt = hclge_get_fd_rule_cnt, 12735 .get_fd_rule_info = hclge_get_fd_rule_info, 12736 .get_fd_all_rules = hclge_get_all_rules, 12737 .enable_fd = hclge_enable_fd, 12738 .add_arfs_entry = hclge_add_fd_entry_by_arfs, 12739 .dbg_read_cmd = hclge_dbg_read_cmd, 12740 .handle_hw_ras_error = hclge_handle_hw_ras_error, 12741 .get_hw_reset_stat = hclge_get_hw_reset_stat, 12742 .ae_dev_resetting = hclge_ae_dev_resetting, 12743 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt, 12744 .set_gro_en = hclge_gro_en, 12745 .get_global_queue_id = hclge_covert_handle_qid_global, 12746 .set_timer_task = hclge_set_timer_task, 12747 .mac_connect_phy = hclge_mac_connect_phy, 12748 .mac_disconnect_phy = hclge_mac_disconnect_phy, 12749 .get_vf_config = hclge_get_vf_config, 12750 .set_vf_link_state = hclge_set_vf_link_state, 12751 .set_vf_spoofchk = hclge_set_vf_spoofchk, 12752 .set_vf_trust = hclge_set_vf_trust, 12753 .set_vf_rate = hclge_set_vf_rate, 12754 .set_vf_mac = hclge_set_vf_mac, 12755 .get_module_eeprom = hclge_get_module_eeprom, 12756 .get_cmdq_stat = hclge_get_cmdq_stat, 12757 .add_cls_flower = hclge_add_cls_flower, 12758 .del_cls_flower = hclge_del_cls_flower, 12759 .cls_flower_active = hclge_is_cls_flower_active, 12760 .get_phy_link_ksettings = hclge_get_phy_link_ksettings, 12761 .set_phy_link_ksettings = hclge_set_phy_link_ksettings, 12762 .set_tx_hwts_info = hclge_ptp_set_tx_info, 12763 .get_rx_hwts = hclge_ptp_get_rx_hwts, 12764 .get_ts_info = hclge_ptp_get_ts_info, 12765 .get_link_diagnosis_info = hclge_get_link_diagnosis_info, 12766 .clean_vf_config = hclge_clean_vport_config, 12767 .get_dscp_prio = hclge_get_dscp_prio, 12768 .get_wol = hclge_get_wol, 12769 .set_wol = hclge_set_wol, 12770 }; 12771 12772 static struct hnae3_ae_algo ae_algo = { 12773 .ops = &hclge_ops, 12774 .pdev_id_table = ae_algo_pci_tbl, 12775 }; 12776 12777 static int __init hclge_init(void) 12778 { 12779 pr_info("%s is initializing\n", HCLGE_NAME); 12780 12781 hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGE_NAME); 12782 if (!hclge_wq) { 12783 pr_err("%s: failed to create workqueue\n", HCLGE_NAME); 12784 return -ENOMEM; 12785 } 12786 12787 hnae3_register_ae_algo(&ae_algo); 12788 12789 return 0; 12790 } 12791 12792 static void __exit hclge_exit(void) 12793 { 12794 hnae3_unregister_ae_algo_prepare(&ae_algo); 12795 hnae3_unregister_ae_algo(&ae_algo); 12796 destroy_workqueue(hclge_wq); 12797 } 12798 module_init(hclge_init); 12799 module_exit(hclge_exit); 12800 12801 MODULE_LICENSE("GPL"); 12802 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 12803 MODULE_DESCRIPTION("HCLGE Driver"); 12804 MODULE_VERSION(HCLGE_MOD_VERSION); 12805