1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/pci.h> 13 #include <linux/platform_device.h> 14 #include <linux/if_vlan.h> 15 #include <net/rtnetlink.h> 16 #include "hclge_cmd.h" 17 #include "hclge_dcb.h" 18 #include "hclge_main.h" 19 #include "hclge_mbx.h" 20 #include "hclge_mdio.h" 21 #include "hclge_tm.h" 22 #include "hnae3.h" 23 24 #define HCLGE_NAME "hclge" 25 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset)))) 26 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f)) 27 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f)) 28 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f)) 29 30 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev, 31 enum hclge_mta_dmac_sel_type mta_mac_sel, 32 bool enable); 33 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu); 34 static int hclge_init_vlan_config(struct hclge_dev *hdev); 35 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 36 37 static struct hnae3_ae_algo ae_algo; 38 39 static const struct pci_device_id ae_algo_pci_tbl[] = { 40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 47 /* required last entry */ 48 {0, } 49 }; 50 51 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 52 53 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 54 "Mac Loopback test", 55 "Serdes Loopback test", 56 "Phy Loopback test" 57 }; 58 59 static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = { 60 {"igu_rx_oversize_pkt", 61 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)}, 62 {"igu_rx_undersize_pkt", 63 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)}, 64 {"igu_rx_out_all_pkt", 65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)}, 66 {"igu_rx_uni_pkt", 67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)}, 68 {"igu_rx_multi_pkt", 69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)}, 70 {"igu_rx_broad_pkt", 71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)}, 72 {"egu_tx_out_all_pkt", 73 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)}, 74 {"egu_tx_uni_pkt", 75 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)}, 76 {"egu_tx_multi_pkt", 77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)}, 78 {"egu_tx_broad_pkt", 79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)}, 80 {"ssu_ppp_mac_key_num", 81 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)}, 82 {"ssu_ppp_host_key_num", 83 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)}, 84 {"ppp_ssu_mac_rlt_num", 85 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)}, 86 {"ppp_ssu_host_rlt_num", 87 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)}, 88 {"ssu_tx_in_num", 89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)}, 90 {"ssu_tx_out_num", 91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)}, 92 {"ssu_rx_in_num", 93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)}, 94 {"ssu_rx_out_num", 95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)} 96 }; 97 98 static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = { 99 {"igu_rx_err_pkt", 100 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)}, 101 {"igu_rx_no_eof_pkt", 102 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)}, 103 {"igu_rx_no_sof_pkt", 104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)}, 105 {"egu_tx_1588_pkt", 106 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)}, 107 {"ssu_full_drop_num", 108 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)}, 109 {"ssu_part_drop_num", 110 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)}, 111 {"ppp_key_drop_num", 112 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)}, 113 {"ppp_rlt_drop_num", 114 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)}, 115 {"ssu_key_drop_num", 116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)}, 117 {"pkt_curr_buf_cnt", 118 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)}, 119 {"qcn_fb_rcv_cnt", 120 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)}, 121 {"qcn_fb_drop_cnt", 122 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)}, 123 {"qcn_fb_invaild_cnt", 124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)}, 125 {"rx_packet_tc0_in_cnt", 126 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)}, 127 {"rx_packet_tc1_in_cnt", 128 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)}, 129 {"rx_packet_tc2_in_cnt", 130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)}, 131 {"rx_packet_tc3_in_cnt", 132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)}, 133 {"rx_packet_tc4_in_cnt", 134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)}, 135 {"rx_packet_tc5_in_cnt", 136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)}, 137 {"rx_packet_tc6_in_cnt", 138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)}, 139 {"rx_packet_tc7_in_cnt", 140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)}, 141 {"rx_packet_tc0_out_cnt", 142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)}, 143 {"rx_packet_tc1_out_cnt", 144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)}, 145 {"rx_packet_tc2_out_cnt", 146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)}, 147 {"rx_packet_tc3_out_cnt", 148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)}, 149 {"rx_packet_tc4_out_cnt", 150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)}, 151 {"rx_packet_tc5_out_cnt", 152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)}, 153 {"rx_packet_tc6_out_cnt", 154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)}, 155 {"rx_packet_tc7_out_cnt", 156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)}, 157 {"tx_packet_tc0_in_cnt", 158 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)}, 159 {"tx_packet_tc1_in_cnt", 160 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)}, 161 {"tx_packet_tc2_in_cnt", 162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)}, 163 {"tx_packet_tc3_in_cnt", 164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)}, 165 {"tx_packet_tc4_in_cnt", 166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)}, 167 {"tx_packet_tc5_in_cnt", 168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)}, 169 {"tx_packet_tc6_in_cnt", 170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)}, 171 {"tx_packet_tc7_in_cnt", 172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)}, 173 {"tx_packet_tc0_out_cnt", 174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)}, 175 {"tx_packet_tc1_out_cnt", 176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)}, 177 {"tx_packet_tc2_out_cnt", 178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)}, 179 {"tx_packet_tc3_out_cnt", 180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)}, 181 {"tx_packet_tc4_out_cnt", 182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)}, 183 {"tx_packet_tc5_out_cnt", 184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)}, 185 {"tx_packet_tc6_out_cnt", 186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)}, 187 {"tx_packet_tc7_out_cnt", 188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)}, 189 {"pkt_curr_buf_tc0_cnt", 190 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)}, 191 {"pkt_curr_buf_tc1_cnt", 192 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)}, 193 {"pkt_curr_buf_tc2_cnt", 194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)}, 195 {"pkt_curr_buf_tc3_cnt", 196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)}, 197 {"pkt_curr_buf_tc4_cnt", 198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)}, 199 {"pkt_curr_buf_tc5_cnt", 200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)}, 201 {"pkt_curr_buf_tc6_cnt", 202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)}, 203 {"pkt_curr_buf_tc7_cnt", 204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)}, 205 {"mb_uncopy_num", 206 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)}, 207 {"lo_pri_unicast_rlt_drop_num", 208 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)}, 209 {"hi_pri_multicast_rlt_drop_num", 210 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)}, 211 {"lo_pri_multicast_rlt_drop_num", 212 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)}, 213 {"rx_oq_drop_pkt_cnt", 214 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)}, 215 {"tx_oq_drop_pkt_cnt", 216 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)}, 217 {"nic_l2_err_drop_pkt_cnt", 218 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)}, 219 {"roc_l2_err_drop_pkt_cnt", 220 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)} 221 }; 222 223 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 224 {"mac_tx_mac_pause_num", 225 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 226 {"mac_rx_mac_pause_num", 227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 228 {"mac_tx_pfc_pri0_pkt_num", 229 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 230 {"mac_tx_pfc_pri1_pkt_num", 231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 232 {"mac_tx_pfc_pri2_pkt_num", 233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 234 {"mac_tx_pfc_pri3_pkt_num", 235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 236 {"mac_tx_pfc_pri4_pkt_num", 237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 238 {"mac_tx_pfc_pri5_pkt_num", 239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 240 {"mac_tx_pfc_pri6_pkt_num", 241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 242 {"mac_tx_pfc_pri7_pkt_num", 243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 244 {"mac_rx_pfc_pri0_pkt_num", 245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 246 {"mac_rx_pfc_pri1_pkt_num", 247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 248 {"mac_rx_pfc_pri2_pkt_num", 249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 250 {"mac_rx_pfc_pri3_pkt_num", 251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 252 {"mac_rx_pfc_pri4_pkt_num", 253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 254 {"mac_rx_pfc_pri5_pkt_num", 255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 256 {"mac_rx_pfc_pri6_pkt_num", 257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 258 {"mac_rx_pfc_pri7_pkt_num", 259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 260 {"mac_tx_total_pkt_num", 261 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 262 {"mac_tx_total_oct_num", 263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 264 {"mac_tx_good_pkt_num", 265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 266 {"mac_tx_bad_pkt_num", 267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 268 {"mac_tx_good_oct_num", 269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 270 {"mac_tx_bad_oct_num", 271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 272 {"mac_tx_uni_pkt_num", 273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 274 {"mac_tx_multi_pkt_num", 275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 276 {"mac_tx_broad_pkt_num", 277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 278 {"mac_tx_undersize_pkt_num", 279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 280 {"mac_tx_oversize_pkt_num", 281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 282 {"mac_tx_64_oct_pkt_num", 283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 284 {"mac_tx_65_127_oct_pkt_num", 285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 286 {"mac_tx_128_255_oct_pkt_num", 287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 288 {"mac_tx_256_511_oct_pkt_num", 289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 290 {"mac_tx_512_1023_oct_pkt_num", 291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 292 {"mac_tx_1024_1518_oct_pkt_num", 293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 294 {"mac_tx_1519_2047_oct_pkt_num", 295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 296 {"mac_tx_2048_4095_oct_pkt_num", 297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 298 {"mac_tx_4096_8191_oct_pkt_num", 299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 300 {"mac_tx_8192_9216_oct_pkt_num", 301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 302 {"mac_tx_9217_12287_oct_pkt_num", 303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 304 {"mac_tx_12288_16383_oct_pkt_num", 305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 306 {"mac_tx_1519_max_good_pkt_num", 307 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 308 {"mac_tx_1519_max_bad_pkt_num", 309 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 310 {"mac_rx_total_pkt_num", 311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 312 {"mac_rx_total_oct_num", 313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 314 {"mac_rx_good_pkt_num", 315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 316 {"mac_rx_bad_pkt_num", 317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 318 {"mac_rx_good_oct_num", 319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 320 {"mac_rx_bad_oct_num", 321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 322 {"mac_rx_uni_pkt_num", 323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 324 {"mac_rx_multi_pkt_num", 325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 326 {"mac_rx_broad_pkt_num", 327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 328 {"mac_rx_undersize_pkt_num", 329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 330 {"mac_rx_oversize_pkt_num", 331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 332 {"mac_rx_64_oct_pkt_num", 333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 334 {"mac_rx_65_127_oct_pkt_num", 335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 336 {"mac_rx_128_255_oct_pkt_num", 337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 338 {"mac_rx_256_511_oct_pkt_num", 339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 340 {"mac_rx_512_1023_oct_pkt_num", 341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 342 {"mac_rx_1024_1518_oct_pkt_num", 343 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 344 {"mac_rx_1519_2047_oct_pkt_num", 345 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 346 {"mac_rx_2048_4095_oct_pkt_num", 347 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 348 {"mac_rx_4096_8191_oct_pkt_num", 349 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 350 {"mac_rx_8192_9216_oct_pkt_num", 351 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 352 {"mac_rx_9217_12287_oct_pkt_num", 353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 354 {"mac_rx_12288_16383_oct_pkt_num", 355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 356 {"mac_rx_1519_max_good_pkt_num", 357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 358 {"mac_rx_1519_max_bad_pkt_num", 359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 360 361 {"mac_tx_fragment_pkt_num", 362 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 363 {"mac_tx_undermin_pkt_num", 364 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 365 {"mac_tx_jabber_pkt_num", 366 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 367 {"mac_tx_err_all_pkt_num", 368 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 369 {"mac_tx_from_app_good_pkt_num", 370 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 371 {"mac_tx_from_app_bad_pkt_num", 372 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 373 {"mac_rx_fragment_pkt_num", 374 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 375 {"mac_rx_undermin_pkt_num", 376 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 377 {"mac_rx_jabber_pkt_num", 378 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 379 {"mac_rx_fcs_err_pkt_num", 380 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 381 {"mac_rx_send_app_good_pkt_num", 382 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 383 {"mac_rx_send_app_bad_pkt_num", 384 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 385 }; 386 387 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 388 { 389 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 390 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP), 391 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)), 392 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)), 393 .i_port_bitmap = 0x1, 394 }, 395 }; 396 397 static int hclge_64_bit_update_stats(struct hclge_dev *hdev) 398 { 399 #define HCLGE_64_BIT_CMD_NUM 5 400 #define HCLGE_64_BIT_RTN_DATANUM 4 401 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats); 402 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM]; 403 __le64 *desc_data; 404 int i, k, n; 405 int ret; 406 407 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true); 408 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM); 409 if (ret) { 410 dev_err(&hdev->pdev->dev, 411 "Get 64 bit pkt stats fail, status = %d.\n", ret); 412 return ret; 413 } 414 415 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) { 416 if (unlikely(i == 0)) { 417 desc_data = (__le64 *)(&desc[i].data[0]); 418 n = HCLGE_64_BIT_RTN_DATANUM - 1; 419 } else { 420 desc_data = (__le64 *)(&desc[i]); 421 n = HCLGE_64_BIT_RTN_DATANUM; 422 } 423 for (k = 0; k < n; k++) { 424 *data++ += le64_to_cpu(*desc_data); 425 desc_data++; 426 } 427 } 428 429 return 0; 430 } 431 432 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats) 433 { 434 stats->pkt_curr_buf_cnt = 0; 435 stats->pkt_curr_buf_tc0_cnt = 0; 436 stats->pkt_curr_buf_tc1_cnt = 0; 437 stats->pkt_curr_buf_tc2_cnt = 0; 438 stats->pkt_curr_buf_tc3_cnt = 0; 439 stats->pkt_curr_buf_tc4_cnt = 0; 440 stats->pkt_curr_buf_tc5_cnt = 0; 441 stats->pkt_curr_buf_tc6_cnt = 0; 442 stats->pkt_curr_buf_tc7_cnt = 0; 443 } 444 445 static int hclge_32_bit_update_stats(struct hclge_dev *hdev) 446 { 447 #define HCLGE_32_BIT_CMD_NUM 8 448 #define HCLGE_32_BIT_RTN_DATANUM 8 449 450 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM]; 451 struct hclge_32_bit_stats *all_32_bit_stats; 452 __le32 *desc_data; 453 int i, k, n; 454 u64 *data; 455 int ret; 456 457 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats; 458 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt); 459 460 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true); 461 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM); 462 if (ret) { 463 dev_err(&hdev->pdev->dev, 464 "Get 32 bit pkt stats fail, status = %d.\n", ret); 465 466 return ret; 467 } 468 469 hclge_reset_partial_32bit_counter(all_32_bit_stats); 470 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) { 471 if (unlikely(i == 0)) { 472 __le16 *desc_data_16bit; 473 474 all_32_bit_stats->igu_rx_err_pkt += 475 le32_to_cpu(desc[i].data[0]); 476 477 desc_data_16bit = (__le16 *)&desc[i].data[1]; 478 all_32_bit_stats->igu_rx_no_eof_pkt += 479 le16_to_cpu(*desc_data_16bit); 480 481 desc_data_16bit++; 482 all_32_bit_stats->igu_rx_no_sof_pkt += 483 le16_to_cpu(*desc_data_16bit); 484 485 desc_data = &desc[i].data[2]; 486 n = HCLGE_32_BIT_RTN_DATANUM - 4; 487 } else { 488 desc_data = (__le32 *)&desc[i]; 489 n = HCLGE_32_BIT_RTN_DATANUM; 490 } 491 for (k = 0; k < n; k++) { 492 *data++ += le32_to_cpu(*desc_data); 493 desc_data++; 494 } 495 } 496 497 return 0; 498 } 499 500 static int hclge_mac_update_stats(struct hclge_dev *hdev) 501 { 502 #define HCLGE_MAC_CMD_NUM 21 503 #define HCLGE_RTN_DATA_NUM 4 504 505 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats); 506 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 507 __le64 *desc_data; 508 int i, k, n; 509 int ret; 510 511 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 512 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 513 if (ret) { 514 dev_err(&hdev->pdev->dev, 515 "Get MAC pkt stats fail, status = %d.\n", ret); 516 517 return ret; 518 } 519 520 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) { 521 if (unlikely(i == 0)) { 522 desc_data = (__le64 *)(&desc[i].data[0]); 523 n = HCLGE_RTN_DATA_NUM - 2; 524 } else { 525 desc_data = (__le64 *)(&desc[i]); 526 n = HCLGE_RTN_DATA_NUM; 527 } 528 for (k = 0; k < n; k++) { 529 *data++ += le64_to_cpu(*desc_data); 530 desc_data++; 531 } 532 } 533 534 return 0; 535 } 536 537 static int hclge_tqps_update_stats(struct hnae3_handle *handle) 538 { 539 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 540 struct hclge_vport *vport = hclge_get_vport(handle); 541 struct hclge_dev *hdev = vport->back; 542 struct hnae3_queue *queue; 543 struct hclge_desc desc[1]; 544 struct hclge_tqp *tqp; 545 int ret, i; 546 547 for (i = 0; i < kinfo->num_tqps; i++) { 548 queue = handle->kinfo.tqp[i]; 549 tqp = container_of(queue, struct hclge_tqp, q); 550 /* command : HCLGE_OPC_QUERY_IGU_STAT */ 551 hclge_cmd_setup_basic_desc(&desc[0], 552 HCLGE_OPC_QUERY_RX_STATUS, 553 true); 554 555 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff)); 556 ret = hclge_cmd_send(&hdev->hw, desc, 1); 557 if (ret) { 558 dev_err(&hdev->pdev->dev, 559 "Query tqp stat fail, status = %d,queue = %d\n", 560 ret, i); 561 return ret; 562 } 563 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += 564 le32_to_cpu(desc[0].data[1]); 565 } 566 567 for (i = 0; i < kinfo->num_tqps; i++) { 568 queue = handle->kinfo.tqp[i]; 569 tqp = container_of(queue, struct hclge_tqp, q); 570 /* command : HCLGE_OPC_QUERY_IGU_STAT */ 571 hclge_cmd_setup_basic_desc(&desc[0], 572 HCLGE_OPC_QUERY_TX_STATUS, 573 true); 574 575 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff)); 576 ret = hclge_cmd_send(&hdev->hw, desc, 1); 577 if (ret) { 578 dev_err(&hdev->pdev->dev, 579 "Query tqp stat fail, status = %d,queue = %d\n", 580 ret, i); 581 return ret; 582 } 583 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += 584 le32_to_cpu(desc[0].data[1]); 585 } 586 587 return 0; 588 } 589 590 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data) 591 { 592 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 593 struct hclge_tqp *tqp; 594 u64 *buff = data; 595 int i; 596 597 for (i = 0; i < kinfo->num_tqps; i++) { 598 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q); 599 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; 600 } 601 602 for (i = 0; i < kinfo->num_tqps; i++) { 603 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q); 604 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; 605 } 606 607 return buff; 608 } 609 610 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset) 611 { 612 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 613 614 return kinfo->num_tqps * (2); 615 } 616 617 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data) 618 { 619 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 620 u8 *buff = data; 621 int i = 0; 622 623 for (i = 0; i < kinfo->num_tqps; i++) { 624 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i], 625 struct hclge_tqp, q); 626 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd", 627 tqp->index); 628 buff = buff + ETH_GSTRING_LEN; 629 } 630 631 for (i = 0; i < kinfo->num_tqps; i++) { 632 struct hclge_tqp *tqp = container_of(kinfo->tqp[i], 633 struct hclge_tqp, q); 634 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd", 635 tqp->index); 636 buff = buff + ETH_GSTRING_LEN; 637 } 638 639 return buff; 640 } 641 642 static u64 *hclge_comm_get_stats(void *comm_stats, 643 const struct hclge_comm_stats_str strs[], 644 int size, u64 *data) 645 { 646 u64 *buf = data; 647 u32 i; 648 649 for (i = 0; i < size; i++) 650 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset); 651 652 return buf + size; 653 } 654 655 static u8 *hclge_comm_get_strings(u32 stringset, 656 const struct hclge_comm_stats_str strs[], 657 int size, u8 *data) 658 { 659 char *buff = (char *)data; 660 u32 i; 661 662 if (stringset != ETH_SS_STATS) 663 return buff; 664 665 for (i = 0; i < size; i++) { 666 snprintf(buff, ETH_GSTRING_LEN, 667 strs[i].desc); 668 buff = buff + ETH_GSTRING_LEN; 669 } 670 671 return (u8 *)buff; 672 } 673 674 static void hclge_update_netstat(struct hclge_hw_stats *hw_stats, 675 struct net_device_stats *net_stats) 676 { 677 net_stats->tx_dropped = 0; 678 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num; 679 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num; 680 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num; 681 682 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num; 683 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num; 684 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt; 685 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt; 686 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num; 687 688 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num; 689 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num; 690 691 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num; 692 net_stats->rx_length_errors = 693 hw_stats->mac_stats.mac_rx_undersize_pkt_num; 694 net_stats->rx_length_errors += 695 hw_stats->mac_stats.mac_rx_oversize_pkt_num; 696 net_stats->rx_over_errors = 697 hw_stats->mac_stats.mac_rx_oversize_pkt_num; 698 } 699 700 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 701 { 702 struct hnae3_handle *handle; 703 int status; 704 705 handle = &hdev->vport[0].nic; 706 if (handle->client) { 707 status = hclge_tqps_update_stats(handle); 708 if (status) { 709 dev_err(&hdev->pdev->dev, 710 "Update TQPS stats fail, status = %d.\n", 711 status); 712 } 713 } 714 715 status = hclge_mac_update_stats(hdev); 716 if (status) 717 dev_err(&hdev->pdev->dev, 718 "Update MAC stats fail, status = %d.\n", status); 719 720 status = hclge_32_bit_update_stats(hdev); 721 if (status) 722 dev_err(&hdev->pdev->dev, 723 "Update 32 bit stats fail, status = %d.\n", 724 status); 725 726 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats); 727 } 728 729 static void hclge_update_stats(struct hnae3_handle *handle, 730 struct net_device_stats *net_stats) 731 { 732 struct hclge_vport *vport = hclge_get_vport(handle); 733 struct hclge_dev *hdev = vport->back; 734 struct hclge_hw_stats *hw_stats = &hdev->hw_stats; 735 int status; 736 737 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 738 return; 739 740 status = hclge_mac_update_stats(hdev); 741 if (status) 742 dev_err(&hdev->pdev->dev, 743 "Update MAC stats fail, status = %d.\n", 744 status); 745 746 status = hclge_32_bit_update_stats(hdev); 747 if (status) 748 dev_err(&hdev->pdev->dev, 749 "Update 32 bit stats fail, status = %d.\n", 750 status); 751 752 status = hclge_64_bit_update_stats(hdev); 753 if (status) 754 dev_err(&hdev->pdev->dev, 755 "Update 64 bit stats fail, status = %d.\n", 756 status); 757 758 status = hclge_tqps_update_stats(handle); 759 if (status) 760 dev_err(&hdev->pdev->dev, 761 "Update TQPS stats fail, status = %d.\n", 762 status); 763 764 hclge_update_netstat(hw_stats, net_stats); 765 766 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 767 } 768 769 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 770 { 771 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7 772 773 struct hclge_vport *vport = hclge_get_vport(handle); 774 struct hclge_dev *hdev = vport->back; 775 int count = 0; 776 777 /* Loopback test support rules: 778 * mac: only GE mode support 779 * serdes: all mac mode will support include GE/XGE/LGE/CGE 780 * phy: only support when phy device exist on board 781 */ 782 if (stringset == ETH_SS_TEST) { 783 /* clear loopback bit flags at first */ 784 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 785 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 786 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 787 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 788 count += 1; 789 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK; 790 } else { 791 count = -EOPNOTSUPP; 792 } 793 } else if (stringset == ETH_SS_STATS) { 794 count = ARRAY_SIZE(g_mac_stats_string) + 795 ARRAY_SIZE(g_all_32bit_stats_string) + 796 ARRAY_SIZE(g_all_64bit_stats_string) + 797 hclge_tqps_get_sset_count(handle, stringset); 798 } 799 800 return count; 801 } 802 803 static void hclge_get_strings(struct hnae3_handle *handle, 804 u32 stringset, 805 u8 *data) 806 { 807 u8 *p = (char *)data; 808 int size; 809 810 if (stringset == ETH_SS_STATS) { 811 size = ARRAY_SIZE(g_mac_stats_string); 812 p = hclge_comm_get_strings(stringset, 813 g_mac_stats_string, 814 size, 815 p); 816 size = ARRAY_SIZE(g_all_32bit_stats_string); 817 p = hclge_comm_get_strings(stringset, 818 g_all_32bit_stats_string, 819 size, 820 p); 821 size = ARRAY_SIZE(g_all_64bit_stats_string); 822 p = hclge_comm_get_strings(stringset, 823 g_all_64bit_stats_string, 824 size, 825 p); 826 p = hclge_tqps_get_strings(handle, p); 827 } else if (stringset == ETH_SS_TEST) { 828 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) { 829 memcpy(p, 830 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC], 831 ETH_GSTRING_LEN); 832 p += ETH_GSTRING_LEN; 833 } 834 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) { 835 memcpy(p, 836 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES], 837 ETH_GSTRING_LEN); 838 p += ETH_GSTRING_LEN; 839 } 840 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 841 memcpy(p, 842 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY], 843 ETH_GSTRING_LEN); 844 p += ETH_GSTRING_LEN; 845 } 846 } 847 } 848 849 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 850 { 851 struct hclge_vport *vport = hclge_get_vport(handle); 852 struct hclge_dev *hdev = vport->back; 853 u64 *p; 854 855 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats, 856 g_mac_stats_string, 857 ARRAY_SIZE(g_mac_stats_string), 858 data); 859 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats, 860 g_all_32bit_stats_string, 861 ARRAY_SIZE(g_all_32bit_stats_string), 862 p); 863 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats, 864 g_all_64bit_stats_string, 865 ARRAY_SIZE(g_all_64bit_stats_string), 866 p); 867 p = hclge_tqps_get_stats(handle, p); 868 } 869 870 static int hclge_parse_func_status(struct hclge_dev *hdev, 871 struct hclge_func_status_cmd *status) 872 { 873 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 874 return -EINVAL; 875 876 /* Set the pf to main pf */ 877 if (status->pf_state & HCLGE_PF_STATE_MAIN) 878 hdev->flag |= HCLGE_FLAG_MAIN; 879 else 880 hdev->flag &= ~HCLGE_FLAG_MAIN; 881 882 return 0; 883 } 884 885 static int hclge_query_function_status(struct hclge_dev *hdev) 886 { 887 struct hclge_func_status_cmd *req; 888 struct hclge_desc desc; 889 int timeout = 0; 890 int ret; 891 892 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 893 req = (struct hclge_func_status_cmd *)desc.data; 894 895 do { 896 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 897 if (ret) { 898 dev_err(&hdev->pdev->dev, 899 "query function status failed %d.\n", 900 ret); 901 902 return ret; 903 } 904 905 /* Check pf reset is done */ 906 if (req->pf_state) 907 break; 908 usleep_range(1000, 2000); 909 } while (timeout++ < 5); 910 911 ret = hclge_parse_func_status(hdev, req); 912 913 return ret; 914 } 915 916 static int hclge_query_pf_resource(struct hclge_dev *hdev) 917 { 918 struct hclge_pf_res_cmd *req; 919 struct hclge_desc desc; 920 int ret; 921 922 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 923 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 924 if (ret) { 925 dev_err(&hdev->pdev->dev, 926 "query pf resource failed %d.\n", ret); 927 return ret; 928 } 929 930 req = (struct hclge_pf_res_cmd *)desc.data; 931 hdev->num_tqps = __le16_to_cpu(req->tqp_num); 932 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 933 934 if (hnae3_dev_roce_supported(hdev)) { 935 hdev->num_roce_msi = 936 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number), 937 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); 938 939 /* PF should have NIC vectors and Roce vectors, 940 * NIC vectors are queued before Roce vectors. 941 */ 942 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET; 943 } else { 944 hdev->num_msi = 945 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number), 946 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); 947 } 948 949 return 0; 950 } 951 952 static int hclge_parse_speed(int speed_cmd, int *speed) 953 { 954 switch (speed_cmd) { 955 case 6: 956 *speed = HCLGE_MAC_SPEED_10M; 957 break; 958 case 7: 959 *speed = HCLGE_MAC_SPEED_100M; 960 break; 961 case 0: 962 *speed = HCLGE_MAC_SPEED_1G; 963 break; 964 case 1: 965 *speed = HCLGE_MAC_SPEED_10G; 966 break; 967 case 2: 968 *speed = HCLGE_MAC_SPEED_25G; 969 break; 970 case 3: 971 *speed = HCLGE_MAC_SPEED_40G; 972 break; 973 case 4: 974 *speed = HCLGE_MAC_SPEED_50G; 975 break; 976 case 5: 977 *speed = HCLGE_MAC_SPEED_100G; 978 break; 979 default: 980 return -EINVAL; 981 } 982 983 return 0; 984 } 985 986 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 987 u8 speed_ability) 988 { 989 unsigned long *supported = hdev->hw.mac.supported; 990 991 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 992 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 993 supported); 994 995 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 996 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 997 supported); 998 999 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1000 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1001 supported); 1002 1003 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1004 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 1005 supported); 1006 1007 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1008 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 1009 supported); 1010 1011 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported); 1012 set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1013 } 1014 1015 static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability) 1016 { 1017 u8 media_type = hdev->hw.mac.media_type; 1018 1019 if (media_type != HNAE3_MEDIA_TYPE_FIBER) 1020 return; 1021 1022 hclge_parse_fiber_link_mode(hdev, speed_ability); 1023 } 1024 1025 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1026 { 1027 struct hclge_cfg_param_cmd *req; 1028 u64 mac_addr_tmp_high; 1029 u64 mac_addr_tmp; 1030 int i; 1031 1032 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1033 1034 /* get the configuration */ 1035 cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1036 HCLGE_CFG_VMDQ_M, 1037 HCLGE_CFG_VMDQ_S); 1038 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1039 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1040 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1041 HCLGE_CFG_TQP_DESC_N_M, 1042 HCLGE_CFG_TQP_DESC_N_S); 1043 1044 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1045 HCLGE_CFG_PHY_ADDR_M, 1046 HCLGE_CFG_PHY_ADDR_S); 1047 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1048 HCLGE_CFG_MEDIA_TP_M, 1049 HCLGE_CFG_MEDIA_TP_S); 1050 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1051 HCLGE_CFG_RX_BUF_LEN_M, 1052 HCLGE_CFG_RX_BUF_LEN_S); 1053 /* get mac_address */ 1054 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1055 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1056 HCLGE_CFG_MAC_ADDR_H_M, 1057 HCLGE_CFG_MAC_ADDR_H_S); 1058 1059 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1060 1061 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1062 HCLGE_CFG_DEFAULT_SPEED_M, 1063 HCLGE_CFG_DEFAULT_SPEED_S); 1064 cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1065 HCLGE_CFG_RSS_SIZE_M, 1066 HCLGE_CFG_RSS_SIZE_S); 1067 1068 for (i = 0; i < ETH_ALEN; i++) 1069 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1070 1071 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1072 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1073 1074 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1075 HCLGE_CFG_SPEED_ABILITY_M, 1076 HCLGE_CFG_SPEED_ABILITY_S); 1077 } 1078 1079 /* hclge_get_cfg: query the static parameter from flash 1080 * @hdev: pointer to struct hclge_dev 1081 * @hcfg: the config structure to be getted 1082 */ 1083 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1084 { 1085 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1086 struct hclge_cfg_param_cmd *req; 1087 int i, ret; 1088 1089 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1090 u32 offset = 0; 1091 1092 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1093 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1094 true); 1095 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1096 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1097 /* Len should be united by 4 bytes when send to hardware */ 1098 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1099 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1100 req->offset = cpu_to_le32(offset); 1101 } 1102 1103 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1104 if (ret) { 1105 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1106 return ret; 1107 } 1108 1109 hclge_parse_cfg(hcfg, desc); 1110 1111 return 0; 1112 } 1113 1114 static int hclge_get_cap(struct hclge_dev *hdev) 1115 { 1116 int ret; 1117 1118 ret = hclge_query_function_status(hdev); 1119 if (ret) { 1120 dev_err(&hdev->pdev->dev, 1121 "query function status error %d.\n", ret); 1122 return ret; 1123 } 1124 1125 /* get pf resource */ 1126 ret = hclge_query_pf_resource(hdev); 1127 if (ret) 1128 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret); 1129 1130 return ret; 1131 } 1132 1133 static int hclge_configure(struct hclge_dev *hdev) 1134 { 1135 struct hclge_cfg cfg; 1136 int ret, i; 1137 1138 ret = hclge_get_cfg(hdev, &cfg); 1139 if (ret) { 1140 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret); 1141 return ret; 1142 } 1143 1144 hdev->num_vmdq_vport = cfg.vmdq_vport_num; 1145 hdev->base_tqp_pid = 0; 1146 hdev->rss_size_max = cfg.rss_size_max; 1147 hdev->rx_buf_len = cfg.rx_buf_len; 1148 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1149 hdev->hw.mac.media_type = cfg.media_type; 1150 hdev->hw.mac.phy_addr = cfg.phy_addr; 1151 hdev->num_desc = cfg.tqp_desc_num; 1152 hdev->tm_info.num_pg = 1; 1153 hdev->tc_max = cfg.tc_num; 1154 hdev->tm_info.hw_pfc_map = 0; 1155 1156 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1157 if (ret) { 1158 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret); 1159 return ret; 1160 } 1161 1162 hclge_parse_link_mode(hdev, cfg.speed_ability); 1163 1164 if ((hdev->tc_max > HNAE3_MAX_TC) || 1165 (hdev->tc_max < 1)) { 1166 dev_warn(&hdev->pdev->dev, "TC num = %d.\n", 1167 hdev->tc_max); 1168 hdev->tc_max = 1; 1169 } 1170 1171 /* Dev does not support DCB */ 1172 if (!hnae3_dev_dcb_supported(hdev)) { 1173 hdev->tc_max = 1; 1174 hdev->pfc_max = 0; 1175 } else { 1176 hdev->pfc_max = hdev->tc_max; 1177 } 1178 1179 hdev->tm_info.num_tc = hdev->tc_max; 1180 1181 /* Currently not support uncontiuous tc */ 1182 for (i = 0; i < hdev->tm_info.num_tc; i++) 1183 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1184 1185 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1186 1187 return ret; 1188 } 1189 1190 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min, 1191 int tso_mss_max) 1192 { 1193 struct hclge_cfg_tso_status_cmd *req; 1194 struct hclge_desc desc; 1195 u16 tso_mss; 1196 1197 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1198 1199 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1200 1201 tso_mss = 0; 1202 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, 1203 HCLGE_TSO_MSS_MIN_S, tso_mss_min); 1204 req->tso_mss_min = cpu_to_le16(tso_mss); 1205 1206 tso_mss = 0; 1207 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, 1208 HCLGE_TSO_MSS_MIN_S, tso_mss_max); 1209 req->tso_mss_max = cpu_to_le16(tso_mss); 1210 1211 return hclge_cmd_send(&hdev->hw, &desc, 1); 1212 } 1213 1214 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1215 { 1216 struct hclge_tqp *tqp; 1217 int i; 1218 1219 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1220 sizeof(struct hclge_tqp), GFP_KERNEL); 1221 if (!hdev->htqp) 1222 return -ENOMEM; 1223 1224 tqp = hdev->htqp; 1225 1226 for (i = 0; i < hdev->num_tqps; i++) { 1227 tqp->dev = &hdev->pdev->dev; 1228 tqp->index = i; 1229 1230 tqp->q.ae_algo = &ae_algo; 1231 tqp->q.buf_size = hdev->rx_buf_len; 1232 tqp->q.desc_num = hdev->num_desc; 1233 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET + 1234 i * HCLGE_TQP_REG_SIZE; 1235 1236 tqp++; 1237 } 1238 1239 return 0; 1240 } 1241 1242 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1243 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1244 { 1245 struct hclge_tqp_map_cmd *req; 1246 struct hclge_desc desc; 1247 int ret; 1248 1249 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1250 1251 req = (struct hclge_tqp_map_cmd *)desc.data; 1252 req->tqp_id = cpu_to_le16(tqp_pid); 1253 req->tqp_vf = func_id; 1254 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B | 1255 1 << HCLGE_TQP_MAP_EN_B; 1256 req->tqp_vid = cpu_to_le16(tqp_vid); 1257 1258 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1259 if (ret) 1260 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1261 1262 return ret; 1263 } 1264 1265 static int hclge_assign_tqp(struct hclge_vport *vport, 1266 struct hnae3_queue **tqp, u16 num_tqps) 1267 { 1268 struct hclge_dev *hdev = vport->back; 1269 int i, alloced; 1270 1271 for (i = 0, alloced = 0; i < hdev->num_tqps && 1272 alloced < num_tqps; i++) { 1273 if (!hdev->htqp[i].alloced) { 1274 hdev->htqp[i].q.handle = &vport->nic; 1275 hdev->htqp[i].q.tqp_index = alloced; 1276 tqp[alloced] = &hdev->htqp[i].q; 1277 hdev->htqp[i].alloced = true; 1278 alloced++; 1279 } 1280 } 1281 vport->alloc_tqps = num_tqps; 1282 1283 return 0; 1284 } 1285 1286 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps) 1287 { 1288 struct hnae3_handle *nic = &vport->nic; 1289 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1290 struct hclge_dev *hdev = vport->back; 1291 int i, ret; 1292 1293 kinfo->num_desc = hdev->num_desc; 1294 kinfo->rx_buf_len = hdev->rx_buf_len; 1295 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc); 1296 kinfo->rss_size 1297 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc); 1298 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc; 1299 1300 for (i = 0; i < HNAE3_MAX_TC; i++) { 1301 if (hdev->hw_tc_map & BIT(i)) { 1302 kinfo->tc_info[i].enable = true; 1303 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size; 1304 kinfo->tc_info[i].tqp_count = kinfo->rss_size; 1305 kinfo->tc_info[i].tc = i; 1306 } else { 1307 /* Set to default queue if TC is disable */ 1308 kinfo->tc_info[i].enable = false; 1309 kinfo->tc_info[i].tqp_offset = 0; 1310 kinfo->tc_info[i].tqp_count = 1; 1311 kinfo->tc_info[i].tc = 0; 1312 } 1313 } 1314 1315 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, 1316 sizeof(struct hnae3_queue *), GFP_KERNEL); 1317 if (!kinfo->tqp) 1318 return -ENOMEM; 1319 1320 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps); 1321 if (ret) 1322 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1323 1324 return ret; 1325 } 1326 1327 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1328 struct hclge_vport *vport) 1329 { 1330 struct hnae3_handle *nic = &vport->nic; 1331 struct hnae3_knic_private_info *kinfo; 1332 u16 i; 1333 1334 kinfo = &nic->kinfo; 1335 for (i = 0; i < kinfo->num_tqps; i++) { 1336 struct hclge_tqp *q = 1337 container_of(kinfo->tqp[i], struct hclge_tqp, q); 1338 bool is_pf; 1339 int ret; 1340 1341 is_pf = !(vport->vport_id); 1342 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1343 i, is_pf); 1344 if (ret) 1345 return ret; 1346 } 1347 1348 return 0; 1349 } 1350 1351 static int hclge_map_tqp(struct hclge_dev *hdev) 1352 { 1353 struct hclge_vport *vport = hdev->vport; 1354 u16 i, num_vport; 1355 1356 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1; 1357 for (i = 0; i < num_vport; i++) { 1358 int ret; 1359 1360 ret = hclge_map_tqp_to_vport(hdev, vport); 1361 if (ret) 1362 return ret; 1363 1364 vport++; 1365 } 1366 1367 return 0; 1368 } 1369 1370 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps) 1371 { 1372 /* this would be initialized later */ 1373 } 1374 1375 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1376 { 1377 struct hnae3_handle *nic = &vport->nic; 1378 struct hclge_dev *hdev = vport->back; 1379 int ret; 1380 1381 nic->pdev = hdev->pdev; 1382 nic->ae_algo = &ae_algo; 1383 nic->numa_node_mask = hdev->numa_node_mask; 1384 1385 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) { 1386 ret = hclge_knic_setup(vport, num_tqps); 1387 if (ret) { 1388 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", 1389 ret); 1390 return ret; 1391 } 1392 } else { 1393 hclge_unic_setup(vport, num_tqps); 1394 } 1395 1396 return 0; 1397 } 1398 1399 static int hclge_alloc_vport(struct hclge_dev *hdev) 1400 { 1401 struct pci_dev *pdev = hdev->pdev; 1402 struct hclge_vport *vport; 1403 u32 tqp_main_vport; 1404 u32 tqp_per_vport; 1405 int num_vport, i; 1406 int ret; 1407 1408 /* We need to alloc a vport for main NIC of PF */ 1409 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1; 1410 1411 if (hdev->num_tqps < num_vport) { 1412 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)", 1413 hdev->num_tqps, num_vport); 1414 return -EINVAL; 1415 } 1416 1417 /* Alloc the same number of TQPs for every vport */ 1418 tqp_per_vport = hdev->num_tqps / num_vport; 1419 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1420 1421 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1422 GFP_KERNEL); 1423 if (!vport) 1424 return -ENOMEM; 1425 1426 hdev->vport = vport; 1427 hdev->num_alloc_vport = num_vport; 1428 1429 if (IS_ENABLED(CONFIG_PCI_IOV)) 1430 hdev->num_alloc_vfs = hdev->num_req_vfs; 1431 1432 for (i = 0; i < num_vport; i++) { 1433 vport->back = hdev; 1434 vport->vport_id = i; 1435 1436 if (i == 0) 1437 ret = hclge_vport_setup(vport, tqp_main_vport); 1438 else 1439 ret = hclge_vport_setup(vport, tqp_per_vport); 1440 if (ret) { 1441 dev_err(&pdev->dev, 1442 "vport setup failed for vport %d, %d\n", 1443 i, ret); 1444 return ret; 1445 } 1446 1447 vport++; 1448 } 1449 1450 return 0; 1451 } 1452 1453 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1454 struct hclge_pkt_buf_alloc *buf_alloc) 1455 { 1456 /* TX buffer size is unit by 128 byte */ 1457 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1458 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1459 struct hclge_tx_buff_alloc_cmd *req; 1460 struct hclge_desc desc; 1461 int ret; 1462 u8 i; 1463 1464 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1465 1466 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1467 for (i = 0; i < HCLGE_TC_NUM; i++) { 1468 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1469 1470 req->tx_pkt_buff[i] = 1471 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1472 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1473 } 1474 1475 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1476 if (ret) 1477 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1478 ret); 1479 1480 return ret; 1481 } 1482 1483 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1484 struct hclge_pkt_buf_alloc *buf_alloc) 1485 { 1486 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1487 1488 if (ret) 1489 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1490 1491 return ret; 1492 } 1493 1494 static int hclge_get_tc_num(struct hclge_dev *hdev) 1495 { 1496 int i, cnt = 0; 1497 1498 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1499 if (hdev->hw_tc_map & BIT(i)) 1500 cnt++; 1501 return cnt; 1502 } 1503 1504 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev) 1505 { 1506 int i, cnt = 0; 1507 1508 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1509 if (hdev->hw_tc_map & BIT(i) && 1510 hdev->tm_info.hw_pfc_map & BIT(i)) 1511 cnt++; 1512 return cnt; 1513 } 1514 1515 /* Get the number of pfc enabled TCs, which have private buffer */ 1516 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1517 struct hclge_pkt_buf_alloc *buf_alloc) 1518 { 1519 struct hclge_priv_buf *priv; 1520 int i, cnt = 0; 1521 1522 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1523 priv = &buf_alloc->priv_buf[i]; 1524 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1525 priv->enable) 1526 cnt++; 1527 } 1528 1529 return cnt; 1530 } 1531 1532 /* Get the number of pfc disabled TCs, which have private buffer */ 1533 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1534 struct hclge_pkt_buf_alloc *buf_alloc) 1535 { 1536 struct hclge_priv_buf *priv; 1537 int i, cnt = 0; 1538 1539 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1540 priv = &buf_alloc->priv_buf[i]; 1541 if (hdev->hw_tc_map & BIT(i) && 1542 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 1543 priv->enable) 1544 cnt++; 1545 } 1546 1547 return cnt; 1548 } 1549 1550 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1551 { 1552 struct hclge_priv_buf *priv; 1553 u32 rx_priv = 0; 1554 int i; 1555 1556 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1557 priv = &buf_alloc->priv_buf[i]; 1558 if (priv->enable) 1559 rx_priv += priv->buf_size; 1560 } 1561 return rx_priv; 1562 } 1563 1564 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1565 { 1566 u32 i, total_tx_size = 0; 1567 1568 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1569 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 1570 1571 return total_tx_size; 1572 } 1573 1574 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 1575 struct hclge_pkt_buf_alloc *buf_alloc, 1576 u32 rx_all) 1577 { 1578 u32 shared_buf_min, shared_buf_tc, shared_std; 1579 int tc_num, pfc_enable_num; 1580 u32 shared_buf; 1581 u32 rx_priv; 1582 int i; 1583 1584 tc_num = hclge_get_tc_num(hdev); 1585 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev); 1586 1587 if (hnae3_dev_dcb_supported(hdev)) 1588 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV; 1589 else 1590 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV; 1591 1592 shared_buf_tc = pfc_enable_num * hdev->mps + 1593 (tc_num - pfc_enable_num) * hdev->mps / 2 + 1594 hdev->mps; 1595 shared_std = max_t(u32, shared_buf_min, shared_buf_tc); 1596 1597 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 1598 if (rx_all <= rx_priv + shared_std) 1599 return false; 1600 1601 shared_buf = rx_all - rx_priv; 1602 buf_alloc->s_buf.buf_size = shared_buf; 1603 buf_alloc->s_buf.self.high = shared_buf; 1604 buf_alloc->s_buf.self.low = 2 * hdev->mps; 1605 1606 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1607 if ((hdev->hw_tc_map & BIT(i)) && 1608 (hdev->tm_info.hw_pfc_map & BIT(i))) { 1609 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps; 1610 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps; 1611 } else { 1612 buf_alloc->s_buf.tc_thrd[i].low = 0; 1613 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps; 1614 } 1615 } 1616 1617 return true; 1618 } 1619 1620 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 1621 struct hclge_pkt_buf_alloc *buf_alloc) 1622 { 1623 u32 i, total_size; 1624 1625 total_size = hdev->pkt_buf_size; 1626 1627 /* alloc tx buffer for all enabled tc */ 1628 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1629 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 1630 1631 if (total_size < HCLGE_DEFAULT_TX_BUF) 1632 return -ENOMEM; 1633 1634 if (hdev->hw_tc_map & BIT(i)) 1635 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 1636 else 1637 priv->tx_buf_size = 0; 1638 1639 total_size -= priv->tx_buf_size; 1640 } 1641 1642 return 0; 1643 } 1644 1645 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 1646 * @hdev: pointer to struct hclge_dev 1647 * @buf_alloc: pointer to buffer calculation data 1648 * @return: 0: calculate sucessful, negative: fail 1649 */ 1650 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 1651 struct hclge_pkt_buf_alloc *buf_alloc) 1652 { 1653 u32 rx_all = hdev->pkt_buf_size; 1654 int no_pfc_priv_num, pfc_priv_num; 1655 struct hclge_priv_buf *priv; 1656 int i; 1657 1658 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 1659 1660 /* When DCB is not supported, rx private 1661 * buffer is not allocated. 1662 */ 1663 if (!hnae3_dev_dcb_supported(hdev)) { 1664 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1665 return -ENOMEM; 1666 1667 return 0; 1668 } 1669 1670 /* step 1, try to alloc private buffer for all enabled tc */ 1671 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1672 priv = &buf_alloc->priv_buf[i]; 1673 if (hdev->hw_tc_map & BIT(i)) { 1674 priv->enable = 1; 1675 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 1676 priv->wl.low = hdev->mps; 1677 priv->wl.high = priv->wl.low + hdev->mps; 1678 priv->buf_size = priv->wl.high + 1679 HCLGE_DEFAULT_DV; 1680 } else { 1681 priv->wl.low = 0; 1682 priv->wl.high = 2 * hdev->mps; 1683 priv->buf_size = priv->wl.high; 1684 } 1685 } else { 1686 priv->enable = 0; 1687 priv->wl.low = 0; 1688 priv->wl.high = 0; 1689 priv->buf_size = 0; 1690 } 1691 } 1692 1693 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1694 return 0; 1695 1696 /* step 2, try to decrease the buffer size of 1697 * no pfc TC's private buffer 1698 */ 1699 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1700 priv = &buf_alloc->priv_buf[i]; 1701 1702 priv->enable = 0; 1703 priv->wl.low = 0; 1704 priv->wl.high = 0; 1705 priv->buf_size = 0; 1706 1707 if (!(hdev->hw_tc_map & BIT(i))) 1708 continue; 1709 1710 priv->enable = 1; 1711 1712 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 1713 priv->wl.low = 128; 1714 priv->wl.high = priv->wl.low + hdev->mps; 1715 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV; 1716 } else { 1717 priv->wl.low = 0; 1718 priv->wl.high = hdev->mps; 1719 priv->buf_size = priv->wl.high; 1720 } 1721 } 1722 1723 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1724 return 0; 1725 1726 /* step 3, try to reduce the number of pfc disabled TCs, 1727 * which have private buffer 1728 */ 1729 /* get the total no pfc enable TC number, which have private buffer */ 1730 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 1731 1732 /* let the last to be cleared first */ 1733 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 1734 priv = &buf_alloc->priv_buf[i]; 1735 1736 if (hdev->hw_tc_map & BIT(i) && 1737 !(hdev->tm_info.hw_pfc_map & BIT(i))) { 1738 /* Clear the no pfc TC private buffer */ 1739 priv->wl.low = 0; 1740 priv->wl.high = 0; 1741 priv->buf_size = 0; 1742 priv->enable = 0; 1743 no_pfc_priv_num--; 1744 } 1745 1746 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 1747 no_pfc_priv_num == 0) 1748 break; 1749 } 1750 1751 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1752 return 0; 1753 1754 /* step 4, try to reduce the number of pfc enabled TCs 1755 * which have private buffer. 1756 */ 1757 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 1758 1759 /* let the last to be cleared first */ 1760 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 1761 priv = &buf_alloc->priv_buf[i]; 1762 1763 if (hdev->hw_tc_map & BIT(i) && 1764 hdev->tm_info.hw_pfc_map & BIT(i)) { 1765 /* Reduce the number of pfc TC with private buffer */ 1766 priv->wl.low = 0; 1767 priv->enable = 0; 1768 priv->wl.high = 0; 1769 priv->buf_size = 0; 1770 pfc_priv_num--; 1771 } 1772 1773 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 1774 pfc_priv_num == 0) 1775 break; 1776 } 1777 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 1778 return 0; 1779 1780 return -ENOMEM; 1781 } 1782 1783 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 1784 struct hclge_pkt_buf_alloc *buf_alloc) 1785 { 1786 struct hclge_rx_priv_buff_cmd *req; 1787 struct hclge_desc desc; 1788 int ret; 1789 int i; 1790 1791 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 1792 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 1793 1794 /* Alloc private buffer TCs */ 1795 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1796 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 1797 1798 req->buf_num[i] = 1799 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 1800 req->buf_num[i] |= 1801 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 1802 } 1803 1804 req->shared_buf = 1805 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 1806 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 1807 1808 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1809 if (ret) 1810 dev_err(&hdev->pdev->dev, 1811 "rx private buffer alloc cmd failed %d\n", ret); 1812 1813 return ret; 1814 } 1815 1816 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 1817 struct hclge_pkt_buf_alloc *buf_alloc) 1818 { 1819 struct hclge_rx_priv_wl_buf *req; 1820 struct hclge_priv_buf *priv; 1821 struct hclge_desc desc[2]; 1822 int i, j; 1823 int ret; 1824 1825 for (i = 0; i < 2; i++) { 1826 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 1827 false); 1828 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 1829 1830 /* The first descriptor set the NEXT bit to 1 */ 1831 if (i == 0) 1832 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1833 else 1834 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1835 1836 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 1837 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 1838 1839 priv = &buf_alloc->priv_buf[idx]; 1840 req->tc_wl[j].high = 1841 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 1842 req->tc_wl[j].high |= 1843 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 1844 req->tc_wl[j].low = 1845 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 1846 req->tc_wl[j].low |= 1847 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 1848 } 1849 } 1850 1851 /* Send 2 descriptor at one time */ 1852 ret = hclge_cmd_send(&hdev->hw, desc, 2); 1853 if (ret) 1854 dev_err(&hdev->pdev->dev, 1855 "rx private waterline config cmd failed %d\n", 1856 ret); 1857 return ret; 1858 } 1859 1860 static int hclge_common_thrd_config(struct hclge_dev *hdev, 1861 struct hclge_pkt_buf_alloc *buf_alloc) 1862 { 1863 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 1864 struct hclge_rx_com_thrd *req; 1865 struct hclge_desc desc[2]; 1866 struct hclge_tc_thrd *tc; 1867 int i, j; 1868 int ret; 1869 1870 for (i = 0; i < 2; i++) { 1871 hclge_cmd_setup_basic_desc(&desc[i], 1872 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 1873 req = (struct hclge_rx_com_thrd *)&desc[i].data; 1874 1875 /* The first descriptor set the NEXT bit to 1 */ 1876 if (i == 0) 1877 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1878 else 1879 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1880 1881 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 1882 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 1883 1884 req->com_thrd[j].high = 1885 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 1886 req->com_thrd[j].high |= 1887 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 1888 req->com_thrd[j].low = 1889 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 1890 req->com_thrd[j].low |= 1891 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 1892 } 1893 } 1894 1895 /* Send 2 descriptors at one time */ 1896 ret = hclge_cmd_send(&hdev->hw, desc, 2); 1897 if (ret) 1898 dev_err(&hdev->pdev->dev, 1899 "common threshold config cmd failed %d\n", ret); 1900 return ret; 1901 } 1902 1903 static int hclge_common_wl_config(struct hclge_dev *hdev, 1904 struct hclge_pkt_buf_alloc *buf_alloc) 1905 { 1906 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 1907 struct hclge_rx_com_wl *req; 1908 struct hclge_desc desc; 1909 int ret; 1910 1911 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 1912 1913 req = (struct hclge_rx_com_wl *)desc.data; 1914 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 1915 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 1916 1917 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 1918 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 1919 1920 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1921 if (ret) 1922 dev_err(&hdev->pdev->dev, 1923 "common waterline config cmd failed %d\n", ret); 1924 1925 return ret; 1926 } 1927 1928 int hclge_buffer_alloc(struct hclge_dev *hdev) 1929 { 1930 struct hclge_pkt_buf_alloc *pkt_buf; 1931 int ret; 1932 1933 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 1934 if (!pkt_buf) 1935 return -ENOMEM; 1936 1937 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 1938 if (ret) { 1939 dev_err(&hdev->pdev->dev, 1940 "could not calc tx buffer size for all TCs %d\n", ret); 1941 goto out; 1942 } 1943 1944 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 1945 if (ret) { 1946 dev_err(&hdev->pdev->dev, 1947 "could not alloc tx buffers %d\n", ret); 1948 goto out; 1949 } 1950 1951 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 1952 if (ret) { 1953 dev_err(&hdev->pdev->dev, 1954 "could not calc rx priv buffer size for all TCs %d\n", 1955 ret); 1956 goto out; 1957 } 1958 1959 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 1960 if (ret) { 1961 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 1962 ret); 1963 goto out; 1964 } 1965 1966 if (hnae3_dev_dcb_supported(hdev)) { 1967 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 1968 if (ret) { 1969 dev_err(&hdev->pdev->dev, 1970 "could not configure rx private waterline %d\n", 1971 ret); 1972 goto out; 1973 } 1974 1975 ret = hclge_common_thrd_config(hdev, pkt_buf); 1976 if (ret) { 1977 dev_err(&hdev->pdev->dev, 1978 "could not configure common threshold %d\n", 1979 ret); 1980 goto out; 1981 } 1982 } 1983 1984 ret = hclge_common_wl_config(hdev, pkt_buf); 1985 if (ret) 1986 dev_err(&hdev->pdev->dev, 1987 "could not configure common waterline %d\n", ret); 1988 1989 out: 1990 kfree(pkt_buf); 1991 return ret; 1992 } 1993 1994 static int hclge_init_roce_base_info(struct hclge_vport *vport) 1995 { 1996 struct hnae3_handle *roce = &vport->roce; 1997 struct hnae3_handle *nic = &vport->nic; 1998 1999 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2000 2001 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors || 2002 vport->back->num_msi_left == 0) 2003 return -EINVAL; 2004 2005 roce->rinfo.base_vector = vport->back->roce_base_vector; 2006 2007 roce->rinfo.netdev = nic->kinfo.netdev; 2008 roce->rinfo.roce_io_base = vport->back->hw.io_base; 2009 2010 roce->pdev = nic->pdev; 2011 roce->ae_algo = nic->ae_algo; 2012 roce->numa_node_mask = nic->numa_node_mask; 2013 2014 return 0; 2015 } 2016 2017 static int hclge_init_msi(struct hclge_dev *hdev) 2018 { 2019 struct pci_dev *pdev = hdev->pdev; 2020 int vectors; 2021 int i; 2022 2023 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, 2024 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2025 if (vectors < 0) { 2026 dev_err(&pdev->dev, 2027 "failed(%d) to allocate MSI/MSI-X vectors\n", 2028 vectors); 2029 return vectors; 2030 } 2031 if (vectors < hdev->num_msi) 2032 dev_warn(&hdev->pdev->dev, 2033 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2034 hdev->num_msi, vectors); 2035 2036 hdev->num_msi = vectors; 2037 hdev->num_msi_left = vectors; 2038 hdev->base_msi_vector = pdev->irq; 2039 hdev->roce_base_vector = hdev->base_msi_vector + 2040 HCLGE_ROCE_VECTOR_OFFSET; 2041 2042 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2043 sizeof(u16), GFP_KERNEL); 2044 if (!hdev->vector_status) { 2045 pci_free_irq_vectors(pdev); 2046 return -ENOMEM; 2047 } 2048 2049 for (i = 0; i < hdev->num_msi; i++) 2050 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2051 2052 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2053 sizeof(int), GFP_KERNEL); 2054 if (!hdev->vector_irq) { 2055 pci_free_irq_vectors(pdev); 2056 return -ENOMEM; 2057 } 2058 2059 return 0; 2060 } 2061 2062 static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed) 2063 { 2064 struct hclge_mac *mac = &hdev->hw.mac; 2065 2066 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M)) 2067 mac->duplex = (u8)duplex; 2068 else 2069 mac->duplex = HCLGE_MAC_FULL; 2070 2071 mac->speed = speed; 2072 } 2073 2074 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex) 2075 { 2076 struct hclge_config_mac_speed_dup_cmd *req; 2077 struct hclge_desc desc; 2078 int ret; 2079 2080 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2081 2082 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2083 2084 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex); 2085 2086 switch (speed) { 2087 case HCLGE_MAC_SPEED_10M: 2088 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2089 HCLGE_CFG_SPEED_S, 6); 2090 break; 2091 case HCLGE_MAC_SPEED_100M: 2092 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2093 HCLGE_CFG_SPEED_S, 7); 2094 break; 2095 case HCLGE_MAC_SPEED_1G: 2096 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2097 HCLGE_CFG_SPEED_S, 0); 2098 break; 2099 case HCLGE_MAC_SPEED_10G: 2100 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2101 HCLGE_CFG_SPEED_S, 1); 2102 break; 2103 case HCLGE_MAC_SPEED_25G: 2104 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2105 HCLGE_CFG_SPEED_S, 2); 2106 break; 2107 case HCLGE_MAC_SPEED_40G: 2108 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2109 HCLGE_CFG_SPEED_S, 3); 2110 break; 2111 case HCLGE_MAC_SPEED_50G: 2112 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2113 HCLGE_CFG_SPEED_S, 4); 2114 break; 2115 case HCLGE_MAC_SPEED_100G: 2116 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, 2117 HCLGE_CFG_SPEED_S, 5); 2118 break; 2119 default: 2120 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2121 return -EINVAL; 2122 } 2123 2124 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2125 1); 2126 2127 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2128 if (ret) { 2129 dev_err(&hdev->pdev->dev, 2130 "mac speed/duplex config cmd failed %d.\n", ret); 2131 return ret; 2132 } 2133 2134 hclge_check_speed_dup(hdev, duplex, speed); 2135 2136 return 0; 2137 } 2138 2139 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2140 u8 duplex) 2141 { 2142 struct hclge_vport *vport = hclge_get_vport(handle); 2143 struct hclge_dev *hdev = vport->back; 2144 2145 return hclge_cfg_mac_speed_dup(hdev, speed, duplex); 2146 } 2147 2148 static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed, 2149 u8 *duplex) 2150 { 2151 struct hclge_query_an_speed_dup_cmd *req; 2152 struct hclge_desc desc; 2153 int speed_tmp; 2154 int ret; 2155 2156 req = (struct hclge_query_an_speed_dup_cmd *)desc.data; 2157 2158 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true); 2159 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2160 if (ret) { 2161 dev_err(&hdev->pdev->dev, 2162 "mac speed/autoneg/duplex query cmd failed %d\n", 2163 ret); 2164 return ret; 2165 } 2166 2167 *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B); 2168 speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M, 2169 HCLGE_QUERY_SPEED_S); 2170 2171 ret = hclge_parse_speed(speed_tmp, speed); 2172 if (ret) 2173 dev_err(&hdev->pdev->dev, 2174 "could not parse speed(=%d), %d\n", speed_tmp, ret); 2175 2176 return ret; 2177 } 2178 2179 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2180 { 2181 struct hclge_config_auto_neg_cmd *req; 2182 struct hclge_desc desc; 2183 u32 flag = 0; 2184 int ret; 2185 2186 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2187 2188 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2189 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable); 2190 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2191 2192 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2193 if (ret) 2194 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2195 ret); 2196 2197 return ret; 2198 } 2199 2200 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2201 { 2202 struct hclge_vport *vport = hclge_get_vport(handle); 2203 struct hclge_dev *hdev = vport->back; 2204 2205 return hclge_set_autoneg_en(hdev, enable); 2206 } 2207 2208 static int hclge_get_autoneg(struct hnae3_handle *handle) 2209 { 2210 struct hclge_vport *vport = hclge_get_vport(handle); 2211 struct hclge_dev *hdev = vport->back; 2212 struct phy_device *phydev = hdev->hw.mac.phydev; 2213 2214 if (phydev) 2215 return phydev->autoneg; 2216 2217 return hdev->hw.mac.autoneg; 2218 } 2219 2220 static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev, 2221 bool mask_vlan, 2222 u8 *mac_mask) 2223 { 2224 struct hclge_mac_vlan_mask_entry_cmd *req; 2225 struct hclge_desc desc; 2226 int status; 2227 2228 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data; 2229 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false); 2230 2231 hnae3_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B, 2232 mask_vlan ? 1 : 0); 2233 ether_addr_copy(req->mac_mask, mac_mask); 2234 2235 status = hclge_cmd_send(&hdev->hw, &desc, 1); 2236 if (status) 2237 dev_err(&hdev->pdev->dev, 2238 "Config mac_vlan_mask failed for cmd_send, ret =%d\n", 2239 status); 2240 2241 return status; 2242 } 2243 2244 static int hclge_mac_init(struct hclge_dev *hdev) 2245 { 2246 struct hnae3_handle *handle = &hdev->vport[0].nic; 2247 struct net_device *netdev = handle->kinfo.netdev; 2248 struct hclge_mac *mac = &hdev->hw.mac; 2249 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; 2250 struct hclge_vport *vport; 2251 int mtu; 2252 int ret; 2253 int i; 2254 2255 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL); 2256 if (ret) { 2257 dev_err(&hdev->pdev->dev, 2258 "Config mac speed dup fail ret=%d\n", ret); 2259 return ret; 2260 } 2261 2262 mac->link = 0; 2263 2264 /* Initialize the MTA table work mode */ 2265 hdev->enable_mta = true; 2266 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36; 2267 2268 ret = hclge_set_mta_filter_mode(hdev, 2269 hdev->mta_mac_sel_type, 2270 hdev->enable_mta); 2271 if (ret) { 2272 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n", 2273 ret); 2274 return ret; 2275 } 2276 2277 for (i = 0; i < hdev->num_alloc_vport; i++) { 2278 vport = &hdev->vport[i]; 2279 vport->accept_mta_mc = false; 2280 2281 memset(vport->mta_shadow, 0, sizeof(vport->mta_shadow)); 2282 ret = hclge_cfg_func_mta_filter(hdev, vport->vport_id, false); 2283 if (ret) { 2284 dev_err(&hdev->pdev->dev, 2285 "set mta filter mode fail ret=%d\n", ret); 2286 return ret; 2287 } 2288 } 2289 2290 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask); 2291 if (ret) { 2292 dev_err(&hdev->pdev->dev, 2293 "set default mac_vlan_mask fail ret=%d\n", ret); 2294 return ret; 2295 } 2296 2297 if (netdev) 2298 mtu = netdev->mtu; 2299 else 2300 mtu = ETH_DATA_LEN; 2301 2302 ret = hclge_set_mtu(handle, mtu); 2303 if (ret) 2304 dev_err(&hdev->pdev->dev, 2305 "set mtu failed ret=%d\n", ret); 2306 2307 return ret; 2308 } 2309 2310 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 2311 { 2312 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) 2313 schedule_work(&hdev->mbx_service_task); 2314 } 2315 2316 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 2317 { 2318 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 2319 schedule_work(&hdev->rst_service_task); 2320 } 2321 2322 static void hclge_task_schedule(struct hclge_dev *hdev) 2323 { 2324 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) && 2325 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2326 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state)) 2327 (void)schedule_work(&hdev->service_task); 2328 } 2329 2330 static int hclge_get_mac_link_status(struct hclge_dev *hdev) 2331 { 2332 struct hclge_link_status_cmd *req; 2333 struct hclge_desc desc; 2334 int link_status; 2335 int ret; 2336 2337 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 2338 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2339 if (ret) { 2340 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 2341 ret); 2342 return ret; 2343 } 2344 2345 req = (struct hclge_link_status_cmd *)desc.data; 2346 link_status = req->status & HCLGE_LINK_STATUS_UP_M; 2347 2348 return !!link_status; 2349 } 2350 2351 static int hclge_get_mac_phy_link(struct hclge_dev *hdev) 2352 { 2353 int mac_state; 2354 int link_stat; 2355 2356 mac_state = hclge_get_mac_link_status(hdev); 2357 2358 if (hdev->hw.mac.phydev) { 2359 if (!genphy_read_status(hdev->hw.mac.phydev)) 2360 link_stat = mac_state & 2361 hdev->hw.mac.phydev->link; 2362 else 2363 link_stat = 0; 2364 2365 } else { 2366 link_stat = mac_state; 2367 } 2368 2369 return !!link_stat; 2370 } 2371 2372 static void hclge_update_link_status(struct hclge_dev *hdev) 2373 { 2374 struct hnae3_client *client = hdev->nic_client; 2375 struct hnae3_handle *handle; 2376 int state; 2377 int i; 2378 2379 if (!client) 2380 return; 2381 state = hclge_get_mac_phy_link(hdev); 2382 if (state != hdev->hw.mac.link) { 2383 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 2384 handle = &hdev->vport[i].nic; 2385 client->ops->link_status_change(handle, state); 2386 } 2387 hdev->hw.mac.link = state; 2388 } 2389 } 2390 2391 static int hclge_update_speed_duplex(struct hclge_dev *hdev) 2392 { 2393 struct hclge_mac mac = hdev->hw.mac; 2394 u8 duplex; 2395 int speed; 2396 int ret; 2397 2398 /* get the speed and duplex as autoneg'result from mac cmd when phy 2399 * doesn't exit. 2400 */ 2401 if (mac.phydev || !mac.autoneg) 2402 return 0; 2403 2404 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex); 2405 if (ret) { 2406 dev_err(&hdev->pdev->dev, 2407 "mac autoneg/speed/duplex query failed %d\n", ret); 2408 return ret; 2409 } 2410 2411 if ((mac.speed != speed) || (mac.duplex != duplex)) { 2412 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex); 2413 if (ret) { 2414 dev_err(&hdev->pdev->dev, 2415 "mac speed/duplex config failed %d\n", ret); 2416 return ret; 2417 } 2418 } 2419 2420 return 0; 2421 } 2422 2423 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle) 2424 { 2425 struct hclge_vport *vport = hclge_get_vport(handle); 2426 struct hclge_dev *hdev = vport->back; 2427 2428 return hclge_update_speed_duplex(hdev); 2429 } 2430 2431 static int hclge_get_status(struct hnae3_handle *handle) 2432 { 2433 struct hclge_vport *vport = hclge_get_vport(handle); 2434 struct hclge_dev *hdev = vport->back; 2435 2436 hclge_update_link_status(hdev); 2437 2438 return hdev->hw.mac.link; 2439 } 2440 2441 static void hclge_service_timer(struct timer_list *t) 2442 { 2443 struct hclge_dev *hdev = from_timer(hdev, t, service_timer); 2444 2445 mod_timer(&hdev->service_timer, jiffies + HZ); 2446 hdev->hw_stats.stats_timer++; 2447 hclge_task_schedule(hdev); 2448 } 2449 2450 static void hclge_service_complete(struct hclge_dev *hdev) 2451 { 2452 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state)); 2453 2454 /* Flush memory before next watchdog */ 2455 smp_mb__before_atomic(); 2456 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state); 2457 } 2458 2459 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 2460 { 2461 u32 rst_src_reg; 2462 u32 cmdq_src_reg; 2463 2464 /* fetch the events from their corresponding regs */ 2465 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 2466 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 2467 2468 /* Assumption: If by any chance reset and mailbox events are reported 2469 * together then we will only process reset event in this go and will 2470 * defer the processing of the mailbox events. Since, we would have not 2471 * cleared RX CMDQ event this time we would receive again another 2472 * interrupt from H/W just for the mailbox. 2473 */ 2474 2475 /* check for vector0 reset event sources */ 2476 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) { 2477 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state); 2478 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 2479 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 2480 return HCLGE_VECTOR0_EVENT_RST; 2481 } 2482 2483 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) { 2484 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state); 2485 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending); 2486 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B); 2487 return HCLGE_VECTOR0_EVENT_RST; 2488 } 2489 2490 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) { 2491 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); 2492 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 2493 return HCLGE_VECTOR0_EVENT_RST; 2494 } 2495 2496 /* check for vector0 mailbox(=CMDQ RX) event source */ 2497 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 2498 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 2499 *clearval = cmdq_src_reg; 2500 return HCLGE_VECTOR0_EVENT_MBX; 2501 } 2502 2503 return HCLGE_VECTOR0_EVENT_OTHER; 2504 } 2505 2506 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 2507 u32 regclr) 2508 { 2509 switch (event_type) { 2510 case HCLGE_VECTOR0_EVENT_RST: 2511 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 2512 break; 2513 case HCLGE_VECTOR0_EVENT_MBX: 2514 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 2515 break; 2516 } 2517 } 2518 2519 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 2520 { 2521 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 2522 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 2523 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 2524 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 2525 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 2526 } 2527 2528 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 2529 { 2530 writel(enable ? 1 : 0, vector->addr); 2531 } 2532 2533 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 2534 { 2535 struct hclge_dev *hdev = data; 2536 u32 event_cause; 2537 u32 clearval; 2538 2539 hclge_enable_vector(&hdev->misc_vector, false); 2540 event_cause = hclge_check_event_cause(hdev, &clearval); 2541 2542 /* vector 0 interrupt is shared with reset and mailbox source events.*/ 2543 switch (event_cause) { 2544 case HCLGE_VECTOR0_EVENT_RST: 2545 hclge_reset_task_schedule(hdev); 2546 break; 2547 case HCLGE_VECTOR0_EVENT_MBX: 2548 /* If we are here then, 2549 * 1. Either we are not handling any mbx task and we are not 2550 * scheduled as well 2551 * OR 2552 * 2. We could be handling a mbx task but nothing more is 2553 * scheduled. 2554 * In both cases, we should schedule mbx task as there are more 2555 * mbx messages reported by this interrupt. 2556 */ 2557 hclge_mbx_task_schedule(hdev); 2558 break; 2559 default: 2560 dev_warn(&hdev->pdev->dev, 2561 "received unknown or unhandled event of vector0\n"); 2562 break; 2563 } 2564 2565 /* clear the source of interrupt if it is not cause by reset */ 2566 if (event_cause != HCLGE_VECTOR0_EVENT_RST) { 2567 hclge_clear_event_cause(hdev, event_cause, clearval); 2568 hclge_enable_vector(&hdev->misc_vector, true); 2569 } 2570 2571 return IRQ_HANDLED; 2572 } 2573 2574 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 2575 { 2576 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 2577 dev_warn(&hdev->pdev->dev, 2578 "vector(vector_id %d) has been freed.\n", vector_id); 2579 return; 2580 } 2581 2582 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 2583 hdev->num_msi_left += 1; 2584 hdev->num_msi_used -= 1; 2585 } 2586 2587 static void hclge_get_misc_vector(struct hclge_dev *hdev) 2588 { 2589 struct hclge_misc_vector *vector = &hdev->misc_vector; 2590 2591 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 2592 2593 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 2594 hdev->vector_status[0] = 0; 2595 2596 hdev->num_msi_left -= 1; 2597 hdev->num_msi_used += 1; 2598 } 2599 2600 static int hclge_misc_irq_init(struct hclge_dev *hdev) 2601 { 2602 int ret; 2603 2604 hclge_get_misc_vector(hdev); 2605 2606 /* this would be explicitly freed in the end */ 2607 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 2608 0, "hclge_misc", hdev); 2609 if (ret) { 2610 hclge_free_vector(hdev, 0); 2611 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 2612 hdev->misc_vector.vector_irq); 2613 } 2614 2615 return ret; 2616 } 2617 2618 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 2619 { 2620 free_irq(hdev->misc_vector.vector_irq, hdev); 2621 hclge_free_vector(hdev, 0); 2622 } 2623 2624 static int hclge_notify_client(struct hclge_dev *hdev, 2625 enum hnae3_reset_notify_type type) 2626 { 2627 struct hnae3_client *client = hdev->nic_client; 2628 u16 i; 2629 2630 if (!client->ops->reset_notify) 2631 return -EOPNOTSUPP; 2632 2633 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 2634 struct hnae3_handle *handle = &hdev->vport[i].nic; 2635 int ret; 2636 2637 ret = client->ops->reset_notify(handle, type); 2638 if (ret) 2639 return ret; 2640 } 2641 2642 return 0; 2643 } 2644 2645 static int hclge_reset_wait(struct hclge_dev *hdev) 2646 { 2647 #define HCLGE_RESET_WATI_MS 100 2648 #define HCLGE_RESET_WAIT_CNT 5 2649 u32 val, reg, reg_bit; 2650 u32 cnt = 0; 2651 2652 switch (hdev->reset_type) { 2653 case HNAE3_GLOBAL_RESET: 2654 reg = HCLGE_GLOBAL_RESET_REG; 2655 reg_bit = HCLGE_GLOBAL_RESET_BIT; 2656 break; 2657 case HNAE3_CORE_RESET: 2658 reg = HCLGE_GLOBAL_RESET_REG; 2659 reg_bit = HCLGE_CORE_RESET_BIT; 2660 break; 2661 case HNAE3_FUNC_RESET: 2662 reg = HCLGE_FUN_RST_ING; 2663 reg_bit = HCLGE_FUN_RST_ING_B; 2664 break; 2665 default: 2666 dev_err(&hdev->pdev->dev, 2667 "Wait for unsupported reset type: %d\n", 2668 hdev->reset_type); 2669 return -EINVAL; 2670 } 2671 2672 val = hclge_read_dev(&hdev->hw, reg); 2673 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 2674 msleep(HCLGE_RESET_WATI_MS); 2675 val = hclge_read_dev(&hdev->hw, reg); 2676 cnt++; 2677 } 2678 2679 if (cnt >= HCLGE_RESET_WAIT_CNT) { 2680 dev_warn(&hdev->pdev->dev, 2681 "Wait for reset timeout: %d\n", hdev->reset_type); 2682 return -EBUSY; 2683 } 2684 2685 return 0; 2686 } 2687 2688 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 2689 { 2690 struct hclge_desc desc; 2691 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 2692 int ret; 2693 2694 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 2695 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 2696 req->fun_reset_vfid = func_id; 2697 2698 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2699 if (ret) 2700 dev_err(&hdev->pdev->dev, 2701 "send function reset cmd fail, status =%d\n", ret); 2702 2703 return ret; 2704 } 2705 2706 static void hclge_do_reset(struct hclge_dev *hdev) 2707 { 2708 struct pci_dev *pdev = hdev->pdev; 2709 u32 val; 2710 2711 switch (hdev->reset_type) { 2712 case HNAE3_GLOBAL_RESET: 2713 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 2714 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 2715 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 2716 dev_info(&pdev->dev, "Global Reset requested\n"); 2717 break; 2718 case HNAE3_CORE_RESET: 2719 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 2720 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1); 2721 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 2722 dev_info(&pdev->dev, "Core Reset requested\n"); 2723 break; 2724 case HNAE3_FUNC_RESET: 2725 dev_info(&pdev->dev, "PF Reset requested\n"); 2726 hclge_func_reset_cmd(hdev, 0); 2727 /* schedule again to check later */ 2728 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); 2729 hclge_reset_task_schedule(hdev); 2730 break; 2731 default: 2732 dev_warn(&pdev->dev, 2733 "Unsupported reset type: %d\n", hdev->reset_type); 2734 break; 2735 } 2736 } 2737 2738 static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev, 2739 unsigned long *addr) 2740 { 2741 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 2742 2743 /* return the highest priority reset level amongst all */ 2744 if (test_bit(HNAE3_GLOBAL_RESET, addr)) 2745 rst_level = HNAE3_GLOBAL_RESET; 2746 else if (test_bit(HNAE3_CORE_RESET, addr)) 2747 rst_level = HNAE3_CORE_RESET; 2748 else if (test_bit(HNAE3_IMP_RESET, addr)) 2749 rst_level = HNAE3_IMP_RESET; 2750 else if (test_bit(HNAE3_FUNC_RESET, addr)) 2751 rst_level = HNAE3_FUNC_RESET; 2752 2753 /* now, clear all other resets */ 2754 clear_bit(HNAE3_GLOBAL_RESET, addr); 2755 clear_bit(HNAE3_CORE_RESET, addr); 2756 clear_bit(HNAE3_IMP_RESET, addr); 2757 clear_bit(HNAE3_FUNC_RESET, addr); 2758 2759 return rst_level; 2760 } 2761 2762 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 2763 { 2764 u32 clearval = 0; 2765 2766 switch (hdev->reset_type) { 2767 case HNAE3_IMP_RESET: 2768 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 2769 break; 2770 case HNAE3_GLOBAL_RESET: 2771 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 2772 break; 2773 case HNAE3_CORE_RESET: 2774 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B); 2775 break; 2776 default: 2777 break; 2778 } 2779 2780 if (!clearval) 2781 return; 2782 2783 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval); 2784 hclge_enable_vector(&hdev->misc_vector, true); 2785 } 2786 2787 static void hclge_reset(struct hclge_dev *hdev) 2788 { 2789 struct hnae3_handle *handle; 2790 2791 /* perform reset of the stack & ae device for a client */ 2792 handle = &hdev->vport[0].nic; 2793 rtnl_lock(); 2794 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2795 2796 if (!hclge_reset_wait(hdev)) { 2797 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 2798 hclge_reset_ae_dev(hdev->ae_dev); 2799 hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 2800 2801 hclge_clear_reset_cause(hdev); 2802 } else { 2803 /* schedule again to check pending resets later */ 2804 set_bit(hdev->reset_type, &hdev->reset_pending); 2805 hclge_reset_task_schedule(hdev); 2806 } 2807 2808 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2809 handle->last_reset_time = jiffies; 2810 rtnl_unlock(); 2811 } 2812 2813 static void hclge_reset_event(struct hnae3_handle *handle) 2814 { 2815 struct hclge_vport *vport = hclge_get_vport(handle); 2816 struct hclge_dev *hdev = vport->back; 2817 2818 /* check if this is a new reset request and we are not here just because 2819 * last reset attempt did not succeed and watchdog hit us again. We will 2820 * know this if last reset request did not occur very recently (watchdog 2821 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 2822 * In case of new request we reset the "reset level" to PF reset. 2823 * And if it is a repeat reset request of the most recent one then we 2824 * want to make sure we throttle the reset request. Therefore, we will 2825 * not allow it again before 3*HZ times. 2826 */ 2827 if (time_before(jiffies, (handle->last_reset_time + 3 * HZ))) 2828 return; 2829 else if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ))) 2830 handle->reset_level = HNAE3_FUNC_RESET; 2831 2832 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d", 2833 handle->reset_level); 2834 2835 /* request reset & schedule reset task */ 2836 set_bit(handle->reset_level, &hdev->reset_request); 2837 hclge_reset_task_schedule(hdev); 2838 2839 if (handle->reset_level < HNAE3_GLOBAL_RESET) 2840 handle->reset_level++; 2841 } 2842 2843 static void hclge_reset_subtask(struct hclge_dev *hdev) 2844 { 2845 /* check if there is any ongoing reset in the hardware. This status can 2846 * be checked from reset_pending. If there is then, we need to wait for 2847 * hardware to complete reset. 2848 * a. If we are able to figure out in reasonable time that hardware 2849 * has fully resetted then, we can proceed with driver, client 2850 * reset. 2851 * b. else, we can come back later to check this status so re-sched 2852 * now. 2853 */ 2854 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending); 2855 if (hdev->reset_type != HNAE3_NONE_RESET) 2856 hclge_reset(hdev); 2857 2858 /* check if we got any *new* reset requests to be honored */ 2859 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request); 2860 if (hdev->reset_type != HNAE3_NONE_RESET) 2861 hclge_do_reset(hdev); 2862 2863 hdev->reset_type = HNAE3_NONE_RESET; 2864 } 2865 2866 static void hclge_reset_service_task(struct work_struct *work) 2867 { 2868 struct hclge_dev *hdev = 2869 container_of(work, struct hclge_dev, rst_service_task); 2870 2871 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 2872 return; 2873 2874 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 2875 2876 hclge_reset_subtask(hdev); 2877 2878 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 2879 } 2880 2881 static void hclge_mailbox_service_task(struct work_struct *work) 2882 { 2883 struct hclge_dev *hdev = 2884 container_of(work, struct hclge_dev, mbx_service_task); 2885 2886 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 2887 return; 2888 2889 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 2890 2891 hclge_mbx_handler(hdev); 2892 2893 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 2894 } 2895 2896 static void hclge_service_task(struct work_struct *work) 2897 { 2898 struct hclge_dev *hdev = 2899 container_of(work, struct hclge_dev, service_task); 2900 2901 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) { 2902 hclge_update_stats_for_all(hdev); 2903 hdev->hw_stats.stats_timer = 0; 2904 } 2905 2906 hclge_update_speed_duplex(hdev); 2907 hclge_update_link_status(hdev); 2908 hclge_service_complete(hdev); 2909 } 2910 2911 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 2912 { 2913 /* VF handle has no client */ 2914 if (!handle->client) 2915 return container_of(handle, struct hclge_vport, nic); 2916 else if (handle->client->type == HNAE3_CLIENT_ROCE) 2917 return container_of(handle, struct hclge_vport, roce); 2918 else 2919 return container_of(handle, struct hclge_vport, nic); 2920 } 2921 2922 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 2923 struct hnae3_vector_info *vector_info) 2924 { 2925 struct hclge_vport *vport = hclge_get_vport(handle); 2926 struct hnae3_vector_info *vector = vector_info; 2927 struct hclge_dev *hdev = vport->back; 2928 int alloc = 0; 2929 int i, j; 2930 2931 vector_num = min(hdev->num_msi_left, vector_num); 2932 2933 for (j = 0; j < vector_num; j++) { 2934 for (i = 1; i < hdev->num_msi; i++) { 2935 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 2936 vector->vector = pci_irq_vector(hdev->pdev, i); 2937 vector->io_addr = hdev->hw.io_base + 2938 HCLGE_VECTOR_REG_BASE + 2939 (i - 1) * HCLGE_VECTOR_REG_OFFSET + 2940 vport->vport_id * 2941 HCLGE_VECTOR_VF_OFFSET; 2942 hdev->vector_status[i] = vport->vport_id; 2943 hdev->vector_irq[i] = vector->vector; 2944 2945 vector++; 2946 alloc++; 2947 2948 break; 2949 } 2950 } 2951 } 2952 hdev->num_msi_left -= alloc; 2953 hdev->num_msi_used += alloc; 2954 2955 return alloc; 2956 } 2957 2958 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 2959 { 2960 int i; 2961 2962 for (i = 0; i < hdev->num_msi; i++) 2963 if (vector == hdev->vector_irq[i]) 2964 return i; 2965 2966 return -EINVAL; 2967 } 2968 2969 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 2970 { 2971 struct hclge_vport *vport = hclge_get_vport(handle); 2972 struct hclge_dev *hdev = vport->back; 2973 int vector_id; 2974 2975 vector_id = hclge_get_vector_index(hdev, vector); 2976 if (vector_id < 0) { 2977 dev_err(&hdev->pdev->dev, 2978 "Get vector index fail. vector_id =%d\n", vector_id); 2979 return vector_id; 2980 } 2981 2982 hclge_free_vector(hdev, vector_id); 2983 2984 return 0; 2985 } 2986 2987 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle) 2988 { 2989 return HCLGE_RSS_KEY_SIZE; 2990 } 2991 2992 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle) 2993 { 2994 return HCLGE_RSS_IND_TBL_SIZE; 2995 } 2996 2997 static int hclge_set_rss_algo_key(struct hclge_dev *hdev, 2998 const u8 hfunc, const u8 *key) 2999 { 3000 struct hclge_rss_config_cmd *req; 3001 struct hclge_desc desc; 3002 int key_offset; 3003 int key_size; 3004 int ret; 3005 3006 req = (struct hclge_rss_config_cmd *)desc.data; 3007 3008 for (key_offset = 0; key_offset < 3; key_offset++) { 3009 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, 3010 false); 3011 3012 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK); 3013 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B); 3014 3015 if (key_offset == 2) 3016 key_size = 3017 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2; 3018 else 3019 key_size = HCLGE_RSS_HASH_KEY_NUM; 3020 3021 memcpy(req->hash_key, 3022 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size); 3023 3024 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3025 if (ret) { 3026 dev_err(&hdev->pdev->dev, 3027 "Configure RSS config fail, status = %d\n", 3028 ret); 3029 return ret; 3030 } 3031 } 3032 return 0; 3033 } 3034 3035 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir) 3036 { 3037 struct hclge_rss_indirection_table_cmd *req; 3038 struct hclge_desc desc; 3039 int i, j; 3040 int ret; 3041 3042 req = (struct hclge_rss_indirection_table_cmd *)desc.data; 3043 3044 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) { 3045 hclge_cmd_setup_basic_desc 3046 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false); 3047 3048 req->start_table_index = 3049 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE); 3050 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK); 3051 3052 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++) 3053 req->rss_result[j] = 3054 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j]; 3055 3056 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3057 if (ret) { 3058 dev_err(&hdev->pdev->dev, 3059 "Configure rss indir table fail,status = %d\n", 3060 ret); 3061 return ret; 3062 } 3063 } 3064 return 0; 3065 } 3066 3067 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid, 3068 u16 *tc_size, u16 *tc_offset) 3069 { 3070 struct hclge_rss_tc_mode_cmd *req; 3071 struct hclge_desc desc; 3072 int ret; 3073 int i; 3074 3075 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false); 3076 req = (struct hclge_rss_tc_mode_cmd *)desc.data; 3077 3078 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 3079 u16 mode = 0; 3080 3081 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1)); 3082 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M, 3083 HCLGE_RSS_TC_SIZE_S, tc_size[i]); 3084 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M, 3085 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]); 3086 3087 req->rss_tc_mode[i] = cpu_to_le16(mode); 3088 } 3089 3090 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3091 if (ret) 3092 dev_err(&hdev->pdev->dev, 3093 "Configure rss tc mode fail, status = %d\n", ret); 3094 3095 return ret; 3096 } 3097 3098 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev) 3099 { 3100 struct hclge_rss_input_tuple_cmd *req; 3101 struct hclge_desc desc; 3102 int ret; 3103 3104 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false); 3105 3106 req = (struct hclge_rss_input_tuple_cmd *)desc.data; 3107 3108 /* Get the tuple cfg from pf */ 3109 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en; 3110 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en; 3111 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en; 3112 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en; 3113 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en; 3114 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en; 3115 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en; 3116 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en; 3117 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3118 if (ret) 3119 dev_err(&hdev->pdev->dev, 3120 "Configure rss input fail, status = %d\n", ret); 3121 return ret; 3122 } 3123 3124 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 3125 u8 *key, u8 *hfunc) 3126 { 3127 struct hclge_vport *vport = hclge_get_vport(handle); 3128 int i; 3129 3130 /* Get hash algorithm */ 3131 if (hfunc) 3132 *hfunc = vport->rss_algo; 3133 3134 /* Get the RSS Key required by the user */ 3135 if (key) 3136 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE); 3137 3138 /* Get indirect table */ 3139 if (indir) 3140 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) 3141 indir[i] = vport->rss_indirection_tbl[i]; 3142 3143 return 0; 3144 } 3145 3146 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 3147 const u8 *key, const u8 hfunc) 3148 { 3149 struct hclge_vport *vport = hclge_get_vport(handle); 3150 struct hclge_dev *hdev = vport->back; 3151 u8 hash_algo; 3152 int ret, i; 3153 3154 /* Set the RSS Hash Key if specififed by the user */ 3155 if (key) { 3156 3157 if (hfunc == ETH_RSS_HASH_TOP || 3158 hfunc == ETH_RSS_HASH_NO_CHANGE) 3159 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ; 3160 else 3161 return -EINVAL; 3162 ret = hclge_set_rss_algo_key(hdev, hash_algo, key); 3163 if (ret) 3164 return ret; 3165 3166 /* Update the shadow RSS key with user specified qids */ 3167 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE); 3168 vport->rss_algo = hash_algo; 3169 } 3170 3171 /* Update the shadow RSS table with user specified qids */ 3172 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) 3173 vport->rss_indirection_tbl[i] = indir[i]; 3174 3175 /* Update the hardware */ 3176 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl); 3177 } 3178 3179 static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc) 3180 { 3181 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0; 3182 3183 if (nfc->data & RXH_L4_B_2_3) 3184 hash_sets |= HCLGE_D_PORT_BIT; 3185 else 3186 hash_sets &= ~HCLGE_D_PORT_BIT; 3187 3188 if (nfc->data & RXH_IP_SRC) 3189 hash_sets |= HCLGE_S_IP_BIT; 3190 else 3191 hash_sets &= ~HCLGE_S_IP_BIT; 3192 3193 if (nfc->data & RXH_IP_DST) 3194 hash_sets |= HCLGE_D_IP_BIT; 3195 else 3196 hash_sets &= ~HCLGE_D_IP_BIT; 3197 3198 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) 3199 hash_sets |= HCLGE_V_TAG_BIT; 3200 3201 return hash_sets; 3202 } 3203 3204 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 3205 struct ethtool_rxnfc *nfc) 3206 { 3207 struct hclge_vport *vport = hclge_get_vport(handle); 3208 struct hclge_dev *hdev = vport->back; 3209 struct hclge_rss_input_tuple_cmd *req; 3210 struct hclge_desc desc; 3211 u8 tuple_sets; 3212 int ret; 3213 3214 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 3215 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 3216 return -EINVAL; 3217 3218 req = (struct hclge_rss_input_tuple_cmd *)desc.data; 3219 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false); 3220 3221 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en; 3222 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en; 3223 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en; 3224 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en; 3225 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en; 3226 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en; 3227 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en; 3228 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en; 3229 3230 tuple_sets = hclge_get_rss_hash_bits(nfc); 3231 switch (nfc->flow_type) { 3232 case TCP_V4_FLOW: 3233 req->ipv4_tcp_en = tuple_sets; 3234 break; 3235 case TCP_V6_FLOW: 3236 req->ipv6_tcp_en = tuple_sets; 3237 break; 3238 case UDP_V4_FLOW: 3239 req->ipv4_udp_en = tuple_sets; 3240 break; 3241 case UDP_V6_FLOW: 3242 req->ipv6_udp_en = tuple_sets; 3243 break; 3244 case SCTP_V4_FLOW: 3245 req->ipv4_sctp_en = tuple_sets; 3246 break; 3247 case SCTP_V6_FLOW: 3248 if ((nfc->data & RXH_L4_B_0_1) || 3249 (nfc->data & RXH_L4_B_2_3)) 3250 return -EINVAL; 3251 3252 req->ipv6_sctp_en = tuple_sets; 3253 break; 3254 case IPV4_FLOW: 3255 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; 3256 break; 3257 case IPV6_FLOW: 3258 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; 3259 break; 3260 default: 3261 return -EINVAL; 3262 } 3263 3264 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3265 if (ret) { 3266 dev_err(&hdev->pdev->dev, 3267 "Set rss tuple fail, status = %d\n", ret); 3268 return ret; 3269 } 3270 3271 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; 3272 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; 3273 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; 3274 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; 3275 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; 3276 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; 3277 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; 3278 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; 3279 return 0; 3280 } 3281 3282 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 3283 struct ethtool_rxnfc *nfc) 3284 { 3285 struct hclge_vport *vport = hclge_get_vport(handle); 3286 u8 tuple_sets; 3287 3288 nfc->data = 0; 3289 3290 switch (nfc->flow_type) { 3291 case TCP_V4_FLOW: 3292 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en; 3293 break; 3294 case UDP_V4_FLOW: 3295 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en; 3296 break; 3297 case TCP_V6_FLOW: 3298 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en; 3299 break; 3300 case UDP_V6_FLOW: 3301 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en; 3302 break; 3303 case SCTP_V4_FLOW: 3304 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en; 3305 break; 3306 case SCTP_V6_FLOW: 3307 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en; 3308 break; 3309 case IPV4_FLOW: 3310 case IPV6_FLOW: 3311 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT; 3312 break; 3313 default: 3314 return -EINVAL; 3315 } 3316 3317 if (!tuple_sets) 3318 return 0; 3319 3320 if (tuple_sets & HCLGE_D_PORT_BIT) 3321 nfc->data |= RXH_L4_B_2_3; 3322 if (tuple_sets & HCLGE_S_PORT_BIT) 3323 nfc->data |= RXH_L4_B_0_1; 3324 if (tuple_sets & HCLGE_D_IP_BIT) 3325 nfc->data |= RXH_IP_DST; 3326 if (tuple_sets & HCLGE_S_IP_BIT) 3327 nfc->data |= RXH_IP_SRC; 3328 3329 return 0; 3330 } 3331 3332 static int hclge_get_tc_size(struct hnae3_handle *handle) 3333 { 3334 struct hclge_vport *vport = hclge_get_vport(handle); 3335 struct hclge_dev *hdev = vport->back; 3336 3337 return hdev->rss_size_max; 3338 } 3339 3340 int hclge_rss_init_hw(struct hclge_dev *hdev) 3341 { 3342 struct hclge_vport *vport = hdev->vport; 3343 u8 *rss_indir = vport[0].rss_indirection_tbl; 3344 u16 rss_size = vport[0].alloc_rss_size; 3345 u8 *key = vport[0].rss_hash_key; 3346 u8 hfunc = vport[0].rss_algo; 3347 u16 tc_offset[HCLGE_MAX_TC_NUM]; 3348 u16 tc_valid[HCLGE_MAX_TC_NUM]; 3349 u16 tc_size[HCLGE_MAX_TC_NUM]; 3350 u16 roundup_size; 3351 int i, ret; 3352 3353 ret = hclge_set_rss_indir_table(hdev, rss_indir); 3354 if (ret) 3355 return ret; 3356 3357 ret = hclge_set_rss_algo_key(hdev, hfunc, key); 3358 if (ret) 3359 return ret; 3360 3361 ret = hclge_set_rss_input_tuple(hdev); 3362 if (ret) 3363 return ret; 3364 3365 /* Each TC have the same queue size, and tc_size set to hardware is 3366 * the log2 of roundup power of two of rss_size, the acutal queue 3367 * size is limited by indirection table. 3368 */ 3369 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) { 3370 dev_err(&hdev->pdev->dev, 3371 "Configure rss tc size failed, invalid TC_SIZE = %d\n", 3372 rss_size); 3373 return -EINVAL; 3374 } 3375 3376 roundup_size = roundup_pow_of_two(rss_size); 3377 roundup_size = ilog2(roundup_size); 3378 3379 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 3380 tc_valid[i] = 0; 3381 3382 if (!(hdev->hw_tc_map & BIT(i))) 3383 continue; 3384 3385 tc_valid[i] = 1; 3386 tc_size[i] = roundup_size; 3387 tc_offset[i] = rss_size * i; 3388 } 3389 3390 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset); 3391 } 3392 3393 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev) 3394 { 3395 struct hclge_vport *vport = hdev->vport; 3396 int i, j; 3397 3398 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) { 3399 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) 3400 vport[j].rss_indirection_tbl[i] = 3401 i % vport[j].alloc_rss_size; 3402 } 3403 } 3404 3405 static void hclge_rss_init_cfg(struct hclge_dev *hdev) 3406 { 3407 struct hclge_vport *vport = hdev->vport; 3408 int i; 3409 3410 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 3411 vport[i].rss_tuple_sets.ipv4_tcp_en = 3412 HCLGE_RSS_INPUT_TUPLE_OTHER; 3413 vport[i].rss_tuple_sets.ipv4_udp_en = 3414 HCLGE_RSS_INPUT_TUPLE_OTHER; 3415 vport[i].rss_tuple_sets.ipv4_sctp_en = 3416 HCLGE_RSS_INPUT_TUPLE_SCTP; 3417 vport[i].rss_tuple_sets.ipv4_fragment_en = 3418 HCLGE_RSS_INPUT_TUPLE_OTHER; 3419 vport[i].rss_tuple_sets.ipv6_tcp_en = 3420 HCLGE_RSS_INPUT_TUPLE_OTHER; 3421 vport[i].rss_tuple_sets.ipv6_udp_en = 3422 HCLGE_RSS_INPUT_TUPLE_OTHER; 3423 vport[i].rss_tuple_sets.ipv6_sctp_en = 3424 HCLGE_RSS_INPUT_TUPLE_SCTP; 3425 vport[i].rss_tuple_sets.ipv6_fragment_en = 3426 HCLGE_RSS_INPUT_TUPLE_OTHER; 3427 3428 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ; 3429 3430 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE); 3431 } 3432 3433 hclge_rss_indir_init_cfg(hdev); 3434 } 3435 3436 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 3437 int vector_id, bool en, 3438 struct hnae3_ring_chain_node *ring_chain) 3439 { 3440 struct hclge_dev *hdev = vport->back; 3441 struct hnae3_ring_chain_node *node; 3442 struct hclge_desc desc; 3443 struct hclge_ctrl_vector_chain_cmd *req 3444 = (struct hclge_ctrl_vector_chain_cmd *)desc.data; 3445 enum hclge_cmd_status status; 3446 enum hclge_opcode_type op; 3447 u16 tqp_type_and_id; 3448 int i; 3449 3450 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 3451 hclge_cmd_setup_basic_desc(&desc, op, false); 3452 req->int_vector_id = vector_id; 3453 3454 i = 0; 3455 for (node = ring_chain; node; node = node->next) { 3456 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 3457 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 3458 HCLGE_INT_TYPE_S, 3459 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 3460 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 3461 HCLGE_TQP_ID_S, node->tqp_index); 3462 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 3463 HCLGE_INT_GL_IDX_S, 3464 hnae3_get_field(node->int_gl_idx, 3465 HNAE3_RING_GL_IDX_M, 3466 HNAE3_RING_GL_IDX_S)); 3467 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 3468 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 3469 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 3470 req->vfid = vport->vport_id; 3471 3472 status = hclge_cmd_send(&hdev->hw, &desc, 1); 3473 if (status) { 3474 dev_err(&hdev->pdev->dev, 3475 "Map TQP fail, status is %d.\n", 3476 status); 3477 return -EIO; 3478 } 3479 i = 0; 3480 3481 hclge_cmd_setup_basic_desc(&desc, 3482 op, 3483 false); 3484 req->int_vector_id = vector_id; 3485 } 3486 } 3487 3488 if (i > 0) { 3489 req->int_cause_num = i; 3490 req->vfid = vport->vport_id; 3491 status = hclge_cmd_send(&hdev->hw, &desc, 1); 3492 if (status) { 3493 dev_err(&hdev->pdev->dev, 3494 "Map TQP fail, status is %d.\n", status); 3495 return -EIO; 3496 } 3497 } 3498 3499 return 0; 3500 } 3501 3502 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, 3503 int vector, 3504 struct hnae3_ring_chain_node *ring_chain) 3505 { 3506 struct hclge_vport *vport = hclge_get_vport(handle); 3507 struct hclge_dev *hdev = vport->back; 3508 int vector_id; 3509 3510 vector_id = hclge_get_vector_index(hdev, vector); 3511 if (vector_id < 0) { 3512 dev_err(&hdev->pdev->dev, 3513 "Get vector index fail. vector_id =%d\n", vector_id); 3514 return vector_id; 3515 } 3516 3517 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 3518 } 3519 3520 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, 3521 int vector, 3522 struct hnae3_ring_chain_node *ring_chain) 3523 { 3524 struct hclge_vport *vport = hclge_get_vport(handle); 3525 struct hclge_dev *hdev = vport->back; 3526 int vector_id, ret; 3527 3528 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 3529 return 0; 3530 3531 vector_id = hclge_get_vector_index(hdev, vector); 3532 if (vector_id < 0) { 3533 dev_err(&handle->pdev->dev, 3534 "Get vector index fail. ret =%d\n", vector_id); 3535 return vector_id; 3536 } 3537 3538 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 3539 if (ret) 3540 dev_err(&handle->pdev->dev, 3541 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 3542 vector_id, 3543 ret); 3544 3545 return ret; 3546 } 3547 3548 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, 3549 struct hclge_promisc_param *param) 3550 { 3551 struct hclge_promisc_cfg_cmd *req; 3552 struct hclge_desc desc; 3553 int ret; 3554 3555 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 3556 3557 req = (struct hclge_promisc_cfg_cmd *)desc.data; 3558 req->vf_id = param->vf_id; 3559 3560 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on 3561 * pdev revision(0x20), new revision support them. The 3562 * value of this two fields will not return error when driver 3563 * send command to fireware in revision(0x20). 3564 */ 3565 req->flag = (param->enable << HCLGE_PROMISC_EN_B) | 3566 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B; 3567 3568 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3569 if (ret) 3570 dev_err(&hdev->pdev->dev, 3571 "Set promisc mode fail, status is %d.\n", ret); 3572 3573 return ret; 3574 } 3575 3576 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc, 3577 bool en_mc, bool en_bc, int vport_id) 3578 { 3579 if (!param) 3580 return; 3581 3582 memset(param, 0, sizeof(struct hclge_promisc_param)); 3583 if (en_uc) 3584 param->enable = HCLGE_PROMISC_EN_UC; 3585 if (en_mc) 3586 param->enable |= HCLGE_PROMISC_EN_MC; 3587 if (en_bc) 3588 param->enable |= HCLGE_PROMISC_EN_BC; 3589 param->vf_id = vport_id; 3590 } 3591 3592 static void hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 3593 bool en_mc_pmc) 3594 { 3595 struct hclge_vport *vport = hclge_get_vport(handle); 3596 struct hclge_dev *hdev = vport->back; 3597 struct hclge_promisc_param param; 3598 3599 hclge_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, true, 3600 vport->vport_id); 3601 hclge_cmd_set_promisc_mode(hdev, ¶m); 3602 } 3603 3604 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 3605 { 3606 struct hclge_desc desc; 3607 struct hclge_config_mac_mode_cmd *req = 3608 (struct hclge_config_mac_mode_cmd *)desc.data; 3609 u32 loop_en = 0; 3610 int ret; 3611 3612 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 3613 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable); 3614 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable); 3615 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable); 3616 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable); 3617 hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0); 3618 hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0); 3619 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0); 3620 hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0); 3621 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable); 3622 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable); 3623 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable); 3624 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable); 3625 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable); 3626 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable); 3627 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 3628 3629 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3630 if (ret) 3631 dev_err(&hdev->pdev->dev, 3632 "mac enable fail, ret =%d.\n", ret); 3633 } 3634 3635 static int hclge_set_mac_loopback(struct hclge_dev *hdev, bool en) 3636 { 3637 struct hclge_config_mac_mode_cmd *req; 3638 struct hclge_desc desc; 3639 u32 loop_en; 3640 int ret; 3641 3642 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 3643 /* 1 Read out the MAC mode config at first */ 3644 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 3645 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3646 if (ret) { 3647 dev_err(&hdev->pdev->dev, 3648 "mac loopback get fail, ret =%d.\n", ret); 3649 return ret; 3650 } 3651 3652 /* 2 Then setup the loopback flag */ 3653 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 3654 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 3655 3656 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 3657 3658 /* 3 Config mac work mode with loopback flag 3659 * and its original configure parameters 3660 */ 3661 hclge_cmd_reuse_desc(&desc, false); 3662 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3663 if (ret) 3664 dev_err(&hdev->pdev->dev, 3665 "mac loopback set fail, ret =%d.\n", ret); 3666 return ret; 3667 } 3668 3669 static int hclge_set_loopback(struct hnae3_handle *handle, 3670 enum hnae3_loop loop_mode, bool en) 3671 { 3672 struct hclge_vport *vport = hclge_get_vport(handle); 3673 struct hclge_dev *hdev = vport->back; 3674 int ret; 3675 3676 switch (loop_mode) { 3677 case HNAE3_MAC_INTER_LOOP_MAC: 3678 ret = hclge_set_mac_loopback(hdev, en); 3679 break; 3680 default: 3681 ret = -ENOTSUPP; 3682 dev_err(&hdev->pdev->dev, 3683 "loop_mode %d is not supported\n", loop_mode); 3684 break; 3685 } 3686 3687 return ret; 3688 } 3689 3690 static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id, 3691 int stream_id, bool enable) 3692 { 3693 struct hclge_desc desc; 3694 struct hclge_cfg_com_tqp_queue_cmd *req = 3695 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 3696 int ret; 3697 3698 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 3699 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK); 3700 req->stream_id = cpu_to_le16(stream_id); 3701 req->enable |= enable << HCLGE_TQP_ENABLE_B; 3702 3703 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3704 if (ret) 3705 dev_err(&hdev->pdev->dev, 3706 "Tqp enable fail, status =%d.\n", ret); 3707 return ret; 3708 } 3709 3710 static void hclge_reset_tqp_stats(struct hnae3_handle *handle) 3711 { 3712 struct hclge_vport *vport = hclge_get_vport(handle); 3713 struct hnae3_queue *queue; 3714 struct hclge_tqp *tqp; 3715 int i; 3716 3717 for (i = 0; i < vport->alloc_tqps; i++) { 3718 queue = handle->kinfo.tqp[i]; 3719 tqp = container_of(queue, struct hclge_tqp, q); 3720 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); 3721 } 3722 } 3723 3724 static int hclge_ae_start(struct hnae3_handle *handle) 3725 { 3726 struct hclge_vport *vport = hclge_get_vport(handle); 3727 struct hclge_dev *hdev = vport->back; 3728 int i, ret; 3729 3730 for (i = 0; i < vport->alloc_tqps; i++) 3731 hclge_tqp_enable(hdev, i, 0, true); 3732 3733 /* mac enable */ 3734 hclge_cfg_mac_mode(hdev, true); 3735 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 3736 mod_timer(&hdev->service_timer, jiffies + HZ); 3737 hdev->hw.mac.link = 0; 3738 3739 /* reset tqp stats */ 3740 hclge_reset_tqp_stats(handle); 3741 3742 ret = hclge_mac_start_phy(hdev); 3743 if (ret) 3744 return ret; 3745 3746 return 0; 3747 } 3748 3749 static void hclge_ae_stop(struct hnae3_handle *handle) 3750 { 3751 struct hclge_vport *vport = hclge_get_vport(handle); 3752 struct hclge_dev *hdev = vport->back; 3753 int i; 3754 3755 del_timer_sync(&hdev->service_timer); 3756 cancel_work_sync(&hdev->service_task); 3757 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state); 3758 3759 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { 3760 hclge_mac_stop_phy(hdev); 3761 return; 3762 } 3763 3764 for (i = 0; i < vport->alloc_tqps; i++) 3765 hclge_tqp_enable(hdev, i, 0, false); 3766 3767 /* Mac disable */ 3768 hclge_cfg_mac_mode(hdev, false); 3769 3770 hclge_mac_stop_phy(hdev); 3771 3772 /* reset tqp stats */ 3773 hclge_reset_tqp_stats(handle); 3774 del_timer_sync(&hdev->service_timer); 3775 cancel_work_sync(&hdev->service_task); 3776 hclge_update_link_status(hdev); 3777 } 3778 3779 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 3780 u16 cmdq_resp, u8 resp_code, 3781 enum hclge_mac_vlan_tbl_opcode op) 3782 { 3783 struct hclge_dev *hdev = vport->back; 3784 int return_status = -EIO; 3785 3786 if (cmdq_resp) { 3787 dev_err(&hdev->pdev->dev, 3788 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n", 3789 cmdq_resp); 3790 return -EIO; 3791 } 3792 3793 if (op == HCLGE_MAC_VLAN_ADD) { 3794 if ((!resp_code) || (resp_code == 1)) { 3795 return_status = 0; 3796 } else if (resp_code == 2) { 3797 return_status = -ENOSPC; 3798 dev_err(&hdev->pdev->dev, 3799 "add mac addr failed for uc_overflow.\n"); 3800 } else if (resp_code == 3) { 3801 return_status = -ENOSPC; 3802 dev_err(&hdev->pdev->dev, 3803 "add mac addr failed for mc_overflow.\n"); 3804 } else { 3805 dev_err(&hdev->pdev->dev, 3806 "add mac addr failed for undefined, code=%d.\n", 3807 resp_code); 3808 } 3809 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 3810 if (!resp_code) { 3811 return_status = 0; 3812 } else if (resp_code == 1) { 3813 return_status = -ENOENT; 3814 dev_dbg(&hdev->pdev->dev, 3815 "remove mac addr failed for miss.\n"); 3816 } else { 3817 dev_err(&hdev->pdev->dev, 3818 "remove mac addr failed for undefined, code=%d.\n", 3819 resp_code); 3820 } 3821 } else if (op == HCLGE_MAC_VLAN_LKUP) { 3822 if (!resp_code) { 3823 return_status = 0; 3824 } else if (resp_code == 1) { 3825 return_status = -ENOENT; 3826 dev_dbg(&hdev->pdev->dev, 3827 "lookup mac addr failed for miss.\n"); 3828 } else { 3829 dev_err(&hdev->pdev->dev, 3830 "lookup mac addr failed for undefined, code=%d.\n", 3831 resp_code); 3832 } 3833 } else { 3834 return_status = -EINVAL; 3835 dev_err(&hdev->pdev->dev, 3836 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n", 3837 op); 3838 } 3839 3840 return return_status; 3841 } 3842 3843 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 3844 { 3845 int word_num; 3846 int bit_num; 3847 3848 if (vfid > 255 || vfid < 0) 3849 return -EIO; 3850 3851 if (vfid >= 0 && vfid <= 191) { 3852 word_num = vfid / 32; 3853 bit_num = vfid % 32; 3854 if (clr) 3855 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 3856 else 3857 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 3858 } else { 3859 word_num = (vfid - 192) / 32; 3860 bit_num = vfid % 32; 3861 if (clr) 3862 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 3863 else 3864 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 3865 } 3866 3867 return 0; 3868 } 3869 3870 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 3871 { 3872 #define HCLGE_DESC_NUMBER 3 3873 #define HCLGE_FUNC_NUMBER_PER_DESC 6 3874 int i, j; 3875 3876 for (i = 0; i < HCLGE_DESC_NUMBER; i++) 3877 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 3878 if (desc[i].data[j]) 3879 return false; 3880 3881 return true; 3882 } 3883 3884 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 3885 const u8 *addr) 3886 { 3887 const unsigned char *mac_addr = addr; 3888 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 3889 (mac_addr[0]) | (mac_addr[1] << 8); 3890 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 3891 3892 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 3893 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 3894 } 3895 3896 static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport, 3897 const u8 *addr) 3898 { 3899 u16 high_val = addr[1] | (addr[0] << 8); 3900 struct hclge_dev *hdev = vport->back; 3901 u32 rsh = 4 - hdev->mta_mac_sel_type; 3902 u16 ret_val = (high_val >> rsh) & 0xfff; 3903 3904 return ret_val; 3905 } 3906 3907 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev, 3908 enum hclge_mta_dmac_sel_type mta_mac_sel, 3909 bool enable) 3910 { 3911 struct hclge_mta_filter_mode_cmd *req; 3912 struct hclge_desc desc; 3913 int ret; 3914 3915 req = (struct hclge_mta_filter_mode_cmd *)desc.data; 3916 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false); 3917 3918 hnae3_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B, 3919 enable); 3920 hnae3_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M, 3921 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel); 3922 3923 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3924 if (ret) 3925 dev_err(&hdev->pdev->dev, 3926 "Config mat filter mode failed for cmd_send, ret =%d.\n", 3927 ret); 3928 3929 return ret; 3930 } 3931 3932 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev, 3933 u8 func_id, 3934 bool enable) 3935 { 3936 struct hclge_cfg_func_mta_filter_cmd *req; 3937 struct hclge_desc desc; 3938 int ret; 3939 3940 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data; 3941 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false); 3942 3943 hnae3_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B, 3944 enable); 3945 req->function_id = func_id; 3946 3947 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3948 if (ret) 3949 dev_err(&hdev->pdev->dev, 3950 "Config func_id enable failed for cmd_send, ret =%d.\n", 3951 ret); 3952 3953 return ret; 3954 } 3955 3956 static int hclge_set_mta_table_item(struct hclge_vport *vport, 3957 u16 idx, 3958 bool enable) 3959 { 3960 struct hclge_dev *hdev = vport->back; 3961 struct hclge_cfg_func_mta_item_cmd *req; 3962 struct hclge_desc desc; 3963 u16 item_idx = 0; 3964 int ret; 3965 3966 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data; 3967 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false); 3968 hnae3_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable); 3969 3970 hnae3_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M, 3971 HCLGE_CFG_MTA_ITEM_IDX_S, idx); 3972 req->item_idx = cpu_to_le16(item_idx); 3973 3974 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3975 if (ret) { 3976 dev_err(&hdev->pdev->dev, 3977 "Config mta table item failed for cmd_send, ret =%d.\n", 3978 ret); 3979 return ret; 3980 } 3981 3982 if (enable) 3983 set_bit(idx, vport->mta_shadow); 3984 else 3985 clear_bit(idx, vport->mta_shadow); 3986 3987 return 0; 3988 } 3989 3990 static int hclge_update_mta_status(struct hnae3_handle *handle) 3991 { 3992 unsigned long mta_status[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)]; 3993 struct hclge_vport *vport = hclge_get_vport(handle); 3994 struct net_device *netdev = handle->kinfo.netdev; 3995 struct netdev_hw_addr *ha; 3996 u16 tbl_idx; 3997 3998 memset(mta_status, 0, sizeof(mta_status)); 3999 4000 /* update mta_status from mc addr list */ 4001 netdev_for_each_mc_addr(ha, netdev) { 4002 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, ha->addr); 4003 set_bit(tbl_idx, mta_status); 4004 } 4005 4006 return hclge_update_mta_status_common(vport, mta_status, 4007 0, HCLGE_MTA_TBL_SIZE, true); 4008 } 4009 4010 int hclge_update_mta_status_common(struct hclge_vport *vport, 4011 unsigned long *status, 4012 u16 idx, 4013 u16 count, 4014 bool update_filter) 4015 { 4016 struct hclge_dev *hdev = vport->back; 4017 u16 update_max = idx + count; 4018 u16 check_max; 4019 int ret = 0; 4020 bool used; 4021 u16 i; 4022 4023 /* setup mta check range */ 4024 if (update_filter) { 4025 i = 0; 4026 check_max = HCLGE_MTA_TBL_SIZE; 4027 } else { 4028 i = idx; 4029 check_max = update_max; 4030 } 4031 4032 used = false; 4033 /* check and update all mta item */ 4034 for (; i < check_max; i++) { 4035 /* ignore unused item */ 4036 if (!test_bit(i, vport->mta_shadow)) 4037 continue; 4038 4039 /* if i in update range then update it */ 4040 if (i >= idx && i < update_max) 4041 if (!test_bit(i - idx, status)) 4042 hclge_set_mta_table_item(vport, i, false); 4043 4044 if (!used && test_bit(i, vport->mta_shadow)) 4045 used = true; 4046 } 4047 4048 /* no longer use mta, disable it */ 4049 if (vport->accept_mta_mc && update_filter && !used) { 4050 ret = hclge_cfg_func_mta_filter(hdev, 4051 vport->vport_id, 4052 false); 4053 if (ret) 4054 dev_err(&hdev->pdev->dev, 4055 "disable func mta filter fail ret=%d\n", 4056 ret); 4057 else 4058 vport->accept_mta_mc = false; 4059 } 4060 4061 return ret; 4062 } 4063 4064 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 4065 struct hclge_mac_vlan_tbl_entry_cmd *req) 4066 { 4067 struct hclge_dev *hdev = vport->back; 4068 struct hclge_desc desc; 4069 u8 resp_code; 4070 u16 retval; 4071 int ret; 4072 4073 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 4074 4075 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4076 4077 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4078 if (ret) { 4079 dev_err(&hdev->pdev->dev, 4080 "del mac addr failed for cmd_send, ret =%d.\n", 4081 ret); 4082 return ret; 4083 } 4084 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 4085 retval = le16_to_cpu(desc.retval); 4086 4087 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 4088 HCLGE_MAC_VLAN_REMOVE); 4089 } 4090 4091 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 4092 struct hclge_mac_vlan_tbl_entry_cmd *req, 4093 struct hclge_desc *desc, 4094 bool is_mc) 4095 { 4096 struct hclge_dev *hdev = vport->back; 4097 u8 resp_code; 4098 u16 retval; 4099 int ret; 4100 4101 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 4102 if (is_mc) { 4103 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4104 memcpy(desc[0].data, 4105 req, 4106 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4107 hclge_cmd_setup_basic_desc(&desc[1], 4108 HCLGE_OPC_MAC_VLAN_ADD, 4109 true); 4110 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4111 hclge_cmd_setup_basic_desc(&desc[2], 4112 HCLGE_OPC_MAC_VLAN_ADD, 4113 true); 4114 ret = hclge_cmd_send(&hdev->hw, desc, 3); 4115 } else { 4116 memcpy(desc[0].data, 4117 req, 4118 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4119 ret = hclge_cmd_send(&hdev->hw, desc, 1); 4120 } 4121 if (ret) { 4122 dev_err(&hdev->pdev->dev, 4123 "lookup mac addr failed for cmd_send, ret =%d.\n", 4124 ret); 4125 return ret; 4126 } 4127 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 4128 retval = le16_to_cpu(desc[0].retval); 4129 4130 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 4131 HCLGE_MAC_VLAN_LKUP); 4132 } 4133 4134 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 4135 struct hclge_mac_vlan_tbl_entry_cmd *req, 4136 struct hclge_desc *mc_desc) 4137 { 4138 struct hclge_dev *hdev = vport->back; 4139 int cfg_status; 4140 u8 resp_code; 4141 u16 retval; 4142 int ret; 4143 4144 if (!mc_desc) { 4145 struct hclge_desc desc; 4146 4147 hclge_cmd_setup_basic_desc(&desc, 4148 HCLGE_OPC_MAC_VLAN_ADD, 4149 false); 4150 memcpy(desc.data, req, 4151 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4152 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4153 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 4154 retval = le16_to_cpu(desc.retval); 4155 4156 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 4157 resp_code, 4158 HCLGE_MAC_VLAN_ADD); 4159 } else { 4160 hclge_cmd_reuse_desc(&mc_desc[0], false); 4161 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4162 hclge_cmd_reuse_desc(&mc_desc[1], false); 4163 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4164 hclge_cmd_reuse_desc(&mc_desc[2], false); 4165 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT); 4166 memcpy(mc_desc[0].data, req, 4167 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 4168 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 4169 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 4170 retval = le16_to_cpu(mc_desc[0].retval); 4171 4172 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 4173 resp_code, 4174 HCLGE_MAC_VLAN_ADD); 4175 } 4176 4177 if (ret) { 4178 dev_err(&hdev->pdev->dev, 4179 "add mac addr failed for cmd_send, ret =%d.\n", 4180 ret); 4181 return ret; 4182 } 4183 4184 return cfg_status; 4185 } 4186 4187 static int hclge_add_uc_addr(struct hnae3_handle *handle, 4188 const unsigned char *addr) 4189 { 4190 struct hclge_vport *vport = hclge_get_vport(handle); 4191 4192 return hclge_add_uc_addr_common(vport, addr); 4193 } 4194 4195 int hclge_add_uc_addr_common(struct hclge_vport *vport, 4196 const unsigned char *addr) 4197 { 4198 struct hclge_dev *hdev = vport->back; 4199 struct hclge_mac_vlan_tbl_entry_cmd req; 4200 struct hclge_desc desc; 4201 u16 egress_port = 0; 4202 int ret; 4203 4204 /* mac addr check */ 4205 if (is_zero_ether_addr(addr) || 4206 is_broadcast_ether_addr(addr) || 4207 is_multicast_ether_addr(addr)) { 4208 dev_err(&hdev->pdev->dev, 4209 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n", 4210 addr, 4211 is_zero_ether_addr(addr), 4212 is_broadcast_ether_addr(addr), 4213 is_multicast_ether_addr(addr)); 4214 return -EINVAL; 4215 } 4216 4217 memset(&req, 0, sizeof(req)); 4218 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 4219 4220 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 4221 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 4222 4223 req.egress_port = cpu_to_le16(egress_port); 4224 4225 hclge_prepare_mac_addr(&req, addr); 4226 4227 /* Lookup the mac address in the mac_vlan table, and add 4228 * it if the entry is inexistent. Repeated unicast entry 4229 * is not allowed in the mac vlan table. 4230 */ 4231 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 4232 if (ret == -ENOENT) 4233 return hclge_add_mac_vlan_tbl(vport, &req, NULL); 4234 4235 /* check if we just hit the duplicate */ 4236 if (!ret) 4237 ret = -EINVAL; 4238 4239 dev_err(&hdev->pdev->dev, 4240 "PF failed to add unicast entry(%pM) in the MAC table\n", 4241 addr); 4242 4243 return ret; 4244 } 4245 4246 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 4247 const unsigned char *addr) 4248 { 4249 struct hclge_vport *vport = hclge_get_vport(handle); 4250 4251 return hclge_rm_uc_addr_common(vport, addr); 4252 } 4253 4254 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 4255 const unsigned char *addr) 4256 { 4257 struct hclge_dev *hdev = vport->back; 4258 struct hclge_mac_vlan_tbl_entry_cmd req; 4259 int ret; 4260 4261 /* mac addr check */ 4262 if (is_zero_ether_addr(addr) || 4263 is_broadcast_ether_addr(addr) || 4264 is_multicast_ether_addr(addr)) { 4265 dev_dbg(&hdev->pdev->dev, 4266 "Remove mac err! invalid mac:%pM.\n", 4267 addr); 4268 return -EINVAL; 4269 } 4270 4271 memset(&req, 0, sizeof(req)); 4272 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 4273 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4274 hclge_prepare_mac_addr(&req, addr); 4275 ret = hclge_remove_mac_vlan_tbl(vport, &req); 4276 4277 return ret; 4278 } 4279 4280 static int hclge_add_mc_addr(struct hnae3_handle *handle, 4281 const unsigned char *addr) 4282 { 4283 struct hclge_vport *vport = hclge_get_vport(handle); 4284 4285 return hclge_add_mc_addr_common(vport, addr); 4286 } 4287 4288 int hclge_add_mc_addr_common(struct hclge_vport *vport, 4289 const unsigned char *addr) 4290 { 4291 struct hclge_dev *hdev = vport->back; 4292 struct hclge_mac_vlan_tbl_entry_cmd req; 4293 struct hclge_desc desc[3]; 4294 u16 tbl_idx; 4295 int status; 4296 4297 /* mac addr check */ 4298 if (!is_multicast_ether_addr(addr)) { 4299 dev_err(&hdev->pdev->dev, 4300 "Add mc mac err! invalid mac:%pM.\n", 4301 addr); 4302 return -EINVAL; 4303 } 4304 memset(&req, 0, sizeof(req)); 4305 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 4306 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4307 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 4308 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4309 hclge_prepare_mac_addr(&req, addr); 4310 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 4311 if (!status) { 4312 /* This mac addr exist, update VFID for it */ 4313 hclge_update_desc_vfid(desc, vport->vport_id, false); 4314 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 4315 } else { 4316 /* This mac addr do not exist, add new entry for it */ 4317 memset(desc[0].data, 0, sizeof(desc[0].data)); 4318 memset(desc[1].data, 0, sizeof(desc[0].data)); 4319 memset(desc[2].data, 0, sizeof(desc[0].data)); 4320 hclge_update_desc_vfid(desc, vport->vport_id, false); 4321 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 4322 } 4323 4324 /* If mc mac vlan table is full, use MTA table */ 4325 if (status == -ENOSPC) { 4326 if (!vport->accept_mta_mc) { 4327 status = hclge_cfg_func_mta_filter(hdev, 4328 vport->vport_id, 4329 true); 4330 if (status) { 4331 dev_err(&hdev->pdev->dev, 4332 "set mta filter mode fail ret=%d\n", 4333 status); 4334 return status; 4335 } 4336 vport->accept_mta_mc = true; 4337 } 4338 4339 /* Set MTA table for this MAC address */ 4340 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr); 4341 status = hclge_set_mta_table_item(vport, tbl_idx, true); 4342 } 4343 4344 return status; 4345 } 4346 4347 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 4348 const unsigned char *addr) 4349 { 4350 struct hclge_vport *vport = hclge_get_vport(handle); 4351 4352 return hclge_rm_mc_addr_common(vport, addr); 4353 } 4354 4355 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 4356 const unsigned char *addr) 4357 { 4358 struct hclge_dev *hdev = vport->back; 4359 struct hclge_mac_vlan_tbl_entry_cmd req; 4360 enum hclge_cmd_status status; 4361 struct hclge_desc desc[3]; 4362 4363 /* mac addr check */ 4364 if (!is_multicast_ether_addr(addr)) { 4365 dev_dbg(&hdev->pdev->dev, 4366 "Remove mc mac err! invalid mac:%pM.\n", 4367 addr); 4368 return -EINVAL; 4369 } 4370 4371 memset(&req, 0, sizeof(req)); 4372 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 4373 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4374 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 4375 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 4376 hclge_prepare_mac_addr(&req, addr); 4377 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 4378 if (!status) { 4379 /* This mac addr exist, remove this handle's VFID for it */ 4380 hclge_update_desc_vfid(desc, vport->vport_id, true); 4381 4382 if (hclge_is_all_function_id_zero(desc)) 4383 /* All the vfid is zero, so need to delete this entry */ 4384 status = hclge_remove_mac_vlan_tbl(vport, &req); 4385 else 4386 /* Not all the vfid is zero, update the vfid */ 4387 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 4388 4389 } else { 4390 /* Maybe this mac address is in mta table, but it cannot be 4391 * deleted here because an entry of mta represents an address 4392 * range rather than a specific address. the delete action to 4393 * all entries will take effect in update_mta_status called by 4394 * hns3_nic_set_rx_mode. 4395 */ 4396 status = 0; 4397 } 4398 4399 return status; 4400 } 4401 4402 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 4403 u16 cmdq_resp, u8 resp_code) 4404 { 4405 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 4406 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 4407 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 4408 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 4409 4410 int return_status; 4411 4412 if (cmdq_resp) { 4413 dev_err(&hdev->pdev->dev, 4414 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n", 4415 cmdq_resp); 4416 return -EIO; 4417 } 4418 4419 switch (resp_code) { 4420 case HCLGE_ETHERTYPE_SUCCESS_ADD: 4421 case HCLGE_ETHERTYPE_ALREADY_ADD: 4422 return_status = 0; 4423 break; 4424 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 4425 dev_err(&hdev->pdev->dev, 4426 "add mac ethertype failed for manager table overflow.\n"); 4427 return_status = -EIO; 4428 break; 4429 case HCLGE_ETHERTYPE_KEY_CONFLICT: 4430 dev_err(&hdev->pdev->dev, 4431 "add mac ethertype failed for key conflict.\n"); 4432 return_status = -EIO; 4433 break; 4434 default: 4435 dev_err(&hdev->pdev->dev, 4436 "add mac ethertype failed for undefined, code=%d.\n", 4437 resp_code); 4438 return_status = -EIO; 4439 } 4440 4441 return return_status; 4442 } 4443 4444 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 4445 const struct hclge_mac_mgr_tbl_entry_cmd *req) 4446 { 4447 struct hclge_desc desc; 4448 u8 resp_code; 4449 u16 retval; 4450 int ret; 4451 4452 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 4453 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 4454 4455 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4456 if (ret) { 4457 dev_err(&hdev->pdev->dev, 4458 "add mac ethertype failed for cmd_send, ret =%d.\n", 4459 ret); 4460 return ret; 4461 } 4462 4463 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 4464 retval = le16_to_cpu(desc.retval); 4465 4466 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 4467 } 4468 4469 static int init_mgr_tbl(struct hclge_dev *hdev) 4470 { 4471 int ret; 4472 int i; 4473 4474 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 4475 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 4476 if (ret) { 4477 dev_err(&hdev->pdev->dev, 4478 "add mac ethertype failed, ret =%d.\n", 4479 ret); 4480 return ret; 4481 } 4482 } 4483 4484 return 0; 4485 } 4486 4487 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 4488 { 4489 struct hclge_vport *vport = hclge_get_vport(handle); 4490 struct hclge_dev *hdev = vport->back; 4491 4492 ether_addr_copy(p, hdev->hw.mac.mac_addr); 4493 } 4494 4495 static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p, 4496 bool is_first) 4497 { 4498 const unsigned char *new_addr = (const unsigned char *)p; 4499 struct hclge_vport *vport = hclge_get_vport(handle); 4500 struct hclge_dev *hdev = vport->back; 4501 int ret; 4502 4503 /* mac addr check */ 4504 if (is_zero_ether_addr(new_addr) || 4505 is_broadcast_ether_addr(new_addr) || 4506 is_multicast_ether_addr(new_addr)) { 4507 dev_err(&hdev->pdev->dev, 4508 "Change uc mac err! invalid mac:%p.\n", 4509 new_addr); 4510 return -EINVAL; 4511 } 4512 4513 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr)) 4514 dev_warn(&hdev->pdev->dev, 4515 "remove old uc mac address fail.\n"); 4516 4517 ret = hclge_add_uc_addr(handle, new_addr); 4518 if (ret) { 4519 dev_err(&hdev->pdev->dev, 4520 "add uc mac address fail, ret =%d.\n", 4521 ret); 4522 4523 if (!is_first && 4524 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr)) 4525 dev_err(&hdev->pdev->dev, 4526 "restore uc mac address fail.\n"); 4527 4528 return -EIO; 4529 } 4530 4531 ret = hclge_pause_addr_cfg(hdev, new_addr); 4532 if (ret) { 4533 dev_err(&hdev->pdev->dev, 4534 "configure mac pause address fail, ret =%d.\n", 4535 ret); 4536 return -EIO; 4537 } 4538 4539 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 4540 4541 return 0; 4542 } 4543 4544 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 4545 bool filter_en) 4546 { 4547 struct hclge_vlan_filter_ctrl_cmd *req; 4548 struct hclge_desc desc; 4549 int ret; 4550 4551 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false); 4552 4553 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 4554 req->vlan_type = vlan_type; 4555 req->vlan_fe = filter_en; 4556 4557 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4558 if (ret) 4559 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n", 4560 ret); 4561 4562 return ret; 4563 } 4564 4565 #define HCLGE_FILTER_TYPE_VF 0 4566 #define HCLGE_FILTER_TYPE_PORT 1 4567 4568 static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 4569 { 4570 struct hclge_vport *vport = hclge_get_vport(handle); 4571 struct hclge_dev *hdev = vport->back; 4572 4573 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable); 4574 } 4575 4576 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid, 4577 bool is_kill, u16 vlan, u8 qos, 4578 __be16 proto) 4579 { 4580 #define HCLGE_MAX_VF_BYTES 16 4581 struct hclge_vlan_filter_vf_cfg_cmd *req0; 4582 struct hclge_vlan_filter_vf_cfg_cmd *req1; 4583 struct hclge_desc desc[2]; 4584 u8 vf_byte_val; 4585 u8 vf_byte_off; 4586 int ret; 4587 4588 hclge_cmd_setup_basic_desc(&desc[0], 4589 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 4590 hclge_cmd_setup_basic_desc(&desc[1], 4591 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 4592 4593 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 4594 4595 vf_byte_off = vfid / 8; 4596 vf_byte_val = 1 << (vfid % 8); 4597 4598 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 4599 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 4600 4601 req0->vlan_id = cpu_to_le16(vlan); 4602 req0->vlan_cfg = is_kill; 4603 4604 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 4605 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 4606 else 4607 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 4608 4609 ret = hclge_cmd_send(&hdev->hw, desc, 2); 4610 if (ret) { 4611 dev_err(&hdev->pdev->dev, 4612 "Send vf vlan command fail, ret =%d.\n", 4613 ret); 4614 return ret; 4615 } 4616 4617 if (!is_kill) { 4618 #define HCLGE_VF_VLAN_NO_ENTRY 2 4619 if (!req0->resp_code || req0->resp_code == 1) 4620 return 0; 4621 4622 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 4623 dev_warn(&hdev->pdev->dev, 4624 "vf vlan table is full, vf vlan filter is disabled\n"); 4625 return 0; 4626 } 4627 4628 dev_err(&hdev->pdev->dev, 4629 "Add vf vlan filter fail, ret =%d.\n", 4630 req0->resp_code); 4631 } else { 4632 if (!req0->resp_code) 4633 return 0; 4634 4635 dev_err(&hdev->pdev->dev, 4636 "Kill vf vlan filter fail, ret =%d.\n", 4637 req0->resp_code); 4638 } 4639 4640 return -EIO; 4641 } 4642 4643 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 4644 u16 vlan_id, bool is_kill) 4645 { 4646 struct hclge_vlan_filter_pf_cfg_cmd *req; 4647 struct hclge_desc desc; 4648 u8 vlan_offset_byte_val; 4649 u8 vlan_offset_byte; 4650 u8 vlan_offset_160; 4651 int ret; 4652 4653 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 4654 4655 vlan_offset_160 = vlan_id / 160; 4656 vlan_offset_byte = (vlan_id % 160) / 8; 4657 vlan_offset_byte_val = 1 << (vlan_id % 8); 4658 4659 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 4660 req->vlan_offset = vlan_offset_160; 4661 req->vlan_cfg = is_kill; 4662 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 4663 4664 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4665 if (ret) 4666 dev_err(&hdev->pdev->dev, 4667 "port vlan command, send fail, ret =%d.\n", ret); 4668 return ret; 4669 } 4670 4671 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 4672 u16 vport_id, u16 vlan_id, u8 qos, 4673 bool is_kill) 4674 { 4675 u16 vport_idx, vport_num = 0; 4676 int ret; 4677 4678 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id, 4679 0, proto); 4680 if (ret) { 4681 dev_err(&hdev->pdev->dev, 4682 "Set %d vport vlan filter config fail, ret =%d.\n", 4683 vport_id, ret); 4684 return ret; 4685 } 4686 4687 /* vlan 0 may be added twice when 8021q module is enabled */ 4688 if (!is_kill && !vlan_id && 4689 test_bit(vport_id, hdev->vlan_table[vlan_id])) 4690 return 0; 4691 4692 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 4693 dev_err(&hdev->pdev->dev, 4694 "Add port vlan failed, vport %d is already in vlan %d\n", 4695 vport_id, vlan_id); 4696 return -EINVAL; 4697 } 4698 4699 if (is_kill && 4700 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 4701 dev_err(&hdev->pdev->dev, 4702 "Delete port vlan failed, vport %d is not in vlan %d\n", 4703 vport_id, vlan_id); 4704 return -EINVAL; 4705 } 4706 4707 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], VLAN_N_VID) 4708 vport_num++; 4709 4710 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 4711 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 4712 is_kill); 4713 4714 return ret; 4715 } 4716 4717 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 4718 u16 vlan_id, bool is_kill) 4719 { 4720 struct hclge_vport *vport = hclge_get_vport(handle); 4721 struct hclge_dev *hdev = vport->back; 4722 4723 return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id, 4724 0, is_kill); 4725 } 4726 4727 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 4728 u16 vlan, u8 qos, __be16 proto) 4729 { 4730 struct hclge_vport *vport = hclge_get_vport(handle); 4731 struct hclge_dev *hdev = vport->back; 4732 4733 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7)) 4734 return -EINVAL; 4735 if (proto != htons(ETH_P_8021Q)) 4736 return -EPROTONOSUPPORT; 4737 4738 return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false); 4739 } 4740 4741 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 4742 { 4743 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 4744 struct hclge_vport_vtag_tx_cfg_cmd *req; 4745 struct hclge_dev *hdev = vport->back; 4746 struct hclge_desc desc; 4747 int status; 4748 4749 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 4750 4751 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 4752 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 4753 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 4754 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 4755 vcfg->accept_tag1 ? 1 : 0); 4756 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 4757 vcfg->accept_untag1 ? 1 : 0); 4758 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 4759 vcfg->accept_tag2 ? 1 : 0); 4760 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 4761 vcfg->accept_untag2 ? 1 : 0); 4762 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 4763 vcfg->insert_tag1_en ? 1 : 0); 4764 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 4765 vcfg->insert_tag2_en ? 1 : 0); 4766 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 4767 4768 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 4769 req->vf_bitmap[req->vf_offset] = 4770 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 4771 4772 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4773 if (status) 4774 dev_err(&hdev->pdev->dev, 4775 "Send port txvlan cfg command fail, ret =%d\n", 4776 status); 4777 4778 return status; 4779 } 4780 4781 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 4782 { 4783 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 4784 struct hclge_vport_vtag_rx_cfg_cmd *req; 4785 struct hclge_dev *hdev = vport->back; 4786 struct hclge_desc desc; 4787 int status; 4788 4789 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 4790 4791 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 4792 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 4793 vcfg->strip_tag1_en ? 1 : 0); 4794 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 4795 vcfg->strip_tag2_en ? 1 : 0); 4796 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 4797 vcfg->vlan1_vlan_prionly ? 1 : 0); 4798 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 4799 vcfg->vlan2_vlan_prionly ? 1 : 0); 4800 4801 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 4802 req->vf_bitmap[req->vf_offset] = 4803 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 4804 4805 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4806 if (status) 4807 dev_err(&hdev->pdev->dev, 4808 "Send port rxvlan cfg command fail, ret =%d\n", 4809 status); 4810 4811 return status; 4812 } 4813 4814 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 4815 { 4816 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 4817 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 4818 struct hclge_desc desc; 4819 int status; 4820 4821 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 4822 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 4823 rx_req->ot_fst_vlan_type = 4824 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 4825 rx_req->ot_sec_vlan_type = 4826 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 4827 rx_req->in_fst_vlan_type = 4828 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 4829 rx_req->in_sec_vlan_type = 4830 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 4831 4832 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4833 if (status) { 4834 dev_err(&hdev->pdev->dev, 4835 "Send rxvlan protocol type command fail, ret =%d\n", 4836 status); 4837 return status; 4838 } 4839 4840 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 4841 4842 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data; 4843 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 4844 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 4845 4846 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4847 if (status) 4848 dev_err(&hdev->pdev->dev, 4849 "Send txvlan protocol type command fail, ret =%d\n", 4850 status); 4851 4852 return status; 4853 } 4854 4855 static int hclge_init_vlan_config(struct hclge_dev *hdev) 4856 { 4857 #define HCLGE_DEF_VLAN_TYPE 0x8100 4858 4859 struct hnae3_handle *handle; 4860 struct hclge_vport *vport; 4861 int ret; 4862 int i; 4863 4864 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true); 4865 if (ret) 4866 return ret; 4867 4868 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true); 4869 if (ret) 4870 return ret; 4871 4872 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE; 4873 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE; 4874 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE; 4875 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE; 4876 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE; 4877 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE; 4878 4879 ret = hclge_set_vlan_protocol_type(hdev); 4880 if (ret) 4881 return ret; 4882 4883 for (i = 0; i < hdev->num_alloc_vport; i++) { 4884 vport = &hdev->vport[i]; 4885 vport->txvlan_cfg.accept_tag1 = true; 4886 vport->txvlan_cfg.accept_untag1 = true; 4887 4888 /* accept_tag2 and accept_untag2 are not supported on 4889 * pdev revision(0x20), new revision support them. The 4890 * value of this two fields will not return error when driver 4891 * send command to fireware in revision(0x20). 4892 * This two fields can not configured by user. 4893 */ 4894 vport->txvlan_cfg.accept_tag2 = true; 4895 vport->txvlan_cfg.accept_untag2 = true; 4896 4897 vport->txvlan_cfg.insert_tag1_en = false; 4898 vport->txvlan_cfg.insert_tag2_en = false; 4899 vport->txvlan_cfg.default_tag1 = 0; 4900 vport->txvlan_cfg.default_tag2 = 0; 4901 4902 ret = hclge_set_vlan_tx_offload_cfg(vport); 4903 if (ret) 4904 return ret; 4905 4906 vport->rxvlan_cfg.strip_tag1_en = false; 4907 vport->rxvlan_cfg.strip_tag2_en = true; 4908 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 4909 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 4910 4911 ret = hclge_set_vlan_rx_offload_cfg(vport); 4912 if (ret) 4913 return ret; 4914 } 4915 4916 handle = &hdev->vport[0].nic; 4917 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 4918 } 4919 4920 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 4921 { 4922 struct hclge_vport *vport = hclge_get_vport(handle); 4923 4924 vport->rxvlan_cfg.strip_tag1_en = false; 4925 vport->rxvlan_cfg.strip_tag2_en = enable; 4926 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 4927 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 4928 4929 return hclge_set_vlan_rx_offload_cfg(vport); 4930 } 4931 4932 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu) 4933 { 4934 struct hclge_config_max_frm_size_cmd *req; 4935 struct hclge_desc desc; 4936 int max_frm_size; 4937 int ret; 4938 4939 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 4940 4941 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 4942 max_frm_size > HCLGE_MAC_MAX_FRAME) 4943 return -EINVAL; 4944 4945 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 4946 4947 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 4948 4949 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 4950 req->max_frm_size = cpu_to_le16(max_frm_size); 4951 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 4952 4953 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4954 if (ret) 4955 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret); 4956 else 4957 hdev->mps = max_frm_size; 4958 4959 return ret; 4960 } 4961 4962 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 4963 { 4964 struct hclge_vport *vport = hclge_get_vport(handle); 4965 struct hclge_dev *hdev = vport->back; 4966 int ret; 4967 4968 ret = hclge_set_mac_mtu(hdev, new_mtu); 4969 if (ret) { 4970 dev_err(&hdev->pdev->dev, 4971 "Change mtu fail, ret =%d\n", ret); 4972 return ret; 4973 } 4974 4975 ret = hclge_buffer_alloc(hdev); 4976 if (ret) 4977 dev_err(&hdev->pdev->dev, 4978 "Allocate buffer fail, ret =%d\n", ret); 4979 4980 return ret; 4981 } 4982 4983 static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id, 4984 bool enable) 4985 { 4986 struct hclge_reset_tqp_queue_cmd *req; 4987 struct hclge_desc desc; 4988 int ret; 4989 4990 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 4991 4992 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 4993 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK); 4994 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable); 4995 4996 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4997 if (ret) { 4998 dev_err(&hdev->pdev->dev, 4999 "Send tqp reset cmd error, status =%d\n", ret); 5000 return ret; 5001 } 5002 5003 return 0; 5004 } 5005 5006 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id) 5007 { 5008 struct hclge_reset_tqp_queue_cmd *req; 5009 struct hclge_desc desc; 5010 int ret; 5011 5012 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 5013 5014 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 5015 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK); 5016 5017 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5018 if (ret) { 5019 dev_err(&hdev->pdev->dev, 5020 "Get reset status error, status =%d\n", ret); 5021 return ret; 5022 } 5023 5024 return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 5025 } 5026 5027 static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, 5028 u16 queue_id) 5029 { 5030 struct hnae3_queue *queue; 5031 struct hclge_tqp *tqp; 5032 5033 queue = handle->kinfo.tqp[queue_id]; 5034 tqp = container_of(queue, struct hclge_tqp, q); 5035 5036 return tqp->index; 5037 } 5038 5039 void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id) 5040 { 5041 struct hclge_vport *vport = hclge_get_vport(handle); 5042 struct hclge_dev *hdev = vport->back; 5043 int reset_try_times = 0; 5044 int reset_status; 5045 u16 queue_gid; 5046 int ret; 5047 5048 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 5049 return; 5050 5051 queue_gid = hclge_covert_handle_qid_global(handle, queue_id); 5052 5053 ret = hclge_tqp_enable(hdev, queue_id, 0, false); 5054 if (ret) { 5055 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret); 5056 return; 5057 } 5058 5059 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true); 5060 if (ret) { 5061 dev_warn(&hdev->pdev->dev, 5062 "Send reset tqp cmd fail, ret = %d\n", ret); 5063 return; 5064 } 5065 5066 reset_try_times = 0; 5067 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 5068 /* Wait for tqp hw reset */ 5069 msleep(20); 5070 reset_status = hclge_get_reset_status(hdev, queue_gid); 5071 if (reset_status) 5072 break; 5073 } 5074 5075 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 5076 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n"); 5077 return; 5078 } 5079 5080 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false); 5081 if (ret) { 5082 dev_warn(&hdev->pdev->dev, 5083 "Deassert the soft reset fail, ret = %d\n", ret); 5084 return; 5085 } 5086 } 5087 5088 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id) 5089 { 5090 struct hclge_dev *hdev = vport->back; 5091 int reset_try_times = 0; 5092 int reset_status; 5093 u16 queue_gid; 5094 int ret; 5095 5096 queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id); 5097 5098 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true); 5099 if (ret) { 5100 dev_warn(&hdev->pdev->dev, 5101 "Send reset tqp cmd fail, ret = %d\n", ret); 5102 return; 5103 } 5104 5105 reset_try_times = 0; 5106 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 5107 /* Wait for tqp hw reset */ 5108 msleep(20); 5109 reset_status = hclge_get_reset_status(hdev, queue_gid); 5110 if (reset_status) 5111 break; 5112 } 5113 5114 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 5115 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n"); 5116 return; 5117 } 5118 5119 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false); 5120 if (ret) 5121 dev_warn(&hdev->pdev->dev, 5122 "Deassert the soft reset fail, ret = %d\n", ret); 5123 } 5124 5125 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 5126 { 5127 struct hclge_vport *vport = hclge_get_vport(handle); 5128 struct hclge_dev *hdev = vport->back; 5129 5130 return hdev->fw_version; 5131 } 5132 5133 static void hclge_get_flowctrl_adv(struct hnae3_handle *handle, 5134 u32 *flowctrl_adv) 5135 { 5136 struct hclge_vport *vport = hclge_get_vport(handle); 5137 struct hclge_dev *hdev = vport->back; 5138 struct phy_device *phydev = hdev->hw.mac.phydev; 5139 5140 if (!phydev) 5141 return; 5142 5143 *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) | 5144 (phydev->advertising & ADVERTISED_Asym_Pause); 5145 } 5146 5147 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 5148 { 5149 struct phy_device *phydev = hdev->hw.mac.phydev; 5150 5151 if (!phydev) 5152 return; 5153 5154 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause); 5155 5156 if (rx_en) 5157 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; 5158 5159 if (tx_en) 5160 phydev->advertising ^= ADVERTISED_Asym_Pause; 5161 } 5162 5163 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 5164 { 5165 int ret; 5166 5167 if (rx_en && tx_en) 5168 hdev->fc_mode_last_time = HCLGE_FC_FULL; 5169 else if (rx_en && !tx_en) 5170 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 5171 else if (!rx_en && tx_en) 5172 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 5173 else 5174 hdev->fc_mode_last_time = HCLGE_FC_NONE; 5175 5176 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 5177 return 0; 5178 5179 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 5180 if (ret) { 5181 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n", 5182 ret); 5183 return ret; 5184 } 5185 5186 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 5187 5188 return 0; 5189 } 5190 5191 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 5192 { 5193 struct phy_device *phydev = hdev->hw.mac.phydev; 5194 u16 remote_advertising = 0; 5195 u16 local_advertising = 0; 5196 u32 rx_pause, tx_pause; 5197 u8 flowctl; 5198 5199 if (!phydev->link || !phydev->autoneg) 5200 return 0; 5201 5202 if (phydev->advertising & ADVERTISED_Pause) 5203 local_advertising = ADVERTISE_PAUSE_CAP; 5204 5205 if (phydev->advertising & ADVERTISED_Asym_Pause) 5206 local_advertising |= ADVERTISE_PAUSE_ASYM; 5207 5208 if (phydev->pause) 5209 remote_advertising = LPA_PAUSE_CAP; 5210 5211 if (phydev->asym_pause) 5212 remote_advertising |= LPA_PAUSE_ASYM; 5213 5214 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 5215 remote_advertising); 5216 tx_pause = flowctl & FLOW_CTRL_TX; 5217 rx_pause = flowctl & FLOW_CTRL_RX; 5218 5219 if (phydev->duplex == HCLGE_MAC_HALF) { 5220 tx_pause = 0; 5221 rx_pause = 0; 5222 } 5223 5224 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 5225 } 5226 5227 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 5228 u32 *rx_en, u32 *tx_en) 5229 { 5230 struct hclge_vport *vport = hclge_get_vport(handle); 5231 struct hclge_dev *hdev = vport->back; 5232 5233 *auto_neg = hclge_get_autoneg(handle); 5234 5235 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 5236 *rx_en = 0; 5237 *tx_en = 0; 5238 return; 5239 } 5240 5241 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 5242 *rx_en = 1; 5243 *tx_en = 0; 5244 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 5245 *tx_en = 1; 5246 *rx_en = 0; 5247 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 5248 *rx_en = 1; 5249 *tx_en = 1; 5250 } else { 5251 *rx_en = 0; 5252 *tx_en = 0; 5253 } 5254 } 5255 5256 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 5257 u32 rx_en, u32 tx_en) 5258 { 5259 struct hclge_vport *vport = hclge_get_vport(handle); 5260 struct hclge_dev *hdev = vport->back; 5261 struct phy_device *phydev = hdev->hw.mac.phydev; 5262 u32 fc_autoneg; 5263 5264 fc_autoneg = hclge_get_autoneg(handle); 5265 if (auto_neg != fc_autoneg) { 5266 dev_info(&hdev->pdev->dev, 5267 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 5268 return -EOPNOTSUPP; 5269 } 5270 5271 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 5272 dev_info(&hdev->pdev->dev, 5273 "Priority flow control enabled. Cannot set link flow control.\n"); 5274 return -EOPNOTSUPP; 5275 } 5276 5277 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 5278 5279 if (!fc_autoneg) 5280 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 5281 5282 /* Only support flow control negotiation for netdev with 5283 * phy attached for now. 5284 */ 5285 if (!phydev) 5286 return -EOPNOTSUPP; 5287 5288 return phy_start_aneg(phydev); 5289 } 5290 5291 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 5292 u8 *auto_neg, u32 *speed, u8 *duplex) 5293 { 5294 struct hclge_vport *vport = hclge_get_vport(handle); 5295 struct hclge_dev *hdev = vport->back; 5296 5297 if (speed) 5298 *speed = hdev->hw.mac.speed; 5299 if (duplex) 5300 *duplex = hdev->hw.mac.duplex; 5301 if (auto_neg) 5302 *auto_neg = hdev->hw.mac.autoneg; 5303 } 5304 5305 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type) 5306 { 5307 struct hclge_vport *vport = hclge_get_vport(handle); 5308 struct hclge_dev *hdev = vport->back; 5309 5310 if (media_type) 5311 *media_type = hdev->hw.mac.media_type; 5312 } 5313 5314 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 5315 u8 *tp_mdix_ctrl, u8 *tp_mdix) 5316 { 5317 struct hclge_vport *vport = hclge_get_vport(handle); 5318 struct hclge_dev *hdev = vport->back; 5319 struct phy_device *phydev = hdev->hw.mac.phydev; 5320 int mdix_ctrl, mdix, retval, is_resolved; 5321 5322 if (!phydev) { 5323 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 5324 *tp_mdix = ETH_TP_MDI_INVALID; 5325 return; 5326 } 5327 5328 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 5329 5330 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 5331 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 5332 HCLGE_PHY_MDIX_CTRL_S); 5333 5334 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 5335 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 5336 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 5337 5338 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 5339 5340 switch (mdix_ctrl) { 5341 case 0x0: 5342 *tp_mdix_ctrl = ETH_TP_MDI; 5343 break; 5344 case 0x1: 5345 *tp_mdix_ctrl = ETH_TP_MDI_X; 5346 break; 5347 case 0x3: 5348 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 5349 break; 5350 default: 5351 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 5352 break; 5353 } 5354 5355 if (!is_resolved) 5356 *tp_mdix = ETH_TP_MDI_INVALID; 5357 else if (mdix) 5358 *tp_mdix = ETH_TP_MDI_X; 5359 else 5360 *tp_mdix = ETH_TP_MDI; 5361 } 5362 5363 static int hclge_init_client_instance(struct hnae3_client *client, 5364 struct hnae3_ae_dev *ae_dev) 5365 { 5366 struct hclge_dev *hdev = ae_dev->priv; 5367 struct hclge_vport *vport; 5368 int i, ret; 5369 5370 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 5371 vport = &hdev->vport[i]; 5372 5373 switch (client->type) { 5374 case HNAE3_CLIENT_KNIC: 5375 5376 hdev->nic_client = client; 5377 vport->nic.client = client; 5378 ret = client->ops->init_instance(&vport->nic); 5379 if (ret) 5380 return ret; 5381 5382 if (hdev->roce_client && 5383 hnae3_dev_roce_supported(hdev)) { 5384 struct hnae3_client *rc = hdev->roce_client; 5385 5386 ret = hclge_init_roce_base_info(vport); 5387 if (ret) 5388 return ret; 5389 5390 ret = rc->ops->init_instance(&vport->roce); 5391 if (ret) 5392 return ret; 5393 } 5394 5395 break; 5396 case HNAE3_CLIENT_UNIC: 5397 hdev->nic_client = client; 5398 vport->nic.client = client; 5399 5400 ret = client->ops->init_instance(&vport->nic); 5401 if (ret) 5402 return ret; 5403 5404 break; 5405 case HNAE3_CLIENT_ROCE: 5406 if (hnae3_dev_roce_supported(hdev)) { 5407 hdev->roce_client = client; 5408 vport->roce.client = client; 5409 } 5410 5411 if (hdev->roce_client && hdev->nic_client) { 5412 ret = hclge_init_roce_base_info(vport); 5413 if (ret) 5414 return ret; 5415 5416 ret = client->ops->init_instance(&vport->roce); 5417 if (ret) 5418 return ret; 5419 } 5420 } 5421 } 5422 5423 return 0; 5424 } 5425 5426 static void hclge_uninit_client_instance(struct hnae3_client *client, 5427 struct hnae3_ae_dev *ae_dev) 5428 { 5429 struct hclge_dev *hdev = ae_dev->priv; 5430 struct hclge_vport *vport; 5431 int i; 5432 5433 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { 5434 vport = &hdev->vport[i]; 5435 if (hdev->roce_client) { 5436 hdev->roce_client->ops->uninit_instance(&vport->roce, 5437 0); 5438 hdev->roce_client = NULL; 5439 vport->roce.client = NULL; 5440 } 5441 if (client->type == HNAE3_CLIENT_ROCE) 5442 return; 5443 if (client->ops->uninit_instance) { 5444 client->ops->uninit_instance(&vport->nic, 0); 5445 hdev->nic_client = NULL; 5446 vport->nic.client = NULL; 5447 } 5448 } 5449 } 5450 5451 static int hclge_pci_init(struct hclge_dev *hdev) 5452 { 5453 struct pci_dev *pdev = hdev->pdev; 5454 struct hclge_hw *hw; 5455 int ret; 5456 5457 ret = pci_enable_device(pdev); 5458 if (ret) { 5459 dev_err(&pdev->dev, "failed to enable PCI device\n"); 5460 return ret; 5461 } 5462 5463 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 5464 if (ret) { 5465 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 5466 if (ret) { 5467 dev_err(&pdev->dev, 5468 "can't set consistent PCI DMA"); 5469 goto err_disable_device; 5470 } 5471 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 5472 } 5473 5474 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 5475 if (ret) { 5476 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 5477 goto err_disable_device; 5478 } 5479 5480 pci_set_master(pdev); 5481 hw = &hdev->hw; 5482 hw->io_base = pcim_iomap(pdev, 2, 0); 5483 if (!hw->io_base) { 5484 dev_err(&pdev->dev, "Can't map configuration register space\n"); 5485 ret = -ENOMEM; 5486 goto err_clr_master; 5487 } 5488 5489 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 5490 5491 return 0; 5492 err_clr_master: 5493 pci_clear_master(pdev); 5494 pci_release_regions(pdev); 5495 err_disable_device: 5496 pci_disable_device(pdev); 5497 5498 return ret; 5499 } 5500 5501 static void hclge_pci_uninit(struct hclge_dev *hdev) 5502 { 5503 struct pci_dev *pdev = hdev->pdev; 5504 5505 pcim_iounmap(pdev, hdev->hw.io_base); 5506 pci_free_irq_vectors(pdev); 5507 pci_clear_master(pdev); 5508 pci_release_mem_regions(pdev); 5509 pci_disable_device(pdev); 5510 } 5511 5512 static void hclge_state_init(struct hclge_dev *hdev) 5513 { 5514 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 5515 set_bit(HCLGE_STATE_DOWN, &hdev->state); 5516 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 5517 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 5518 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 5519 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 5520 } 5521 5522 static void hclge_state_uninit(struct hclge_dev *hdev) 5523 { 5524 set_bit(HCLGE_STATE_DOWN, &hdev->state); 5525 5526 if (hdev->service_timer.function) 5527 del_timer_sync(&hdev->service_timer); 5528 if (hdev->service_task.func) 5529 cancel_work_sync(&hdev->service_task); 5530 if (hdev->rst_service_task.func) 5531 cancel_work_sync(&hdev->rst_service_task); 5532 if (hdev->mbx_service_task.func) 5533 cancel_work_sync(&hdev->mbx_service_task); 5534 } 5535 5536 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 5537 { 5538 struct pci_dev *pdev = ae_dev->pdev; 5539 struct hclge_dev *hdev; 5540 int ret; 5541 5542 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 5543 if (!hdev) { 5544 ret = -ENOMEM; 5545 goto out; 5546 } 5547 5548 hdev->pdev = pdev; 5549 hdev->ae_dev = ae_dev; 5550 hdev->reset_type = HNAE3_NONE_RESET; 5551 ae_dev->priv = hdev; 5552 5553 ret = hclge_pci_init(hdev); 5554 if (ret) { 5555 dev_err(&pdev->dev, "PCI init failed\n"); 5556 goto out; 5557 } 5558 5559 /* Firmware command queue initialize */ 5560 ret = hclge_cmd_queue_init(hdev); 5561 if (ret) { 5562 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret); 5563 goto err_pci_uninit; 5564 } 5565 5566 /* Firmware command initialize */ 5567 ret = hclge_cmd_init(hdev); 5568 if (ret) 5569 goto err_cmd_uninit; 5570 5571 ret = hclge_get_cap(hdev); 5572 if (ret) { 5573 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n", 5574 ret); 5575 goto err_cmd_uninit; 5576 } 5577 5578 ret = hclge_configure(hdev); 5579 if (ret) { 5580 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 5581 goto err_cmd_uninit; 5582 } 5583 5584 ret = hclge_init_msi(hdev); 5585 if (ret) { 5586 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 5587 goto err_cmd_uninit; 5588 } 5589 5590 ret = hclge_misc_irq_init(hdev); 5591 if (ret) { 5592 dev_err(&pdev->dev, 5593 "Misc IRQ(vector0) init error, ret = %d.\n", 5594 ret); 5595 goto err_msi_uninit; 5596 } 5597 5598 ret = hclge_alloc_tqps(hdev); 5599 if (ret) { 5600 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 5601 goto err_msi_irq_uninit; 5602 } 5603 5604 ret = hclge_alloc_vport(hdev); 5605 if (ret) { 5606 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret); 5607 goto err_msi_irq_uninit; 5608 } 5609 5610 ret = hclge_map_tqp(hdev); 5611 if (ret) { 5612 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 5613 goto err_msi_irq_uninit; 5614 } 5615 5616 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { 5617 ret = hclge_mac_mdio_config(hdev); 5618 if (ret) { 5619 dev_err(&hdev->pdev->dev, 5620 "mdio config fail ret=%d\n", ret); 5621 goto err_msi_irq_uninit; 5622 } 5623 } 5624 5625 ret = hclge_mac_init(hdev); 5626 if (ret) { 5627 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 5628 goto err_mdiobus_unreg; 5629 } 5630 5631 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 5632 if (ret) { 5633 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 5634 goto err_mdiobus_unreg; 5635 } 5636 5637 ret = hclge_init_vlan_config(hdev); 5638 if (ret) { 5639 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 5640 goto err_mdiobus_unreg; 5641 } 5642 5643 ret = hclge_tm_schd_init(hdev); 5644 if (ret) { 5645 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 5646 goto err_mdiobus_unreg; 5647 } 5648 5649 hclge_rss_init_cfg(hdev); 5650 ret = hclge_rss_init_hw(hdev); 5651 if (ret) { 5652 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 5653 goto err_mdiobus_unreg; 5654 } 5655 5656 ret = init_mgr_tbl(hdev); 5657 if (ret) { 5658 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 5659 goto err_mdiobus_unreg; 5660 } 5661 5662 hclge_dcb_ops_set(hdev); 5663 5664 timer_setup(&hdev->service_timer, hclge_service_timer, 0); 5665 INIT_WORK(&hdev->service_task, hclge_service_task); 5666 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task); 5667 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task); 5668 5669 hclge_clear_all_event_cause(hdev); 5670 5671 /* Enable MISC vector(vector0) */ 5672 hclge_enable_vector(&hdev->misc_vector, true); 5673 5674 hclge_state_init(hdev); 5675 5676 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME); 5677 return 0; 5678 5679 err_mdiobus_unreg: 5680 if (hdev->hw.mac.phydev) 5681 mdiobus_unregister(hdev->hw.mac.mdio_bus); 5682 err_msi_irq_uninit: 5683 hclge_misc_irq_uninit(hdev); 5684 err_msi_uninit: 5685 pci_free_irq_vectors(pdev); 5686 err_cmd_uninit: 5687 hclge_destroy_cmd_queue(&hdev->hw); 5688 err_pci_uninit: 5689 pcim_iounmap(pdev, hdev->hw.io_base); 5690 pci_clear_master(pdev); 5691 pci_release_regions(pdev); 5692 pci_disable_device(pdev); 5693 out: 5694 return ret; 5695 } 5696 5697 static void hclge_stats_clear(struct hclge_dev *hdev) 5698 { 5699 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats)); 5700 } 5701 5702 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 5703 { 5704 struct hclge_dev *hdev = ae_dev->priv; 5705 struct pci_dev *pdev = ae_dev->pdev; 5706 int ret; 5707 5708 set_bit(HCLGE_STATE_DOWN, &hdev->state); 5709 5710 hclge_stats_clear(hdev); 5711 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 5712 5713 ret = hclge_cmd_init(hdev); 5714 if (ret) { 5715 dev_err(&pdev->dev, "Cmd queue init failed\n"); 5716 return ret; 5717 } 5718 5719 ret = hclge_get_cap(hdev); 5720 if (ret) { 5721 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n", 5722 ret); 5723 return ret; 5724 } 5725 5726 ret = hclge_configure(hdev); 5727 if (ret) { 5728 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 5729 return ret; 5730 } 5731 5732 ret = hclge_map_tqp(hdev); 5733 if (ret) { 5734 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 5735 return ret; 5736 } 5737 5738 ret = hclge_mac_init(hdev); 5739 if (ret) { 5740 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 5741 return ret; 5742 } 5743 5744 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 5745 if (ret) { 5746 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 5747 return ret; 5748 } 5749 5750 ret = hclge_init_vlan_config(hdev); 5751 if (ret) { 5752 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 5753 return ret; 5754 } 5755 5756 ret = hclge_tm_init_hw(hdev); 5757 if (ret) { 5758 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 5759 return ret; 5760 } 5761 5762 ret = hclge_rss_init_hw(hdev); 5763 if (ret) { 5764 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 5765 return ret; 5766 } 5767 5768 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 5769 HCLGE_DRIVER_NAME); 5770 5771 return 0; 5772 } 5773 5774 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 5775 { 5776 struct hclge_dev *hdev = ae_dev->priv; 5777 struct hclge_mac *mac = &hdev->hw.mac; 5778 5779 hclge_state_uninit(hdev); 5780 5781 if (mac->phydev) 5782 mdiobus_unregister(mac->mdio_bus); 5783 5784 /* Disable MISC vector(vector0) */ 5785 hclge_enable_vector(&hdev->misc_vector, false); 5786 synchronize_irq(hdev->misc_vector.vector_irq); 5787 5788 hclge_destroy_cmd_queue(&hdev->hw); 5789 hclge_misc_irq_uninit(hdev); 5790 hclge_pci_uninit(hdev); 5791 ae_dev->priv = NULL; 5792 } 5793 5794 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 5795 { 5796 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 5797 struct hclge_vport *vport = hclge_get_vport(handle); 5798 struct hclge_dev *hdev = vport->back; 5799 5800 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps); 5801 } 5802 5803 static void hclge_get_channels(struct hnae3_handle *handle, 5804 struct ethtool_channels *ch) 5805 { 5806 struct hclge_vport *vport = hclge_get_vport(handle); 5807 5808 ch->max_combined = hclge_get_max_channels(handle); 5809 ch->other_count = 1; 5810 ch->max_other = 1; 5811 ch->combined_count = vport->alloc_tqps; 5812 } 5813 5814 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 5815 u16 *free_tqps, u16 *max_rss_size) 5816 { 5817 struct hclge_vport *vport = hclge_get_vport(handle); 5818 struct hclge_dev *hdev = vport->back; 5819 u16 temp_tqps = 0; 5820 int i; 5821 5822 for (i = 0; i < hdev->num_tqps; i++) { 5823 if (!hdev->htqp[i].alloced) 5824 temp_tqps++; 5825 } 5826 *free_tqps = temp_tqps; 5827 *max_rss_size = hdev->rss_size_max; 5828 } 5829 5830 static void hclge_release_tqp(struct hclge_vport *vport) 5831 { 5832 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5833 struct hclge_dev *hdev = vport->back; 5834 int i; 5835 5836 for (i = 0; i < kinfo->num_tqps; i++) { 5837 struct hclge_tqp *tqp = 5838 container_of(kinfo->tqp[i], struct hclge_tqp, q); 5839 5840 tqp->q.handle = NULL; 5841 tqp->q.tqp_index = 0; 5842 tqp->alloced = false; 5843 } 5844 5845 devm_kfree(&hdev->pdev->dev, kinfo->tqp); 5846 kinfo->tqp = NULL; 5847 } 5848 5849 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num) 5850 { 5851 struct hclge_vport *vport = hclge_get_vport(handle); 5852 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5853 struct hclge_dev *hdev = vport->back; 5854 int cur_rss_size = kinfo->rss_size; 5855 int cur_tqps = kinfo->num_tqps; 5856 u16 tc_offset[HCLGE_MAX_TC_NUM]; 5857 u16 tc_valid[HCLGE_MAX_TC_NUM]; 5858 u16 tc_size[HCLGE_MAX_TC_NUM]; 5859 u16 roundup_size; 5860 u32 *rss_indir; 5861 int ret, i; 5862 5863 /* Free old tqps, and reallocate with new tqp number when nic setup */ 5864 hclge_release_tqp(vport); 5865 5866 ret = hclge_knic_setup(vport, new_tqps_num); 5867 if (ret) { 5868 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret); 5869 return ret; 5870 } 5871 5872 ret = hclge_map_tqp_to_vport(hdev, vport); 5873 if (ret) { 5874 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret); 5875 return ret; 5876 } 5877 5878 ret = hclge_tm_schd_init(hdev); 5879 if (ret) { 5880 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret); 5881 return ret; 5882 } 5883 5884 roundup_size = roundup_pow_of_two(kinfo->rss_size); 5885 roundup_size = ilog2(roundup_size); 5886 /* Set the RSS TC mode according to the new RSS size */ 5887 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 5888 tc_valid[i] = 0; 5889 5890 if (!(hdev->hw_tc_map & BIT(i))) 5891 continue; 5892 5893 tc_valid[i] = 1; 5894 tc_size[i] = roundup_size; 5895 tc_offset[i] = kinfo->rss_size * i; 5896 } 5897 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset); 5898 if (ret) 5899 return ret; 5900 5901 /* Reinitializes the rss indirect table according to the new RSS size */ 5902 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); 5903 if (!rss_indir) 5904 return -ENOMEM; 5905 5906 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) 5907 rss_indir[i] = i % kinfo->rss_size; 5908 5909 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 5910 if (ret) 5911 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 5912 ret); 5913 5914 kfree(rss_indir); 5915 5916 if (!ret) 5917 dev_info(&hdev->pdev->dev, 5918 "Channels changed, rss_size from %d to %d, tqps from %d to %d", 5919 cur_rss_size, kinfo->rss_size, 5920 cur_tqps, kinfo->rss_size * kinfo->num_tc); 5921 5922 return ret; 5923 } 5924 5925 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit, 5926 u32 *regs_num_64_bit) 5927 { 5928 struct hclge_desc desc; 5929 u32 total_num; 5930 int ret; 5931 5932 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true); 5933 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5934 if (ret) { 5935 dev_err(&hdev->pdev->dev, 5936 "Query register number cmd failed, ret = %d.\n", ret); 5937 return ret; 5938 } 5939 5940 *regs_num_32_bit = le32_to_cpu(desc.data[0]); 5941 *regs_num_64_bit = le32_to_cpu(desc.data[1]); 5942 5943 total_num = *regs_num_32_bit + *regs_num_64_bit; 5944 if (!total_num) 5945 return -EINVAL; 5946 5947 return 0; 5948 } 5949 5950 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num, 5951 void *data) 5952 { 5953 #define HCLGE_32_BIT_REG_RTN_DATANUM 8 5954 5955 struct hclge_desc *desc; 5956 u32 *reg_val = data; 5957 __le32 *desc_data; 5958 int cmd_num; 5959 int i, k, n; 5960 int ret; 5961 5962 if (regs_num == 0) 5963 return 0; 5964 5965 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM); 5966 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 5967 if (!desc) 5968 return -ENOMEM; 5969 5970 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true); 5971 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 5972 if (ret) { 5973 dev_err(&hdev->pdev->dev, 5974 "Query 32 bit register cmd failed, ret = %d.\n", ret); 5975 kfree(desc); 5976 return ret; 5977 } 5978 5979 for (i = 0; i < cmd_num; i++) { 5980 if (i == 0) { 5981 desc_data = (__le32 *)(&desc[i].data[0]); 5982 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2; 5983 } else { 5984 desc_data = (__le32 *)(&desc[i]); 5985 n = HCLGE_32_BIT_REG_RTN_DATANUM; 5986 } 5987 for (k = 0; k < n; k++) { 5988 *reg_val++ = le32_to_cpu(*desc_data++); 5989 5990 regs_num--; 5991 if (!regs_num) 5992 break; 5993 } 5994 } 5995 5996 kfree(desc); 5997 return 0; 5998 } 5999 6000 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num, 6001 void *data) 6002 { 6003 #define HCLGE_64_BIT_REG_RTN_DATANUM 4 6004 6005 struct hclge_desc *desc; 6006 u64 *reg_val = data; 6007 __le64 *desc_data; 6008 int cmd_num; 6009 int i, k, n; 6010 int ret; 6011 6012 if (regs_num == 0) 6013 return 0; 6014 6015 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM); 6016 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 6017 if (!desc) 6018 return -ENOMEM; 6019 6020 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true); 6021 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 6022 if (ret) { 6023 dev_err(&hdev->pdev->dev, 6024 "Query 64 bit register cmd failed, ret = %d.\n", ret); 6025 kfree(desc); 6026 return ret; 6027 } 6028 6029 for (i = 0; i < cmd_num; i++) { 6030 if (i == 0) { 6031 desc_data = (__le64 *)(&desc[i].data[0]); 6032 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1; 6033 } else { 6034 desc_data = (__le64 *)(&desc[i]); 6035 n = HCLGE_64_BIT_REG_RTN_DATANUM; 6036 } 6037 for (k = 0; k < n; k++) { 6038 *reg_val++ = le64_to_cpu(*desc_data++); 6039 6040 regs_num--; 6041 if (!regs_num) 6042 break; 6043 } 6044 } 6045 6046 kfree(desc); 6047 return 0; 6048 } 6049 6050 static int hclge_get_regs_len(struct hnae3_handle *handle) 6051 { 6052 struct hclge_vport *vport = hclge_get_vport(handle); 6053 struct hclge_dev *hdev = vport->back; 6054 u32 regs_num_32_bit, regs_num_64_bit; 6055 int ret; 6056 6057 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 6058 if (ret) { 6059 dev_err(&hdev->pdev->dev, 6060 "Get register number failed, ret = %d.\n", ret); 6061 return -EOPNOTSUPP; 6062 } 6063 6064 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64); 6065 } 6066 6067 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version, 6068 void *data) 6069 { 6070 struct hclge_vport *vport = hclge_get_vport(handle); 6071 struct hclge_dev *hdev = vport->back; 6072 u32 regs_num_32_bit, regs_num_64_bit; 6073 int ret; 6074 6075 *version = hdev->fw_version; 6076 6077 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 6078 if (ret) { 6079 dev_err(&hdev->pdev->dev, 6080 "Get register number failed, ret = %d.\n", ret); 6081 return; 6082 } 6083 6084 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data); 6085 if (ret) { 6086 dev_err(&hdev->pdev->dev, 6087 "Get 32 bit register failed, ret = %d.\n", ret); 6088 return; 6089 } 6090 6091 data = (u32 *)data + regs_num_32_bit; 6092 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, 6093 data); 6094 if (ret) 6095 dev_err(&hdev->pdev->dev, 6096 "Get 64 bit register failed, ret = %d.\n", ret); 6097 } 6098 6099 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 6100 { 6101 struct hclge_set_led_state_cmd *req; 6102 struct hclge_desc desc; 6103 int ret; 6104 6105 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 6106 6107 req = (struct hclge_set_led_state_cmd *)desc.data; 6108 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 6109 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 6110 6111 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 6112 if (ret) 6113 dev_err(&hdev->pdev->dev, 6114 "Send set led state cmd error, ret =%d\n", ret); 6115 6116 return ret; 6117 } 6118 6119 enum hclge_led_status { 6120 HCLGE_LED_OFF, 6121 HCLGE_LED_ON, 6122 HCLGE_LED_NO_CHANGE = 0xFF, 6123 }; 6124 6125 static int hclge_set_led_id(struct hnae3_handle *handle, 6126 enum ethtool_phys_id_state status) 6127 { 6128 struct hclge_vport *vport = hclge_get_vport(handle); 6129 struct hclge_dev *hdev = vport->back; 6130 6131 switch (status) { 6132 case ETHTOOL_ID_ACTIVE: 6133 return hclge_set_led_status(hdev, HCLGE_LED_ON); 6134 case ETHTOOL_ID_INACTIVE: 6135 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 6136 default: 6137 return -EINVAL; 6138 } 6139 } 6140 6141 static void hclge_get_link_mode(struct hnae3_handle *handle, 6142 unsigned long *supported, 6143 unsigned long *advertising) 6144 { 6145 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 6146 struct hclge_vport *vport = hclge_get_vport(handle); 6147 struct hclge_dev *hdev = vport->back; 6148 unsigned int idx = 0; 6149 6150 for (; idx < size; idx++) { 6151 supported[idx] = hdev->hw.mac.supported[idx]; 6152 advertising[idx] = hdev->hw.mac.advertising[idx]; 6153 } 6154 } 6155 6156 static void hclge_get_port_type(struct hnae3_handle *handle, 6157 u8 *port_type) 6158 { 6159 struct hclge_vport *vport = hclge_get_vport(handle); 6160 struct hclge_dev *hdev = vport->back; 6161 u8 media_type = hdev->hw.mac.media_type; 6162 6163 switch (media_type) { 6164 case HNAE3_MEDIA_TYPE_FIBER: 6165 *port_type = PORT_FIBRE; 6166 break; 6167 case HNAE3_MEDIA_TYPE_COPPER: 6168 *port_type = PORT_TP; 6169 break; 6170 case HNAE3_MEDIA_TYPE_UNKNOWN: 6171 default: 6172 *port_type = PORT_OTHER; 6173 break; 6174 } 6175 } 6176 6177 static const struct hnae3_ae_ops hclge_ops = { 6178 .init_ae_dev = hclge_init_ae_dev, 6179 .uninit_ae_dev = hclge_uninit_ae_dev, 6180 .init_client_instance = hclge_init_client_instance, 6181 .uninit_client_instance = hclge_uninit_client_instance, 6182 .map_ring_to_vector = hclge_map_ring_to_vector, 6183 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 6184 .get_vector = hclge_get_vector, 6185 .put_vector = hclge_put_vector, 6186 .set_promisc_mode = hclge_set_promisc_mode, 6187 .set_loopback = hclge_set_loopback, 6188 .start = hclge_ae_start, 6189 .stop = hclge_ae_stop, 6190 .get_status = hclge_get_status, 6191 .get_ksettings_an_result = hclge_get_ksettings_an_result, 6192 .update_speed_duplex_h = hclge_update_speed_duplex_h, 6193 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 6194 .get_media_type = hclge_get_media_type, 6195 .get_rss_key_size = hclge_get_rss_key_size, 6196 .get_rss_indir_size = hclge_get_rss_indir_size, 6197 .get_rss = hclge_get_rss, 6198 .set_rss = hclge_set_rss, 6199 .set_rss_tuple = hclge_set_rss_tuple, 6200 .get_rss_tuple = hclge_get_rss_tuple, 6201 .get_tc_size = hclge_get_tc_size, 6202 .get_mac_addr = hclge_get_mac_addr, 6203 .set_mac_addr = hclge_set_mac_addr, 6204 .add_uc_addr = hclge_add_uc_addr, 6205 .rm_uc_addr = hclge_rm_uc_addr, 6206 .add_mc_addr = hclge_add_mc_addr, 6207 .rm_mc_addr = hclge_rm_mc_addr, 6208 .update_mta_status = hclge_update_mta_status, 6209 .set_autoneg = hclge_set_autoneg, 6210 .get_autoneg = hclge_get_autoneg, 6211 .get_pauseparam = hclge_get_pauseparam, 6212 .set_pauseparam = hclge_set_pauseparam, 6213 .set_mtu = hclge_set_mtu, 6214 .reset_queue = hclge_reset_tqp, 6215 .get_stats = hclge_get_stats, 6216 .update_stats = hclge_update_stats, 6217 .get_strings = hclge_get_strings, 6218 .get_sset_count = hclge_get_sset_count, 6219 .get_fw_version = hclge_get_fw_version, 6220 .get_mdix_mode = hclge_get_mdix_mode, 6221 .enable_vlan_filter = hclge_enable_vlan_filter, 6222 .set_vlan_filter = hclge_set_vlan_filter, 6223 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 6224 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 6225 .reset_event = hclge_reset_event, 6226 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 6227 .set_channels = hclge_set_channels, 6228 .get_channels = hclge_get_channels, 6229 .get_flowctrl_adv = hclge_get_flowctrl_adv, 6230 .get_regs_len = hclge_get_regs_len, 6231 .get_regs = hclge_get_regs, 6232 .set_led_id = hclge_set_led_id, 6233 .get_link_mode = hclge_get_link_mode, 6234 .get_port_type = hclge_get_port_type, 6235 }; 6236 6237 static struct hnae3_ae_algo ae_algo = { 6238 .ops = &hclge_ops, 6239 .pdev_id_table = ae_algo_pci_tbl, 6240 }; 6241 6242 static int hclge_init(void) 6243 { 6244 pr_info("%s is initializing\n", HCLGE_NAME); 6245 6246 hnae3_register_ae_algo(&ae_algo); 6247 6248 return 0; 6249 } 6250 6251 static void hclge_exit(void) 6252 { 6253 hnae3_unregister_ae_algo(&ae_algo); 6254 } 6255 module_init(hclge_init); 6256 module_exit(hclge_exit); 6257 6258 MODULE_LICENSE("GPL"); 6259 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 6260 MODULE_DESCRIPTION("HCLGE Driver"); 6261 MODULE_VERSION(HCLGE_MOD_VERSION); 6262