1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/pci.h> 13 #include <linux/platform_device.h> 14 #include <linux/if_vlan.h> 15 #include <linux/crash_dump.h> 16 #include <net/ipv6.h> 17 #include <net/rtnetlink.h> 18 #include "hclge_cmd.h" 19 #include "hclge_dcb.h" 20 #include "hclge_main.h" 21 #include "hclge_mbx.h" 22 #include "hclge_mdio.h" 23 #include "hclge_tm.h" 24 #include "hclge_err.h" 25 #include "hnae3.h" 26 #include "hclge_devlink.h" 27 #include "hclge_comm_cmd.h" 28 29 #define HCLGE_NAME "hclge" 30 31 #define HCLGE_BUF_SIZE_UNIT 256U 32 #define HCLGE_BUF_MUL_BY 2 33 #define HCLGE_BUF_DIV_BY 2 34 #define NEED_RESERVE_TC_NUM 2 35 #define BUF_MAX_PERCENT 100 36 #define BUF_RESERVE_PERCENT 90 37 38 #define HCLGE_RESET_MAX_FAIL_CNT 5 39 #define HCLGE_RESET_SYNC_TIME 100 40 #define HCLGE_PF_RESET_SYNC_TIME 20 41 #define HCLGE_PF_RESET_SYNC_CNT 1500 42 43 /* Get DFX BD number offset */ 44 #define HCLGE_DFX_BIOS_BD_OFFSET 1 45 #define HCLGE_DFX_SSU_0_BD_OFFSET 2 46 #define HCLGE_DFX_SSU_1_BD_OFFSET 3 47 #define HCLGE_DFX_IGU_BD_OFFSET 4 48 #define HCLGE_DFX_RPU_0_BD_OFFSET 5 49 #define HCLGE_DFX_RPU_1_BD_OFFSET 6 50 #define HCLGE_DFX_NCSI_BD_OFFSET 7 51 #define HCLGE_DFX_RTC_BD_OFFSET 8 52 #define HCLGE_DFX_PPP_BD_OFFSET 9 53 #define HCLGE_DFX_RCB_BD_OFFSET 10 54 #define HCLGE_DFX_TQP_BD_OFFSET 11 55 #define HCLGE_DFX_SSU_2_BD_OFFSET 12 56 57 #define HCLGE_LINK_STATUS_MS 10 58 59 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps); 60 static int hclge_init_vlan_config(struct hclge_dev *hdev); 61 static void hclge_sync_vlan_filter(struct hclge_dev *hdev); 62 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 63 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle); 64 static void hclge_rfs_filter_expire(struct hclge_dev *hdev); 65 static int hclge_clear_arfs_rules(struct hclge_dev *hdev); 66 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 67 unsigned long *addr); 68 static int hclge_set_default_loopback(struct hclge_dev *hdev); 69 70 static void hclge_sync_mac_table(struct hclge_dev *hdev); 71 static void hclge_restore_hw_table(struct hclge_dev *hdev); 72 static void hclge_sync_promisc_mode(struct hclge_dev *hdev); 73 static void hclge_sync_fd_table(struct hclge_dev *hdev); 74 static void hclge_update_fec_stats(struct hclge_dev *hdev); 75 76 static struct hnae3_ae_algo ae_algo; 77 78 static struct workqueue_struct *hclge_wq; 79 80 static const struct pci_device_id ae_algo_pci_tbl[] = { 81 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 83 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 84 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 85 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 86 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 88 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 89 /* required last entry */ 90 {0, } 91 }; 92 93 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 94 95 static const u32 cmdq_reg_addr_list[] = {HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG, 96 HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG, 97 HCLGE_COMM_NIC_CSQ_DEPTH_REG, 98 HCLGE_COMM_NIC_CSQ_TAIL_REG, 99 HCLGE_COMM_NIC_CSQ_HEAD_REG, 100 HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG, 101 HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG, 102 HCLGE_COMM_NIC_CRQ_DEPTH_REG, 103 HCLGE_COMM_NIC_CRQ_TAIL_REG, 104 HCLGE_COMM_NIC_CRQ_HEAD_REG, 105 HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, 106 HCLGE_COMM_CMDQ_INTR_STS_REG, 107 HCLGE_COMM_CMDQ_INTR_EN_REG, 108 HCLGE_COMM_CMDQ_INTR_GEN_REG}; 109 110 static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE, 111 HCLGE_PF_OTHER_INT_REG, 112 HCLGE_MISC_RESET_STS_REG, 113 HCLGE_MISC_VECTOR_INT_STS, 114 HCLGE_GLOBAL_RESET_REG, 115 HCLGE_FUN_RST_ING, 116 HCLGE_GRO_EN_REG}; 117 118 static const u32 ring_reg_addr_list[] = {HCLGE_RING_RX_ADDR_L_REG, 119 HCLGE_RING_RX_ADDR_H_REG, 120 HCLGE_RING_RX_BD_NUM_REG, 121 HCLGE_RING_RX_BD_LENGTH_REG, 122 HCLGE_RING_RX_MERGE_EN_REG, 123 HCLGE_RING_RX_TAIL_REG, 124 HCLGE_RING_RX_HEAD_REG, 125 HCLGE_RING_RX_FBD_NUM_REG, 126 HCLGE_RING_RX_OFFSET_REG, 127 HCLGE_RING_RX_FBD_OFFSET_REG, 128 HCLGE_RING_RX_STASH_REG, 129 HCLGE_RING_RX_BD_ERR_REG, 130 HCLGE_RING_TX_ADDR_L_REG, 131 HCLGE_RING_TX_ADDR_H_REG, 132 HCLGE_RING_TX_BD_NUM_REG, 133 HCLGE_RING_TX_PRIORITY_REG, 134 HCLGE_RING_TX_TC_REG, 135 HCLGE_RING_TX_MERGE_EN_REG, 136 HCLGE_RING_TX_TAIL_REG, 137 HCLGE_RING_TX_HEAD_REG, 138 HCLGE_RING_TX_FBD_NUM_REG, 139 HCLGE_RING_TX_OFFSET_REG, 140 HCLGE_RING_TX_EBD_NUM_REG, 141 HCLGE_RING_TX_EBD_OFFSET_REG, 142 HCLGE_RING_TX_BD_ERR_REG, 143 HCLGE_RING_EN_REG}; 144 145 static const u32 tqp_intr_reg_addr_list[] = {HCLGE_TQP_INTR_CTRL_REG, 146 HCLGE_TQP_INTR_GL0_REG, 147 HCLGE_TQP_INTR_GL1_REG, 148 HCLGE_TQP_INTR_GL2_REG, 149 HCLGE_TQP_INTR_RL_REG}; 150 151 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 152 "External Loopback test", 153 "App Loopback test", 154 "Serdes serial Loopback test", 155 "Serdes parallel Loopback test", 156 "Phy Loopback test" 157 }; 158 159 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 160 {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 161 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 162 {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 163 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 164 {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 165 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)}, 166 {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 167 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)}, 168 {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 169 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)}, 170 {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 171 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)}, 172 {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 173 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)}, 174 {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 175 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 176 {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 177 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 178 {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 179 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 180 {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 181 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 182 {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 183 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 184 {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 185 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 186 {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 187 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 188 {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 189 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 190 {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 191 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)}, 192 {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 193 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)}, 194 {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 195 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)}, 196 {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 197 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)}, 198 {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 199 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)}, 200 {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 201 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)}, 202 {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 203 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)}, 204 {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 205 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)}, 206 {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 207 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)}, 208 {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 209 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 210 {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 211 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 212 {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 213 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 214 {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 215 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 216 {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 217 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 218 {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 219 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 220 {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 221 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 222 {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 223 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 224 {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 225 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)}, 226 {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)}, 228 {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)}, 230 {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 231 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)}, 232 {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)}, 234 {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 235 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)}, 236 {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 237 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)}, 238 {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 239 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)}, 240 {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 242 {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 244 {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 246 {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 247 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 248 {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 249 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 250 {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 251 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 252 {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 253 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 254 {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 255 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 256 {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 257 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 258 {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 259 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 260 {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 261 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 262 {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 264 {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 266 {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 268 {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 270 {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 272 {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 274 {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 276 {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 278 {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 280 {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 282 {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 284 {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 286 {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 288 {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 290 {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 291 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 292 {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 293 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 294 {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 295 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 296 {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 297 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 298 {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 300 {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 301 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 302 {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 303 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 304 {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 305 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 306 {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 307 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 308 {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 309 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 310 {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 312 {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 314 {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 316 {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 318 {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 320 {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 322 {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 324 {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 326 {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 328 {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 330 {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 332 {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 334 {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 336 {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 338 {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 340 341 {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 342 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 343 {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 344 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 345 {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 346 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 347 {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 348 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 349 {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 350 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 351 {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 352 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 353 {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 354 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 355 {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 356 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 357 {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 358 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 359 {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 360 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 361 {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 362 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 363 {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 364 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 365 }; 366 367 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 368 { 369 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 370 .ethter_type = cpu_to_le16(ETH_P_LLDP), 371 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e}, 372 .i_port_bitmap = 0x1, 373 }, 374 }; 375 376 static const u32 hclge_dfx_bd_offset_list[] = { 377 HCLGE_DFX_BIOS_BD_OFFSET, 378 HCLGE_DFX_SSU_0_BD_OFFSET, 379 HCLGE_DFX_SSU_1_BD_OFFSET, 380 HCLGE_DFX_IGU_BD_OFFSET, 381 HCLGE_DFX_RPU_0_BD_OFFSET, 382 HCLGE_DFX_RPU_1_BD_OFFSET, 383 HCLGE_DFX_NCSI_BD_OFFSET, 384 HCLGE_DFX_RTC_BD_OFFSET, 385 HCLGE_DFX_PPP_BD_OFFSET, 386 HCLGE_DFX_RCB_BD_OFFSET, 387 HCLGE_DFX_TQP_BD_OFFSET, 388 HCLGE_DFX_SSU_2_BD_OFFSET 389 }; 390 391 static const enum hclge_opcode_type hclge_dfx_reg_opcode_list[] = { 392 HCLGE_OPC_DFX_BIOS_COMMON_REG, 393 HCLGE_OPC_DFX_SSU_REG_0, 394 HCLGE_OPC_DFX_SSU_REG_1, 395 HCLGE_OPC_DFX_IGU_EGU_REG, 396 HCLGE_OPC_DFX_RPU_REG_0, 397 HCLGE_OPC_DFX_RPU_REG_1, 398 HCLGE_OPC_DFX_NCSI_REG, 399 HCLGE_OPC_DFX_RTC_REG, 400 HCLGE_OPC_DFX_PPP_REG, 401 HCLGE_OPC_DFX_RCB_REG, 402 HCLGE_OPC_DFX_TQP_REG, 403 HCLGE_OPC_DFX_SSU_REG_2 404 }; 405 406 static const struct key_info meta_data_key_info[] = { 407 { PACKET_TYPE_ID, 6 }, 408 { IP_FRAGEMENT, 1 }, 409 { ROCE_TYPE, 1 }, 410 { NEXT_KEY, 5 }, 411 { VLAN_NUMBER, 2 }, 412 { SRC_VPORT, 12 }, 413 { DST_VPORT, 12 }, 414 { TUNNEL_PACKET, 1 }, 415 }; 416 417 static const struct key_info tuple_key_info[] = { 418 { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 }, 419 { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 }, 420 { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 }, 421 { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 422 { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 }, 423 { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 }, 424 { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 }, 425 { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 }, 426 { OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 }, 427 { OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 }, 428 { OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 }, 429 { OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 }, 430 { OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 }, 431 { OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 }, 432 { OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 }, 433 { OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 }, 434 { INNER_DST_MAC, 48, KEY_OPT_MAC, 435 offsetof(struct hclge_fd_rule, tuples.dst_mac), 436 offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) }, 437 { INNER_SRC_MAC, 48, KEY_OPT_MAC, 438 offsetof(struct hclge_fd_rule, tuples.src_mac), 439 offsetof(struct hclge_fd_rule, tuples_mask.src_mac) }, 440 { INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16, 441 offsetof(struct hclge_fd_rule, tuples.vlan_tag1), 442 offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) }, 443 { INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 444 { INNER_ETH_TYPE, 16, KEY_OPT_LE16, 445 offsetof(struct hclge_fd_rule, tuples.ether_proto), 446 offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) }, 447 { INNER_L2_RSV, 16, KEY_OPT_LE16, 448 offsetof(struct hclge_fd_rule, tuples.l2_user_def), 449 offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) }, 450 { INNER_IP_TOS, 8, KEY_OPT_U8, 451 offsetof(struct hclge_fd_rule, tuples.ip_tos), 452 offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) }, 453 { INNER_IP_PROTO, 8, KEY_OPT_U8, 454 offsetof(struct hclge_fd_rule, tuples.ip_proto), 455 offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) }, 456 { INNER_SRC_IP, 32, KEY_OPT_IP, 457 offsetof(struct hclge_fd_rule, tuples.src_ip), 458 offsetof(struct hclge_fd_rule, tuples_mask.src_ip) }, 459 { INNER_DST_IP, 32, KEY_OPT_IP, 460 offsetof(struct hclge_fd_rule, tuples.dst_ip), 461 offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) }, 462 { INNER_L3_RSV, 16, KEY_OPT_LE16, 463 offsetof(struct hclge_fd_rule, tuples.l3_user_def), 464 offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) }, 465 { INNER_SRC_PORT, 16, KEY_OPT_LE16, 466 offsetof(struct hclge_fd_rule, tuples.src_port), 467 offsetof(struct hclge_fd_rule, tuples_mask.src_port) }, 468 { INNER_DST_PORT, 16, KEY_OPT_LE16, 469 offsetof(struct hclge_fd_rule, tuples.dst_port), 470 offsetof(struct hclge_fd_rule, tuples_mask.dst_port) }, 471 { INNER_L4_RSV, 32, KEY_OPT_LE32, 472 offsetof(struct hclge_fd_rule, tuples.l4_user_def), 473 offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) }, 474 }; 475 476 /** 477 * hclge_cmd_send - send command to command queue 478 * @hw: pointer to the hw struct 479 * @desc: prefilled descriptor for describing the command 480 * @num : the number of descriptors to be sent 481 * 482 * This is the main send command for command queue, it 483 * sends the queue, cleans the queue, etc 484 **/ 485 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 486 { 487 return hclge_comm_cmd_send(&hw->hw, desc, num); 488 } 489 490 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev) 491 { 492 #define HCLGE_MAC_CMD_NUM 21 493 494 u64 *data = (u64 *)(&hdev->mac_stats); 495 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 496 __le64 *desc_data; 497 u32 data_size; 498 int ret; 499 u32 i; 500 501 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 502 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 503 if (ret) { 504 dev_err(&hdev->pdev->dev, 505 "Get MAC pkt stats fail, status = %d.\n", ret); 506 507 return ret; 508 } 509 510 /* The first desc has a 64-bit header, so data size need to minus 1 */ 511 data_size = sizeof(desc) / (sizeof(u64)) - 1; 512 513 desc_data = (__le64 *)(&desc[0].data[0]); 514 for (i = 0; i < data_size; i++) { 515 /* data memory is continuous becase only the first desc has a 516 * header in this command 517 */ 518 *data += le64_to_cpu(*desc_data); 519 data++; 520 desc_data++; 521 } 522 523 return 0; 524 } 525 526 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev) 527 { 528 #define HCLGE_REG_NUM_PER_DESC 4 529 530 u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num; 531 u64 *data = (u64 *)(&hdev->mac_stats); 532 struct hclge_desc *desc; 533 __le64 *desc_data; 534 u32 data_size; 535 u32 desc_num; 536 int ret; 537 u32 i; 538 539 /* The first desc has a 64-bit header, so need to consider it */ 540 desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1; 541 542 /* This may be called inside atomic sections, 543 * so GFP_ATOMIC is more suitalbe here 544 */ 545 desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC); 546 if (!desc) 547 return -ENOMEM; 548 549 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true); 550 ret = hclge_cmd_send(&hdev->hw, desc, desc_num); 551 if (ret) { 552 kfree(desc); 553 return ret; 554 } 555 556 data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num); 557 558 desc_data = (__le64 *)(&desc[0].data[0]); 559 for (i = 0; i < data_size; i++) { 560 /* data memory is continuous becase only the first desc has a 561 * header in this command 562 */ 563 *data += le64_to_cpu(*desc_data); 564 data++; 565 desc_data++; 566 } 567 568 kfree(desc); 569 570 return 0; 571 } 572 573 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num) 574 { 575 struct hclge_desc desc; 576 int ret; 577 578 /* Driver needs total register number of both valid registers and 579 * reserved registers, but the old firmware only returns number 580 * of valid registers in device V2. To be compatible with these 581 * devices, driver uses a fixed value. 582 */ 583 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) { 584 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1; 585 return 0; 586 } 587 588 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true); 589 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 590 if (ret) { 591 dev_err(&hdev->pdev->dev, 592 "failed to query mac statistic reg number, ret = %d\n", 593 ret); 594 return ret; 595 } 596 597 *reg_num = le32_to_cpu(desc.data[0]); 598 if (*reg_num == 0) { 599 dev_err(&hdev->pdev->dev, 600 "mac statistic reg number is invalid!\n"); 601 return -ENODATA; 602 } 603 604 return 0; 605 } 606 607 int hclge_mac_update_stats(struct hclge_dev *hdev) 608 { 609 /* The firmware supports the new statistics acquisition method */ 610 if (hdev->ae_dev->dev_specs.mac_stats_num) 611 return hclge_mac_update_stats_complete(hdev); 612 else 613 return hclge_mac_update_stats_defective(hdev); 614 } 615 616 static int hclge_comm_get_count(struct hclge_dev *hdev, 617 const struct hclge_comm_stats_str strs[], 618 u32 size) 619 { 620 int count = 0; 621 u32 i; 622 623 for (i = 0; i < size; i++) 624 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num) 625 count++; 626 627 return count; 628 } 629 630 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, 631 const struct hclge_comm_stats_str strs[], 632 int size, u64 *data) 633 { 634 u64 *buf = data; 635 u32 i; 636 637 for (i = 0; i < size; i++) { 638 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 639 continue; 640 641 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset); 642 buf++; 643 } 644 645 return buf; 646 } 647 648 static u8 *hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, 649 const struct hclge_comm_stats_str strs[], 650 int size, u8 *data) 651 { 652 char *buff = (char *)data; 653 u32 i; 654 655 if (stringset != ETH_SS_STATS) 656 return buff; 657 658 for (i = 0; i < size; i++) { 659 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 660 continue; 661 662 snprintf(buff, ETH_GSTRING_LEN, "%s", strs[i].desc); 663 buff = buff + ETH_GSTRING_LEN; 664 } 665 666 return (u8 *)buff; 667 } 668 669 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 670 { 671 struct hnae3_handle *handle; 672 int status; 673 674 handle = &hdev->vport[0].nic; 675 if (handle->client) { 676 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 677 if (status) { 678 dev_err(&hdev->pdev->dev, 679 "Update TQPS stats fail, status = %d.\n", 680 status); 681 } 682 } 683 684 hclge_update_fec_stats(hdev); 685 686 status = hclge_mac_update_stats(hdev); 687 if (status) 688 dev_err(&hdev->pdev->dev, 689 "Update MAC stats fail, status = %d.\n", status); 690 } 691 692 static void hclge_update_stats(struct hnae3_handle *handle) 693 { 694 struct hclge_vport *vport = hclge_get_vport(handle); 695 struct hclge_dev *hdev = vport->back; 696 int status; 697 698 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 699 return; 700 701 status = hclge_mac_update_stats(hdev); 702 if (status) 703 dev_err(&hdev->pdev->dev, 704 "Update MAC stats fail, status = %d.\n", 705 status); 706 707 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 708 if (status) 709 dev_err(&hdev->pdev->dev, 710 "Update TQPS stats fail, status = %d.\n", 711 status); 712 713 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 714 } 715 716 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 717 { 718 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \ 719 HNAE3_SUPPORT_PHY_LOOPBACK | \ 720 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \ 721 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \ 722 HNAE3_SUPPORT_EXTERNAL_LOOPBACK) 723 724 struct hclge_vport *vport = hclge_get_vport(handle); 725 struct hclge_dev *hdev = vport->back; 726 int count = 0; 727 728 /* Loopback test support rules: 729 * mac: only GE mode support 730 * serdes: all mac mode will support include GE/XGE/LGE/CGE 731 * phy: only support when phy device exist on board 732 */ 733 if (stringset == ETH_SS_TEST) { 734 /* clear loopback bit flags at first */ 735 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 736 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 || 737 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 738 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 739 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 740 count += 1; 741 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; 742 } 743 744 count += 1; 745 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; 746 count += 1; 747 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; 748 count += 1; 749 handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK; 750 751 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv && 752 hdev->hw.mac.phydev->drv->set_loopback) || 753 hnae3_dev_phy_imp_supported(hdev)) { 754 count += 1; 755 handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK; 756 } 757 } else if (stringset == ETH_SS_STATS) { 758 count = hclge_comm_get_count(hdev, g_mac_stats_string, 759 ARRAY_SIZE(g_mac_stats_string)) + 760 hclge_comm_tqps_get_sset_count(handle); 761 } 762 763 return count; 764 } 765 766 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset, 767 u8 *data) 768 { 769 struct hclge_vport *vport = hclge_get_vport(handle); 770 struct hclge_dev *hdev = vport->back; 771 u8 *p = (char *)data; 772 int size; 773 774 if (stringset == ETH_SS_STATS) { 775 size = ARRAY_SIZE(g_mac_stats_string); 776 p = hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, 777 size, p); 778 p = hclge_comm_tqps_get_strings(handle, p); 779 } else if (stringset == ETH_SS_TEST) { 780 if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) { 781 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL], 782 ETH_GSTRING_LEN); 783 p += ETH_GSTRING_LEN; 784 } 785 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { 786 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_APP], 787 ETH_GSTRING_LEN); 788 p += ETH_GSTRING_LEN; 789 } 790 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { 791 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES], 792 ETH_GSTRING_LEN); 793 p += ETH_GSTRING_LEN; 794 } 795 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { 796 memcpy(p, 797 hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES], 798 ETH_GSTRING_LEN); 799 p += ETH_GSTRING_LEN; 800 } 801 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 802 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_PHY], 803 ETH_GSTRING_LEN); 804 p += ETH_GSTRING_LEN; 805 } 806 } 807 } 808 809 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 810 { 811 struct hclge_vport *vport = hclge_get_vport(handle); 812 struct hclge_dev *hdev = vport->back; 813 u64 *p; 814 815 p = hclge_comm_get_stats(hdev, g_mac_stats_string, 816 ARRAY_SIZE(g_mac_stats_string), data); 817 p = hclge_comm_tqps_get_stats(handle, p); 818 } 819 820 static void hclge_get_mac_stat(struct hnae3_handle *handle, 821 struct hns3_mac_stats *mac_stats) 822 { 823 struct hclge_vport *vport = hclge_get_vport(handle); 824 struct hclge_dev *hdev = vport->back; 825 826 hclge_update_stats(handle); 827 828 mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num; 829 mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num; 830 } 831 832 static int hclge_parse_func_status(struct hclge_dev *hdev, 833 struct hclge_func_status_cmd *status) 834 { 835 #define HCLGE_MAC_ID_MASK 0xF 836 837 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 838 return -EINVAL; 839 840 /* Set the pf to main pf */ 841 if (status->pf_state & HCLGE_PF_STATE_MAIN) 842 hdev->flag |= HCLGE_FLAG_MAIN; 843 else 844 hdev->flag &= ~HCLGE_FLAG_MAIN; 845 846 hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK; 847 return 0; 848 } 849 850 static int hclge_query_function_status(struct hclge_dev *hdev) 851 { 852 #define HCLGE_QUERY_MAX_CNT 5 853 854 struct hclge_func_status_cmd *req; 855 struct hclge_desc desc; 856 int timeout = 0; 857 int ret; 858 859 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 860 req = (struct hclge_func_status_cmd *)desc.data; 861 862 do { 863 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 864 if (ret) { 865 dev_err(&hdev->pdev->dev, 866 "query function status failed %d.\n", ret); 867 return ret; 868 } 869 870 /* Check pf reset is done */ 871 if (req->pf_state) 872 break; 873 usleep_range(1000, 2000); 874 } while (timeout++ < HCLGE_QUERY_MAX_CNT); 875 876 return hclge_parse_func_status(hdev, req); 877 } 878 879 static int hclge_query_pf_resource(struct hclge_dev *hdev) 880 { 881 struct hclge_pf_res_cmd *req; 882 struct hclge_desc desc; 883 int ret; 884 885 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 886 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 887 if (ret) { 888 dev_err(&hdev->pdev->dev, 889 "query pf resource failed %d.\n", ret); 890 return ret; 891 } 892 893 req = (struct hclge_pf_res_cmd *)desc.data; 894 hdev->num_tqps = le16_to_cpu(req->tqp_num) + 895 le16_to_cpu(req->ext_tqp_num); 896 hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 897 898 if (req->tx_buf_size) 899 hdev->tx_buf_size = 900 le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S; 901 else 902 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 903 904 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT); 905 906 if (req->dv_buf_size) 907 hdev->dv_buf_size = 908 le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S; 909 else 910 hdev->dv_buf_size = HCLGE_DEFAULT_DV; 911 912 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT); 913 914 hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic); 915 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) { 916 dev_err(&hdev->pdev->dev, 917 "only %u msi resources available, not enough for pf(min:2).\n", 918 hdev->num_nic_msi); 919 return -EINVAL; 920 } 921 922 if (hnae3_dev_roce_supported(hdev)) { 923 hdev->num_roce_msi = 924 le16_to_cpu(req->pf_intr_vector_number_roce); 925 926 /* PF should have NIC vectors and Roce vectors, 927 * NIC vectors are queued before Roce vectors. 928 */ 929 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi; 930 } else { 931 hdev->num_msi = hdev->num_nic_msi; 932 } 933 934 return 0; 935 } 936 937 static int hclge_parse_speed(u8 speed_cmd, u32 *speed) 938 { 939 switch (speed_cmd) { 940 case HCLGE_FW_MAC_SPEED_10M: 941 *speed = HCLGE_MAC_SPEED_10M; 942 break; 943 case HCLGE_FW_MAC_SPEED_100M: 944 *speed = HCLGE_MAC_SPEED_100M; 945 break; 946 case HCLGE_FW_MAC_SPEED_1G: 947 *speed = HCLGE_MAC_SPEED_1G; 948 break; 949 case HCLGE_FW_MAC_SPEED_10G: 950 *speed = HCLGE_MAC_SPEED_10G; 951 break; 952 case HCLGE_FW_MAC_SPEED_25G: 953 *speed = HCLGE_MAC_SPEED_25G; 954 break; 955 case HCLGE_FW_MAC_SPEED_40G: 956 *speed = HCLGE_MAC_SPEED_40G; 957 break; 958 case HCLGE_FW_MAC_SPEED_50G: 959 *speed = HCLGE_MAC_SPEED_50G; 960 break; 961 case HCLGE_FW_MAC_SPEED_100G: 962 *speed = HCLGE_MAC_SPEED_100G; 963 break; 964 case HCLGE_FW_MAC_SPEED_200G: 965 *speed = HCLGE_MAC_SPEED_200G; 966 break; 967 default: 968 return -EINVAL; 969 } 970 971 return 0; 972 } 973 974 static const struct hclge_speed_bit_map speed_bit_map[] = { 975 {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT}, 976 {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT}, 977 {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT}, 978 {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT}, 979 {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT}, 980 {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT}, 981 {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BIT}, 982 {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BIT}, 983 {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT}, 984 }; 985 986 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit) 987 { 988 u16 i; 989 990 for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) { 991 if (speed == speed_bit_map[i].speed) { 992 *speed_bit = speed_bit_map[i].speed_bit; 993 return 0; 994 } 995 } 996 997 return -EINVAL; 998 } 999 1000 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed) 1001 { 1002 struct hclge_vport *vport = hclge_get_vport(handle); 1003 struct hclge_dev *hdev = vport->back; 1004 u32 speed_ability = hdev->hw.mac.speed_ability; 1005 u32 speed_bit = 0; 1006 int ret; 1007 1008 ret = hclge_get_speed_bit(speed, &speed_bit); 1009 if (ret) 1010 return ret; 1011 1012 if (speed_bit & speed_ability) 1013 return 0; 1014 1015 return -EINVAL; 1016 } 1017 1018 static void hclge_update_fec_support(struct hclge_mac *mac) 1019 { 1020 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported); 1021 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported); 1022 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported); 1023 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1024 1025 if (mac->fec_ability & BIT(HNAE3_FEC_BASER)) 1026 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1027 mac->supported); 1028 if (mac->fec_ability & BIT(HNAE3_FEC_RS)) 1029 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1030 mac->supported); 1031 if (mac->fec_ability & BIT(HNAE3_FEC_LLRS)) 1032 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1033 mac->supported); 1034 if (mac->fec_ability & BIT(HNAE3_FEC_NONE)) 1035 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1036 mac->supported); 1037 } 1038 1039 static void hclge_convert_setting_sr(u16 speed_ability, 1040 unsigned long *link_mode) 1041 { 1042 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1043 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1044 link_mode); 1045 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1046 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1047 link_mode); 1048 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1049 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 1050 link_mode); 1051 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1052 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 1053 link_mode); 1054 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1055 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 1056 link_mode); 1057 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1058 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 1059 link_mode); 1060 } 1061 1062 static void hclge_convert_setting_lr(u16 speed_ability, 1063 unsigned long *link_mode) 1064 { 1065 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1066 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 1067 link_mode); 1068 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1069 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1070 link_mode); 1071 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1072 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 1073 link_mode); 1074 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1075 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 1076 link_mode); 1077 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1078 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 1079 link_mode); 1080 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1081 linkmode_set_bit( 1082 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 1083 link_mode); 1084 } 1085 1086 static void hclge_convert_setting_cr(u16 speed_ability, 1087 unsigned long *link_mode) 1088 { 1089 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1090 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 1091 link_mode); 1092 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1093 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 1094 link_mode); 1095 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1096 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 1097 link_mode); 1098 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1099 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 1100 link_mode); 1101 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1102 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 1103 link_mode); 1104 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1105 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 1106 link_mode); 1107 } 1108 1109 static void hclge_convert_setting_kr(u16 speed_ability, 1110 unsigned long *link_mode) 1111 { 1112 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1113 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1114 link_mode); 1115 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1116 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1117 link_mode); 1118 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1119 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 1120 link_mode); 1121 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1122 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 1123 link_mode); 1124 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1125 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 1126 link_mode); 1127 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1128 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 1129 link_mode); 1130 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1131 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 1132 link_mode); 1133 } 1134 1135 static void hclge_convert_setting_fec(struct hclge_mac *mac) 1136 { 1137 /* If firmware has reported fec_ability, don't need to convert by speed */ 1138 if (mac->fec_ability) 1139 goto out; 1140 1141 switch (mac->speed) { 1142 case HCLGE_MAC_SPEED_10G: 1143 case HCLGE_MAC_SPEED_40G: 1144 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) | 1145 BIT(HNAE3_FEC_NONE); 1146 break; 1147 case HCLGE_MAC_SPEED_25G: 1148 case HCLGE_MAC_SPEED_50G: 1149 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) | 1150 BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE); 1151 break; 1152 case HCLGE_MAC_SPEED_100G: 1153 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1154 BIT(HNAE3_FEC_NONE); 1155 break; 1156 case HCLGE_MAC_SPEED_200G: 1157 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1158 BIT(HNAE3_FEC_LLRS); 1159 break; 1160 default: 1161 mac->fec_ability = 0; 1162 break; 1163 } 1164 1165 out: 1166 hclge_update_fec_support(mac); 1167 } 1168 1169 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 1170 u16 speed_ability) 1171 { 1172 struct hclge_mac *mac = &hdev->hw.mac; 1173 1174 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1175 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1176 mac->supported); 1177 1178 hclge_convert_setting_sr(speed_ability, mac->supported); 1179 hclge_convert_setting_lr(speed_ability, mac->supported); 1180 hclge_convert_setting_cr(speed_ability, mac->supported); 1181 if (hnae3_dev_fec_supported(hdev)) 1182 hclge_convert_setting_fec(mac); 1183 1184 if (hnae3_dev_pause_supported(hdev)) 1185 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1186 1187 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported); 1188 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1189 } 1190 1191 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev, 1192 u16 speed_ability) 1193 { 1194 struct hclge_mac *mac = &hdev->hw.mac; 1195 1196 hclge_convert_setting_kr(speed_ability, mac->supported); 1197 if (hnae3_dev_fec_supported(hdev)) 1198 hclge_convert_setting_fec(mac); 1199 1200 if (hnae3_dev_pause_supported(hdev)) 1201 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1202 1203 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported); 1204 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1205 } 1206 1207 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev, 1208 u16 speed_ability) 1209 { 1210 unsigned long *supported = hdev->hw.mac.supported; 1211 1212 /* default to support all speed for GE port */ 1213 if (!speed_ability) 1214 speed_ability = HCLGE_SUPPORT_GE; 1215 1216 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1217 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1218 supported); 1219 1220 if (speed_ability & HCLGE_SUPPORT_100M_BIT) { 1221 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1222 supported); 1223 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1224 supported); 1225 } 1226 1227 if (speed_ability & HCLGE_SUPPORT_10M_BIT) { 1228 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported); 1229 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported); 1230 } 1231 1232 if (hnae3_dev_pause_supported(hdev)) { 1233 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1234 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 1235 } 1236 1237 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 1238 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 1239 } 1240 1241 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 1242 { 1243 u8 media_type = hdev->hw.mac.media_type; 1244 1245 if (media_type == HNAE3_MEDIA_TYPE_FIBER) 1246 hclge_parse_fiber_link_mode(hdev, speed_ability); 1247 else if (media_type == HNAE3_MEDIA_TYPE_COPPER) 1248 hclge_parse_copper_link_mode(hdev, speed_ability); 1249 else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE) 1250 hclge_parse_backplane_link_mode(hdev, speed_ability); 1251 } 1252 1253 static u32 hclge_get_max_speed(u16 speed_ability) 1254 { 1255 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1256 return HCLGE_MAC_SPEED_200G; 1257 1258 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1259 return HCLGE_MAC_SPEED_100G; 1260 1261 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1262 return HCLGE_MAC_SPEED_50G; 1263 1264 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1265 return HCLGE_MAC_SPEED_40G; 1266 1267 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1268 return HCLGE_MAC_SPEED_25G; 1269 1270 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1271 return HCLGE_MAC_SPEED_10G; 1272 1273 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1274 return HCLGE_MAC_SPEED_1G; 1275 1276 if (speed_ability & HCLGE_SUPPORT_100M_BIT) 1277 return HCLGE_MAC_SPEED_100M; 1278 1279 if (speed_ability & HCLGE_SUPPORT_10M_BIT) 1280 return HCLGE_MAC_SPEED_10M; 1281 1282 return HCLGE_MAC_SPEED_1G; 1283 } 1284 1285 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1286 { 1287 #define HCLGE_TX_SPARE_SIZE_UNIT 4096 1288 #define SPEED_ABILITY_EXT_SHIFT 8 1289 1290 struct hclge_cfg_param_cmd *req; 1291 u64 mac_addr_tmp_high; 1292 u16 speed_ability_ext; 1293 u64 mac_addr_tmp; 1294 unsigned int i; 1295 1296 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1297 1298 /* get the configuration */ 1299 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1300 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1301 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1302 HCLGE_CFG_TQP_DESC_N_M, 1303 HCLGE_CFG_TQP_DESC_N_S); 1304 1305 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1306 HCLGE_CFG_PHY_ADDR_M, 1307 HCLGE_CFG_PHY_ADDR_S); 1308 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1309 HCLGE_CFG_MEDIA_TP_M, 1310 HCLGE_CFG_MEDIA_TP_S); 1311 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1312 HCLGE_CFG_RX_BUF_LEN_M, 1313 HCLGE_CFG_RX_BUF_LEN_S); 1314 /* get mac_address */ 1315 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1316 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1317 HCLGE_CFG_MAC_ADDR_H_M, 1318 HCLGE_CFG_MAC_ADDR_H_S); 1319 1320 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1321 1322 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1323 HCLGE_CFG_DEFAULT_SPEED_M, 1324 HCLGE_CFG_DEFAULT_SPEED_S); 1325 cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1326 HCLGE_CFG_RSS_SIZE_M, 1327 HCLGE_CFG_RSS_SIZE_S); 1328 1329 for (i = 0; i < ETH_ALEN; i++) 1330 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1331 1332 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1333 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1334 1335 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1336 HCLGE_CFG_SPEED_ABILITY_M, 1337 HCLGE_CFG_SPEED_ABILITY_S); 1338 speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]), 1339 HCLGE_CFG_SPEED_ABILITY_EXT_M, 1340 HCLGE_CFG_SPEED_ABILITY_EXT_S); 1341 cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT; 1342 1343 cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]), 1344 HCLGE_CFG_VLAN_FLTR_CAP_M, 1345 HCLGE_CFG_VLAN_FLTR_CAP_S); 1346 1347 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]), 1348 HCLGE_CFG_UMV_TBL_SPACE_M, 1349 HCLGE_CFG_UMV_TBL_SPACE_S); 1350 1351 cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]), 1352 HCLGE_CFG_PF_RSS_SIZE_M, 1353 HCLGE_CFG_PF_RSS_SIZE_S); 1354 1355 /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a 1356 * power of 2, instead of reading out directly. This would 1357 * be more flexible for future changes and expansions. 1358 * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S, 1359 * it does not make sense if PF's field is 0. In this case, PF and VF 1360 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S. 1361 */ 1362 cfg->pf_rss_size_max = cfg->pf_rss_size_max ? 1363 1U << cfg->pf_rss_size_max : 1364 cfg->vf_rss_size_max; 1365 1366 /* The unit of the tx spare buffer size queried from configuration 1367 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is 1368 * needed here. 1369 */ 1370 cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]), 1371 HCLGE_CFG_TX_SPARE_BUF_SIZE_M, 1372 HCLGE_CFG_TX_SPARE_BUF_SIZE_S); 1373 cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT; 1374 } 1375 1376 /* hclge_get_cfg: query the static parameter from flash 1377 * @hdev: pointer to struct hclge_dev 1378 * @hcfg: the config structure to be getted 1379 */ 1380 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1381 { 1382 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1383 struct hclge_cfg_param_cmd *req; 1384 unsigned int i; 1385 int ret; 1386 1387 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1388 u32 offset = 0; 1389 1390 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1391 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1392 true); 1393 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1394 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1395 /* Len should be united by 4 bytes when send to hardware */ 1396 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1397 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1398 req->offset = cpu_to_le32(offset); 1399 } 1400 1401 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1402 if (ret) { 1403 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1404 return ret; 1405 } 1406 1407 hclge_parse_cfg(hcfg, desc); 1408 1409 return 0; 1410 } 1411 1412 static void hclge_set_default_dev_specs(struct hclge_dev *hdev) 1413 { 1414 #define HCLGE_MAX_NON_TSO_BD_NUM 8U 1415 1416 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1417 1418 ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1419 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1420 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1421 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE; 1422 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL; 1423 ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME; 1424 ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM; 1425 ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1426 } 1427 1428 static void hclge_parse_dev_specs(struct hclge_dev *hdev, 1429 struct hclge_desc *desc) 1430 { 1431 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1432 struct hclge_dev_specs_0_cmd *req0; 1433 struct hclge_dev_specs_1_cmd *req1; 1434 1435 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data; 1436 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data; 1437 1438 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 1439 ae_dev->dev_specs.rss_ind_tbl_size = 1440 le16_to_cpu(req0->rss_ind_tbl_size); 1441 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 1442 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 1443 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate); 1444 ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num); 1445 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 1446 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 1447 ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size); 1448 ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size); 1449 } 1450 1451 static void hclge_check_dev_specs(struct hclge_dev *hdev) 1452 { 1453 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 1454 1455 if (!dev_specs->max_non_tso_bd_num) 1456 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1457 if (!dev_specs->rss_ind_tbl_size) 1458 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1459 if (!dev_specs->rss_key_size) 1460 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1461 if (!dev_specs->max_tm_rate) 1462 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE; 1463 if (!dev_specs->max_qset_num) 1464 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM; 1465 if (!dev_specs->max_int_gl) 1466 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL; 1467 if (!dev_specs->max_frm_size) 1468 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME; 1469 if (!dev_specs->umv_size) 1470 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1471 } 1472 1473 static int hclge_query_mac_stats_num(struct hclge_dev *hdev) 1474 { 1475 u32 reg_num = 0; 1476 int ret; 1477 1478 ret = hclge_mac_query_reg_num(hdev, ®_num); 1479 if (ret && ret != -EOPNOTSUPP) 1480 return ret; 1481 1482 hdev->ae_dev->dev_specs.mac_stats_num = reg_num; 1483 return 0; 1484 } 1485 1486 static int hclge_query_dev_specs(struct hclge_dev *hdev) 1487 { 1488 struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM]; 1489 int ret; 1490 int i; 1491 1492 ret = hclge_query_mac_stats_num(hdev); 1493 if (ret) 1494 return ret; 1495 1496 /* set default specifications as devices lower than version V3 do not 1497 * support querying specifications from firmware. 1498 */ 1499 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 1500 hclge_set_default_dev_specs(hdev); 1501 return 0; 1502 } 1503 1504 for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1505 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, 1506 true); 1507 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 1508 } 1509 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 1510 1511 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM); 1512 if (ret) 1513 return ret; 1514 1515 hclge_parse_dev_specs(hdev, desc); 1516 hclge_check_dev_specs(hdev); 1517 1518 return 0; 1519 } 1520 1521 static int hclge_get_cap(struct hclge_dev *hdev) 1522 { 1523 int ret; 1524 1525 ret = hclge_query_function_status(hdev); 1526 if (ret) { 1527 dev_err(&hdev->pdev->dev, 1528 "query function status error %d.\n", ret); 1529 return ret; 1530 } 1531 1532 /* get pf resource */ 1533 return hclge_query_pf_resource(hdev); 1534 } 1535 1536 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev) 1537 { 1538 #define HCLGE_MIN_TX_DESC 64 1539 #define HCLGE_MIN_RX_DESC 64 1540 1541 if (!is_kdump_kernel()) 1542 return; 1543 1544 dev_info(&hdev->pdev->dev, 1545 "Running kdump kernel. Using minimal resources\n"); 1546 1547 /* minimal queue pairs equals to the number of vports */ 1548 hdev->num_tqps = hdev->num_req_vfs + 1; 1549 hdev->num_tx_desc = HCLGE_MIN_TX_DESC; 1550 hdev->num_rx_desc = HCLGE_MIN_RX_DESC; 1551 } 1552 1553 static void hclge_init_tc_config(struct hclge_dev *hdev) 1554 { 1555 unsigned int i; 1556 1557 if (hdev->tc_max > HNAE3_MAX_TC || 1558 hdev->tc_max < 1) { 1559 dev_warn(&hdev->pdev->dev, "TC num = %u.\n", 1560 hdev->tc_max); 1561 hdev->tc_max = 1; 1562 } 1563 1564 /* Dev does not support DCB */ 1565 if (!hnae3_dev_dcb_supported(hdev)) { 1566 hdev->tc_max = 1; 1567 hdev->pfc_max = 0; 1568 } else { 1569 hdev->pfc_max = hdev->tc_max; 1570 } 1571 1572 hdev->tm_info.num_tc = 1; 1573 1574 /* Currently not support uncontiuous tc */ 1575 for (i = 0; i < hdev->tm_info.num_tc; i++) 1576 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1577 1578 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1579 } 1580 1581 static int hclge_configure(struct hclge_dev *hdev) 1582 { 1583 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1584 struct hclge_cfg cfg; 1585 int ret; 1586 1587 ret = hclge_get_cfg(hdev, &cfg); 1588 if (ret) 1589 return ret; 1590 1591 hdev->base_tqp_pid = 0; 1592 hdev->vf_rss_size_max = cfg.vf_rss_size_max; 1593 hdev->pf_rss_size_max = cfg.pf_rss_size_max; 1594 hdev->rx_buf_len = cfg.rx_buf_len; 1595 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1596 hdev->hw.mac.media_type = cfg.media_type; 1597 hdev->hw.mac.phy_addr = cfg.phy_addr; 1598 hdev->num_tx_desc = cfg.tqp_desc_num; 1599 hdev->num_rx_desc = cfg.tqp_desc_num; 1600 hdev->tm_info.num_pg = 1; 1601 hdev->tc_max = cfg.tc_num; 1602 hdev->tm_info.hw_pfc_map = 0; 1603 if (cfg.umv_space) 1604 hdev->wanted_umv_size = cfg.umv_space; 1605 else 1606 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size; 1607 hdev->tx_spare_buf_size = cfg.tx_spare_buf_size; 1608 hdev->gro_en = true; 1609 if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF) 1610 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 1611 1612 if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 1613 hdev->fd_en = true; 1614 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 1615 } 1616 1617 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1618 if (ret) { 1619 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n", 1620 cfg.default_speed, ret); 1621 return ret; 1622 } 1623 1624 hclge_parse_link_mode(hdev, cfg.speed_ability); 1625 1626 hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability); 1627 1628 hclge_init_tc_config(hdev); 1629 hclge_init_kdump_kernel_config(hdev); 1630 1631 return ret; 1632 } 1633 1634 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min, 1635 u16 tso_mss_max) 1636 { 1637 struct hclge_cfg_tso_status_cmd *req; 1638 struct hclge_desc desc; 1639 1640 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1641 1642 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1643 req->tso_mss_min = cpu_to_le16(tso_mss_min); 1644 req->tso_mss_max = cpu_to_le16(tso_mss_max); 1645 1646 return hclge_cmd_send(&hdev->hw, &desc, 1); 1647 } 1648 1649 static int hclge_config_gro(struct hclge_dev *hdev) 1650 { 1651 struct hclge_cfg_gro_status_cmd *req; 1652 struct hclge_desc desc; 1653 int ret; 1654 1655 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 1656 return 0; 1657 1658 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false); 1659 req = (struct hclge_cfg_gro_status_cmd *)desc.data; 1660 1661 req->gro_en = hdev->gro_en ? 1 : 0; 1662 1663 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1664 if (ret) 1665 dev_err(&hdev->pdev->dev, 1666 "GRO hardware config cmd failed, ret = %d\n", ret); 1667 1668 return ret; 1669 } 1670 1671 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1672 { 1673 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1674 struct hclge_comm_tqp *tqp; 1675 int i; 1676 1677 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1678 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 1679 if (!hdev->htqp) 1680 return -ENOMEM; 1681 1682 tqp = hdev->htqp; 1683 1684 for (i = 0; i < hdev->num_tqps; i++) { 1685 tqp->dev = &hdev->pdev->dev; 1686 tqp->index = i; 1687 1688 tqp->q.ae_algo = &ae_algo; 1689 tqp->q.buf_size = hdev->rx_buf_len; 1690 tqp->q.tx_desc_num = hdev->num_tx_desc; 1691 tqp->q.rx_desc_num = hdev->num_rx_desc; 1692 1693 /* need an extended offset to configure queues >= 1694 * HCLGE_TQP_MAX_SIZE_DEV_V2 1695 */ 1696 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2) 1697 tqp->q.io_base = hdev->hw.hw.io_base + 1698 HCLGE_TQP_REG_OFFSET + 1699 i * HCLGE_TQP_REG_SIZE; 1700 else 1701 tqp->q.io_base = hdev->hw.hw.io_base + 1702 HCLGE_TQP_REG_OFFSET + 1703 HCLGE_TQP_EXT_REG_OFFSET + 1704 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) * 1705 HCLGE_TQP_REG_SIZE; 1706 1707 /* when device supports tx push and has device memory, 1708 * the queue can execute push mode or doorbell mode on 1709 * device memory. 1710 */ 1711 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 1712 tqp->q.mem_base = hdev->hw.hw.mem_base + 1713 HCLGE_TQP_MEM_OFFSET(hdev, i); 1714 1715 tqp++; 1716 } 1717 1718 return 0; 1719 } 1720 1721 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1722 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1723 { 1724 struct hclge_tqp_map_cmd *req; 1725 struct hclge_desc desc; 1726 int ret; 1727 1728 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1729 1730 req = (struct hclge_tqp_map_cmd *)desc.data; 1731 req->tqp_id = cpu_to_le16(tqp_pid); 1732 req->tqp_vf = func_id; 1733 req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B; 1734 if (!is_pf) 1735 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B; 1736 req->tqp_vid = cpu_to_le16(tqp_vid); 1737 1738 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1739 if (ret) 1740 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1741 1742 return ret; 1743 } 1744 1745 static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) 1746 { 1747 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1748 struct hclge_dev *hdev = vport->back; 1749 int i, alloced; 1750 1751 for (i = 0, alloced = 0; i < hdev->num_tqps && 1752 alloced < num_tqps; i++) { 1753 if (!hdev->htqp[i].alloced) { 1754 hdev->htqp[i].q.handle = &vport->nic; 1755 hdev->htqp[i].q.tqp_index = alloced; 1756 hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc; 1757 hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc; 1758 kinfo->tqp[alloced] = &hdev->htqp[i].q; 1759 hdev->htqp[i].alloced = true; 1760 alloced++; 1761 } 1762 } 1763 vport->alloc_tqps = alloced; 1764 kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max, 1765 vport->alloc_tqps / hdev->tm_info.num_tc); 1766 1767 /* ensure one to one mapping between irq and queue at default */ 1768 kinfo->rss_size = min_t(u16, kinfo->rss_size, 1769 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc); 1770 1771 return 0; 1772 } 1773 1774 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps, 1775 u16 num_tx_desc, u16 num_rx_desc) 1776 1777 { 1778 struct hnae3_handle *nic = &vport->nic; 1779 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1780 struct hclge_dev *hdev = vport->back; 1781 int ret; 1782 1783 kinfo->num_tx_desc = num_tx_desc; 1784 kinfo->num_rx_desc = num_rx_desc; 1785 1786 kinfo->rx_buf_len = hdev->rx_buf_len; 1787 kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size; 1788 1789 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps, 1790 sizeof(struct hnae3_queue *), GFP_KERNEL); 1791 if (!kinfo->tqp) 1792 return -ENOMEM; 1793 1794 ret = hclge_assign_tqp(vport, num_tqps); 1795 if (ret) 1796 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1797 1798 return ret; 1799 } 1800 1801 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1802 struct hclge_vport *vport) 1803 { 1804 struct hnae3_handle *nic = &vport->nic; 1805 struct hnae3_knic_private_info *kinfo; 1806 u16 i; 1807 1808 kinfo = &nic->kinfo; 1809 for (i = 0; i < vport->alloc_tqps; i++) { 1810 struct hclge_comm_tqp *q = 1811 container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); 1812 bool is_pf; 1813 int ret; 1814 1815 is_pf = !(vport->vport_id); 1816 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1817 i, is_pf); 1818 if (ret) 1819 return ret; 1820 } 1821 1822 return 0; 1823 } 1824 1825 static int hclge_map_tqp(struct hclge_dev *hdev) 1826 { 1827 struct hclge_vport *vport = hdev->vport; 1828 u16 i, num_vport; 1829 1830 num_vport = hdev->num_req_vfs + 1; 1831 for (i = 0; i < num_vport; i++) { 1832 int ret; 1833 1834 ret = hclge_map_tqp_to_vport(hdev, vport); 1835 if (ret) 1836 return ret; 1837 1838 vport++; 1839 } 1840 1841 return 0; 1842 } 1843 1844 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1845 { 1846 struct hnae3_handle *nic = &vport->nic; 1847 struct hclge_dev *hdev = vport->back; 1848 int ret; 1849 1850 nic->pdev = hdev->pdev; 1851 nic->ae_algo = &ae_algo; 1852 nic->numa_node_mask = hdev->numa_node_mask; 1853 nic->kinfo.io_base = hdev->hw.hw.io_base; 1854 1855 ret = hclge_knic_setup(vport, num_tqps, 1856 hdev->num_tx_desc, hdev->num_rx_desc); 1857 if (ret) 1858 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret); 1859 1860 return ret; 1861 } 1862 1863 static int hclge_alloc_vport(struct hclge_dev *hdev) 1864 { 1865 struct pci_dev *pdev = hdev->pdev; 1866 struct hclge_vport *vport; 1867 u32 tqp_main_vport; 1868 u32 tqp_per_vport; 1869 int num_vport, i; 1870 int ret; 1871 1872 /* We need to alloc a vport for main NIC of PF */ 1873 num_vport = hdev->num_req_vfs + 1; 1874 1875 if (hdev->num_tqps < num_vport) { 1876 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)", 1877 hdev->num_tqps, num_vport); 1878 return -EINVAL; 1879 } 1880 1881 /* Alloc the same number of TQPs for every vport */ 1882 tqp_per_vport = hdev->num_tqps / num_vport; 1883 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1884 1885 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1886 GFP_KERNEL); 1887 if (!vport) 1888 return -ENOMEM; 1889 1890 hdev->vport = vport; 1891 hdev->num_alloc_vport = num_vport; 1892 1893 if (IS_ENABLED(CONFIG_PCI_IOV)) 1894 hdev->num_alloc_vfs = hdev->num_req_vfs; 1895 1896 for (i = 0; i < num_vport; i++) { 1897 vport->back = hdev; 1898 vport->vport_id = i; 1899 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO; 1900 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 1901 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE; 1902 vport->port_base_vlan_cfg.tbl_sta = true; 1903 vport->rxvlan_cfg.rx_vlan_offload_en = true; 1904 vport->req_vlan_fltr_en = true; 1905 INIT_LIST_HEAD(&vport->vlan_list); 1906 INIT_LIST_HEAD(&vport->uc_mac_list); 1907 INIT_LIST_HEAD(&vport->mc_mac_list); 1908 spin_lock_init(&vport->mac_list_lock); 1909 1910 if (i == 0) 1911 ret = hclge_vport_setup(vport, tqp_main_vport); 1912 else 1913 ret = hclge_vport_setup(vport, tqp_per_vport); 1914 if (ret) { 1915 dev_err(&pdev->dev, 1916 "vport setup failed for vport %d, %d\n", 1917 i, ret); 1918 return ret; 1919 } 1920 1921 vport++; 1922 } 1923 1924 return 0; 1925 } 1926 1927 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1928 struct hclge_pkt_buf_alloc *buf_alloc) 1929 { 1930 /* TX buffer size is unit by 128 byte */ 1931 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1932 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1933 struct hclge_tx_buff_alloc_cmd *req; 1934 struct hclge_desc desc; 1935 int ret; 1936 u8 i; 1937 1938 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1939 1940 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1941 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1942 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1943 1944 req->tx_pkt_buff[i] = 1945 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1946 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1947 } 1948 1949 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1950 if (ret) 1951 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1952 ret); 1953 1954 return ret; 1955 } 1956 1957 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1958 struct hclge_pkt_buf_alloc *buf_alloc) 1959 { 1960 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1961 1962 if (ret) 1963 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1964 1965 return ret; 1966 } 1967 1968 static u32 hclge_get_tc_num(struct hclge_dev *hdev) 1969 { 1970 unsigned int i; 1971 u32 cnt = 0; 1972 1973 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1974 if (hdev->hw_tc_map & BIT(i)) 1975 cnt++; 1976 return cnt; 1977 } 1978 1979 /* Get the number of pfc enabled TCs, which have private buffer */ 1980 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1981 struct hclge_pkt_buf_alloc *buf_alloc) 1982 { 1983 struct hclge_priv_buf *priv; 1984 unsigned int i; 1985 int cnt = 0; 1986 1987 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1988 priv = &buf_alloc->priv_buf[i]; 1989 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1990 priv->enable) 1991 cnt++; 1992 } 1993 1994 return cnt; 1995 } 1996 1997 /* Get the number of pfc disabled TCs, which have private buffer */ 1998 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1999 struct hclge_pkt_buf_alloc *buf_alloc) 2000 { 2001 struct hclge_priv_buf *priv; 2002 unsigned int i; 2003 int cnt = 0; 2004 2005 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2006 priv = &buf_alloc->priv_buf[i]; 2007 if (hdev->hw_tc_map & BIT(i) && 2008 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 2009 priv->enable) 2010 cnt++; 2011 } 2012 2013 return cnt; 2014 } 2015 2016 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 2017 { 2018 struct hclge_priv_buf *priv; 2019 u32 rx_priv = 0; 2020 int i; 2021 2022 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2023 priv = &buf_alloc->priv_buf[i]; 2024 if (priv->enable) 2025 rx_priv += priv->buf_size; 2026 } 2027 return rx_priv; 2028 } 2029 2030 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 2031 { 2032 u32 i, total_tx_size = 0; 2033 2034 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 2035 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 2036 2037 return total_tx_size; 2038 } 2039 2040 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 2041 struct hclge_pkt_buf_alloc *buf_alloc, 2042 u32 rx_all) 2043 { 2044 u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 2045 u32 tc_num = hclge_get_tc_num(hdev); 2046 u32 shared_buf, aligned_mps; 2047 u32 rx_priv; 2048 int i; 2049 2050 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2051 2052 if (hnae3_dev_dcb_supported(hdev)) 2053 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps + 2054 hdev->dv_buf_size; 2055 else 2056 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF 2057 + hdev->dv_buf_size; 2058 2059 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 2060 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc), 2061 HCLGE_BUF_SIZE_UNIT); 2062 2063 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 2064 if (rx_all < rx_priv + shared_std) 2065 return false; 2066 2067 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT); 2068 buf_alloc->s_buf.buf_size = shared_buf; 2069 if (hnae3_dev_dcb_supported(hdev)) { 2070 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size; 2071 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 2072 - roundup(aligned_mps / HCLGE_BUF_DIV_BY, 2073 HCLGE_BUF_SIZE_UNIT); 2074 } else { 2075 buf_alloc->s_buf.self.high = aligned_mps + 2076 HCLGE_NON_DCB_ADDITIONAL_BUF; 2077 buf_alloc->s_buf.self.low = aligned_mps; 2078 } 2079 2080 if (hnae3_dev_dcb_supported(hdev)) { 2081 hi_thrd = shared_buf - hdev->dv_buf_size; 2082 2083 if (tc_num <= NEED_RESERVE_TC_NUM) 2084 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 2085 / BUF_MAX_PERCENT; 2086 2087 if (tc_num) 2088 hi_thrd = hi_thrd / tc_num; 2089 2090 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps); 2091 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT); 2092 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY; 2093 } else { 2094 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF; 2095 lo_thrd = aligned_mps; 2096 } 2097 2098 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2099 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 2100 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 2101 } 2102 2103 return true; 2104 } 2105 2106 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 2107 struct hclge_pkt_buf_alloc *buf_alloc) 2108 { 2109 u32 i, total_size; 2110 2111 total_size = hdev->pkt_buf_size; 2112 2113 /* alloc tx buffer for all enabled tc */ 2114 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2115 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2116 2117 if (hdev->hw_tc_map & BIT(i)) { 2118 if (total_size < hdev->tx_buf_size) 2119 return -ENOMEM; 2120 2121 priv->tx_buf_size = hdev->tx_buf_size; 2122 } else { 2123 priv->tx_buf_size = 0; 2124 } 2125 2126 total_size -= priv->tx_buf_size; 2127 } 2128 2129 return 0; 2130 } 2131 2132 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max, 2133 struct hclge_pkt_buf_alloc *buf_alloc) 2134 { 2135 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2136 u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2137 unsigned int i; 2138 2139 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2140 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2141 2142 priv->enable = 0; 2143 priv->wl.low = 0; 2144 priv->wl.high = 0; 2145 priv->buf_size = 0; 2146 2147 if (!(hdev->hw_tc_map & BIT(i))) 2148 continue; 2149 2150 priv->enable = 1; 2151 2152 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 2153 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT; 2154 priv->wl.high = roundup(priv->wl.low + aligned_mps, 2155 HCLGE_BUF_SIZE_UNIT); 2156 } else { 2157 priv->wl.low = 0; 2158 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) : 2159 aligned_mps; 2160 } 2161 2162 priv->buf_size = priv->wl.high + hdev->dv_buf_size; 2163 } 2164 2165 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2166 } 2167 2168 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev, 2169 struct hclge_pkt_buf_alloc *buf_alloc) 2170 { 2171 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2172 int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 2173 int i; 2174 2175 /* let the last to be cleared first */ 2176 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2177 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2178 unsigned int mask = BIT((unsigned int)i); 2179 2180 if (hdev->hw_tc_map & mask && 2181 !(hdev->tm_info.hw_pfc_map & mask)) { 2182 /* Clear the no pfc TC private buffer */ 2183 priv->wl.low = 0; 2184 priv->wl.high = 0; 2185 priv->buf_size = 0; 2186 priv->enable = 0; 2187 no_pfc_priv_num--; 2188 } 2189 2190 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2191 no_pfc_priv_num == 0) 2192 break; 2193 } 2194 2195 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2196 } 2197 2198 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev, 2199 struct hclge_pkt_buf_alloc *buf_alloc) 2200 { 2201 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2202 int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 2203 int i; 2204 2205 /* let the last to be cleared first */ 2206 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2207 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2208 unsigned int mask = BIT((unsigned int)i); 2209 2210 if (hdev->hw_tc_map & mask && 2211 hdev->tm_info.hw_pfc_map & mask) { 2212 /* Reduce the number of pfc TC with private buffer */ 2213 priv->wl.low = 0; 2214 priv->enable = 0; 2215 priv->wl.high = 0; 2216 priv->buf_size = 0; 2217 pfc_priv_num--; 2218 } 2219 2220 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2221 pfc_priv_num == 0) 2222 break; 2223 } 2224 2225 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2226 } 2227 2228 static int hclge_only_alloc_priv_buff(struct hclge_dev *hdev, 2229 struct hclge_pkt_buf_alloc *buf_alloc) 2230 { 2231 #define COMPENSATE_BUFFER 0x3C00 2232 #define COMPENSATE_HALF_MPS_NUM 5 2233 #define PRIV_WL_GAP 0x1800 2234 2235 u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2236 u32 tc_num = hclge_get_tc_num(hdev); 2237 u32 half_mps = hdev->mps >> 1; 2238 u32 min_rx_priv; 2239 unsigned int i; 2240 2241 if (tc_num) 2242 rx_priv = rx_priv / tc_num; 2243 2244 if (tc_num <= NEED_RESERVE_TC_NUM) 2245 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 2246 2247 min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER + 2248 COMPENSATE_HALF_MPS_NUM * half_mps; 2249 min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT); 2250 rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT); 2251 if (rx_priv < min_rx_priv) 2252 return false; 2253 2254 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2255 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2256 2257 priv->enable = 0; 2258 priv->wl.low = 0; 2259 priv->wl.high = 0; 2260 priv->buf_size = 0; 2261 2262 if (!(hdev->hw_tc_map & BIT(i))) 2263 continue; 2264 2265 priv->enable = 1; 2266 priv->buf_size = rx_priv; 2267 priv->wl.high = rx_priv - hdev->dv_buf_size; 2268 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 2269 } 2270 2271 buf_alloc->s_buf.buf_size = 0; 2272 2273 return true; 2274 } 2275 2276 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 2277 * @hdev: pointer to struct hclge_dev 2278 * @buf_alloc: pointer to buffer calculation data 2279 * @return: 0: calculate successful, negative: fail 2280 */ 2281 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 2282 struct hclge_pkt_buf_alloc *buf_alloc) 2283 { 2284 /* When DCB is not supported, rx private buffer is not allocated. */ 2285 if (!hnae3_dev_dcb_supported(hdev)) { 2286 u32 rx_all = hdev->pkt_buf_size; 2287 2288 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 2289 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 2290 return -ENOMEM; 2291 2292 return 0; 2293 } 2294 2295 if (hclge_only_alloc_priv_buff(hdev, buf_alloc)) 2296 return 0; 2297 2298 if (hclge_rx_buf_calc_all(hdev, true, buf_alloc)) 2299 return 0; 2300 2301 /* try to decrease the buffer size */ 2302 if (hclge_rx_buf_calc_all(hdev, false, buf_alloc)) 2303 return 0; 2304 2305 if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc)) 2306 return 0; 2307 2308 if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc)) 2309 return 0; 2310 2311 return -ENOMEM; 2312 } 2313 2314 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 2315 struct hclge_pkt_buf_alloc *buf_alloc) 2316 { 2317 struct hclge_rx_priv_buff_cmd *req; 2318 struct hclge_desc desc; 2319 int ret; 2320 int i; 2321 2322 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 2323 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 2324 2325 /* Alloc private buffer TCs */ 2326 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2327 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2328 2329 req->buf_num[i] = 2330 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 2331 req->buf_num[i] |= 2332 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 2333 } 2334 2335 req->shared_buf = 2336 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 2337 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 2338 2339 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2340 if (ret) 2341 dev_err(&hdev->pdev->dev, 2342 "rx private buffer alloc cmd failed %d\n", ret); 2343 2344 return ret; 2345 } 2346 2347 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 2348 struct hclge_pkt_buf_alloc *buf_alloc) 2349 { 2350 struct hclge_rx_priv_wl_buf *req; 2351 struct hclge_priv_buf *priv; 2352 struct hclge_desc desc[2]; 2353 int i, j; 2354 int ret; 2355 2356 for (i = 0; i < 2; i++) { 2357 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 2358 false); 2359 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 2360 2361 /* The first descriptor set the NEXT bit to 1 */ 2362 if (i == 0) 2363 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2364 else 2365 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2366 2367 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2368 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 2369 2370 priv = &buf_alloc->priv_buf[idx]; 2371 req->tc_wl[j].high = 2372 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 2373 req->tc_wl[j].high |= 2374 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2375 req->tc_wl[j].low = 2376 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 2377 req->tc_wl[j].low |= 2378 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2379 } 2380 } 2381 2382 /* Send 2 descriptor at one time */ 2383 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2384 if (ret) 2385 dev_err(&hdev->pdev->dev, 2386 "rx private waterline config cmd failed %d\n", 2387 ret); 2388 return ret; 2389 } 2390 2391 static int hclge_common_thrd_config(struct hclge_dev *hdev, 2392 struct hclge_pkt_buf_alloc *buf_alloc) 2393 { 2394 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 2395 struct hclge_rx_com_thrd *req; 2396 struct hclge_desc desc[2]; 2397 struct hclge_tc_thrd *tc; 2398 int i, j; 2399 int ret; 2400 2401 for (i = 0; i < 2; i++) { 2402 hclge_cmd_setup_basic_desc(&desc[i], 2403 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 2404 req = (struct hclge_rx_com_thrd *)&desc[i].data; 2405 2406 /* The first descriptor set the NEXT bit to 1 */ 2407 if (i == 0) 2408 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2409 else 2410 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2411 2412 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2413 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 2414 2415 req->com_thrd[j].high = 2416 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 2417 req->com_thrd[j].high |= 2418 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2419 req->com_thrd[j].low = 2420 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 2421 req->com_thrd[j].low |= 2422 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2423 } 2424 } 2425 2426 /* Send 2 descriptors at one time */ 2427 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2428 if (ret) 2429 dev_err(&hdev->pdev->dev, 2430 "common threshold config cmd failed %d\n", ret); 2431 return ret; 2432 } 2433 2434 static int hclge_common_wl_config(struct hclge_dev *hdev, 2435 struct hclge_pkt_buf_alloc *buf_alloc) 2436 { 2437 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 2438 struct hclge_rx_com_wl *req; 2439 struct hclge_desc desc; 2440 int ret; 2441 2442 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 2443 2444 req = (struct hclge_rx_com_wl *)desc.data; 2445 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 2446 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2447 2448 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 2449 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2450 2451 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2452 if (ret) 2453 dev_err(&hdev->pdev->dev, 2454 "common waterline config cmd failed %d\n", ret); 2455 2456 return ret; 2457 } 2458 2459 int hclge_buffer_alloc(struct hclge_dev *hdev) 2460 { 2461 struct hclge_pkt_buf_alloc *pkt_buf; 2462 int ret; 2463 2464 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 2465 if (!pkt_buf) 2466 return -ENOMEM; 2467 2468 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 2469 if (ret) { 2470 dev_err(&hdev->pdev->dev, 2471 "could not calc tx buffer size for all TCs %d\n", ret); 2472 goto out; 2473 } 2474 2475 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 2476 if (ret) { 2477 dev_err(&hdev->pdev->dev, 2478 "could not alloc tx buffers %d\n", ret); 2479 goto out; 2480 } 2481 2482 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 2483 if (ret) { 2484 dev_err(&hdev->pdev->dev, 2485 "could not calc rx priv buffer size for all TCs %d\n", 2486 ret); 2487 goto out; 2488 } 2489 2490 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 2491 if (ret) { 2492 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 2493 ret); 2494 goto out; 2495 } 2496 2497 if (hnae3_dev_dcb_supported(hdev)) { 2498 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2499 if (ret) { 2500 dev_err(&hdev->pdev->dev, 2501 "could not configure rx private waterline %d\n", 2502 ret); 2503 goto out; 2504 } 2505 2506 ret = hclge_common_thrd_config(hdev, pkt_buf); 2507 if (ret) { 2508 dev_err(&hdev->pdev->dev, 2509 "could not configure common threshold %d\n", 2510 ret); 2511 goto out; 2512 } 2513 } 2514 2515 ret = hclge_common_wl_config(hdev, pkt_buf); 2516 if (ret) 2517 dev_err(&hdev->pdev->dev, 2518 "could not configure common waterline %d\n", ret); 2519 2520 out: 2521 kfree(pkt_buf); 2522 return ret; 2523 } 2524 2525 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2526 { 2527 struct hnae3_handle *roce = &vport->roce; 2528 struct hnae3_handle *nic = &vport->nic; 2529 struct hclge_dev *hdev = vport->back; 2530 2531 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2532 2533 if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi) 2534 return -EINVAL; 2535 2536 roce->rinfo.base_vector = hdev->num_nic_msi; 2537 2538 roce->rinfo.netdev = nic->kinfo.netdev; 2539 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2540 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2541 2542 roce->pdev = nic->pdev; 2543 roce->ae_algo = nic->ae_algo; 2544 roce->numa_node_mask = nic->numa_node_mask; 2545 2546 return 0; 2547 } 2548 2549 static int hclge_init_msi(struct hclge_dev *hdev) 2550 { 2551 struct pci_dev *pdev = hdev->pdev; 2552 int vectors; 2553 int i; 2554 2555 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2556 hdev->num_msi, 2557 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2558 if (vectors < 0) { 2559 dev_err(&pdev->dev, 2560 "failed(%d) to allocate MSI/MSI-X vectors\n", 2561 vectors); 2562 return vectors; 2563 } 2564 if (vectors < hdev->num_msi) 2565 dev_warn(&hdev->pdev->dev, 2566 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2567 hdev->num_msi, vectors); 2568 2569 hdev->num_msi = vectors; 2570 hdev->num_msi_left = vectors; 2571 2572 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2573 sizeof(u16), GFP_KERNEL); 2574 if (!hdev->vector_status) { 2575 pci_free_irq_vectors(pdev); 2576 return -ENOMEM; 2577 } 2578 2579 for (i = 0; i < hdev->num_msi; i++) 2580 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2581 2582 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2583 sizeof(int), GFP_KERNEL); 2584 if (!hdev->vector_irq) { 2585 pci_free_irq_vectors(pdev); 2586 return -ENOMEM; 2587 } 2588 2589 return 0; 2590 } 2591 2592 static u8 hclge_check_speed_dup(u8 duplex, int speed) 2593 { 2594 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 2595 duplex = HCLGE_MAC_FULL; 2596 2597 return duplex; 2598 } 2599 2600 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = { 2601 {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M}, 2602 {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M}, 2603 {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G}, 2604 {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G}, 2605 {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G}, 2606 {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G}, 2607 {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G}, 2608 {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G}, 2609 {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G}, 2610 }; 2611 2612 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw) 2613 { 2614 u16 i; 2615 2616 for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) { 2617 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) { 2618 *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw; 2619 return 0; 2620 } 2621 } 2622 2623 return -EINVAL; 2624 } 2625 2626 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 2627 u8 duplex, u8 lane_num) 2628 { 2629 struct hclge_config_mac_speed_dup_cmd *req; 2630 struct hclge_desc desc; 2631 u32 speed_fw; 2632 int ret; 2633 2634 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2635 2636 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2637 2638 if (duplex) 2639 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1); 2640 2641 ret = hclge_convert_to_fw_speed(speed, &speed_fw); 2642 if (ret) { 2643 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2644 return ret; 2645 } 2646 2647 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S, 2648 speed_fw); 2649 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2650 1); 2651 req->lane_num = lane_num; 2652 2653 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2654 if (ret) { 2655 dev_err(&hdev->pdev->dev, 2656 "mac speed/duplex config cmd failed %d.\n", ret); 2657 return ret; 2658 } 2659 2660 return 0; 2661 } 2662 2663 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num) 2664 { 2665 struct hclge_mac *mac = &hdev->hw.mac; 2666 int ret; 2667 2668 duplex = hclge_check_speed_dup(duplex, speed); 2669 if (!mac->support_autoneg && mac->speed == speed && 2670 mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0)) 2671 return 0; 2672 2673 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num); 2674 if (ret) 2675 return ret; 2676 2677 hdev->hw.mac.speed = speed; 2678 hdev->hw.mac.duplex = duplex; 2679 if (!lane_num) 2680 hdev->hw.mac.lane_num = lane_num; 2681 2682 return 0; 2683 } 2684 2685 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2686 u8 duplex, u8 lane_num) 2687 { 2688 struct hclge_vport *vport = hclge_get_vport(handle); 2689 struct hclge_dev *hdev = vport->back; 2690 2691 return hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num); 2692 } 2693 2694 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2695 { 2696 struct hclge_config_auto_neg_cmd *req; 2697 struct hclge_desc desc; 2698 u32 flag = 0; 2699 int ret; 2700 2701 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2702 2703 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2704 if (enable) 2705 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U); 2706 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2707 2708 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2709 if (ret) 2710 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2711 ret); 2712 2713 return ret; 2714 } 2715 2716 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2717 { 2718 struct hclge_vport *vport = hclge_get_vport(handle); 2719 struct hclge_dev *hdev = vport->back; 2720 2721 if (!hdev->hw.mac.support_autoneg) { 2722 if (enable) { 2723 dev_err(&hdev->pdev->dev, 2724 "autoneg is not supported by current port\n"); 2725 return -EOPNOTSUPP; 2726 } else { 2727 return 0; 2728 } 2729 } 2730 2731 return hclge_set_autoneg_en(hdev, enable); 2732 } 2733 2734 static int hclge_get_autoneg(struct hnae3_handle *handle) 2735 { 2736 struct hclge_vport *vport = hclge_get_vport(handle); 2737 struct hclge_dev *hdev = vport->back; 2738 struct phy_device *phydev = hdev->hw.mac.phydev; 2739 2740 if (phydev) 2741 return phydev->autoneg; 2742 2743 return hdev->hw.mac.autoneg; 2744 } 2745 2746 static int hclge_restart_autoneg(struct hnae3_handle *handle) 2747 { 2748 struct hclge_vport *vport = hclge_get_vport(handle); 2749 struct hclge_dev *hdev = vport->back; 2750 int ret; 2751 2752 dev_dbg(&hdev->pdev->dev, "restart autoneg\n"); 2753 2754 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2755 if (ret) 2756 return ret; 2757 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2758 } 2759 2760 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt) 2761 { 2762 struct hclge_vport *vport = hclge_get_vport(handle); 2763 struct hclge_dev *hdev = vport->back; 2764 2765 if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) 2766 return hclge_set_autoneg_en(hdev, !halt); 2767 2768 return 0; 2769 } 2770 2771 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev, 2772 struct hclge_desc *desc, u32 desc_len) 2773 { 2774 u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2; 2775 u32 desc_index = 0; 2776 u32 data_index = 0; 2777 u32 i; 2778 2779 for (i = 0; i < lane_size; i++) { 2780 if (data_index >= HCLGE_DESC_DATA_LEN) { 2781 desc_index++; 2782 data_index = 0; 2783 } 2784 2785 if (desc_index >= desc_len) 2786 return; 2787 2788 hdev->fec_stats.per_lanes[i] += 2789 le32_to_cpu(desc[desc_index].data[data_index]); 2790 data_index++; 2791 } 2792 } 2793 2794 static void hclge_parse_fec_stats(struct hclge_dev *hdev, 2795 struct hclge_desc *desc, u32 desc_len) 2796 { 2797 struct hclge_query_fec_stats_cmd *req; 2798 2799 req = (struct hclge_query_fec_stats_cmd *)desc[0].data; 2800 2801 hdev->fec_stats.base_r_lane_num = req->base_r_lane_num; 2802 hdev->fec_stats.rs_corr_blocks += 2803 le32_to_cpu(req->rs_fec_corr_blocks); 2804 hdev->fec_stats.rs_uncorr_blocks += 2805 le32_to_cpu(req->rs_fec_uncorr_blocks); 2806 hdev->fec_stats.rs_error_blocks += 2807 le32_to_cpu(req->rs_fec_error_blocks); 2808 hdev->fec_stats.base_r_corr_blocks += 2809 le32_to_cpu(req->base_r_fec_corr_blocks); 2810 hdev->fec_stats.base_r_uncorr_blocks += 2811 le32_to_cpu(req->base_r_fec_uncorr_blocks); 2812 2813 hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1); 2814 } 2815 2816 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev) 2817 { 2818 struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM]; 2819 int ret; 2820 u32 i; 2821 2822 for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) { 2823 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS, 2824 true); 2825 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1)) 2826 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2827 } 2828 2829 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM); 2830 if (ret) 2831 return ret; 2832 2833 hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM); 2834 2835 return 0; 2836 } 2837 2838 static void hclge_update_fec_stats(struct hclge_dev *hdev) 2839 { 2840 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2841 int ret; 2842 2843 if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || 2844 test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state)) 2845 return; 2846 2847 ret = hclge_update_fec_stats_hw(hdev); 2848 if (ret) 2849 dev_err(&hdev->pdev->dev, 2850 "failed to update fec stats, ret = %d\n", ret); 2851 2852 clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state); 2853 } 2854 2855 static void hclge_get_fec_stats_total(struct hclge_dev *hdev, 2856 struct ethtool_fec_stats *fec_stats) 2857 { 2858 fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks; 2859 fec_stats->uncorrectable_blocks.total = 2860 hdev->fec_stats.rs_uncorr_blocks; 2861 } 2862 2863 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev, 2864 struct ethtool_fec_stats *fec_stats) 2865 { 2866 u32 i; 2867 2868 if (hdev->fec_stats.base_r_lane_num == 0 || 2869 hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) { 2870 dev_err(&hdev->pdev->dev, 2871 "fec stats lane number(%llu) is invalid\n", 2872 hdev->fec_stats.base_r_lane_num); 2873 return; 2874 } 2875 2876 for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) { 2877 fec_stats->corrected_blocks.lanes[i] = 2878 hdev->fec_stats.base_r_corr_per_lanes[i]; 2879 fec_stats->uncorrectable_blocks.lanes[i] = 2880 hdev->fec_stats.base_r_uncorr_per_lanes[i]; 2881 } 2882 } 2883 2884 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev, 2885 struct ethtool_fec_stats *fec_stats) 2886 { 2887 u32 fec_mode = hdev->hw.mac.fec_mode; 2888 2889 switch (fec_mode) { 2890 case BIT(HNAE3_FEC_RS): 2891 case BIT(HNAE3_FEC_LLRS): 2892 hclge_get_fec_stats_total(hdev, fec_stats); 2893 break; 2894 case BIT(HNAE3_FEC_BASER): 2895 hclge_get_fec_stats_lanes(hdev, fec_stats); 2896 break; 2897 default: 2898 dev_err(&hdev->pdev->dev, 2899 "fec stats is not supported by current fec mode(0x%x)\n", 2900 fec_mode); 2901 break; 2902 } 2903 } 2904 2905 static void hclge_get_fec_stats(struct hnae3_handle *handle, 2906 struct ethtool_fec_stats *fec_stats) 2907 { 2908 struct hclge_vport *vport = hclge_get_vport(handle); 2909 struct hclge_dev *hdev = vport->back; 2910 u32 fec_mode = hdev->hw.mac.fec_mode; 2911 2912 if (fec_mode == BIT(HNAE3_FEC_NONE) || 2913 fec_mode == BIT(HNAE3_FEC_AUTO) || 2914 fec_mode == BIT(HNAE3_FEC_USER_DEF)) 2915 return; 2916 2917 hclge_update_fec_stats(hdev); 2918 2919 hclge_comm_get_fec_stats(hdev, fec_stats); 2920 } 2921 2922 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode) 2923 { 2924 struct hclge_config_fec_cmd *req; 2925 struct hclge_desc desc; 2926 int ret; 2927 2928 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false); 2929 2930 req = (struct hclge_config_fec_cmd *)desc.data; 2931 if (fec_mode & BIT(HNAE3_FEC_AUTO)) 2932 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1); 2933 if (fec_mode & BIT(HNAE3_FEC_RS)) 2934 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2935 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS); 2936 if (fec_mode & BIT(HNAE3_FEC_LLRS)) 2937 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2938 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS); 2939 if (fec_mode & BIT(HNAE3_FEC_BASER)) 2940 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2941 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER); 2942 2943 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2944 if (ret) 2945 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret); 2946 2947 return ret; 2948 } 2949 2950 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode) 2951 { 2952 struct hclge_vport *vport = hclge_get_vport(handle); 2953 struct hclge_dev *hdev = vport->back; 2954 struct hclge_mac *mac = &hdev->hw.mac; 2955 int ret; 2956 2957 if (fec_mode && !(mac->fec_ability & fec_mode)) { 2958 dev_err(&hdev->pdev->dev, "unsupported fec mode\n"); 2959 return -EINVAL; 2960 } 2961 2962 ret = hclge_set_fec_hw(hdev, fec_mode); 2963 if (ret) 2964 return ret; 2965 2966 mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF); 2967 return 0; 2968 } 2969 2970 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability, 2971 u8 *fec_mode) 2972 { 2973 struct hclge_vport *vport = hclge_get_vport(handle); 2974 struct hclge_dev *hdev = vport->back; 2975 struct hclge_mac *mac = &hdev->hw.mac; 2976 2977 if (fec_ability) 2978 *fec_ability = mac->fec_ability; 2979 if (fec_mode) 2980 *fec_mode = mac->fec_mode; 2981 } 2982 2983 static int hclge_mac_init(struct hclge_dev *hdev) 2984 { 2985 struct hclge_mac *mac = &hdev->hw.mac; 2986 int ret; 2987 2988 hdev->support_sfp_query = true; 2989 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 2990 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed, 2991 hdev->hw.mac.duplex, hdev->hw.mac.lane_num); 2992 if (ret) 2993 return ret; 2994 2995 if (hdev->hw.mac.support_autoneg) { 2996 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg); 2997 if (ret) 2998 return ret; 2999 } 3000 3001 mac->link = 0; 3002 3003 if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { 3004 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode); 3005 if (ret) 3006 return ret; 3007 } 3008 3009 ret = hclge_set_mac_mtu(hdev, hdev->mps); 3010 if (ret) { 3011 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret); 3012 return ret; 3013 } 3014 3015 ret = hclge_set_default_loopback(hdev); 3016 if (ret) 3017 return ret; 3018 3019 ret = hclge_buffer_alloc(hdev); 3020 if (ret) 3021 dev_err(&hdev->pdev->dev, 3022 "allocate buffer fail, ret=%d\n", ret); 3023 3024 return ret; 3025 } 3026 3027 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 3028 { 3029 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3030 !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) { 3031 hdev->last_mbx_scheduled = jiffies; 3032 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3033 } 3034 } 3035 3036 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 3037 { 3038 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3039 test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) && 3040 !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) { 3041 hdev->last_rst_scheduled = jiffies; 3042 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3043 } 3044 } 3045 3046 static void hclge_errhand_task_schedule(struct hclge_dev *hdev) 3047 { 3048 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3049 !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 3050 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3051 } 3052 3053 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time) 3054 { 3055 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3056 !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 3057 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time); 3058 } 3059 3060 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status) 3061 { 3062 struct hclge_link_status_cmd *req; 3063 struct hclge_desc desc; 3064 int ret; 3065 3066 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 3067 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3068 if (ret) { 3069 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 3070 ret); 3071 return ret; 3072 } 3073 3074 req = (struct hclge_link_status_cmd *)desc.data; 3075 *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ? 3076 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 3077 3078 return 0; 3079 } 3080 3081 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status) 3082 { 3083 struct phy_device *phydev = hdev->hw.mac.phydev; 3084 3085 *link_status = HCLGE_LINK_STATUS_DOWN; 3086 3087 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) 3088 return 0; 3089 3090 if (phydev && (phydev->state != PHY_RUNNING || !phydev->link)) 3091 return 0; 3092 3093 return hclge_get_mac_link_status(hdev, link_status); 3094 } 3095 3096 static void hclge_push_link_status(struct hclge_dev *hdev) 3097 { 3098 struct hclge_vport *vport; 3099 int ret; 3100 u16 i; 3101 3102 for (i = 0; i < pci_num_vf(hdev->pdev); i++) { 3103 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 3104 3105 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) || 3106 vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO) 3107 continue; 3108 3109 ret = hclge_push_vf_link_status(vport); 3110 if (ret) { 3111 dev_err(&hdev->pdev->dev, 3112 "failed to push link status to vf%u, ret = %d\n", 3113 i, ret); 3114 } 3115 } 3116 } 3117 3118 static void hclge_update_link_status(struct hclge_dev *hdev) 3119 { 3120 struct hnae3_handle *rhandle = &hdev->vport[0].roce; 3121 struct hnae3_handle *handle = &hdev->vport[0].nic; 3122 struct hnae3_client *rclient = hdev->roce_client; 3123 struct hnae3_client *client = hdev->nic_client; 3124 int state; 3125 int ret; 3126 3127 if (!client) 3128 return; 3129 3130 if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state)) 3131 return; 3132 3133 ret = hclge_get_mac_phy_link(hdev, &state); 3134 if (ret) { 3135 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3136 return; 3137 } 3138 3139 if (state != hdev->hw.mac.link) { 3140 hdev->hw.mac.link = state; 3141 client->ops->link_status_change(handle, state); 3142 hclge_config_mac_tnl_int(hdev, state); 3143 if (rclient && rclient->ops->link_status_change) 3144 rclient->ops->link_status_change(rhandle, state); 3145 3146 hclge_push_link_status(hdev); 3147 } 3148 3149 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3150 } 3151 3152 static void hclge_update_speed_advertising(struct hclge_mac *mac) 3153 { 3154 u32 speed_ability; 3155 3156 if (hclge_get_speed_bit(mac->speed, &speed_ability)) 3157 return; 3158 3159 switch (mac->module_type) { 3160 case HNAE3_MODULE_TYPE_FIBRE_LR: 3161 hclge_convert_setting_lr(speed_ability, mac->advertising); 3162 break; 3163 case HNAE3_MODULE_TYPE_FIBRE_SR: 3164 case HNAE3_MODULE_TYPE_AOC: 3165 hclge_convert_setting_sr(speed_ability, mac->advertising); 3166 break; 3167 case HNAE3_MODULE_TYPE_CR: 3168 hclge_convert_setting_cr(speed_ability, mac->advertising); 3169 break; 3170 case HNAE3_MODULE_TYPE_KR: 3171 hclge_convert_setting_kr(speed_ability, mac->advertising); 3172 break; 3173 default: 3174 break; 3175 } 3176 } 3177 3178 static void hclge_update_fec_advertising(struct hclge_mac *mac) 3179 { 3180 if (mac->fec_mode & BIT(HNAE3_FEC_RS)) 3181 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 3182 mac->advertising); 3183 else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS)) 3184 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 3185 mac->advertising); 3186 else if (mac->fec_mode & BIT(HNAE3_FEC_BASER)) 3187 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 3188 mac->advertising); 3189 else 3190 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 3191 mac->advertising); 3192 } 3193 3194 static void hclge_update_pause_advertising(struct hclge_dev *hdev) 3195 { 3196 struct hclge_mac *mac = &hdev->hw.mac; 3197 bool rx_en, tx_en; 3198 3199 switch (hdev->fc_mode_last_time) { 3200 case HCLGE_FC_RX_PAUSE: 3201 rx_en = true; 3202 tx_en = false; 3203 break; 3204 case HCLGE_FC_TX_PAUSE: 3205 rx_en = false; 3206 tx_en = true; 3207 break; 3208 case HCLGE_FC_FULL: 3209 rx_en = true; 3210 tx_en = true; 3211 break; 3212 default: 3213 rx_en = false; 3214 tx_en = false; 3215 break; 3216 } 3217 3218 linkmode_set_pause(mac->advertising, tx_en, rx_en); 3219 } 3220 3221 static void hclge_update_advertising(struct hclge_dev *hdev) 3222 { 3223 struct hclge_mac *mac = &hdev->hw.mac; 3224 3225 linkmode_zero(mac->advertising); 3226 hclge_update_speed_advertising(mac); 3227 hclge_update_fec_advertising(mac); 3228 hclge_update_pause_advertising(hdev); 3229 } 3230 3231 static void hclge_update_port_capability(struct hclge_dev *hdev, 3232 struct hclge_mac *mac) 3233 { 3234 if (hnae3_dev_fec_supported(hdev)) 3235 hclge_convert_setting_fec(mac); 3236 3237 /* firmware can not identify back plane type, the media type 3238 * read from configuration can help deal it 3239 */ 3240 if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE && 3241 mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN) 3242 mac->module_type = HNAE3_MODULE_TYPE_KR; 3243 else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3244 mac->module_type = HNAE3_MODULE_TYPE_TP; 3245 3246 if (mac->support_autoneg) { 3247 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported); 3248 linkmode_copy(mac->advertising, mac->supported); 3249 } else { 3250 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3251 mac->supported); 3252 hclge_update_advertising(hdev); 3253 } 3254 } 3255 3256 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed) 3257 { 3258 struct hclge_sfp_info_cmd *resp; 3259 struct hclge_desc desc; 3260 int ret; 3261 3262 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3263 resp = (struct hclge_sfp_info_cmd *)desc.data; 3264 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3265 if (ret == -EOPNOTSUPP) { 3266 dev_warn(&hdev->pdev->dev, 3267 "IMP do not support get SFP speed %d\n", ret); 3268 return ret; 3269 } else if (ret) { 3270 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret); 3271 return ret; 3272 } 3273 3274 *speed = le32_to_cpu(resp->speed); 3275 3276 return 0; 3277 } 3278 3279 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac) 3280 { 3281 struct hclge_sfp_info_cmd *resp; 3282 struct hclge_desc desc; 3283 int ret; 3284 3285 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3286 resp = (struct hclge_sfp_info_cmd *)desc.data; 3287 3288 resp->query_type = QUERY_ACTIVE_SPEED; 3289 3290 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3291 if (ret == -EOPNOTSUPP) { 3292 dev_warn(&hdev->pdev->dev, 3293 "IMP does not support get SFP info %d\n", ret); 3294 return ret; 3295 } else if (ret) { 3296 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret); 3297 return ret; 3298 } 3299 3300 /* In some case, mac speed get from IMP may be 0, it shouldn't be 3301 * set to mac->speed. 3302 */ 3303 if (!le32_to_cpu(resp->speed)) 3304 return 0; 3305 3306 mac->speed = le32_to_cpu(resp->speed); 3307 /* if resp->speed_ability is 0, it means it's an old version 3308 * firmware, do not update these params 3309 */ 3310 if (resp->speed_ability) { 3311 mac->module_type = le32_to_cpu(resp->module_type); 3312 mac->speed_ability = le32_to_cpu(resp->speed_ability); 3313 mac->autoneg = resp->autoneg; 3314 mac->support_autoneg = resp->autoneg_ability; 3315 mac->speed_type = QUERY_ACTIVE_SPEED; 3316 mac->lane_num = resp->lane_num; 3317 if (!resp->active_fec) 3318 mac->fec_mode = 0; 3319 else 3320 mac->fec_mode = BIT(resp->active_fec); 3321 mac->fec_ability = resp->fec_ability; 3322 } else { 3323 mac->speed_type = QUERY_SFP_SPEED; 3324 } 3325 3326 return 0; 3327 } 3328 3329 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle, 3330 struct ethtool_link_ksettings *cmd) 3331 { 3332 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3333 struct hclge_vport *vport = hclge_get_vport(handle); 3334 struct hclge_phy_link_ksetting_0_cmd *req0; 3335 struct hclge_phy_link_ksetting_1_cmd *req1; 3336 u32 supported, advertising, lp_advertising; 3337 struct hclge_dev *hdev = vport->back; 3338 int ret; 3339 3340 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3341 true); 3342 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3343 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3344 true); 3345 3346 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3347 if (ret) { 3348 dev_err(&hdev->pdev->dev, 3349 "failed to get phy link ksetting, ret = %d.\n", ret); 3350 return ret; 3351 } 3352 3353 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3354 cmd->base.autoneg = req0->autoneg; 3355 cmd->base.speed = le32_to_cpu(req0->speed); 3356 cmd->base.duplex = req0->duplex; 3357 cmd->base.port = req0->port; 3358 cmd->base.transceiver = req0->transceiver; 3359 cmd->base.phy_address = req0->phy_address; 3360 cmd->base.eth_tp_mdix = req0->eth_tp_mdix; 3361 cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl; 3362 supported = le32_to_cpu(req0->supported); 3363 advertising = le32_to_cpu(req0->advertising); 3364 lp_advertising = le32_to_cpu(req0->lp_advertising); 3365 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3366 supported); 3367 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3368 advertising); 3369 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 3370 lp_advertising); 3371 3372 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3373 cmd->base.master_slave_cfg = req1->master_slave_cfg; 3374 cmd->base.master_slave_state = req1->master_slave_state; 3375 3376 return 0; 3377 } 3378 3379 static int 3380 hclge_set_phy_link_ksettings(struct hnae3_handle *handle, 3381 const struct ethtool_link_ksettings *cmd) 3382 { 3383 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3384 struct hclge_vport *vport = hclge_get_vport(handle); 3385 struct hclge_phy_link_ksetting_0_cmd *req0; 3386 struct hclge_phy_link_ksetting_1_cmd *req1; 3387 struct hclge_dev *hdev = vport->back; 3388 u32 advertising; 3389 int ret; 3390 3391 if (cmd->base.autoneg == AUTONEG_DISABLE && 3392 ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) || 3393 (cmd->base.duplex != DUPLEX_HALF && 3394 cmd->base.duplex != DUPLEX_FULL))) 3395 return -EINVAL; 3396 3397 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3398 false); 3399 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3400 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3401 false); 3402 3403 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3404 req0->autoneg = cmd->base.autoneg; 3405 req0->speed = cpu_to_le32(cmd->base.speed); 3406 req0->duplex = cmd->base.duplex; 3407 ethtool_convert_link_mode_to_legacy_u32(&advertising, 3408 cmd->link_modes.advertising); 3409 req0->advertising = cpu_to_le32(advertising); 3410 req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; 3411 3412 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3413 req1->master_slave_cfg = cmd->base.master_slave_cfg; 3414 3415 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3416 if (ret) { 3417 dev_err(&hdev->pdev->dev, 3418 "failed to set phy link ksettings, ret = %d.\n", ret); 3419 return ret; 3420 } 3421 3422 hdev->hw.mac.autoneg = cmd->base.autoneg; 3423 hdev->hw.mac.speed = cmd->base.speed; 3424 hdev->hw.mac.duplex = cmd->base.duplex; 3425 linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising); 3426 3427 return 0; 3428 } 3429 3430 static int hclge_update_tp_port_info(struct hclge_dev *hdev) 3431 { 3432 struct ethtool_link_ksettings cmd; 3433 int ret; 3434 3435 if (!hnae3_dev_phy_imp_supported(hdev)) 3436 return 0; 3437 3438 ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd); 3439 if (ret) 3440 return ret; 3441 3442 hdev->hw.mac.autoneg = cmd.base.autoneg; 3443 hdev->hw.mac.speed = cmd.base.speed; 3444 hdev->hw.mac.duplex = cmd.base.duplex; 3445 linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising); 3446 3447 return 0; 3448 } 3449 3450 static int hclge_tp_port_init(struct hclge_dev *hdev) 3451 { 3452 struct ethtool_link_ksettings cmd; 3453 3454 if (!hnae3_dev_phy_imp_supported(hdev)) 3455 return 0; 3456 3457 cmd.base.autoneg = hdev->hw.mac.autoneg; 3458 cmd.base.speed = hdev->hw.mac.speed; 3459 cmd.base.duplex = hdev->hw.mac.duplex; 3460 linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising); 3461 3462 return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd); 3463 } 3464 3465 static int hclge_update_port_info(struct hclge_dev *hdev) 3466 { 3467 struct hclge_mac *mac = &hdev->hw.mac; 3468 int speed; 3469 int ret; 3470 3471 /* get the port info from SFP cmd if not copper port */ 3472 if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3473 return hclge_update_tp_port_info(hdev); 3474 3475 /* if IMP does not support get SFP/qSFP info, return directly */ 3476 if (!hdev->support_sfp_query) 3477 return 0; 3478 3479 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3480 speed = mac->speed; 3481 ret = hclge_get_sfp_info(hdev, mac); 3482 } else { 3483 speed = HCLGE_MAC_SPEED_UNKNOWN; 3484 ret = hclge_get_sfp_speed(hdev, &speed); 3485 } 3486 3487 if (ret == -EOPNOTSUPP) { 3488 hdev->support_sfp_query = false; 3489 return ret; 3490 } else if (ret) { 3491 return ret; 3492 } 3493 3494 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3495 if (mac->speed_type == QUERY_ACTIVE_SPEED) { 3496 hclge_update_port_capability(hdev, mac); 3497 if (mac->speed != speed) 3498 (void)hclge_tm_port_shaper_cfg(hdev); 3499 return 0; 3500 } 3501 return hclge_cfg_mac_speed_dup(hdev, mac->speed, 3502 HCLGE_MAC_FULL, mac->lane_num); 3503 } else { 3504 if (speed == HCLGE_MAC_SPEED_UNKNOWN) 3505 return 0; /* do nothing if no SFP */ 3506 3507 /* must config full duplex for SFP */ 3508 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0); 3509 } 3510 } 3511 3512 static int hclge_get_status(struct hnae3_handle *handle) 3513 { 3514 struct hclge_vport *vport = hclge_get_vport(handle); 3515 struct hclge_dev *hdev = vport->back; 3516 3517 hclge_update_link_status(hdev); 3518 3519 return hdev->hw.mac.link; 3520 } 3521 3522 static struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf) 3523 { 3524 if (!pci_num_vf(hdev->pdev)) { 3525 dev_err(&hdev->pdev->dev, 3526 "SRIOV is disabled, can not get vport(%d) info.\n", vf); 3527 return NULL; 3528 } 3529 3530 if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) { 3531 dev_err(&hdev->pdev->dev, 3532 "vf id(%d) is out of range(0 <= vfid < %d)\n", 3533 vf, pci_num_vf(hdev->pdev)); 3534 return NULL; 3535 } 3536 3537 /* VF start from 1 in vport */ 3538 vf += HCLGE_VF_VPORT_START_NUM; 3539 return &hdev->vport[vf]; 3540 } 3541 3542 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf, 3543 struct ifla_vf_info *ivf) 3544 { 3545 struct hclge_vport *vport = hclge_get_vport(handle); 3546 struct hclge_dev *hdev = vport->back; 3547 3548 vport = hclge_get_vf_vport(hdev, vf); 3549 if (!vport) 3550 return -EINVAL; 3551 3552 ivf->vf = vf; 3553 ivf->linkstate = vport->vf_info.link_state; 3554 ivf->spoofchk = vport->vf_info.spoofchk; 3555 ivf->trusted = vport->vf_info.trusted; 3556 ivf->min_tx_rate = 0; 3557 ivf->max_tx_rate = vport->vf_info.max_tx_rate; 3558 ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag; 3559 ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto); 3560 ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos; 3561 ether_addr_copy(ivf->mac, vport->vf_info.mac); 3562 3563 return 0; 3564 } 3565 3566 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, 3567 int link_state) 3568 { 3569 struct hclge_vport *vport = hclge_get_vport(handle); 3570 struct hclge_dev *hdev = vport->back; 3571 int link_state_old; 3572 int ret; 3573 3574 vport = hclge_get_vf_vport(hdev, vf); 3575 if (!vport) 3576 return -EINVAL; 3577 3578 link_state_old = vport->vf_info.link_state; 3579 vport->vf_info.link_state = link_state; 3580 3581 /* return success directly if the VF is unalive, VF will 3582 * query link state itself when it starts work. 3583 */ 3584 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3585 return 0; 3586 3587 ret = hclge_push_vf_link_status(vport); 3588 if (ret) { 3589 vport->vf_info.link_state = link_state_old; 3590 dev_err(&hdev->pdev->dev, 3591 "failed to push vf%d link status, ret = %d\n", vf, ret); 3592 } 3593 3594 return ret; 3595 } 3596 3597 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 3598 { 3599 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; 3600 3601 /* fetch the events from their corresponding regs */ 3602 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 3603 msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 3604 hw_err_src_reg = hclge_read_dev(&hdev->hw, 3605 HCLGE_RAS_PF_OTHER_INT_STS_REG); 3606 3607 /* Assumption: If by any chance reset and mailbox events are reported 3608 * together then we will only process reset event in this go and will 3609 * defer the processing of the mailbox events. Since, we would have not 3610 * cleared RX CMDQ event this time we would receive again another 3611 * interrupt from H/W just for the mailbox. 3612 * 3613 * check for vector0 reset event sources 3614 */ 3615 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { 3616 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); 3617 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); 3618 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3619 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3620 hdev->rst_stats.imp_rst_cnt++; 3621 return HCLGE_VECTOR0_EVENT_RST; 3622 } 3623 3624 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { 3625 dev_info(&hdev->pdev->dev, "global reset interrupt\n"); 3626 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3627 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 3628 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3629 hdev->rst_stats.global_rst_cnt++; 3630 return HCLGE_VECTOR0_EVENT_RST; 3631 } 3632 3633 /* check for vector0 msix event and hardware error event source */ 3634 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK || 3635 hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK) 3636 return HCLGE_VECTOR0_EVENT_ERR; 3637 3638 /* check for vector0 ptp event source */ 3639 if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) { 3640 *clearval = msix_src_reg; 3641 return HCLGE_VECTOR0_EVENT_PTP; 3642 } 3643 3644 /* check for vector0 mailbox(=CMDQ RX) event source */ 3645 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 3646 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 3647 *clearval = cmdq_src_reg; 3648 return HCLGE_VECTOR0_EVENT_MBX; 3649 } 3650 3651 /* print other vector0 event source */ 3652 dev_info(&hdev->pdev->dev, 3653 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n", 3654 cmdq_src_reg, hw_err_src_reg, msix_src_reg); 3655 3656 return HCLGE_VECTOR0_EVENT_OTHER; 3657 } 3658 3659 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 3660 u32 regclr) 3661 { 3662 switch (event_type) { 3663 case HCLGE_VECTOR0_EVENT_PTP: 3664 case HCLGE_VECTOR0_EVENT_RST: 3665 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 3666 break; 3667 case HCLGE_VECTOR0_EVENT_MBX: 3668 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 3669 break; 3670 default: 3671 break; 3672 } 3673 } 3674 3675 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 3676 { 3677 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 3678 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 3679 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 3680 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 3681 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 3682 } 3683 3684 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 3685 { 3686 writel(enable ? 1 : 0, vector->addr); 3687 } 3688 3689 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 3690 { 3691 struct hclge_dev *hdev = data; 3692 unsigned long flags; 3693 u32 clearval = 0; 3694 u32 event_cause; 3695 3696 hclge_enable_vector(&hdev->misc_vector, false); 3697 event_cause = hclge_check_event_cause(hdev, &clearval); 3698 3699 /* vector 0 interrupt is shared with reset and mailbox source events. */ 3700 switch (event_cause) { 3701 case HCLGE_VECTOR0_EVENT_ERR: 3702 hclge_errhand_task_schedule(hdev); 3703 break; 3704 case HCLGE_VECTOR0_EVENT_RST: 3705 hclge_reset_task_schedule(hdev); 3706 break; 3707 case HCLGE_VECTOR0_EVENT_PTP: 3708 spin_lock_irqsave(&hdev->ptp->lock, flags); 3709 hclge_ptp_clean_tx_hwts(hdev); 3710 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 3711 break; 3712 case HCLGE_VECTOR0_EVENT_MBX: 3713 /* If we are here then, 3714 * 1. Either we are not handling any mbx task and we are not 3715 * scheduled as well 3716 * OR 3717 * 2. We could be handling a mbx task but nothing more is 3718 * scheduled. 3719 * In both cases, we should schedule mbx task as there are more 3720 * mbx messages reported by this interrupt. 3721 */ 3722 hclge_mbx_task_schedule(hdev); 3723 break; 3724 default: 3725 dev_warn(&hdev->pdev->dev, 3726 "received unknown or unhandled event of vector0\n"); 3727 break; 3728 } 3729 3730 hclge_clear_event_cause(hdev, event_cause, clearval); 3731 3732 /* Enable interrupt if it is not caused by reset event or error event */ 3733 if (event_cause == HCLGE_VECTOR0_EVENT_PTP || 3734 event_cause == HCLGE_VECTOR0_EVENT_MBX || 3735 event_cause == HCLGE_VECTOR0_EVENT_OTHER) 3736 hclge_enable_vector(&hdev->misc_vector, true); 3737 3738 return IRQ_HANDLED; 3739 } 3740 3741 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 3742 { 3743 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 3744 dev_warn(&hdev->pdev->dev, 3745 "vector(vector_id %d) has been freed.\n", vector_id); 3746 return; 3747 } 3748 3749 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 3750 hdev->num_msi_left += 1; 3751 hdev->num_msi_used -= 1; 3752 } 3753 3754 static void hclge_get_misc_vector(struct hclge_dev *hdev) 3755 { 3756 struct hclge_misc_vector *vector = &hdev->misc_vector; 3757 3758 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 3759 3760 vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 3761 hdev->vector_status[0] = 0; 3762 3763 hdev->num_msi_left -= 1; 3764 hdev->num_msi_used += 1; 3765 } 3766 3767 static int hclge_misc_irq_init(struct hclge_dev *hdev) 3768 { 3769 int ret; 3770 3771 hclge_get_misc_vector(hdev); 3772 3773 /* this would be explicitly freed in the end */ 3774 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 3775 HCLGE_NAME, pci_name(hdev->pdev)); 3776 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 3777 0, hdev->misc_vector.name, hdev); 3778 if (ret) { 3779 hclge_free_vector(hdev, 0); 3780 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 3781 hdev->misc_vector.vector_irq); 3782 } 3783 3784 return ret; 3785 } 3786 3787 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 3788 { 3789 free_irq(hdev->misc_vector.vector_irq, hdev); 3790 hclge_free_vector(hdev, 0); 3791 } 3792 3793 int hclge_notify_client(struct hclge_dev *hdev, 3794 enum hnae3_reset_notify_type type) 3795 { 3796 struct hnae3_handle *handle = &hdev->vport[0].nic; 3797 struct hnae3_client *client = hdev->nic_client; 3798 int ret; 3799 3800 if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client) 3801 return 0; 3802 3803 if (!client->ops->reset_notify) 3804 return -EOPNOTSUPP; 3805 3806 ret = client->ops->reset_notify(handle, type); 3807 if (ret) 3808 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 3809 type, ret); 3810 3811 return ret; 3812 } 3813 3814 static int hclge_notify_roce_client(struct hclge_dev *hdev, 3815 enum hnae3_reset_notify_type type) 3816 { 3817 struct hnae3_handle *handle = &hdev->vport[0].roce; 3818 struct hnae3_client *client = hdev->roce_client; 3819 int ret; 3820 3821 if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client) 3822 return 0; 3823 3824 if (!client->ops->reset_notify) 3825 return -EOPNOTSUPP; 3826 3827 ret = client->ops->reset_notify(handle, type); 3828 if (ret) 3829 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 3830 type, ret); 3831 3832 return ret; 3833 } 3834 3835 static int hclge_reset_wait(struct hclge_dev *hdev) 3836 { 3837 #define HCLGE_RESET_WATI_MS 100 3838 #define HCLGE_RESET_WAIT_CNT 350 3839 3840 u32 val, reg, reg_bit; 3841 u32 cnt = 0; 3842 3843 switch (hdev->reset_type) { 3844 case HNAE3_IMP_RESET: 3845 reg = HCLGE_GLOBAL_RESET_REG; 3846 reg_bit = HCLGE_IMP_RESET_BIT; 3847 break; 3848 case HNAE3_GLOBAL_RESET: 3849 reg = HCLGE_GLOBAL_RESET_REG; 3850 reg_bit = HCLGE_GLOBAL_RESET_BIT; 3851 break; 3852 case HNAE3_FUNC_RESET: 3853 reg = HCLGE_FUN_RST_ING; 3854 reg_bit = HCLGE_FUN_RST_ING_B; 3855 break; 3856 default: 3857 dev_err(&hdev->pdev->dev, 3858 "Wait for unsupported reset type: %d\n", 3859 hdev->reset_type); 3860 return -EINVAL; 3861 } 3862 3863 val = hclge_read_dev(&hdev->hw, reg); 3864 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 3865 msleep(HCLGE_RESET_WATI_MS); 3866 val = hclge_read_dev(&hdev->hw, reg); 3867 cnt++; 3868 } 3869 3870 if (cnt >= HCLGE_RESET_WAIT_CNT) { 3871 dev_warn(&hdev->pdev->dev, 3872 "Wait for reset timeout: %d\n", hdev->reset_type); 3873 return -EBUSY; 3874 } 3875 3876 return 0; 3877 } 3878 3879 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset) 3880 { 3881 struct hclge_vf_rst_cmd *req; 3882 struct hclge_desc desc; 3883 3884 req = (struct hclge_vf_rst_cmd *)desc.data; 3885 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false); 3886 req->dest_vfid = func_id; 3887 3888 if (reset) 3889 req->vf_rst = 0x1; 3890 3891 return hclge_cmd_send(&hdev->hw, &desc, 1); 3892 } 3893 3894 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset) 3895 { 3896 int i; 3897 3898 for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) { 3899 struct hclge_vport *vport = &hdev->vport[i]; 3900 int ret; 3901 3902 /* Send cmd to set/clear VF's FUNC_RST_ING */ 3903 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset); 3904 if (ret) { 3905 dev_err(&hdev->pdev->dev, 3906 "set vf(%u) rst failed %d!\n", 3907 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3908 ret); 3909 return ret; 3910 } 3911 3912 if (!reset || 3913 !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state)) 3914 continue; 3915 3916 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) && 3917 hdev->reset_type == HNAE3_FUNC_RESET) { 3918 set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET, 3919 &vport->need_notify); 3920 continue; 3921 } 3922 3923 /* Inform VF to process the reset. 3924 * hclge_inform_reset_assert_to_vf may fail if VF 3925 * driver is not loaded. 3926 */ 3927 ret = hclge_inform_reset_assert_to_vf(vport); 3928 if (ret) 3929 dev_warn(&hdev->pdev->dev, 3930 "inform reset to vf(%u) failed %d!\n", 3931 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3932 ret); 3933 } 3934 3935 return 0; 3936 } 3937 3938 static void hclge_mailbox_service_task(struct hclge_dev *hdev) 3939 { 3940 if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) || 3941 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) || 3942 test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 3943 return; 3944 3945 if (time_is_before_jiffies(hdev->last_mbx_scheduled + 3946 HCLGE_MBX_SCHED_TIMEOUT)) 3947 dev_warn(&hdev->pdev->dev, 3948 "mbx service task is scheduled after %ums on cpu%u!\n", 3949 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled), 3950 smp_processor_id()); 3951 3952 hclge_mbx_handler(hdev); 3953 3954 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 3955 } 3956 3957 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev) 3958 { 3959 struct hclge_pf_rst_sync_cmd *req; 3960 struct hclge_desc desc; 3961 int cnt = 0; 3962 int ret; 3963 3964 req = (struct hclge_pf_rst_sync_cmd *)desc.data; 3965 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true); 3966 3967 do { 3968 /* vf need to down netdev by mbx during PF or FLR reset */ 3969 hclge_mailbox_service_task(hdev); 3970 3971 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3972 /* for compatible with old firmware, wait 3973 * 100 ms for VF to stop IO 3974 */ 3975 if (ret == -EOPNOTSUPP) { 3976 msleep(HCLGE_RESET_SYNC_TIME); 3977 return; 3978 } else if (ret) { 3979 dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n", 3980 ret); 3981 return; 3982 } else if (req->all_vf_ready) { 3983 return; 3984 } 3985 msleep(HCLGE_PF_RESET_SYNC_TIME); 3986 hclge_comm_cmd_reuse_desc(&desc, true); 3987 } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT); 3988 3989 dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n"); 3990 } 3991 3992 void hclge_report_hw_error(struct hclge_dev *hdev, 3993 enum hnae3_hw_error_type type) 3994 { 3995 struct hnae3_client *client = hdev->nic_client; 3996 3997 if (!client || !client->ops->process_hw_error || 3998 !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) 3999 return; 4000 4001 client->ops->process_hw_error(&hdev->vport[0].nic, type); 4002 } 4003 4004 static void hclge_handle_imp_error(struct hclge_dev *hdev) 4005 { 4006 u32 reg_val; 4007 4008 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4009 if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { 4010 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); 4011 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); 4012 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 4013 } 4014 4015 if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { 4016 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); 4017 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); 4018 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 4019 } 4020 } 4021 4022 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 4023 { 4024 struct hclge_desc desc; 4025 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 4026 int ret; 4027 4028 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 4029 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 4030 req->fun_reset_vfid = func_id; 4031 4032 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4033 if (ret) 4034 dev_err(&hdev->pdev->dev, 4035 "send function reset cmd fail, status =%d\n", ret); 4036 4037 return ret; 4038 } 4039 4040 static void hclge_do_reset(struct hclge_dev *hdev) 4041 { 4042 struct hnae3_handle *handle = &hdev->vport[0].nic; 4043 struct pci_dev *pdev = hdev->pdev; 4044 u32 val; 4045 4046 if (hclge_get_hw_reset_stat(handle)) { 4047 dev_info(&pdev->dev, "hardware reset not finish\n"); 4048 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n", 4049 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING), 4050 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 4051 return; 4052 } 4053 4054 switch (hdev->reset_type) { 4055 case HNAE3_IMP_RESET: 4056 dev_info(&pdev->dev, "IMP reset requested\n"); 4057 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4058 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1); 4059 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val); 4060 break; 4061 case HNAE3_GLOBAL_RESET: 4062 dev_info(&pdev->dev, "global reset requested\n"); 4063 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 4064 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 4065 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 4066 break; 4067 case HNAE3_FUNC_RESET: 4068 dev_info(&pdev->dev, "PF reset requested\n"); 4069 /* schedule again to check later */ 4070 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); 4071 hclge_reset_task_schedule(hdev); 4072 break; 4073 default: 4074 dev_warn(&pdev->dev, 4075 "unsupported reset type: %d\n", hdev->reset_type); 4076 break; 4077 } 4078 } 4079 4080 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 4081 unsigned long *addr) 4082 { 4083 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 4084 struct hclge_dev *hdev = ae_dev->priv; 4085 4086 /* return the highest priority reset level amongst all */ 4087 if (test_bit(HNAE3_IMP_RESET, addr)) { 4088 rst_level = HNAE3_IMP_RESET; 4089 clear_bit(HNAE3_IMP_RESET, addr); 4090 clear_bit(HNAE3_GLOBAL_RESET, addr); 4091 clear_bit(HNAE3_FUNC_RESET, addr); 4092 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) { 4093 rst_level = HNAE3_GLOBAL_RESET; 4094 clear_bit(HNAE3_GLOBAL_RESET, addr); 4095 clear_bit(HNAE3_FUNC_RESET, addr); 4096 } else if (test_bit(HNAE3_FUNC_RESET, addr)) { 4097 rst_level = HNAE3_FUNC_RESET; 4098 clear_bit(HNAE3_FUNC_RESET, addr); 4099 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 4100 rst_level = HNAE3_FLR_RESET; 4101 clear_bit(HNAE3_FLR_RESET, addr); 4102 } 4103 4104 if (hdev->reset_type != HNAE3_NONE_RESET && 4105 rst_level < hdev->reset_type) 4106 return HNAE3_NONE_RESET; 4107 4108 return rst_level; 4109 } 4110 4111 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 4112 { 4113 u32 clearval = 0; 4114 4115 switch (hdev->reset_type) { 4116 case HNAE3_IMP_RESET: 4117 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 4118 break; 4119 case HNAE3_GLOBAL_RESET: 4120 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 4121 break; 4122 default: 4123 break; 4124 } 4125 4126 if (!clearval) 4127 return; 4128 4129 /* For revision 0x20, the reset interrupt source 4130 * can only be cleared after hardware reset done 4131 */ 4132 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 4133 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, 4134 clearval); 4135 4136 hclge_enable_vector(&hdev->misc_vector, true); 4137 } 4138 4139 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable) 4140 { 4141 u32 reg_val; 4142 4143 reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 4144 if (enable) 4145 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY; 4146 else 4147 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY; 4148 4149 hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val); 4150 } 4151 4152 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev) 4153 { 4154 int ret; 4155 4156 ret = hclge_set_all_vf_rst(hdev, true); 4157 if (ret) 4158 return ret; 4159 4160 hclge_func_reset_sync_vf(hdev); 4161 4162 return 0; 4163 } 4164 4165 static int hclge_reset_prepare_wait(struct hclge_dev *hdev) 4166 { 4167 u32 reg_val; 4168 int ret = 0; 4169 4170 switch (hdev->reset_type) { 4171 case HNAE3_FUNC_RESET: 4172 ret = hclge_func_reset_notify_vf(hdev); 4173 if (ret) 4174 return ret; 4175 4176 ret = hclge_func_reset_cmd(hdev, 0); 4177 if (ret) { 4178 dev_err(&hdev->pdev->dev, 4179 "asserting function reset fail %d!\n", ret); 4180 return ret; 4181 } 4182 4183 /* After performaning pf reset, it is not necessary to do the 4184 * mailbox handling or send any command to firmware, because 4185 * any mailbox handling or command to firmware is only valid 4186 * after hclge_comm_cmd_init is called. 4187 */ 4188 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 4189 hdev->rst_stats.pf_rst_cnt++; 4190 break; 4191 case HNAE3_FLR_RESET: 4192 ret = hclge_func_reset_notify_vf(hdev); 4193 if (ret) 4194 return ret; 4195 break; 4196 case HNAE3_IMP_RESET: 4197 hclge_handle_imp_error(hdev); 4198 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4199 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, 4200 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); 4201 break; 4202 default: 4203 break; 4204 } 4205 4206 /* inform hardware that preparatory work is done */ 4207 msleep(HCLGE_RESET_SYNC_TIME); 4208 hclge_reset_handshake(hdev, true); 4209 dev_info(&hdev->pdev->dev, "prepare wait ok\n"); 4210 4211 return ret; 4212 } 4213 4214 static void hclge_show_rst_info(struct hclge_dev *hdev) 4215 { 4216 char *buf; 4217 4218 buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL); 4219 if (!buf) 4220 return; 4221 4222 hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN); 4223 4224 dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf); 4225 4226 kfree(buf); 4227 } 4228 4229 static bool hclge_reset_err_handle(struct hclge_dev *hdev) 4230 { 4231 #define MAX_RESET_FAIL_CNT 5 4232 4233 if (hdev->reset_pending) { 4234 dev_info(&hdev->pdev->dev, "Reset pending %lu\n", 4235 hdev->reset_pending); 4236 return true; 4237 } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) & 4238 HCLGE_RESET_INT_M) { 4239 dev_info(&hdev->pdev->dev, 4240 "reset failed because new reset interrupt\n"); 4241 hclge_clear_reset_cause(hdev); 4242 return false; 4243 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { 4244 hdev->rst_stats.reset_fail_cnt++; 4245 set_bit(hdev->reset_type, &hdev->reset_pending); 4246 dev_info(&hdev->pdev->dev, 4247 "re-schedule reset task(%u)\n", 4248 hdev->rst_stats.reset_fail_cnt); 4249 return true; 4250 } 4251 4252 hclge_clear_reset_cause(hdev); 4253 4254 /* recover the handshake status when reset fail */ 4255 hclge_reset_handshake(hdev, true); 4256 4257 dev_err(&hdev->pdev->dev, "Reset fail!\n"); 4258 4259 hclge_show_rst_info(hdev); 4260 4261 set_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4262 4263 return false; 4264 } 4265 4266 static void hclge_update_reset_level(struct hclge_dev *hdev) 4267 { 4268 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4269 enum hnae3_reset_type reset_level; 4270 4271 /* reset request will not be set during reset, so clear 4272 * pending reset request to avoid unnecessary reset 4273 * caused by the same reason. 4274 */ 4275 hclge_get_reset_level(ae_dev, &hdev->reset_request); 4276 4277 /* if default_reset_request has a higher level reset request, 4278 * it should be handled as soon as possible. since some errors 4279 * need this kind of reset to fix. 4280 */ 4281 reset_level = hclge_get_reset_level(ae_dev, 4282 &hdev->default_reset_request); 4283 if (reset_level != HNAE3_NONE_RESET) 4284 set_bit(reset_level, &hdev->reset_request); 4285 } 4286 4287 static int hclge_set_rst_done(struct hclge_dev *hdev) 4288 { 4289 struct hclge_pf_rst_done_cmd *req; 4290 struct hclge_desc desc; 4291 int ret; 4292 4293 req = (struct hclge_pf_rst_done_cmd *)desc.data; 4294 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false); 4295 req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT; 4296 4297 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4298 /* To be compatible with the old firmware, which does not support 4299 * command HCLGE_OPC_PF_RST_DONE, just print a warning and 4300 * return success 4301 */ 4302 if (ret == -EOPNOTSUPP) { 4303 dev_warn(&hdev->pdev->dev, 4304 "current firmware does not support command(0x%x)!\n", 4305 HCLGE_OPC_PF_RST_DONE); 4306 return 0; 4307 } else if (ret) { 4308 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n", 4309 ret); 4310 } 4311 4312 return ret; 4313 } 4314 4315 static int hclge_reset_prepare_up(struct hclge_dev *hdev) 4316 { 4317 int ret = 0; 4318 4319 switch (hdev->reset_type) { 4320 case HNAE3_FUNC_RESET: 4321 case HNAE3_FLR_RESET: 4322 ret = hclge_set_all_vf_rst(hdev, false); 4323 break; 4324 case HNAE3_GLOBAL_RESET: 4325 case HNAE3_IMP_RESET: 4326 ret = hclge_set_rst_done(hdev); 4327 break; 4328 default: 4329 break; 4330 } 4331 4332 /* clear up the handshake status after re-initialize done */ 4333 hclge_reset_handshake(hdev, false); 4334 4335 return ret; 4336 } 4337 4338 static int hclge_reset_stack(struct hclge_dev *hdev) 4339 { 4340 int ret; 4341 4342 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 4343 if (ret) 4344 return ret; 4345 4346 ret = hclge_reset_ae_dev(hdev->ae_dev); 4347 if (ret) 4348 return ret; 4349 4350 return hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 4351 } 4352 4353 static int hclge_reset_prepare(struct hclge_dev *hdev) 4354 { 4355 int ret; 4356 4357 hdev->rst_stats.reset_cnt++; 4358 /* perform reset of the stack & ae device for a client */ 4359 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 4360 if (ret) 4361 return ret; 4362 4363 rtnl_lock(); 4364 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 4365 rtnl_unlock(); 4366 if (ret) 4367 return ret; 4368 4369 return hclge_reset_prepare_wait(hdev); 4370 } 4371 4372 static int hclge_reset_rebuild(struct hclge_dev *hdev) 4373 { 4374 int ret; 4375 4376 hdev->rst_stats.hw_reset_done_cnt++; 4377 4378 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 4379 if (ret) 4380 return ret; 4381 4382 rtnl_lock(); 4383 ret = hclge_reset_stack(hdev); 4384 rtnl_unlock(); 4385 if (ret) 4386 return ret; 4387 4388 hclge_clear_reset_cause(hdev); 4389 4390 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 4391 /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1 4392 * times 4393 */ 4394 if (ret && 4395 hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1) 4396 return ret; 4397 4398 ret = hclge_reset_prepare_up(hdev); 4399 if (ret) 4400 return ret; 4401 4402 rtnl_lock(); 4403 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT); 4404 rtnl_unlock(); 4405 if (ret) 4406 return ret; 4407 4408 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT); 4409 if (ret) 4410 return ret; 4411 4412 hdev->last_reset_time = jiffies; 4413 hdev->rst_stats.reset_fail_cnt = 0; 4414 hdev->rst_stats.reset_done_cnt++; 4415 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4416 4417 hclge_update_reset_level(hdev); 4418 4419 return 0; 4420 } 4421 4422 static void hclge_reset(struct hclge_dev *hdev) 4423 { 4424 if (hclge_reset_prepare(hdev)) 4425 goto err_reset; 4426 4427 if (hclge_reset_wait(hdev)) 4428 goto err_reset; 4429 4430 if (hclge_reset_rebuild(hdev)) 4431 goto err_reset; 4432 4433 return; 4434 4435 err_reset: 4436 if (hclge_reset_err_handle(hdev)) 4437 hclge_reset_task_schedule(hdev); 4438 } 4439 4440 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) 4441 { 4442 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4443 struct hclge_dev *hdev = ae_dev->priv; 4444 4445 /* We might end up getting called broadly because of 2 below cases: 4446 * 1. Recoverable error was conveyed through APEI and only way to bring 4447 * normalcy is to reset. 4448 * 2. A new reset request from the stack due to timeout 4449 * 4450 * check if this is a new reset request and we are not here just because 4451 * last reset attempt did not succeed and watchdog hit us again. We will 4452 * know this if last reset request did not occur very recently (watchdog 4453 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 4454 * In case of new request we reset the "reset level" to PF reset. 4455 * And if it is a repeat reset request of the most recent one then we 4456 * want to make sure we throttle the reset request. Therefore, we will 4457 * not allow it again before 3*HZ times. 4458 */ 4459 4460 if (time_before(jiffies, (hdev->last_reset_time + 4461 HCLGE_RESET_INTERVAL))) { 4462 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 4463 return; 4464 } 4465 4466 if (hdev->default_reset_request) { 4467 hdev->reset_level = 4468 hclge_get_reset_level(ae_dev, 4469 &hdev->default_reset_request); 4470 } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) { 4471 hdev->reset_level = HNAE3_FUNC_RESET; 4472 } 4473 4474 dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n", 4475 hdev->reset_level); 4476 4477 /* request reset & schedule reset task */ 4478 set_bit(hdev->reset_level, &hdev->reset_request); 4479 hclge_reset_task_schedule(hdev); 4480 4481 if (hdev->reset_level < HNAE3_GLOBAL_RESET) 4482 hdev->reset_level++; 4483 } 4484 4485 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 4486 enum hnae3_reset_type rst_type) 4487 { 4488 struct hclge_dev *hdev = ae_dev->priv; 4489 4490 set_bit(rst_type, &hdev->default_reset_request); 4491 } 4492 4493 static void hclge_reset_timer(struct timer_list *t) 4494 { 4495 struct hclge_dev *hdev = from_timer(hdev, t, reset_timer); 4496 4497 /* if default_reset_request has no value, it means that this reset 4498 * request has already be handled, so just return here 4499 */ 4500 if (!hdev->default_reset_request) 4501 return; 4502 4503 dev_info(&hdev->pdev->dev, 4504 "triggering reset in reset timer\n"); 4505 hclge_reset_event(hdev->pdev, NULL); 4506 } 4507 4508 static void hclge_reset_subtask(struct hclge_dev *hdev) 4509 { 4510 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4511 4512 /* check if there is any ongoing reset in the hardware. This status can 4513 * be checked from reset_pending. If there is then, we need to wait for 4514 * hardware to complete reset. 4515 * a. If we are able to figure out in reasonable time that hardware 4516 * has fully resetted then, we can proceed with driver, client 4517 * reset. 4518 * b. else, we can come back later to check this status so re-sched 4519 * now. 4520 */ 4521 hdev->last_reset_time = jiffies; 4522 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending); 4523 if (hdev->reset_type != HNAE3_NONE_RESET) 4524 hclge_reset(hdev); 4525 4526 /* check if we got any *new* reset requests to be honored */ 4527 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request); 4528 if (hdev->reset_type != HNAE3_NONE_RESET) 4529 hclge_do_reset(hdev); 4530 4531 hdev->reset_type = HNAE3_NONE_RESET; 4532 } 4533 4534 static void hclge_handle_err_reset_request(struct hclge_dev *hdev) 4535 { 4536 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4537 enum hnae3_reset_type reset_type; 4538 4539 if (ae_dev->hw_err_reset_req) { 4540 reset_type = hclge_get_reset_level(ae_dev, 4541 &ae_dev->hw_err_reset_req); 4542 hclge_set_def_reset_request(ae_dev, reset_type); 4543 } 4544 4545 if (hdev->default_reset_request && ae_dev->ops->reset_event) 4546 ae_dev->ops->reset_event(hdev->pdev, NULL); 4547 4548 /* enable interrupt after error handling complete */ 4549 hclge_enable_vector(&hdev->misc_vector, true); 4550 } 4551 4552 static void hclge_handle_err_recovery(struct hclge_dev *hdev) 4553 { 4554 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4555 4556 ae_dev->hw_err_reset_req = 0; 4557 4558 if (hclge_find_error_source(hdev)) { 4559 hclge_handle_error_info_log(ae_dev); 4560 hclge_handle_mac_tnl(hdev); 4561 } 4562 4563 hclge_handle_err_reset_request(hdev); 4564 } 4565 4566 static void hclge_misc_err_recovery(struct hclge_dev *hdev) 4567 { 4568 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4569 struct device *dev = &hdev->pdev->dev; 4570 u32 msix_sts_reg; 4571 4572 msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 4573 if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) { 4574 if (hclge_handle_hw_msix_error 4575 (hdev, &hdev->default_reset_request)) 4576 dev_info(dev, "received msix interrupt 0x%x\n", 4577 msix_sts_reg); 4578 } 4579 4580 hclge_handle_hw_ras_error(ae_dev); 4581 4582 hclge_handle_err_reset_request(hdev); 4583 } 4584 4585 static void hclge_errhand_service_task(struct hclge_dev *hdev) 4586 { 4587 if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 4588 return; 4589 4590 if (hnae3_dev_ras_imp_supported(hdev)) 4591 hclge_handle_err_recovery(hdev); 4592 else 4593 hclge_misc_err_recovery(hdev); 4594 } 4595 4596 static void hclge_reset_service_task(struct hclge_dev *hdev) 4597 { 4598 if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 4599 return; 4600 4601 if (time_is_before_jiffies(hdev->last_rst_scheduled + 4602 HCLGE_RESET_SCHED_TIMEOUT)) 4603 dev_warn(&hdev->pdev->dev, 4604 "reset service task is scheduled after %ums on cpu%u!\n", 4605 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled), 4606 smp_processor_id()); 4607 4608 down(&hdev->reset_sem); 4609 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4610 4611 hclge_reset_subtask(hdev); 4612 4613 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4614 up(&hdev->reset_sem); 4615 } 4616 4617 static void hclge_update_vport_alive(struct hclge_dev *hdev) 4618 { 4619 #define HCLGE_ALIVE_SECONDS_NORMAL 8 4620 4621 unsigned long alive_time = HCLGE_ALIVE_SECONDS_NORMAL * HZ; 4622 int i; 4623 4624 /* start from vport 1 for PF is always alive */ 4625 for (i = 1; i < hdev->num_alloc_vport; i++) { 4626 struct hclge_vport *vport = &hdev->vport[i]; 4627 4628 if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) || 4629 !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 4630 continue; 4631 if (time_after(jiffies, vport->last_active_jiffies + 4632 alive_time)) { 4633 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 4634 dev_warn(&hdev->pdev->dev, 4635 "VF %u heartbeat timeout\n", 4636 i - HCLGE_VF_VPORT_START_NUM); 4637 } 4638 } 4639 } 4640 4641 static void hclge_periodic_service_task(struct hclge_dev *hdev) 4642 { 4643 unsigned long delta = round_jiffies_relative(HZ); 4644 4645 if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 4646 return; 4647 4648 /* Always handle the link updating to make sure link state is 4649 * updated when it is triggered by mbx. 4650 */ 4651 hclge_update_link_status(hdev); 4652 hclge_sync_mac_table(hdev); 4653 hclge_sync_promisc_mode(hdev); 4654 hclge_sync_fd_table(hdev); 4655 4656 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 4657 delta = jiffies - hdev->last_serv_processed; 4658 4659 if (delta < round_jiffies_relative(HZ)) { 4660 delta = round_jiffies_relative(HZ) - delta; 4661 goto out; 4662 } 4663 } 4664 4665 hdev->serv_processed_cnt++; 4666 hclge_update_vport_alive(hdev); 4667 4668 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) { 4669 hdev->last_serv_processed = jiffies; 4670 goto out; 4671 } 4672 4673 if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL)) 4674 hclge_update_stats_for_all(hdev); 4675 4676 hclge_update_port_info(hdev); 4677 hclge_sync_vlan_filter(hdev); 4678 4679 if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL)) 4680 hclge_rfs_filter_expire(hdev); 4681 4682 hdev->last_serv_processed = jiffies; 4683 4684 out: 4685 hclge_task_schedule(hdev, delta); 4686 } 4687 4688 static void hclge_ptp_service_task(struct hclge_dev *hdev) 4689 { 4690 unsigned long flags; 4691 4692 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) || 4693 !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) || 4694 !time_is_before_jiffies(hdev->ptp->tx_start + HZ)) 4695 return; 4696 4697 /* to prevent concurrence with the irq handler */ 4698 spin_lock_irqsave(&hdev->ptp->lock, flags); 4699 4700 /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq 4701 * handler may handle it just before spin_lock_irqsave(). 4702 */ 4703 if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) 4704 hclge_ptp_clean_tx_hwts(hdev); 4705 4706 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 4707 } 4708 4709 static void hclge_service_task(struct work_struct *work) 4710 { 4711 struct hclge_dev *hdev = 4712 container_of(work, struct hclge_dev, service_task.work); 4713 4714 hclge_errhand_service_task(hdev); 4715 hclge_reset_service_task(hdev); 4716 hclge_ptp_service_task(hdev); 4717 hclge_mailbox_service_task(hdev); 4718 hclge_periodic_service_task(hdev); 4719 4720 /* Handle error recovery, reset and mbx again in case periodical task 4721 * delays the handling by calling hclge_task_schedule() in 4722 * hclge_periodic_service_task(). 4723 */ 4724 hclge_errhand_service_task(hdev); 4725 hclge_reset_service_task(hdev); 4726 hclge_mailbox_service_task(hdev); 4727 } 4728 4729 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 4730 { 4731 /* VF handle has no client */ 4732 if (!handle->client) 4733 return container_of(handle, struct hclge_vport, nic); 4734 else if (handle->client->type == HNAE3_CLIENT_ROCE) 4735 return container_of(handle, struct hclge_vport, roce); 4736 else 4737 return container_of(handle, struct hclge_vport, nic); 4738 } 4739 4740 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx, 4741 struct hnae3_vector_info *vector_info) 4742 { 4743 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 64 4744 4745 vector_info->vector = pci_irq_vector(hdev->pdev, idx); 4746 4747 /* need an extend offset to config vector >= 64 */ 4748 if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2) 4749 vector_info->io_addr = hdev->hw.hw.io_base + 4750 HCLGE_VECTOR_REG_BASE + 4751 (idx - 1) * HCLGE_VECTOR_REG_OFFSET; 4752 else 4753 vector_info->io_addr = hdev->hw.hw.io_base + 4754 HCLGE_VECTOR_EXT_REG_BASE + 4755 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4756 HCLGE_VECTOR_REG_OFFSET_H + 4757 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4758 HCLGE_VECTOR_REG_OFFSET; 4759 4760 hdev->vector_status[idx] = hdev->vport[0].vport_id; 4761 hdev->vector_irq[idx] = vector_info->vector; 4762 } 4763 4764 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 4765 struct hnae3_vector_info *vector_info) 4766 { 4767 struct hclge_vport *vport = hclge_get_vport(handle); 4768 struct hnae3_vector_info *vector = vector_info; 4769 struct hclge_dev *hdev = vport->back; 4770 int alloc = 0; 4771 u16 i = 0; 4772 u16 j; 4773 4774 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num); 4775 vector_num = min(hdev->num_msi_left, vector_num); 4776 4777 for (j = 0; j < vector_num; j++) { 4778 while (++i < hdev->num_nic_msi) { 4779 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 4780 hclge_get_vector_info(hdev, i, vector); 4781 vector++; 4782 alloc++; 4783 4784 break; 4785 } 4786 } 4787 } 4788 hdev->num_msi_left -= alloc; 4789 hdev->num_msi_used += alloc; 4790 4791 return alloc; 4792 } 4793 4794 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 4795 { 4796 int i; 4797 4798 for (i = 0; i < hdev->num_msi; i++) 4799 if (vector == hdev->vector_irq[i]) 4800 return i; 4801 4802 return -EINVAL; 4803 } 4804 4805 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 4806 { 4807 struct hclge_vport *vport = hclge_get_vport(handle); 4808 struct hclge_dev *hdev = vport->back; 4809 int vector_id; 4810 4811 vector_id = hclge_get_vector_index(hdev, vector); 4812 if (vector_id < 0) { 4813 dev_err(&hdev->pdev->dev, 4814 "Get vector index fail. vector = %d\n", vector); 4815 return vector_id; 4816 } 4817 4818 hclge_free_vector(hdev, vector_id); 4819 4820 return 0; 4821 } 4822 4823 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 4824 u8 *key, u8 *hfunc) 4825 { 4826 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4827 struct hclge_vport *vport = hclge_get_vport(handle); 4828 struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg; 4829 4830 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 4831 4832 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 4833 ae_dev->dev_specs.rss_ind_tbl_size); 4834 4835 return 0; 4836 } 4837 4838 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 4839 const u8 *key, const u8 hfunc) 4840 { 4841 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4842 struct hclge_vport *vport = hclge_get_vport(handle); 4843 struct hclge_dev *hdev = vport->back; 4844 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 4845 int ret, i; 4846 4847 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc); 4848 if (ret) { 4849 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc); 4850 return ret; 4851 } 4852 4853 /* Update the shadow RSS table with user specified qids */ 4854 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 4855 rss_cfg->rss_indirection_tbl[i] = indir[i]; 4856 4857 /* Update the hardware */ 4858 return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw, 4859 rss_cfg->rss_indirection_tbl); 4860 } 4861 4862 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 4863 struct ethtool_rxnfc *nfc) 4864 { 4865 struct hclge_vport *vport = hclge_get_vport(handle); 4866 struct hclge_dev *hdev = vport->back; 4867 int ret; 4868 4869 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 4870 &hdev->rss_cfg, nfc); 4871 if (ret) { 4872 dev_err(&hdev->pdev->dev, 4873 "failed to set rss tuple, ret = %d.\n", ret); 4874 return ret; 4875 } 4876 4877 return 0; 4878 } 4879 4880 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 4881 struct ethtool_rxnfc *nfc) 4882 { 4883 struct hclge_vport *vport = hclge_get_vport(handle); 4884 u8 tuple_sets; 4885 int ret; 4886 4887 nfc->data = 0; 4888 4889 ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type, 4890 &tuple_sets); 4891 if (ret || !tuple_sets) 4892 return ret; 4893 4894 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 4895 4896 return 0; 4897 } 4898 4899 static int hclge_get_tc_size(struct hnae3_handle *handle) 4900 { 4901 struct hclge_vport *vport = hclge_get_vport(handle); 4902 struct hclge_dev *hdev = vport->back; 4903 4904 return hdev->pf_rss_size_max; 4905 } 4906 4907 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev) 4908 { 4909 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 4910 struct hclge_vport *vport = hdev->vport; 4911 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 4912 u16 tc_valid[HCLGE_MAX_TC_NUM] = {0}; 4913 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 4914 struct hnae3_tc_info *tc_info; 4915 u16 roundup_size; 4916 u16 rss_size; 4917 int i; 4918 4919 tc_info = &vport->nic.kinfo.tc_info; 4920 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 4921 rss_size = tc_info->tqp_count[i]; 4922 tc_valid[i] = 0; 4923 4924 if (!(hdev->hw_tc_map & BIT(i))) 4925 continue; 4926 4927 /* tc_size set to hardware is the log2 of roundup power of two 4928 * of rss_size, the acutal queue size is limited by indirection 4929 * table. 4930 */ 4931 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size || 4932 rss_size == 0) { 4933 dev_err(&hdev->pdev->dev, 4934 "Configure rss tc size failed, invalid TC_SIZE = %u\n", 4935 rss_size); 4936 return -EINVAL; 4937 } 4938 4939 roundup_size = roundup_pow_of_two(rss_size); 4940 roundup_size = ilog2(roundup_size); 4941 4942 tc_valid[i] = 1; 4943 tc_size[i] = roundup_size; 4944 tc_offset[i] = tc_info->tqp_offset[i]; 4945 } 4946 4947 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 4948 tc_size); 4949 } 4950 4951 int hclge_rss_init_hw(struct hclge_dev *hdev) 4952 { 4953 u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl; 4954 u8 *key = hdev->rss_cfg.rss_hash_key; 4955 u8 hfunc = hdev->rss_cfg.rss_algo; 4956 int ret; 4957 4958 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 4959 rss_indir); 4960 if (ret) 4961 return ret; 4962 4963 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key); 4964 if (ret) 4965 return ret; 4966 4967 ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, &hdev->rss_cfg); 4968 if (ret) 4969 return ret; 4970 4971 return hclge_init_rss_tc_mode(hdev); 4972 } 4973 4974 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 4975 int vector_id, bool en, 4976 struct hnae3_ring_chain_node *ring_chain) 4977 { 4978 struct hclge_dev *hdev = vport->back; 4979 struct hnae3_ring_chain_node *node; 4980 struct hclge_desc desc; 4981 struct hclge_ctrl_vector_chain_cmd *req = 4982 (struct hclge_ctrl_vector_chain_cmd *)desc.data; 4983 enum hclge_comm_cmd_status status; 4984 enum hclge_opcode_type op; 4985 u16 tqp_type_and_id; 4986 int i; 4987 4988 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 4989 hclge_cmd_setup_basic_desc(&desc, op, false); 4990 req->int_vector_id_l = hnae3_get_field(vector_id, 4991 HCLGE_VECTOR_ID_L_M, 4992 HCLGE_VECTOR_ID_L_S); 4993 req->int_vector_id_h = hnae3_get_field(vector_id, 4994 HCLGE_VECTOR_ID_H_M, 4995 HCLGE_VECTOR_ID_H_S); 4996 4997 i = 0; 4998 for (node = ring_chain; node; node = node->next) { 4999 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 5000 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 5001 HCLGE_INT_TYPE_S, 5002 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 5003 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 5004 HCLGE_TQP_ID_S, node->tqp_index); 5005 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 5006 HCLGE_INT_GL_IDX_S, 5007 hnae3_get_field(node->int_gl_idx, 5008 HNAE3_RING_GL_IDX_M, 5009 HNAE3_RING_GL_IDX_S)); 5010 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 5011 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 5012 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 5013 req->vfid = vport->vport_id; 5014 5015 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5016 if (status) { 5017 dev_err(&hdev->pdev->dev, 5018 "Map TQP fail, status is %d.\n", 5019 status); 5020 return -EIO; 5021 } 5022 i = 0; 5023 5024 hclge_cmd_setup_basic_desc(&desc, 5025 op, 5026 false); 5027 req->int_vector_id_l = 5028 hnae3_get_field(vector_id, 5029 HCLGE_VECTOR_ID_L_M, 5030 HCLGE_VECTOR_ID_L_S); 5031 req->int_vector_id_h = 5032 hnae3_get_field(vector_id, 5033 HCLGE_VECTOR_ID_H_M, 5034 HCLGE_VECTOR_ID_H_S); 5035 } 5036 } 5037 5038 if (i > 0) { 5039 req->int_cause_num = i; 5040 req->vfid = vport->vport_id; 5041 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5042 if (status) { 5043 dev_err(&hdev->pdev->dev, 5044 "Map TQP fail, status is %d.\n", status); 5045 return -EIO; 5046 } 5047 } 5048 5049 return 0; 5050 } 5051 5052 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector, 5053 struct hnae3_ring_chain_node *ring_chain) 5054 { 5055 struct hclge_vport *vport = hclge_get_vport(handle); 5056 struct hclge_dev *hdev = vport->back; 5057 int vector_id; 5058 5059 vector_id = hclge_get_vector_index(hdev, vector); 5060 if (vector_id < 0) { 5061 dev_err(&hdev->pdev->dev, 5062 "failed to get vector index. vector=%d\n", vector); 5063 return vector_id; 5064 } 5065 5066 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 5067 } 5068 5069 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector, 5070 struct hnae3_ring_chain_node *ring_chain) 5071 { 5072 struct hclge_vport *vport = hclge_get_vport(handle); 5073 struct hclge_dev *hdev = vport->back; 5074 int vector_id, ret; 5075 5076 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 5077 return 0; 5078 5079 vector_id = hclge_get_vector_index(hdev, vector); 5080 if (vector_id < 0) { 5081 dev_err(&handle->pdev->dev, 5082 "Get vector index fail. ret =%d\n", vector_id); 5083 return vector_id; 5084 } 5085 5086 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 5087 if (ret) 5088 dev_err(&handle->pdev->dev, 5089 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 5090 vector_id, ret); 5091 5092 return ret; 5093 } 5094 5095 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id, 5096 bool en_uc, bool en_mc, bool en_bc) 5097 { 5098 struct hclge_vport *vport = &hdev->vport[vf_id]; 5099 struct hnae3_handle *handle = &vport->nic; 5100 struct hclge_promisc_cfg_cmd *req; 5101 struct hclge_desc desc; 5102 bool uc_tx_en = en_uc; 5103 u8 promisc_cfg = 0; 5104 int ret; 5105 5106 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 5107 5108 req = (struct hclge_promisc_cfg_cmd *)desc.data; 5109 req->vf_id = vf_id; 5110 5111 if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags)) 5112 uc_tx_en = false; 5113 5114 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0); 5115 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0); 5116 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0); 5117 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0); 5118 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0); 5119 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0); 5120 req->extend_promisc = promisc_cfg; 5121 5122 /* to be compatible with DEVICE_VERSION_V1/2 */ 5123 promisc_cfg = 0; 5124 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0); 5125 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0); 5126 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0); 5127 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1); 5128 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1); 5129 req->promisc = promisc_cfg; 5130 5131 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5132 if (ret) 5133 dev_err(&hdev->pdev->dev, 5134 "failed to set vport %u promisc mode, ret = %d.\n", 5135 vf_id, ret); 5136 5137 return ret; 5138 } 5139 5140 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 5141 bool en_mc_pmc, bool en_bc_pmc) 5142 { 5143 return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id, 5144 en_uc_pmc, en_mc_pmc, en_bc_pmc); 5145 } 5146 5147 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 5148 bool en_mc_pmc) 5149 { 5150 struct hclge_vport *vport = hclge_get_vport(handle); 5151 struct hclge_dev *hdev = vport->back; 5152 bool en_bc_pmc = true; 5153 5154 /* For device whose version below V2, if broadcast promisc enabled, 5155 * vlan filter is always bypassed. So broadcast promisc should be 5156 * disabled until user enable promisc mode 5157 */ 5158 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 5159 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false; 5160 5161 return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc, 5162 en_bc_pmc); 5163 } 5164 5165 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle) 5166 { 5167 struct hclge_vport *vport = hclge_get_vport(handle); 5168 5169 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5170 } 5171 5172 static void hclge_sync_fd_state(struct hclge_dev *hdev) 5173 { 5174 if (hlist_empty(&hdev->fd_rule_list)) 5175 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 5176 } 5177 5178 static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location) 5179 { 5180 if (!test_bit(location, hdev->fd_bmap)) { 5181 set_bit(location, hdev->fd_bmap); 5182 hdev->hclge_fd_rule_num++; 5183 } 5184 } 5185 5186 static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location) 5187 { 5188 if (test_bit(location, hdev->fd_bmap)) { 5189 clear_bit(location, hdev->fd_bmap); 5190 hdev->hclge_fd_rule_num--; 5191 } 5192 } 5193 5194 static void hclge_fd_free_node(struct hclge_dev *hdev, 5195 struct hclge_fd_rule *rule) 5196 { 5197 hlist_del(&rule->rule_node); 5198 kfree(rule); 5199 hclge_sync_fd_state(hdev); 5200 } 5201 5202 static void hclge_update_fd_rule_node(struct hclge_dev *hdev, 5203 struct hclge_fd_rule *old_rule, 5204 struct hclge_fd_rule *new_rule, 5205 enum HCLGE_FD_NODE_STATE state) 5206 { 5207 switch (state) { 5208 case HCLGE_FD_TO_ADD: 5209 case HCLGE_FD_ACTIVE: 5210 /* 1) if the new state is TO_ADD, just replace the old rule 5211 * with the same location, no matter its state, because the 5212 * new rule will be configured to the hardware. 5213 * 2) if the new state is ACTIVE, it means the new rule 5214 * has been configured to the hardware, so just replace 5215 * the old rule node with the same location. 5216 * 3) for it doesn't add a new node to the list, so it's 5217 * unnecessary to update the rule number and fd_bmap. 5218 */ 5219 new_rule->rule_node.next = old_rule->rule_node.next; 5220 new_rule->rule_node.pprev = old_rule->rule_node.pprev; 5221 memcpy(old_rule, new_rule, sizeof(*old_rule)); 5222 kfree(new_rule); 5223 break; 5224 case HCLGE_FD_DELETED: 5225 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5226 hclge_fd_free_node(hdev, old_rule); 5227 break; 5228 case HCLGE_FD_TO_DEL: 5229 /* if new request is TO_DEL, and old rule is existent 5230 * 1) the state of old rule is TO_DEL, we need do nothing, 5231 * because we delete rule by location, other rule content 5232 * is unncessary. 5233 * 2) the state of old rule is ACTIVE, we need to change its 5234 * state to TO_DEL, so the rule will be deleted when periodic 5235 * task being scheduled. 5236 * 3) the state of old rule is TO_ADD, it means the rule hasn't 5237 * been added to hardware, so we just delete the rule node from 5238 * fd_rule_list directly. 5239 */ 5240 if (old_rule->state == HCLGE_FD_TO_ADD) { 5241 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5242 hclge_fd_free_node(hdev, old_rule); 5243 return; 5244 } 5245 old_rule->state = HCLGE_FD_TO_DEL; 5246 break; 5247 } 5248 } 5249 5250 static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist, 5251 u16 location, 5252 struct hclge_fd_rule **parent) 5253 { 5254 struct hclge_fd_rule *rule; 5255 struct hlist_node *node; 5256 5257 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 5258 if (rule->location == location) 5259 return rule; 5260 else if (rule->location > location) 5261 return NULL; 5262 /* record the parent node, use to keep the nodes in fd_rule_list 5263 * in ascend order. 5264 */ 5265 *parent = rule; 5266 } 5267 5268 return NULL; 5269 } 5270 5271 /* insert fd rule node in ascend order according to rule->location */ 5272 static void hclge_fd_insert_rule_node(struct hlist_head *hlist, 5273 struct hclge_fd_rule *rule, 5274 struct hclge_fd_rule *parent) 5275 { 5276 INIT_HLIST_NODE(&rule->rule_node); 5277 5278 if (parent) 5279 hlist_add_behind(&rule->rule_node, &parent->rule_node); 5280 else 5281 hlist_add_head(&rule->rule_node, hlist); 5282 } 5283 5284 static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev, 5285 struct hclge_fd_user_def_cfg *cfg) 5286 { 5287 struct hclge_fd_user_def_cfg_cmd *req; 5288 struct hclge_desc desc; 5289 u16 data = 0; 5290 int ret; 5291 5292 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false); 5293 5294 req = (struct hclge_fd_user_def_cfg_cmd *)desc.data; 5295 5296 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0); 5297 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5298 HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset); 5299 req->ol2_cfg = cpu_to_le16(data); 5300 5301 data = 0; 5302 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0); 5303 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5304 HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset); 5305 req->ol3_cfg = cpu_to_le16(data); 5306 5307 data = 0; 5308 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0); 5309 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5310 HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset); 5311 req->ol4_cfg = cpu_to_le16(data); 5312 5313 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5314 if (ret) 5315 dev_err(&hdev->pdev->dev, 5316 "failed to set fd user def data, ret= %d\n", ret); 5317 return ret; 5318 } 5319 5320 static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked) 5321 { 5322 int ret; 5323 5324 if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state)) 5325 return; 5326 5327 if (!locked) 5328 spin_lock_bh(&hdev->fd_rule_lock); 5329 5330 ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg); 5331 if (ret) 5332 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5333 5334 if (!locked) 5335 spin_unlock_bh(&hdev->fd_rule_lock); 5336 } 5337 5338 static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev, 5339 struct hclge_fd_rule *rule) 5340 { 5341 struct hlist_head *hlist = &hdev->fd_rule_list; 5342 struct hclge_fd_rule *fd_rule, *parent = NULL; 5343 struct hclge_fd_user_def_info *info, *old_info; 5344 struct hclge_fd_user_def_cfg *cfg; 5345 5346 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5347 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5348 return 0; 5349 5350 /* for valid layer is start from 1, so need minus 1 to get the cfg */ 5351 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5352 info = &rule->ep.user_def; 5353 5354 if (!cfg->ref_cnt || cfg->offset == info->offset) 5355 return 0; 5356 5357 if (cfg->ref_cnt > 1) 5358 goto error; 5359 5360 fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent); 5361 if (fd_rule) { 5362 old_info = &fd_rule->ep.user_def; 5363 if (info->layer == old_info->layer) 5364 return 0; 5365 } 5366 5367 error: 5368 dev_err(&hdev->pdev->dev, 5369 "No available offset for layer%d fd rule, each layer only support one user def offset.\n", 5370 info->layer + 1); 5371 return -ENOSPC; 5372 } 5373 5374 static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev, 5375 struct hclge_fd_rule *rule) 5376 { 5377 struct hclge_fd_user_def_cfg *cfg; 5378 5379 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5380 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5381 return; 5382 5383 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5384 if (!cfg->ref_cnt) { 5385 cfg->offset = rule->ep.user_def.offset; 5386 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5387 } 5388 cfg->ref_cnt++; 5389 } 5390 5391 static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev, 5392 struct hclge_fd_rule *rule) 5393 { 5394 struct hclge_fd_user_def_cfg *cfg; 5395 5396 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5397 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5398 return; 5399 5400 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5401 if (!cfg->ref_cnt) 5402 return; 5403 5404 cfg->ref_cnt--; 5405 if (!cfg->ref_cnt) { 5406 cfg->offset = 0; 5407 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5408 } 5409 } 5410 5411 static void hclge_update_fd_list(struct hclge_dev *hdev, 5412 enum HCLGE_FD_NODE_STATE state, u16 location, 5413 struct hclge_fd_rule *new_rule) 5414 { 5415 struct hlist_head *hlist = &hdev->fd_rule_list; 5416 struct hclge_fd_rule *fd_rule, *parent = NULL; 5417 5418 fd_rule = hclge_find_fd_rule(hlist, location, &parent); 5419 if (fd_rule) { 5420 hclge_fd_dec_user_def_refcnt(hdev, fd_rule); 5421 if (state == HCLGE_FD_ACTIVE) 5422 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5423 hclge_sync_fd_user_def_cfg(hdev, true); 5424 5425 hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state); 5426 return; 5427 } 5428 5429 /* it's unlikely to fail here, because we have checked the rule 5430 * exist before. 5431 */ 5432 if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) { 5433 dev_warn(&hdev->pdev->dev, 5434 "failed to delete fd rule %u, it's inexistent\n", 5435 location); 5436 return; 5437 } 5438 5439 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5440 hclge_sync_fd_user_def_cfg(hdev, true); 5441 5442 hclge_fd_insert_rule_node(hlist, new_rule, parent); 5443 hclge_fd_inc_rule_cnt(hdev, new_rule->location); 5444 5445 if (state == HCLGE_FD_TO_ADD) { 5446 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 5447 hclge_task_schedule(hdev, 0); 5448 } 5449 } 5450 5451 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode) 5452 { 5453 struct hclge_get_fd_mode_cmd *req; 5454 struct hclge_desc desc; 5455 int ret; 5456 5457 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true); 5458 5459 req = (struct hclge_get_fd_mode_cmd *)desc.data; 5460 5461 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5462 if (ret) { 5463 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret); 5464 return ret; 5465 } 5466 5467 *fd_mode = req->mode; 5468 5469 return ret; 5470 } 5471 5472 static int hclge_get_fd_allocation(struct hclge_dev *hdev, 5473 u32 *stage1_entry_num, 5474 u32 *stage2_entry_num, 5475 u16 *stage1_counter_num, 5476 u16 *stage2_counter_num) 5477 { 5478 struct hclge_get_fd_allocation_cmd *req; 5479 struct hclge_desc desc; 5480 int ret; 5481 5482 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true); 5483 5484 req = (struct hclge_get_fd_allocation_cmd *)desc.data; 5485 5486 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5487 if (ret) { 5488 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n", 5489 ret); 5490 return ret; 5491 } 5492 5493 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num); 5494 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num); 5495 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num); 5496 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num); 5497 5498 return ret; 5499 } 5500 5501 static int hclge_set_fd_key_config(struct hclge_dev *hdev, 5502 enum HCLGE_FD_STAGE stage_num) 5503 { 5504 struct hclge_set_fd_key_config_cmd *req; 5505 struct hclge_fd_key_cfg *stage; 5506 struct hclge_desc desc; 5507 int ret; 5508 5509 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false); 5510 5511 req = (struct hclge_set_fd_key_config_cmd *)desc.data; 5512 stage = &hdev->fd_cfg.key_cfg[stage_num]; 5513 req->stage = stage_num; 5514 req->key_select = stage->key_sel; 5515 req->inner_sipv6_word_en = stage->inner_sipv6_word_en; 5516 req->inner_dipv6_word_en = stage->inner_dipv6_word_en; 5517 req->outer_sipv6_word_en = stage->outer_sipv6_word_en; 5518 req->outer_dipv6_word_en = stage->outer_dipv6_word_en; 5519 req->tuple_mask = cpu_to_le32(~stage->tuple_active); 5520 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active); 5521 5522 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5523 if (ret) 5524 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret); 5525 5526 return ret; 5527 } 5528 5529 static void hclge_fd_disable_user_def(struct hclge_dev *hdev) 5530 { 5531 struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg; 5532 5533 spin_lock_bh(&hdev->fd_rule_lock); 5534 memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg)); 5535 spin_unlock_bh(&hdev->fd_rule_lock); 5536 5537 hclge_fd_set_user_def_cmd(hdev, cfg); 5538 } 5539 5540 static int hclge_init_fd_config(struct hclge_dev *hdev) 5541 { 5542 #define LOW_2_WORDS 0x03 5543 struct hclge_fd_key_cfg *key_cfg; 5544 int ret; 5545 5546 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 5547 return 0; 5548 5549 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode); 5550 if (ret) 5551 return ret; 5552 5553 switch (hdev->fd_cfg.fd_mode) { 5554 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1: 5555 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH; 5556 break; 5557 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1: 5558 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2; 5559 break; 5560 default: 5561 dev_err(&hdev->pdev->dev, 5562 "Unsupported flow director mode %u\n", 5563 hdev->fd_cfg.fd_mode); 5564 return -EOPNOTSUPP; 5565 } 5566 5567 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1]; 5568 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE; 5569 key_cfg->inner_sipv6_word_en = LOW_2_WORDS; 5570 key_cfg->inner_dipv6_word_en = LOW_2_WORDS; 5571 key_cfg->outer_sipv6_word_en = 0; 5572 key_cfg->outer_dipv6_word_en = 0; 5573 5574 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) | 5575 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) | 5576 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5577 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5578 5579 /* If use max 400bit key, we can support tuples for ether type */ 5580 if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 5581 key_cfg->tuple_active |= 5582 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC); 5583 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5584 key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 5585 } 5586 5587 /* roce_type is used to filter roce frames 5588 * dst_vport is used to specify the rule 5589 */ 5590 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT); 5591 5592 ret = hclge_get_fd_allocation(hdev, 5593 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1], 5594 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2], 5595 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1], 5596 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]); 5597 if (ret) 5598 return ret; 5599 5600 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1); 5601 } 5602 5603 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x, 5604 int loc, u8 *key, bool is_add) 5605 { 5606 struct hclge_fd_tcam_config_1_cmd *req1; 5607 struct hclge_fd_tcam_config_2_cmd *req2; 5608 struct hclge_fd_tcam_config_3_cmd *req3; 5609 struct hclge_desc desc[3]; 5610 int ret; 5611 5612 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false); 5613 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5614 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false); 5615 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5616 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false); 5617 5618 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 5619 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 5620 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 5621 5622 req1->stage = stage; 5623 req1->xy_sel = sel_x ? 1 : 0; 5624 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0); 5625 req1->index = cpu_to_le32(loc); 5626 req1->entry_vld = sel_x ? is_add : 0; 5627 5628 if (key) { 5629 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data)); 5630 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)], 5631 sizeof(req2->tcam_data)); 5632 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) + 5633 sizeof(req2->tcam_data)], sizeof(req3->tcam_data)); 5634 } 5635 5636 ret = hclge_cmd_send(&hdev->hw, desc, 3); 5637 if (ret) 5638 dev_err(&hdev->pdev->dev, 5639 "config tcam key fail, ret=%d\n", 5640 ret); 5641 5642 return ret; 5643 } 5644 5645 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc, 5646 struct hclge_fd_ad_data *action) 5647 { 5648 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 5649 struct hclge_fd_ad_config_cmd *req; 5650 struct hclge_desc desc; 5651 u64 ad_data = 0; 5652 int ret; 5653 5654 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false); 5655 5656 req = (struct hclge_fd_ad_config_cmd *)desc.data; 5657 req->index = cpu_to_le32(loc); 5658 req->stage = stage; 5659 5660 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B, 5661 action->write_rule_id_to_bd); 5662 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S, 5663 action->rule_id); 5664 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) { 5665 hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B, 5666 action->override_tc); 5667 hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M, 5668 HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size); 5669 } 5670 ad_data <<= 32; 5671 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet); 5672 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B, 5673 action->forward_to_direct_queue); 5674 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S, 5675 action->queue_id); 5676 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter); 5677 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M, 5678 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id); 5679 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage); 5680 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S, 5681 action->counter_id); 5682 5683 req->ad_data = cpu_to_le64(ad_data); 5684 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5685 if (ret) 5686 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret); 5687 5688 return ret; 5689 } 5690 5691 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y, 5692 struct hclge_fd_rule *rule) 5693 { 5694 int offset, moffset, ip_offset; 5695 enum HCLGE_FD_KEY_OPT key_opt; 5696 u16 tmp_x_s, tmp_y_s; 5697 u32 tmp_x_l, tmp_y_l; 5698 u8 *p = (u8 *)rule; 5699 int i; 5700 5701 if (rule->unused_tuple & BIT(tuple_bit)) 5702 return true; 5703 5704 key_opt = tuple_key_info[tuple_bit].key_opt; 5705 offset = tuple_key_info[tuple_bit].offset; 5706 moffset = tuple_key_info[tuple_bit].moffset; 5707 5708 switch (key_opt) { 5709 case KEY_OPT_U8: 5710 calc_x(*key_x, p[offset], p[moffset]); 5711 calc_y(*key_y, p[offset], p[moffset]); 5712 5713 return true; 5714 case KEY_OPT_LE16: 5715 calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5716 calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5717 *(__le16 *)key_x = cpu_to_le16(tmp_x_s); 5718 *(__le16 *)key_y = cpu_to_le16(tmp_y_s); 5719 5720 return true; 5721 case KEY_OPT_LE32: 5722 calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5723 calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5724 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5725 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5726 5727 return true; 5728 case KEY_OPT_MAC: 5729 for (i = 0; i < ETH_ALEN; i++) { 5730 calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i], 5731 p[moffset + i]); 5732 calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i], 5733 p[moffset + i]); 5734 } 5735 5736 return true; 5737 case KEY_OPT_IP: 5738 ip_offset = IPV4_INDEX * sizeof(u32); 5739 calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]), 5740 *(u32 *)(&p[moffset + ip_offset])); 5741 calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]), 5742 *(u32 *)(&p[moffset + ip_offset])); 5743 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5744 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5745 5746 return true; 5747 default: 5748 return false; 5749 } 5750 } 5751 5752 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 5753 u8 vf_id, u8 network_port_id) 5754 { 5755 u32 port_number = 0; 5756 5757 if (port_type == HOST_PORT) { 5758 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S, 5759 pf_id); 5760 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S, 5761 vf_id); 5762 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT); 5763 } else { 5764 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M, 5765 HCLGE_NETWORK_PORT_ID_S, network_port_id); 5766 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT); 5767 } 5768 5769 return port_number; 5770 } 5771 5772 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg, 5773 __le32 *key_x, __le32 *key_y, 5774 struct hclge_fd_rule *rule) 5775 { 5776 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number; 5777 u8 cur_pos = 0, tuple_size, shift_bits; 5778 unsigned int i; 5779 5780 for (i = 0; i < MAX_META_DATA; i++) { 5781 tuple_size = meta_data_key_info[i].key_length; 5782 tuple_bit = key_cfg->meta_data_active & BIT(i); 5783 5784 switch (tuple_bit) { 5785 case BIT(ROCE_TYPE): 5786 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET); 5787 cur_pos += tuple_size; 5788 break; 5789 case BIT(DST_VPORT): 5790 port_number = hclge_get_port_number(HOST_PORT, 0, 5791 rule->vf_id, 0); 5792 hnae3_set_field(meta_data, 5793 GENMASK(cur_pos + tuple_size, cur_pos), 5794 cur_pos, port_number); 5795 cur_pos += tuple_size; 5796 break; 5797 default: 5798 break; 5799 } 5800 } 5801 5802 calc_x(tmp_x, meta_data, 0xFFFFFFFF); 5803 calc_y(tmp_y, meta_data, 0xFFFFFFFF); 5804 shift_bits = sizeof(meta_data) * 8 - cur_pos; 5805 5806 *key_x = cpu_to_le32(tmp_x << shift_bits); 5807 *key_y = cpu_to_le32(tmp_y << shift_bits); 5808 } 5809 5810 /* A complete key is combined with meta data key and tuple key. 5811 * Meta data key is stored at the MSB region, and tuple key is stored at 5812 * the LSB region, unused bits will be filled 0. 5813 */ 5814 static int hclge_config_key(struct hclge_dev *hdev, u8 stage, 5815 struct hclge_fd_rule *rule) 5816 { 5817 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage]; 5818 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES]; 5819 u8 *cur_key_x, *cur_key_y; 5820 u8 meta_data_region; 5821 u8 tuple_size; 5822 int ret; 5823 u32 i; 5824 5825 memset(key_x, 0, sizeof(key_x)); 5826 memset(key_y, 0, sizeof(key_y)); 5827 cur_key_x = key_x; 5828 cur_key_y = key_y; 5829 5830 for (i = 0; i < MAX_TUPLE; i++) { 5831 bool tuple_valid; 5832 5833 tuple_size = tuple_key_info[i].key_length / 8; 5834 if (!(key_cfg->tuple_active & BIT(i))) 5835 continue; 5836 5837 tuple_valid = hclge_fd_convert_tuple(i, cur_key_x, 5838 cur_key_y, rule); 5839 if (tuple_valid) { 5840 cur_key_x += tuple_size; 5841 cur_key_y += tuple_size; 5842 } 5843 } 5844 5845 meta_data_region = hdev->fd_cfg.max_key_length / 8 - 5846 MAX_META_DATA_LENGTH / 8; 5847 5848 hclge_fd_convert_meta_data(key_cfg, 5849 (__le32 *)(key_x + meta_data_region), 5850 (__le32 *)(key_y + meta_data_region), 5851 rule); 5852 5853 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y, 5854 true); 5855 if (ret) { 5856 dev_err(&hdev->pdev->dev, 5857 "fd key_y config fail, loc=%u, ret=%d\n", 5858 rule->queue_id, ret); 5859 return ret; 5860 } 5861 5862 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x, 5863 true); 5864 if (ret) 5865 dev_err(&hdev->pdev->dev, 5866 "fd key_x config fail, loc=%u, ret=%d\n", 5867 rule->queue_id, ret); 5868 return ret; 5869 } 5870 5871 static int hclge_config_action(struct hclge_dev *hdev, u8 stage, 5872 struct hclge_fd_rule *rule) 5873 { 5874 struct hclge_vport *vport = hdev->vport; 5875 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5876 struct hclge_fd_ad_data ad_data; 5877 5878 memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data)); 5879 ad_data.ad_id = rule->location; 5880 5881 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 5882 ad_data.drop_packet = true; 5883 } else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) { 5884 ad_data.override_tc = true; 5885 ad_data.queue_id = 5886 kinfo->tc_info.tqp_offset[rule->cls_flower.tc]; 5887 ad_data.tc_size = 5888 ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]); 5889 } else { 5890 ad_data.forward_to_direct_queue = true; 5891 ad_data.queue_id = rule->queue_id; 5892 } 5893 5894 if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) { 5895 ad_data.use_counter = true; 5896 ad_data.counter_id = rule->vf_id % 5897 hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]; 5898 } else { 5899 ad_data.use_counter = false; 5900 ad_data.counter_id = 0; 5901 } 5902 5903 ad_data.use_next_stage = false; 5904 ad_data.next_input_key = 0; 5905 5906 ad_data.write_rule_id_to_bd = true; 5907 ad_data.rule_id = rule->location; 5908 5909 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data); 5910 } 5911 5912 static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec, 5913 u32 *unused_tuple) 5914 { 5915 if (!spec || !unused_tuple) 5916 return -EINVAL; 5917 5918 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5919 5920 if (!spec->ip4src) 5921 *unused_tuple |= BIT(INNER_SRC_IP); 5922 5923 if (!spec->ip4dst) 5924 *unused_tuple |= BIT(INNER_DST_IP); 5925 5926 if (!spec->psrc) 5927 *unused_tuple |= BIT(INNER_SRC_PORT); 5928 5929 if (!spec->pdst) 5930 *unused_tuple |= BIT(INNER_DST_PORT); 5931 5932 if (!spec->tos) 5933 *unused_tuple |= BIT(INNER_IP_TOS); 5934 5935 return 0; 5936 } 5937 5938 static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec, 5939 u32 *unused_tuple) 5940 { 5941 if (!spec || !unused_tuple) 5942 return -EINVAL; 5943 5944 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5945 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5946 5947 if (!spec->ip4src) 5948 *unused_tuple |= BIT(INNER_SRC_IP); 5949 5950 if (!spec->ip4dst) 5951 *unused_tuple |= BIT(INNER_DST_IP); 5952 5953 if (!spec->tos) 5954 *unused_tuple |= BIT(INNER_IP_TOS); 5955 5956 if (!spec->proto) 5957 *unused_tuple |= BIT(INNER_IP_PROTO); 5958 5959 if (spec->l4_4_bytes) 5960 return -EOPNOTSUPP; 5961 5962 if (spec->ip_ver != ETH_RX_NFC_IP4) 5963 return -EOPNOTSUPP; 5964 5965 return 0; 5966 } 5967 5968 static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec, 5969 u32 *unused_tuple) 5970 { 5971 if (!spec || !unused_tuple) 5972 return -EINVAL; 5973 5974 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5975 5976 /* check whether src/dst ip address used */ 5977 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5978 *unused_tuple |= BIT(INNER_SRC_IP); 5979 5980 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5981 *unused_tuple |= BIT(INNER_DST_IP); 5982 5983 if (!spec->psrc) 5984 *unused_tuple |= BIT(INNER_SRC_PORT); 5985 5986 if (!spec->pdst) 5987 *unused_tuple |= BIT(INNER_DST_PORT); 5988 5989 if (!spec->tclass) 5990 *unused_tuple |= BIT(INNER_IP_TOS); 5991 5992 return 0; 5993 } 5994 5995 static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec, 5996 u32 *unused_tuple) 5997 { 5998 if (!spec || !unused_tuple) 5999 return -EINVAL; 6000 6001 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 6002 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 6003 6004 /* check whether src/dst ip address used */ 6005 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 6006 *unused_tuple |= BIT(INNER_SRC_IP); 6007 6008 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 6009 *unused_tuple |= BIT(INNER_DST_IP); 6010 6011 if (!spec->l4_proto) 6012 *unused_tuple |= BIT(INNER_IP_PROTO); 6013 6014 if (!spec->tclass) 6015 *unused_tuple |= BIT(INNER_IP_TOS); 6016 6017 if (spec->l4_4_bytes) 6018 return -EOPNOTSUPP; 6019 6020 return 0; 6021 } 6022 6023 static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple) 6024 { 6025 if (!spec || !unused_tuple) 6026 return -EINVAL; 6027 6028 *unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 6029 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) | 6030 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO); 6031 6032 if (is_zero_ether_addr(spec->h_source)) 6033 *unused_tuple |= BIT(INNER_SRC_MAC); 6034 6035 if (is_zero_ether_addr(spec->h_dest)) 6036 *unused_tuple |= BIT(INNER_DST_MAC); 6037 6038 if (!spec->h_proto) 6039 *unused_tuple |= BIT(INNER_ETH_TYPE); 6040 6041 return 0; 6042 } 6043 6044 static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev, 6045 struct ethtool_rx_flow_spec *fs, 6046 u32 *unused_tuple) 6047 { 6048 if (fs->flow_type & FLOW_EXT) { 6049 if (fs->h_ext.vlan_etype) { 6050 dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n"); 6051 return -EOPNOTSUPP; 6052 } 6053 6054 if (!fs->h_ext.vlan_tci) 6055 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6056 6057 if (fs->m_ext.vlan_tci && 6058 be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) { 6059 dev_err(&hdev->pdev->dev, 6060 "failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n", 6061 ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1); 6062 return -EINVAL; 6063 } 6064 } else { 6065 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6066 } 6067 6068 if (fs->flow_type & FLOW_MAC_EXT) { 6069 if (hdev->fd_cfg.fd_mode != 6070 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6071 dev_err(&hdev->pdev->dev, 6072 "FLOW_MAC_EXT is not supported in current fd mode!\n"); 6073 return -EOPNOTSUPP; 6074 } 6075 6076 if (is_zero_ether_addr(fs->h_ext.h_dest)) 6077 *unused_tuple |= BIT(INNER_DST_MAC); 6078 else 6079 *unused_tuple &= ~BIT(INNER_DST_MAC); 6080 } 6081 6082 return 0; 6083 } 6084 6085 static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple, 6086 struct hclge_fd_user_def_info *info) 6087 { 6088 switch (flow_type) { 6089 case ETHER_FLOW: 6090 info->layer = HCLGE_FD_USER_DEF_L2; 6091 *unused_tuple &= ~BIT(INNER_L2_RSV); 6092 break; 6093 case IP_USER_FLOW: 6094 case IPV6_USER_FLOW: 6095 info->layer = HCLGE_FD_USER_DEF_L3; 6096 *unused_tuple &= ~BIT(INNER_L3_RSV); 6097 break; 6098 case TCP_V4_FLOW: 6099 case UDP_V4_FLOW: 6100 case TCP_V6_FLOW: 6101 case UDP_V6_FLOW: 6102 info->layer = HCLGE_FD_USER_DEF_L4; 6103 *unused_tuple &= ~BIT(INNER_L4_RSV); 6104 break; 6105 default: 6106 return -EOPNOTSUPP; 6107 } 6108 6109 return 0; 6110 } 6111 6112 static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs) 6113 { 6114 return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0; 6115 } 6116 6117 static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev, 6118 struct ethtool_rx_flow_spec *fs, 6119 u32 *unused_tuple, 6120 struct hclge_fd_user_def_info *info) 6121 { 6122 u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active; 6123 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6124 u16 data, offset, data_mask, offset_mask; 6125 int ret; 6126 6127 info->layer = HCLGE_FD_USER_DEF_NONE; 6128 *unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 6129 6130 if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs)) 6131 return 0; 6132 6133 /* user-def data from ethtool is 64 bit value, the bit0~15 is used 6134 * for data, and bit32~47 is used for offset. 6135 */ 6136 data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6137 data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6138 offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6139 offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6140 6141 if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) { 6142 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n"); 6143 return -EOPNOTSUPP; 6144 } 6145 6146 if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) { 6147 dev_err(&hdev->pdev->dev, 6148 "user-def offset[%u] should be no more than %u\n", 6149 offset, HCLGE_FD_MAX_USER_DEF_OFFSET); 6150 return -EINVAL; 6151 } 6152 6153 if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) { 6154 dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n"); 6155 return -EINVAL; 6156 } 6157 6158 ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info); 6159 if (ret) { 6160 dev_err(&hdev->pdev->dev, 6161 "unsupported flow type for user-def bytes, ret = %d\n", 6162 ret); 6163 return ret; 6164 } 6165 6166 info->data = data; 6167 info->data_mask = data_mask; 6168 info->offset = offset; 6169 6170 return 0; 6171 } 6172 6173 static int hclge_fd_check_spec(struct hclge_dev *hdev, 6174 struct ethtool_rx_flow_spec *fs, 6175 u32 *unused_tuple, 6176 struct hclge_fd_user_def_info *info) 6177 { 6178 u32 flow_type; 6179 int ret; 6180 6181 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 6182 dev_err(&hdev->pdev->dev, 6183 "failed to config fd rules, invalid rule location: %u, max is %u\n.", 6184 fs->location, 6185 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1); 6186 return -EINVAL; 6187 } 6188 6189 ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info); 6190 if (ret) 6191 return ret; 6192 6193 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6194 switch (flow_type) { 6195 case SCTP_V4_FLOW: 6196 case TCP_V4_FLOW: 6197 case UDP_V4_FLOW: 6198 ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec, 6199 unused_tuple); 6200 break; 6201 case IP_USER_FLOW: 6202 ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec, 6203 unused_tuple); 6204 break; 6205 case SCTP_V6_FLOW: 6206 case TCP_V6_FLOW: 6207 case UDP_V6_FLOW: 6208 ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec, 6209 unused_tuple); 6210 break; 6211 case IPV6_USER_FLOW: 6212 ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec, 6213 unused_tuple); 6214 break; 6215 case ETHER_FLOW: 6216 if (hdev->fd_cfg.fd_mode != 6217 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6218 dev_err(&hdev->pdev->dev, 6219 "ETHER_FLOW is not supported in current fd mode!\n"); 6220 return -EOPNOTSUPP; 6221 } 6222 6223 ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec, 6224 unused_tuple); 6225 break; 6226 default: 6227 dev_err(&hdev->pdev->dev, 6228 "unsupported protocol type, protocol type = %#x\n", 6229 flow_type); 6230 return -EOPNOTSUPP; 6231 } 6232 6233 if (ret) { 6234 dev_err(&hdev->pdev->dev, 6235 "failed to check flow union tuple, ret = %d\n", 6236 ret); 6237 return ret; 6238 } 6239 6240 return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple); 6241 } 6242 6243 static void hclge_fd_get_tcpip4_tuple(struct ethtool_rx_flow_spec *fs, 6244 struct hclge_fd_rule *rule, u8 ip_proto) 6245 { 6246 rule->tuples.src_ip[IPV4_INDEX] = 6247 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src); 6248 rule->tuples_mask.src_ip[IPV4_INDEX] = 6249 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src); 6250 6251 rule->tuples.dst_ip[IPV4_INDEX] = 6252 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst); 6253 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6254 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst); 6255 6256 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc); 6257 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc); 6258 6259 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst); 6260 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst); 6261 6262 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos; 6263 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos; 6264 6265 rule->tuples.ether_proto = ETH_P_IP; 6266 rule->tuples_mask.ether_proto = 0xFFFF; 6267 6268 rule->tuples.ip_proto = ip_proto; 6269 rule->tuples_mask.ip_proto = 0xFF; 6270 } 6271 6272 static void hclge_fd_get_ip4_tuple(struct ethtool_rx_flow_spec *fs, 6273 struct hclge_fd_rule *rule) 6274 { 6275 rule->tuples.src_ip[IPV4_INDEX] = 6276 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src); 6277 rule->tuples_mask.src_ip[IPV4_INDEX] = 6278 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src); 6279 6280 rule->tuples.dst_ip[IPV4_INDEX] = 6281 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst); 6282 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6283 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst); 6284 6285 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos; 6286 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos; 6287 6288 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto; 6289 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto; 6290 6291 rule->tuples.ether_proto = ETH_P_IP; 6292 rule->tuples_mask.ether_proto = 0xFFFF; 6293 } 6294 6295 static void hclge_fd_get_tcpip6_tuple(struct ethtool_rx_flow_spec *fs, 6296 struct hclge_fd_rule *rule, u8 ip_proto) 6297 { 6298 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.tcp_ip6_spec.ip6src, 6299 IPV6_SIZE); 6300 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.tcp_ip6_spec.ip6src, 6301 IPV6_SIZE); 6302 6303 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.tcp_ip6_spec.ip6dst, 6304 IPV6_SIZE); 6305 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.tcp_ip6_spec.ip6dst, 6306 IPV6_SIZE); 6307 6308 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc); 6309 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc); 6310 6311 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst); 6312 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst); 6313 6314 rule->tuples.ether_proto = ETH_P_IPV6; 6315 rule->tuples_mask.ether_proto = 0xFFFF; 6316 6317 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6318 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6319 6320 rule->tuples.ip_proto = ip_proto; 6321 rule->tuples_mask.ip_proto = 0xFF; 6322 } 6323 6324 static void hclge_fd_get_ip6_tuple(struct ethtool_rx_flow_spec *fs, 6325 struct hclge_fd_rule *rule) 6326 { 6327 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.usr_ip6_spec.ip6src, 6328 IPV6_SIZE); 6329 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.usr_ip6_spec.ip6src, 6330 IPV6_SIZE); 6331 6332 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.usr_ip6_spec.ip6dst, 6333 IPV6_SIZE); 6334 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.usr_ip6_spec.ip6dst, 6335 IPV6_SIZE); 6336 6337 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto; 6338 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto; 6339 6340 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6341 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6342 6343 rule->tuples.ether_proto = ETH_P_IPV6; 6344 rule->tuples_mask.ether_proto = 0xFFFF; 6345 } 6346 6347 static void hclge_fd_get_ether_tuple(struct ethtool_rx_flow_spec *fs, 6348 struct hclge_fd_rule *rule) 6349 { 6350 ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source); 6351 ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source); 6352 6353 ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest); 6354 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest); 6355 6356 rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto); 6357 rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto); 6358 } 6359 6360 static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info, 6361 struct hclge_fd_rule *rule) 6362 { 6363 switch (info->layer) { 6364 case HCLGE_FD_USER_DEF_L2: 6365 rule->tuples.l2_user_def = info->data; 6366 rule->tuples_mask.l2_user_def = info->data_mask; 6367 break; 6368 case HCLGE_FD_USER_DEF_L3: 6369 rule->tuples.l3_user_def = info->data; 6370 rule->tuples_mask.l3_user_def = info->data_mask; 6371 break; 6372 case HCLGE_FD_USER_DEF_L4: 6373 rule->tuples.l4_user_def = (u32)info->data << 16; 6374 rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16; 6375 break; 6376 default: 6377 break; 6378 } 6379 6380 rule->ep.user_def = *info; 6381 } 6382 6383 static int hclge_fd_get_tuple(struct ethtool_rx_flow_spec *fs, 6384 struct hclge_fd_rule *rule, 6385 struct hclge_fd_user_def_info *info) 6386 { 6387 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6388 6389 switch (flow_type) { 6390 case SCTP_V4_FLOW: 6391 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_SCTP); 6392 break; 6393 case TCP_V4_FLOW: 6394 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_TCP); 6395 break; 6396 case UDP_V4_FLOW: 6397 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_UDP); 6398 break; 6399 case IP_USER_FLOW: 6400 hclge_fd_get_ip4_tuple(fs, rule); 6401 break; 6402 case SCTP_V6_FLOW: 6403 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_SCTP); 6404 break; 6405 case TCP_V6_FLOW: 6406 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_TCP); 6407 break; 6408 case UDP_V6_FLOW: 6409 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_UDP); 6410 break; 6411 case IPV6_USER_FLOW: 6412 hclge_fd_get_ip6_tuple(fs, rule); 6413 break; 6414 case ETHER_FLOW: 6415 hclge_fd_get_ether_tuple(fs, rule); 6416 break; 6417 default: 6418 return -EOPNOTSUPP; 6419 } 6420 6421 if (fs->flow_type & FLOW_EXT) { 6422 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci); 6423 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci); 6424 hclge_fd_get_user_def_tuple(info, rule); 6425 } 6426 6427 if (fs->flow_type & FLOW_MAC_EXT) { 6428 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest); 6429 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest); 6430 } 6431 6432 return 0; 6433 } 6434 6435 static int hclge_fd_config_rule(struct hclge_dev *hdev, 6436 struct hclge_fd_rule *rule) 6437 { 6438 int ret; 6439 6440 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule); 6441 if (ret) 6442 return ret; 6443 6444 return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule); 6445 } 6446 6447 static int hclge_add_fd_entry_common(struct hclge_dev *hdev, 6448 struct hclge_fd_rule *rule) 6449 { 6450 int ret; 6451 6452 spin_lock_bh(&hdev->fd_rule_lock); 6453 6454 if (hdev->fd_active_type != rule->rule_type && 6455 (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6456 hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) { 6457 dev_err(&hdev->pdev->dev, 6458 "mode conflict(new type %d, active type %d), please delete existent rules first\n", 6459 rule->rule_type, hdev->fd_active_type); 6460 spin_unlock_bh(&hdev->fd_rule_lock); 6461 return -EINVAL; 6462 } 6463 6464 ret = hclge_fd_check_user_def_refcnt(hdev, rule); 6465 if (ret) 6466 goto out; 6467 6468 ret = hclge_clear_arfs_rules(hdev); 6469 if (ret) 6470 goto out; 6471 6472 ret = hclge_fd_config_rule(hdev, rule); 6473 if (ret) 6474 goto out; 6475 6476 rule->state = HCLGE_FD_ACTIVE; 6477 hdev->fd_active_type = rule->rule_type; 6478 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 6479 6480 out: 6481 spin_unlock_bh(&hdev->fd_rule_lock); 6482 return ret; 6483 } 6484 6485 static bool hclge_is_cls_flower_active(struct hnae3_handle *handle) 6486 { 6487 struct hclge_vport *vport = hclge_get_vport(handle); 6488 struct hclge_dev *hdev = vport->back; 6489 6490 return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE; 6491 } 6492 6493 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie, 6494 u16 *vport_id, u8 *action, u16 *queue_id) 6495 { 6496 struct hclge_vport *vport = hdev->vport; 6497 6498 if (ring_cookie == RX_CLS_FLOW_DISC) { 6499 *action = HCLGE_FD_ACTION_DROP_PACKET; 6500 } else { 6501 u32 ring = ethtool_get_flow_spec_ring(ring_cookie); 6502 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie); 6503 u16 tqps; 6504 6505 /* To keep consistent with user's configuration, minus 1 when 6506 * printing 'vf', because vf id from ethtool is added 1 for vf. 6507 */ 6508 if (vf > hdev->num_req_vfs) { 6509 dev_err(&hdev->pdev->dev, 6510 "Error: vf id (%u) should be less than %u\n", 6511 vf - 1U, hdev->num_req_vfs); 6512 return -EINVAL; 6513 } 6514 6515 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id; 6516 tqps = hdev->vport[vf].nic.kinfo.num_tqps; 6517 6518 if (ring >= tqps) { 6519 dev_err(&hdev->pdev->dev, 6520 "Error: queue id (%u) > max tqp num (%u)\n", 6521 ring, tqps - 1U); 6522 return -EINVAL; 6523 } 6524 6525 *action = HCLGE_FD_ACTION_SELECT_QUEUE; 6526 *queue_id = ring; 6527 } 6528 6529 return 0; 6530 } 6531 6532 static int hclge_add_fd_entry(struct hnae3_handle *handle, 6533 struct ethtool_rxnfc *cmd) 6534 { 6535 struct hclge_vport *vport = hclge_get_vport(handle); 6536 struct hclge_dev *hdev = vport->back; 6537 struct hclge_fd_user_def_info info; 6538 u16 dst_vport_id = 0, q_index = 0; 6539 struct ethtool_rx_flow_spec *fs; 6540 struct hclge_fd_rule *rule; 6541 u32 unused = 0; 6542 u8 action; 6543 int ret; 6544 6545 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 6546 dev_err(&hdev->pdev->dev, 6547 "flow table director is not supported\n"); 6548 return -EOPNOTSUPP; 6549 } 6550 6551 if (!hdev->fd_en) { 6552 dev_err(&hdev->pdev->dev, 6553 "please enable flow director first\n"); 6554 return -EOPNOTSUPP; 6555 } 6556 6557 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6558 6559 ret = hclge_fd_check_spec(hdev, fs, &unused, &info); 6560 if (ret) 6561 return ret; 6562 6563 ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id, 6564 &action, &q_index); 6565 if (ret) 6566 return ret; 6567 6568 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 6569 if (!rule) 6570 return -ENOMEM; 6571 6572 ret = hclge_fd_get_tuple(fs, rule, &info); 6573 if (ret) { 6574 kfree(rule); 6575 return ret; 6576 } 6577 6578 rule->flow_type = fs->flow_type; 6579 rule->location = fs->location; 6580 rule->unused_tuple = unused; 6581 rule->vf_id = dst_vport_id; 6582 rule->queue_id = q_index; 6583 rule->action = action; 6584 rule->rule_type = HCLGE_FD_EP_ACTIVE; 6585 6586 ret = hclge_add_fd_entry_common(hdev, rule); 6587 if (ret) 6588 kfree(rule); 6589 6590 return ret; 6591 } 6592 6593 static int hclge_del_fd_entry(struct hnae3_handle *handle, 6594 struct ethtool_rxnfc *cmd) 6595 { 6596 struct hclge_vport *vport = hclge_get_vport(handle); 6597 struct hclge_dev *hdev = vport->back; 6598 struct ethtool_rx_flow_spec *fs; 6599 int ret; 6600 6601 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6602 return -EOPNOTSUPP; 6603 6604 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6605 6606 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6607 return -EINVAL; 6608 6609 spin_lock_bh(&hdev->fd_rule_lock); 6610 if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6611 !test_bit(fs->location, hdev->fd_bmap)) { 6612 dev_err(&hdev->pdev->dev, 6613 "Delete fail, rule %u is inexistent\n", fs->location); 6614 spin_unlock_bh(&hdev->fd_rule_lock); 6615 return -ENOENT; 6616 } 6617 6618 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location, 6619 NULL, false); 6620 if (ret) 6621 goto out; 6622 6623 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL); 6624 6625 out: 6626 spin_unlock_bh(&hdev->fd_rule_lock); 6627 return ret; 6628 } 6629 6630 static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev, 6631 bool clear_list) 6632 { 6633 struct hclge_fd_rule *rule; 6634 struct hlist_node *node; 6635 u16 location; 6636 6637 spin_lock_bh(&hdev->fd_rule_lock); 6638 6639 for_each_set_bit(location, hdev->fd_bmap, 6640 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6641 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location, 6642 NULL, false); 6643 6644 if (clear_list) { 6645 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, 6646 rule_node) { 6647 hlist_del(&rule->rule_node); 6648 kfree(rule); 6649 } 6650 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 6651 hdev->hclge_fd_rule_num = 0; 6652 bitmap_zero(hdev->fd_bmap, 6653 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 6654 } 6655 6656 spin_unlock_bh(&hdev->fd_rule_lock); 6657 } 6658 6659 static void hclge_del_all_fd_entries(struct hclge_dev *hdev) 6660 { 6661 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6662 return; 6663 6664 hclge_clear_fd_rules_in_list(hdev, true); 6665 hclge_fd_disable_user_def(hdev); 6666 } 6667 6668 static int hclge_restore_fd_entries(struct hnae3_handle *handle) 6669 { 6670 struct hclge_vport *vport = hclge_get_vport(handle); 6671 struct hclge_dev *hdev = vport->back; 6672 struct hclge_fd_rule *rule; 6673 struct hlist_node *node; 6674 6675 /* Return ok here, because reset error handling will check this 6676 * return value. If error is returned here, the reset process will 6677 * fail. 6678 */ 6679 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6680 return 0; 6681 6682 /* if fd is disabled, should not restore it when reset */ 6683 if (!hdev->fd_en) 6684 return 0; 6685 6686 spin_lock_bh(&hdev->fd_rule_lock); 6687 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6688 if (rule->state == HCLGE_FD_ACTIVE) 6689 rule->state = HCLGE_FD_TO_ADD; 6690 } 6691 spin_unlock_bh(&hdev->fd_rule_lock); 6692 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 6693 6694 return 0; 6695 } 6696 6697 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle, 6698 struct ethtool_rxnfc *cmd) 6699 { 6700 struct hclge_vport *vport = hclge_get_vport(handle); 6701 struct hclge_dev *hdev = vport->back; 6702 6703 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev) || hclge_is_cls_flower_active(handle)) 6704 return -EOPNOTSUPP; 6705 6706 cmd->rule_cnt = hdev->hclge_fd_rule_num; 6707 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6708 6709 return 0; 6710 } 6711 6712 static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule, 6713 struct ethtool_tcpip4_spec *spec, 6714 struct ethtool_tcpip4_spec *spec_mask) 6715 { 6716 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6717 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6718 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6719 6720 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6721 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6722 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6723 6724 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6725 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6726 0 : cpu_to_be16(rule->tuples_mask.src_port); 6727 6728 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6729 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6730 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6731 6732 spec->tos = rule->tuples.ip_tos; 6733 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6734 0 : rule->tuples_mask.ip_tos; 6735 } 6736 6737 static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule, 6738 struct ethtool_usrip4_spec *spec, 6739 struct ethtool_usrip4_spec *spec_mask) 6740 { 6741 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6742 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6743 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6744 6745 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6746 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6747 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6748 6749 spec->tos = rule->tuples.ip_tos; 6750 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6751 0 : rule->tuples_mask.ip_tos; 6752 6753 spec->proto = rule->tuples.ip_proto; 6754 spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6755 0 : rule->tuples_mask.ip_proto; 6756 6757 spec->ip_ver = ETH_RX_NFC_IP4; 6758 } 6759 6760 static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule, 6761 struct ethtool_tcpip6_spec *spec, 6762 struct ethtool_tcpip6_spec *spec_mask) 6763 { 6764 cpu_to_be32_array(spec->ip6src, 6765 rule->tuples.src_ip, IPV6_SIZE); 6766 cpu_to_be32_array(spec->ip6dst, 6767 rule->tuples.dst_ip, IPV6_SIZE); 6768 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6769 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6770 else 6771 cpu_to_be32_array(spec_mask->ip6src, rule->tuples_mask.src_ip, 6772 IPV6_SIZE); 6773 6774 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6775 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6776 else 6777 cpu_to_be32_array(spec_mask->ip6dst, rule->tuples_mask.dst_ip, 6778 IPV6_SIZE); 6779 6780 spec->tclass = rule->tuples.ip_tos; 6781 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6782 0 : rule->tuples_mask.ip_tos; 6783 6784 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6785 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6786 0 : cpu_to_be16(rule->tuples_mask.src_port); 6787 6788 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6789 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6790 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6791 } 6792 6793 static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule, 6794 struct ethtool_usrip6_spec *spec, 6795 struct ethtool_usrip6_spec *spec_mask) 6796 { 6797 cpu_to_be32_array(spec->ip6src, rule->tuples.src_ip, IPV6_SIZE); 6798 cpu_to_be32_array(spec->ip6dst, rule->tuples.dst_ip, IPV6_SIZE); 6799 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6800 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6801 else 6802 cpu_to_be32_array(spec_mask->ip6src, 6803 rule->tuples_mask.src_ip, IPV6_SIZE); 6804 6805 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6806 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6807 else 6808 cpu_to_be32_array(spec_mask->ip6dst, 6809 rule->tuples_mask.dst_ip, IPV6_SIZE); 6810 6811 spec->tclass = rule->tuples.ip_tos; 6812 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6813 0 : rule->tuples_mask.ip_tos; 6814 6815 spec->l4_proto = rule->tuples.ip_proto; 6816 spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6817 0 : rule->tuples_mask.ip_proto; 6818 } 6819 6820 static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule, 6821 struct ethhdr *spec, 6822 struct ethhdr *spec_mask) 6823 { 6824 ether_addr_copy(spec->h_source, rule->tuples.src_mac); 6825 ether_addr_copy(spec->h_dest, rule->tuples.dst_mac); 6826 6827 if (rule->unused_tuple & BIT(INNER_SRC_MAC)) 6828 eth_zero_addr(spec_mask->h_source); 6829 else 6830 ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac); 6831 6832 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6833 eth_zero_addr(spec_mask->h_dest); 6834 else 6835 ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac); 6836 6837 spec->h_proto = cpu_to_be16(rule->tuples.ether_proto); 6838 spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ? 6839 0 : cpu_to_be16(rule->tuples_mask.ether_proto); 6840 } 6841 6842 static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs, 6843 struct hclge_fd_rule *rule) 6844 { 6845 if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) == 6846 HCLGE_FD_TUPLE_USER_DEF_TUPLES) { 6847 fs->h_ext.data[0] = 0; 6848 fs->h_ext.data[1] = 0; 6849 fs->m_ext.data[0] = 0; 6850 fs->m_ext.data[1] = 0; 6851 } else { 6852 fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset); 6853 fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data); 6854 fs->m_ext.data[0] = 6855 cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK); 6856 fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask); 6857 } 6858 } 6859 6860 static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs, 6861 struct hclge_fd_rule *rule) 6862 { 6863 if (fs->flow_type & FLOW_EXT) { 6864 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1); 6865 fs->m_ext.vlan_tci = 6866 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ? 6867 0 : cpu_to_be16(rule->tuples_mask.vlan_tag1); 6868 6869 hclge_fd_get_user_def_info(fs, rule); 6870 } 6871 6872 if (fs->flow_type & FLOW_MAC_EXT) { 6873 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac); 6874 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6875 eth_zero_addr(fs->m_u.ether_spec.h_dest); 6876 else 6877 ether_addr_copy(fs->m_u.ether_spec.h_dest, 6878 rule->tuples_mask.dst_mac); 6879 } 6880 } 6881 6882 static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev, 6883 u16 location) 6884 { 6885 struct hclge_fd_rule *rule = NULL; 6886 struct hlist_node *node2; 6887 6888 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) { 6889 if (rule->location == location) 6890 return rule; 6891 else if (rule->location > location) 6892 return NULL; 6893 } 6894 6895 return NULL; 6896 } 6897 6898 static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs, 6899 struct hclge_fd_rule *rule) 6900 { 6901 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 6902 fs->ring_cookie = RX_CLS_FLOW_DISC; 6903 } else { 6904 u64 vf_id; 6905 6906 fs->ring_cookie = rule->queue_id; 6907 vf_id = rule->vf_id; 6908 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 6909 fs->ring_cookie |= vf_id; 6910 } 6911 } 6912 6913 static int hclge_get_fd_rule_info(struct hnae3_handle *handle, 6914 struct ethtool_rxnfc *cmd) 6915 { 6916 struct hclge_vport *vport = hclge_get_vport(handle); 6917 struct hclge_fd_rule *rule = NULL; 6918 struct hclge_dev *hdev = vport->back; 6919 struct ethtool_rx_flow_spec *fs; 6920 6921 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6922 return -EOPNOTSUPP; 6923 6924 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6925 6926 spin_lock_bh(&hdev->fd_rule_lock); 6927 6928 rule = hclge_get_fd_rule(hdev, fs->location); 6929 if (!rule) { 6930 spin_unlock_bh(&hdev->fd_rule_lock); 6931 return -ENOENT; 6932 } 6933 6934 fs->flow_type = rule->flow_type; 6935 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 6936 case SCTP_V4_FLOW: 6937 case TCP_V4_FLOW: 6938 case UDP_V4_FLOW: 6939 hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec, 6940 &fs->m_u.tcp_ip4_spec); 6941 break; 6942 case IP_USER_FLOW: 6943 hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec, 6944 &fs->m_u.usr_ip4_spec); 6945 break; 6946 case SCTP_V6_FLOW: 6947 case TCP_V6_FLOW: 6948 case UDP_V6_FLOW: 6949 hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec, 6950 &fs->m_u.tcp_ip6_spec); 6951 break; 6952 case IPV6_USER_FLOW: 6953 hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec, 6954 &fs->m_u.usr_ip6_spec); 6955 break; 6956 /* The flow type of fd rule has been checked before adding in to rule 6957 * list. As other flow types have been handled, it must be ETHER_FLOW 6958 * for the default case 6959 */ 6960 default: 6961 hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec, 6962 &fs->m_u.ether_spec); 6963 break; 6964 } 6965 6966 hclge_fd_get_ext_info(fs, rule); 6967 6968 hclge_fd_get_ring_cookie(fs, rule); 6969 6970 spin_unlock_bh(&hdev->fd_rule_lock); 6971 6972 return 0; 6973 } 6974 6975 static int hclge_get_all_rules(struct hnae3_handle *handle, 6976 struct ethtool_rxnfc *cmd, u32 *rule_locs) 6977 { 6978 struct hclge_vport *vport = hclge_get_vport(handle); 6979 struct hclge_dev *hdev = vport->back; 6980 struct hclge_fd_rule *rule; 6981 struct hlist_node *node2; 6982 int cnt = 0; 6983 6984 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6985 return -EOPNOTSUPP; 6986 6987 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6988 6989 spin_lock_bh(&hdev->fd_rule_lock); 6990 hlist_for_each_entry_safe(rule, node2, 6991 &hdev->fd_rule_list, rule_node) { 6992 if (cnt == cmd->rule_cnt) { 6993 spin_unlock_bh(&hdev->fd_rule_lock); 6994 return -EMSGSIZE; 6995 } 6996 6997 if (rule->state == HCLGE_FD_TO_DEL) 6998 continue; 6999 7000 rule_locs[cnt] = rule->location; 7001 cnt++; 7002 } 7003 7004 spin_unlock_bh(&hdev->fd_rule_lock); 7005 7006 cmd->rule_cnt = cnt; 7007 7008 return 0; 7009 } 7010 7011 static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys, 7012 struct hclge_fd_rule_tuples *tuples) 7013 { 7014 #define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32 7015 #define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32 7016 7017 tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto); 7018 tuples->ip_proto = fkeys->basic.ip_proto; 7019 tuples->dst_port = be16_to_cpu(fkeys->ports.dst); 7020 7021 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 7022 tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src); 7023 tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst); 7024 } else { 7025 int i; 7026 7027 for (i = 0; i < IPV6_SIZE; i++) { 7028 tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]); 7029 tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]); 7030 } 7031 } 7032 } 7033 7034 /* traverse all rules, check whether an existed rule has the same tuples */ 7035 static struct hclge_fd_rule * 7036 hclge_fd_search_flow_keys(struct hclge_dev *hdev, 7037 const struct hclge_fd_rule_tuples *tuples) 7038 { 7039 struct hclge_fd_rule *rule = NULL; 7040 struct hlist_node *node; 7041 7042 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7043 if (!memcmp(tuples, &rule->tuples, sizeof(*tuples))) 7044 return rule; 7045 } 7046 7047 return NULL; 7048 } 7049 7050 static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples, 7051 struct hclge_fd_rule *rule) 7052 { 7053 rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 7054 BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) | 7055 BIT(INNER_SRC_PORT); 7056 rule->action = 0; 7057 rule->vf_id = 0; 7058 rule->rule_type = HCLGE_FD_ARFS_ACTIVE; 7059 rule->state = HCLGE_FD_TO_ADD; 7060 if (tuples->ether_proto == ETH_P_IP) { 7061 if (tuples->ip_proto == IPPROTO_TCP) 7062 rule->flow_type = TCP_V4_FLOW; 7063 else 7064 rule->flow_type = UDP_V4_FLOW; 7065 } else { 7066 if (tuples->ip_proto == IPPROTO_TCP) 7067 rule->flow_type = TCP_V6_FLOW; 7068 else 7069 rule->flow_type = UDP_V6_FLOW; 7070 } 7071 memcpy(&rule->tuples, tuples, sizeof(rule->tuples)); 7072 memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask)); 7073 } 7074 7075 static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id, 7076 u16 flow_id, struct flow_keys *fkeys) 7077 { 7078 struct hclge_vport *vport = hclge_get_vport(handle); 7079 struct hclge_fd_rule_tuples new_tuples = {}; 7080 struct hclge_dev *hdev = vport->back; 7081 struct hclge_fd_rule *rule; 7082 u16 bit_id; 7083 7084 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7085 return -EOPNOTSUPP; 7086 7087 /* when there is already fd rule existed add by user, 7088 * arfs should not work 7089 */ 7090 spin_lock_bh(&hdev->fd_rule_lock); 7091 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE && 7092 hdev->fd_active_type != HCLGE_FD_RULE_NONE) { 7093 spin_unlock_bh(&hdev->fd_rule_lock); 7094 return -EOPNOTSUPP; 7095 } 7096 7097 hclge_fd_get_flow_tuples(fkeys, &new_tuples); 7098 7099 /* check is there flow director filter existed for this flow, 7100 * if not, create a new filter for it; 7101 * if filter exist with different queue id, modify the filter; 7102 * if filter exist with same queue id, do nothing 7103 */ 7104 rule = hclge_fd_search_flow_keys(hdev, &new_tuples); 7105 if (!rule) { 7106 bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM); 7107 if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7108 spin_unlock_bh(&hdev->fd_rule_lock); 7109 return -ENOSPC; 7110 } 7111 7112 rule = kzalloc(sizeof(*rule), GFP_ATOMIC); 7113 if (!rule) { 7114 spin_unlock_bh(&hdev->fd_rule_lock); 7115 return -ENOMEM; 7116 } 7117 7118 rule->location = bit_id; 7119 rule->arfs.flow_id = flow_id; 7120 rule->queue_id = queue_id; 7121 hclge_fd_build_arfs_rule(&new_tuples, rule); 7122 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 7123 hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE; 7124 } else if (rule->queue_id != queue_id) { 7125 rule->queue_id = queue_id; 7126 rule->state = HCLGE_FD_TO_ADD; 7127 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7128 hclge_task_schedule(hdev, 0); 7129 } 7130 spin_unlock_bh(&hdev->fd_rule_lock); 7131 return rule->location; 7132 } 7133 7134 static void hclge_rfs_filter_expire(struct hclge_dev *hdev) 7135 { 7136 #ifdef CONFIG_RFS_ACCEL 7137 struct hnae3_handle *handle = &hdev->vport[0].nic; 7138 struct hclge_fd_rule *rule; 7139 struct hlist_node *node; 7140 7141 spin_lock_bh(&hdev->fd_rule_lock); 7142 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) { 7143 spin_unlock_bh(&hdev->fd_rule_lock); 7144 return; 7145 } 7146 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7147 if (rule->state != HCLGE_FD_ACTIVE) 7148 continue; 7149 if (rps_may_expire_flow(handle->netdev, rule->queue_id, 7150 rule->arfs.flow_id, rule->location)) { 7151 rule->state = HCLGE_FD_TO_DEL; 7152 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7153 } 7154 } 7155 spin_unlock_bh(&hdev->fd_rule_lock); 7156 #endif 7157 } 7158 7159 /* make sure being called after lock up with fd_rule_lock */ 7160 static int hclge_clear_arfs_rules(struct hclge_dev *hdev) 7161 { 7162 #ifdef CONFIG_RFS_ACCEL 7163 struct hclge_fd_rule *rule; 7164 struct hlist_node *node; 7165 int ret; 7166 7167 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) 7168 return 0; 7169 7170 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7171 switch (rule->state) { 7172 case HCLGE_FD_TO_DEL: 7173 case HCLGE_FD_ACTIVE: 7174 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7175 rule->location, NULL, false); 7176 if (ret) 7177 return ret; 7178 fallthrough; 7179 case HCLGE_FD_TO_ADD: 7180 hclge_fd_dec_rule_cnt(hdev, rule->location); 7181 hlist_del(&rule->rule_node); 7182 kfree(rule); 7183 break; 7184 default: 7185 break; 7186 } 7187 } 7188 hclge_sync_fd_state(hdev); 7189 7190 #endif 7191 return 0; 7192 } 7193 7194 static void hclge_get_cls_key_basic(const struct flow_rule *flow, 7195 struct hclge_fd_rule *rule) 7196 { 7197 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) { 7198 struct flow_match_basic match; 7199 u16 ethtype_key, ethtype_mask; 7200 7201 flow_rule_match_basic(flow, &match); 7202 ethtype_key = ntohs(match.key->n_proto); 7203 ethtype_mask = ntohs(match.mask->n_proto); 7204 7205 if (ethtype_key == ETH_P_ALL) { 7206 ethtype_key = 0; 7207 ethtype_mask = 0; 7208 } 7209 rule->tuples.ether_proto = ethtype_key; 7210 rule->tuples_mask.ether_proto = ethtype_mask; 7211 rule->tuples.ip_proto = match.key->ip_proto; 7212 rule->tuples_mask.ip_proto = match.mask->ip_proto; 7213 } else { 7214 rule->unused_tuple |= BIT(INNER_IP_PROTO); 7215 rule->unused_tuple |= BIT(INNER_ETH_TYPE); 7216 } 7217 } 7218 7219 static void hclge_get_cls_key_mac(const struct flow_rule *flow, 7220 struct hclge_fd_rule *rule) 7221 { 7222 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 7223 struct flow_match_eth_addrs match; 7224 7225 flow_rule_match_eth_addrs(flow, &match); 7226 ether_addr_copy(rule->tuples.dst_mac, match.key->dst); 7227 ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst); 7228 ether_addr_copy(rule->tuples.src_mac, match.key->src); 7229 ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src); 7230 } else { 7231 rule->unused_tuple |= BIT(INNER_DST_MAC); 7232 rule->unused_tuple |= BIT(INNER_SRC_MAC); 7233 } 7234 } 7235 7236 static void hclge_get_cls_key_vlan(const struct flow_rule *flow, 7237 struct hclge_fd_rule *rule) 7238 { 7239 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) { 7240 struct flow_match_vlan match; 7241 7242 flow_rule_match_vlan(flow, &match); 7243 rule->tuples.vlan_tag1 = match.key->vlan_id | 7244 (match.key->vlan_priority << VLAN_PRIO_SHIFT); 7245 rule->tuples_mask.vlan_tag1 = match.mask->vlan_id | 7246 (match.mask->vlan_priority << VLAN_PRIO_SHIFT); 7247 } else { 7248 rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST); 7249 } 7250 } 7251 7252 static void hclge_get_cls_key_ip(const struct flow_rule *flow, 7253 struct hclge_fd_rule *rule) 7254 { 7255 u16 addr_type = 0; 7256 7257 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) { 7258 struct flow_match_control match; 7259 7260 flow_rule_match_control(flow, &match); 7261 addr_type = match.key->addr_type; 7262 } 7263 7264 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { 7265 struct flow_match_ipv4_addrs match; 7266 7267 flow_rule_match_ipv4_addrs(flow, &match); 7268 rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src); 7269 rule->tuples_mask.src_ip[IPV4_INDEX] = 7270 be32_to_cpu(match.mask->src); 7271 rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst); 7272 rule->tuples_mask.dst_ip[IPV4_INDEX] = 7273 be32_to_cpu(match.mask->dst); 7274 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { 7275 struct flow_match_ipv6_addrs match; 7276 7277 flow_rule_match_ipv6_addrs(flow, &match); 7278 be32_to_cpu_array(rule->tuples.src_ip, match.key->src.s6_addr32, 7279 IPV6_SIZE); 7280 be32_to_cpu_array(rule->tuples_mask.src_ip, 7281 match.mask->src.s6_addr32, IPV6_SIZE); 7282 be32_to_cpu_array(rule->tuples.dst_ip, match.key->dst.s6_addr32, 7283 IPV6_SIZE); 7284 be32_to_cpu_array(rule->tuples_mask.dst_ip, 7285 match.mask->dst.s6_addr32, IPV6_SIZE); 7286 } else { 7287 rule->unused_tuple |= BIT(INNER_SRC_IP); 7288 rule->unused_tuple |= BIT(INNER_DST_IP); 7289 } 7290 } 7291 7292 static void hclge_get_cls_key_port(const struct flow_rule *flow, 7293 struct hclge_fd_rule *rule) 7294 { 7295 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) { 7296 struct flow_match_ports match; 7297 7298 flow_rule_match_ports(flow, &match); 7299 7300 rule->tuples.src_port = be16_to_cpu(match.key->src); 7301 rule->tuples_mask.src_port = be16_to_cpu(match.mask->src); 7302 rule->tuples.dst_port = be16_to_cpu(match.key->dst); 7303 rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst); 7304 } else { 7305 rule->unused_tuple |= BIT(INNER_SRC_PORT); 7306 rule->unused_tuple |= BIT(INNER_DST_PORT); 7307 } 7308 } 7309 7310 static int hclge_parse_cls_flower(struct hclge_dev *hdev, 7311 struct flow_cls_offload *cls_flower, 7312 struct hclge_fd_rule *rule) 7313 { 7314 struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower); 7315 struct flow_dissector *dissector = flow->match.dissector; 7316 7317 if (dissector->used_keys & 7318 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | 7319 BIT(FLOW_DISSECTOR_KEY_BASIC) | 7320 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 7321 BIT(FLOW_DISSECTOR_KEY_VLAN) | 7322 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | 7323 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | 7324 BIT(FLOW_DISSECTOR_KEY_PORTS))) { 7325 dev_err(&hdev->pdev->dev, "unsupported key set: %#x\n", 7326 dissector->used_keys); 7327 return -EOPNOTSUPP; 7328 } 7329 7330 hclge_get_cls_key_basic(flow, rule); 7331 hclge_get_cls_key_mac(flow, rule); 7332 hclge_get_cls_key_vlan(flow, rule); 7333 hclge_get_cls_key_ip(flow, rule); 7334 hclge_get_cls_key_port(flow, rule); 7335 7336 return 0; 7337 } 7338 7339 static int hclge_check_cls_flower(struct hclge_dev *hdev, 7340 struct flow_cls_offload *cls_flower, int tc) 7341 { 7342 u32 prio = cls_flower->common.prio; 7343 7344 if (tc < 0 || tc > hdev->tc_max) { 7345 dev_err(&hdev->pdev->dev, "invalid traffic class\n"); 7346 return -EINVAL; 7347 } 7348 7349 if (prio == 0 || 7350 prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7351 dev_err(&hdev->pdev->dev, 7352 "prio %u should be in range[1, %u]\n", 7353 prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 7354 return -EINVAL; 7355 } 7356 7357 if (test_bit(prio - 1, hdev->fd_bmap)) { 7358 dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio); 7359 return -EINVAL; 7360 } 7361 return 0; 7362 } 7363 7364 static int hclge_add_cls_flower(struct hnae3_handle *handle, 7365 struct flow_cls_offload *cls_flower, 7366 int tc) 7367 { 7368 struct hclge_vport *vport = hclge_get_vport(handle); 7369 struct hclge_dev *hdev = vport->back; 7370 struct hclge_fd_rule *rule; 7371 int ret; 7372 7373 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 7374 dev_err(&hdev->pdev->dev, 7375 "cls flower is not supported\n"); 7376 return -EOPNOTSUPP; 7377 } 7378 7379 ret = hclge_check_cls_flower(hdev, cls_flower, tc); 7380 if (ret) { 7381 dev_err(&hdev->pdev->dev, 7382 "failed to check cls flower params, ret = %d\n", ret); 7383 return ret; 7384 } 7385 7386 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 7387 if (!rule) 7388 return -ENOMEM; 7389 7390 ret = hclge_parse_cls_flower(hdev, cls_flower, rule); 7391 if (ret) { 7392 kfree(rule); 7393 return ret; 7394 } 7395 7396 rule->action = HCLGE_FD_ACTION_SELECT_TC; 7397 rule->cls_flower.tc = tc; 7398 rule->location = cls_flower->common.prio - 1; 7399 rule->vf_id = 0; 7400 rule->cls_flower.cookie = cls_flower->cookie; 7401 rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE; 7402 7403 ret = hclge_add_fd_entry_common(hdev, rule); 7404 if (ret) 7405 kfree(rule); 7406 7407 return ret; 7408 } 7409 7410 static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev, 7411 unsigned long cookie) 7412 { 7413 struct hclge_fd_rule *rule; 7414 struct hlist_node *node; 7415 7416 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7417 if (rule->cls_flower.cookie == cookie) 7418 return rule; 7419 } 7420 7421 return NULL; 7422 } 7423 7424 static int hclge_del_cls_flower(struct hnae3_handle *handle, 7425 struct flow_cls_offload *cls_flower) 7426 { 7427 struct hclge_vport *vport = hclge_get_vport(handle); 7428 struct hclge_dev *hdev = vport->back; 7429 struct hclge_fd_rule *rule; 7430 int ret; 7431 7432 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7433 return -EOPNOTSUPP; 7434 7435 spin_lock_bh(&hdev->fd_rule_lock); 7436 7437 rule = hclge_find_cls_flower(hdev, cls_flower->cookie); 7438 if (!rule) { 7439 spin_unlock_bh(&hdev->fd_rule_lock); 7440 return -EINVAL; 7441 } 7442 7443 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location, 7444 NULL, false); 7445 if (ret) { 7446 spin_unlock_bh(&hdev->fd_rule_lock); 7447 return ret; 7448 } 7449 7450 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL); 7451 spin_unlock_bh(&hdev->fd_rule_lock); 7452 7453 return 0; 7454 } 7455 7456 static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist) 7457 { 7458 struct hclge_fd_rule *rule; 7459 struct hlist_node *node; 7460 int ret = 0; 7461 7462 if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state)) 7463 return; 7464 7465 spin_lock_bh(&hdev->fd_rule_lock); 7466 7467 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 7468 switch (rule->state) { 7469 case HCLGE_FD_TO_ADD: 7470 ret = hclge_fd_config_rule(hdev, rule); 7471 if (ret) 7472 goto out; 7473 rule->state = HCLGE_FD_ACTIVE; 7474 break; 7475 case HCLGE_FD_TO_DEL: 7476 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7477 rule->location, NULL, false); 7478 if (ret) 7479 goto out; 7480 hclge_fd_dec_rule_cnt(hdev, rule->location); 7481 hclge_fd_free_node(hdev, rule); 7482 break; 7483 default: 7484 break; 7485 } 7486 } 7487 7488 out: 7489 if (ret) 7490 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7491 7492 spin_unlock_bh(&hdev->fd_rule_lock); 7493 } 7494 7495 static void hclge_sync_fd_table(struct hclge_dev *hdev) 7496 { 7497 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7498 return; 7499 7500 if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) { 7501 bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE; 7502 7503 hclge_clear_fd_rules_in_list(hdev, clear_list); 7504 } 7505 7506 hclge_sync_fd_user_def_cfg(hdev, false); 7507 7508 hclge_sync_fd_list(hdev, &hdev->fd_rule_list); 7509 } 7510 7511 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle) 7512 { 7513 struct hclge_vport *vport = hclge_get_vport(handle); 7514 struct hclge_dev *hdev = vport->back; 7515 7516 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) || 7517 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING); 7518 } 7519 7520 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle) 7521 { 7522 struct hclge_vport *vport = hclge_get_vport(handle); 7523 struct hclge_dev *hdev = vport->back; 7524 7525 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 7526 } 7527 7528 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle) 7529 { 7530 struct hclge_vport *vport = hclge_get_vport(handle); 7531 struct hclge_dev *hdev = vport->back; 7532 7533 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 7534 } 7535 7536 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle) 7537 { 7538 struct hclge_vport *vport = hclge_get_vport(handle); 7539 struct hclge_dev *hdev = vport->back; 7540 7541 return hdev->rst_stats.hw_reset_done_cnt; 7542 } 7543 7544 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable) 7545 { 7546 struct hclge_vport *vport = hclge_get_vport(handle); 7547 struct hclge_dev *hdev = vport->back; 7548 7549 hdev->fd_en = enable; 7550 7551 if (!enable) 7552 set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state); 7553 else 7554 hclge_restore_fd_entries(handle); 7555 7556 hclge_task_schedule(hdev, 0); 7557 } 7558 7559 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 7560 { 7561 struct hclge_desc desc; 7562 struct hclge_config_mac_mode_cmd *req = 7563 (struct hclge_config_mac_mode_cmd *)desc.data; 7564 u32 loop_en = 0; 7565 int ret; 7566 7567 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 7568 7569 if (enable) { 7570 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U); 7571 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U); 7572 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U); 7573 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U); 7574 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U); 7575 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U); 7576 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U); 7577 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U); 7578 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U); 7579 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U); 7580 } 7581 7582 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7583 7584 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7585 if (ret) 7586 dev_err(&hdev->pdev->dev, 7587 "mac enable fail, ret =%d.\n", ret); 7588 } 7589 7590 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid, 7591 u8 switch_param, u8 param_mask) 7592 { 7593 struct hclge_mac_vlan_switch_cmd *req; 7594 struct hclge_desc desc; 7595 u32 func_id; 7596 int ret; 7597 7598 func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0); 7599 req = (struct hclge_mac_vlan_switch_cmd *)desc.data; 7600 7601 /* read current config parameter */ 7602 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM, 7603 true); 7604 req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL; 7605 req->func_id = cpu_to_le32(func_id); 7606 7607 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7608 if (ret) { 7609 dev_err(&hdev->pdev->dev, 7610 "read mac vlan switch parameter fail, ret = %d\n", ret); 7611 return ret; 7612 } 7613 7614 /* modify and write new config parameter */ 7615 hclge_comm_cmd_reuse_desc(&desc, false); 7616 req->switch_param = (req->switch_param & param_mask) | switch_param; 7617 req->param_mask = param_mask; 7618 7619 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7620 if (ret) 7621 dev_err(&hdev->pdev->dev, 7622 "set mac vlan switch parameter fail, ret = %d\n", ret); 7623 return ret; 7624 } 7625 7626 static void hclge_phy_link_status_wait(struct hclge_dev *hdev, 7627 int link_ret) 7628 { 7629 #define HCLGE_PHY_LINK_STATUS_NUM 200 7630 7631 struct phy_device *phydev = hdev->hw.mac.phydev; 7632 int i = 0; 7633 int ret; 7634 7635 do { 7636 ret = phy_read_status(phydev); 7637 if (ret) { 7638 dev_err(&hdev->pdev->dev, 7639 "phy update link status fail, ret = %d\n", ret); 7640 return; 7641 } 7642 7643 if (phydev->link == link_ret) 7644 break; 7645 7646 msleep(HCLGE_LINK_STATUS_MS); 7647 } while (++i < HCLGE_PHY_LINK_STATUS_NUM); 7648 } 7649 7650 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret) 7651 { 7652 #define HCLGE_MAC_LINK_STATUS_NUM 100 7653 7654 int link_status; 7655 int i = 0; 7656 int ret; 7657 7658 do { 7659 ret = hclge_get_mac_link_status(hdev, &link_status); 7660 if (ret) 7661 return ret; 7662 if (link_status == link_ret) 7663 return 0; 7664 7665 msleep(HCLGE_LINK_STATUS_MS); 7666 } while (++i < HCLGE_MAC_LINK_STATUS_NUM); 7667 return -EBUSY; 7668 } 7669 7670 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en, 7671 bool is_phy) 7672 { 7673 int link_ret; 7674 7675 link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 7676 7677 if (is_phy) 7678 hclge_phy_link_status_wait(hdev, link_ret); 7679 7680 return hclge_mac_link_status_wait(hdev, link_ret); 7681 } 7682 7683 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) 7684 { 7685 struct hclge_config_mac_mode_cmd *req; 7686 struct hclge_desc desc; 7687 u32 loop_en; 7688 int ret; 7689 7690 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 7691 /* 1 Read out the MAC mode config at first */ 7692 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 7693 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7694 if (ret) { 7695 dev_err(&hdev->pdev->dev, 7696 "mac loopback get fail, ret =%d.\n", ret); 7697 return ret; 7698 } 7699 7700 /* 2 Then setup the loopback flag */ 7701 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 7702 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 7703 7704 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7705 7706 /* 3 Config mac work mode with loopback flag 7707 * and its original configure parameters 7708 */ 7709 hclge_comm_cmd_reuse_desc(&desc, false); 7710 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7711 if (ret) 7712 dev_err(&hdev->pdev->dev, 7713 "mac loopback set fail, ret =%d.\n", ret); 7714 return ret; 7715 } 7716 7717 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en, 7718 enum hnae3_loop loop_mode) 7719 { 7720 struct hclge_common_lb_cmd *req; 7721 struct hclge_desc desc; 7722 u8 loop_mode_b; 7723 int ret; 7724 7725 req = (struct hclge_common_lb_cmd *)desc.data; 7726 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false); 7727 7728 switch (loop_mode) { 7729 case HNAE3_LOOP_SERIAL_SERDES: 7730 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 7731 break; 7732 case HNAE3_LOOP_PARALLEL_SERDES: 7733 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B; 7734 break; 7735 case HNAE3_LOOP_PHY: 7736 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B; 7737 break; 7738 default: 7739 dev_err(&hdev->pdev->dev, 7740 "unsupported loopback mode %d\n", loop_mode); 7741 return -ENOTSUPP; 7742 } 7743 7744 req->mask = loop_mode_b; 7745 if (en) 7746 req->enable = loop_mode_b; 7747 7748 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7749 if (ret) 7750 dev_err(&hdev->pdev->dev, 7751 "failed to send loopback cmd, loop_mode = %d, ret = %d\n", 7752 loop_mode, ret); 7753 7754 return ret; 7755 } 7756 7757 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev) 7758 { 7759 #define HCLGE_COMMON_LB_RETRY_MS 10 7760 #define HCLGE_COMMON_LB_RETRY_NUM 100 7761 7762 struct hclge_common_lb_cmd *req; 7763 struct hclge_desc desc; 7764 u32 i = 0; 7765 int ret; 7766 7767 req = (struct hclge_common_lb_cmd *)desc.data; 7768 7769 do { 7770 msleep(HCLGE_COMMON_LB_RETRY_MS); 7771 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, 7772 true); 7773 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7774 if (ret) { 7775 dev_err(&hdev->pdev->dev, 7776 "failed to get loopback done status, ret = %d\n", 7777 ret); 7778 return ret; 7779 } 7780 } while (++i < HCLGE_COMMON_LB_RETRY_NUM && 7781 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B)); 7782 7783 if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) { 7784 dev_err(&hdev->pdev->dev, "wait loopback timeout\n"); 7785 return -EBUSY; 7786 } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) { 7787 dev_err(&hdev->pdev->dev, "failed to do loopback test\n"); 7788 return -EIO; 7789 } 7790 7791 return 0; 7792 } 7793 7794 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en, 7795 enum hnae3_loop loop_mode) 7796 { 7797 int ret; 7798 7799 ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode); 7800 if (ret) 7801 return ret; 7802 7803 return hclge_cfg_common_loopback_wait(hdev); 7804 } 7805 7806 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en, 7807 enum hnae3_loop loop_mode) 7808 { 7809 int ret; 7810 7811 ret = hclge_cfg_common_loopback(hdev, en, loop_mode); 7812 if (ret) 7813 return ret; 7814 7815 hclge_cfg_mac_mode(hdev, en); 7816 7817 ret = hclge_mac_phy_link_status_wait(hdev, en, false); 7818 if (ret) 7819 dev_err(&hdev->pdev->dev, 7820 "serdes loopback config mac mode timeout\n"); 7821 7822 return ret; 7823 } 7824 7825 static int hclge_enable_phy_loopback(struct hclge_dev *hdev, 7826 struct phy_device *phydev) 7827 { 7828 int ret; 7829 7830 if (!phydev->suspended) { 7831 ret = phy_suspend(phydev); 7832 if (ret) 7833 return ret; 7834 } 7835 7836 ret = phy_resume(phydev); 7837 if (ret) 7838 return ret; 7839 7840 return phy_loopback(phydev, true); 7841 } 7842 7843 static int hclge_disable_phy_loopback(struct hclge_dev *hdev, 7844 struct phy_device *phydev) 7845 { 7846 int ret; 7847 7848 ret = phy_loopback(phydev, false); 7849 if (ret) 7850 return ret; 7851 7852 return phy_suspend(phydev); 7853 } 7854 7855 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en) 7856 { 7857 struct phy_device *phydev = hdev->hw.mac.phydev; 7858 int ret; 7859 7860 if (!phydev) { 7861 if (hnae3_dev_phy_imp_supported(hdev)) 7862 return hclge_set_common_loopback(hdev, en, 7863 HNAE3_LOOP_PHY); 7864 return -ENOTSUPP; 7865 } 7866 7867 if (en) 7868 ret = hclge_enable_phy_loopback(hdev, phydev); 7869 else 7870 ret = hclge_disable_phy_loopback(hdev, phydev); 7871 if (ret) { 7872 dev_err(&hdev->pdev->dev, 7873 "set phy loopback fail, ret = %d\n", ret); 7874 return ret; 7875 } 7876 7877 hclge_cfg_mac_mode(hdev, en); 7878 7879 ret = hclge_mac_phy_link_status_wait(hdev, en, true); 7880 if (ret) 7881 dev_err(&hdev->pdev->dev, 7882 "phy loopback config mac mode timeout\n"); 7883 7884 return ret; 7885 } 7886 7887 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id, 7888 u16 stream_id, bool enable) 7889 { 7890 struct hclge_desc desc; 7891 struct hclge_cfg_com_tqp_queue_cmd *req = 7892 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 7893 7894 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 7895 req->tqp_id = cpu_to_le16(tqp_id); 7896 req->stream_id = cpu_to_le16(stream_id); 7897 if (enable) 7898 req->enable |= 1U << HCLGE_TQP_ENABLE_B; 7899 7900 return hclge_cmd_send(&hdev->hw, &desc, 1); 7901 } 7902 7903 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable) 7904 { 7905 struct hclge_vport *vport = hclge_get_vport(handle); 7906 struct hclge_dev *hdev = vport->back; 7907 int ret; 7908 u16 i; 7909 7910 for (i = 0; i < handle->kinfo.num_tqps; i++) { 7911 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable); 7912 if (ret) 7913 return ret; 7914 } 7915 return 0; 7916 } 7917 7918 static int hclge_set_loopback(struct hnae3_handle *handle, 7919 enum hnae3_loop loop_mode, bool en) 7920 { 7921 struct hclge_vport *vport = hclge_get_vport(handle); 7922 struct hclge_dev *hdev = vport->back; 7923 int ret = 0; 7924 7925 /* Loopback can be enabled in three places: SSU, MAC, and serdes. By 7926 * default, SSU loopback is enabled, so if the SMAC and the DMAC are 7927 * the same, the packets are looped back in the SSU. If SSU loopback 7928 * is disabled, packets can reach MAC even if SMAC is the same as DMAC. 7929 */ 7930 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 7931 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B); 7932 7933 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param, 7934 HCLGE_SWITCH_ALW_LPBK_MASK); 7935 if (ret) 7936 return ret; 7937 } 7938 7939 switch (loop_mode) { 7940 case HNAE3_LOOP_APP: 7941 ret = hclge_set_app_loopback(hdev, en); 7942 break; 7943 case HNAE3_LOOP_SERIAL_SERDES: 7944 case HNAE3_LOOP_PARALLEL_SERDES: 7945 ret = hclge_set_common_loopback(hdev, en, loop_mode); 7946 break; 7947 case HNAE3_LOOP_PHY: 7948 ret = hclge_set_phy_loopback(hdev, en); 7949 break; 7950 case HNAE3_LOOP_EXTERNAL: 7951 break; 7952 default: 7953 ret = -ENOTSUPP; 7954 dev_err(&hdev->pdev->dev, 7955 "loop_mode %d is not supported\n", loop_mode); 7956 break; 7957 } 7958 7959 if (ret) 7960 return ret; 7961 7962 ret = hclge_tqp_enable(handle, en); 7963 if (ret) 7964 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n", 7965 en ? "enable" : "disable", ret); 7966 7967 return ret; 7968 } 7969 7970 static int hclge_set_default_loopback(struct hclge_dev *hdev) 7971 { 7972 int ret; 7973 7974 ret = hclge_set_app_loopback(hdev, false); 7975 if (ret) 7976 return ret; 7977 7978 ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES); 7979 if (ret) 7980 return ret; 7981 7982 return hclge_cfg_common_loopback(hdev, false, 7983 HNAE3_LOOP_PARALLEL_SERDES); 7984 } 7985 7986 static void hclge_flush_link_update(struct hclge_dev *hdev) 7987 { 7988 #define HCLGE_FLUSH_LINK_TIMEOUT 100000 7989 7990 unsigned long last = hdev->serv_processed_cnt; 7991 int i = 0; 7992 7993 while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) && 7994 i++ < HCLGE_FLUSH_LINK_TIMEOUT && 7995 last == hdev->serv_processed_cnt) 7996 usleep_range(1, 1); 7997 } 7998 7999 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable) 8000 { 8001 struct hclge_vport *vport = hclge_get_vport(handle); 8002 struct hclge_dev *hdev = vport->back; 8003 8004 if (enable) { 8005 hclge_task_schedule(hdev, 0); 8006 } else { 8007 /* Set the DOWN flag here to disable link updating */ 8008 set_bit(HCLGE_STATE_DOWN, &hdev->state); 8009 8010 /* flush memory to make sure DOWN is seen by service task */ 8011 smp_mb__before_atomic(); 8012 hclge_flush_link_update(hdev); 8013 } 8014 } 8015 8016 static int hclge_ae_start(struct hnae3_handle *handle) 8017 { 8018 struct hclge_vport *vport = hclge_get_vport(handle); 8019 struct hclge_dev *hdev = vport->back; 8020 8021 /* mac enable */ 8022 hclge_cfg_mac_mode(hdev, true); 8023 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 8024 hdev->hw.mac.link = 0; 8025 8026 /* reset tqp stats */ 8027 hclge_comm_reset_tqp_stats(handle); 8028 8029 hclge_mac_start_phy(hdev); 8030 8031 return 0; 8032 } 8033 8034 static void hclge_ae_stop(struct hnae3_handle *handle) 8035 { 8036 struct hclge_vport *vport = hclge_get_vport(handle); 8037 struct hclge_dev *hdev = vport->back; 8038 8039 set_bit(HCLGE_STATE_DOWN, &hdev->state); 8040 spin_lock_bh(&hdev->fd_rule_lock); 8041 hclge_clear_arfs_rules(hdev); 8042 spin_unlock_bh(&hdev->fd_rule_lock); 8043 8044 /* If it is not PF reset or FLR, the firmware will disable the MAC, 8045 * so it only need to stop phy here. 8046 */ 8047 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { 8048 hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE, 8049 HCLGE_PFC_DISABLE); 8050 if (hdev->reset_type != HNAE3_FUNC_RESET && 8051 hdev->reset_type != HNAE3_FLR_RESET) { 8052 hclge_mac_stop_phy(hdev); 8053 hclge_update_link_status(hdev); 8054 return; 8055 } 8056 } 8057 8058 hclge_reset_tqp(handle); 8059 8060 hclge_config_mac_tnl_int(hdev, false); 8061 8062 /* Mac disable */ 8063 hclge_cfg_mac_mode(hdev, false); 8064 8065 hclge_mac_stop_phy(hdev); 8066 8067 /* reset tqp stats */ 8068 hclge_comm_reset_tqp_stats(handle); 8069 hclge_update_link_status(hdev); 8070 } 8071 8072 int hclge_vport_start(struct hclge_vport *vport) 8073 { 8074 struct hclge_dev *hdev = vport->back; 8075 8076 set_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8077 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8078 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 8079 vport->last_active_jiffies = jiffies; 8080 vport->need_notify = 0; 8081 8082 if (test_bit(vport->vport_id, hdev->vport_config_block)) { 8083 if (vport->vport_id) { 8084 hclge_restore_mac_table_common(vport); 8085 hclge_restore_vport_vlan_table(vport); 8086 } else { 8087 hclge_restore_hw_table(hdev); 8088 } 8089 } 8090 8091 clear_bit(vport->vport_id, hdev->vport_config_block); 8092 8093 return 0; 8094 } 8095 8096 void hclge_vport_stop(struct hclge_vport *vport) 8097 { 8098 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8099 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8100 vport->need_notify = 0; 8101 } 8102 8103 static int hclge_client_start(struct hnae3_handle *handle) 8104 { 8105 struct hclge_vport *vport = hclge_get_vport(handle); 8106 8107 return hclge_vport_start(vport); 8108 } 8109 8110 static void hclge_client_stop(struct hnae3_handle *handle) 8111 { 8112 struct hclge_vport *vport = hclge_get_vport(handle); 8113 8114 hclge_vport_stop(vport); 8115 } 8116 8117 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 8118 u16 cmdq_resp, u8 resp_code, 8119 enum hclge_mac_vlan_tbl_opcode op) 8120 { 8121 struct hclge_dev *hdev = vport->back; 8122 8123 if (cmdq_resp) { 8124 dev_err(&hdev->pdev->dev, 8125 "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n", 8126 cmdq_resp); 8127 return -EIO; 8128 } 8129 8130 if (op == HCLGE_MAC_VLAN_ADD) { 8131 if (!resp_code || resp_code == 1) 8132 return 0; 8133 else if (resp_code == HCLGE_ADD_UC_OVERFLOW || 8134 resp_code == HCLGE_ADD_MC_OVERFLOW) 8135 return -ENOSPC; 8136 8137 dev_err(&hdev->pdev->dev, 8138 "add mac addr failed for undefined, code=%u.\n", 8139 resp_code); 8140 return -EIO; 8141 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 8142 if (!resp_code) { 8143 return 0; 8144 } else if (resp_code == 1) { 8145 dev_dbg(&hdev->pdev->dev, 8146 "remove mac addr failed for miss.\n"); 8147 return -ENOENT; 8148 } 8149 8150 dev_err(&hdev->pdev->dev, 8151 "remove mac addr failed for undefined, code=%u.\n", 8152 resp_code); 8153 return -EIO; 8154 } else if (op == HCLGE_MAC_VLAN_LKUP) { 8155 if (!resp_code) { 8156 return 0; 8157 } else if (resp_code == 1) { 8158 dev_dbg(&hdev->pdev->dev, 8159 "lookup mac addr failed for miss.\n"); 8160 return -ENOENT; 8161 } 8162 8163 dev_err(&hdev->pdev->dev, 8164 "lookup mac addr failed for undefined, code=%u.\n", 8165 resp_code); 8166 return -EIO; 8167 } 8168 8169 dev_err(&hdev->pdev->dev, 8170 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op); 8171 8172 return -EINVAL; 8173 } 8174 8175 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 8176 { 8177 #define HCLGE_VF_NUM_IN_FIRST_DESC 192 8178 8179 unsigned int word_num; 8180 unsigned int bit_num; 8181 8182 if (vfid > 255 || vfid < 0) 8183 return -EIO; 8184 8185 if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) { 8186 word_num = vfid / 32; 8187 bit_num = vfid % 32; 8188 if (clr) 8189 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8190 else 8191 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 8192 } else { 8193 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32; 8194 bit_num = vfid % 32; 8195 if (clr) 8196 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8197 else 8198 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 8199 } 8200 8201 return 0; 8202 } 8203 8204 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 8205 { 8206 #define HCLGE_DESC_NUMBER 3 8207 #define HCLGE_FUNC_NUMBER_PER_DESC 6 8208 int i, j; 8209 8210 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 8211 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 8212 if (desc[i].data[j]) 8213 return false; 8214 8215 return true; 8216 } 8217 8218 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 8219 const u8 *addr, bool is_mc) 8220 { 8221 const unsigned char *mac_addr = addr; 8222 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 8223 (mac_addr[0]) | (mac_addr[1] << 8); 8224 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 8225 8226 hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8227 if (is_mc) { 8228 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 8229 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8230 } 8231 8232 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 8233 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 8234 } 8235 8236 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 8237 struct hclge_mac_vlan_tbl_entry_cmd *req) 8238 { 8239 struct hclge_dev *hdev = vport->back; 8240 struct hclge_desc desc; 8241 u8 resp_code; 8242 u16 retval; 8243 int ret; 8244 8245 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 8246 8247 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8248 8249 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8250 if (ret) { 8251 dev_err(&hdev->pdev->dev, 8252 "del mac addr failed for cmd_send, ret =%d.\n", 8253 ret); 8254 return ret; 8255 } 8256 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8257 retval = le16_to_cpu(desc.retval); 8258 8259 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8260 HCLGE_MAC_VLAN_REMOVE); 8261 } 8262 8263 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 8264 struct hclge_mac_vlan_tbl_entry_cmd *req, 8265 struct hclge_desc *desc, 8266 bool is_mc) 8267 { 8268 struct hclge_dev *hdev = vport->back; 8269 u8 resp_code; 8270 u16 retval; 8271 int ret; 8272 8273 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 8274 if (is_mc) { 8275 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8276 memcpy(desc[0].data, 8277 req, 8278 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8279 hclge_cmd_setup_basic_desc(&desc[1], 8280 HCLGE_OPC_MAC_VLAN_ADD, 8281 true); 8282 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8283 hclge_cmd_setup_basic_desc(&desc[2], 8284 HCLGE_OPC_MAC_VLAN_ADD, 8285 true); 8286 ret = hclge_cmd_send(&hdev->hw, desc, 3); 8287 } else { 8288 memcpy(desc[0].data, 8289 req, 8290 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8291 ret = hclge_cmd_send(&hdev->hw, desc, 1); 8292 } 8293 if (ret) { 8294 dev_err(&hdev->pdev->dev, 8295 "lookup mac addr failed for cmd_send, ret =%d.\n", 8296 ret); 8297 return ret; 8298 } 8299 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 8300 retval = le16_to_cpu(desc[0].retval); 8301 8302 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8303 HCLGE_MAC_VLAN_LKUP); 8304 } 8305 8306 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 8307 struct hclge_mac_vlan_tbl_entry_cmd *req, 8308 struct hclge_desc *mc_desc) 8309 { 8310 struct hclge_dev *hdev = vport->back; 8311 int cfg_status; 8312 u8 resp_code; 8313 u16 retval; 8314 int ret; 8315 8316 if (!mc_desc) { 8317 struct hclge_desc desc; 8318 8319 hclge_cmd_setup_basic_desc(&desc, 8320 HCLGE_OPC_MAC_VLAN_ADD, 8321 false); 8322 memcpy(desc.data, req, 8323 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8324 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8325 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8326 retval = le16_to_cpu(desc.retval); 8327 8328 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8329 resp_code, 8330 HCLGE_MAC_VLAN_ADD); 8331 } else { 8332 hclge_comm_cmd_reuse_desc(&mc_desc[0], false); 8333 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8334 hclge_comm_cmd_reuse_desc(&mc_desc[1], false); 8335 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8336 hclge_comm_cmd_reuse_desc(&mc_desc[2], false); 8337 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT); 8338 memcpy(mc_desc[0].data, req, 8339 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8340 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 8341 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 8342 retval = le16_to_cpu(mc_desc[0].retval); 8343 8344 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8345 resp_code, 8346 HCLGE_MAC_VLAN_ADD); 8347 } 8348 8349 if (ret) { 8350 dev_err(&hdev->pdev->dev, 8351 "add mac addr failed for cmd_send, ret =%d.\n", 8352 ret); 8353 return ret; 8354 } 8355 8356 return cfg_status; 8357 } 8358 8359 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 8360 u16 *allocated_size) 8361 { 8362 struct hclge_umv_spc_alc_cmd *req; 8363 struct hclge_desc desc; 8364 int ret; 8365 8366 req = (struct hclge_umv_spc_alc_cmd *)desc.data; 8367 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false); 8368 8369 req->space_size = cpu_to_le32(space_size); 8370 8371 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8372 if (ret) { 8373 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n", 8374 ret); 8375 return ret; 8376 } 8377 8378 *allocated_size = le32_to_cpu(desc.data[1]); 8379 8380 return 0; 8381 } 8382 8383 static int hclge_init_umv_space(struct hclge_dev *hdev) 8384 { 8385 u16 allocated_size = 0; 8386 int ret; 8387 8388 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size); 8389 if (ret) 8390 return ret; 8391 8392 if (allocated_size < hdev->wanted_umv_size) 8393 dev_warn(&hdev->pdev->dev, 8394 "failed to alloc umv space, want %u, get %u\n", 8395 hdev->wanted_umv_size, allocated_size); 8396 8397 hdev->max_umv_size = allocated_size; 8398 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1); 8399 hdev->share_umv_size = hdev->priv_umv_size + 8400 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8401 8402 if (hdev->ae_dev->dev_specs.mc_mac_size) 8403 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps); 8404 8405 return 0; 8406 } 8407 8408 static void hclge_reset_umv_space(struct hclge_dev *hdev) 8409 { 8410 struct hclge_vport *vport; 8411 int i; 8412 8413 for (i = 0; i < hdev->num_alloc_vport; i++) { 8414 vport = &hdev->vport[i]; 8415 vport->used_umv_num = 0; 8416 } 8417 8418 mutex_lock(&hdev->vport_lock); 8419 hdev->share_umv_size = hdev->priv_umv_size + 8420 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8421 mutex_unlock(&hdev->vport_lock); 8422 8423 hdev->used_mc_mac_num = 0; 8424 } 8425 8426 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock) 8427 { 8428 struct hclge_dev *hdev = vport->back; 8429 bool is_full; 8430 8431 if (need_lock) 8432 mutex_lock(&hdev->vport_lock); 8433 8434 is_full = (vport->used_umv_num >= hdev->priv_umv_size && 8435 hdev->share_umv_size == 0); 8436 8437 if (need_lock) 8438 mutex_unlock(&hdev->vport_lock); 8439 8440 return is_full; 8441 } 8442 8443 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free) 8444 { 8445 struct hclge_dev *hdev = vport->back; 8446 8447 if (is_free) { 8448 if (vport->used_umv_num > hdev->priv_umv_size) 8449 hdev->share_umv_size++; 8450 8451 if (vport->used_umv_num > 0) 8452 vport->used_umv_num--; 8453 } else { 8454 if (vport->used_umv_num >= hdev->priv_umv_size && 8455 hdev->share_umv_size > 0) 8456 hdev->share_umv_size--; 8457 vport->used_umv_num++; 8458 } 8459 } 8460 8461 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list, 8462 const u8 *mac_addr) 8463 { 8464 struct hclge_mac_node *mac_node, *tmp; 8465 8466 list_for_each_entry_safe(mac_node, tmp, list, node) 8467 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 8468 return mac_node; 8469 8470 return NULL; 8471 } 8472 8473 static void hclge_update_mac_node(struct hclge_mac_node *mac_node, 8474 enum HCLGE_MAC_NODE_STATE state) 8475 { 8476 switch (state) { 8477 /* from set_rx_mode or tmp_add_list */ 8478 case HCLGE_MAC_TO_ADD: 8479 if (mac_node->state == HCLGE_MAC_TO_DEL) 8480 mac_node->state = HCLGE_MAC_ACTIVE; 8481 break; 8482 /* only from set_rx_mode */ 8483 case HCLGE_MAC_TO_DEL: 8484 if (mac_node->state == HCLGE_MAC_TO_ADD) { 8485 list_del(&mac_node->node); 8486 kfree(mac_node); 8487 } else { 8488 mac_node->state = HCLGE_MAC_TO_DEL; 8489 } 8490 break; 8491 /* only from tmp_add_list, the mac_node->state won't be 8492 * ACTIVE. 8493 */ 8494 case HCLGE_MAC_ACTIVE: 8495 if (mac_node->state == HCLGE_MAC_TO_ADD) 8496 mac_node->state = HCLGE_MAC_ACTIVE; 8497 8498 break; 8499 } 8500 } 8501 8502 int hclge_update_mac_list(struct hclge_vport *vport, 8503 enum HCLGE_MAC_NODE_STATE state, 8504 enum HCLGE_MAC_ADDR_TYPE mac_type, 8505 const unsigned char *addr) 8506 { 8507 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8508 struct hclge_dev *hdev = vport->back; 8509 struct hclge_mac_node *mac_node; 8510 struct list_head *list; 8511 8512 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8513 &vport->uc_mac_list : &vport->mc_mac_list; 8514 8515 spin_lock_bh(&vport->mac_list_lock); 8516 8517 /* if the mac addr is already in the mac list, no need to add a new 8518 * one into it, just check the mac addr state, convert it to a new 8519 * state, or just remove it, or do nothing. 8520 */ 8521 mac_node = hclge_find_mac_node(list, addr); 8522 if (mac_node) { 8523 hclge_update_mac_node(mac_node, state); 8524 spin_unlock_bh(&vport->mac_list_lock); 8525 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8526 return 0; 8527 } 8528 8529 /* if this address is never added, unnecessary to delete */ 8530 if (state == HCLGE_MAC_TO_DEL) { 8531 spin_unlock_bh(&vport->mac_list_lock); 8532 hnae3_format_mac_addr(format_mac_addr, addr); 8533 dev_err(&hdev->pdev->dev, 8534 "failed to delete address %s from mac list\n", 8535 format_mac_addr); 8536 return -ENOENT; 8537 } 8538 8539 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 8540 if (!mac_node) { 8541 spin_unlock_bh(&vport->mac_list_lock); 8542 return -ENOMEM; 8543 } 8544 8545 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8546 8547 mac_node->state = state; 8548 ether_addr_copy(mac_node->mac_addr, addr); 8549 list_add_tail(&mac_node->node, list); 8550 8551 spin_unlock_bh(&vport->mac_list_lock); 8552 8553 return 0; 8554 } 8555 8556 static int hclge_add_uc_addr(struct hnae3_handle *handle, 8557 const unsigned char *addr) 8558 { 8559 struct hclge_vport *vport = hclge_get_vport(handle); 8560 8561 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC, 8562 addr); 8563 } 8564 8565 int hclge_add_uc_addr_common(struct hclge_vport *vport, 8566 const unsigned char *addr) 8567 { 8568 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8569 struct hclge_dev *hdev = vport->back; 8570 struct hclge_mac_vlan_tbl_entry_cmd req; 8571 struct hclge_desc desc; 8572 u16 egress_port = 0; 8573 int ret; 8574 8575 /* mac addr check */ 8576 if (is_zero_ether_addr(addr) || 8577 is_broadcast_ether_addr(addr) || 8578 is_multicast_ether_addr(addr)) { 8579 hnae3_format_mac_addr(format_mac_addr, addr); 8580 dev_err(&hdev->pdev->dev, 8581 "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n", 8582 format_mac_addr, is_zero_ether_addr(addr), 8583 is_broadcast_ether_addr(addr), 8584 is_multicast_ether_addr(addr)); 8585 return -EINVAL; 8586 } 8587 8588 memset(&req, 0, sizeof(req)); 8589 8590 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 8591 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 8592 8593 req.egress_port = cpu_to_le16(egress_port); 8594 8595 hclge_prepare_mac_addr(&req, addr, false); 8596 8597 /* Lookup the mac address in the mac_vlan table, and add 8598 * it if the entry is inexistent. Repeated unicast entry 8599 * is not allowed in the mac vlan table. 8600 */ 8601 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 8602 if (ret == -ENOENT) { 8603 mutex_lock(&hdev->vport_lock); 8604 if (!hclge_is_umv_space_full(vport, false)) { 8605 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL); 8606 if (!ret) 8607 hclge_update_umv_space(vport, false); 8608 mutex_unlock(&hdev->vport_lock); 8609 return ret; 8610 } 8611 mutex_unlock(&hdev->vport_lock); 8612 8613 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE)) 8614 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n", 8615 hdev->priv_umv_size); 8616 8617 return -ENOSPC; 8618 } 8619 8620 /* check if we just hit the duplicate */ 8621 if (!ret) 8622 return -EEXIST; 8623 8624 return ret; 8625 } 8626 8627 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 8628 const unsigned char *addr) 8629 { 8630 struct hclge_vport *vport = hclge_get_vport(handle); 8631 8632 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC, 8633 addr); 8634 } 8635 8636 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 8637 const unsigned char *addr) 8638 { 8639 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8640 struct hclge_dev *hdev = vport->back; 8641 struct hclge_mac_vlan_tbl_entry_cmd req; 8642 int ret; 8643 8644 /* mac addr check */ 8645 if (is_zero_ether_addr(addr) || 8646 is_broadcast_ether_addr(addr) || 8647 is_multicast_ether_addr(addr)) { 8648 hnae3_format_mac_addr(format_mac_addr, addr); 8649 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n", 8650 format_mac_addr); 8651 return -EINVAL; 8652 } 8653 8654 memset(&req, 0, sizeof(req)); 8655 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 8656 hclge_prepare_mac_addr(&req, addr, false); 8657 ret = hclge_remove_mac_vlan_tbl(vport, &req); 8658 if (!ret || ret == -ENOENT) { 8659 mutex_lock(&hdev->vport_lock); 8660 hclge_update_umv_space(vport, true); 8661 mutex_unlock(&hdev->vport_lock); 8662 return 0; 8663 } 8664 8665 return ret; 8666 } 8667 8668 static int hclge_add_mc_addr(struct hnae3_handle *handle, 8669 const unsigned char *addr) 8670 { 8671 struct hclge_vport *vport = hclge_get_vport(handle); 8672 8673 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC, 8674 addr); 8675 } 8676 8677 int hclge_add_mc_addr_common(struct hclge_vport *vport, 8678 const unsigned char *addr) 8679 { 8680 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8681 struct hclge_dev *hdev = vport->back; 8682 struct hclge_mac_vlan_tbl_entry_cmd req; 8683 struct hclge_desc desc[3]; 8684 bool is_new_addr = false; 8685 int status; 8686 8687 /* mac addr check */ 8688 if (!is_multicast_ether_addr(addr)) { 8689 hnae3_format_mac_addr(format_mac_addr, addr); 8690 dev_err(&hdev->pdev->dev, 8691 "Add mc mac err! invalid mac:%s.\n", 8692 format_mac_addr); 8693 return -EINVAL; 8694 } 8695 memset(&req, 0, sizeof(req)); 8696 hclge_prepare_mac_addr(&req, addr, true); 8697 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8698 if (status) { 8699 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) && 8700 hdev->used_mc_mac_num >= 8701 hdev->ae_dev->dev_specs.mc_mac_size) 8702 goto err_no_space; 8703 8704 is_new_addr = true; 8705 8706 /* This mac addr do not exist, add new entry for it */ 8707 memset(desc[0].data, 0, sizeof(desc[0].data)); 8708 memset(desc[1].data, 0, sizeof(desc[0].data)); 8709 memset(desc[2].data, 0, sizeof(desc[0].data)); 8710 } 8711 status = hclge_update_desc_vfid(desc, vport->vport_id, false); 8712 if (status) 8713 return status; 8714 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8715 if (status == -ENOSPC) 8716 goto err_no_space; 8717 else if (!status && is_new_addr) 8718 hdev->used_mc_mac_num++; 8719 8720 return status; 8721 8722 err_no_space: 8723 /* if already overflow, not to print each time */ 8724 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) { 8725 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8726 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n"); 8727 } 8728 8729 return -ENOSPC; 8730 } 8731 8732 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 8733 const unsigned char *addr) 8734 { 8735 struct hclge_vport *vport = hclge_get_vport(handle); 8736 8737 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC, 8738 addr); 8739 } 8740 8741 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 8742 const unsigned char *addr) 8743 { 8744 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8745 struct hclge_dev *hdev = vport->back; 8746 struct hclge_mac_vlan_tbl_entry_cmd req; 8747 enum hclge_comm_cmd_status status; 8748 struct hclge_desc desc[3]; 8749 8750 /* mac addr check */ 8751 if (!is_multicast_ether_addr(addr)) { 8752 hnae3_format_mac_addr(format_mac_addr, addr); 8753 dev_dbg(&hdev->pdev->dev, 8754 "Remove mc mac err! invalid mac:%s.\n", 8755 format_mac_addr); 8756 return -EINVAL; 8757 } 8758 8759 memset(&req, 0, sizeof(req)); 8760 hclge_prepare_mac_addr(&req, addr, true); 8761 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8762 if (!status) { 8763 /* This mac addr exist, remove this handle's VFID for it */ 8764 status = hclge_update_desc_vfid(desc, vport->vport_id, true); 8765 if (status) 8766 return status; 8767 8768 if (hclge_is_all_function_id_zero(desc)) { 8769 /* All the vfid is zero, so need to delete this entry */ 8770 status = hclge_remove_mac_vlan_tbl(vport, &req); 8771 if (!status) 8772 hdev->used_mc_mac_num--; 8773 } else { 8774 /* Not all the vfid is zero, update the vfid */ 8775 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8776 } 8777 } else if (status == -ENOENT) { 8778 status = 0; 8779 } 8780 8781 return status; 8782 } 8783 8784 static void hclge_sync_vport_mac_list(struct hclge_vport *vport, 8785 struct list_head *list, 8786 enum HCLGE_MAC_ADDR_TYPE mac_type) 8787 { 8788 int (*sync)(struct hclge_vport *vport, const unsigned char *addr); 8789 struct hclge_mac_node *mac_node, *tmp; 8790 int ret; 8791 8792 if (mac_type == HCLGE_MAC_ADDR_UC) 8793 sync = hclge_add_uc_addr_common; 8794 else 8795 sync = hclge_add_mc_addr_common; 8796 8797 list_for_each_entry_safe(mac_node, tmp, list, node) { 8798 ret = sync(vport, mac_node->mac_addr); 8799 if (!ret) { 8800 mac_node->state = HCLGE_MAC_ACTIVE; 8801 } else { 8802 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8803 &vport->state); 8804 8805 /* If one unicast mac address is existing in hardware, 8806 * we need to try whether other unicast mac addresses 8807 * are new addresses that can be added. 8808 * Multicast mac address can be reusable, even though 8809 * there is no space to add new multicast mac address, 8810 * we should check whether other mac addresses are 8811 * existing in hardware for reuse. 8812 */ 8813 if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) || 8814 (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC)) 8815 break; 8816 } 8817 } 8818 } 8819 8820 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport, 8821 struct list_head *list, 8822 enum HCLGE_MAC_ADDR_TYPE mac_type) 8823 { 8824 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 8825 struct hclge_mac_node *mac_node, *tmp; 8826 int ret; 8827 8828 if (mac_type == HCLGE_MAC_ADDR_UC) 8829 unsync = hclge_rm_uc_addr_common; 8830 else 8831 unsync = hclge_rm_mc_addr_common; 8832 8833 list_for_each_entry_safe(mac_node, tmp, list, node) { 8834 ret = unsync(vport, mac_node->mac_addr); 8835 if (!ret || ret == -ENOENT) { 8836 list_del(&mac_node->node); 8837 kfree(mac_node); 8838 } else { 8839 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8840 &vport->state); 8841 break; 8842 } 8843 } 8844 } 8845 8846 static bool hclge_sync_from_add_list(struct list_head *add_list, 8847 struct list_head *mac_list) 8848 { 8849 struct hclge_mac_node *mac_node, *tmp, *new_node; 8850 bool all_added = true; 8851 8852 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 8853 if (mac_node->state == HCLGE_MAC_TO_ADD) 8854 all_added = false; 8855 8856 /* if the mac address from tmp_add_list is not in the 8857 * uc/mc_mac_list, it means have received a TO_DEL request 8858 * during the time window of adding the mac address into mac 8859 * table. if mac_node state is ACTIVE, then change it to TO_DEL, 8860 * then it will be removed at next time. else it must be TO_ADD, 8861 * this address hasn't been added into mac table, 8862 * so just remove the mac node. 8863 */ 8864 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8865 if (new_node) { 8866 hclge_update_mac_node(new_node, mac_node->state); 8867 list_del(&mac_node->node); 8868 kfree(mac_node); 8869 } else if (mac_node->state == HCLGE_MAC_ACTIVE) { 8870 mac_node->state = HCLGE_MAC_TO_DEL; 8871 list_move_tail(&mac_node->node, mac_list); 8872 } else { 8873 list_del(&mac_node->node); 8874 kfree(mac_node); 8875 } 8876 } 8877 8878 return all_added; 8879 } 8880 8881 static void hclge_sync_from_del_list(struct list_head *del_list, 8882 struct list_head *mac_list) 8883 { 8884 struct hclge_mac_node *mac_node, *tmp, *new_node; 8885 8886 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 8887 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8888 if (new_node) { 8889 /* If the mac addr exists in the mac list, it means 8890 * received a new TO_ADD request during the time window 8891 * of configuring the mac address. For the mac node 8892 * state is TO_ADD, and the address is already in the 8893 * in the hardware(due to delete fail), so we just need 8894 * to change the mac node state to ACTIVE. 8895 */ 8896 new_node->state = HCLGE_MAC_ACTIVE; 8897 list_del(&mac_node->node); 8898 kfree(mac_node); 8899 } else { 8900 list_move_tail(&mac_node->node, mac_list); 8901 } 8902 } 8903 } 8904 8905 static void hclge_update_overflow_flags(struct hclge_vport *vport, 8906 enum HCLGE_MAC_ADDR_TYPE mac_type, 8907 bool is_all_added) 8908 { 8909 if (mac_type == HCLGE_MAC_ADDR_UC) { 8910 if (is_all_added) 8911 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE; 8912 else 8913 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE; 8914 } else { 8915 if (is_all_added) 8916 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE; 8917 else 8918 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8919 } 8920 } 8921 8922 static void hclge_sync_vport_mac_table(struct hclge_vport *vport, 8923 enum HCLGE_MAC_ADDR_TYPE mac_type) 8924 { 8925 struct hclge_mac_node *mac_node, *tmp, *new_node; 8926 struct list_head tmp_add_list, tmp_del_list; 8927 struct list_head *list; 8928 bool all_added; 8929 8930 INIT_LIST_HEAD(&tmp_add_list); 8931 INIT_LIST_HEAD(&tmp_del_list); 8932 8933 /* move the mac addr to the tmp_add_list and tmp_del_list, then 8934 * we can add/delete these mac addr outside the spin lock 8935 */ 8936 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8937 &vport->uc_mac_list : &vport->mc_mac_list; 8938 8939 spin_lock_bh(&vport->mac_list_lock); 8940 8941 list_for_each_entry_safe(mac_node, tmp, list, node) { 8942 switch (mac_node->state) { 8943 case HCLGE_MAC_TO_DEL: 8944 list_move_tail(&mac_node->node, &tmp_del_list); 8945 break; 8946 case HCLGE_MAC_TO_ADD: 8947 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 8948 if (!new_node) 8949 goto stop_traverse; 8950 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 8951 new_node->state = mac_node->state; 8952 list_add_tail(&new_node->node, &tmp_add_list); 8953 break; 8954 default: 8955 break; 8956 } 8957 } 8958 8959 stop_traverse: 8960 spin_unlock_bh(&vport->mac_list_lock); 8961 8962 /* delete first, in order to get max mac table space for adding */ 8963 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 8964 hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type); 8965 8966 /* if some mac addresses were added/deleted fail, move back to the 8967 * mac_list, and retry at next time. 8968 */ 8969 spin_lock_bh(&vport->mac_list_lock); 8970 8971 hclge_sync_from_del_list(&tmp_del_list, list); 8972 all_added = hclge_sync_from_add_list(&tmp_add_list, list); 8973 8974 spin_unlock_bh(&vport->mac_list_lock); 8975 8976 hclge_update_overflow_flags(vport, mac_type, all_added); 8977 } 8978 8979 static bool hclge_need_sync_mac_table(struct hclge_vport *vport) 8980 { 8981 struct hclge_dev *hdev = vport->back; 8982 8983 if (test_bit(vport->vport_id, hdev->vport_config_block)) 8984 return false; 8985 8986 if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state)) 8987 return true; 8988 8989 return false; 8990 } 8991 8992 static void hclge_sync_mac_table(struct hclge_dev *hdev) 8993 { 8994 int i; 8995 8996 for (i = 0; i < hdev->num_alloc_vport; i++) { 8997 struct hclge_vport *vport = &hdev->vport[i]; 8998 8999 if (!hclge_need_sync_mac_table(vport)) 9000 continue; 9001 9002 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC); 9003 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC); 9004 } 9005 } 9006 9007 static void hclge_build_del_list(struct list_head *list, 9008 bool is_del_list, 9009 struct list_head *tmp_del_list) 9010 { 9011 struct hclge_mac_node *mac_cfg, *tmp; 9012 9013 list_for_each_entry_safe(mac_cfg, tmp, list, node) { 9014 switch (mac_cfg->state) { 9015 case HCLGE_MAC_TO_DEL: 9016 case HCLGE_MAC_ACTIVE: 9017 list_move_tail(&mac_cfg->node, tmp_del_list); 9018 break; 9019 case HCLGE_MAC_TO_ADD: 9020 if (is_del_list) { 9021 list_del(&mac_cfg->node); 9022 kfree(mac_cfg); 9023 } 9024 break; 9025 } 9026 } 9027 } 9028 9029 static void hclge_unsync_del_list(struct hclge_vport *vport, 9030 int (*unsync)(struct hclge_vport *vport, 9031 const unsigned char *addr), 9032 bool is_del_list, 9033 struct list_head *tmp_del_list) 9034 { 9035 struct hclge_mac_node *mac_cfg, *tmp; 9036 int ret; 9037 9038 list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) { 9039 ret = unsync(vport, mac_cfg->mac_addr); 9040 if (!ret || ret == -ENOENT) { 9041 /* clear all mac addr from hardware, but remain these 9042 * mac addr in the mac list, and restore them after 9043 * vf reset finished. 9044 */ 9045 if (!is_del_list && 9046 mac_cfg->state == HCLGE_MAC_ACTIVE) { 9047 mac_cfg->state = HCLGE_MAC_TO_ADD; 9048 } else { 9049 list_del(&mac_cfg->node); 9050 kfree(mac_cfg); 9051 } 9052 } else if (is_del_list) { 9053 mac_cfg->state = HCLGE_MAC_TO_DEL; 9054 } 9055 } 9056 } 9057 9058 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 9059 enum HCLGE_MAC_ADDR_TYPE mac_type) 9060 { 9061 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 9062 struct hclge_dev *hdev = vport->back; 9063 struct list_head tmp_del_list, *list; 9064 9065 if (mac_type == HCLGE_MAC_ADDR_UC) { 9066 list = &vport->uc_mac_list; 9067 unsync = hclge_rm_uc_addr_common; 9068 } else { 9069 list = &vport->mc_mac_list; 9070 unsync = hclge_rm_mc_addr_common; 9071 } 9072 9073 INIT_LIST_HEAD(&tmp_del_list); 9074 9075 if (!is_del_list) 9076 set_bit(vport->vport_id, hdev->vport_config_block); 9077 9078 spin_lock_bh(&vport->mac_list_lock); 9079 9080 hclge_build_del_list(list, is_del_list, &tmp_del_list); 9081 9082 spin_unlock_bh(&vport->mac_list_lock); 9083 9084 hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list); 9085 9086 spin_lock_bh(&vport->mac_list_lock); 9087 9088 hclge_sync_from_del_list(&tmp_del_list, list); 9089 9090 spin_unlock_bh(&vport->mac_list_lock); 9091 } 9092 9093 /* remove all mac address when uninitailize */ 9094 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport, 9095 enum HCLGE_MAC_ADDR_TYPE mac_type) 9096 { 9097 struct hclge_mac_node *mac_node, *tmp; 9098 struct hclge_dev *hdev = vport->back; 9099 struct list_head tmp_del_list, *list; 9100 9101 INIT_LIST_HEAD(&tmp_del_list); 9102 9103 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 9104 &vport->uc_mac_list : &vport->mc_mac_list; 9105 9106 spin_lock_bh(&vport->mac_list_lock); 9107 9108 list_for_each_entry_safe(mac_node, tmp, list, node) { 9109 switch (mac_node->state) { 9110 case HCLGE_MAC_TO_DEL: 9111 case HCLGE_MAC_ACTIVE: 9112 list_move_tail(&mac_node->node, &tmp_del_list); 9113 break; 9114 case HCLGE_MAC_TO_ADD: 9115 list_del(&mac_node->node); 9116 kfree(mac_node); 9117 break; 9118 } 9119 } 9120 9121 spin_unlock_bh(&vport->mac_list_lock); 9122 9123 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 9124 9125 if (!list_empty(&tmp_del_list)) 9126 dev_warn(&hdev->pdev->dev, 9127 "uninit %s mac list for vport %u not completely.\n", 9128 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc", 9129 vport->vport_id); 9130 9131 list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) { 9132 list_del(&mac_node->node); 9133 kfree(mac_node); 9134 } 9135 } 9136 9137 static void hclge_uninit_mac_table(struct hclge_dev *hdev) 9138 { 9139 struct hclge_vport *vport; 9140 int i; 9141 9142 for (i = 0; i < hdev->num_alloc_vport; i++) { 9143 vport = &hdev->vport[i]; 9144 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC); 9145 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC); 9146 } 9147 } 9148 9149 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 9150 u16 cmdq_resp, u8 resp_code) 9151 { 9152 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 9153 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 9154 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 9155 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 9156 9157 int return_status; 9158 9159 if (cmdq_resp) { 9160 dev_err(&hdev->pdev->dev, 9161 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 9162 cmdq_resp); 9163 return -EIO; 9164 } 9165 9166 switch (resp_code) { 9167 case HCLGE_ETHERTYPE_SUCCESS_ADD: 9168 case HCLGE_ETHERTYPE_ALREADY_ADD: 9169 return_status = 0; 9170 break; 9171 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 9172 dev_err(&hdev->pdev->dev, 9173 "add mac ethertype failed for manager table overflow.\n"); 9174 return_status = -EIO; 9175 break; 9176 case HCLGE_ETHERTYPE_KEY_CONFLICT: 9177 dev_err(&hdev->pdev->dev, 9178 "add mac ethertype failed for key conflict.\n"); 9179 return_status = -EIO; 9180 break; 9181 default: 9182 dev_err(&hdev->pdev->dev, 9183 "add mac ethertype failed for undefined, code=%u.\n", 9184 resp_code); 9185 return_status = -EIO; 9186 } 9187 9188 return return_status; 9189 } 9190 9191 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf, 9192 u8 *mac_addr) 9193 { 9194 struct hclge_vport *vport = hclge_get_vport(handle); 9195 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9196 struct hclge_dev *hdev = vport->back; 9197 9198 vport = hclge_get_vf_vport(hdev, vf); 9199 if (!vport) 9200 return -EINVAL; 9201 9202 hnae3_format_mac_addr(format_mac_addr, mac_addr); 9203 if (ether_addr_equal(mac_addr, vport->vf_info.mac)) { 9204 dev_info(&hdev->pdev->dev, 9205 "Specified MAC(=%s) is same as before, no change committed!\n", 9206 format_mac_addr); 9207 return 0; 9208 } 9209 9210 ether_addr_copy(vport->vf_info.mac, mac_addr); 9211 9212 /* there is a timewindow for PF to know VF unalive, it may 9213 * cause send mailbox fail, but it doesn't matter, VF will 9214 * query it when reinit. 9215 */ 9216 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) { 9217 dev_info(&hdev->pdev->dev, 9218 "MAC of VF %d has been set to %s, and it will be reinitialized!\n", 9219 vf, format_mac_addr); 9220 (void)hclge_inform_reset_assert_to_vf(vport); 9221 return 0; 9222 } 9223 9224 dev_info(&hdev->pdev->dev, 9225 "MAC of VF %d has been set to %s, will be active after VF reset\n", 9226 vf, format_mac_addr); 9227 return 0; 9228 } 9229 9230 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 9231 const struct hclge_mac_mgr_tbl_entry_cmd *req) 9232 { 9233 struct hclge_desc desc; 9234 u8 resp_code; 9235 u16 retval; 9236 int ret; 9237 9238 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 9239 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 9240 9241 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9242 if (ret) { 9243 dev_err(&hdev->pdev->dev, 9244 "add mac ethertype failed for cmd_send, ret =%d.\n", 9245 ret); 9246 return ret; 9247 } 9248 9249 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 9250 retval = le16_to_cpu(desc.retval); 9251 9252 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 9253 } 9254 9255 static int init_mgr_tbl(struct hclge_dev *hdev) 9256 { 9257 int ret; 9258 int i; 9259 9260 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 9261 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 9262 if (ret) { 9263 dev_err(&hdev->pdev->dev, 9264 "add mac ethertype failed, ret =%d.\n", 9265 ret); 9266 return ret; 9267 } 9268 } 9269 9270 return 0; 9271 } 9272 9273 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 9274 { 9275 struct hclge_vport *vport = hclge_get_vport(handle); 9276 struct hclge_dev *hdev = vport->back; 9277 9278 ether_addr_copy(p, hdev->hw.mac.mac_addr); 9279 } 9280 9281 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 9282 const u8 *old_addr, const u8 *new_addr) 9283 { 9284 struct list_head *list = &vport->uc_mac_list; 9285 struct hclge_mac_node *old_node, *new_node; 9286 9287 new_node = hclge_find_mac_node(list, new_addr); 9288 if (!new_node) { 9289 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 9290 if (!new_node) 9291 return -ENOMEM; 9292 9293 new_node->state = HCLGE_MAC_TO_ADD; 9294 ether_addr_copy(new_node->mac_addr, new_addr); 9295 list_add(&new_node->node, list); 9296 } else { 9297 if (new_node->state == HCLGE_MAC_TO_DEL) 9298 new_node->state = HCLGE_MAC_ACTIVE; 9299 9300 /* make sure the new addr is in the list head, avoid dev 9301 * addr may be not re-added into mac table for the umv space 9302 * limitation after global/imp reset which will clear mac 9303 * table by hardware. 9304 */ 9305 list_move(&new_node->node, list); 9306 } 9307 9308 if (old_addr && !ether_addr_equal(old_addr, new_addr)) { 9309 old_node = hclge_find_mac_node(list, old_addr); 9310 if (old_node) { 9311 if (old_node->state == HCLGE_MAC_TO_ADD) { 9312 list_del(&old_node->node); 9313 kfree(old_node); 9314 } else { 9315 old_node->state = HCLGE_MAC_TO_DEL; 9316 } 9317 } 9318 } 9319 9320 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 9321 9322 return 0; 9323 } 9324 9325 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p, 9326 bool is_first) 9327 { 9328 const unsigned char *new_addr = (const unsigned char *)p; 9329 struct hclge_vport *vport = hclge_get_vport(handle); 9330 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9331 struct hclge_dev *hdev = vport->back; 9332 unsigned char *old_addr = NULL; 9333 int ret; 9334 9335 /* mac addr check */ 9336 if (is_zero_ether_addr(new_addr) || 9337 is_broadcast_ether_addr(new_addr) || 9338 is_multicast_ether_addr(new_addr)) { 9339 hnae3_format_mac_addr(format_mac_addr, new_addr); 9340 dev_err(&hdev->pdev->dev, 9341 "change uc mac err! invalid mac: %s.\n", 9342 format_mac_addr); 9343 return -EINVAL; 9344 } 9345 9346 ret = hclge_pause_addr_cfg(hdev, new_addr); 9347 if (ret) { 9348 dev_err(&hdev->pdev->dev, 9349 "failed to configure mac pause address, ret = %d\n", 9350 ret); 9351 return ret; 9352 } 9353 9354 if (!is_first) 9355 old_addr = hdev->hw.mac.mac_addr; 9356 9357 spin_lock_bh(&vport->mac_list_lock); 9358 ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr); 9359 if (ret) { 9360 hnae3_format_mac_addr(format_mac_addr, new_addr); 9361 dev_err(&hdev->pdev->dev, 9362 "failed to change the mac addr:%s, ret = %d\n", 9363 format_mac_addr, ret); 9364 spin_unlock_bh(&vport->mac_list_lock); 9365 9366 if (!is_first) 9367 hclge_pause_addr_cfg(hdev, old_addr); 9368 9369 return ret; 9370 } 9371 /* we must update dev addr with spin lock protect, preventing dev addr 9372 * being removed by set_rx_mode path. 9373 */ 9374 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 9375 spin_unlock_bh(&vport->mac_list_lock); 9376 9377 hclge_task_schedule(hdev, 0); 9378 9379 return 0; 9380 } 9381 9382 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd) 9383 { 9384 struct mii_ioctl_data *data = if_mii(ifr); 9385 9386 if (!hnae3_dev_phy_imp_supported(hdev)) 9387 return -EOPNOTSUPP; 9388 9389 switch (cmd) { 9390 case SIOCGMIIPHY: 9391 data->phy_id = hdev->hw.mac.phy_addr; 9392 /* this command reads phy id and register at the same time */ 9393 fallthrough; 9394 case SIOCGMIIREG: 9395 data->val_out = hclge_read_phy_reg(hdev, data->reg_num); 9396 return 0; 9397 9398 case SIOCSMIIREG: 9399 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in); 9400 default: 9401 return -EOPNOTSUPP; 9402 } 9403 } 9404 9405 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr, 9406 int cmd) 9407 { 9408 struct hclge_vport *vport = hclge_get_vport(handle); 9409 struct hclge_dev *hdev = vport->back; 9410 9411 switch (cmd) { 9412 case SIOCGHWTSTAMP: 9413 return hclge_ptp_get_cfg(hdev, ifr); 9414 case SIOCSHWTSTAMP: 9415 return hclge_ptp_set_cfg(hdev, ifr); 9416 default: 9417 if (!hdev->hw.mac.phydev) 9418 return hclge_mii_ioctl(hdev, ifr, cmd); 9419 } 9420 9421 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd); 9422 } 9423 9424 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id, 9425 bool bypass_en) 9426 { 9427 struct hclge_port_vlan_filter_bypass_cmd *req; 9428 struct hclge_desc desc; 9429 int ret; 9430 9431 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false); 9432 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 9433 req->vf_id = vf_id; 9434 hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B, 9435 bypass_en ? 1 : 0); 9436 9437 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9438 if (ret) 9439 dev_err(&hdev->pdev->dev, 9440 "failed to set vport%u port vlan filter bypass state, ret = %d.\n", 9441 vf_id, ret); 9442 9443 return ret; 9444 } 9445 9446 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 9447 u8 fe_type, bool filter_en, u8 vf_id) 9448 { 9449 struct hclge_vlan_filter_ctrl_cmd *req; 9450 struct hclge_desc desc; 9451 int ret; 9452 9453 /* read current vlan filter parameter */ 9454 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 9455 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 9456 req->vlan_type = vlan_type; 9457 req->vf_id = vf_id; 9458 9459 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9460 if (ret) { 9461 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n", 9462 vf_id, ret); 9463 return ret; 9464 } 9465 9466 /* modify and write new config parameter */ 9467 hclge_comm_cmd_reuse_desc(&desc, false); 9468 req->vlan_fe = filter_en ? 9469 (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type); 9470 9471 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9472 if (ret) 9473 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n", 9474 vf_id, ret); 9475 9476 return ret; 9477 } 9478 9479 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable) 9480 { 9481 struct hclge_dev *hdev = vport->back; 9482 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 9483 int ret; 9484 9485 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9486 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9487 HCLGE_FILTER_FE_EGRESS_V1_B, 9488 enable, vport->vport_id); 9489 9490 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9491 HCLGE_FILTER_FE_EGRESS, enable, 9492 vport->vport_id); 9493 if (ret) 9494 return ret; 9495 9496 if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) { 9497 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id, 9498 !enable); 9499 } else if (!vport->vport_id) { 9500 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 9501 enable = false; 9502 9503 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9504 HCLGE_FILTER_FE_INGRESS, 9505 enable, 0); 9506 } 9507 9508 return ret; 9509 } 9510 9511 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport) 9512 { 9513 struct hnae3_handle *handle = &vport->nic; 9514 struct hclge_vport_vlan_cfg *vlan, *tmp; 9515 struct hclge_dev *hdev = vport->back; 9516 9517 if (vport->vport_id) { 9518 if (vport->port_base_vlan_cfg.state != 9519 HNAE3_PORT_BASE_VLAN_DISABLE) 9520 return true; 9521 9522 if (vport->vf_info.trusted && vport->vf_info.request_uc_en) 9523 return false; 9524 } else if (handle->netdev_flags & HNAE3_USER_UPE) { 9525 return false; 9526 } 9527 9528 if (!vport->req_vlan_fltr_en) 9529 return false; 9530 9531 /* compatible with former device, always enable vlan filter */ 9532 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 9533 return true; 9534 9535 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) 9536 if (vlan->vlan_id != 0) 9537 return true; 9538 9539 return false; 9540 } 9541 9542 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) 9543 { 9544 struct hclge_dev *hdev = vport->back; 9545 bool need_en; 9546 int ret; 9547 9548 mutex_lock(&hdev->vport_lock); 9549 9550 vport->req_vlan_fltr_en = request_en; 9551 9552 need_en = hclge_need_enable_vport_vlan_filter(vport); 9553 if (need_en == vport->cur_vlan_fltr_en) { 9554 mutex_unlock(&hdev->vport_lock); 9555 return 0; 9556 } 9557 9558 ret = hclge_set_vport_vlan_filter(vport, need_en); 9559 if (ret) { 9560 mutex_unlock(&hdev->vport_lock); 9561 return ret; 9562 } 9563 9564 vport->cur_vlan_fltr_en = need_en; 9565 9566 mutex_unlock(&hdev->vport_lock); 9567 9568 return 0; 9569 } 9570 9571 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 9572 { 9573 struct hclge_vport *vport = hclge_get_vport(handle); 9574 9575 return hclge_enable_vport_vlan_filter(vport, enable); 9576 } 9577 9578 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid, 9579 bool is_kill, u16 vlan, 9580 struct hclge_desc *desc) 9581 { 9582 struct hclge_vlan_filter_vf_cfg_cmd *req0; 9583 struct hclge_vlan_filter_vf_cfg_cmd *req1; 9584 u8 vf_byte_val; 9585 u8 vf_byte_off; 9586 int ret; 9587 9588 hclge_cmd_setup_basic_desc(&desc[0], 9589 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9590 hclge_cmd_setup_basic_desc(&desc[1], 9591 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9592 9593 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 9594 9595 vf_byte_off = vfid / 8; 9596 vf_byte_val = 1 << (vfid % 8); 9597 9598 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9599 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 9600 9601 req0->vlan_id = cpu_to_le16(vlan); 9602 req0->vlan_cfg = is_kill; 9603 9604 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 9605 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 9606 else 9607 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 9608 9609 ret = hclge_cmd_send(&hdev->hw, desc, 2); 9610 if (ret) { 9611 dev_err(&hdev->pdev->dev, 9612 "Send vf vlan command fail, ret =%d.\n", 9613 ret); 9614 return ret; 9615 } 9616 9617 return 0; 9618 } 9619 9620 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid, 9621 bool is_kill, struct hclge_desc *desc) 9622 { 9623 struct hclge_vlan_filter_vf_cfg_cmd *req; 9624 9625 req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9626 9627 if (!is_kill) { 9628 #define HCLGE_VF_VLAN_NO_ENTRY 2 9629 if (!req->resp_code || req->resp_code == 1) 9630 return 0; 9631 9632 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 9633 set_bit(vfid, hdev->vf_vlan_full); 9634 dev_warn(&hdev->pdev->dev, 9635 "vf vlan table is full, vf vlan filter is disabled\n"); 9636 return 0; 9637 } 9638 9639 dev_err(&hdev->pdev->dev, 9640 "Add vf vlan filter fail, ret =%u.\n", 9641 req->resp_code); 9642 } else { 9643 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 9644 if (!req->resp_code) 9645 return 0; 9646 9647 /* vf vlan filter is disabled when vf vlan table is full, 9648 * then new vlan id will not be added into vf vlan table. 9649 * Just return 0 without warning, avoid massive verbose 9650 * print logs when unload. 9651 */ 9652 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) 9653 return 0; 9654 9655 dev_err(&hdev->pdev->dev, 9656 "Kill vf vlan filter fail, ret =%u.\n", 9657 req->resp_code); 9658 } 9659 9660 return -EIO; 9661 } 9662 9663 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid, 9664 bool is_kill, u16 vlan) 9665 { 9666 struct hclge_vport *vport = &hdev->vport[vfid]; 9667 struct hclge_desc desc[2]; 9668 int ret; 9669 9670 /* if vf vlan table is full, firmware will close vf vlan filter, it 9671 * is unable and unnecessary to add new vlan id to vf vlan filter. 9672 * If spoof check is enable, and vf vlan is full, it shouldn't add 9673 * new vlan, because tx packets with these vlan id will be dropped. 9674 */ 9675 if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) { 9676 if (vport->vf_info.spoofchk && vlan) { 9677 dev_err(&hdev->pdev->dev, 9678 "Can't add vlan due to spoof check is on and vf vlan table is full\n"); 9679 return -EPERM; 9680 } 9681 return 0; 9682 } 9683 9684 ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc); 9685 if (ret) 9686 return ret; 9687 9688 return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc); 9689 } 9690 9691 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 9692 u16 vlan_id, bool is_kill) 9693 { 9694 struct hclge_vlan_filter_pf_cfg_cmd *req; 9695 struct hclge_desc desc; 9696 u8 vlan_offset_byte_val; 9697 u8 vlan_offset_byte; 9698 u8 vlan_offset_160; 9699 int ret; 9700 9701 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 9702 9703 vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP; 9704 vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) / 9705 HCLGE_VLAN_BYTE_SIZE; 9706 vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE); 9707 9708 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 9709 req->vlan_offset = vlan_offset_160; 9710 req->vlan_cfg = is_kill; 9711 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 9712 9713 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9714 if (ret) 9715 dev_err(&hdev->pdev->dev, 9716 "port vlan command, send fail, ret =%d.\n", ret); 9717 return ret; 9718 } 9719 9720 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id, 9721 u16 vlan_id, bool is_kill) 9722 { 9723 /* vlan 0 may be added twice when 8021q module is enabled */ 9724 if (!is_kill && !vlan_id && 9725 test_bit(vport_id, hdev->vlan_table[vlan_id])) 9726 return false; 9727 9728 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 9729 dev_warn(&hdev->pdev->dev, 9730 "Add port vlan failed, vport %u is already in vlan %u\n", 9731 vport_id, vlan_id); 9732 return false; 9733 } 9734 9735 if (is_kill && 9736 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 9737 dev_warn(&hdev->pdev->dev, 9738 "Delete port vlan failed, vport %u is not in vlan %u\n", 9739 vport_id, vlan_id); 9740 return false; 9741 } 9742 9743 return true; 9744 } 9745 9746 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 9747 u16 vport_id, u16 vlan_id, 9748 bool is_kill) 9749 { 9750 u16 vport_idx, vport_num = 0; 9751 int ret; 9752 9753 if (is_kill && !vlan_id) 9754 return 0; 9755 9756 if (vlan_id >= VLAN_N_VID) 9757 return -EINVAL; 9758 9759 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id); 9760 if (ret) { 9761 dev_err(&hdev->pdev->dev, 9762 "Set %u vport vlan filter config fail, ret =%d.\n", 9763 vport_id, ret); 9764 return ret; 9765 } 9766 9767 if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill)) 9768 return 0; 9769 9770 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 9771 vport_num++; 9772 9773 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 9774 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 9775 is_kill); 9776 9777 return ret; 9778 } 9779 9780 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 9781 { 9782 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 9783 struct hclge_vport_vtag_tx_cfg_cmd *req; 9784 struct hclge_dev *hdev = vport->back; 9785 struct hclge_desc desc; 9786 u16 bmap_index; 9787 int status; 9788 9789 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 9790 9791 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 9792 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 9793 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 9794 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 9795 vcfg->accept_tag1 ? 1 : 0); 9796 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 9797 vcfg->accept_untag1 ? 1 : 0); 9798 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 9799 vcfg->accept_tag2 ? 1 : 0); 9800 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 9801 vcfg->accept_untag2 ? 1 : 0); 9802 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 9803 vcfg->insert_tag1_en ? 1 : 0); 9804 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 9805 vcfg->insert_tag2_en ? 1 : 0); 9806 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B, 9807 vcfg->tag_shift_mode_en ? 1 : 0); 9808 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 9809 9810 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9811 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9812 HCLGE_VF_NUM_PER_BYTE; 9813 req->vf_bitmap[bmap_index] = 9814 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9815 9816 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9817 if (status) 9818 dev_err(&hdev->pdev->dev, 9819 "Send port txvlan cfg command fail, ret =%d\n", 9820 status); 9821 9822 return status; 9823 } 9824 9825 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 9826 { 9827 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 9828 struct hclge_vport_vtag_rx_cfg_cmd *req; 9829 struct hclge_dev *hdev = vport->back; 9830 struct hclge_desc desc; 9831 u16 bmap_index; 9832 int status; 9833 9834 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 9835 9836 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 9837 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 9838 vcfg->strip_tag1_en ? 1 : 0); 9839 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 9840 vcfg->strip_tag2_en ? 1 : 0); 9841 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 9842 vcfg->vlan1_vlan_prionly ? 1 : 0); 9843 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 9844 vcfg->vlan2_vlan_prionly ? 1 : 0); 9845 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B, 9846 vcfg->strip_tag1_discard_en ? 1 : 0); 9847 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B, 9848 vcfg->strip_tag2_discard_en ? 1 : 0); 9849 9850 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9851 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9852 HCLGE_VF_NUM_PER_BYTE; 9853 req->vf_bitmap[bmap_index] = 9854 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9855 9856 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9857 if (status) 9858 dev_err(&hdev->pdev->dev, 9859 "Send port rxvlan cfg command fail, ret =%d\n", 9860 status); 9861 9862 return status; 9863 } 9864 9865 static int hclge_vlan_offload_cfg(struct hclge_vport *vport, 9866 u16 port_base_vlan_state, 9867 u16 vlan_tag, u8 qos) 9868 { 9869 int ret; 9870 9871 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9872 vport->txvlan_cfg.accept_tag1 = true; 9873 vport->txvlan_cfg.insert_tag1_en = false; 9874 vport->txvlan_cfg.default_tag1 = 0; 9875 } else { 9876 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev); 9877 9878 vport->txvlan_cfg.accept_tag1 = 9879 ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3; 9880 vport->txvlan_cfg.insert_tag1_en = true; 9881 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) | 9882 vlan_tag; 9883 } 9884 9885 vport->txvlan_cfg.accept_untag1 = true; 9886 9887 /* accept_tag2 and accept_untag2 are not supported on 9888 * pdev revision(0x20), new revision support them, 9889 * this two fields can not be configured by user. 9890 */ 9891 vport->txvlan_cfg.accept_tag2 = true; 9892 vport->txvlan_cfg.accept_untag2 = true; 9893 vport->txvlan_cfg.insert_tag2_en = false; 9894 vport->txvlan_cfg.default_tag2 = 0; 9895 vport->txvlan_cfg.tag_shift_mode_en = true; 9896 9897 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9898 vport->rxvlan_cfg.strip_tag1_en = false; 9899 vport->rxvlan_cfg.strip_tag2_en = 9900 vport->rxvlan_cfg.rx_vlan_offload_en; 9901 vport->rxvlan_cfg.strip_tag2_discard_en = false; 9902 } else { 9903 vport->rxvlan_cfg.strip_tag1_en = 9904 vport->rxvlan_cfg.rx_vlan_offload_en; 9905 vport->rxvlan_cfg.strip_tag2_en = true; 9906 vport->rxvlan_cfg.strip_tag2_discard_en = true; 9907 } 9908 9909 vport->rxvlan_cfg.strip_tag1_discard_en = false; 9910 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 9911 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 9912 9913 ret = hclge_set_vlan_tx_offload_cfg(vport); 9914 if (ret) 9915 return ret; 9916 9917 return hclge_set_vlan_rx_offload_cfg(vport); 9918 } 9919 9920 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 9921 { 9922 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 9923 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 9924 struct hclge_desc desc; 9925 int status; 9926 9927 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 9928 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 9929 rx_req->ot_fst_vlan_type = 9930 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 9931 rx_req->ot_sec_vlan_type = 9932 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 9933 rx_req->in_fst_vlan_type = 9934 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 9935 rx_req->in_sec_vlan_type = 9936 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 9937 9938 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9939 if (status) { 9940 dev_err(&hdev->pdev->dev, 9941 "Send rxvlan protocol type command fail, ret =%d\n", 9942 status); 9943 return status; 9944 } 9945 9946 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 9947 9948 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data; 9949 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 9950 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 9951 9952 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9953 if (status) 9954 dev_err(&hdev->pdev->dev, 9955 "Send txvlan protocol type command fail, ret =%d\n", 9956 status); 9957 9958 return status; 9959 } 9960 9961 static int hclge_init_vlan_filter(struct hclge_dev *hdev) 9962 { 9963 struct hclge_vport *vport; 9964 int ret; 9965 int i; 9966 9967 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9968 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9969 HCLGE_FILTER_FE_EGRESS_V1_B, 9970 true, 0); 9971 9972 /* for revision 0x21, vf vlan filter is per function */ 9973 for (i = 0; i < hdev->num_alloc_vport; i++) { 9974 vport = &hdev->vport[i]; 9975 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9976 HCLGE_FILTER_FE_EGRESS, true, 9977 vport->vport_id); 9978 if (ret) 9979 return ret; 9980 vport->cur_vlan_fltr_en = true; 9981 } 9982 9983 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9984 HCLGE_FILTER_FE_INGRESS, true, 0); 9985 } 9986 9987 static int hclge_init_vlan_type(struct hclge_dev *hdev) 9988 { 9989 hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q; 9990 hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q; 9991 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q; 9992 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q; 9993 hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q; 9994 hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q; 9995 9996 return hclge_set_vlan_protocol_type(hdev); 9997 } 9998 9999 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev) 10000 { 10001 struct hclge_port_base_vlan_config *cfg; 10002 struct hclge_vport *vport; 10003 int ret; 10004 int i; 10005 10006 for (i = 0; i < hdev->num_alloc_vport; i++) { 10007 vport = &hdev->vport[i]; 10008 cfg = &vport->port_base_vlan_cfg; 10009 10010 ret = hclge_vlan_offload_cfg(vport, cfg->state, 10011 cfg->vlan_info.vlan_tag, 10012 cfg->vlan_info.qos); 10013 if (ret) 10014 return ret; 10015 } 10016 return 0; 10017 } 10018 10019 static int hclge_init_vlan_config(struct hclge_dev *hdev) 10020 { 10021 struct hnae3_handle *handle = &hdev->vport[0].nic; 10022 int ret; 10023 10024 ret = hclge_init_vlan_filter(hdev); 10025 if (ret) 10026 return ret; 10027 10028 ret = hclge_init_vlan_type(hdev); 10029 if (ret) 10030 return ret; 10031 10032 ret = hclge_init_vport_vlan_offload(hdev); 10033 if (ret) 10034 return ret; 10035 10036 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 10037 } 10038 10039 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10040 bool writen_to_tbl) 10041 { 10042 struct hclge_vport_vlan_cfg *vlan, *tmp; 10043 struct hclge_dev *hdev = vport->back; 10044 10045 mutex_lock(&hdev->vport_lock); 10046 10047 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10048 if (vlan->vlan_id == vlan_id) { 10049 mutex_unlock(&hdev->vport_lock); 10050 return; 10051 } 10052 } 10053 10054 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 10055 if (!vlan) { 10056 mutex_unlock(&hdev->vport_lock); 10057 return; 10058 } 10059 10060 vlan->hd_tbl_status = writen_to_tbl; 10061 vlan->vlan_id = vlan_id; 10062 10063 list_add_tail(&vlan->node, &vport->vlan_list); 10064 mutex_unlock(&hdev->vport_lock); 10065 } 10066 10067 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport) 10068 { 10069 struct hclge_vport_vlan_cfg *vlan, *tmp; 10070 struct hclge_dev *hdev = vport->back; 10071 int ret; 10072 10073 mutex_lock(&hdev->vport_lock); 10074 10075 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10076 if (!vlan->hd_tbl_status) { 10077 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10078 vport->vport_id, 10079 vlan->vlan_id, false); 10080 if (ret) { 10081 dev_err(&hdev->pdev->dev, 10082 "restore vport vlan list failed, ret=%d\n", 10083 ret); 10084 10085 mutex_unlock(&hdev->vport_lock); 10086 return ret; 10087 } 10088 } 10089 vlan->hd_tbl_status = true; 10090 } 10091 10092 mutex_unlock(&hdev->vport_lock); 10093 10094 return 0; 10095 } 10096 10097 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10098 bool is_write_tbl) 10099 { 10100 struct hclge_vport_vlan_cfg *vlan, *tmp; 10101 struct hclge_dev *hdev = vport->back; 10102 10103 mutex_lock(&hdev->vport_lock); 10104 10105 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10106 if (vlan->vlan_id == vlan_id) { 10107 if (is_write_tbl && vlan->hd_tbl_status) 10108 hclge_set_vlan_filter_hw(hdev, 10109 htons(ETH_P_8021Q), 10110 vport->vport_id, 10111 vlan_id, 10112 true); 10113 10114 list_del(&vlan->node); 10115 kfree(vlan); 10116 break; 10117 } 10118 } 10119 10120 mutex_unlock(&hdev->vport_lock); 10121 } 10122 10123 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list) 10124 { 10125 struct hclge_vport_vlan_cfg *vlan, *tmp; 10126 struct hclge_dev *hdev = vport->back; 10127 10128 mutex_lock(&hdev->vport_lock); 10129 10130 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10131 if (vlan->hd_tbl_status) 10132 hclge_set_vlan_filter_hw(hdev, 10133 htons(ETH_P_8021Q), 10134 vport->vport_id, 10135 vlan->vlan_id, 10136 true); 10137 10138 vlan->hd_tbl_status = false; 10139 if (is_del_list) { 10140 list_del(&vlan->node); 10141 kfree(vlan); 10142 } 10143 } 10144 clear_bit(vport->vport_id, hdev->vf_vlan_full); 10145 mutex_unlock(&hdev->vport_lock); 10146 } 10147 10148 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev) 10149 { 10150 struct hclge_vport_vlan_cfg *vlan, *tmp; 10151 struct hclge_vport *vport; 10152 int i; 10153 10154 mutex_lock(&hdev->vport_lock); 10155 10156 for (i = 0; i < hdev->num_alloc_vport; i++) { 10157 vport = &hdev->vport[i]; 10158 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10159 list_del(&vlan->node); 10160 kfree(vlan); 10161 } 10162 } 10163 10164 mutex_unlock(&hdev->vport_lock); 10165 } 10166 10167 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev) 10168 { 10169 struct hclge_vlan_info *vlan_info; 10170 struct hclge_vport *vport; 10171 u16 vlan_proto; 10172 u16 vlan_id; 10173 u16 state; 10174 int vf_id; 10175 int ret; 10176 10177 /* PF should restore all vfs port base vlan */ 10178 for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) { 10179 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM]; 10180 vlan_info = vport->port_base_vlan_cfg.tbl_sta ? 10181 &vport->port_base_vlan_cfg.vlan_info : 10182 &vport->port_base_vlan_cfg.old_vlan_info; 10183 10184 vlan_id = vlan_info->vlan_tag; 10185 vlan_proto = vlan_info->vlan_proto; 10186 state = vport->port_base_vlan_cfg.state; 10187 10188 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) { 10189 clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]); 10190 ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto), 10191 vport->vport_id, 10192 vlan_id, false); 10193 vport->port_base_vlan_cfg.tbl_sta = ret == 0; 10194 } 10195 } 10196 } 10197 10198 void hclge_restore_vport_vlan_table(struct hclge_vport *vport) 10199 { 10200 struct hclge_vport_vlan_cfg *vlan, *tmp; 10201 struct hclge_dev *hdev = vport->back; 10202 int ret; 10203 10204 mutex_lock(&hdev->vport_lock); 10205 10206 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10207 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10208 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10209 vport->vport_id, 10210 vlan->vlan_id, false); 10211 if (ret) 10212 break; 10213 vlan->hd_tbl_status = true; 10214 } 10215 } 10216 10217 mutex_unlock(&hdev->vport_lock); 10218 } 10219 10220 /* For global reset and imp reset, hardware will clear the mac table, 10221 * so we change the mac address state from ACTIVE to TO_ADD, then they 10222 * can be restored in the service task after reset complete. Furtherly, 10223 * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to 10224 * be restored after reset, so just remove these mac nodes from mac_list. 10225 */ 10226 static void hclge_mac_node_convert_for_reset(struct list_head *list) 10227 { 10228 struct hclge_mac_node *mac_node, *tmp; 10229 10230 list_for_each_entry_safe(mac_node, tmp, list, node) { 10231 if (mac_node->state == HCLGE_MAC_ACTIVE) { 10232 mac_node->state = HCLGE_MAC_TO_ADD; 10233 } else if (mac_node->state == HCLGE_MAC_TO_DEL) { 10234 list_del(&mac_node->node); 10235 kfree(mac_node); 10236 } 10237 } 10238 } 10239 10240 void hclge_restore_mac_table_common(struct hclge_vport *vport) 10241 { 10242 spin_lock_bh(&vport->mac_list_lock); 10243 10244 hclge_mac_node_convert_for_reset(&vport->uc_mac_list); 10245 hclge_mac_node_convert_for_reset(&vport->mc_mac_list); 10246 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 10247 10248 spin_unlock_bh(&vport->mac_list_lock); 10249 } 10250 10251 static void hclge_restore_hw_table(struct hclge_dev *hdev) 10252 { 10253 struct hclge_vport *vport = &hdev->vport[0]; 10254 struct hnae3_handle *handle = &vport->nic; 10255 10256 hclge_restore_mac_table_common(vport); 10257 hclge_restore_vport_port_base_vlan_config(hdev); 10258 hclge_restore_vport_vlan_table(vport); 10259 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 10260 hclge_restore_fd_entries(handle); 10261 } 10262 10263 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 10264 { 10265 struct hclge_vport *vport = hclge_get_vport(handle); 10266 10267 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10268 vport->rxvlan_cfg.strip_tag1_en = false; 10269 vport->rxvlan_cfg.strip_tag2_en = enable; 10270 vport->rxvlan_cfg.strip_tag2_discard_en = false; 10271 } else { 10272 vport->rxvlan_cfg.strip_tag1_en = enable; 10273 vport->rxvlan_cfg.strip_tag2_en = true; 10274 vport->rxvlan_cfg.strip_tag2_discard_en = true; 10275 } 10276 10277 vport->rxvlan_cfg.strip_tag1_discard_en = false; 10278 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 10279 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 10280 vport->rxvlan_cfg.rx_vlan_offload_en = enable; 10281 10282 return hclge_set_vlan_rx_offload_cfg(vport); 10283 } 10284 10285 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport) 10286 { 10287 struct hclge_dev *hdev = vport->back; 10288 10289 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 10290 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state); 10291 } 10292 10293 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport, 10294 u16 port_base_vlan_state, 10295 struct hclge_vlan_info *new_info, 10296 struct hclge_vlan_info *old_info) 10297 { 10298 struct hclge_dev *hdev = vport->back; 10299 int ret; 10300 10301 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) { 10302 hclge_rm_vport_all_vlan_table(vport, false); 10303 /* force clear VLAN 0 */ 10304 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0); 10305 if (ret) 10306 return ret; 10307 return hclge_set_vlan_filter_hw(hdev, 10308 htons(new_info->vlan_proto), 10309 vport->vport_id, 10310 new_info->vlan_tag, 10311 false); 10312 } 10313 10314 vport->port_base_vlan_cfg.tbl_sta = false; 10315 10316 /* force add VLAN 0 */ 10317 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0); 10318 if (ret) 10319 return ret; 10320 10321 ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto), 10322 vport->vport_id, old_info->vlan_tag, 10323 true); 10324 if (ret) 10325 return ret; 10326 10327 return hclge_add_vport_all_vlan_table(vport); 10328 } 10329 10330 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg, 10331 const struct hclge_vlan_info *old_cfg) 10332 { 10333 if (new_cfg->vlan_tag != old_cfg->vlan_tag) 10334 return true; 10335 10336 if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0)) 10337 return true; 10338 10339 return false; 10340 } 10341 10342 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport, 10343 struct hclge_vlan_info *new_info, 10344 struct hclge_vlan_info *old_info) 10345 { 10346 struct hclge_dev *hdev = vport->back; 10347 int ret; 10348 10349 /* add new VLAN tag */ 10350 ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto), 10351 vport->vport_id, new_info->vlan_tag, 10352 false); 10353 if (ret) 10354 return ret; 10355 10356 vport->port_base_vlan_cfg.tbl_sta = false; 10357 /* remove old VLAN tag */ 10358 if (old_info->vlan_tag == 0) 10359 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, 10360 true, 0); 10361 else 10362 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10363 vport->vport_id, 10364 old_info->vlan_tag, true); 10365 if (ret) 10366 dev_err(&hdev->pdev->dev, 10367 "failed to clear vport%u port base vlan %u, ret = %d.\n", 10368 vport->vport_id, old_info->vlan_tag, ret); 10369 10370 return ret; 10371 } 10372 10373 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 10374 struct hclge_vlan_info *vlan_info) 10375 { 10376 struct hnae3_handle *nic = &vport->nic; 10377 struct hclge_vlan_info *old_vlan_info; 10378 int ret; 10379 10380 old_vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10381 10382 ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag, 10383 vlan_info->qos); 10384 if (ret) 10385 return ret; 10386 10387 if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info)) 10388 goto out; 10389 10390 if (state == HNAE3_PORT_BASE_VLAN_MODIFY) 10391 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info, 10392 old_vlan_info); 10393 else 10394 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info, 10395 old_vlan_info); 10396 if (ret) 10397 return ret; 10398 10399 out: 10400 vport->port_base_vlan_cfg.state = state; 10401 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 10402 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 10403 else 10404 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 10405 10406 vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info; 10407 vport->port_base_vlan_cfg.vlan_info = *vlan_info; 10408 vport->port_base_vlan_cfg.tbl_sta = true; 10409 hclge_set_vport_vlan_fltr_change(vport); 10410 10411 return 0; 10412 } 10413 10414 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport, 10415 enum hnae3_port_base_vlan_state state, 10416 u16 vlan, u8 qos) 10417 { 10418 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10419 if (!vlan && !qos) 10420 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10421 10422 return HNAE3_PORT_BASE_VLAN_ENABLE; 10423 } 10424 10425 if (!vlan && !qos) 10426 return HNAE3_PORT_BASE_VLAN_DISABLE; 10427 10428 if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan && 10429 vport->port_base_vlan_cfg.vlan_info.qos == qos) 10430 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10431 10432 return HNAE3_PORT_BASE_VLAN_MODIFY; 10433 } 10434 10435 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 10436 u16 vlan, u8 qos, __be16 proto) 10437 { 10438 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 10439 struct hclge_vport *vport = hclge_get_vport(handle); 10440 struct hclge_dev *hdev = vport->back; 10441 struct hclge_vlan_info vlan_info; 10442 u16 state; 10443 int ret; 10444 10445 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 10446 return -EOPNOTSUPP; 10447 10448 vport = hclge_get_vf_vport(hdev, vfid); 10449 if (!vport) 10450 return -EINVAL; 10451 10452 /* qos is a 3 bits value, so can not be bigger than 7 */ 10453 if (vlan > VLAN_N_VID - 1 || qos > 7) 10454 return -EINVAL; 10455 if (proto != htons(ETH_P_8021Q)) 10456 return -EPROTONOSUPPORT; 10457 10458 state = hclge_get_port_base_vlan_state(vport, 10459 vport->port_base_vlan_cfg.state, 10460 vlan, qos); 10461 if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE) 10462 return 0; 10463 10464 vlan_info.vlan_tag = vlan; 10465 vlan_info.qos = qos; 10466 vlan_info.vlan_proto = ntohs(proto); 10467 10468 ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info); 10469 if (ret) { 10470 dev_err(&hdev->pdev->dev, 10471 "failed to update port base vlan for vf %d, ret = %d\n", 10472 vfid, ret); 10473 return ret; 10474 } 10475 10476 /* there is a timewindow for PF to know VF unalive, it may 10477 * cause send mailbox fail, but it doesn't matter, VF will 10478 * query it when reinit. 10479 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based 10480 * VLAN state. 10481 */ 10482 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 10483 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 10484 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0], 10485 vport->vport_id, 10486 state, 10487 &vlan_info); 10488 else 10489 set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, 10490 &vport->need_notify); 10491 } 10492 return 0; 10493 } 10494 10495 static void hclge_clear_vf_vlan(struct hclge_dev *hdev) 10496 { 10497 struct hclge_vlan_info *vlan_info; 10498 struct hclge_vport *vport; 10499 int ret; 10500 int vf; 10501 10502 /* clear port base vlan for all vf */ 10503 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 10504 vport = &hdev->vport[vf]; 10505 vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10506 10507 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10508 vport->vport_id, 10509 vlan_info->vlan_tag, true); 10510 if (ret) 10511 dev_err(&hdev->pdev->dev, 10512 "failed to clear vf vlan for vf%d, ret = %d\n", 10513 vf - HCLGE_VF_VPORT_START_NUM, ret); 10514 } 10515 } 10516 10517 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 10518 u16 vlan_id, bool is_kill) 10519 { 10520 struct hclge_vport *vport = hclge_get_vport(handle); 10521 struct hclge_dev *hdev = vport->back; 10522 bool writen_to_tbl = false; 10523 int ret = 0; 10524 10525 /* When device is resetting or reset failed, firmware is unable to 10526 * handle mailbox. Just record the vlan id, and remove it after 10527 * reset finished. 10528 */ 10529 if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 10530 test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) { 10531 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10532 return -EBUSY; 10533 } 10534 10535 /* when port base vlan enabled, we use port base vlan as the vlan 10536 * filter entry. In this case, we don't update vlan filter table 10537 * when user add new vlan or remove exist vlan, just update the vport 10538 * vlan list. The vlan id in vlan list will be writen in vlan filter 10539 * table until port base vlan disabled 10540 */ 10541 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10542 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, 10543 vlan_id, is_kill); 10544 writen_to_tbl = true; 10545 } 10546 10547 if (!ret) { 10548 if (!is_kill) 10549 hclge_add_vport_vlan_table(vport, vlan_id, 10550 writen_to_tbl); 10551 else if (is_kill && vlan_id != 0) 10552 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10553 } else if (is_kill) { 10554 /* when remove hw vlan filter failed, record the vlan id, 10555 * and try to remove it from hw later, to be consistence 10556 * with stack 10557 */ 10558 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10559 } 10560 10561 hclge_set_vport_vlan_fltr_change(vport); 10562 10563 return ret; 10564 } 10565 10566 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev) 10567 { 10568 struct hclge_vport *vport; 10569 int ret; 10570 u16 i; 10571 10572 for (i = 0; i < hdev->num_alloc_vport; i++) { 10573 vport = &hdev->vport[i]; 10574 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10575 &vport->state)) 10576 continue; 10577 10578 ret = hclge_enable_vport_vlan_filter(vport, 10579 vport->req_vlan_fltr_en); 10580 if (ret) { 10581 dev_err(&hdev->pdev->dev, 10582 "failed to sync vlan filter state for vport%u, ret = %d\n", 10583 vport->vport_id, ret); 10584 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10585 &vport->state); 10586 return; 10587 } 10588 } 10589 } 10590 10591 static void hclge_sync_vlan_filter(struct hclge_dev *hdev) 10592 { 10593 #define HCLGE_MAX_SYNC_COUNT 60 10594 10595 int i, ret, sync_cnt = 0; 10596 u16 vlan_id; 10597 10598 /* start from vport 1 for PF is always alive */ 10599 for (i = 0; i < hdev->num_alloc_vport; i++) { 10600 struct hclge_vport *vport = &hdev->vport[i]; 10601 10602 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10603 VLAN_N_VID); 10604 while (vlan_id != VLAN_N_VID) { 10605 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10606 vport->vport_id, vlan_id, 10607 true); 10608 if (ret && ret != -EINVAL) 10609 return; 10610 10611 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10612 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10613 hclge_set_vport_vlan_fltr_change(vport); 10614 10615 sync_cnt++; 10616 if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) 10617 return; 10618 10619 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10620 VLAN_N_VID); 10621 } 10622 } 10623 10624 hclge_sync_vlan_fltr_state(hdev); 10625 } 10626 10627 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps) 10628 { 10629 struct hclge_config_max_frm_size_cmd *req; 10630 struct hclge_desc desc; 10631 10632 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 10633 10634 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 10635 req->max_frm_size = cpu_to_le16(new_mps); 10636 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 10637 10638 return hclge_cmd_send(&hdev->hw, &desc, 1); 10639 } 10640 10641 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 10642 { 10643 struct hclge_vport *vport = hclge_get_vport(handle); 10644 10645 return hclge_set_vport_mtu(vport, new_mtu); 10646 } 10647 10648 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) 10649 { 10650 struct hclge_dev *hdev = vport->back; 10651 int i, max_frm_size, ret; 10652 10653 /* HW supprt 2 layer vlan */ 10654 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 10655 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 10656 max_frm_size > hdev->ae_dev->dev_specs.max_frm_size) 10657 return -EINVAL; 10658 10659 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 10660 mutex_lock(&hdev->vport_lock); 10661 /* VF's mps must fit within hdev->mps */ 10662 if (vport->vport_id && max_frm_size > hdev->mps) { 10663 mutex_unlock(&hdev->vport_lock); 10664 return -EINVAL; 10665 } else if (vport->vport_id) { 10666 vport->mps = max_frm_size; 10667 mutex_unlock(&hdev->vport_lock); 10668 return 0; 10669 } 10670 10671 /* PF's mps must be greater then VF's mps */ 10672 for (i = 1; i < hdev->num_alloc_vport; i++) 10673 if (max_frm_size < hdev->vport[i].mps) { 10674 dev_err(&hdev->pdev->dev, 10675 "failed to set pf mtu for less than vport %d, mps = %u.\n", 10676 i, hdev->vport[i].mps); 10677 mutex_unlock(&hdev->vport_lock); 10678 return -EINVAL; 10679 } 10680 10681 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 10682 10683 ret = hclge_set_mac_mtu(hdev, max_frm_size); 10684 if (ret) { 10685 dev_err(&hdev->pdev->dev, 10686 "Change mtu fail, ret =%d\n", ret); 10687 goto out; 10688 } 10689 10690 hdev->mps = max_frm_size; 10691 vport->mps = max_frm_size; 10692 10693 ret = hclge_buffer_alloc(hdev); 10694 if (ret) 10695 dev_err(&hdev->pdev->dev, 10696 "Allocate buffer fail, ret =%d\n", ret); 10697 10698 out: 10699 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 10700 mutex_unlock(&hdev->vport_lock); 10701 return ret; 10702 } 10703 10704 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id, 10705 bool enable) 10706 { 10707 struct hclge_reset_tqp_queue_cmd *req; 10708 struct hclge_desc desc; 10709 int ret; 10710 10711 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 10712 10713 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10714 req->tqp_id = cpu_to_le16(queue_id); 10715 if (enable) 10716 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U); 10717 10718 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10719 if (ret) { 10720 dev_err(&hdev->pdev->dev, 10721 "Send tqp reset cmd error, status =%d\n", ret); 10722 return ret; 10723 } 10724 10725 return 0; 10726 } 10727 10728 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id, 10729 u8 *reset_status) 10730 { 10731 struct hclge_reset_tqp_queue_cmd *req; 10732 struct hclge_desc desc; 10733 int ret; 10734 10735 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 10736 10737 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10738 req->tqp_id = cpu_to_le16(queue_id); 10739 10740 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10741 if (ret) { 10742 dev_err(&hdev->pdev->dev, 10743 "Get reset status error, status =%d\n", ret); 10744 return ret; 10745 } 10746 10747 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 10748 10749 return 0; 10750 } 10751 10752 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id) 10753 { 10754 struct hclge_comm_tqp *tqp; 10755 struct hnae3_queue *queue; 10756 10757 queue = handle->kinfo.tqp[queue_id]; 10758 tqp = container_of(queue, struct hclge_comm_tqp, q); 10759 10760 return tqp->index; 10761 } 10762 10763 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle) 10764 { 10765 struct hclge_vport *vport = hclge_get_vport(handle); 10766 struct hclge_dev *hdev = vport->back; 10767 u16 reset_try_times = 0; 10768 u8 reset_status; 10769 u16 queue_gid; 10770 int ret; 10771 u16 i; 10772 10773 for (i = 0; i < handle->kinfo.num_tqps; i++) { 10774 queue_gid = hclge_covert_handle_qid_global(handle, i); 10775 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true); 10776 if (ret) { 10777 dev_err(&hdev->pdev->dev, 10778 "failed to send reset tqp cmd, ret = %d\n", 10779 ret); 10780 return ret; 10781 } 10782 10783 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 10784 ret = hclge_get_reset_status(hdev, queue_gid, 10785 &reset_status); 10786 if (ret) 10787 return ret; 10788 10789 if (reset_status) 10790 break; 10791 10792 /* Wait for tqp hw reset */ 10793 usleep_range(1000, 1200); 10794 } 10795 10796 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 10797 dev_err(&hdev->pdev->dev, 10798 "wait for tqp hw reset timeout\n"); 10799 return -ETIME; 10800 } 10801 10802 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false); 10803 if (ret) { 10804 dev_err(&hdev->pdev->dev, 10805 "failed to deassert soft reset, ret = %d\n", 10806 ret); 10807 return ret; 10808 } 10809 reset_try_times = 0; 10810 } 10811 return 0; 10812 } 10813 10814 static int hclge_reset_rcb(struct hnae3_handle *handle) 10815 { 10816 #define HCLGE_RESET_RCB_NOT_SUPPORT 0U 10817 #define HCLGE_RESET_RCB_SUCCESS 1U 10818 10819 struct hclge_vport *vport = hclge_get_vport(handle); 10820 struct hclge_dev *hdev = vport->back; 10821 struct hclge_reset_cmd *req; 10822 struct hclge_desc desc; 10823 u8 return_status; 10824 u16 queue_gid; 10825 int ret; 10826 10827 queue_gid = hclge_covert_handle_qid_global(handle, 0); 10828 10829 req = (struct hclge_reset_cmd *)desc.data; 10830 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 10831 hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1); 10832 req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid); 10833 req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps); 10834 10835 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10836 if (ret) { 10837 dev_err(&hdev->pdev->dev, 10838 "failed to send rcb reset cmd, ret = %d\n", ret); 10839 return ret; 10840 } 10841 10842 return_status = req->fun_reset_rcb_return_status; 10843 if (return_status == HCLGE_RESET_RCB_SUCCESS) 10844 return 0; 10845 10846 if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) { 10847 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n", 10848 return_status); 10849 return -EIO; 10850 } 10851 10852 /* if reset rcb cmd is unsupported, we need to send reset tqp cmd 10853 * again to reset all tqps 10854 */ 10855 return hclge_reset_tqp_cmd(handle); 10856 } 10857 10858 int hclge_reset_tqp(struct hnae3_handle *handle) 10859 { 10860 struct hclge_vport *vport = hclge_get_vport(handle); 10861 struct hclge_dev *hdev = vport->back; 10862 int ret; 10863 10864 /* only need to disable PF's tqp */ 10865 if (!vport->vport_id) { 10866 ret = hclge_tqp_enable(handle, false); 10867 if (ret) { 10868 dev_err(&hdev->pdev->dev, 10869 "failed to disable tqp, ret = %d\n", ret); 10870 return ret; 10871 } 10872 } 10873 10874 return hclge_reset_rcb(handle); 10875 } 10876 10877 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 10878 { 10879 struct hclge_vport *vport = hclge_get_vport(handle); 10880 struct hclge_dev *hdev = vport->back; 10881 10882 return hdev->fw_version; 10883 } 10884 10885 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10886 { 10887 struct phy_device *phydev = hdev->hw.mac.phydev; 10888 10889 if (!phydev) 10890 return; 10891 10892 phy_set_asym_pause(phydev, rx_en, tx_en); 10893 } 10894 10895 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10896 { 10897 int ret; 10898 10899 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 10900 return 0; 10901 10902 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 10903 if (ret) 10904 dev_err(&hdev->pdev->dev, 10905 "configure pauseparam error, ret = %d.\n", ret); 10906 10907 return ret; 10908 } 10909 10910 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 10911 { 10912 struct phy_device *phydev = hdev->hw.mac.phydev; 10913 u16 remote_advertising = 0; 10914 u16 local_advertising; 10915 u32 rx_pause, tx_pause; 10916 u8 flowctl; 10917 10918 if (!phydev->link || !phydev->autoneg) 10919 return 0; 10920 10921 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising); 10922 10923 if (phydev->pause) 10924 remote_advertising = LPA_PAUSE_CAP; 10925 10926 if (phydev->asym_pause) 10927 remote_advertising |= LPA_PAUSE_ASYM; 10928 10929 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 10930 remote_advertising); 10931 tx_pause = flowctl & FLOW_CTRL_TX; 10932 rx_pause = flowctl & FLOW_CTRL_RX; 10933 10934 if (phydev->duplex == HCLGE_MAC_HALF) { 10935 tx_pause = 0; 10936 rx_pause = 0; 10937 } 10938 10939 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 10940 } 10941 10942 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 10943 u32 *rx_en, u32 *tx_en) 10944 { 10945 struct hclge_vport *vport = hclge_get_vport(handle); 10946 struct hclge_dev *hdev = vport->back; 10947 u8 media_type = hdev->hw.mac.media_type; 10948 10949 *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ? 10950 hclge_get_autoneg(handle) : 0; 10951 10952 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 10953 *rx_en = 0; 10954 *tx_en = 0; 10955 return; 10956 } 10957 10958 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 10959 *rx_en = 1; 10960 *tx_en = 0; 10961 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 10962 *tx_en = 1; 10963 *rx_en = 0; 10964 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 10965 *rx_en = 1; 10966 *tx_en = 1; 10967 } else { 10968 *rx_en = 0; 10969 *tx_en = 0; 10970 } 10971 } 10972 10973 static void hclge_record_user_pauseparam(struct hclge_dev *hdev, 10974 u32 rx_en, u32 tx_en) 10975 { 10976 if (rx_en && tx_en) 10977 hdev->fc_mode_last_time = HCLGE_FC_FULL; 10978 else if (rx_en && !tx_en) 10979 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 10980 else if (!rx_en && tx_en) 10981 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 10982 else 10983 hdev->fc_mode_last_time = HCLGE_FC_NONE; 10984 10985 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 10986 } 10987 10988 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 10989 u32 rx_en, u32 tx_en) 10990 { 10991 struct hclge_vport *vport = hclge_get_vport(handle); 10992 struct hclge_dev *hdev = vport->back; 10993 struct phy_device *phydev = hdev->hw.mac.phydev; 10994 u32 fc_autoneg; 10995 10996 if (phydev || hnae3_dev_phy_imp_supported(hdev)) { 10997 fc_autoneg = hclge_get_autoneg(handle); 10998 if (auto_neg != fc_autoneg) { 10999 dev_info(&hdev->pdev->dev, 11000 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 11001 return -EOPNOTSUPP; 11002 } 11003 } 11004 11005 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 11006 dev_info(&hdev->pdev->dev, 11007 "Priority flow control enabled. Cannot set link flow control.\n"); 11008 return -EOPNOTSUPP; 11009 } 11010 11011 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 11012 11013 hclge_record_user_pauseparam(hdev, rx_en, tx_en); 11014 11015 if (!auto_neg || hnae3_dev_phy_imp_supported(hdev)) 11016 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 11017 11018 if (phydev) 11019 return phy_start_aneg(phydev); 11020 11021 return -EOPNOTSUPP; 11022 } 11023 11024 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 11025 u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num) 11026 { 11027 struct hclge_vport *vport = hclge_get_vport(handle); 11028 struct hclge_dev *hdev = vport->back; 11029 11030 if (speed) 11031 *speed = hdev->hw.mac.speed; 11032 if (duplex) 11033 *duplex = hdev->hw.mac.duplex; 11034 if (auto_neg) 11035 *auto_neg = hdev->hw.mac.autoneg; 11036 if (lane_num) 11037 *lane_num = hdev->hw.mac.lane_num; 11038 } 11039 11040 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type, 11041 u8 *module_type) 11042 { 11043 struct hclge_vport *vport = hclge_get_vport(handle); 11044 struct hclge_dev *hdev = vport->back; 11045 11046 /* When nic is down, the service task is not running, doesn't update 11047 * the port information per second. Query the port information before 11048 * return the media type, ensure getting the correct media information. 11049 */ 11050 hclge_update_port_info(hdev); 11051 11052 if (media_type) 11053 *media_type = hdev->hw.mac.media_type; 11054 11055 if (module_type) 11056 *module_type = hdev->hw.mac.module_type; 11057 } 11058 11059 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 11060 u8 *tp_mdix_ctrl, u8 *tp_mdix) 11061 { 11062 struct hclge_vport *vport = hclge_get_vport(handle); 11063 struct hclge_dev *hdev = vport->back; 11064 struct phy_device *phydev = hdev->hw.mac.phydev; 11065 int mdix_ctrl, mdix, is_resolved; 11066 unsigned int retval; 11067 11068 if (!phydev) { 11069 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11070 *tp_mdix = ETH_TP_MDI_INVALID; 11071 return; 11072 } 11073 11074 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 11075 11076 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 11077 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 11078 HCLGE_PHY_MDIX_CTRL_S); 11079 11080 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 11081 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 11082 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 11083 11084 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 11085 11086 switch (mdix_ctrl) { 11087 case 0x0: 11088 *tp_mdix_ctrl = ETH_TP_MDI; 11089 break; 11090 case 0x1: 11091 *tp_mdix_ctrl = ETH_TP_MDI_X; 11092 break; 11093 case 0x3: 11094 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 11095 break; 11096 default: 11097 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11098 break; 11099 } 11100 11101 if (!is_resolved) 11102 *tp_mdix = ETH_TP_MDI_INVALID; 11103 else if (mdix) 11104 *tp_mdix = ETH_TP_MDI_X; 11105 else 11106 *tp_mdix = ETH_TP_MDI; 11107 } 11108 11109 static void hclge_info_show(struct hclge_dev *hdev) 11110 { 11111 struct device *dev = &hdev->pdev->dev; 11112 11113 dev_info(dev, "PF info begin:\n"); 11114 11115 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 11116 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 11117 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 11118 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 11119 dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs); 11120 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 11121 dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size); 11122 dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size); 11123 dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size); 11124 dev_info(dev, "This is %s PF\n", 11125 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main"); 11126 dev_info(dev, "DCB %s\n", 11127 hdev->flag & HCLGE_FLAG_DCB_ENABLE ? "enable" : "disable"); 11128 dev_info(dev, "MQPRIO %s\n", 11129 hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE ? "enable" : "disable"); 11130 dev_info(dev, "Default tx spare buffer size: %u\n", 11131 hdev->tx_spare_buf_size); 11132 11133 dev_info(dev, "PF info end.\n"); 11134 } 11135 11136 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 11137 struct hclge_vport *vport) 11138 { 11139 struct hnae3_client *client = vport->nic.client; 11140 struct hclge_dev *hdev = ae_dev->priv; 11141 int rst_cnt = hdev->rst_stats.reset_cnt; 11142 int ret; 11143 11144 ret = client->ops->init_instance(&vport->nic); 11145 if (ret) 11146 return ret; 11147 11148 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11149 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11150 rst_cnt != hdev->rst_stats.reset_cnt) { 11151 ret = -EBUSY; 11152 goto init_nic_err; 11153 } 11154 11155 /* Enable nic hw error interrupts */ 11156 ret = hclge_config_nic_hw_error(hdev, true); 11157 if (ret) { 11158 dev_err(&ae_dev->pdev->dev, 11159 "fail(%d) to enable hw error interrupts\n", ret); 11160 goto init_nic_err; 11161 } 11162 11163 hnae3_set_client_init_flag(client, ae_dev, 1); 11164 11165 if (netif_msg_drv(&hdev->vport->nic)) 11166 hclge_info_show(hdev); 11167 11168 return ret; 11169 11170 init_nic_err: 11171 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11172 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11173 msleep(HCLGE_WAIT_RESET_DONE); 11174 11175 client->ops->uninit_instance(&vport->nic, 0); 11176 11177 return ret; 11178 } 11179 11180 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 11181 struct hclge_vport *vport) 11182 { 11183 struct hclge_dev *hdev = ae_dev->priv; 11184 struct hnae3_client *client; 11185 int rst_cnt; 11186 int ret; 11187 11188 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 11189 !hdev->nic_client) 11190 return 0; 11191 11192 client = hdev->roce_client; 11193 ret = hclge_init_roce_base_info(vport); 11194 if (ret) 11195 return ret; 11196 11197 rst_cnt = hdev->rst_stats.reset_cnt; 11198 ret = client->ops->init_instance(&vport->roce); 11199 if (ret) 11200 return ret; 11201 11202 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11203 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11204 rst_cnt != hdev->rst_stats.reset_cnt) { 11205 ret = -EBUSY; 11206 goto init_roce_err; 11207 } 11208 11209 /* Enable roce ras interrupts */ 11210 ret = hclge_config_rocee_ras_interrupt(hdev, true); 11211 if (ret) { 11212 dev_err(&ae_dev->pdev->dev, 11213 "fail(%d) to enable roce ras interrupts\n", ret); 11214 goto init_roce_err; 11215 } 11216 11217 hnae3_set_client_init_flag(client, ae_dev, 1); 11218 11219 return 0; 11220 11221 init_roce_err: 11222 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11223 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11224 msleep(HCLGE_WAIT_RESET_DONE); 11225 11226 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11227 11228 return ret; 11229 } 11230 11231 static int hclge_init_client_instance(struct hnae3_client *client, 11232 struct hnae3_ae_dev *ae_dev) 11233 { 11234 struct hclge_dev *hdev = ae_dev->priv; 11235 struct hclge_vport *vport = &hdev->vport[0]; 11236 int ret; 11237 11238 switch (client->type) { 11239 case HNAE3_CLIENT_KNIC: 11240 hdev->nic_client = client; 11241 vport->nic.client = client; 11242 ret = hclge_init_nic_client_instance(ae_dev, vport); 11243 if (ret) 11244 goto clear_nic; 11245 11246 ret = hclge_init_roce_client_instance(ae_dev, vport); 11247 if (ret) 11248 goto clear_roce; 11249 11250 break; 11251 case HNAE3_CLIENT_ROCE: 11252 if (hnae3_dev_roce_supported(hdev)) { 11253 hdev->roce_client = client; 11254 vport->roce.client = client; 11255 } 11256 11257 ret = hclge_init_roce_client_instance(ae_dev, vport); 11258 if (ret) 11259 goto clear_roce; 11260 11261 break; 11262 default: 11263 return -EINVAL; 11264 } 11265 11266 return 0; 11267 11268 clear_nic: 11269 hdev->nic_client = NULL; 11270 vport->nic.client = NULL; 11271 return ret; 11272 clear_roce: 11273 hdev->roce_client = NULL; 11274 vport->roce.client = NULL; 11275 return ret; 11276 } 11277 11278 static void hclge_uninit_client_instance(struct hnae3_client *client, 11279 struct hnae3_ae_dev *ae_dev) 11280 { 11281 struct hclge_dev *hdev = ae_dev->priv; 11282 struct hclge_vport *vport = &hdev->vport[0]; 11283 11284 if (hdev->roce_client) { 11285 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11286 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11287 msleep(HCLGE_WAIT_RESET_DONE); 11288 11289 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11290 hdev->roce_client = NULL; 11291 vport->roce.client = NULL; 11292 } 11293 if (client->type == HNAE3_CLIENT_ROCE) 11294 return; 11295 if (hdev->nic_client && client->ops->uninit_instance) { 11296 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11297 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11298 msleep(HCLGE_WAIT_RESET_DONE); 11299 11300 client->ops->uninit_instance(&vport->nic, 0); 11301 hdev->nic_client = NULL; 11302 vport->nic.client = NULL; 11303 } 11304 } 11305 11306 static int hclge_dev_mem_map(struct hclge_dev *hdev) 11307 { 11308 struct pci_dev *pdev = hdev->pdev; 11309 struct hclge_hw *hw = &hdev->hw; 11310 11311 /* for device does not have device memory, return directly */ 11312 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR))) 11313 return 0; 11314 11315 hw->hw.mem_base = 11316 devm_ioremap_wc(&pdev->dev, 11317 pci_resource_start(pdev, HCLGE_MEM_BAR), 11318 pci_resource_len(pdev, HCLGE_MEM_BAR)); 11319 if (!hw->hw.mem_base) { 11320 dev_err(&pdev->dev, "failed to map device memory\n"); 11321 return -EFAULT; 11322 } 11323 11324 return 0; 11325 } 11326 11327 static int hclge_pci_init(struct hclge_dev *hdev) 11328 { 11329 struct pci_dev *pdev = hdev->pdev; 11330 struct hclge_hw *hw; 11331 int ret; 11332 11333 ret = pci_enable_device(pdev); 11334 if (ret) { 11335 dev_err(&pdev->dev, "failed to enable PCI device\n"); 11336 return ret; 11337 } 11338 11339 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 11340 if (ret) { 11341 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 11342 if (ret) { 11343 dev_err(&pdev->dev, 11344 "can't set consistent PCI DMA"); 11345 goto err_disable_device; 11346 } 11347 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 11348 } 11349 11350 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 11351 if (ret) { 11352 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 11353 goto err_disable_device; 11354 } 11355 11356 pci_set_master(pdev); 11357 hw = &hdev->hw; 11358 hw->hw.io_base = pcim_iomap(pdev, 2, 0); 11359 if (!hw->hw.io_base) { 11360 dev_err(&pdev->dev, "Can't map configuration register space\n"); 11361 ret = -ENOMEM; 11362 goto err_release_regions; 11363 } 11364 11365 ret = hclge_dev_mem_map(hdev); 11366 if (ret) 11367 goto err_unmap_io_base; 11368 11369 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 11370 11371 return 0; 11372 11373 err_unmap_io_base: 11374 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11375 err_release_regions: 11376 pci_release_regions(pdev); 11377 err_disable_device: 11378 pci_disable_device(pdev); 11379 11380 return ret; 11381 } 11382 11383 static void hclge_pci_uninit(struct hclge_dev *hdev) 11384 { 11385 struct pci_dev *pdev = hdev->pdev; 11386 11387 if (hdev->hw.hw.mem_base) 11388 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 11389 11390 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11391 pci_free_irq_vectors(pdev); 11392 pci_release_mem_regions(pdev); 11393 pci_disable_device(pdev); 11394 } 11395 11396 static void hclge_state_init(struct hclge_dev *hdev) 11397 { 11398 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 11399 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11400 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 11401 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11402 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 11403 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 11404 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 11405 } 11406 11407 static void hclge_state_uninit(struct hclge_dev *hdev) 11408 { 11409 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11410 set_bit(HCLGE_STATE_REMOVING, &hdev->state); 11411 11412 if (hdev->reset_timer.function) 11413 del_timer_sync(&hdev->reset_timer); 11414 if (hdev->service_task.work.func) 11415 cancel_delayed_work_sync(&hdev->service_task); 11416 } 11417 11418 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 11419 enum hnae3_reset_type rst_type) 11420 { 11421 #define HCLGE_RESET_RETRY_WAIT_MS 500 11422 #define HCLGE_RESET_RETRY_CNT 5 11423 11424 struct hclge_dev *hdev = ae_dev->priv; 11425 int retry_cnt = 0; 11426 int ret; 11427 11428 while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) { 11429 down(&hdev->reset_sem); 11430 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11431 hdev->reset_type = rst_type; 11432 ret = hclge_reset_prepare(hdev); 11433 if (!ret && !hdev->reset_pending) 11434 break; 11435 11436 dev_err(&hdev->pdev->dev, 11437 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 11438 ret, hdev->reset_pending, retry_cnt); 11439 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11440 up(&hdev->reset_sem); 11441 msleep(HCLGE_RESET_RETRY_WAIT_MS); 11442 } 11443 11444 /* disable misc vector before reset done */ 11445 hclge_enable_vector(&hdev->misc_vector, false); 11446 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 11447 11448 if (hdev->reset_type == HNAE3_FLR_RESET) 11449 hdev->rst_stats.flr_rst_cnt++; 11450 } 11451 11452 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev) 11453 { 11454 struct hclge_dev *hdev = ae_dev->priv; 11455 int ret; 11456 11457 hclge_enable_vector(&hdev->misc_vector, true); 11458 11459 ret = hclge_reset_rebuild(hdev); 11460 if (ret) 11461 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret); 11462 11463 hdev->reset_type = HNAE3_NONE_RESET; 11464 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11465 up(&hdev->reset_sem); 11466 } 11467 11468 static void hclge_clear_resetting_state(struct hclge_dev *hdev) 11469 { 11470 u16 i; 11471 11472 for (i = 0; i < hdev->num_alloc_vport; i++) { 11473 struct hclge_vport *vport = &hdev->vport[i]; 11474 int ret; 11475 11476 /* Send cmd to clear vport's FUNC_RST_ING */ 11477 ret = hclge_set_vf_rst(hdev, vport->vport_id, false); 11478 if (ret) 11479 dev_warn(&hdev->pdev->dev, 11480 "clear vport(%u) rst failed %d!\n", 11481 vport->vport_id, ret); 11482 } 11483 } 11484 11485 static int hclge_clear_hw_resource(struct hclge_dev *hdev) 11486 { 11487 struct hclge_desc desc; 11488 int ret; 11489 11490 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false); 11491 11492 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11493 /* This new command is only supported by new firmware, it will 11494 * fail with older firmware. Error value -EOPNOSUPP can only be 11495 * returned by older firmware running this command, to keep code 11496 * backward compatible we will override this value and return 11497 * success. 11498 */ 11499 if (ret && ret != -EOPNOTSUPP) { 11500 dev_err(&hdev->pdev->dev, 11501 "failed to clear hw resource, ret = %d\n", ret); 11502 return ret; 11503 } 11504 return 0; 11505 } 11506 11507 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev) 11508 { 11509 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11510 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1); 11511 } 11512 11513 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev) 11514 { 11515 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11516 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0); 11517 } 11518 11519 static struct hclge_wol_info *hclge_get_wol_info(struct hnae3_handle *handle) 11520 { 11521 struct hclge_vport *vport = hclge_get_vport(handle); 11522 11523 return &vport->back->hw.mac.wol; 11524 } 11525 11526 static int hclge_get_wol_supported_mode(struct hclge_dev *hdev, 11527 u32 *wol_supported) 11528 { 11529 struct hclge_query_wol_supported_cmd *wol_supported_cmd; 11530 struct hclge_desc desc; 11531 int ret; 11532 11533 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_GET_SUPPORTED_MODE, 11534 true); 11535 wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)desc.data; 11536 11537 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11538 if (ret) { 11539 dev_err(&hdev->pdev->dev, 11540 "failed to query wol supported, ret = %d\n", ret); 11541 return ret; 11542 } 11543 11544 *wol_supported = le32_to_cpu(wol_supported_cmd->supported_wake_mode); 11545 11546 return 0; 11547 } 11548 11549 static int hclge_set_wol_cfg(struct hclge_dev *hdev, 11550 struct hclge_wol_info *wol_info) 11551 { 11552 struct hclge_wol_cfg_cmd *wol_cfg_cmd; 11553 struct hclge_desc desc; 11554 int ret; 11555 11556 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, false); 11557 wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)desc.data; 11558 wol_cfg_cmd->wake_on_lan_mode = cpu_to_le32(wol_info->wol_current_mode); 11559 wol_cfg_cmd->sopass_size = wol_info->wol_sopass_size; 11560 memcpy(wol_cfg_cmd->sopass, wol_info->wol_sopass, SOPASS_MAX); 11561 11562 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11563 if (ret) 11564 dev_err(&hdev->pdev->dev, 11565 "failed to set wol config, ret = %d\n", ret); 11566 11567 return ret; 11568 } 11569 11570 static int hclge_update_wol(struct hclge_dev *hdev) 11571 { 11572 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11573 11574 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11575 return 0; 11576 11577 return hclge_set_wol_cfg(hdev, wol_info); 11578 } 11579 11580 static int hclge_init_wol(struct hclge_dev *hdev) 11581 { 11582 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11583 int ret; 11584 11585 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11586 return 0; 11587 11588 memset(wol_info, 0, sizeof(struct hclge_wol_info)); 11589 ret = hclge_get_wol_supported_mode(hdev, 11590 &wol_info->wol_support_mode); 11591 if (ret) { 11592 wol_info->wol_support_mode = 0; 11593 return ret; 11594 } 11595 11596 return hclge_update_wol(hdev); 11597 } 11598 11599 static void hclge_get_wol(struct hnae3_handle *handle, 11600 struct ethtool_wolinfo *wol) 11601 { 11602 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11603 11604 wol->supported = wol_info->wol_support_mode; 11605 wol->wolopts = wol_info->wol_current_mode; 11606 if (wol_info->wol_current_mode & WAKE_MAGICSECURE) 11607 memcpy(wol->sopass, wol_info->wol_sopass, SOPASS_MAX); 11608 } 11609 11610 static int hclge_set_wol(struct hnae3_handle *handle, 11611 struct ethtool_wolinfo *wol) 11612 { 11613 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11614 struct hclge_vport *vport = hclge_get_vport(handle); 11615 u32 wol_mode; 11616 int ret; 11617 11618 wol_mode = wol->wolopts; 11619 if (wol_mode & ~wol_info->wol_support_mode) 11620 return -EINVAL; 11621 11622 wol_info->wol_current_mode = wol_mode; 11623 if (wol_mode & WAKE_MAGICSECURE) { 11624 memcpy(wol_info->wol_sopass, wol->sopass, SOPASS_MAX); 11625 wol_info->wol_sopass_size = SOPASS_MAX; 11626 } else { 11627 wol_info->wol_sopass_size = 0; 11628 } 11629 11630 ret = hclge_set_wol_cfg(vport->back, wol_info); 11631 if (ret) 11632 wol_info->wol_current_mode = 0; 11633 11634 return ret; 11635 } 11636 11637 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 11638 { 11639 struct pci_dev *pdev = ae_dev->pdev; 11640 struct hclge_dev *hdev; 11641 int ret; 11642 11643 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 11644 if (!hdev) 11645 return -ENOMEM; 11646 11647 hdev->pdev = pdev; 11648 hdev->ae_dev = ae_dev; 11649 hdev->reset_type = HNAE3_NONE_RESET; 11650 hdev->reset_level = HNAE3_FUNC_RESET; 11651 ae_dev->priv = hdev; 11652 11653 /* HW supprt 2 layer vlan */ 11654 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 11655 11656 mutex_init(&hdev->vport_lock); 11657 spin_lock_init(&hdev->fd_rule_lock); 11658 sema_init(&hdev->reset_sem, 1); 11659 11660 ret = hclge_pci_init(hdev); 11661 if (ret) 11662 goto out; 11663 11664 ret = hclge_devlink_init(hdev); 11665 if (ret) 11666 goto err_pci_uninit; 11667 11668 /* Firmware command queue initialize */ 11669 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 11670 if (ret) 11671 goto err_devlink_uninit; 11672 11673 /* Firmware command initialize */ 11674 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 11675 true, hdev->reset_pending); 11676 if (ret) 11677 goto err_cmd_uninit; 11678 11679 ret = hclge_clear_hw_resource(hdev); 11680 if (ret) 11681 goto err_cmd_uninit; 11682 11683 ret = hclge_get_cap(hdev); 11684 if (ret) 11685 goto err_cmd_uninit; 11686 11687 ret = hclge_query_dev_specs(hdev); 11688 if (ret) { 11689 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n", 11690 ret); 11691 goto err_cmd_uninit; 11692 } 11693 11694 ret = hclge_configure(hdev); 11695 if (ret) { 11696 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 11697 goto err_cmd_uninit; 11698 } 11699 11700 ret = hclge_init_msi(hdev); 11701 if (ret) { 11702 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 11703 goto err_cmd_uninit; 11704 } 11705 11706 ret = hclge_misc_irq_init(hdev); 11707 if (ret) 11708 goto err_msi_uninit; 11709 11710 ret = hclge_alloc_tqps(hdev); 11711 if (ret) { 11712 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 11713 goto err_msi_irq_uninit; 11714 } 11715 11716 ret = hclge_alloc_vport(hdev); 11717 if (ret) 11718 goto err_msi_irq_uninit; 11719 11720 ret = hclge_map_tqp(hdev); 11721 if (ret) 11722 goto err_msi_irq_uninit; 11723 11724 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { 11725 if (hnae3_dev_phy_imp_supported(hdev)) 11726 ret = hclge_update_tp_port_info(hdev); 11727 else 11728 ret = hclge_mac_mdio_config(hdev); 11729 11730 if (ret) 11731 goto err_msi_irq_uninit; 11732 } 11733 11734 ret = hclge_init_umv_space(hdev); 11735 if (ret) 11736 goto err_mdiobus_unreg; 11737 11738 ret = hclge_mac_init(hdev); 11739 if (ret) { 11740 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 11741 goto err_mdiobus_unreg; 11742 } 11743 11744 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 11745 if (ret) { 11746 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 11747 goto err_mdiobus_unreg; 11748 } 11749 11750 ret = hclge_config_gro(hdev); 11751 if (ret) 11752 goto err_mdiobus_unreg; 11753 11754 ret = hclge_init_vlan_config(hdev); 11755 if (ret) { 11756 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 11757 goto err_mdiobus_unreg; 11758 } 11759 11760 ret = hclge_tm_schd_init(hdev); 11761 if (ret) { 11762 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 11763 goto err_mdiobus_unreg; 11764 } 11765 11766 ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev, 11767 &hdev->rss_cfg); 11768 if (ret) { 11769 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 11770 goto err_mdiobus_unreg; 11771 } 11772 11773 ret = hclge_rss_init_hw(hdev); 11774 if (ret) { 11775 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 11776 goto err_mdiobus_unreg; 11777 } 11778 11779 ret = init_mgr_tbl(hdev); 11780 if (ret) { 11781 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 11782 goto err_mdiobus_unreg; 11783 } 11784 11785 ret = hclge_init_fd_config(hdev); 11786 if (ret) { 11787 dev_err(&pdev->dev, 11788 "fd table init fail, ret=%d\n", ret); 11789 goto err_mdiobus_unreg; 11790 } 11791 11792 ret = hclge_ptp_init(hdev); 11793 if (ret) 11794 goto err_mdiobus_unreg; 11795 11796 ret = hclge_update_port_info(hdev); 11797 if (ret) 11798 goto err_mdiobus_unreg; 11799 11800 INIT_KFIFO(hdev->mac_tnl_log); 11801 11802 hclge_dcb_ops_set(hdev); 11803 11804 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0); 11805 INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task); 11806 11807 hclge_clear_all_event_cause(hdev); 11808 hclge_clear_resetting_state(hdev); 11809 11810 /* Log and clear the hw errors those already occurred */ 11811 if (hnae3_dev_ras_imp_supported(hdev)) 11812 hclge_handle_occurred_error(hdev); 11813 else 11814 hclge_handle_all_hns_hw_errors(ae_dev); 11815 11816 /* request delayed reset for the error recovery because an immediate 11817 * global reset on a PF affecting pending initialization of other PFs 11818 */ 11819 if (ae_dev->hw_err_reset_req) { 11820 enum hnae3_reset_type reset_level; 11821 11822 reset_level = hclge_get_reset_level(ae_dev, 11823 &ae_dev->hw_err_reset_req); 11824 hclge_set_def_reset_request(ae_dev, reset_level); 11825 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 11826 } 11827 11828 hclge_init_rxd_adv_layout(hdev); 11829 11830 /* Enable MISC vector(vector0) */ 11831 hclge_enable_vector(&hdev->misc_vector, true); 11832 11833 ret = hclge_init_wol(hdev); 11834 if (ret) 11835 dev_warn(&pdev->dev, 11836 "failed to wake on lan init, ret = %d\n", ret); 11837 11838 hclge_state_init(hdev); 11839 hdev->last_reset_time = jiffies; 11840 11841 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", 11842 HCLGE_DRIVER_NAME); 11843 11844 hclge_task_schedule(hdev, round_jiffies_relative(HZ)); 11845 11846 return 0; 11847 11848 err_mdiobus_unreg: 11849 if (hdev->hw.mac.phydev) 11850 mdiobus_unregister(hdev->hw.mac.mdio_bus); 11851 err_msi_irq_uninit: 11852 hclge_misc_irq_uninit(hdev); 11853 err_msi_uninit: 11854 pci_free_irq_vectors(pdev); 11855 err_cmd_uninit: 11856 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 11857 err_devlink_uninit: 11858 hclge_devlink_uninit(hdev); 11859 err_pci_uninit: 11860 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11861 pci_release_regions(pdev); 11862 pci_disable_device(pdev); 11863 out: 11864 mutex_destroy(&hdev->vport_lock); 11865 return ret; 11866 } 11867 11868 static void hclge_stats_clear(struct hclge_dev *hdev) 11869 { 11870 memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats)); 11871 memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats)); 11872 } 11873 11874 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11875 { 11876 return hclge_config_switch_param(hdev, vf, enable, 11877 HCLGE_SWITCH_ANTI_SPOOF_MASK); 11878 } 11879 11880 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11881 { 11882 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 11883 HCLGE_FILTER_FE_NIC_INGRESS_B, 11884 enable, vf); 11885 } 11886 11887 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) 11888 { 11889 int ret; 11890 11891 ret = hclge_set_mac_spoofchk(hdev, vf, enable); 11892 if (ret) { 11893 dev_err(&hdev->pdev->dev, 11894 "Set vf %d mac spoof check %s failed, ret=%d\n", 11895 vf, enable ? "on" : "off", ret); 11896 return ret; 11897 } 11898 11899 ret = hclge_set_vlan_spoofchk(hdev, vf, enable); 11900 if (ret) 11901 dev_err(&hdev->pdev->dev, 11902 "Set vf %d vlan spoof check %s failed, ret=%d\n", 11903 vf, enable ? "on" : "off", ret); 11904 11905 return ret; 11906 } 11907 11908 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf, 11909 bool enable) 11910 { 11911 struct hclge_vport *vport = hclge_get_vport(handle); 11912 struct hclge_dev *hdev = vport->back; 11913 u32 new_spoofchk = enable ? 1 : 0; 11914 int ret; 11915 11916 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11917 return -EOPNOTSUPP; 11918 11919 vport = hclge_get_vf_vport(hdev, vf); 11920 if (!vport) 11921 return -EINVAL; 11922 11923 if (vport->vf_info.spoofchk == new_spoofchk) 11924 return 0; 11925 11926 if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full)) 11927 dev_warn(&hdev->pdev->dev, 11928 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n", 11929 vf); 11930 else if (enable && hclge_is_umv_space_full(vport, true)) 11931 dev_warn(&hdev->pdev->dev, 11932 "vf %d mac table is full, enable spoof check may cause its packet send fail\n", 11933 vf); 11934 11935 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable); 11936 if (ret) 11937 return ret; 11938 11939 vport->vf_info.spoofchk = new_spoofchk; 11940 return 0; 11941 } 11942 11943 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev) 11944 { 11945 struct hclge_vport *vport = hdev->vport; 11946 int ret; 11947 int i; 11948 11949 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11950 return 0; 11951 11952 /* resume the vf spoof check state after reset */ 11953 for (i = 0; i < hdev->num_alloc_vport; i++) { 11954 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, 11955 vport->vf_info.spoofchk); 11956 if (ret) 11957 return ret; 11958 11959 vport++; 11960 } 11961 11962 return 0; 11963 } 11964 11965 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable) 11966 { 11967 struct hclge_vport *vport = hclge_get_vport(handle); 11968 struct hclge_dev *hdev = vport->back; 11969 u32 new_trusted = enable ? 1 : 0; 11970 11971 vport = hclge_get_vf_vport(hdev, vf); 11972 if (!vport) 11973 return -EINVAL; 11974 11975 if (vport->vf_info.trusted == new_trusted) 11976 return 0; 11977 11978 vport->vf_info.trusted = new_trusted; 11979 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 11980 hclge_task_schedule(hdev, 0); 11981 11982 return 0; 11983 } 11984 11985 static void hclge_reset_vf_rate(struct hclge_dev *hdev) 11986 { 11987 int ret; 11988 int vf; 11989 11990 /* reset vf rate to default value */ 11991 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 11992 struct hclge_vport *vport = &hdev->vport[vf]; 11993 11994 vport->vf_info.max_tx_rate = 0; 11995 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); 11996 if (ret) 11997 dev_err(&hdev->pdev->dev, 11998 "vf%d failed to reset to default, ret=%d\n", 11999 vf - HCLGE_VF_VPORT_START_NUM, ret); 12000 } 12001 } 12002 12003 static int hclge_vf_rate_param_check(struct hclge_dev *hdev, 12004 int min_tx_rate, int max_tx_rate) 12005 { 12006 if (min_tx_rate != 0 || 12007 max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) { 12008 dev_err(&hdev->pdev->dev, 12009 "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n", 12010 min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed); 12011 return -EINVAL; 12012 } 12013 12014 return 0; 12015 } 12016 12017 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf, 12018 int min_tx_rate, int max_tx_rate, bool force) 12019 { 12020 struct hclge_vport *vport = hclge_get_vport(handle); 12021 struct hclge_dev *hdev = vport->back; 12022 int ret; 12023 12024 ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate); 12025 if (ret) 12026 return ret; 12027 12028 vport = hclge_get_vf_vport(hdev, vf); 12029 if (!vport) 12030 return -EINVAL; 12031 12032 if (!force && max_tx_rate == vport->vf_info.max_tx_rate) 12033 return 0; 12034 12035 ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); 12036 if (ret) 12037 return ret; 12038 12039 vport->vf_info.max_tx_rate = max_tx_rate; 12040 12041 return 0; 12042 } 12043 12044 static int hclge_resume_vf_rate(struct hclge_dev *hdev) 12045 { 12046 struct hnae3_handle *handle = &hdev->vport->nic; 12047 struct hclge_vport *vport; 12048 int ret; 12049 int vf; 12050 12051 /* resume the vf max_tx_rate after reset */ 12052 for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) { 12053 vport = hclge_get_vf_vport(hdev, vf); 12054 if (!vport) 12055 return -EINVAL; 12056 12057 /* zero means max rate, after reset, firmware already set it to 12058 * max rate, so just continue. 12059 */ 12060 if (!vport->vf_info.max_tx_rate) 12061 continue; 12062 12063 ret = hclge_set_vf_rate(handle, vf, 0, 12064 vport->vf_info.max_tx_rate, true); 12065 if (ret) { 12066 dev_err(&hdev->pdev->dev, 12067 "vf%d failed to resume tx_rate:%u, ret=%d\n", 12068 vf, vport->vf_info.max_tx_rate, ret); 12069 return ret; 12070 } 12071 } 12072 12073 return 0; 12074 } 12075 12076 static void hclge_reset_vport_state(struct hclge_dev *hdev) 12077 { 12078 struct hclge_vport *vport = hdev->vport; 12079 int i; 12080 12081 for (i = 0; i < hdev->num_alloc_vport; i++) { 12082 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12083 vport++; 12084 } 12085 } 12086 12087 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 12088 { 12089 struct hclge_dev *hdev = ae_dev->priv; 12090 struct pci_dev *pdev = ae_dev->pdev; 12091 int ret; 12092 12093 set_bit(HCLGE_STATE_DOWN, &hdev->state); 12094 12095 hclge_stats_clear(hdev); 12096 /* NOTE: pf reset needn't to clear or restore pf and vf table entry. 12097 * so here should not clean table in memory. 12098 */ 12099 if (hdev->reset_type == HNAE3_IMP_RESET || 12100 hdev->reset_type == HNAE3_GLOBAL_RESET) { 12101 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 12102 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full)); 12103 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport); 12104 hclge_reset_umv_space(hdev); 12105 } 12106 12107 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 12108 true, hdev->reset_pending); 12109 if (ret) { 12110 dev_err(&pdev->dev, "Cmd queue init failed\n"); 12111 return ret; 12112 } 12113 12114 ret = hclge_map_tqp(hdev); 12115 if (ret) { 12116 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 12117 return ret; 12118 } 12119 12120 ret = hclge_mac_init(hdev); 12121 if (ret) { 12122 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 12123 return ret; 12124 } 12125 12126 ret = hclge_tp_port_init(hdev); 12127 if (ret) { 12128 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n", 12129 ret); 12130 return ret; 12131 } 12132 12133 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 12134 if (ret) { 12135 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 12136 return ret; 12137 } 12138 12139 ret = hclge_config_gro(hdev); 12140 if (ret) 12141 return ret; 12142 12143 ret = hclge_init_vlan_config(hdev); 12144 if (ret) { 12145 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 12146 return ret; 12147 } 12148 12149 ret = hclge_tm_init_hw(hdev, true); 12150 if (ret) { 12151 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 12152 return ret; 12153 } 12154 12155 ret = hclge_rss_init_hw(hdev); 12156 if (ret) { 12157 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 12158 return ret; 12159 } 12160 12161 ret = init_mgr_tbl(hdev); 12162 if (ret) { 12163 dev_err(&pdev->dev, 12164 "failed to reinit manager table, ret = %d\n", ret); 12165 return ret; 12166 } 12167 12168 ret = hclge_init_fd_config(hdev); 12169 if (ret) { 12170 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret); 12171 return ret; 12172 } 12173 12174 ret = hclge_ptp_init(hdev); 12175 if (ret) 12176 return ret; 12177 12178 /* Log and clear the hw errors those already occurred */ 12179 if (hnae3_dev_ras_imp_supported(hdev)) 12180 hclge_handle_occurred_error(hdev); 12181 else 12182 hclge_handle_all_hns_hw_errors(ae_dev); 12183 12184 /* Re-enable the hw error interrupts because 12185 * the interrupts get disabled on global reset. 12186 */ 12187 ret = hclge_config_nic_hw_error(hdev, true); 12188 if (ret) { 12189 dev_err(&pdev->dev, 12190 "fail(%d) to re-enable NIC hw error interrupts\n", 12191 ret); 12192 return ret; 12193 } 12194 12195 if (hdev->roce_client) { 12196 ret = hclge_config_rocee_ras_interrupt(hdev, true); 12197 if (ret) { 12198 dev_err(&pdev->dev, 12199 "fail(%d) to re-enable roce ras interrupts\n", 12200 ret); 12201 return ret; 12202 } 12203 } 12204 12205 hclge_reset_vport_state(hdev); 12206 ret = hclge_reset_vport_spoofchk(hdev); 12207 if (ret) 12208 return ret; 12209 12210 ret = hclge_resume_vf_rate(hdev); 12211 if (ret) 12212 return ret; 12213 12214 hclge_init_rxd_adv_layout(hdev); 12215 12216 ret = hclge_update_wol(hdev); 12217 if (ret) 12218 dev_warn(&pdev->dev, 12219 "failed to update wol config, ret = %d\n", ret); 12220 12221 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 12222 HCLGE_DRIVER_NAME); 12223 12224 return 0; 12225 } 12226 12227 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 12228 { 12229 struct hclge_dev *hdev = ae_dev->priv; 12230 struct hclge_mac *mac = &hdev->hw.mac; 12231 12232 hclge_reset_vf_rate(hdev); 12233 hclge_clear_vf_vlan(hdev); 12234 hclge_state_uninit(hdev); 12235 hclge_ptp_uninit(hdev); 12236 hclge_uninit_rxd_adv_layout(hdev); 12237 hclge_uninit_mac_table(hdev); 12238 hclge_del_all_fd_entries(hdev); 12239 12240 if (mac->phydev) 12241 mdiobus_unregister(mac->mdio_bus); 12242 12243 /* Disable MISC vector(vector0) */ 12244 hclge_enable_vector(&hdev->misc_vector, false); 12245 synchronize_irq(hdev->misc_vector.vector_irq); 12246 12247 /* Disable all hw interrupts */ 12248 hclge_config_mac_tnl_int(hdev, false); 12249 hclge_config_nic_hw_error(hdev, false); 12250 hclge_config_rocee_ras_interrupt(hdev, false); 12251 12252 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 12253 hclge_misc_irq_uninit(hdev); 12254 hclge_devlink_uninit(hdev); 12255 hclge_pci_uninit(hdev); 12256 hclge_uninit_vport_vlan_table(hdev); 12257 mutex_destroy(&hdev->vport_lock); 12258 ae_dev->priv = NULL; 12259 } 12260 12261 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 12262 { 12263 struct hclge_vport *vport = hclge_get_vport(handle); 12264 struct hclge_dev *hdev = vport->back; 12265 12266 return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps); 12267 } 12268 12269 static void hclge_get_channels(struct hnae3_handle *handle, 12270 struct ethtool_channels *ch) 12271 { 12272 ch->max_combined = hclge_get_max_channels(handle); 12273 ch->other_count = 1; 12274 ch->max_other = 1; 12275 ch->combined_count = handle->kinfo.rss_size; 12276 } 12277 12278 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 12279 u16 *alloc_tqps, u16 *max_rss_size) 12280 { 12281 struct hclge_vport *vport = hclge_get_vport(handle); 12282 struct hclge_dev *hdev = vport->back; 12283 12284 *alloc_tqps = vport->alloc_tqps; 12285 *max_rss_size = hdev->pf_rss_size_max; 12286 } 12287 12288 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle) 12289 { 12290 struct hclge_vport *vport = hclge_get_vport(handle); 12291 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 12292 struct hclge_dev *hdev = vport->back; 12293 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 12294 u16 tc_valid[HCLGE_MAX_TC_NUM]; 12295 u16 roundup_size; 12296 unsigned int i; 12297 12298 roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size); 12299 roundup_size = ilog2(roundup_size); 12300 /* Set the RSS TC mode according to the new RSS size */ 12301 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 12302 tc_valid[i] = 0; 12303 12304 if (!(hdev->hw_tc_map & BIT(i))) 12305 continue; 12306 12307 tc_valid[i] = 1; 12308 tc_size[i] = roundup_size; 12309 tc_offset[i] = vport->nic.kinfo.rss_size * i; 12310 } 12311 12312 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 12313 tc_size); 12314 } 12315 12316 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 12317 bool rxfh_configured) 12318 { 12319 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 12320 struct hclge_vport *vport = hclge_get_vport(handle); 12321 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 12322 struct hclge_dev *hdev = vport->back; 12323 u16 cur_rss_size = kinfo->rss_size; 12324 u16 cur_tqps = kinfo->num_tqps; 12325 u32 *rss_indir; 12326 unsigned int i; 12327 int ret; 12328 12329 kinfo->req_rss_size = new_tqps_num; 12330 12331 ret = hclge_tm_vport_map_update(hdev); 12332 if (ret) { 12333 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret); 12334 return ret; 12335 } 12336 12337 ret = hclge_set_rss_tc_mode_cfg(handle); 12338 if (ret) 12339 return ret; 12340 12341 /* RSS indirection table has been configured by user */ 12342 if (rxfh_configured) 12343 goto out; 12344 12345 /* Reinitializes the rss indirect table according to the new RSS size */ 12346 rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32), 12347 GFP_KERNEL); 12348 if (!rss_indir) 12349 return -ENOMEM; 12350 12351 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 12352 rss_indir[i] = i % kinfo->rss_size; 12353 12354 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 12355 if (ret) 12356 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 12357 ret); 12358 12359 kfree(rss_indir); 12360 12361 out: 12362 if (!ret) 12363 dev_info(&hdev->pdev->dev, 12364 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 12365 cur_rss_size, kinfo->rss_size, 12366 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 12367 12368 return ret; 12369 } 12370 12371 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit, 12372 u32 *regs_num_64_bit) 12373 { 12374 struct hclge_desc desc; 12375 u32 total_num; 12376 int ret; 12377 12378 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true); 12379 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12380 if (ret) { 12381 dev_err(&hdev->pdev->dev, 12382 "Query register number cmd failed, ret = %d.\n", ret); 12383 return ret; 12384 } 12385 12386 *regs_num_32_bit = le32_to_cpu(desc.data[0]); 12387 *regs_num_64_bit = le32_to_cpu(desc.data[1]); 12388 12389 total_num = *regs_num_32_bit + *regs_num_64_bit; 12390 if (!total_num) 12391 return -EINVAL; 12392 12393 return 0; 12394 } 12395 12396 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num, 12397 void *data) 12398 { 12399 #define HCLGE_32_BIT_REG_RTN_DATANUM 8 12400 #define HCLGE_32_BIT_DESC_NODATA_LEN 2 12401 12402 struct hclge_desc *desc; 12403 u32 *reg_val = data; 12404 __le32 *desc_data; 12405 int nodata_num; 12406 int cmd_num; 12407 int i, k, n; 12408 int ret; 12409 12410 if (regs_num == 0) 12411 return 0; 12412 12413 nodata_num = HCLGE_32_BIT_DESC_NODATA_LEN; 12414 cmd_num = DIV_ROUND_UP(regs_num + nodata_num, 12415 HCLGE_32_BIT_REG_RTN_DATANUM); 12416 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 12417 if (!desc) 12418 return -ENOMEM; 12419 12420 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true); 12421 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 12422 if (ret) { 12423 dev_err(&hdev->pdev->dev, 12424 "Query 32 bit register cmd failed, ret = %d.\n", ret); 12425 kfree(desc); 12426 return ret; 12427 } 12428 12429 for (i = 0; i < cmd_num; i++) { 12430 if (i == 0) { 12431 desc_data = (__le32 *)(&desc[i].data[0]); 12432 n = HCLGE_32_BIT_REG_RTN_DATANUM - nodata_num; 12433 } else { 12434 desc_data = (__le32 *)(&desc[i]); 12435 n = HCLGE_32_BIT_REG_RTN_DATANUM; 12436 } 12437 for (k = 0; k < n; k++) { 12438 *reg_val++ = le32_to_cpu(*desc_data++); 12439 12440 regs_num--; 12441 if (!regs_num) 12442 break; 12443 } 12444 } 12445 12446 kfree(desc); 12447 return 0; 12448 } 12449 12450 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num, 12451 void *data) 12452 { 12453 #define HCLGE_64_BIT_REG_RTN_DATANUM 4 12454 #define HCLGE_64_BIT_DESC_NODATA_LEN 1 12455 12456 struct hclge_desc *desc; 12457 u64 *reg_val = data; 12458 __le64 *desc_data; 12459 int nodata_len; 12460 int cmd_num; 12461 int i, k, n; 12462 int ret; 12463 12464 if (regs_num == 0) 12465 return 0; 12466 12467 nodata_len = HCLGE_64_BIT_DESC_NODATA_LEN; 12468 cmd_num = DIV_ROUND_UP(regs_num + nodata_len, 12469 HCLGE_64_BIT_REG_RTN_DATANUM); 12470 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 12471 if (!desc) 12472 return -ENOMEM; 12473 12474 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true); 12475 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 12476 if (ret) { 12477 dev_err(&hdev->pdev->dev, 12478 "Query 64 bit register cmd failed, ret = %d.\n", ret); 12479 kfree(desc); 12480 return ret; 12481 } 12482 12483 for (i = 0; i < cmd_num; i++) { 12484 if (i == 0) { 12485 desc_data = (__le64 *)(&desc[i].data[0]); 12486 n = HCLGE_64_BIT_REG_RTN_DATANUM - nodata_len; 12487 } else { 12488 desc_data = (__le64 *)(&desc[i]); 12489 n = HCLGE_64_BIT_REG_RTN_DATANUM; 12490 } 12491 for (k = 0; k < n; k++) { 12492 *reg_val++ = le64_to_cpu(*desc_data++); 12493 12494 regs_num--; 12495 if (!regs_num) 12496 break; 12497 } 12498 } 12499 12500 kfree(desc); 12501 return 0; 12502 } 12503 12504 #define MAX_SEPARATE_NUM 4 12505 #define SEPARATOR_VALUE 0xFDFCFBFA 12506 #define REG_NUM_PER_LINE 4 12507 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 12508 #define REG_SEPARATOR_LINE 1 12509 #define REG_NUM_REMAIN_MASK 3 12510 12511 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc) 12512 { 12513 int i; 12514 12515 /* initialize command BD except the last one */ 12516 for (i = 0; i < HCLGE_GET_DFX_REG_TYPE_CNT - 1; i++) { 12517 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM, 12518 true); 12519 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12520 } 12521 12522 /* initialize the last command BD */ 12523 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM, true); 12524 12525 return hclge_cmd_send(&hdev->hw, desc, HCLGE_GET_DFX_REG_TYPE_CNT); 12526 } 12527 12528 static int hclge_get_dfx_reg_bd_num(struct hclge_dev *hdev, 12529 int *bd_num_list, 12530 u32 type_num) 12531 { 12532 u32 entries_per_desc, desc_index, index, offset, i; 12533 struct hclge_desc desc[HCLGE_GET_DFX_REG_TYPE_CNT]; 12534 int ret; 12535 12536 ret = hclge_query_bd_num_cmd_send(hdev, desc); 12537 if (ret) { 12538 dev_err(&hdev->pdev->dev, 12539 "Get dfx bd num fail, status is %d.\n", ret); 12540 return ret; 12541 } 12542 12543 entries_per_desc = ARRAY_SIZE(desc[0].data); 12544 for (i = 0; i < type_num; i++) { 12545 offset = hclge_dfx_bd_offset_list[i]; 12546 index = offset % entries_per_desc; 12547 desc_index = offset / entries_per_desc; 12548 bd_num_list[i] = le32_to_cpu(desc[desc_index].data[index]); 12549 } 12550 12551 return ret; 12552 } 12553 12554 static int hclge_dfx_reg_cmd_send(struct hclge_dev *hdev, 12555 struct hclge_desc *desc_src, int bd_num, 12556 enum hclge_opcode_type cmd) 12557 { 12558 struct hclge_desc *desc = desc_src; 12559 int i, ret; 12560 12561 hclge_cmd_setup_basic_desc(desc, cmd, true); 12562 for (i = 0; i < bd_num - 1; i++) { 12563 desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12564 desc++; 12565 hclge_cmd_setup_basic_desc(desc, cmd, true); 12566 } 12567 12568 desc = desc_src; 12569 ret = hclge_cmd_send(&hdev->hw, desc, bd_num); 12570 if (ret) 12571 dev_err(&hdev->pdev->dev, 12572 "Query dfx reg cmd(0x%x) send fail, status is %d.\n", 12573 cmd, ret); 12574 12575 return ret; 12576 } 12577 12578 static int hclge_dfx_reg_fetch_data(struct hclge_desc *desc_src, int bd_num, 12579 void *data) 12580 { 12581 int entries_per_desc, reg_num, separator_num, desc_index, index, i; 12582 struct hclge_desc *desc = desc_src; 12583 u32 *reg = data; 12584 12585 entries_per_desc = ARRAY_SIZE(desc->data); 12586 reg_num = entries_per_desc * bd_num; 12587 separator_num = REG_NUM_PER_LINE - (reg_num & REG_NUM_REMAIN_MASK); 12588 for (i = 0; i < reg_num; i++) { 12589 index = i % entries_per_desc; 12590 desc_index = i / entries_per_desc; 12591 *reg++ = le32_to_cpu(desc[desc_index].data[index]); 12592 } 12593 for (i = 0; i < separator_num; i++) 12594 *reg++ = SEPARATOR_VALUE; 12595 12596 return reg_num + separator_num; 12597 } 12598 12599 static int hclge_get_dfx_reg_len(struct hclge_dev *hdev, int *len) 12600 { 12601 u32 dfx_reg_type_num = ARRAY_SIZE(hclge_dfx_bd_offset_list); 12602 int data_len_per_desc, bd_num, i; 12603 int *bd_num_list; 12604 u32 data_len; 12605 int ret; 12606 12607 bd_num_list = kcalloc(dfx_reg_type_num, sizeof(int), GFP_KERNEL); 12608 if (!bd_num_list) 12609 return -ENOMEM; 12610 12611 ret = hclge_get_dfx_reg_bd_num(hdev, bd_num_list, dfx_reg_type_num); 12612 if (ret) { 12613 dev_err(&hdev->pdev->dev, 12614 "Get dfx reg bd num fail, status is %d.\n", ret); 12615 goto out; 12616 } 12617 12618 data_len_per_desc = sizeof_field(struct hclge_desc, data); 12619 *len = 0; 12620 for (i = 0; i < dfx_reg_type_num; i++) { 12621 bd_num = bd_num_list[i]; 12622 data_len = data_len_per_desc * bd_num; 12623 *len += (data_len / REG_LEN_PER_LINE + 1) * REG_LEN_PER_LINE; 12624 } 12625 12626 out: 12627 kfree(bd_num_list); 12628 return ret; 12629 } 12630 12631 static int hclge_get_dfx_reg(struct hclge_dev *hdev, void *data) 12632 { 12633 u32 dfx_reg_type_num = ARRAY_SIZE(hclge_dfx_bd_offset_list); 12634 int bd_num, bd_num_max, buf_len, i; 12635 struct hclge_desc *desc_src; 12636 int *bd_num_list; 12637 u32 *reg = data; 12638 int ret; 12639 12640 bd_num_list = kcalloc(dfx_reg_type_num, sizeof(int), GFP_KERNEL); 12641 if (!bd_num_list) 12642 return -ENOMEM; 12643 12644 ret = hclge_get_dfx_reg_bd_num(hdev, bd_num_list, dfx_reg_type_num); 12645 if (ret) { 12646 dev_err(&hdev->pdev->dev, 12647 "Get dfx reg bd num fail, status is %d.\n", ret); 12648 goto out; 12649 } 12650 12651 bd_num_max = bd_num_list[0]; 12652 for (i = 1; i < dfx_reg_type_num; i++) 12653 bd_num_max = max_t(int, bd_num_max, bd_num_list[i]); 12654 12655 buf_len = sizeof(*desc_src) * bd_num_max; 12656 desc_src = kzalloc(buf_len, GFP_KERNEL); 12657 if (!desc_src) { 12658 ret = -ENOMEM; 12659 goto out; 12660 } 12661 12662 for (i = 0; i < dfx_reg_type_num; i++) { 12663 bd_num = bd_num_list[i]; 12664 ret = hclge_dfx_reg_cmd_send(hdev, desc_src, bd_num, 12665 hclge_dfx_reg_opcode_list[i]); 12666 if (ret) { 12667 dev_err(&hdev->pdev->dev, 12668 "Get dfx reg fail, status is %d.\n", ret); 12669 break; 12670 } 12671 12672 reg += hclge_dfx_reg_fetch_data(desc_src, bd_num, reg); 12673 } 12674 12675 kfree(desc_src); 12676 out: 12677 kfree(bd_num_list); 12678 return ret; 12679 } 12680 12681 static int hclge_fetch_pf_reg(struct hclge_dev *hdev, void *data, 12682 struct hnae3_knic_private_info *kinfo) 12683 { 12684 #define HCLGE_RING_REG_OFFSET 0x200 12685 #define HCLGE_RING_INT_REG_OFFSET 0x4 12686 12687 int i, j, reg_num, separator_num; 12688 int data_num_sum; 12689 u32 *reg = data; 12690 12691 /* fetching per-PF registers valus from PF PCIe register space */ 12692 reg_num = ARRAY_SIZE(cmdq_reg_addr_list); 12693 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12694 for (i = 0; i < reg_num; i++) 12695 *reg++ = hclge_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 12696 for (i = 0; i < separator_num; i++) 12697 *reg++ = SEPARATOR_VALUE; 12698 data_num_sum = reg_num + separator_num; 12699 12700 reg_num = ARRAY_SIZE(common_reg_addr_list); 12701 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12702 for (i = 0; i < reg_num; i++) 12703 *reg++ = hclge_read_dev(&hdev->hw, common_reg_addr_list[i]); 12704 for (i = 0; i < separator_num; i++) 12705 *reg++ = SEPARATOR_VALUE; 12706 data_num_sum += reg_num + separator_num; 12707 12708 reg_num = ARRAY_SIZE(ring_reg_addr_list); 12709 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12710 for (j = 0; j < kinfo->num_tqps; j++) { 12711 for (i = 0; i < reg_num; i++) 12712 *reg++ = hclge_read_dev(&hdev->hw, 12713 ring_reg_addr_list[i] + 12714 HCLGE_RING_REG_OFFSET * j); 12715 for (i = 0; i < separator_num; i++) 12716 *reg++ = SEPARATOR_VALUE; 12717 } 12718 data_num_sum += (reg_num + separator_num) * kinfo->num_tqps; 12719 12720 reg_num = ARRAY_SIZE(tqp_intr_reg_addr_list); 12721 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12722 for (j = 0; j < hdev->num_msi_used - 1; j++) { 12723 for (i = 0; i < reg_num; i++) 12724 *reg++ = hclge_read_dev(&hdev->hw, 12725 tqp_intr_reg_addr_list[i] + 12726 HCLGE_RING_INT_REG_OFFSET * j); 12727 for (i = 0; i < separator_num; i++) 12728 *reg++ = SEPARATOR_VALUE; 12729 } 12730 data_num_sum += (reg_num + separator_num) * (hdev->num_msi_used - 1); 12731 12732 return data_num_sum; 12733 } 12734 12735 static int hclge_get_regs_len(struct hnae3_handle *handle) 12736 { 12737 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 12738 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 12739 struct hclge_vport *vport = hclge_get_vport(handle); 12740 struct hclge_dev *hdev = vport->back; 12741 int regs_num_32_bit, regs_num_64_bit, dfx_regs_len; 12742 int regs_lines_32_bit, regs_lines_64_bit; 12743 int ret; 12744 12745 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 12746 if (ret) { 12747 dev_err(&hdev->pdev->dev, 12748 "Get register number failed, ret = %d.\n", ret); 12749 return ret; 12750 } 12751 12752 ret = hclge_get_dfx_reg_len(hdev, &dfx_regs_len); 12753 if (ret) { 12754 dev_err(&hdev->pdev->dev, 12755 "Get dfx reg len failed, ret = %d.\n", ret); 12756 return ret; 12757 } 12758 12759 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 12760 REG_SEPARATOR_LINE; 12761 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 12762 REG_SEPARATOR_LINE; 12763 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 12764 REG_SEPARATOR_LINE; 12765 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 12766 REG_SEPARATOR_LINE; 12767 regs_lines_32_bit = regs_num_32_bit * sizeof(u32) / REG_LEN_PER_LINE + 12768 REG_SEPARATOR_LINE; 12769 regs_lines_64_bit = regs_num_64_bit * sizeof(u64) / REG_LEN_PER_LINE + 12770 REG_SEPARATOR_LINE; 12771 12772 return (cmdq_lines + common_lines + ring_lines * kinfo->num_tqps + 12773 tqp_intr_lines * (hdev->num_msi_used - 1) + regs_lines_32_bit + 12774 regs_lines_64_bit) * REG_LEN_PER_LINE + dfx_regs_len; 12775 } 12776 12777 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version, 12778 void *data) 12779 { 12780 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 12781 struct hclge_vport *vport = hclge_get_vport(handle); 12782 struct hclge_dev *hdev = vport->back; 12783 u32 regs_num_32_bit, regs_num_64_bit; 12784 int i, reg_num, separator_num, ret; 12785 u32 *reg = data; 12786 12787 *version = hdev->fw_version; 12788 12789 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 12790 if (ret) { 12791 dev_err(&hdev->pdev->dev, 12792 "Get register number failed, ret = %d.\n", ret); 12793 return; 12794 } 12795 12796 reg += hclge_fetch_pf_reg(hdev, reg, kinfo); 12797 12798 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, reg); 12799 if (ret) { 12800 dev_err(&hdev->pdev->dev, 12801 "Get 32 bit register failed, ret = %d.\n", ret); 12802 return; 12803 } 12804 reg_num = regs_num_32_bit; 12805 reg += reg_num; 12806 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12807 for (i = 0; i < separator_num; i++) 12808 *reg++ = SEPARATOR_VALUE; 12809 12810 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, reg); 12811 if (ret) { 12812 dev_err(&hdev->pdev->dev, 12813 "Get 64 bit register failed, ret = %d.\n", ret); 12814 return; 12815 } 12816 reg_num = regs_num_64_bit * 2; 12817 reg += reg_num; 12818 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12819 for (i = 0; i < separator_num; i++) 12820 *reg++ = SEPARATOR_VALUE; 12821 12822 ret = hclge_get_dfx_reg(hdev, reg); 12823 if (ret) 12824 dev_err(&hdev->pdev->dev, 12825 "Get dfx register failed, ret = %d.\n", ret); 12826 } 12827 12828 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 12829 { 12830 struct hclge_set_led_state_cmd *req; 12831 struct hclge_desc desc; 12832 int ret; 12833 12834 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 12835 12836 req = (struct hclge_set_led_state_cmd *)desc.data; 12837 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 12838 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 12839 12840 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12841 if (ret) 12842 dev_err(&hdev->pdev->dev, 12843 "Send set led state cmd error, ret =%d\n", ret); 12844 12845 return ret; 12846 } 12847 12848 enum hclge_led_status { 12849 HCLGE_LED_OFF, 12850 HCLGE_LED_ON, 12851 HCLGE_LED_NO_CHANGE = 0xFF, 12852 }; 12853 12854 static int hclge_set_led_id(struct hnae3_handle *handle, 12855 enum ethtool_phys_id_state status) 12856 { 12857 struct hclge_vport *vport = hclge_get_vport(handle); 12858 struct hclge_dev *hdev = vport->back; 12859 12860 switch (status) { 12861 case ETHTOOL_ID_ACTIVE: 12862 return hclge_set_led_status(hdev, HCLGE_LED_ON); 12863 case ETHTOOL_ID_INACTIVE: 12864 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 12865 default: 12866 return -EINVAL; 12867 } 12868 } 12869 12870 static void hclge_get_link_mode(struct hnae3_handle *handle, 12871 unsigned long *supported, 12872 unsigned long *advertising) 12873 { 12874 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 12875 struct hclge_vport *vport = hclge_get_vport(handle); 12876 struct hclge_dev *hdev = vport->back; 12877 unsigned int idx = 0; 12878 12879 for (; idx < size; idx++) { 12880 supported[idx] = hdev->hw.mac.supported[idx]; 12881 advertising[idx] = hdev->hw.mac.advertising[idx]; 12882 } 12883 } 12884 12885 static int hclge_gro_en(struct hnae3_handle *handle, bool enable) 12886 { 12887 struct hclge_vport *vport = hclge_get_vport(handle); 12888 struct hclge_dev *hdev = vport->back; 12889 bool gro_en_old = hdev->gro_en; 12890 int ret; 12891 12892 hdev->gro_en = enable; 12893 ret = hclge_config_gro(hdev); 12894 if (ret) 12895 hdev->gro_en = gro_en_old; 12896 12897 return ret; 12898 } 12899 12900 static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport) 12901 { 12902 struct hnae3_handle *handle = &vport->nic; 12903 struct hclge_dev *hdev = vport->back; 12904 bool uc_en = false; 12905 bool mc_en = false; 12906 u8 tmp_flags; 12907 bool bc_en; 12908 int ret; 12909 12910 if (vport->last_promisc_flags != vport->overflow_promisc_flags) { 12911 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12912 vport->last_promisc_flags = vport->overflow_promisc_flags; 12913 } 12914 12915 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12916 &vport->state)) 12917 return 0; 12918 12919 /* for PF */ 12920 if (!vport->vport_id) { 12921 tmp_flags = handle->netdev_flags | vport->last_promisc_flags; 12922 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE, 12923 tmp_flags & HNAE3_MPE); 12924 if (!ret) 12925 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 12926 &vport->state); 12927 else 12928 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12929 &vport->state); 12930 return ret; 12931 } 12932 12933 /* for VF */ 12934 if (vport->vf_info.trusted) { 12935 uc_en = vport->vf_info.request_uc_en > 0 || 12936 vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE; 12937 mc_en = vport->vf_info.request_mc_en > 0 || 12938 vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE; 12939 } 12940 bc_en = vport->vf_info.request_bc_en > 0; 12941 12942 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en, 12943 mc_en, bc_en); 12944 if (ret) { 12945 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12946 return ret; 12947 } 12948 hclge_set_vport_vlan_fltr_change(vport); 12949 12950 return 0; 12951 } 12952 12953 static void hclge_sync_promisc_mode(struct hclge_dev *hdev) 12954 { 12955 struct hclge_vport *vport; 12956 int ret; 12957 u16 i; 12958 12959 for (i = 0; i < hdev->num_alloc_vport; i++) { 12960 vport = &hdev->vport[i]; 12961 12962 ret = hclge_sync_vport_promisc_mode(vport); 12963 if (ret) 12964 return; 12965 } 12966 } 12967 12968 static bool hclge_module_existed(struct hclge_dev *hdev) 12969 { 12970 struct hclge_desc desc; 12971 u32 existed; 12972 int ret; 12973 12974 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true); 12975 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12976 if (ret) { 12977 dev_err(&hdev->pdev->dev, 12978 "failed to get SFP exist state, ret = %d\n", ret); 12979 return false; 12980 } 12981 12982 existed = le32_to_cpu(desc.data[0]); 12983 12984 return existed != 0; 12985 } 12986 12987 /* need 6 bds(total 140 bytes) in one reading 12988 * return the number of bytes actually read, 0 means read failed. 12989 */ 12990 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset, 12991 u32 len, u8 *data) 12992 { 12993 struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM]; 12994 struct hclge_sfp_info_bd0_cmd *sfp_info_bd0; 12995 u16 read_len; 12996 u16 copy_len; 12997 int ret; 12998 int i; 12999 13000 /* setup all 6 bds to read module eeprom info. */ 13001 for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 13002 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM, 13003 true); 13004 13005 /* bd0~bd4 need next flag */ 13006 if (i < HCLGE_SFP_INFO_CMD_NUM - 1) 13007 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 13008 } 13009 13010 /* setup bd0, this bd contains offset and read length. */ 13011 sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data; 13012 sfp_info_bd0->offset = cpu_to_le16((u16)offset); 13013 read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN); 13014 sfp_info_bd0->read_len = cpu_to_le16(read_len); 13015 13016 ret = hclge_cmd_send(&hdev->hw, desc, i); 13017 if (ret) { 13018 dev_err(&hdev->pdev->dev, 13019 "failed to get SFP eeprom info, ret = %d\n", ret); 13020 return 0; 13021 } 13022 13023 /* copy sfp info from bd0 to out buffer. */ 13024 copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN); 13025 memcpy(data, sfp_info_bd0->data, copy_len); 13026 read_len = copy_len; 13027 13028 /* copy sfp info from bd1~bd5 to out buffer if needed. */ 13029 for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 13030 if (read_len >= len) 13031 return read_len; 13032 13033 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN); 13034 memcpy(data + read_len, desc[i].data, copy_len); 13035 read_len += copy_len; 13036 } 13037 13038 return read_len; 13039 } 13040 13041 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset, 13042 u32 len, u8 *data) 13043 { 13044 struct hclge_vport *vport = hclge_get_vport(handle); 13045 struct hclge_dev *hdev = vport->back; 13046 u32 read_len = 0; 13047 u16 data_len; 13048 13049 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 13050 return -EOPNOTSUPP; 13051 13052 if (!hclge_module_existed(hdev)) 13053 return -ENXIO; 13054 13055 while (read_len < len) { 13056 data_len = hclge_get_sfp_eeprom_info(hdev, 13057 offset + read_len, 13058 len - read_len, 13059 data + read_len); 13060 if (!data_len) 13061 return -EIO; 13062 13063 read_len += data_len; 13064 } 13065 13066 return 0; 13067 } 13068 13069 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle, 13070 u32 *status_code) 13071 { 13072 struct hclge_vport *vport = hclge_get_vport(handle); 13073 struct hclge_dev *hdev = vport->back; 13074 struct hclge_desc desc; 13075 int ret; 13076 13077 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 13078 return -EOPNOTSUPP; 13079 13080 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true); 13081 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 13082 if (ret) { 13083 dev_err(&hdev->pdev->dev, 13084 "failed to query link diagnosis info, ret = %d\n", ret); 13085 return ret; 13086 } 13087 13088 *status_code = le32_to_cpu(desc.data[0]); 13089 return 0; 13090 } 13091 13092 /* After disable sriov, VF still has some config and info need clean, 13093 * which configed by PF. 13094 */ 13095 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid) 13096 { 13097 struct hclge_dev *hdev = vport->back; 13098 struct hclge_vlan_info vlan_info; 13099 int ret; 13100 13101 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 13102 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 13103 vport->need_notify = 0; 13104 vport->mps = 0; 13105 13106 /* after disable sriov, clean VF rate configured by PF */ 13107 ret = hclge_tm_qs_shaper_cfg(vport, 0); 13108 if (ret) 13109 dev_err(&hdev->pdev->dev, 13110 "failed to clean vf%d rate config, ret = %d\n", 13111 vfid, ret); 13112 13113 vlan_info.vlan_tag = 0; 13114 vlan_info.qos = 0; 13115 vlan_info.vlan_proto = ETH_P_8021Q; 13116 ret = hclge_update_port_base_vlan_cfg(vport, 13117 HNAE3_PORT_BASE_VLAN_DISABLE, 13118 &vlan_info); 13119 if (ret) 13120 dev_err(&hdev->pdev->dev, 13121 "failed to clean vf%d port base vlan, ret = %d\n", 13122 vfid, ret); 13123 13124 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false); 13125 if (ret) 13126 dev_err(&hdev->pdev->dev, 13127 "failed to clean vf%d spoof config, ret = %d\n", 13128 vfid, ret); 13129 13130 memset(&vport->vf_info, 0, sizeof(vport->vf_info)); 13131 } 13132 13133 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs) 13134 { 13135 struct hclge_dev *hdev = ae_dev->priv; 13136 struct hclge_vport *vport; 13137 int i; 13138 13139 for (i = 0; i < num_vfs; i++) { 13140 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 13141 13142 hclge_clear_vport_vf_info(vport, i); 13143 } 13144 } 13145 13146 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode, 13147 u8 *priority) 13148 { 13149 struct hclge_vport *vport = hclge_get_vport(h); 13150 13151 if (dscp >= HNAE3_MAX_DSCP) 13152 return -EINVAL; 13153 13154 if (tc_mode) 13155 *tc_mode = vport->nic.kinfo.tc_map_mode; 13156 if (priority) 13157 *priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 : 13158 vport->nic.kinfo.dscp_prio[dscp]; 13159 13160 return 0; 13161 } 13162 13163 static const struct hnae3_ae_ops hclge_ops = { 13164 .init_ae_dev = hclge_init_ae_dev, 13165 .uninit_ae_dev = hclge_uninit_ae_dev, 13166 .reset_prepare = hclge_reset_prepare_general, 13167 .reset_done = hclge_reset_done, 13168 .init_client_instance = hclge_init_client_instance, 13169 .uninit_client_instance = hclge_uninit_client_instance, 13170 .map_ring_to_vector = hclge_map_ring_to_vector, 13171 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 13172 .get_vector = hclge_get_vector, 13173 .put_vector = hclge_put_vector, 13174 .set_promisc_mode = hclge_set_promisc_mode, 13175 .request_update_promisc_mode = hclge_request_update_promisc_mode, 13176 .set_loopback = hclge_set_loopback, 13177 .start = hclge_ae_start, 13178 .stop = hclge_ae_stop, 13179 .client_start = hclge_client_start, 13180 .client_stop = hclge_client_stop, 13181 .get_status = hclge_get_status, 13182 .get_ksettings_an_result = hclge_get_ksettings_an_result, 13183 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 13184 .get_media_type = hclge_get_media_type, 13185 .check_port_speed = hclge_check_port_speed, 13186 .get_fec_stats = hclge_get_fec_stats, 13187 .get_fec = hclge_get_fec, 13188 .set_fec = hclge_set_fec, 13189 .get_rss_key_size = hclge_comm_get_rss_key_size, 13190 .get_rss = hclge_get_rss, 13191 .set_rss = hclge_set_rss, 13192 .set_rss_tuple = hclge_set_rss_tuple, 13193 .get_rss_tuple = hclge_get_rss_tuple, 13194 .get_tc_size = hclge_get_tc_size, 13195 .get_mac_addr = hclge_get_mac_addr, 13196 .set_mac_addr = hclge_set_mac_addr, 13197 .do_ioctl = hclge_do_ioctl, 13198 .add_uc_addr = hclge_add_uc_addr, 13199 .rm_uc_addr = hclge_rm_uc_addr, 13200 .add_mc_addr = hclge_add_mc_addr, 13201 .rm_mc_addr = hclge_rm_mc_addr, 13202 .set_autoneg = hclge_set_autoneg, 13203 .get_autoneg = hclge_get_autoneg, 13204 .restart_autoneg = hclge_restart_autoneg, 13205 .halt_autoneg = hclge_halt_autoneg, 13206 .get_pauseparam = hclge_get_pauseparam, 13207 .set_pauseparam = hclge_set_pauseparam, 13208 .set_mtu = hclge_set_mtu, 13209 .reset_queue = hclge_reset_tqp, 13210 .get_stats = hclge_get_stats, 13211 .get_mac_stats = hclge_get_mac_stat, 13212 .update_stats = hclge_update_stats, 13213 .get_strings = hclge_get_strings, 13214 .get_sset_count = hclge_get_sset_count, 13215 .get_fw_version = hclge_get_fw_version, 13216 .get_mdix_mode = hclge_get_mdix_mode, 13217 .enable_vlan_filter = hclge_enable_vlan_filter, 13218 .set_vlan_filter = hclge_set_vlan_filter, 13219 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 13220 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 13221 .reset_event = hclge_reset_event, 13222 .get_reset_level = hclge_get_reset_level, 13223 .set_default_reset_request = hclge_set_def_reset_request, 13224 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 13225 .set_channels = hclge_set_channels, 13226 .get_channels = hclge_get_channels, 13227 .get_regs_len = hclge_get_regs_len, 13228 .get_regs = hclge_get_regs, 13229 .set_led_id = hclge_set_led_id, 13230 .get_link_mode = hclge_get_link_mode, 13231 .add_fd_entry = hclge_add_fd_entry, 13232 .del_fd_entry = hclge_del_fd_entry, 13233 .get_fd_rule_cnt = hclge_get_fd_rule_cnt, 13234 .get_fd_rule_info = hclge_get_fd_rule_info, 13235 .get_fd_all_rules = hclge_get_all_rules, 13236 .enable_fd = hclge_enable_fd, 13237 .add_arfs_entry = hclge_add_fd_entry_by_arfs, 13238 .dbg_read_cmd = hclge_dbg_read_cmd, 13239 .handle_hw_ras_error = hclge_handle_hw_ras_error, 13240 .get_hw_reset_stat = hclge_get_hw_reset_stat, 13241 .ae_dev_resetting = hclge_ae_dev_resetting, 13242 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt, 13243 .set_gro_en = hclge_gro_en, 13244 .get_global_queue_id = hclge_covert_handle_qid_global, 13245 .set_timer_task = hclge_set_timer_task, 13246 .mac_connect_phy = hclge_mac_connect_phy, 13247 .mac_disconnect_phy = hclge_mac_disconnect_phy, 13248 .get_vf_config = hclge_get_vf_config, 13249 .set_vf_link_state = hclge_set_vf_link_state, 13250 .set_vf_spoofchk = hclge_set_vf_spoofchk, 13251 .set_vf_trust = hclge_set_vf_trust, 13252 .set_vf_rate = hclge_set_vf_rate, 13253 .set_vf_mac = hclge_set_vf_mac, 13254 .get_module_eeprom = hclge_get_module_eeprom, 13255 .get_cmdq_stat = hclge_get_cmdq_stat, 13256 .add_cls_flower = hclge_add_cls_flower, 13257 .del_cls_flower = hclge_del_cls_flower, 13258 .cls_flower_active = hclge_is_cls_flower_active, 13259 .get_phy_link_ksettings = hclge_get_phy_link_ksettings, 13260 .set_phy_link_ksettings = hclge_set_phy_link_ksettings, 13261 .set_tx_hwts_info = hclge_ptp_set_tx_info, 13262 .get_rx_hwts = hclge_ptp_get_rx_hwts, 13263 .get_ts_info = hclge_ptp_get_ts_info, 13264 .get_link_diagnosis_info = hclge_get_link_diagnosis_info, 13265 .clean_vf_config = hclge_clean_vport_config, 13266 .get_dscp_prio = hclge_get_dscp_prio, 13267 .get_wol = hclge_get_wol, 13268 .set_wol = hclge_set_wol, 13269 }; 13270 13271 static struct hnae3_ae_algo ae_algo = { 13272 .ops = &hclge_ops, 13273 .pdev_id_table = ae_algo_pci_tbl, 13274 }; 13275 13276 static int __init hclge_init(void) 13277 { 13278 pr_info("%s is initializing\n", HCLGE_NAME); 13279 13280 hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGE_NAME); 13281 if (!hclge_wq) { 13282 pr_err("%s: failed to create workqueue\n", HCLGE_NAME); 13283 return -ENOMEM; 13284 } 13285 13286 hnae3_register_ae_algo(&ae_algo); 13287 13288 return 0; 13289 } 13290 13291 static void __exit hclge_exit(void) 13292 { 13293 hnae3_unregister_ae_algo_prepare(&ae_algo); 13294 hnae3_unregister_ae_algo(&ae_algo); 13295 destroy_workqueue(hclge_wq); 13296 } 13297 module_init(hclge_init); 13298 module_exit(hclge_exit); 13299 13300 MODULE_LICENSE("GPL"); 13301 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 13302 MODULE_DESCRIPTION("HCLGE Driver"); 13303 MODULE_VERSION(HCLGE_MOD_VERSION); 13304