1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/pci.h> 13 #include <linux/platform_device.h> 14 #include <linux/if_vlan.h> 15 #include <linux/crash_dump.h> 16 #include <net/ipv6.h> 17 #include <net/rtnetlink.h> 18 #include "hclge_cmd.h" 19 #include "hclge_dcb.h" 20 #include "hclge_main.h" 21 #include "hclge_mbx.h" 22 #include "hclge_mdio.h" 23 #include "hclge_regs.h" 24 #include "hclge_tm.h" 25 #include "hclge_err.h" 26 #include "hnae3.h" 27 #include "hclge_devlink.h" 28 #include "hclge_comm_cmd.h" 29 30 #define HCLGE_NAME "hclge" 31 32 #define HCLGE_BUF_SIZE_UNIT 256U 33 #define HCLGE_BUF_MUL_BY 2 34 #define HCLGE_BUF_DIV_BY 2 35 #define NEED_RESERVE_TC_NUM 2 36 #define BUF_MAX_PERCENT 100 37 #define BUF_RESERVE_PERCENT 90 38 39 #define HCLGE_RESET_MAX_FAIL_CNT 5 40 #define HCLGE_RESET_SYNC_TIME 100 41 #define HCLGE_PF_RESET_SYNC_TIME 20 42 #define HCLGE_PF_RESET_SYNC_CNT 1500 43 44 #define HCLGE_LINK_STATUS_MS 10 45 46 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps); 47 static int hclge_init_vlan_config(struct hclge_dev *hdev); 48 static void hclge_sync_vlan_filter(struct hclge_dev *hdev); 49 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 50 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle); 51 static void hclge_rfs_filter_expire(struct hclge_dev *hdev); 52 static int hclge_clear_arfs_rules(struct hclge_dev *hdev); 53 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 54 unsigned long *addr); 55 static int hclge_set_default_loopback(struct hclge_dev *hdev); 56 57 static void hclge_sync_mac_table(struct hclge_dev *hdev); 58 static void hclge_restore_hw_table(struct hclge_dev *hdev); 59 static void hclge_sync_promisc_mode(struct hclge_dev *hdev); 60 static void hclge_sync_fd_table(struct hclge_dev *hdev); 61 static void hclge_update_fec_stats(struct hclge_dev *hdev); 62 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 63 int wait_cnt); 64 static int hclge_update_port_info(struct hclge_dev *hdev); 65 66 static struct hnae3_ae_algo ae_algo; 67 68 static struct workqueue_struct *hclge_wq; 69 70 static const struct pci_device_id ae_algo_pci_tbl[] = { 71 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 72 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 75 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 77 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 79 /* required last entry */ 80 {0, } 81 }; 82 83 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 84 85 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 86 "External Loopback test", 87 "App Loopback test", 88 "Serdes serial Loopback test", 89 "Serdes parallel Loopback test", 90 "Phy Loopback test" 91 }; 92 93 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 94 {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 95 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 96 {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 97 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 98 {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 99 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)}, 100 {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 101 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)}, 102 {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 103 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)}, 104 {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 105 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)}, 106 {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 107 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)}, 108 {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 109 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 110 {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 111 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 112 {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 113 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 114 {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 115 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 116 {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 117 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 118 {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 119 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 120 {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 121 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 122 {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 123 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 124 {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 125 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)}, 126 {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 127 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)}, 128 {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 129 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)}, 130 {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 131 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)}, 132 {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 133 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)}, 134 {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 135 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)}, 136 {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 137 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)}, 138 {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 139 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)}, 140 {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 141 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)}, 142 {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 143 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 144 {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 145 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 146 {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 147 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 148 {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 149 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 150 {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 151 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 152 {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 153 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 154 {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 155 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 156 {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 157 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 158 {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 159 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)}, 160 {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 161 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)}, 162 {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 163 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)}, 164 {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 165 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)}, 166 {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 167 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)}, 168 {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 169 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)}, 170 {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 171 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)}, 172 {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 173 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)}, 174 {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 175 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 176 {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 177 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 178 {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 179 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 180 {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 181 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 182 {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 183 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 184 {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 185 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 186 {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 187 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 188 {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 189 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 190 {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 191 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 192 {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 193 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 194 {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 195 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 196 {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 197 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 198 {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 199 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 200 {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 201 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 202 {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 203 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 204 {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 205 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 206 {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 207 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 208 {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 209 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 210 {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 211 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 212 {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 213 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 214 {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 215 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 216 {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 217 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 218 {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 219 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 220 {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 221 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 222 {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 223 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 224 {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 225 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 226 {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 228 {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 230 {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 231 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 232 {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 233 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 234 {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 235 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 236 {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 237 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 238 {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 239 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 240 {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 241 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 242 {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 243 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 244 {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 246 {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 248 {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 250 {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 252 {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 254 {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 256 {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 258 {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 260 {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 262 {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 264 {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 265 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 266 {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 267 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 268 {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 269 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 270 {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 271 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 272 {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 273 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 274 275 {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 277 {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 279 {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 281 {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 283 {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 285 {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 287 {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 288 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 289 {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 290 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 291 {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 292 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 293 {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 294 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 295 {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 296 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 297 {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 298 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 299 }; 300 301 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 302 { 303 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 304 .ethter_type = cpu_to_le16(ETH_P_LLDP), 305 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e}, 306 .i_port_bitmap = 0x1, 307 }, 308 }; 309 310 static const struct key_info meta_data_key_info[] = { 311 { PACKET_TYPE_ID, 6 }, 312 { IP_FRAGEMENT, 1 }, 313 { ROCE_TYPE, 1 }, 314 { NEXT_KEY, 5 }, 315 { VLAN_NUMBER, 2 }, 316 { SRC_VPORT, 12 }, 317 { DST_VPORT, 12 }, 318 { TUNNEL_PACKET, 1 }, 319 }; 320 321 static const struct key_info tuple_key_info[] = { 322 { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 }, 323 { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 }, 324 { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 }, 325 { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 326 { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 }, 327 { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 }, 328 { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 }, 329 { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 }, 330 { OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 }, 331 { OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 }, 332 { OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 }, 333 { OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 }, 334 { OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 }, 335 { OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 }, 336 { OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 }, 337 { OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 }, 338 { INNER_DST_MAC, 48, KEY_OPT_MAC, 339 offsetof(struct hclge_fd_rule, tuples.dst_mac), 340 offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) }, 341 { INNER_SRC_MAC, 48, KEY_OPT_MAC, 342 offsetof(struct hclge_fd_rule, tuples.src_mac), 343 offsetof(struct hclge_fd_rule, tuples_mask.src_mac) }, 344 { INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16, 345 offsetof(struct hclge_fd_rule, tuples.vlan_tag1), 346 offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) }, 347 { INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 348 { INNER_ETH_TYPE, 16, KEY_OPT_LE16, 349 offsetof(struct hclge_fd_rule, tuples.ether_proto), 350 offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) }, 351 { INNER_L2_RSV, 16, KEY_OPT_LE16, 352 offsetof(struct hclge_fd_rule, tuples.l2_user_def), 353 offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) }, 354 { INNER_IP_TOS, 8, KEY_OPT_U8, 355 offsetof(struct hclge_fd_rule, tuples.ip_tos), 356 offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) }, 357 { INNER_IP_PROTO, 8, KEY_OPT_U8, 358 offsetof(struct hclge_fd_rule, tuples.ip_proto), 359 offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) }, 360 { INNER_SRC_IP, 32, KEY_OPT_IP, 361 offsetof(struct hclge_fd_rule, tuples.src_ip), 362 offsetof(struct hclge_fd_rule, tuples_mask.src_ip) }, 363 { INNER_DST_IP, 32, KEY_OPT_IP, 364 offsetof(struct hclge_fd_rule, tuples.dst_ip), 365 offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) }, 366 { INNER_L3_RSV, 16, KEY_OPT_LE16, 367 offsetof(struct hclge_fd_rule, tuples.l3_user_def), 368 offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) }, 369 { INNER_SRC_PORT, 16, KEY_OPT_LE16, 370 offsetof(struct hclge_fd_rule, tuples.src_port), 371 offsetof(struct hclge_fd_rule, tuples_mask.src_port) }, 372 { INNER_DST_PORT, 16, KEY_OPT_LE16, 373 offsetof(struct hclge_fd_rule, tuples.dst_port), 374 offsetof(struct hclge_fd_rule, tuples_mask.dst_port) }, 375 { INNER_L4_RSV, 32, KEY_OPT_LE32, 376 offsetof(struct hclge_fd_rule, tuples.l4_user_def), 377 offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) }, 378 }; 379 380 /** 381 * hclge_cmd_send - send command to command queue 382 * @hw: pointer to the hw struct 383 * @desc: prefilled descriptor for describing the command 384 * @num : the number of descriptors to be sent 385 * 386 * This is the main send command for command queue, it 387 * sends the queue, cleans the queue, etc 388 **/ 389 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 390 { 391 return hclge_comm_cmd_send(&hw->hw, desc, num); 392 } 393 394 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev) 395 { 396 #define HCLGE_MAC_CMD_NUM 21 397 398 u64 *data = (u64 *)(&hdev->mac_stats); 399 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 400 __le64 *desc_data; 401 u32 data_size; 402 int ret; 403 u32 i; 404 405 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 406 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 407 if (ret) { 408 dev_err(&hdev->pdev->dev, 409 "Get MAC pkt stats fail, status = %d.\n", ret); 410 411 return ret; 412 } 413 414 /* The first desc has a 64-bit header, so data size need to minus 1 */ 415 data_size = sizeof(desc) / (sizeof(u64)) - 1; 416 417 desc_data = (__le64 *)(&desc[0].data[0]); 418 for (i = 0; i < data_size; i++) { 419 /* data memory is continuous becase only the first desc has a 420 * header in this command 421 */ 422 *data += le64_to_cpu(*desc_data); 423 data++; 424 desc_data++; 425 } 426 427 return 0; 428 } 429 430 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev) 431 { 432 #define HCLGE_REG_NUM_PER_DESC 4 433 434 u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num; 435 u64 *data = (u64 *)(&hdev->mac_stats); 436 struct hclge_desc *desc; 437 __le64 *desc_data; 438 u32 data_size; 439 u32 desc_num; 440 int ret; 441 u32 i; 442 443 /* The first desc has a 64-bit header, so need to consider it */ 444 desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1; 445 446 /* This may be called inside atomic sections, 447 * so GFP_ATOMIC is more suitalbe here 448 */ 449 desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC); 450 if (!desc) 451 return -ENOMEM; 452 453 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true); 454 ret = hclge_cmd_send(&hdev->hw, desc, desc_num); 455 if (ret) { 456 kfree(desc); 457 return ret; 458 } 459 460 data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num); 461 462 desc_data = (__le64 *)(&desc[0].data[0]); 463 for (i = 0; i < data_size; i++) { 464 /* data memory is continuous becase only the first desc has a 465 * header in this command 466 */ 467 *data += le64_to_cpu(*desc_data); 468 data++; 469 desc_data++; 470 } 471 472 kfree(desc); 473 474 return 0; 475 } 476 477 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num) 478 { 479 struct hclge_desc desc; 480 int ret; 481 482 /* Driver needs total register number of both valid registers and 483 * reserved registers, but the old firmware only returns number 484 * of valid registers in device V2. To be compatible with these 485 * devices, driver uses a fixed value. 486 */ 487 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) { 488 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1; 489 return 0; 490 } 491 492 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true); 493 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 494 if (ret) { 495 dev_err(&hdev->pdev->dev, 496 "failed to query mac statistic reg number, ret = %d\n", 497 ret); 498 return ret; 499 } 500 501 *reg_num = le32_to_cpu(desc.data[0]); 502 if (*reg_num == 0) { 503 dev_err(&hdev->pdev->dev, 504 "mac statistic reg number is invalid!\n"); 505 return -ENODATA; 506 } 507 508 return 0; 509 } 510 511 int hclge_mac_update_stats(struct hclge_dev *hdev) 512 { 513 /* The firmware supports the new statistics acquisition method */ 514 if (hdev->ae_dev->dev_specs.mac_stats_num) 515 return hclge_mac_update_stats_complete(hdev); 516 else 517 return hclge_mac_update_stats_defective(hdev); 518 } 519 520 static int hclge_comm_get_count(struct hclge_dev *hdev, 521 const struct hclge_comm_stats_str strs[], 522 u32 size) 523 { 524 int count = 0; 525 u32 i; 526 527 for (i = 0; i < size; i++) 528 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num) 529 count++; 530 531 return count; 532 } 533 534 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, 535 const struct hclge_comm_stats_str strs[], 536 int size, u64 *data) 537 { 538 u64 *buf = data; 539 u32 i; 540 541 for (i = 0; i < size; i++) { 542 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 543 continue; 544 545 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset); 546 buf++; 547 } 548 549 return buf; 550 } 551 552 static u8 *hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, 553 const struct hclge_comm_stats_str strs[], 554 int size, u8 *data) 555 { 556 char *buff = (char *)data; 557 u32 i; 558 559 if (stringset != ETH_SS_STATS) 560 return buff; 561 562 for (i = 0; i < size; i++) { 563 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 564 continue; 565 566 snprintf(buff, ETH_GSTRING_LEN, "%s", strs[i].desc); 567 buff = buff + ETH_GSTRING_LEN; 568 } 569 570 return (u8 *)buff; 571 } 572 573 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 574 { 575 struct hnae3_handle *handle; 576 int status; 577 578 handle = &hdev->vport[0].nic; 579 if (handle->client) { 580 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 581 if (status) { 582 dev_err(&hdev->pdev->dev, 583 "Update TQPS stats fail, status = %d.\n", 584 status); 585 } 586 } 587 588 hclge_update_fec_stats(hdev); 589 590 status = hclge_mac_update_stats(hdev); 591 if (status) 592 dev_err(&hdev->pdev->dev, 593 "Update MAC stats fail, status = %d.\n", status); 594 } 595 596 static void hclge_update_stats(struct hnae3_handle *handle) 597 { 598 struct hclge_vport *vport = hclge_get_vport(handle); 599 struct hclge_dev *hdev = vport->back; 600 int status; 601 602 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 603 return; 604 605 status = hclge_mac_update_stats(hdev); 606 if (status) 607 dev_err(&hdev->pdev->dev, 608 "Update MAC stats fail, status = %d.\n", 609 status); 610 611 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 612 if (status) 613 dev_err(&hdev->pdev->dev, 614 "Update TQPS stats fail, status = %d.\n", 615 status); 616 617 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 618 } 619 620 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 621 { 622 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \ 623 HNAE3_SUPPORT_PHY_LOOPBACK | \ 624 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \ 625 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \ 626 HNAE3_SUPPORT_EXTERNAL_LOOPBACK) 627 628 struct hclge_vport *vport = hclge_get_vport(handle); 629 struct hclge_dev *hdev = vport->back; 630 int count = 0; 631 632 /* Loopback test support rules: 633 * mac: only GE mode support 634 * serdes: all mac mode will support include GE/XGE/LGE/CGE 635 * phy: only support when phy device exist on board 636 */ 637 if (stringset == ETH_SS_TEST) { 638 /* clear loopback bit flags at first */ 639 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 640 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 || 641 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 642 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 643 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 644 count += 1; 645 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; 646 } 647 648 count += 1; 649 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; 650 count += 1; 651 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; 652 count += 1; 653 handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK; 654 655 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv && 656 hdev->hw.mac.phydev->drv->set_loopback) || 657 hnae3_dev_phy_imp_supported(hdev)) { 658 count += 1; 659 handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK; 660 } 661 } else if (stringset == ETH_SS_STATS) { 662 count = hclge_comm_get_count(hdev, g_mac_stats_string, 663 ARRAY_SIZE(g_mac_stats_string)) + 664 hclge_comm_tqps_get_sset_count(handle); 665 } 666 667 return count; 668 } 669 670 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset, 671 u8 *data) 672 { 673 struct hclge_vport *vport = hclge_get_vport(handle); 674 struct hclge_dev *hdev = vport->back; 675 u8 *p = (char *)data; 676 int size; 677 678 if (stringset == ETH_SS_STATS) { 679 size = ARRAY_SIZE(g_mac_stats_string); 680 p = hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, 681 size, p); 682 p = hclge_comm_tqps_get_strings(handle, p); 683 } else if (stringset == ETH_SS_TEST) { 684 if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) { 685 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL], 686 ETH_GSTRING_LEN); 687 p += ETH_GSTRING_LEN; 688 } 689 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { 690 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_APP], 691 ETH_GSTRING_LEN); 692 p += ETH_GSTRING_LEN; 693 } 694 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { 695 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES], 696 ETH_GSTRING_LEN); 697 p += ETH_GSTRING_LEN; 698 } 699 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { 700 memcpy(p, 701 hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES], 702 ETH_GSTRING_LEN); 703 p += ETH_GSTRING_LEN; 704 } 705 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 706 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_PHY], 707 ETH_GSTRING_LEN); 708 p += ETH_GSTRING_LEN; 709 } 710 } 711 } 712 713 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 714 { 715 struct hclge_vport *vport = hclge_get_vport(handle); 716 struct hclge_dev *hdev = vport->back; 717 u64 *p; 718 719 p = hclge_comm_get_stats(hdev, g_mac_stats_string, 720 ARRAY_SIZE(g_mac_stats_string), data); 721 p = hclge_comm_tqps_get_stats(handle, p); 722 } 723 724 static void hclge_get_mac_stat(struct hnae3_handle *handle, 725 struct hns3_mac_stats *mac_stats) 726 { 727 struct hclge_vport *vport = hclge_get_vport(handle); 728 struct hclge_dev *hdev = vport->back; 729 730 hclge_update_stats(handle); 731 732 mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num; 733 mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num; 734 } 735 736 static int hclge_parse_func_status(struct hclge_dev *hdev, 737 struct hclge_func_status_cmd *status) 738 { 739 #define HCLGE_MAC_ID_MASK 0xF 740 741 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 742 return -EINVAL; 743 744 /* Set the pf to main pf */ 745 if (status->pf_state & HCLGE_PF_STATE_MAIN) 746 hdev->flag |= HCLGE_FLAG_MAIN; 747 else 748 hdev->flag &= ~HCLGE_FLAG_MAIN; 749 750 hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK; 751 return 0; 752 } 753 754 static int hclge_query_function_status(struct hclge_dev *hdev) 755 { 756 #define HCLGE_QUERY_MAX_CNT 5 757 758 struct hclge_func_status_cmd *req; 759 struct hclge_desc desc; 760 int timeout = 0; 761 int ret; 762 763 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 764 req = (struct hclge_func_status_cmd *)desc.data; 765 766 do { 767 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 768 if (ret) { 769 dev_err(&hdev->pdev->dev, 770 "query function status failed %d.\n", ret); 771 return ret; 772 } 773 774 /* Check pf reset is done */ 775 if (req->pf_state) 776 break; 777 usleep_range(1000, 2000); 778 } while (timeout++ < HCLGE_QUERY_MAX_CNT); 779 780 return hclge_parse_func_status(hdev, req); 781 } 782 783 static int hclge_query_pf_resource(struct hclge_dev *hdev) 784 { 785 struct hclge_pf_res_cmd *req; 786 struct hclge_desc desc; 787 int ret; 788 789 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 790 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 791 if (ret) { 792 dev_err(&hdev->pdev->dev, 793 "query pf resource failed %d.\n", ret); 794 return ret; 795 } 796 797 req = (struct hclge_pf_res_cmd *)desc.data; 798 hdev->num_tqps = le16_to_cpu(req->tqp_num) + 799 le16_to_cpu(req->ext_tqp_num); 800 hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 801 802 if (req->tx_buf_size) 803 hdev->tx_buf_size = 804 le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S; 805 else 806 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 807 808 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT); 809 810 if (req->dv_buf_size) 811 hdev->dv_buf_size = 812 le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S; 813 else 814 hdev->dv_buf_size = HCLGE_DEFAULT_DV; 815 816 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT); 817 818 hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic); 819 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) { 820 dev_err(&hdev->pdev->dev, 821 "only %u msi resources available, not enough for pf(min:2).\n", 822 hdev->num_nic_msi); 823 return -EINVAL; 824 } 825 826 if (hnae3_dev_roce_supported(hdev)) { 827 hdev->num_roce_msi = 828 le16_to_cpu(req->pf_intr_vector_number_roce); 829 830 /* PF should have NIC vectors and Roce vectors, 831 * NIC vectors are queued before Roce vectors. 832 */ 833 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi; 834 } else { 835 hdev->num_msi = hdev->num_nic_msi; 836 } 837 838 return 0; 839 } 840 841 static int hclge_parse_speed(u8 speed_cmd, u32 *speed) 842 { 843 switch (speed_cmd) { 844 case HCLGE_FW_MAC_SPEED_10M: 845 *speed = HCLGE_MAC_SPEED_10M; 846 break; 847 case HCLGE_FW_MAC_SPEED_100M: 848 *speed = HCLGE_MAC_SPEED_100M; 849 break; 850 case HCLGE_FW_MAC_SPEED_1G: 851 *speed = HCLGE_MAC_SPEED_1G; 852 break; 853 case HCLGE_FW_MAC_SPEED_10G: 854 *speed = HCLGE_MAC_SPEED_10G; 855 break; 856 case HCLGE_FW_MAC_SPEED_25G: 857 *speed = HCLGE_MAC_SPEED_25G; 858 break; 859 case HCLGE_FW_MAC_SPEED_40G: 860 *speed = HCLGE_MAC_SPEED_40G; 861 break; 862 case HCLGE_FW_MAC_SPEED_50G: 863 *speed = HCLGE_MAC_SPEED_50G; 864 break; 865 case HCLGE_FW_MAC_SPEED_100G: 866 *speed = HCLGE_MAC_SPEED_100G; 867 break; 868 case HCLGE_FW_MAC_SPEED_200G: 869 *speed = HCLGE_MAC_SPEED_200G; 870 break; 871 default: 872 return -EINVAL; 873 } 874 875 return 0; 876 } 877 878 static const struct hclge_speed_bit_map speed_bit_map[] = { 879 {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT}, 880 {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT}, 881 {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT}, 882 {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT}, 883 {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT}, 884 {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT}, 885 {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BIT}, 886 {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BIT}, 887 {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT}, 888 }; 889 890 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit) 891 { 892 u16 i; 893 894 for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) { 895 if (speed == speed_bit_map[i].speed) { 896 *speed_bit = speed_bit_map[i].speed_bit; 897 return 0; 898 } 899 } 900 901 return -EINVAL; 902 } 903 904 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed) 905 { 906 struct hclge_vport *vport = hclge_get_vport(handle); 907 struct hclge_dev *hdev = vport->back; 908 u32 speed_ability = hdev->hw.mac.speed_ability; 909 u32 speed_bit = 0; 910 int ret; 911 912 ret = hclge_get_speed_bit(speed, &speed_bit); 913 if (ret) 914 return ret; 915 916 if (speed_bit & speed_ability) 917 return 0; 918 919 return -EINVAL; 920 } 921 922 static void hclge_update_fec_support(struct hclge_mac *mac) 923 { 924 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported); 925 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported); 926 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported); 927 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 928 929 if (mac->fec_ability & BIT(HNAE3_FEC_BASER)) 930 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 931 mac->supported); 932 if (mac->fec_ability & BIT(HNAE3_FEC_RS)) 933 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 934 mac->supported); 935 if (mac->fec_ability & BIT(HNAE3_FEC_LLRS)) 936 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 937 mac->supported); 938 if (mac->fec_ability & BIT(HNAE3_FEC_NONE)) 939 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 940 mac->supported); 941 } 942 943 static void hclge_convert_setting_sr(u16 speed_ability, 944 unsigned long *link_mode) 945 { 946 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 947 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 948 link_mode); 949 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 950 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 951 link_mode); 952 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 953 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 954 link_mode); 955 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 956 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 957 link_mode); 958 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 959 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 960 link_mode); 961 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 962 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 963 link_mode); 964 } 965 966 static void hclge_convert_setting_lr(u16 speed_ability, 967 unsigned long *link_mode) 968 { 969 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 970 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 971 link_mode); 972 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 973 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 974 link_mode); 975 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 976 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 977 link_mode); 978 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 979 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 980 link_mode); 981 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 982 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 983 link_mode); 984 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 985 linkmode_set_bit( 986 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 987 link_mode); 988 } 989 990 static void hclge_convert_setting_cr(u16 speed_ability, 991 unsigned long *link_mode) 992 { 993 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 994 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 995 link_mode); 996 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 997 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 998 link_mode); 999 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1000 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 1001 link_mode); 1002 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1003 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 1004 link_mode); 1005 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1006 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 1007 link_mode); 1008 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1009 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 1010 link_mode); 1011 } 1012 1013 static void hclge_convert_setting_kr(u16 speed_ability, 1014 unsigned long *link_mode) 1015 { 1016 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1017 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1018 link_mode); 1019 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1020 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1021 link_mode); 1022 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1023 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 1024 link_mode); 1025 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1026 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 1027 link_mode); 1028 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1029 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 1030 link_mode); 1031 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1032 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 1033 link_mode); 1034 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1035 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 1036 link_mode); 1037 } 1038 1039 static void hclge_convert_setting_fec(struct hclge_mac *mac) 1040 { 1041 /* If firmware has reported fec_ability, don't need to convert by speed */ 1042 if (mac->fec_ability) 1043 goto out; 1044 1045 switch (mac->speed) { 1046 case HCLGE_MAC_SPEED_10G: 1047 case HCLGE_MAC_SPEED_40G: 1048 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) | 1049 BIT(HNAE3_FEC_NONE); 1050 break; 1051 case HCLGE_MAC_SPEED_25G: 1052 case HCLGE_MAC_SPEED_50G: 1053 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) | 1054 BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE); 1055 break; 1056 case HCLGE_MAC_SPEED_100G: 1057 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1058 BIT(HNAE3_FEC_NONE); 1059 break; 1060 case HCLGE_MAC_SPEED_200G: 1061 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1062 BIT(HNAE3_FEC_LLRS); 1063 break; 1064 default: 1065 mac->fec_ability = 0; 1066 break; 1067 } 1068 1069 out: 1070 hclge_update_fec_support(mac); 1071 } 1072 1073 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 1074 u16 speed_ability) 1075 { 1076 struct hclge_mac *mac = &hdev->hw.mac; 1077 1078 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1079 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1080 mac->supported); 1081 1082 hclge_convert_setting_sr(speed_ability, mac->supported); 1083 hclge_convert_setting_lr(speed_ability, mac->supported); 1084 hclge_convert_setting_cr(speed_ability, mac->supported); 1085 if (hnae3_dev_fec_supported(hdev)) 1086 hclge_convert_setting_fec(mac); 1087 1088 if (hnae3_dev_pause_supported(hdev)) 1089 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1090 1091 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported); 1092 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1093 } 1094 1095 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev, 1096 u16 speed_ability) 1097 { 1098 struct hclge_mac *mac = &hdev->hw.mac; 1099 1100 hclge_convert_setting_kr(speed_ability, mac->supported); 1101 if (hnae3_dev_fec_supported(hdev)) 1102 hclge_convert_setting_fec(mac); 1103 1104 if (hnae3_dev_pause_supported(hdev)) 1105 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1106 1107 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported); 1108 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1109 } 1110 1111 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev, 1112 u16 speed_ability) 1113 { 1114 unsigned long *supported = hdev->hw.mac.supported; 1115 1116 /* default to support all speed for GE port */ 1117 if (!speed_ability) 1118 speed_ability = HCLGE_SUPPORT_GE; 1119 1120 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1121 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1122 supported); 1123 1124 if (speed_ability & HCLGE_SUPPORT_100M_BIT) { 1125 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1126 supported); 1127 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1128 supported); 1129 } 1130 1131 if (speed_ability & HCLGE_SUPPORT_10M_BIT) { 1132 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported); 1133 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported); 1134 } 1135 1136 if (hnae3_dev_pause_supported(hdev)) { 1137 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1138 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 1139 } 1140 1141 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 1142 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 1143 } 1144 1145 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 1146 { 1147 u8 media_type = hdev->hw.mac.media_type; 1148 1149 if (media_type == HNAE3_MEDIA_TYPE_FIBER) 1150 hclge_parse_fiber_link_mode(hdev, speed_ability); 1151 else if (media_type == HNAE3_MEDIA_TYPE_COPPER) 1152 hclge_parse_copper_link_mode(hdev, speed_ability); 1153 else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE) 1154 hclge_parse_backplane_link_mode(hdev, speed_ability); 1155 } 1156 1157 static u32 hclge_get_max_speed(u16 speed_ability) 1158 { 1159 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1160 return HCLGE_MAC_SPEED_200G; 1161 1162 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1163 return HCLGE_MAC_SPEED_100G; 1164 1165 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1166 return HCLGE_MAC_SPEED_50G; 1167 1168 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1169 return HCLGE_MAC_SPEED_40G; 1170 1171 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1172 return HCLGE_MAC_SPEED_25G; 1173 1174 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1175 return HCLGE_MAC_SPEED_10G; 1176 1177 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1178 return HCLGE_MAC_SPEED_1G; 1179 1180 if (speed_ability & HCLGE_SUPPORT_100M_BIT) 1181 return HCLGE_MAC_SPEED_100M; 1182 1183 if (speed_ability & HCLGE_SUPPORT_10M_BIT) 1184 return HCLGE_MAC_SPEED_10M; 1185 1186 return HCLGE_MAC_SPEED_1G; 1187 } 1188 1189 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1190 { 1191 #define HCLGE_TX_SPARE_SIZE_UNIT 4096 1192 #define SPEED_ABILITY_EXT_SHIFT 8 1193 1194 struct hclge_cfg_param_cmd *req; 1195 u64 mac_addr_tmp_high; 1196 u16 speed_ability_ext; 1197 u64 mac_addr_tmp; 1198 unsigned int i; 1199 1200 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1201 1202 /* get the configuration */ 1203 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1204 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1205 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1206 HCLGE_CFG_TQP_DESC_N_M, 1207 HCLGE_CFG_TQP_DESC_N_S); 1208 1209 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1210 HCLGE_CFG_PHY_ADDR_M, 1211 HCLGE_CFG_PHY_ADDR_S); 1212 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1213 HCLGE_CFG_MEDIA_TP_M, 1214 HCLGE_CFG_MEDIA_TP_S); 1215 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1216 HCLGE_CFG_RX_BUF_LEN_M, 1217 HCLGE_CFG_RX_BUF_LEN_S); 1218 /* get mac_address */ 1219 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1220 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1221 HCLGE_CFG_MAC_ADDR_H_M, 1222 HCLGE_CFG_MAC_ADDR_H_S); 1223 1224 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1225 1226 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1227 HCLGE_CFG_DEFAULT_SPEED_M, 1228 HCLGE_CFG_DEFAULT_SPEED_S); 1229 cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1230 HCLGE_CFG_RSS_SIZE_M, 1231 HCLGE_CFG_RSS_SIZE_S); 1232 1233 for (i = 0; i < ETH_ALEN; i++) 1234 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1235 1236 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1237 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1238 1239 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1240 HCLGE_CFG_SPEED_ABILITY_M, 1241 HCLGE_CFG_SPEED_ABILITY_S); 1242 speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]), 1243 HCLGE_CFG_SPEED_ABILITY_EXT_M, 1244 HCLGE_CFG_SPEED_ABILITY_EXT_S); 1245 cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT; 1246 1247 cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]), 1248 HCLGE_CFG_VLAN_FLTR_CAP_M, 1249 HCLGE_CFG_VLAN_FLTR_CAP_S); 1250 1251 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]), 1252 HCLGE_CFG_UMV_TBL_SPACE_M, 1253 HCLGE_CFG_UMV_TBL_SPACE_S); 1254 1255 cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]), 1256 HCLGE_CFG_PF_RSS_SIZE_M, 1257 HCLGE_CFG_PF_RSS_SIZE_S); 1258 1259 /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a 1260 * power of 2, instead of reading out directly. This would 1261 * be more flexible for future changes and expansions. 1262 * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S, 1263 * it does not make sense if PF's field is 0. In this case, PF and VF 1264 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S. 1265 */ 1266 cfg->pf_rss_size_max = cfg->pf_rss_size_max ? 1267 1U << cfg->pf_rss_size_max : 1268 cfg->vf_rss_size_max; 1269 1270 /* The unit of the tx spare buffer size queried from configuration 1271 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is 1272 * needed here. 1273 */ 1274 cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]), 1275 HCLGE_CFG_TX_SPARE_BUF_SIZE_M, 1276 HCLGE_CFG_TX_SPARE_BUF_SIZE_S); 1277 cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT; 1278 } 1279 1280 /* hclge_get_cfg: query the static parameter from flash 1281 * @hdev: pointer to struct hclge_dev 1282 * @hcfg: the config structure to be getted 1283 */ 1284 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1285 { 1286 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1287 struct hclge_cfg_param_cmd *req; 1288 unsigned int i; 1289 int ret; 1290 1291 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1292 u32 offset = 0; 1293 1294 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1295 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1296 true); 1297 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1298 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1299 /* Len should be united by 4 bytes when send to hardware */ 1300 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1301 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1302 req->offset = cpu_to_le32(offset); 1303 } 1304 1305 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1306 if (ret) { 1307 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1308 return ret; 1309 } 1310 1311 hclge_parse_cfg(hcfg, desc); 1312 1313 return 0; 1314 } 1315 1316 static void hclge_set_default_dev_specs(struct hclge_dev *hdev) 1317 { 1318 #define HCLGE_MAX_NON_TSO_BD_NUM 8U 1319 1320 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1321 1322 ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1323 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1324 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1325 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE; 1326 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL; 1327 ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME; 1328 ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM; 1329 ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1330 ae_dev->dev_specs.tnl_num = 0; 1331 } 1332 1333 static void hclge_parse_dev_specs(struct hclge_dev *hdev, 1334 struct hclge_desc *desc) 1335 { 1336 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1337 struct hclge_dev_specs_0_cmd *req0; 1338 struct hclge_dev_specs_1_cmd *req1; 1339 1340 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data; 1341 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data; 1342 1343 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 1344 ae_dev->dev_specs.rss_ind_tbl_size = 1345 le16_to_cpu(req0->rss_ind_tbl_size); 1346 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 1347 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 1348 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate); 1349 ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num); 1350 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 1351 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 1352 ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size); 1353 ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size); 1354 ae_dev->dev_specs.tnl_num = req1->tnl_num; 1355 } 1356 1357 static void hclge_check_dev_specs(struct hclge_dev *hdev) 1358 { 1359 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 1360 1361 if (!dev_specs->max_non_tso_bd_num) 1362 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1363 if (!dev_specs->rss_ind_tbl_size) 1364 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1365 if (!dev_specs->rss_key_size) 1366 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1367 if (!dev_specs->max_tm_rate) 1368 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE; 1369 if (!dev_specs->max_qset_num) 1370 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM; 1371 if (!dev_specs->max_int_gl) 1372 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL; 1373 if (!dev_specs->max_frm_size) 1374 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME; 1375 if (!dev_specs->umv_size) 1376 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1377 } 1378 1379 static int hclge_query_mac_stats_num(struct hclge_dev *hdev) 1380 { 1381 u32 reg_num = 0; 1382 int ret; 1383 1384 ret = hclge_mac_query_reg_num(hdev, ®_num); 1385 if (ret && ret != -EOPNOTSUPP) 1386 return ret; 1387 1388 hdev->ae_dev->dev_specs.mac_stats_num = reg_num; 1389 return 0; 1390 } 1391 1392 static int hclge_query_dev_specs(struct hclge_dev *hdev) 1393 { 1394 struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM]; 1395 int ret; 1396 int i; 1397 1398 ret = hclge_query_mac_stats_num(hdev); 1399 if (ret) 1400 return ret; 1401 1402 /* set default specifications as devices lower than version V3 do not 1403 * support querying specifications from firmware. 1404 */ 1405 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 1406 hclge_set_default_dev_specs(hdev); 1407 return 0; 1408 } 1409 1410 for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1411 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, 1412 true); 1413 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 1414 } 1415 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 1416 1417 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM); 1418 if (ret) 1419 return ret; 1420 1421 hclge_parse_dev_specs(hdev, desc); 1422 hclge_check_dev_specs(hdev); 1423 1424 return 0; 1425 } 1426 1427 static int hclge_get_cap(struct hclge_dev *hdev) 1428 { 1429 int ret; 1430 1431 ret = hclge_query_function_status(hdev); 1432 if (ret) { 1433 dev_err(&hdev->pdev->dev, 1434 "query function status error %d.\n", ret); 1435 return ret; 1436 } 1437 1438 /* get pf resource */ 1439 return hclge_query_pf_resource(hdev); 1440 } 1441 1442 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev) 1443 { 1444 #define HCLGE_MIN_TX_DESC 64 1445 #define HCLGE_MIN_RX_DESC 64 1446 1447 if (!is_kdump_kernel()) 1448 return; 1449 1450 dev_info(&hdev->pdev->dev, 1451 "Running kdump kernel. Using minimal resources\n"); 1452 1453 /* minimal queue pairs equals to the number of vports */ 1454 hdev->num_tqps = hdev->num_req_vfs + 1; 1455 hdev->num_tx_desc = HCLGE_MIN_TX_DESC; 1456 hdev->num_rx_desc = HCLGE_MIN_RX_DESC; 1457 } 1458 1459 static void hclge_init_tc_config(struct hclge_dev *hdev) 1460 { 1461 unsigned int i; 1462 1463 if (hdev->tc_max > HNAE3_MAX_TC || 1464 hdev->tc_max < 1) { 1465 dev_warn(&hdev->pdev->dev, "TC num = %u.\n", 1466 hdev->tc_max); 1467 hdev->tc_max = 1; 1468 } 1469 1470 /* Dev does not support DCB */ 1471 if (!hnae3_dev_dcb_supported(hdev)) { 1472 hdev->tc_max = 1; 1473 hdev->pfc_max = 0; 1474 } else { 1475 hdev->pfc_max = hdev->tc_max; 1476 } 1477 1478 hdev->tm_info.num_tc = 1; 1479 1480 /* Currently not support uncontiuous tc */ 1481 for (i = 0; i < hdev->tm_info.num_tc; i++) 1482 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1483 1484 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1485 } 1486 1487 static int hclge_configure(struct hclge_dev *hdev) 1488 { 1489 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1490 struct hclge_cfg cfg; 1491 int ret; 1492 1493 ret = hclge_get_cfg(hdev, &cfg); 1494 if (ret) 1495 return ret; 1496 1497 hdev->base_tqp_pid = 0; 1498 hdev->vf_rss_size_max = cfg.vf_rss_size_max; 1499 hdev->pf_rss_size_max = cfg.pf_rss_size_max; 1500 hdev->rx_buf_len = cfg.rx_buf_len; 1501 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1502 hdev->hw.mac.media_type = cfg.media_type; 1503 hdev->hw.mac.phy_addr = cfg.phy_addr; 1504 hdev->num_tx_desc = cfg.tqp_desc_num; 1505 hdev->num_rx_desc = cfg.tqp_desc_num; 1506 hdev->tm_info.num_pg = 1; 1507 hdev->tc_max = cfg.tc_num; 1508 hdev->tm_info.hw_pfc_map = 0; 1509 if (cfg.umv_space) 1510 hdev->wanted_umv_size = cfg.umv_space; 1511 else 1512 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size; 1513 hdev->tx_spare_buf_size = cfg.tx_spare_buf_size; 1514 hdev->gro_en = true; 1515 if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF) 1516 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 1517 1518 if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 1519 hdev->fd_en = true; 1520 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 1521 } 1522 1523 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1524 if (ret) { 1525 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n", 1526 cfg.default_speed, ret); 1527 return ret; 1528 } 1529 1530 hclge_parse_link_mode(hdev, cfg.speed_ability); 1531 1532 hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability); 1533 1534 hclge_init_tc_config(hdev); 1535 hclge_init_kdump_kernel_config(hdev); 1536 1537 return ret; 1538 } 1539 1540 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min, 1541 u16 tso_mss_max) 1542 { 1543 struct hclge_cfg_tso_status_cmd *req; 1544 struct hclge_desc desc; 1545 1546 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1547 1548 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1549 req->tso_mss_min = cpu_to_le16(tso_mss_min); 1550 req->tso_mss_max = cpu_to_le16(tso_mss_max); 1551 1552 return hclge_cmd_send(&hdev->hw, &desc, 1); 1553 } 1554 1555 static int hclge_config_gro(struct hclge_dev *hdev) 1556 { 1557 struct hclge_cfg_gro_status_cmd *req; 1558 struct hclge_desc desc; 1559 int ret; 1560 1561 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 1562 return 0; 1563 1564 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false); 1565 req = (struct hclge_cfg_gro_status_cmd *)desc.data; 1566 1567 req->gro_en = hdev->gro_en ? 1 : 0; 1568 1569 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1570 if (ret) 1571 dev_err(&hdev->pdev->dev, 1572 "GRO hardware config cmd failed, ret = %d\n", ret); 1573 1574 return ret; 1575 } 1576 1577 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1578 { 1579 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1580 struct hclge_comm_tqp *tqp; 1581 int i; 1582 1583 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1584 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 1585 if (!hdev->htqp) 1586 return -ENOMEM; 1587 1588 tqp = hdev->htqp; 1589 1590 for (i = 0; i < hdev->num_tqps; i++) { 1591 tqp->dev = &hdev->pdev->dev; 1592 tqp->index = i; 1593 1594 tqp->q.ae_algo = &ae_algo; 1595 tqp->q.buf_size = hdev->rx_buf_len; 1596 tqp->q.tx_desc_num = hdev->num_tx_desc; 1597 tqp->q.rx_desc_num = hdev->num_rx_desc; 1598 1599 /* need an extended offset to configure queues >= 1600 * HCLGE_TQP_MAX_SIZE_DEV_V2 1601 */ 1602 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2) 1603 tqp->q.io_base = hdev->hw.hw.io_base + 1604 HCLGE_TQP_REG_OFFSET + 1605 i * HCLGE_TQP_REG_SIZE; 1606 else 1607 tqp->q.io_base = hdev->hw.hw.io_base + 1608 HCLGE_TQP_REG_OFFSET + 1609 HCLGE_TQP_EXT_REG_OFFSET + 1610 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) * 1611 HCLGE_TQP_REG_SIZE; 1612 1613 /* when device supports tx push and has device memory, 1614 * the queue can execute push mode or doorbell mode on 1615 * device memory. 1616 */ 1617 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 1618 tqp->q.mem_base = hdev->hw.hw.mem_base + 1619 HCLGE_TQP_MEM_OFFSET(hdev, i); 1620 1621 tqp++; 1622 } 1623 1624 return 0; 1625 } 1626 1627 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1628 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1629 { 1630 struct hclge_tqp_map_cmd *req; 1631 struct hclge_desc desc; 1632 int ret; 1633 1634 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1635 1636 req = (struct hclge_tqp_map_cmd *)desc.data; 1637 req->tqp_id = cpu_to_le16(tqp_pid); 1638 req->tqp_vf = func_id; 1639 req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B; 1640 if (!is_pf) 1641 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B; 1642 req->tqp_vid = cpu_to_le16(tqp_vid); 1643 1644 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1645 if (ret) 1646 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1647 1648 return ret; 1649 } 1650 1651 static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) 1652 { 1653 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1654 struct hclge_dev *hdev = vport->back; 1655 int i, alloced; 1656 1657 for (i = 0, alloced = 0; i < hdev->num_tqps && 1658 alloced < num_tqps; i++) { 1659 if (!hdev->htqp[i].alloced) { 1660 hdev->htqp[i].q.handle = &vport->nic; 1661 hdev->htqp[i].q.tqp_index = alloced; 1662 hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc; 1663 hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc; 1664 kinfo->tqp[alloced] = &hdev->htqp[i].q; 1665 hdev->htqp[i].alloced = true; 1666 alloced++; 1667 } 1668 } 1669 vport->alloc_tqps = alloced; 1670 kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max, 1671 vport->alloc_tqps / hdev->tm_info.num_tc); 1672 1673 /* ensure one to one mapping between irq and queue at default */ 1674 kinfo->rss_size = min_t(u16, kinfo->rss_size, 1675 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc); 1676 1677 return 0; 1678 } 1679 1680 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps, 1681 u16 num_tx_desc, u16 num_rx_desc) 1682 1683 { 1684 struct hnae3_handle *nic = &vport->nic; 1685 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1686 struct hclge_dev *hdev = vport->back; 1687 int ret; 1688 1689 kinfo->num_tx_desc = num_tx_desc; 1690 kinfo->num_rx_desc = num_rx_desc; 1691 1692 kinfo->rx_buf_len = hdev->rx_buf_len; 1693 kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size; 1694 1695 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps, 1696 sizeof(struct hnae3_queue *), GFP_KERNEL); 1697 if (!kinfo->tqp) 1698 return -ENOMEM; 1699 1700 ret = hclge_assign_tqp(vport, num_tqps); 1701 if (ret) 1702 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1703 1704 return ret; 1705 } 1706 1707 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1708 struct hclge_vport *vport) 1709 { 1710 struct hnae3_handle *nic = &vport->nic; 1711 struct hnae3_knic_private_info *kinfo; 1712 u16 i; 1713 1714 kinfo = &nic->kinfo; 1715 for (i = 0; i < vport->alloc_tqps; i++) { 1716 struct hclge_comm_tqp *q = 1717 container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); 1718 bool is_pf; 1719 int ret; 1720 1721 is_pf = !(vport->vport_id); 1722 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1723 i, is_pf); 1724 if (ret) 1725 return ret; 1726 } 1727 1728 return 0; 1729 } 1730 1731 static int hclge_map_tqp(struct hclge_dev *hdev) 1732 { 1733 struct hclge_vport *vport = hdev->vport; 1734 u16 i, num_vport; 1735 1736 num_vport = hdev->num_req_vfs + 1; 1737 for (i = 0; i < num_vport; i++) { 1738 int ret; 1739 1740 ret = hclge_map_tqp_to_vport(hdev, vport); 1741 if (ret) 1742 return ret; 1743 1744 vport++; 1745 } 1746 1747 return 0; 1748 } 1749 1750 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1751 { 1752 struct hnae3_handle *nic = &vport->nic; 1753 struct hclge_dev *hdev = vport->back; 1754 int ret; 1755 1756 nic->pdev = hdev->pdev; 1757 nic->ae_algo = &ae_algo; 1758 nic->numa_node_mask = hdev->numa_node_mask; 1759 nic->kinfo.io_base = hdev->hw.hw.io_base; 1760 1761 ret = hclge_knic_setup(vport, num_tqps, 1762 hdev->num_tx_desc, hdev->num_rx_desc); 1763 if (ret) 1764 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret); 1765 1766 return ret; 1767 } 1768 1769 static int hclge_alloc_vport(struct hclge_dev *hdev) 1770 { 1771 struct pci_dev *pdev = hdev->pdev; 1772 struct hclge_vport *vport; 1773 u32 tqp_main_vport; 1774 u32 tqp_per_vport; 1775 int num_vport, i; 1776 int ret; 1777 1778 /* We need to alloc a vport for main NIC of PF */ 1779 num_vport = hdev->num_req_vfs + 1; 1780 1781 if (hdev->num_tqps < num_vport) { 1782 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)", 1783 hdev->num_tqps, num_vport); 1784 return -EINVAL; 1785 } 1786 1787 /* Alloc the same number of TQPs for every vport */ 1788 tqp_per_vport = hdev->num_tqps / num_vport; 1789 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1790 1791 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1792 GFP_KERNEL); 1793 if (!vport) 1794 return -ENOMEM; 1795 1796 hdev->vport = vport; 1797 hdev->num_alloc_vport = num_vport; 1798 1799 if (IS_ENABLED(CONFIG_PCI_IOV)) 1800 hdev->num_alloc_vfs = hdev->num_req_vfs; 1801 1802 for (i = 0; i < num_vport; i++) { 1803 vport->back = hdev; 1804 vport->vport_id = i; 1805 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO; 1806 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 1807 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE; 1808 vport->port_base_vlan_cfg.tbl_sta = true; 1809 vport->rxvlan_cfg.rx_vlan_offload_en = true; 1810 vport->req_vlan_fltr_en = true; 1811 INIT_LIST_HEAD(&vport->vlan_list); 1812 INIT_LIST_HEAD(&vport->uc_mac_list); 1813 INIT_LIST_HEAD(&vport->mc_mac_list); 1814 spin_lock_init(&vport->mac_list_lock); 1815 1816 if (i == 0) 1817 ret = hclge_vport_setup(vport, tqp_main_vport); 1818 else 1819 ret = hclge_vport_setup(vport, tqp_per_vport); 1820 if (ret) { 1821 dev_err(&pdev->dev, 1822 "vport setup failed for vport %d, %d\n", 1823 i, ret); 1824 return ret; 1825 } 1826 1827 vport++; 1828 } 1829 1830 return 0; 1831 } 1832 1833 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1834 struct hclge_pkt_buf_alloc *buf_alloc) 1835 { 1836 /* TX buffer size is unit by 128 byte */ 1837 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1838 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1839 struct hclge_tx_buff_alloc_cmd *req; 1840 struct hclge_desc desc; 1841 int ret; 1842 u8 i; 1843 1844 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1845 1846 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1847 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1848 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1849 1850 req->tx_pkt_buff[i] = 1851 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1852 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1853 } 1854 1855 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1856 if (ret) 1857 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1858 ret); 1859 1860 return ret; 1861 } 1862 1863 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1864 struct hclge_pkt_buf_alloc *buf_alloc) 1865 { 1866 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1867 1868 if (ret) 1869 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1870 1871 return ret; 1872 } 1873 1874 static u32 hclge_get_tc_num(struct hclge_dev *hdev) 1875 { 1876 unsigned int i; 1877 u32 cnt = 0; 1878 1879 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1880 if (hdev->hw_tc_map & BIT(i)) 1881 cnt++; 1882 return cnt; 1883 } 1884 1885 /* Get the number of pfc enabled TCs, which have private buffer */ 1886 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1887 struct hclge_pkt_buf_alloc *buf_alloc) 1888 { 1889 struct hclge_priv_buf *priv; 1890 unsigned int i; 1891 int cnt = 0; 1892 1893 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1894 priv = &buf_alloc->priv_buf[i]; 1895 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1896 priv->enable) 1897 cnt++; 1898 } 1899 1900 return cnt; 1901 } 1902 1903 /* Get the number of pfc disabled TCs, which have private buffer */ 1904 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1905 struct hclge_pkt_buf_alloc *buf_alloc) 1906 { 1907 struct hclge_priv_buf *priv; 1908 unsigned int i; 1909 int cnt = 0; 1910 1911 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1912 priv = &buf_alloc->priv_buf[i]; 1913 if (hdev->hw_tc_map & BIT(i) && 1914 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 1915 priv->enable) 1916 cnt++; 1917 } 1918 1919 return cnt; 1920 } 1921 1922 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1923 { 1924 struct hclge_priv_buf *priv; 1925 u32 rx_priv = 0; 1926 int i; 1927 1928 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1929 priv = &buf_alloc->priv_buf[i]; 1930 if (priv->enable) 1931 rx_priv += priv->buf_size; 1932 } 1933 return rx_priv; 1934 } 1935 1936 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1937 { 1938 u32 i, total_tx_size = 0; 1939 1940 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1941 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 1942 1943 return total_tx_size; 1944 } 1945 1946 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 1947 struct hclge_pkt_buf_alloc *buf_alloc, 1948 u32 rx_all) 1949 { 1950 u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 1951 u32 tc_num = hclge_get_tc_num(hdev); 1952 u32 shared_buf, aligned_mps; 1953 u32 rx_priv; 1954 int i; 1955 1956 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT); 1957 1958 if (hnae3_dev_dcb_supported(hdev)) 1959 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps + 1960 hdev->dv_buf_size; 1961 else 1962 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF 1963 + hdev->dv_buf_size; 1964 1965 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 1966 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc), 1967 HCLGE_BUF_SIZE_UNIT); 1968 1969 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 1970 if (rx_all < rx_priv + shared_std) 1971 return false; 1972 1973 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT); 1974 buf_alloc->s_buf.buf_size = shared_buf; 1975 if (hnae3_dev_dcb_supported(hdev)) { 1976 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size; 1977 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 1978 - roundup(aligned_mps / HCLGE_BUF_DIV_BY, 1979 HCLGE_BUF_SIZE_UNIT); 1980 } else { 1981 buf_alloc->s_buf.self.high = aligned_mps + 1982 HCLGE_NON_DCB_ADDITIONAL_BUF; 1983 buf_alloc->s_buf.self.low = aligned_mps; 1984 } 1985 1986 if (hnae3_dev_dcb_supported(hdev)) { 1987 hi_thrd = shared_buf - hdev->dv_buf_size; 1988 1989 if (tc_num <= NEED_RESERVE_TC_NUM) 1990 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 1991 / BUF_MAX_PERCENT; 1992 1993 if (tc_num) 1994 hi_thrd = hi_thrd / tc_num; 1995 1996 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps); 1997 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT); 1998 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY; 1999 } else { 2000 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF; 2001 lo_thrd = aligned_mps; 2002 } 2003 2004 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2005 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 2006 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 2007 } 2008 2009 return true; 2010 } 2011 2012 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 2013 struct hclge_pkt_buf_alloc *buf_alloc) 2014 { 2015 u32 i, total_size; 2016 2017 total_size = hdev->pkt_buf_size; 2018 2019 /* alloc tx buffer for all enabled tc */ 2020 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2021 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2022 2023 if (hdev->hw_tc_map & BIT(i)) { 2024 if (total_size < hdev->tx_buf_size) 2025 return -ENOMEM; 2026 2027 priv->tx_buf_size = hdev->tx_buf_size; 2028 } else { 2029 priv->tx_buf_size = 0; 2030 } 2031 2032 total_size -= priv->tx_buf_size; 2033 } 2034 2035 return 0; 2036 } 2037 2038 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max, 2039 struct hclge_pkt_buf_alloc *buf_alloc) 2040 { 2041 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2042 u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2043 unsigned int i; 2044 2045 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2046 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2047 2048 priv->enable = 0; 2049 priv->wl.low = 0; 2050 priv->wl.high = 0; 2051 priv->buf_size = 0; 2052 2053 if (!(hdev->hw_tc_map & BIT(i))) 2054 continue; 2055 2056 priv->enable = 1; 2057 2058 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 2059 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT; 2060 priv->wl.high = roundup(priv->wl.low + aligned_mps, 2061 HCLGE_BUF_SIZE_UNIT); 2062 } else { 2063 priv->wl.low = 0; 2064 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) : 2065 aligned_mps; 2066 } 2067 2068 priv->buf_size = priv->wl.high + hdev->dv_buf_size; 2069 } 2070 2071 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2072 } 2073 2074 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev, 2075 struct hclge_pkt_buf_alloc *buf_alloc) 2076 { 2077 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2078 int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 2079 int i; 2080 2081 /* let the last to be cleared first */ 2082 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2083 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2084 unsigned int mask = BIT((unsigned int)i); 2085 2086 if (hdev->hw_tc_map & mask && 2087 !(hdev->tm_info.hw_pfc_map & mask)) { 2088 /* Clear the no pfc TC private buffer */ 2089 priv->wl.low = 0; 2090 priv->wl.high = 0; 2091 priv->buf_size = 0; 2092 priv->enable = 0; 2093 no_pfc_priv_num--; 2094 } 2095 2096 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2097 no_pfc_priv_num == 0) 2098 break; 2099 } 2100 2101 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2102 } 2103 2104 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev, 2105 struct hclge_pkt_buf_alloc *buf_alloc) 2106 { 2107 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2108 int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 2109 int i; 2110 2111 /* let the last to be cleared first */ 2112 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2113 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2114 unsigned int mask = BIT((unsigned int)i); 2115 2116 if (hdev->hw_tc_map & mask && 2117 hdev->tm_info.hw_pfc_map & mask) { 2118 /* Reduce the number of pfc TC with private buffer */ 2119 priv->wl.low = 0; 2120 priv->enable = 0; 2121 priv->wl.high = 0; 2122 priv->buf_size = 0; 2123 pfc_priv_num--; 2124 } 2125 2126 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2127 pfc_priv_num == 0) 2128 break; 2129 } 2130 2131 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2132 } 2133 2134 static int hclge_only_alloc_priv_buff(struct hclge_dev *hdev, 2135 struct hclge_pkt_buf_alloc *buf_alloc) 2136 { 2137 #define COMPENSATE_BUFFER 0x3C00 2138 #define COMPENSATE_HALF_MPS_NUM 5 2139 #define PRIV_WL_GAP 0x1800 2140 2141 u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2142 u32 tc_num = hclge_get_tc_num(hdev); 2143 u32 half_mps = hdev->mps >> 1; 2144 u32 min_rx_priv; 2145 unsigned int i; 2146 2147 if (tc_num) 2148 rx_priv = rx_priv / tc_num; 2149 2150 if (tc_num <= NEED_RESERVE_TC_NUM) 2151 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 2152 2153 min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER + 2154 COMPENSATE_HALF_MPS_NUM * half_mps; 2155 min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT); 2156 rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT); 2157 if (rx_priv < min_rx_priv) 2158 return false; 2159 2160 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2161 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2162 2163 priv->enable = 0; 2164 priv->wl.low = 0; 2165 priv->wl.high = 0; 2166 priv->buf_size = 0; 2167 2168 if (!(hdev->hw_tc_map & BIT(i))) 2169 continue; 2170 2171 priv->enable = 1; 2172 priv->buf_size = rx_priv; 2173 priv->wl.high = rx_priv - hdev->dv_buf_size; 2174 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 2175 } 2176 2177 buf_alloc->s_buf.buf_size = 0; 2178 2179 return true; 2180 } 2181 2182 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 2183 * @hdev: pointer to struct hclge_dev 2184 * @buf_alloc: pointer to buffer calculation data 2185 * @return: 0: calculate successful, negative: fail 2186 */ 2187 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 2188 struct hclge_pkt_buf_alloc *buf_alloc) 2189 { 2190 /* When DCB is not supported, rx private buffer is not allocated. */ 2191 if (!hnae3_dev_dcb_supported(hdev)) { 2192 u32 rx_all = hdev->pkt_buf_size; 2193 2194 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 2195 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 2196 return -ENOMEM; 2197 2198 return 0; 2199 } 2200 2201 if (hclge_only_alloc_priv_buff(hdev, buf_alloc)) 2202 return 0; 2203 2204 if (hclge_rx_buf_calc_all(hdev, true, buf_alloc)) 2205 return 0; 2206 2207 /* try to decrease the buffer size */ 2208 if (hclge_rx_buf_calc_all(hdev, false, buf_alloc)) 2209 return 0; 2210 2211 if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc)) 2212 return 0; 2213 2214 if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc)) 2215 return 0; 2216 2217 return -ENOMEM; 2218 } 2219 2220 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 2221 struct hclge_pkt_buf_alloc *buf_alloc) 2222 { 2223 struct hclge_rx_priv_buff_cmd *req; 2224 struct hclge_desc desc; 2225 int ret; 2226 int i; 2227 2228 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 2229 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 2230 2231 /* Alloc private buffer TCs */ 2232 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2233 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2234 2235 req->buf_num[i] = 2236 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 2237 req->buf_num[i] |= 2238 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 2239 } 2240 2241 req->shared_buf = 2242 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 2243 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 2244 2245 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2246 if (ret) 2247 dev_err(&hdev->pdev->dev, 2248 "rx private buffer alloc cmd failed %d\n", ret); 2249 2250 return ret; 2251 } 2252 2253 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 2254 struct hclge_pkt_buf_alloc *buf_alloc) 2255 { 2256 struct hclge_rx_priv_wl_buf *req; 2257 struct hclge_priv_buf *priv; 2258 struct hclge_desc desc[2]; 2259 int i, j; 2260 int ret; 2261 2262 for (i = 0; i < 2; i++) { 2263 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 2264 false); 2265 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 2266 2267 /* The first descriptor set the NEXT bit to 1 */ 2268 if (i == 0) 2269 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2270 else 2271 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2272 2273 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2274 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 2275 2276 priv = &buf_alloc->priv_buf[idx]; 2277 req->tc_wl[j].high = 2278 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 2279 req->tc_wl[j].high |= 2280 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2281 req->tc_wl[j].low = 2282 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 2283 req->tc_wl[j].low |= 2284 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2285 } 2286 } 2287 2288 /* Send 2 descriptor at one time */ 2289 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2290 if (ret) 2291 dev_err(&hdev->pdev->dev, 2292 "rx private waterline config cmd failed %d\n", 2293 ret); 2294 return ret; 2295 } 2296 2297 static int hclge_common_thrd_config(struct hclge_dev *hdev, 2298 struct hclge_pkt_buf_alloc *buf_alloc) 2299 { 2300 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 2301 struct hclge_rx_com_thrd *req; 2302 struct hclge_desc desc[2]; 2303 struct hclge_tc_thrd *tc; 2304 int i, j; 2305 int ret; 2306 2307 for (i = 0; i < 2; i++) { 2308 hclge_cmd_setup_basic_desc(&desc[i], 2309 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 2310 req = (struct hclge_rx_com_thrd *)&desc[i].data; 2311 2312 /* The first descriptor set the NEXT bit to 1 */ 2313 if (i == 0) 2314 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2315 else 2316 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2317 2318 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2319 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 2320 2321 req->com_thrd[j].high = 2322 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 2323 req->com_thrd[j].high |= 2324 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2325 req->com_thrd[j].low = 2326 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 2327 req->com_thrd[j].low |= 2328 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2329 } 2330 } 2331 2332 /* Send 2 descriptors at one time */ 2333 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2334 if (ret) 2335 dev_err(&hdev->pdev->dev, 2336 "common threshold config cmd failed %d\n", ret); 2337 return ret; 2338 } 2339 2340 static int hclge_common_wl_config(struct hclge_dev *hdev, 2341 struct hclge_pkt_buf_alloc *buf_alloc) 2342 { 2343 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 2344 struct hclge_rx_com_wl *req; 2345 struct hclge_desc desc; 2346 int ret; 2347 2348 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 2349 2350 req = (struct hclge_rx_com_wl *)desc.data; 2351 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 2352 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2353 2354 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 2355 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2356 2357 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2358 if (ret) 2359 dev_err(&hdev->pdev->dev, 2360 "common waterline config cmd failed %d\n", ret); 2361 2362 return ret; 2363 } 2364 2365 int hclge_buffer_alloc(struct hclge_dev *hdev) 2366 { 2367 struct hclge_pkt_buf_alloc *pkt_buf; 2368 int ret; 2369 2370 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 2371 if (!pkt_buf) 2372 return -ENOMEM; 2373 2374 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 2375 if (ret) { 2376 dev_err(&hdev->pdev->dev, 2377 "could not calc tx buffer size for all TCs %d\n", ret); 2378 goto out; 2379 } 2380 2381 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 2382 if (ret) { 2383 dev_err(&hdev->pdev->dev, 2384 "could not alloc tx buffers %d\n", ret); 2385 goto out; 2386 } 2387 2388 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 2389 if (ret) { 2390 dev_err(&hdev->pdev->dev, 2391 "could not calc rx priv buffer size for all TCs %d\n", 2392 ret); 2393 goto out; 2394 } 2395 2396 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 2397 if (ret) { 2398 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 2399 ret); 2400 goto out; 2401 } 2402 2403 if (hnae3_dev_dcb_supported(hdev)) { 2404 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2405 if (ret) { 2406 dev_err(&hdev->pdev->dev, 2407 "could not configure rx private waterline %d\n", 2408 ret); 2409 goto out; 2410 } 2411 2412 ret = hclge_common_thrd_config(hdev, pkt_buf); 2413 if (ret) { 2414 dev_err(&hdev->pdev->dev, 2415 "could not configure common threshold %d\n", 2416 ret); 2417 goto out; 2418 } 2419 } 2420 2421 ret = hclge_common_wl_config(hdev, pkt_buf); 2422 if (ret) 2423 dev_err(&hdev->pdev->dev, 2424 "could not configure common waterline %d\n", ret); 2425 2426 out: 2427 kfree(pkt_buf); 2428 return ret; 2429 } 2430 2431 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2432 { 2433 struct hnae3_handle *roce = &vport->roce; 2434 struct hnae3_handle *nic = &vport->nic; 2435 struct hclge_dev *hdev = vport->back; 2436 2437 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2438 2439 if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi) 2440 return -EINVAL; 2441 2442 roce->rinfo.base_vector = hdev->num_nic_msi; 2443 2444 roce->rinfo.netdev = nic->kinfo.netdev; 2445 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2446 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2447 2448 roce->pdev = nic->pdev; 2449 roce->ae_algo = nic->ae_algo; 2450 roce->numa_node_mask = nic->numa_node_mask; 2451 2452 return 0; 2453 } 2454 2455 static int hclge_init_msi(struct hclge_dev *hdev) 2456 { 2457 struct pci_dev *pdev = hdev->pdev; 2458 int vectors; 2459 int i; 2460 2461 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2462 hdev->num_msi, 2463 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2464 if (vectors < 0) { 2465 dev_err(&pdev->dev, 2466 "failed(%d) to allocate MSI/MSI-X vectors\n", 2467 vectors); 2468 return vectors; 2469 } 2470 if (vectors < hdev->num_msi) 2471 dev_warn(&hdev->pdev->dev, 2472 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2473 hdev->num_msi, vectors); 2474 2475 hdev->num_msi = vectors; 2476 hdev->num_msi_left = vectors; 2477 2478 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2479 sizeof(u16), GFP_KERNEL); 2480 if (!hdev->vector_status) { 2481 pci_free_irq_vectors(pdev); 2482 return -ENOMEM; 2483 } 2484 2485 for (i = 0; i < hdev->num_msi; i++) 2486 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2487 2488 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2489 sizeof(int), GFP_KERNEL); 2490 if (!hdev->vector_irq) { 2491 pci_free_irq_vectors(pdev); 2492 return -ENOMEM; 2493 } 2494 2495 return 0; 2496 } 2497 2498 static u8 hclge_check_speed_dup(u8 duplex, int speed) 2499 { 2500 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 2501 duplex = HCLGE_MAC_FULL; 2502 2503 return duplex; 2504 } 2505 2506 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = { 2507 {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M}, 2508 {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M}, 2509 {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G}, 2510 {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G}, 2511 {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G}, 2512 {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G}, 2513 {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G}, 2514 {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G}, 2515 {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G}, 2516 }; 2517 2518 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw) 2519 { 2520 u16 i; 2521 2522 for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) { 2523 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) { 2524 *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw; 2525 return 0; 2526 } 2527 } 2528 2529 return -EINVAL; 2530 } 2531 2532 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 2533 u8 duplex, u8 lane_num) 2534 { 2535 struct hclge_config_mac_speed_dup_cmd *req; 2536 struct hclge_desc desc; 2537 u32 speed_fw; 2538 int ret; 2539 2540 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2541 2542 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2543 2544 if (duplex) 2545 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1); 2546 2547 ret = hclge_convert_to_fw_speed(speed, &speed_fw); 2548 if (ret) { 2549 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2550 return ret; 2551 } 2552 2553 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S, 2554 speed_fw); 2555 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2556 1); 2557 req->lane_num = lane_num; 2558 2559 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2560 if (ret) { 2561 dev_err(&hdev->pdev->dev, 2562 "mac speed/duplex config cmd failed %d.\n", ret); 2563 return ret; 2564 } 2565 2566 return 0; 2567 } 2568 2569 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num) 2570 { 2571 struct hclge_mac *mac = &hdev->hw.mac; 2572 int ret; 2573 2574 duplex = hclge_check_speed_dup(duplex, speed); 2575 if (!mac->support_autoneg && mac->speed == speed && 2576 mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0)) 2577 return 0; 2578 2579 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num); 2580 if (ret) 2581 return ret; 2582 2583 hdev->hw.mac.speed = speed; 2584 hdev->hw.mac.duplex = duplex; 2585 if (!lane_num) 2586 hdev->hw.mac.lane_num = lane_num; 2587 2588 return 0; 2589 } 2590 2591 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2592 u8 duplex, u8 lane_num) 2593 { 2594 struct hclge_vport *vport = hclge_get_vport(handle); 2595 struct hclge_dev *hdev = vport->back; 2596 2597 return hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num); 2598 } 2599 2600 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2601 { 2602 struct hclge_config_auto_neg_cmd *req; 2603 struct hclge_desc desc; 2604 u32 flag = 0; 2605 int ret; 2606 2607 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2608 2609 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2610 if (enable) 2611 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U); 2612 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2613 2614 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2615 if (ret) 2616 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2617 ret); 2618 2619 return ret; 2620 } 2621 2622 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2623 { 2624 struct hclge_vport *vport = hclge_get_vport(handle); 2625 struct hclge_dev *hdev = vport->back; 2626 2627 if (!hdev->hw.mac.support_autoneg) { 2628 if (enable) { 2629 dev_err(&hdev->pdev->dev, 2630 "autoneg is not supported by current port\n"); 2631 return -EOPNOTSUPP; 2632 } else { 2633 return 0; 2634 } 2635 } 2636 2637 return hclge_set_autoneg_en(hdev, enable); 2638 } 2639 2640 static int hclge_get_autoneg(struct hnae3_handle *handle) 2641 { 2642 struct hclge_vport *vport = hclge_get_vport(handle); 2643 struct hclge_dev *hdev = vport->back; 2644 struct phy_device *phydev = hdev->hw.mac.phydev; 2645 2646 if (phydev) 2647 return phydev->autoneg; 2648 2649 return hdev->hw.mac.autoneg; 2650 } 2651 2652 static int hclge_restart_autoneg(struct hnae3_handle *handle) 2653 { 2654 struct hclge_vport *vport = hclge_get_vport(handle); 2655 struct hclge_dev *hdev = vport->back; 2656 int ret; 2657 2658 dev_dbg(&hdev->pdev->dev, "restart autoneg\n"); 2659 2660 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2661 if (ret) 2662 return ret; 2663 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2664 } 2665 2666 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt) 2667 { 2668 struct hclge_vport *vport = hclge_get_vport(handle); 2669 struct hclge_dev *hdev = vport->back; 2670 2671 if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) 2672 return hclge_set_autoneg_en(hdev, !halt); 2673 2674 return 0; 2675 } 2676 2677 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev, 2678 struct hclge_desc *desc, u32 desc_len) 2679 { 2680 u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2; 2681 u32 desc_index = 0; 2682 u32 data_index = 0; 2683 u32 i; 2684 2685 for (i = 0; i < lane_size; i++) { 2686 if (data_index >= HCLGE_DESC_DATA_LEN) { 2687 desc_index++; 2688 data_index = 0; 2689 } 2690 2691 if (desc_index >= desc_len) 2692 return; 2693 2694 hdev->fec_stats.per_lanes[i] += 2695 le32_to_cpu(desc[desc_index].data[data_index]); 2696 data_index++; 2697 } 2698 } 2699 2700 static void hclge_parse_fec_stats(struct hclge_dev *hdev, 2701 struct hclge_desc *desc, u32 desc_len) 2702 { 2703 struct hclge_query_fec_stats_cmd *req; 2704 2705 req = (struct hclge_query_fec_stats_cmd *)desc[0].data; 2706 2707 hdev->fec_stats.base_r_lane_num = req->base_r_lane_num; 2708 hdev->fec_stats.rs_corr_blocks += 2709 le32_to_cpu(req->rs_fec_corr_blocks); 2710 hdev->fec_stats.rs_uncorr_blocks += 2711 le32_to_cpu(req->rs_fec_uncorr_blocks); 2712 hdev->fec_stats.rs_error_blocks += 2713 le32_to_cpu(req->rs_fec_error_blocks); 2714 hdev->fec_stats.base_r_corr_blocks += 2715 le32_to_cpu(req->base_r_fec_corr_blocks); 2716 hdev->fec_stats.base_r_uncorr_blocks += 2717 le32_to_cpu(req->base_r_fec_uncorr_blocks); 2718 2719 hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1); 2720 } 2721 2722 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev) 2723 { 2724 struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM]; 2725 int ret; 2726 u32 i; 2727 2728 for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) { 2729 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS, 2730 true); 2731 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1)) 2732 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2733 } 2734 2735 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM); 2736 if (ret) 2737 return ret; 2738 2739 hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM); 2740 2741 return 0; 2742 } 2743 2744 static void hclge_update_fec_stats(struct hclge_dev *hdev) 2745 { 2746 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2747 int ret; 2748 2749 if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || 2750 test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state)) 2751 return; 2752 2753 ret = hclge_update_fec_stats_hw(hdev); 2754 if (ret) 2755 dev_err(&hdev->pdev->dev, 2756 "failed to update fec stats, ret = %d\n", ret); 2757 2758 clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state); 2759 } 2760 2761 static void hclge_get_fec_stats_total(struct hclge_dev *hdev, 2762 struct ethtool_fec_stats *fec_stats) 2763 { 2764 fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks; 2765 fec_stats->uncorrectable_blocks.total = 2766 hdev->fec_stats.rs_uncorr_blocks; 2767 } 2768 2769 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev, 2770 struct ethtool_fec_stats *fec_stats) 2771 { 2772 u32 i; 2773 2774 if (hdev->fec_stats.base_r_lane_num == 0 || 2775 hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) { 2776 dev_err(&hdev->pdev->dev, 2777 "fec stats lane number(%llu) is invalid\n", 2778 hdev->fec_stats.base_r_lane_num); 2779 return; 2780 } 2781 2782 for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) { 2783 fec_stats->corrected_blocks.lanes[i] = 2784 hdev->fec_stats.base_r_corr_per_lanes[i]; 2785 fec_stats->uncorrectable_blocks.lanes[i] = 2786 hdev->fec_stats.base_r_uncorr_per_lanes[i]; 2787 } 2788 } 2789 2790 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev, 2791 struct ethtool_fec_stats *fec_stats) 2792 { 2793 u32 fec_mode = hdev->hw.mac.fec_mode; 2794 2795 switch (fec_mode) { 2796 case BIT(HNAE3_FEC_RS): 2797 case BIT(HNAE3_FEC_LLRS): 2798 hclge_get_fec_stats_total(hdev, fec_stats); 2799 break; 2800 case BIT(HNAE3_FEC_BASER): 2801 hclge_get_fec_stats_lanes(hdev, fec_stats); 2802 break; 2803 default: 2804 dev_err(&hdev->pdev->dev, 2805 "fec stats is not supported by current fec mode(0x%x)\n", 2806 fec_mode); 2807 break; 2808 } 2809 } 2810 2811 static void hclge_get_fec_stats(struct hnae3_handle *handle, 2812 struct ethtool_fec_stats *fec_stats) 2813 { 2814 struct hclge_vport *vport = hclge_get_vport(handle); 2815 struct hclge_dev *hdev = vport->back; 2816 u32 fec_mode = hdev->hw.mac.fec_mode; 2817 2818 if (fec_mode == BIT(HNAE3_FEC_NONE) || 2819 fec_mode == BIT(HNAE3_FEC_AUTO) || 2820 fec_mode == BIT(HNAE3_FEC_USER_DEF)) 2821 return; 2822 2823 hclge_update_fec_stats(hdev); 2824 2825 hclge_comm_get_fec_stats(hdev, fec_stats); 2826 } 2827 2828 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode) 2829 { 2830 struct hclge_config_fec_cmd *req; 2831 struct hclge_desc desc; 2832 int ret; 2833 2834 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false); 2835 2836 req = (struct hclge_config_fec_cmd *)desc.data; 2837 if (fec_mode & BIT(HNAE3_FEC_AUTO)) 2838 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1); 2839 if (fec_mode & BIT(HNAE3_FEC_RS)) 2840 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2841 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS); 2842 if (fec_mode & BIT(HNAE3_FEC_LLRS)) 2843 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2844 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS); 2845 if (fec_mode & BIT(HNAE3_FEC_BASER)) 2846 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2847 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER); 2848 2849 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2850 if (ret) 2851 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret); 2852 2853 return ret; 2854 } 2855 2856 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode) 2857 { 2858 struct hclge_vport *vport = hclge_get_vport(handle); 2859 struct hclge_dev *hdev = vport->back; 2860 struct hclge_mac *mac = &hdev->hw.mac; 2861 int ret; 2862 2863 if (fec_mode && !(mac->fec_ability & fec_mode)) { 2864 dev_err(&hdev->pdev->dev, "unsupported fec mode\n"); 2865 return -EINVAL; 2866 } 2867 2868 ret = hclge_set_fec_hw(hdev, fec_mode); 2869 if (ret) 2870 return ret; 2871 2872 mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF); 2873 return 0; 2874 } 2875 2876 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability, 2877 u8 *fec_mode) 2878 { 2879 struct hclge_vport *vport = hclge_get_vport(handle); 2880 struct hclge_dev *hdev = vport->back; 2881 struct hclge_mac *mac = &hdev->hw.mac; 2882 2883 if (fec_ability) 2884 *fec_ability = mac->fec_ability; 2885 if (fec_mode) 2886 *fec_mode = mac->fec_mode; 2887 } 2888 2889 static int hclge_mac_init(struct hclge_dev *hdev) 2890 { 2891 struct hclge_mac *mac = &hdev->hw.mac; 2892 int ret; 2893 2894 hdev->support_sfp_query = true; 2895 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 2896 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed, 2897 hdev->hw.mac.duplex, hdev->hw.mac.lane_num); 2898 if (ret) 2899 return ret; 2900 2901 if (hdev->hw.mac.support_autoneg) { 2902 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg); 2903 if (ret) 2904 return ret; 2905 } 2906 2907 mac->link = 0; 2908 2909 if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { 2910 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode); 2911 if (ret) 2912 return ret; 2913 } 2914 2915 ret = hclge_set_mac_mtu(hdev, hdev->mps); 2916 if (ret) { 2917 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret); 2918 return ret; 2919 } 2920 2921 ret = hclge_set_default_loopback(hdev); 2922 if (ret) 2923 return ret; 2924 2925 ret = hclge_buffer_alloc(hdev); 2926 if (ret) 2927 dev_err(&hdev->pdev->dev, 2928 "allocate buffer fail, ret=%d\n", ret); 2929 2930 return ret; 2931 } 2932 2933 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 2934 { 2935 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2936 !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) { 2937 hdev->last_mbx_scheduled = jiffies; 2938 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2939 } 2940 } 2941 2942 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 2943 { 2944 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2945 test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) && 2946 !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) { 2947 hdev->last_rst_scheduled = jiffies; 2948 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2949 } 2950 } 2951 2952 static void hclge_errhand_task_schedule(struct hclge_dev *hdev) 2953 { 2954 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2955 !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 2956 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2957 } 2958 2959 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time) 2960 { 2961 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2962 !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 2963 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time); 2964 } 2965 2966 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status) 2967 { 2968 struct hclge_link_status_cmd *req; 2969 struct hclge_desc desc; 2970 int ret; 2971 2972 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 2973 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2974 if (ret) { 2975 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 2976 ret); 2977 return ret; 2978 } 2979 2980 req = (struct hclge_link_status_cmd *)desc.data; 2981 *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ? 2982 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 2983 2984 return 0; 2985 } 2986 2987 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status) 2988 { 2989 struct phy_device *phydev = hdev->hw.mac.phydev; 2990 2991 *link_status = HCLGE_LINK_STATUS_DOWN; 2992 2993 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) 2994 return 0; 2995 2996 if (phydev && (phydev->state != PHY_RUNNING || !phydev->link)) 2997 return 0; 2998 2999 return hclge_get_mac_link_status(hdev, link_status); 3000 } 3001 3002 static void hclge_push_link_status(struct hclge_dev *hdev) 3003 { 3004 struct hclge_vport *vport; 3005 int ret; 3006 u16 i; 3007 3008 for (i = 0; i < pci_num_vf(hdev->pdev); i++) { 3009 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 3010 3011 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) || 3012 vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO) 3013 continue; 3014 3015 ret = hclge_push_vf_link_status(vport); 3016 if (ret) { 3017 dev_err(&hdev->pdev->dev, 3018 "failed to push link status to vf%u, ret = %d\n", 3019 i, ret); 3020 } 3021 } 3022 } 3023 3024 static void hclge_update_link_status(struct hclge_dev *hdev) 3025 { 3026 struct hnae3_handle *rhandle = &hdev->vport[0].roce; 3027 struct hnae3_handle *handle = &hdev->vport[0].nic; 3028 struct hnae3_client *rclient = hdev->roce_client; 3029 struct hnae3_client *client = hdev->nic_client; 3030 int state; 3031 int ret; 3032 3033 if (!client) 3034 return; 3035 3036 if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state)) 3037 return; 3038 3039 ret = hclge_get_mac_phy_link(hdev, &state); 3040 if (ret) { 3041 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3042 return; 3043 } 3044 3045 if (state != hdev->hw.mac.link) { 3046 hdev->hw.mac.link = state; 3047 if (state == HCLGE_LINK_STATUS_UP) 3048 hclge_update_port_info(hdev); 3049 3050 client->ops->link_status_change(handle, state); 3051 hclge_config_mac_tnl_int(hdev, state); 3052 if (rclient && rclient->ops->link_status_change) 3053 rclient->ops->link_status_change(rhandle, state); 3054 3055 hclge_push_link_status(hdev); 3056 } 3057 3058 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3059 } 3060 3061 static void hclge_update_speed_advertising(struct hclge_mac *mac) 3062 { 3063 u32 speed_ability; 3064 3065 if (hclge_get_speed_bit(mac->speed, &speed_ability)) 3066 return; 3067 3068 switch (mac->module_type) { 3069 case HNAE3_MODULE_TYPE_FIBRE_LR: 3070 hclge_convert_setting_lr(speed_ability, mac->advertising); 3071 break; 3072 case HNAE3_MODULE_TYPE_FIBRE_SR: 3073 case HNAE3_MODULE_TYPE_AOC: 3074 hclge_convert_setting_sr(speed_ability, mac->advertising); 3075 break; 3076 case HNAE3_MODULE_TYPE_CR: 3077 hclge_convert_setting_cr(speed_ability, mac->advertising); 3078 break; 3079 case HNAE3_MODULE_TYPE_KR: 3080 hclge_convert_setting_kr(speed_ability, mac->advertising); 3081 break; 3082 default: 3083 break; 3084 } 3085 } 3086 3087 static void hclge_update_fec_advertising(struct hclge_mac *mac) 3088 { 3089 if (mac->fec_mode & BIT(HNAE3_FEC_RS)) 3090 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 3091 mac->advertising); 3092 else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS)) 3093 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 3094 mac->advertising); 3095 else if (mac->fec_mode & BIT(HNAE3_FEC_BASER)) 3096 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 3097 mac->advertising); 3098 else 3099 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 3100 mac->advertising); 3101 } 3102 3103 static void hclge_update_pause_advertising(struct hclge_dev *hdev) 3104 { 3105 struct hclge_mac *mac = &hdev->hw.mac; 3106 bool rx_en, tx_en; 3107 3108 switch (hdev->fc_mode_last_time) { 3109 case HCLGE_FC_RX_PAUSE: 3110 rx_en = true; 3111 tx_en = false; 3112 break; 3113 case HCLGE_FC_TX_PAUSE: 3114 rx_en = false; 3115 tx_en = true; 3116 break; 3117 case HCLGE_FC_FULL: 3118 rx_en = true; 3119 tx_en = true; 3120 break; 3121 default: 3122 rx_en = false; 3123 tx_en = false; 3124 break; 3125 } 3126 3127 linkmode_set_pause(mac->advertising, tx_en, rx_en); 3128 } 3129 3130 static void hclge_update_advertising(struct hclge_dev *hdev) 3131 { 3132 struct hclge_mac *mac = &hdev->hw.mac; 3133 3134 linkmode_zero(mac->advertising); 3135 hclge_update_speed_advertising(mac); 3136 hclge_update_fec_advertising(mac); 3137 hclge_update_pause_advertising(hdev); 3138 } 3139 3140 static void hclge_update_port_capability(struct hclge_dev *hdev, 3141 struct hclge_mac *mac) 3142 { 3143 if (hnae3_dev_fec_supported(hdev)) 3144 hclge_convert_setting_fec(mac); 3145 3146 /* firmware can not identify back plane type, the media type 3147 * read from configuration can help deal it 3148 */ 3149 if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE && 3150 mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN) 3151 mac->module_type = HNAE3_MODULE_TYPE_KR; 3152 else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3153 mac->module_type = HNAE3_MODULE_TYPE_TP; 3154 3155 if (mac->support_autoneg) { 3156 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported); 3157 linkmode_copy(mac->advertising, mac->supported); 3158 } else { 3159 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3160 mac->supported); 3161 hclge_update_advertising(hdev); 3162 } 3163 } 3164 3165 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed) 3166 { 3167 struct hclge_sfp_info_cmd *resp; 3168 struct hclge_desc desc; 3169 int ret; 3170 3171 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3172 resp = (struct hclge_sfp_info_cmd *)desc.data; 3173 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3174 if (ret == -EOPNOTSUPP) { 3175 dev_warn(&hdev->pdev->dev, 3176 "IMP do not support get SFP speed %d\n", ret); 3177 return ret; 3178 } else if (ret) { 3179 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret); 3180 return ret; 3181 } 3182 3183 *speed = le32_to_cpu(resp->speed); 3184 3185 return 0; 3186 } 3187 3188 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac) 3189 { 3190 struct hclge_sfp_info_cmd *resp; 3191 struct hclge_desc desc; 3192 int ret; 3193 3194 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3195 resp = (struct hclge_sfp_info_cmd *)desc.data; 3196 3197 resp->query_type = QUERY_ACTIVE_SPEED; 3198 3199 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3200 if (ret == -EOPNOTSUPP) { 3201 dev_warn(&hdev->pdev->dev, 3202 "IMP does not support get SFP info %d\n", ret); 3203 return ret; 3204 } else if (ret) { 3205 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret); 3206 return ret; 3207 } 3208 3209 /* In some case, mac speed get from IMP may be 0, it shouldn't be 3210 * set to mac->speed. 3211 */ 3212 if (!le32_to_cpu(resp->speed)) 3213 return 0; 3214 3215 mac->speed = le32_to_cpu(resp->speed); 3216 /* if resp->speed_ability is 0, it means it's an old version 3217 * firmware, do not update these params 3218 */ 3219 if (resp->speed_ability) { 3220 mac->module_type = le32_to_cpu(resp->module_type); 3221 mac->speed_ability = le32_to_cpu(resp->speed_ability); 3222 mac->autoneg = resp->autoneg; 3223 mac->support_autoneg = resp->autoneg_ability; 3224 mac->speed_type = QUERY_ACTIVE_SPEED; 3225 mac->lane_num = resp->lane_num; 3226 if (!resp->active_fec) 3227 mac->fec_mode = 0; 3228 else 3229 mac->fec_mode = BIT(resp->active_fec); 3230 mac->fec_ability = resp->fec_ability; 3231 } else { 3232 mac->speed_type = QUERY_SFP_SPEED; 3233 } 3234 3235 return 0; 3236 } 3237 3238 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle, 3239 struct ethtool_link_ksettings *cmd) 3240 { 3241 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3242 struct hclge_vport *vport = hclge_get_vport(handle); 3243 struct hclge_phy_link_ksetting_0_cmd *req0; 3244 struct hclge_phy_link_ksetting_1_cmd *req1; 3245 u32 supported, advertising, lp_advertising; 3246 struct hclge_dev *hdev = vport->back; 3247 int ret; 3248 3249 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3250 true); 3251 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3252 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3253 true); 3254 3255 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3256 if (ret) { 3257 dev_err(&hdev->pdev->dev, 3258 "failed to get phy link ksetting, ret = %d.\n", ret); 3259 return ret; 3260 } 3261 3262 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3263 cmd->base.autoneg = req0->autoneg; 3264 cmd->base.speed = le32_to_cpu(req0->speed); 3265 cmd->base.duplex = req0->duplex; 3266 cmd->base.port = req0->port; 3267 cmd->base.transceiver = req0->transceiver; 3268 cmd->base.phy_address = req0->phy_address; 3269 cmd->base.eth_tp_mdix = req0->eth_tp_mdix; 3270 cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl; 3271 supported = le32_to_cpu(req0->supported); 3272 advertising = le32_to_cpu(req0->advertising); 3273 lp_advertising = le32_to_cpu(req0->lp_advertising); 3274 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3275 supported); 3276 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3277 advertising); 3278 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 3279 lp_advertising); 3280 3281 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3282 cmd->base.master_slave_cfg = req1->master_slave_cfg; 3283 cmd->base.master_slave_state = req1->master_slave_state; 3284 3285 return 0; 3286 } 3287 3288 static int 3289 hclge_set_phy_link_ksettings(struct hnae3_handle *handle, 3290 const struct ethtool_link_ksettings *cmd) 3291 { 3292 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3293 struct hclge_vport *vport = hclge_get_vport(handle); 3294 struct hclge_phy_link_ksetting_0_cmd *req0; 3295 struct hclge_phy_link_ksetting_1_cmd *req1; 3296 struct hclge_dev *hdev = vport->back; 3297 u32 advertising; 3298 int ret; 3299 3300 if (cmd->base.autoneg == AUTONEG_DISABLE && 3301 ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) || 3302 (cmd->base.duplex != DUPLEX_HALF && 3303 cmd->base.duplex != DUPLEX_FULL))) 3304 return -EINVAL; 3305 3306 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3307 false); 3308 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3309 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3310 false); 3311 3312 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3313 req0->autoneg = cmd->base.autoneg; 3314 req0->speed = cpu_to_le32(cmd->base.speed); 3315 req0->duplex = cmd->base.duplex; 3316 ethtool_convert_link_mode_to_legacy_u32(&advertising, 3317 cmd->link_modes.advertising); 3318 req0->advertising = cpu_to_le32(advertising); 3319 req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; 3320 3321 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3322 req1->master_slave_cfg = cmd->base.master_slave_cfg; 3323 3324 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3325 if (ret) { 3326 dev_err(&hdev->pdev->dev, 3327 "failed to set phy link ksettings, ret = %d.\n", ret); 3328 return ret; 3329 } 3330 3331 hdev->hw.mac.autoneg = cmd->base.autoneg; 3332 hdev->hw.mac.speed = cmd->base.speed; 3333 hdev->hw.mac.duplex = cmd->base.duplex; 3334 linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising); 3335 3336 return 0; 3337 } 3338 3339 static int hclge_update_tp_port_info(struct hclge_dev *hdev) 3340 { 3341 struct ethtool_link_ksettings cmd; 3342 int ret; 3343 3344 if (!hnae3_dev_phy_imp_supported(hdev)) 3345 return 0; 3346 3347 ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd); 3348 if (ret) 3349 return ret; 3350 3351 hdev->hw.mac.autoneg = cmd.base.autoneg; 3352 hdev->hw.mac.speed = cmd.base.speed; 3353 hdev->hw.mac.duplex = cmd.base.duplex; 3354 linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising); 3355 3356 return 0; 3357 } 3358 3359 static int hclge_tp_port_init(struct hclge_dev *hdev) 3360 { 3361 struct ethtool_link_ksettings cmd; 3362 3363 if (!hnae3_dev_phy_imp_supported(hdev)) 3364 return 0; 3365 3366 cmd.base.autoneg = hdev->hw.mac.autoneg; 3367 cmd.base.speed = hdev->hw.mac.speed; 3368 cmd.base.duplex = hdev->hw.mac.duplex; 3369 linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising); 3370 3371 return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd); 3372 } 3373 3374 static int hclge_update_port_info(struct hclge_dev *hdev) 3375 { 3376 struct hclge_mac *mac = &hdev->hw.mac; 3377 int speed; 3378 int ret; 3379 3380 /* get the port info from SFP cmd if not copper port */ 3381 if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3382 return hclge_update_tp_port_info(hdev); 3383 3384 /* if IMP does not support get SFP/qSFP info, return directly */ 3385 if (!hdev->support_sfp_query) 3386 return 0; 3387 3388 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3389 speed = mac->speed; 3390 ret = hclge_get_sfp_info(hdev, mac); 3391 } else { 3392 speed = HCLGE_MAC_SPEED_UNKNOWN; 3393 ret = hclge_get_sfp_speed(hdev, &speed); 3394 } 3395 3396 if (ret == -EOPNOTSUPP) { 3397 hdev->support_sfp_query = false; 3398 return ret; 3399 } else if (ret) { 3400 return ret; 3401 } 3402 3403 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3404 if (mac->speed_type == QUERY_ACTIVE_SPEED) { 3405 hclge_update_port_capability(hdev, mac); 3406 if (mac->speed != speed) 3407 (void)hclge_tm_port_shaper_cfg(hdev); 3408 return 0; 3409 } 3410 return hclge_cfg_mac_speed_dup(hdev, mac->speed, 3411 HCLGE_MAC_FULL, mac->lane_num); 3412 } else { 3413 if (speed == HCLGE_MAC_SPEED_UNKNOWN) 3414 return 0; /* do nothing if no SFP */ 3415 3416 /* must config full duplex for SFP */ 3417 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0); 3418 } 3419 } 3420 3421 static int hclge_get_status(struct hnae3_handle *handle) 3422 { 3423 struct hclge_vport *vport = hclge_get_vport(handle); 3424 struct hclge_dev *hdev = vport->back; 3425 3426 hclge_update_link_status(hdev); 3427 3428 return hdev->hw.mac.link; 3429 } 3430 3431 static struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf) 3432 { 3433 if (!pci_num_vf(hdev->pdev)) { 3434 dev_err(&hdev->pdev->dev, 3435 "SRIOV is disabled, can not get vport(%d) info.\n", vf); 3436 return NULL; 3437 } 3438 3439 if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) { 3440 dev_err(&hdev->pdev->dev, 3441 "vf id(%d) is out of range(0 <= vfid < %d)\n", 3442 vf, pci_num_vf(hdev->pdev)); 3443 return NULL; 3444 } 3445 3446 /* VF start from 1 in vport */ 3447 vf += HCLGE_VF_VPORT_START_NUM; 3448 return &hdev->vport[vf]; 3449 } 3450 3451 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf, 3452 struct ifla_vf_info *ivf) 3453 { 3454 struct hclge_vport *vport = hclge_get_vport(handle); 3455 struct hclge_dev *hdev = vport->back; 3456 3457 vport = hclge_get_vf_vport(hdev, vf); 3458 if (!vport) 3459 return -EINVAL; 3460 3461 ivf->vf = vf; 3462 ivf->linkstate = vport->vf_info.link_state; 3463 ivf->spoofchk = vport->vf_info.spoofchk; 3464 ivf->trusted = vport->vf_info.trusted; 3465 ivf->min_tx_rate = 0; 3466 ivf->max_tx_rate = vport->vf_info.max_tx_rate; 3467 ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag; 3468 ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto); 3469 ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos; 3470 ether_addr_copy(ivf->mac, vport->vf_info.mac); 3471 3472 return 0; 3473 } 3474 3475 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, 3476 int link_state) 3477 { 3478 struct hclge_vport *vport = hclge_get_vport(handle); 3479 struct hclge_dev *hdev = vport->back; 3480 int link_state_old; 3481 int ret; 3482 3483 vport = hclge_get_vf_vport(hdev, vf); 3484 if (!vport) 3485 return -EINVAL; 3486 3487 link_state_old = vport->vf_info.link_state; 3488 vport->vf_info.link_state = link_state; 3489 3490 /* return success directly if the VF is unalive, VF will 3491 * query link state itself when it starts work. 3492 */ 3493 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3494 return 0; 3495 3496 ret = hclge_push_vf_link_status(vport); 3497 if (ret) { 3498 vport->vf_info.link_state = link_state_old; 3499 dev_err(&hdev->pdev->dev, 3500 "failed to push vf%d link status, ret = %d\n", vf, ret); 3501 } 3502 3503 return ret; 3504 } 3505 3506 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 3507 { 3508 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; 3509 3510 /* fetch the events from their corresponding regs */ 3511 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 3512 msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 3513 hw_err_src_reg = hclge_read_dev(&hdev->hw, 3514 HCLGE_RAS_PF_OTHER_INT_STS_REG); 3515 3516 /* Assumption: If by any chance reset and mailbox events are reported 3517 * together then we will only process reset event in this go and will 3518 * defer the processing of the mailbox events. Since, we would have not 3519 * cleared RX CMDQ event this time we would receive again another 3520 * interrupt from H/W just for the mailbox. 3521 * 3522 * check for vector0 reset event sources 3523 */ 3524 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { 3525 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); 3526 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); 3527 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3528 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3529 hdev->rst_stats.imp_rst_cnt++; 3530 return HCLGE_VECTOR0_EVENT_RST; 3531 } 3532 3533 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { 3534 dev_info(&hdev->pdev->dev, "global reset interrupt\n"); 3535 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3536 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 3537 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3538 hdev->rst_stats.global_rst_cnt++; 3539 return HCLGE_VECTOR0_EVENT_RST; 3540 } 3541 3542 /* check for vector0 msix event and hardware error event source */ 3543 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK || 3544 hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK) 3545 return HCLGE_VECTOR0_EVENT_ERR; 3546 3547 /* check for vector0 ptp event source */ 3548 if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) { 3549 *clearval = msix_src_reg; 3550 return HCLGE_VECTOR0_EVENT_PTP; 3551 } 3552 3553 /* check for vector0 mailbox(=CMDQ RX) event source */ 3554 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 3555 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 3556 *clearval = cmdq_src_reg; 3557 return HCLGE_VECTOR0_EVENT_MBX; 3558 } 3559 3560 /* print other vector0 event source */ 3561 dev_info(&hdev->pdev->dev, 3562 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n", 3563 cmdq_src_reg, hw_err_src_reg, msix_src_reg); 3564 3565 return HCLGE_VECTOR0_EVENT_OTHER; 3566 } 3567 3568 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 3569 u32 regclr) 3570 { 3571 #define HCLGE_IMP_RESET_DELAY 5 3572 3573 switch (event_type) { 3574 case HCLGE_VECTOR0_EVENT_PTP: 3575 case HCLGE_VECTOR0_EVENT_RST: 3576 if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B)) 3577 mdelay(HCLGE_IMP_RESET_DELAY); 3578 3579 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 3580 break; 3581 case HCLGE_VECTOR0_EVENT_MBX: 3582 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 3583 break; 3584 default: 3585 break; 3586 } 3587 } 3588 3589 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 3590 { 3591 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 3592 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 3593 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 3594 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 3595 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 3596 } 3597 3598 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 3599 { 3600 writel(enable ? 1 : 0, vector->addr); 3601 } 3602 3603 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 3604 { 3605 struct hclge_dev *hdev = data; 3606 unsigned long flags; 3607 u32 clearval = 0; 3608 u32 event_cause; 3609 3610 hclge_enable_vector(&hdev->misc_vector, false); 3611 event_cause = hclge_check_event_cause(hdev, &clearval); 3612 3613 /* vector 0 interrupt is shared with reset and mailbox source events. */ 3614 switch (event_cause) { 3615 case HCLGE_VECTOR0_EVENT_ERR: 3616 hclge_errhand_task_schedule(hdev); 3617 break; 3618 case HCLGE_VECTOR0_EVENT_RST: 3619 hclge_reset_task_schedule(hdev); 3620 break; 3621 case HCLGE_VECTOR0_EVENT_PTP: 3622 spin_lock_irqsave(&hdev->ptp->lock, flags); 3623 hclge_ptp_clean_tx_hwts(hdev); 3624 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 3625 break; 3626 case HCLGE_VECTOR0_EVENT_MBX: 3627 /* If we are here then, 3628 * 1. Either we are not handling any mbx task and we are not 3629 * scheduled as well 3630 * OR 3631 * 2. We could be handling a mbx task but nothing more is 3632 * scheduled. 3633 * In both cases, we should schedule mbx task as there are more 3634 * mbx messages reported by this interrupt. 3635 */ 3636 hclge_mbx_task_schedule(hdev); 3637 break; 3638 default: 3639 dev_warn(&hdev->pdev->dev, 3640 "received unknown or unhandled event of vector0\n"); 3641 break; 3642 } 3643 3644 hclge_clear_event_cause(hdev, event_cause, clearval); 3645 3646 /* Enable interrupt if it is not caused by reset event or error event */ 3647 if (event_cause == HCLGE_VECTOR0_EVENT_PTP || 3648 event_cause == HCLGE_VECTOR0_EVENT_MBX || 3649 event_cause == HCLGE_VECTOR0_EVENT_OTHER) 3650 hclge_enable_vector(&hdev->misc_vector, true); 3651 3652 return IRQ_HANDLED; 3653 } 3654 3655 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 3656 { 3657 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 3658 dev_warn(&hdev->pdev->dev, 3659 "vector(vector_id %d) has been freed.\n", vector_id); 3660 return; 3661 } 3662 3663 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 3664 hdev->num_msi_left += 1; 3665 hdev->num_msi_used -= 1; 3666 } 3667 3668 static void hclge_get_misc_vector(struct hclge_dev *hdev) 3669 { 3670 struct hclge_misc_vector *vector = &hdev->misc_vector; 3671 3672 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 3673 3674 vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 3675 hdev->vector_status[0] = 0; 3676 3677 hdev->num_msi_left -= 1; 3678 hdev->num_msi_used += 1; 3679 } 3680 3681 static int hclge_misc_irq_init(struct hclge_dev *hdev) 3682 { 3683 int ret; 3684 3685 hclge_get_misc_vector(hdev); 3686 3687 /* this would be explicitly freed in the end */ 3688 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 3689 HCLGE_NAME, pci_name(hdev->pdev)); 3690 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 3691 0, hdev->misc_vector.name, hdev); 3692 if (ret) { 3693 hclge_free_vector(hdev, 0); 3694 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 3695 hdev->misc_vector.vector_irq); 3696 } 3697 3698 return ret; 3699 } 3700 3701 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 3702 { 3703 free_irq(hdev->misc_vector.vector_irq, hdev); 3704 hclge_free_vector(hdev, 0); 3705 } 3706 3707 int hclge_notify_client(struct hclge_dev *hdev, 3708 enum hnae3_reset_notify_type type) 3709 { 3710 struct hnae3_handle *handle = &hdev->vport[0].nic; 3711 struct hnae3_client *client = hdev->nic_client; 3712 int ret; 3713 3714 if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client) 3715 return 0; 3716 3717 if (!client->ops->reset_notify) 3718 return -EOPNOTSUPP; 3719 3720 ret = client->ops->reset_notify(handle, type); 3721 if (ret) 3722 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 3723 type, ret); 3724 3725 return ret; 3726 } 3727 3728 static int hclge_notify_roce_client(struct hclge_dev *hdev, 3729 enum hnae3_reset_notify_type type) 3730 { 3731 struct hnae3_handle *handle = &hdev->vport[0].roce; 3732 struct hnae3_client *client = hdev->roce_client; 3733 int ret; 3734 3735 if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client) 3736 return 0; 3737 3738 if (!client->ops->reset_notify) 3739 return -EOPNOTSUPP; 3740 3741 ret = client->ops->reset_notify(handle, type); 3742 if (ret) 3743 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 3744 type, ret); 3745 3746 return ret; 3747 } 3748 3749 static int hclge_reset_wait(struct hclge_dev *hdev) 3750 { 3751 #define HCLGE_RESET_WATI_MS 100 3752 #define HCLGE_RESET_WAIT_CNT 350 3753 3754 u32 val, reg, reg_bit; 3755 u32 cnt = 0; 3756 3757 switch (hdev->reset_type) { 3758 case HNAE3_IMP_RESET: 3759 reg = HCLGE_GLOBAL_RESET_REG; 3760 reg_bit = HCLGE_IMP_RESET_BIT; 3761 break; 3762 case HNAE3_GLOBAL_RESET: 3763 reg = HCLGE_GLOBAL_RESET_REG; 3764 reg_bit = HCLGE_GLOBAL_RESET_BIT; 3765 break; 3766 case HNAE3_FUNC_RESET: 3767 reg = HCLGE_FUN_RST_ING; 3768 reg_bit = HCLGE_FUN_RST_ING_B; 3769 break; 3770 default: 3771 dev_err(&hdev->pdev->dev, 3772 "Wait for unsupported reset type: %d\n", 3773 hdev->reset_type); 3774 return -EINVAL; 3775 } 3776 3777 val = hclge_read_dev(&hdev->hw, reg); 3778 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 3779 msleep(HCLGE_RESET_WATI_MS); 3780 val = hclge_read_dev(&hdev->hw, reg); 3781 cnt++; 3782 } 3783 3784 if (cnt >= HCLGE_RESET_WAIT_CNT) { 3785 dev_warn(&hdev->pdev->dev, 3786 "Wait for reset timeout: %d\n", hdev->reset_type); 3787 return -EBUSY; 3788 } 3789 3790 return 0; 3791 } 3792 3793 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset) 3794 { 3795 struct hclge_vf_rst_cmd *req; 3796 struct hclge_desc desc; 3797 3798 req = (struct hclge_vf_rst_cmd *)desc.data; 3799 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false); 3800 req->dest_vfid = func_id; 3801 3802 if (reset) 3803 req->vf_rst = 0x1; 3804 3805 return hclge_cmd_send(&hdev->hw, &desc, 1); 3806 } 3807 3808 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset) 3809 { 3810 int i; 3811 3812 for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) { 3813 struct hclge_vport *vport = &hdev->vport[i]; 3814 int ret; 3815 3816 /* Send cmd to set/clear VF's FUNC_RST_ING */ 3817 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset); 3818 if (ret) { 3819 dev_err(&hdev->pdev->dev, 3820 "set vf(%u) rst failed %d!\n", 3821 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3822 ret); 3823 return ret; 3824 } 3825 3826 if (!reset || 3827 !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state)) 3828 continue; 3829 3830 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) && 3831 hdev->reset_type == HNAE3_FUNC_RESET) { 3832 set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET, 3833 &vport->need_notify); 3834 continue; 3835 } 3836 3837 /* Inform VF to process the reset. 3838 * hclge_inform_reset_assert_to_vf may fail if VF 3839 * driver is not loaded. 3840 */ 3841 ret = hclge_inform_reset_assert_to_vf(vport); 3842 if (ret) 3843 dev_warn(&hdev->pdev->dev, 3844 "inform reset to vf(%u) failed %d!\n", 3845 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3846 ret); 3847 } 3848 3849 return 0; 3850 } 3851 3852 static void hclge_mailbox_service_task(struct hclge_dev *hdev) 3853 { 3854 if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) || 3855 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) || 3856 test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 3857 return; 3858 3859 if (time_is_before_jiffies(hdev->last_mbx_scheduled + 3860 HCLGE_MBX_SCHED_TIMEOUT)) 3861 dev_warn(&hdev->pdev->dev, 3862 "mbx service task is scheduled after %ums on cpu%u!\n", 3863 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled), 3864 smp_processor_id()); 3865 3866 hclge_mbx_handler(hdev); 3867 3868 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 3869 } 3870 3871 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev) 3872 { 3873 struct hclge_pf_rst_sync_cmd *req; 3874 struct hclge_desc desc; 3875 int cnt = 0; 3876 int ret; 3877 3878 req = (struct hclge_pf_rst_sync_cmd *)desc.data; 3879 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true); 3880 3881 do { 3882 /* vf need to down netdev by mbx during PF or FLR reset */ 3883 hclge_mailbox_service_task(hdev); 3884 3885 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3886 /* for compatible with old firmware, wait 3887 * 100 ms for VF to stop IO 3888 */ 3889 if (ret == -EOPNOTSUPP) { 3890 msleep(HCLGE_RESET_SYNC_TIME); 3891 return; 3892 } else if (ret) { 3893 dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n", 3894 ret); 3895 return; 3896 } else if (req->all_vf_ready) { 3897 return; 3898 } 3899 msleep(HCLGE_PF_RESET_SYNC_TIME); 3900 hclge_comm_cmd_reuse_desc(&desc, true); 3901 } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT); 3902 3903 dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n"); 3904 } 3905 3906 void hclge_report_hw_error(struct hclge_dev *hdev, 3907 enum hnae3_hw_error_type type) 3908 { 3909 struct hnae3_client *client = hdev->nic_client; 3910 3911 if (!client || !client->ops->process_hw_error || 3912 !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) 3913 return; 3914 3915 client->ops->process_hw_error(&hdev->vport[0].nic, type); 3916 } 3917 3918 static void hclge_handle_imp_error(struct hclge_dev *hdev) 3919 { 3920 u32 reg_val; 3921 3922 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 3923 if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { 3924 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); 3925 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); 3926 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 3927 } 3928 3929 if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { 3930 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); 3931 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); 3932 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 3933 } 3934 } 3935 3936 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 3937 { 3938 struct hclge_desc desc; 3939 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 3940 int ret; 3941 3942 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 3943 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 3944 req->fun_reset_vfid = func_id; 3945 3946 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3947 if (ret) 3948 dev_err(&hdev->pdev->dev, 3949 "send function reset cmd fail, status =%d\n", ret); 3950 3951 return ret; 3952 } 3953 3954 static void hclge_do_reset(struct hclge_dev *hdev) 3955 { 3956 struct hnae3_handle *handle = &hdev->vport[0].nic; 3957 struct pci_dev *pdev = hdev->pdev; 3958 u32 val; 3959 3960 if (hclge_get_hw_reset_stat(handle)) { 3961 dev_info(&pdev->dev, "hardware reset not finish\n"); 3962 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n", 3963 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING), 3964 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 3965 return; 3966 } 3967 3968 switch (hdev->reset_type) { 3969 case HNAE3_IMP_RESET: 3970 dev_info(&pdev->dev, "IMP reset requested\n"); 3971 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 3972 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1); 3973 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val); 3974 break; 3975 case HNAE3_GLOBAL_RESET: 3976 dev_info(&pdev->dev, "global reset requested\n"); 3977 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 3978 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 3979 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 3980 break; 3981 case HNAE3_FUNC_RESET: 3982 dev_info(&pdev->dev, "PF reset requested\n"); 3983 /* schedule again to check later */ 3984 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); 3985 hclge_reset_task_schedule(hdev); 3986 break; 3987 default: 3988 dev_warn(&pdev->dev, 3989 "unsupported reset type: %d\n", hdev->reset_type); 3990 break; 3991 } 3992 } 3993 3994 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 3995 unsigned long *addr) 3996 { 3997 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 3998 struct hclge_dev *hdev = ae_dev->priv; 3999 4000 /* return the highest priority reset level amongst all */ 4001 if (test_bit(HNAE3_IMP_RESET, addr)) { 4002 rst_level = HNAE3_IMP_RESET; 4003 clear_bit(HNAE3_IMP_RESET, addr); 4004 clear_bit(HNAE3_GLOBAL_RESET, addr); 4005 clear_bit(HNAE3_FUNC_RESET, addr); 4006 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) { 4007 rst_level = HNAE3_GLOBAL_RESET; 4008 clear_bit(HNAE3_GLOBAL_RESET, addr); 4009 clear_bit(HNAE3_FUNC_RESET, addr); 4010 } else if (test_bit(HNAE3_FUNC_RESET, addr)) { 4011 rst_level = HNAE3_FUNC_RESET; 4012 clear_bit(HNAE3_FUNC_RESET, addr); 4013 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 4014 rst_level = HNAE3_FLR_RESET; 4015 clear_bit(HNAE3_FLR_RESET, addr); 4016 } 4017 4018 if (hdev->reset_type != HNAE3_NONE_RESET && 4019 rst_level < hdev->reset_type) 4020 return HNAE3_NONE_RESET; 4021 4022 return rst_level; 4023 } 4024 4025 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 4026 { 4027 u32 clearval = 0; 4028 4029 switch (hdev->reset_type) { 4030 case HNAE3_IMP_RESET: 4031 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 4032 break; 4033 case HNAE3_GLOBAL_RESET: 4034 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 4035 break; 4036 default: 4037 break; 4038 } 4039 4040 if (!clearval) 4041 return; 4042 4043 /* For revision 0x20, the reset interrupt source 4044 * can only be cleared after hardware reset done 4045 */ 4046 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 4047 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, 4048 clearval); 4049 4050 hclge_enable_vector(&hdev->misc_vector, true); 4051 } 4052 4053 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable) 4054 { 4055 u32 reg_val; 4056 4057 reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 4058 if (enable) 4059 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY; 4060 else 4061 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY; 4062 4063 hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val); 4064 } 4065 4066 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev) 4067 { 4068 int ret; 4069 4070 ret = hclge_set_all_vf_rst(hdev, true); 4071 if (ret) 4072 return ret; 4073 4074 hclge_func_reset_sync_vf(hdev); 4075 4076 return 0; 4077 } 4078 4079 static int hclge_reset_prepare_wait(struct hclge_dev *hdev) 4080 { 4081 u32 reg_val; 4082 int ret = 0; 4083 4084 switch (hdev->reset_type) { 4085 case HNAE3_FUNC_RESET: 4086 ret = hclge_func_reset_notify_vf(hdev); 4087 if (ret) 4088 return ret; 4089 4090 ret = hclge_func_reset_cmd(hdev, 0); 4091 if (ret) { 4092 dev_err(&hdev->pdev->dev, 4093 "asserting function reset fail %d!\n", ret); 4094 return ret; 4095 } 4096 4097 /* After performaning pf reset, it is not necessary to do the 4098 * mailbox handling or send any command to firmware, because 4099 * any mailbox handling or command to firmware is only valid 4100 * after hclge_comm_cmd_init is called. 4101 */ 4102 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 4103 hdev->rst_stats.pf_rst_cnt++; 4104 break; 4105 case HNAE3_FLR_RESET: 4106 ret = hclge_func_reset_notify_vf(hdev); 4107 if (ret) 4108 return ret; 4109 break; 4110 case HNAE3_IMP_RESET: 4111 hclge_handle_imp_error(hdev); 4112 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4113 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, 4114 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); 4115 break; 4116 default: 4117 break; 4118 } 4119 4120 /* inform hardware that preparatory work is done */ 4121 msleep(HCLGE_RESET_SYNC_TIME); 4122 hclge_reset_handshake(hdev, true); 4123 dev_info(&hdev->pdev->dev, "prepare wait ok\n"); 4124 4125 return ret; 4126 } 4127 4128 static void hclge_show_rst_info(struct hclge_dev *hdev) 4129 { 4130 char *buf; 4131 4132 buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL); 4133 if (!buf) 4134 return; 4135 4136 hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN); 4137 4138 dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf); 4139 4140 kfree(buf); 4141 } 4142 4143 static bool hclge_reset_err_handle(struct hclge_dev *hdev) 4144 { 4145 #define MAX_RESET_FAIL_CNT 5 4146 4147 if (hdev->reset_pending) { 4148 dev_info(&hdev->pdev->dev, "Reset pending %lu\n", 4149 hdev->reset_pending); 4150 return true; 4151 } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) & 4152 HCLGE_RESET_INT_M) { 4153 dev_info(&hdev->pdev->dev, 4154 "reset failed because new reset interrupt\n"); 4155 hclge_clear_reset_cause(hdev); 4156 return false; 4157 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { 4158 hdev->rst_stats.reset_fail_cnt++; 4159 set_bit(hdev->reset_type, &hdev->reset_pending); 4160 dev_info(&hdev->pdev->dev, 4161 "re-schedule reset task(%u)\n", 4162 hdev->rst_stats.reset_fail_cnt); 4163 return true; 4164 } 4165 4166 hclge_clear_reset_cause(hdev); 4167 4168 /* recover the handshake status when reset fail */ 4169 hclge_reset_handshake(hdev, true); 4170 4171 dev_err(&hdev->pdev->dev, "Reset fail!\n"); 4172 4173 hclge_show_rst_info(hdev); 4174 4175 set_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4176 4177 return false; 4178 } 4179 4180 static void hclge_update_reset_level(struct hclge_dev *hdev) 4181 { 4182 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4183 enum hnae3_reset_type reset_level; 4184 4185 /* reset request will not be set during reset, so clear 4186 * pending reset request to avoid unnecessary reset 4187 * caused by the same reason. 4188 */ 4189 hclge_get_reset_level(ae_dev, &hdev->reset_request); 4190 4191 /* if default_reset_request has a higher level reset request, 4192 * it should be handled as soon as possible. since some errors 4193 * need this kind of reset to fix. 4194 */ 4195 reset_level = hclge_get_reset_level(ae_dev, 4196 &hdev->default_reset_request); 4197 if (reset_level != HNAE3_NONE_RESET) 4198 set_bit(reset_level, &hdev->reset_request); 4199 } 4200 4201 static int hclge_set_rst_done(struct hclge_dev *hdev) 4202 { 4203 struct hclge_pf_rst_done_cmd *req; 4204 struct hclge_desc desc; 4205 int ret; 4206 4207 req = (struct hclge_pf_rst_done_cmd *)desc.data; 4208 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false); 4209 req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT; 4210 4211 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4212 /* To be compatible with the old firmware, which does not support 4213 * command HCLGE_OPC_PF_RST_DONE, just print a warning and 4214 * return success 4215 */ 4216 if (ret == -EOPNOTSUPP) { 4217 dev_warn(&hdev->pdev->dev, 4218 "current firmware does not support command(0x%x)!\n", 4219 HCLGE_OPC_PF_RST_DONE); 4220 return 0; 4221 } else if (ret) { 4222 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n", 4223 ret); 4224 } 4225 4226 return ret; 4227 } 4228 4229 static int hclge_reset_prepare_up(struct hclge_dev *hdev) 4230 { 4231 int ret = 0; 4232 4233 switch (hdev->reset_type) { 4234 case HNAE3_FUNC_RESET: 4235 case HNAE3_FLR_RESET: 4236 ret = hclge_set_all_vf_rst(hdev, false); 4237 break; 4238 case HNAE3_GLOBAL_RESET: 4239 case HNAE3_IMP_RESET: 4240 ret = hclge_set_rst_done(hdev); 4241 break; 4242 default: 4243 break; 4244 } 4245 4246 /* clear up the handshake status after re-initialize done */ 4247 hclge_reset_handshake(hdev, false); 4248 4249 return ret; 4250 } 4251 4252 static int hclge_reset_stack(struct hclge_dev *hdev) 4253 { 4254 int ret; 4255 4256 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 4257 if (ret) 4258 return ret; 4259 4260 ret = hclge_reset_ae_dev(hdev->ae_dev); 4261 if (ret) 4262 return ret; 4263 4264 return hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 4265 } 4266 4267 static int hclge_reset_prepare(struct hclge_dev *hdev) 4268 { 4269 int ret; 4270 4271 hdev->rst_stats.reset_cnt++; 4272 /* perform reset of the stack & ae device for a client */ 4273 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 4274 if (ret) 4275 return ret; 4276 4277 rtnl_lock(); 4278 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 4279 rtnl_unlock(); 4280 if (ret) 4281 return ret; 4282 4283 return hclge_reset_prepare_wait(hdev); 4284 } 4285 4286 static int hclge_reset_rebuild(struct hclge_dev *hdev) 4287 { 4288 int ret; 4289 4290 hdev->rst_stats.hw_reset_done_cnt++; 4291 4292 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 4293 if (ret) 4294 return ret; 4295 4296 rtnl_lock(); 4297 ret = hclge_reset_stack(hdev); 4298 rtnl_unlock(); 4299 if (ret) 4300 return ret; 4301 4302 hclge_clear_reset_cause(hdev); 4303 4304 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 4305 /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1 4306 * times 4307 */ 4308 if (ret && 4309 hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1) 4310 return ret; 4311 4312 ret = hclge_reset_prepare_up(hdev); 4313 if (ret) 4314 return ret; 4315 4316 rtnl_lock(); 4317 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT); 4318 rtnl_unlock(); 4319 if (ret) 4320 return ret; 4321 4322 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT); 4323 if (ret) 4324 return ret; 4325 4326 hdev->last_reset_time = jiffies; 4327 hdev->rst_stats.reset_fail_cnt = 0; 4328 hdev->rst_stats.reset_done_cnt++; 4329 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4330 4331 hclge_update_reset_level(hdev); 4332 4333 return 0; 4334 } 4335 4336 static void hclge_reset(struct hclge_dev *hdev) 4337 { 4338 if (hclge_reset_prepare(hdev)) 4339 goto err_reset; 4340 4341 if (hclge_reset_wait(hdev)) 4342 goto err_reset; 4343 4344 if (hclge_reset_rebuild(hdev)) 4345 goto err_reset; 4346 4347 return; 4348 4349 err_reset: 4350 if (hclge_reset_err_handle(hdev)) 4351 hclge_reset_task_schedule(hdev); 4352 } 4353 4354 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) 4355 { 4356 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4357 struct hclge_dev *hdev = ae_dev->priv; 4358 4359 /* We might end up getting called broadly because of 2 below cases: 4360 * 1. Recoverable error was conveyed through APEI and only way to bring 4361 * normalcy is to reset. 4362 * 2. A new reset request from the stack due to timeout 4363 * 4364 * check if this is a new reset request and we are not here just because 4365 * last reset attempt did not succeed and watchdog hit us again. We will 4366 * know this if last reset request did not occur very recently (watchdog 4367 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 4368 * In case of new request we reset the "reset level" to PF reset. 4369 * And if it is a repeat reset request of the most recent one then we 4370 * want to make sure we throttle the reset request. Therefore, we will 4371 * not allow it again before 3*HZ times. 4372 */ 4373 4374 if (time_before(jiffies, (hdev->last_reset_time + 4375 HCLGE_RESET_INTERVAL))) { 4376 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 4377 return; 4378 } 4379 4380 if (hdev->default_reset_request) { 4381 hdev->reset_level = 4382 hclge_get_reset_level(ae_dev, 4383 &hdev->default_reset_request); 4384 } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) { 4385 hdev->reset_level = HNAE3_FUNC_RESET; 4386 } 4387 4388 dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n", 4389 hdev->reset_level); 4390 4391 /* request reset & schedule reset task */ 4392 set_bit(hdev->reset_level, &hdev->reset_request); 4393 hclge_reset_task_schedule(hdev); 4394 4395 if (hdev->reset_level < HNAE3_GLOBAL_RESET) 4396 hdev->reset_level++; 4397 } 4398 4399 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 4400 enum hnae3_reset_type rst_type) 4401 { 4402 struct hclge_dev *hdev = ae_dev->priv; 4403 4404 set_bit(rst_type, &hdev->default_reset_request); 4405 } 4406 4407 static void hclge_reset_timer(struct timer_list *t) 4408 { 4409 struct hclge_dev *hdev = from_timer(hdev, t, reset_timer); 4410 4411 /* if default_reset_request has no value, it means that this reset 4412 * request has already be handled, so just return here 4413 */ 4414 if (!hdev->default_reset_request) 4415 return; 4416 4417 dev_info(&hdev->pdev->dev, 4418 "triggering reset in reset timer\n"); 4419 hclge_reset_event(hdev->pdev, NULL); 4420 } 4421 4422 static void hclge_reset_subtask(struct hclge_dev *hdev) 4423 { 4424 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4425 4426 /* check if there is any ongoing reset in the hardware. This status can 4427 * be checked from reset_pending. If there is then, we need to wait for 4428 * hardware to complete reset. 4429 * a. If we are able to figure out in reasonable time that hardware 4430 * has fully resetted then, we can proceed with driver, client 4431 * reset. 4432 * b. else, we can come back later to check this status so re-sched 4433 * now. 4434 */ 4435 hdev->last_reset_time = jiffies; 4436 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending); 4437 if (hdev->reset_type != HNAE3_NONE_RESET) 4438 hclge_reset(hdev); 4439 4440 /* check if we got any *new* reset requests to be honored */ 4441 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request); 4442 if (hdev->reset_type != HNAE3_NONE_RESET) 4443 hclge_do_reset(hdev); 4444 4445 hdev->reset_type = HNAE3_NONE_RESET; 4446 } 4447 4448 static void hclge_handle_err_reset_request(struct hclge_dev *hdev) 4449 { 4450 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4451 enum hnae3_reset_type reset_type; 4452 4453 if (ae_dev->hw_err_reset_req) { 4454 reset_type = hclge_get_reset_level(ae_dev, 4455 &ae_dev->hw_err_reset_req); 4456 hclge_set_def_reset_request(ae_dev, reset_type); 4457 } 4458 4459 if (hdev->default_reset_request && ae_dev->ops->reset_event) 4460 ae_dev->ops->reset_event(hdev->pdev, NULL); 4461 4462 /* enable interrupt after error handling complete */ 4463 hclge_enable_vector(&hdev->misc_vector, true); 4464 } 4465 4466 static void hclge_handle_err_recovery(struct hclge_dev *hdev) 4467 { 4468 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4469 4470 ae_dev->hw_err_reset_req = 0; 4471 4472 if (hclge_find_error_source(hdev)) { 4473 hclge_handle_error_info_log(ae_dev); 4474 hclge_handle_mac_tnl(hdev); 4475 } 4476 4477 hclge_handle_err_reset_request(hdev); 4478 } 4479 4480 static void hclge_misc_err_recovery(struct hclge_dev *hdev) 4481 { 4482 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4483 struct device *dev = &hdev->pdev->dev; 4484 u32 msix_sts_reg; 4485 4486 msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 4487 if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) { 4488 if (hclge_handle_hw_msix_error 4489 (hdev, &hdev->default_reset_request)) 4490 dev_info(dev, "received msix interrupt 0x%x\n", 4491 msix_sts_reg); 4492 } 4493 4494 hclge_handle_hw_ras_error(ae_dev); 4495 4496 hclge_handle_err_reset_request(hdev); 4497 } 4498 4499 static void hclge_errhand_service_task(struct hclge_dev *hdev) 4500 { 4501 if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 4502 return; 4503 4504 if (hnae3_dev_ras_imp_supported(hdev)) 4505 hclge_handle_err_recovery(hdev); 4506 else 4507 hclge_misc_err_recovery(hdev); 4508 } 4509 4510 static void hclge_reset_service_task(struct hclge_dev *hdev) 4511 { 4512 if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 4513 return; 4514 4515 if (time_is_before_jiffies(hdev->last_rst_scheduled + 4516 HCLGE_RESET_SCHED_TIMEOUT)) 4517 dev_warn(&hdev->pdev->dev, 4518 "reset service task is scheduled after %ums on cpu%u!\n", 4519 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled), 4520 smp_processor_id()); 4521 4522 down(&hdev->reset_sem); 4523 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4524 4525 hclge_reset_subtask(hdev); 4526 4527 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4528 up(&hdev->reset_sem); 4529 } 4530 4531 static void hclge_update_vport_alive(struct hclge_dev *hdev) 4532 { 4533 #define HCLGE_ALIVE_SECONDS_NORMAL 8 4534 4535 unsigned long alive_time = HCLGE_ALIVE_SECONDS_NORMAL * HZ; 4536 int i; 4537 4538 /* start from vport 1 for PF is always alive */ 4539 for (i = 1; i < hdev->num_alloc_vport; i++) { 4540 struct hclge_vport *vport = &hdev->vport[i]; 4541 4542 if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) || 4543 !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 4544 continue; 4545 if (time_after(jiffies, vport->last_active_jiffies + 4546 alive_time)) { 4547 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 4548 dev_warn(&hdev->pdev->dev, 4549 "VF %u heartbeat timeout\n", 4550 i - HCLGE_VF_VPORT_START_NUM); 4551 } 4552 } 4553 } 4554 4555 static void hclge_periodic_service_task(struct hclge_dev *hdev) 4556 { 4557 unsigned long delta = round_jiffies_relative(HZ); 4558 4559 if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 4560 return; 4561 4562 /* Always handle the link updating to make sure link state is 4563 * updated when it is triggered by mbx. 4564 */ 4565 hclge_update_link_status(hdev); 4566 hclge_sync_mac_table(hdev); 4567 hclge_sync_promisc_mode(hdev); 4568 hclge_sync_fd_table(hdev); 4569 4570 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 4571 delta = jiffies - hdev->last_serv_processed; 4572 4573 if (delta < round_jiffies_relative(HZ)) { 4574 delta = round_jiffies_relative(HZ) - delta; 4575 goto out; 4576 } 4577 } 4578 4579 hdev->serv_processed_cnt++; 4580 hclge_update_vport_alive(hdev); 4581 4582 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) { 4583 hdev->last_serv_processed = jiffies; 4584 goto out; 4585 } 4586 4587 if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL)) 4588 hclge_update_stats_for_all(hdev); 4589 4590 hclge_update_port_info(hdev); 4591 hclge_sync_vlan_filter(hdev); 4592 4593 if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL)) 4594 hclge_rfs_filter_expire(hdev); 4595 4596 hdev->last_serv_processed = jiffies; 4597 4598 out: 4599 hclge_task_schedule(hdev, delta); 4600 } 4601 4602 static void hclge_ptp_service_task(struct hclge_dev *hdev) 4603 { 4604 unsigned long flags; 4605 4606 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) || 4607 !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) || 4608 !time_is_before_jiffies(hdev->ptp->tx_start + HZ)) 4609 return; 4610 4611 /* to prevent concurrence with the irq handler */ 4612 spin_lock_irqsave(&hdev->ptp->lock, flags); 4613 4614 /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq 4615 * handler may handle it just before spin_lock_irqsave(). 4616 */ 4617 if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) 4618 hclge_ptp_clean_tx_hwts(hdev); 4619 4620 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 4621 } 4622 4623 static void hclge_service_task(struct work_struct *work) 4624 { 4625 struct hclge_dev *hdev = 4626 container_of(work, struct hclge_dev, service_task.work); 4627 4628 hclge_errhand_service_task(hdev); 4629 hclge_reset_service_task(hdev); 4630 hclge_ptp_service_task(hdev); 4631 hclge_mailbox_service_task(hdev); 4632 hclge_periodic_service_task(hdev); 4633 4634 /* Handle error recovery, reset and mbx again in case periodical task 4635 * delays the handling by calling hclge_task_schedule() in 4636 * hclge_periodic_service_task(). 4637 */ 4638 hclge_errhand_service_task(hdev); 4639 hclge_reset_service_task(hdev); 4640 hclge_mailbox_service_task(hdev); 4641 } 4642 4643 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 4644 { 4645 /* VF handle has no client */ 4646 if (!handle->client) 4647 return container_of(handle, struct hclge_vport, nic); 4648 else if (handle->client->type == HNAE3_CLIENT_ROCE) 4649 return container_of(handle, struct hclge_vport, roce); 4650 else 4651 return container_of(handle, struct hclge_vport, nic); 4652 } 4653 4654 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx, 4655 struct hnae3_vector_info *vector_info) 4656 { 4657 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 64 4658 4659 vector_info->vector = pci_irq_vector(hdev->pdev, idx); 4660 4661 /* need an extend offset to config vector >= 64 */ 4662 if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2) 4663 vector_info->io_addr = hdev->hw.hw.io_base + 4664 HCLGE_VECTOR_REG_BASE + 4665 (idx - 1) * HCLGE_VECTOR_REG_OFFSET; 4666 else 4667 vector_info->io_addr = hdev->hw.hw.io_base + 4668 HCLGE_VECTOR_EXT_REG_BASE + 4669 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4670 HCLGE_VECTOR_REG_OFFSET_H + 4671 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4672 HCLGE_VECTOR_REG_OFFSET; 4673 4674 hdev->vector_status[idx] = hdev->vport[0].vport_id; 4675 hdev->vector_irq[idx] = vector_info->vector; 4676 } 4677 4678 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 4679 struct hnae3_vector_info *vector_info) 4680 { 4681 struct hclge_vport *vport = hclge_get_vport(handle); 4682 struct hnae3_vector_info *vector = vector_info; 4683 struct hclge_dev *hdev = vport->back; 4684 int alloc = 0; 4685 u16 i = 0; 4686 u16 j; 4687 4688 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num); 4689 vector_num = min(hdev->num_msi_left, vector_num); 4690 4691 for (j = 0; j < vector_num; j++) { 4692 while (++i < hdev->num_nic_msi) { 4693 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 4694 hclge_get_vector_info(hdev, i, vector); 4695 vector++; 4696 alloc++; 4697 4698 break; 4699 } 4700 } 4701 } 4702 hdev->num_msi_left -= alloc; 4703 hdev->num_msi_used += alloc; 4704 4705 return alloc; 4706 } 4707 4708 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 4709 { 4710 int i; 4711 4712 for (i = 0; i < hdev->num_msi; i++) 4713 if (vector == hdev->vector_irq[i]) 4714 return i; 4715 4716 return -EINVAL; 4717 } 4718 4719 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 4720 { 4721 struct hclge_vport *vport = hclge_get_vport(handle); 4722 struct hclge_dev *hdev = vport->back; 4723 int vector_id; 4724 4725 vector_id = hclge_get_vector_index(hdev, vector); 4726 if (vector_id < 0) { 4727 dev_err(&hdev->pdev->dev, 4728 "Get vector index fail. vector = %d\n", vector); 4729 return vector_id; 4730 } 4731 4732 hclge_free_vector(hdev, vector_id); 4733 4734 return 0; 4735 } 4736 4737 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 4738 u8 *key, u8 *hfunc) 4739 { 4740 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4741 struct hclge_vport *vport = hclge_get_vport(handle); 4742 struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg; 4743 4744 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 4745 4746 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 4747 ae_dev->dev_specs.rss_ind_tbl_size); 4748 4749 return 0; 4750 } 4751 4752 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 4753 const u8 *key, const u8 hfunc) 4754 { 4755 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4756 struct hclge_vport *vport = hclge_get_vport(handle); 4757 struct hclge_dev *hdev = vport->back; 4758 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 4759 int ret, i; 4760 4761 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc); 4762 if (ret) { 4763 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc); 4764 return ret; 4765 } 4766 4767 /* Update the shadow RSS table with user specified qids */ 4768 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 4769 rss_cfg->rss_indirection_tbl[i] = indir[i]; 4770 4771 /* Update the hardware */ 4772 return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw, 4773 rss_cfg->rss_indirection_tbl); 4774 } 4775 4776 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 4777 struct ethtool_rxnfc *nfc) 4778 { 4779 struct hclge_vport *vport = hclge_get_vport(handle); 4780 struct hclge_dev *hdev = vport->back; 4781 int ret; 4782 4783 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 4784 &hdev->rss_cfg, nfc); 4785 if (ret) { 4786 dev_err(&hdev->pdev->dev, 4787 "failed to set rss tuple, ret = %d.\n", ret); 4788 return ret; 4789 } 4790 4791 return 0; 4792 } 4793 4794 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 4795 struct ethtool_rxnfc *nfc) 4796 { 4797 struct hclge_vport *vport = hclge_get_vport(handle); 4798 u8 tuple_sets; 4799 int ret; 4800 4801 nfc->data = 0; 4802 4803 ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type, 4804 &tuple_sets); 4805 if (ret || !tuple_sets) 4806 return ret; 4807 4808 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 4809 4810 return 0; 4811 } 4812 4813 static int hclge_get_tc_size(struct hnae3_handle *handle) 4814 { 4815 struct hclge_vport *vport = hclge_get_vport(handle); 4816 struct hclge_dev *hdev = vport->back; 4817 4818 return hdev->pf_rss_size_max; 4819 } 4820 4821 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev) 4822 { 4823 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 4824 struct hclge_vport *vport = hdev->vport; 4825 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 4826 u16 tc_valid[HCLGE_MAX_TC_NUM] = {0}; 4827 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 4828 struct hnae3_tc_info *tc_info; 4829 u16 roundup_size; 4830 u16 rss_size; 4831 int i; 4832 4833 tc_info = &vport->nic.kinfo.tc_info; 4834 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 4835 rss_size = tc_info->tqp_count[i]; 4836 tc_valid[i] = 0; 4837 4838 if (!(hdev->hw_tc_map & BIT(i))) 4839 continue; 4840 4841 /* tc_size set to hardware is the log2 of roundup power of two 4842 * of rss_size, the acutal queue size is limited by indirection 4843 * table. 4844 */ 4845 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size || 4846 rss_size == 0) { 4847 dev_err(&hdev->pdev->dev, 4848 "Configure rss tc size failed, invalid TC_SIZE = %u\n", 4849 rss_size); 4850 return -EINVAL; 4851 } 4852 4853 roundup_size = roundup_pow_of_two(rss_size); 4854 roundup_size = ilog2(roundup_size); 4855 4856 tc_valid[i] = 1; 4857 tc_size[i] = roundup_size; 4858 tc_offset[i] = tc_info->tqp_offset[i]; 4859 } 4860 4861 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 4862 tc_size); 4863 } 4864 4865 int hclge_rss_init_hw(struct hclge_dev *hdev) 4866 { 4867 u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl; 4868 u8 *key = hdev->rss_cfg.rss_hash_key; 4869 u8 hfunc = hdev->rss_cfg.rss_algo; 4870 int ret; 4871 4872 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 4873 rss_indir); 4874 if (ret) 4875 return ret; 4876 4877 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key); 4878 if (ret) 4879 return ret; 4880 4881 ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, &hdev->rss_cfg); 4882 if (ret) 4883 return ret; 4884 4885 return hclge_init_rss_tc_mode(hdev); 4886 } 4887 4888 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 4889 int vector_id, bool en, 4890 struct hnae3_ring_chain_node *ring_chain) 4891 { 4892 struct hclge_dev *hdev = vport->back; 4893 struct hnae3_ring_chain_node *node; 4894 struct hclge_desc desc; 4895 struct hclge_ctrl_vector_chain_cmd *req = 4896 (struct hclge_ctrl_vector_chain_cmd *)desc.data; 4897 enum hclge_comm_cmd_status status; 4898 enum hclge_opcode_type op; 4899 u16 tqp_type_and_id; 4900 int i; 4901 4902 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 4903 hclge_cmd_setup_basic_desc(&desc, op, false); 4904 req->int_vector_id_l = hnae3_get_field(vector_id, 4905 HCLGE_VECTOR_ID_L_M, 4906 HCLGE_VECTOR_ID_L_S); 4907 req->int_vector_id_h = hnae3_get_field(vector_id, 4908 HCLGE_VECTOR_ID_H_M, 4909 HCLGE_VECTOR_ID_H_S); 4910 4911 i = 0; 4912 for (node = ring_chain; node; node = node->next) { 4913 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 4914 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 4915 HCLGE_INT_TYPE_S, 4916 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 4917 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 4918 HCLGE_TQP_ID_S, node->tqp_index); 4919 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 4920 HCLGE_INT_GL_IDX_S, 4921 hnae3_get_field(node->int_gl_idx, 4922 HNAE3_RING_GL_IDX_M, 4923 HNAE3_RING_GL_IDX_S)); 4924 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 4925 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 4926 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 4927 req->vfid = vport->vport_id; 4928 4929 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4930 if (status) { 4931 dev_err(&hdev->pdev->dev, 4932 "Map TQP fail, status is %d.\n", 4933 status); 4934 return -EIO; 4935 } 4936 i = 0; 4937 4938 hclge_cmd_setup_basic_desc(&desc, 4939 op, 4940 false); 4941 req->int_vector_id_l = 4942 hnae3_get_field(vector_id, 4943 HCLGE_VECTOR_ID_L_M, 4944 HCLGE_VECTOR_ID_L_S); 4945 req->int_vector_id_h = 4946 hnae3_get_field(vector_id, 4947 HCLGE_VECTOR_ID_H_M, 4948 HCLGE_VECTOR_ID_H_S); 4949 } 4950 } 4951 4952 if (i > 0) { 4953 req->int_cause_num = i; 4954 req->vfid = vport->vport_id; 4955 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4956 if (status) { 4957 dev_err(&hdev->pdev->dev, 4958 "Map TQP fail, status is %d.\n", status); 4959 return -EIO; 4960 } 4961 } 4962 4963 return 0; 4964 } 4965 4966 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector, 4967 struct hnae3_ring_chain_node *ring_chain) 4968 { 4969 struct hclge_vport *vport = hclge_get_vport(handle); 4970 struct hclge_dev *hdev = vport->back; 4971 int vector_id; 4972 4973 vector_id = hclge_get_vector_index(hdev, vector); 4974 if (vector_id < 0) { 4975 dev_err(&hdev->pdev->dev, 4976 "failed to get vector index. vector=%d\n", vector); 4977 return vector_id; 4978 } 4979 4980 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 4981 } 4982 4983 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector, 4984 struct hnae3_ring_chain_node *ring_chain) 4985 { 4986 struct hclge_vport *vport = hclge_get_vport(handle); 4987 struct hclge_dev *hdev = vport->back; 4988 int vector_id, ret; 4989 4990 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 4991 return 0; 4992 4993 vector_id = hclge_get_vector_index(hdev, vector); 4994 if (vector_id < 0) { 4995 dev_err(&handle->pdev->dev, 4996 "Get vector index fail. ret =%d\n", vector_id); 4997 return vector_id; 4998 } 4999 5000 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 5001 if (ret) 5002 dev_err(&handle->pdev->dev, 5003 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 5004 vector_id, ret); 5005 5006 return ret; 5007 } 5008 5009 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id, 5010 bool en_uc, bool en_mc, bool en_bc) 5011 { 5012 struct hclge_vport *vport = &hdev->vport[vf_id]; 5013 struct hnae3_handle *handle = &vport->nic; 5014 struct hclge_promisc_cfg_cmd *req; 5015 struct hclge_desc desc; 5016 bool uc_tx_en = en_uc; 5017 u8 promisc_cfg = 0; 5018 int ret; 5019 5020 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 5021 5022 req = (struct hclge_promisc_cfg_cmd *)desc.data; 5023 req->vf_id = vf_id; 5024 5025 if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags)) 5026 uc_tx_en = false; 5027 5028 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0); 5029 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0); 5030 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0); 5031 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0); 5032 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0); 5033 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0); 5034 req->extend_promisc = promisc_cfg; 5035 5036 /* to be compatible with DEVICE_VERSION_V1/2 */ 5037 promisc_cfg = 0; 5038 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0); 5039 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0); 5040 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0); 5041 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1); 5042 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1); 5043 req->promisc = promisc_cfg; 5044 5045 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5046 if (ret) 5047 dev_err(&hdev->pdev->dev, 5048 "failed to set vport %u promisc mode, ret = %d.\n", 5049 vf_id, ret); 5050 5051 return ret; 5052 } 5053 5054 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 5055 bool en_mc_pmc, bool en_bc_pmc) 5056 { 5057 return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id, 5058 en_uc_pmc, en_mc_pmc, en_bc_pmc); 5059 } 5060 5061 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 5062 bool en_mc_pmc) 5063 { 5064 struct hclge_vport *vport = hclge_get_vport(handle); 5065 struct hclge_dev *hdev = vport->back; 5066 bool en_bc_pmc = true; 5067 5068 /* For device whose version below V2, if broadcast promisc enabled, 5069 * vlan filter is always bypassed. So broadcast promisc should be 5070 * disabled until user enable promisc mode 5071 */ 5072 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 5073 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false; 5074 5075 return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc, 5076 en_bc_pmc); 5077 } 5078 5079 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle) 5080 { 5081 struct hclge_vport *vport = hclge_get_vport(handle); 5082 5083 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5084 } 5085 5086 static void hclge_sync_fd_state(struct hclge_dev *hdev) 5087 { 5088 if (hlist_empty(&hdev->fd_rule_list)) 5089 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 5090 } 5091 5092 static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location) 5093 { 5094 if (!test_bit(location, hdev->fd_bmap)) { 5095 set_bit(location, hdev->fd_bmap); 5096 hdev->hclge_fd_rule_num++; 5097 } 5098 } 5099 5100 static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location) 5101 { 5102 if (test_bit(location, hdev->fd_bmap)) { 5103 clear_bit(location, hdev->fd_bmap); 5104 hdev->hclge_fd_rule_num--; 5105 } 5106 } 5107 5108 static void hclge_fd_free_node(struct hclge_dev *hdev, 5109 struct hclge_fd_rule *rule) 5110 { 5111 hlist_del(&rule->rule_node); 5112 kfree(rule); 5113 hclge_sync_fd_state(hdev); 5114 } 5115 5116 static void hclge_update_fd_rule_node(struct hclge_dev *hdev, 5117 struct hclge_fd_rule *old_rule, 5118 struct hclge_fd_rule *new_rule, 5119 enum HCLGE_FD_NODE_STATE state) 5120 { 5121 switch (state) { 5122 case HCLGE_FD_TO_ADD: 5123 case HCLGE_FD_ACTIVE: 5124 /* 1) if the new state is TO_ADD, just replace the old rule 5125 * with the same location, no matter its state, because the 5126 * new rule will be configured to the hardware. 5127 * 2) if the new state is ACTIVE, it means the new rule 5128 * has been configured to the hardware, so just replace 5129 * the old rule node with the same location. 5130 * 3) for it doesn't add a new node to the list, so it's 5131 * unnecessary to update the rule number and fd_bmap. 5132 */ 5133 new_rule->rule_node.next = old_rule->rule_node.next; 5134 new_rule->rule_node.pprev = old_rule->rule_node.pprev; 5135 memcpy(old_rule, new_rule, sizeof(*old_rule)); 5136 kfree(new_rule); 5137 break; 5138 case HCLGE_FD_DELETED: 5139 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5140 hclge_fd_free_node(hdev, old_rule); 5141 break; 5142 case HCLGE_FD_TO_DEL: 5143 /* if new request is TO_DEL, and old rule is existent 5144 * 1) the state of old rule is TO_DEL, we need do nothing, 5145 * because we delete rule by location, other rule content 5146 * is unncessary. 5147 * 2) the state of old rule is ACTIVE, we need to change its 5148 * state to TO_DEL, so the rule will be deleted when periodic 5149 * task being scheduled. 5150 * 3) the state of old rule is TO_ADD, it means the rule hasn't 5151 * been added to hardware, so we just delete the rule node from 5152 * fd_rule_list directly. 5153 */ 5154 if (old_rule->state == HCLGE_FD_TO_ADD) { 5155 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5156 hclge_fd_free_node(hdev, old_rule); 5157 return; 5158 } 5159 old_rule->state = HCLGE_FD_TO_DEL; 5160 break; 5161 } 5162 } 5163 5164 static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist, 5165 u16 location, 5166 struct hclge_fd_rule **parent) 5167 { 5168 struct hclge_fd_rule *rule; 5169 struct hlist_node *node; 5170 5171 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 5172 if (rule->location == location) 5173 return rule; 5174 else if (rule->location > location) 5175 return NULL; 5176 /* record the parent node, use to keep the nodes in fd_rule_list 5177 * in ascend order. 5178 */ 5179 *parent = rule; 5180 } 5181 5182 return NULL; 5183 } 5184 5185 /* insert fd rule node in ascend order according to rule->location */ 5186 static void hclge_fd_insert_rule_node(struct hlist_head *hlist, 5187 struct hclge_fd_rule *rule, 5188 struct hclge_fd_rule *parent) 5189 { 5190 INIT_HLIST_NODE(&rule->rule_node); 5191 5192 if (parent) 5193 hlist_add_behind(&rule->rule_node, &parent->rule_node); 5194 else 5195 hlist_add_head(&rule->rule_node, hlist); 5196 } 5197 5198 static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev, 5199 struct hclge_fd_user_def_cfg *cfg) 5200 { 5201 struct hclge_fd_user_def_cfg_cmd *req; 5202 struct hclge_desc desc; 5203 u16 data = 0; 5204 int ret; 5205 5206 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false); 5207 5208 req = (struct hclge_fd_user_def_cfg_cmd *)desc.data; 5209 5210 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0); 5211 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5212 HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset); 5213 req->ol2_cfg = cpu_to_le16(data); 5214 5215 data = 0; 5216 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0); 5217 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5218 HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset); 5219 req->ol3_cfg = cpu_to_le16(data); 5220 5221 data = 0; 5222 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0); 5223 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5224 HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset); 5225 req->ol4_cfg = cpu_to_le16(data); 5226 5227 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5228 if (ret) 5229 dev_err(&hdev->pdev->dev, 5230 "failed to set fd user def data, ret= %d\n", ret); 5231 return ret; 5232 } 5233 5234 static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked) 5235 { 5236 int ret; 5237 5238 if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state)) 5239 return; 5240 5241 if (!locked) 5242 spin_lock_bh(&hdev->fd_rule_lock); 5243 5244 ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg); 5245 if (ret) 5246 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5247 5248 if (!locked) 5249 spin_unlock_bh(&hdev->fd_rule_lock); 5250 } 5251 5252 static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev, 5253 struct hclge_fd_rule *rule) 5254 { 5255 struct hlist_head *hlist = &hdev->fd_rule_list; 5256 struct hclge_fd_rule *fd_rule, *parent = NULL; 5257 struct hclge_fd_user_def_info *info, *old_info; 5258 struct hclge_fd_user_def_cfg *cfg; 5259 5260 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5261 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5262 return 0; 5263 5264 /* for valid layer is start from 1, so need minus 1 to get the cfg */ 5265 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5266 info = &rule->ep.user_def; 5267 5268 if (!cfg->ref_cnt || cfg->offset == info->offset) 5269 return 0; 5270 5271 if (cfg->ref_cnt > 1) 5272 goto error; 5273 5274 fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent); 5275 if (fd_rule) { 5276 old_info = &fd_rule->ep.user_def; 5277 if (info->layer == old_info->layer) 5278 return 0; 5279 } 5280 5281 error: 5282 dev_err(&hdev->pdev->dev, 5283 "No available offset for layer%d fd rule, each layer only support one user def offset.\n", 5284 info->layer + 1); 5285 return -ENOSPC; 5286 } 5287 5288 static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev, 5289 struct hclge_fd_rule *rule) 5290 { 5291 struct hclge_fd_user_def_cfg *cfg; 5292 5293 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5294 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5295 return; 5296 5297 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5298 if (!cfg->ref_cnt) { 5299 cfg->offset = rule->ep.user_def.offset; 5300 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5301 } 5302 cfg->ref_cnt++; 5303 } 5304 5305 static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev, 5306 struct hclge_fd_rule *rule) 5307 { 5308 struct hclge_fd_user_def_cfg *cfg; 5309 5310 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5311 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5312 return; 5313 5314 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5315 if (!cfg->ref_cnt) 5316 return; 5317 5318 cfg->ref_cnt--; 5319 if (!cfg->ref_cnt) { 5320 cfg->offset = 0; 5321 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5322 } 5323 } 5324 5325 static void hclge_update_fd_list(struct hclge_dev *hdev, 5326 enum HCLGE_FD_NODE_STATE state, u16 location, 5327 struct hclge_fd_rule *new_rule) 5328 { 5329 struct hlist_head *hlist = &hdev->fd_rule_list; 5330 struct hclge_fd_rule *fd_rule, *parent = NULL; 5331 5332 fd_rule = hclge_find_fd_rule(hlist, location, &parent); 5333 if (fd_rule) { 5334 hclge_fd_dec_user_def_refcnt(hdev, fd_rule); 5335 if (state == HCLGE_FD_ACTIVE) 5336 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5337 hclge_sync_fd_user_def_cfg(hdev, true); 5338 5339 hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state); 5340 return; 5341 } 5342 5343 /* it's unlikely to fail here, because we have checked the rule 5344 * exist before. 5345 */ 5346 if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) { 5347 dev_warn(&hdev->pdev->dev, 5348 "failed to delete fd rule %u, it's inexistent\n", 5349 location); 5350 return; 5351 } 5352 5353 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5354 hclge_sync_fd_user_def_cfg(hdev, true); 5355 5356 hclge_fd_insert_rule_node(hlist, new_rule, parent); 5357 hclge_fd_inc_rule_cnt(hdev, new_rule->location); 5358 5359 if (state == HCLGE_FD_TO_ADD) { 5360 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 5361 hclge_task_schedule(hdev, 0); 5362 } 5363 } 5364 5365 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode) 5366 { 5367 struct hclge_get_fd_mode_cmd *req; 5368 struct hclge_desc desc; 5369 int ret; 5370 5371 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true); 5372 5373 req = (struct hclge_get_fd_mode_cmd *)desc.data; 5374 5375 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5376 if (ret) { 5377 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret); 5378 return ret; 5379 } 5380 5381 *fd_mode = req->mode; 5382 5383 return ret; 5384 } 5385 5386 static int hclge_get_fd_allocation(struct hclge_dev *hdev, 5387 u32 *stage1_entry_num, 5388 u32 *stage2_entry_num, 5389 u16 *stage1_counter_num, 5390 u16 *stage2_counter_num) 5391 { 5392 struct hclge_get_fd_allocation_cmd *req; 5393 struct hclge_desc desc; 5394 int ret; 5395 5396 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true); 5397 5398 req = (struct hclge_get_fd_allocation_cmd *)desc.data; 5399 5400 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5401 if (ret) { 5402 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n", 5403 ret); 5404 return ret; 5405 } 5406 5407 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num); 5408 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num); 5409 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num); 5410 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num); 5411 5412 return ret; 5413 } 5414 5415 static int hclge_set_fd_key_config(struct hclge_dev *hdev, 5416 enum HCLGE_FD_STAGE stage_num) 5417 { 5418 struct hclge_set_fd_key_config_cmd *req; 5419 struct hclge_fd_key_cfg *stage; 5420 struct hclge_desc desc; 5421 int ret; 5422 5423 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false); 5424 5425 req = (struct hclge_set_fd_key_config_cmd *)desc.data; 5426 stage = &hdev->fd_cfg.key_cfg[stage_num]; 5427 req->stage = stage_num; 5428 req->key_select = stage->key_sel; 5429 req->inner_sipv6_word_en = stage->inner_sipv6_word_en; 5430 req->inner_dipv6_word_en = stage->inner_dipv6_word_en; 5431 req->outer_sipv6_word_en = stage->outer_sipv6_word_en; 5432 req->outer_dipv6_word_en = stage->outer_dipv6_word_en; 5433 req->tuple_mask = cpu_to_le32(~stage->tuple_active); 5434 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active); 5435 5436 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5437 if (ret) 5438 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret); 5439 5440 return ret; 5441 } 5442 5443 static void hclge_fd_disable_user_def(struct hclge_dev *hdev) 5444 { 5445 struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg; 5446 5447 spin_lock_bh(&hdev->fd_rule_lock); 5448 memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg)); 5449 spin_unlock_bh(&hdev->fd_rule_lock); 5450 5451 hclge_fd_set_user_def_cmd(hdev, cfg); 5452 } 5453 5454 static int hclge_init_fd_config(struct hclge_dev *hdev) 5455 { 5456 #define LOW_2_WORDS 0x03 5457 struct hclge_fd_key_cfg *key_cfg; 5458 int ret; 5459 5460 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 5461 return 0; 5462 5463 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode); 5464 if (ret) 5465 return ret; 5466 5467 switch (hdev->fd_cfg.fd_mode) { 5468 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1: 5469 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH; 5470 break; 5471 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1: 5472 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2; 5473 break; 5474 default: 5475 dev_err(&hdev->pdev->dev, 5476 "Unsupported flow director mode %u\n", 5477 hdev->fd_cfg.fd_mode); 5478 return -EOPNOTSUPP; 5479 } 5480 5481 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1]; 5482 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE; 5483 key_cfg->inner_sipv6_word_en = LOW_2_WORDS; 5484 key_cfg->inner_dipv6_word_en = LOW_2_WORDS; 5485 key_cfg->outer_sipv6_word_en = 0; 5486 key_cfg->outer_dipv6_word_en = 0; 5487 5488 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) | 5489 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) | 5490 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5491 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5492 5493 /* If use max 400bit key, we can support tuples for ether type */ 5494 if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 5495 key_cfg->tuple_active |= 5496 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC); 5497 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5498 key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 5499 } 5500 5501 /* roce_type is used to filter roce frames 5502 * dst_vport is used to specify the rule 5503 */ 5504 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT); 5505 5506 ret = hclge_get_fd_allocation(hdev, 5507 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1], 5508 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2], 5509 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1], 5510 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]); 5511 if (ret) 5512 return ret; 5513 5514 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1); 5515 } 5516 5517 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x, 5518 int loc, u8 *key, bool is_add) 5519 { 5520 struct hclge_fd_tcam_config_1_cmd *req1; 5521 struct hclge_fd_tcam_config_2_cmd *req2; 5522 struct hclge_fd_tcam_config_3_cmd *req3; 5523 struct hclge_desc desc[3]; 5524 int ret; 5525 5526 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false); 5527 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5528 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false); 5529 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5530 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false); 5531 5532 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 5533 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 5534 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 5535 5536 req1->stage = stage; 5537 req1->xy_sel = sel_x ? 1 : 0; 5538 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0); 5539 req1->index = cpu_to_le32(loc); 5540 req1->entry_vld = sel_x ? is_add : 0; 5541 5542 if (key) { 5543 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data)); 5544 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)], 5545 sizeof(req2->tcam_data)); 5546 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) + 5547 sizeof(req2->tcam_data)], sizeof(req3->tcam_data)); 5548 } 5549 5550 ret = hclge_cmd_send(&hdev->hw, desc, 3); 5551 if (ret) 5552 dev_err(&hdev->pdev->dev, 5553 "config tcam key fail, ret=%d\n", 5554 ret); 5555 5556 return ret; 5557 } 5558 5559 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc, 5560 struct hclge_fd_ad_data *action) 5561 { 5562 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 5563 struct hclge_fd_ad_config_cmd *req; 5564 struct hclge_desc desc; 5565 u64 ad_data = 0; 5566 int ret; 5567 5568 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false); 5569 5570 req = (struct hclge_fd_ad_config_cmd *)desc.data; 5571 req->index = cpu_to_le32(loc); 5572 req->stage = stage; 5573 5574 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B, 5575 action->write_rule_id_to_bd); 5576 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S, 5577 action->rule_id); 5578 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) { 5579 hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B, 5580 action->override_tc); 5581 hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M, 5582 HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size); 5583 } 5584 ad_data <<= 32; 5585 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet); 5586 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B, 5587 action->forward_to_direct_queue); 5588 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S, 5589 action->queue_id); 5590 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter); 5591 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M, 5592 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id); 5593 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage); 5594 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S, 5595 action->counter_id); 5596 5597 req->ad_data = cpu_to_le64(ad_data); 5598 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5599 if (ret) 5600 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret); 5601 5602 return ret; 5603 } 5604 5605 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y, 5606 struct hclge_fd_rule *rule) 5607 { 5608 int offset, moffset, ip_offset; 5609 enum HCLGE_FD_KEY_OPT key_opt; 5610 u16 tmp_x_s, tmp_y_s; 5611 u32 tmp_x_l, tmp_y_l; 5612 u8 *p = (u8 *)rule; 5613 int i; 5614 5615 if (rule->unused_tuple & BIT(tuple_bit)) 5616 return true; 5617 5618 key_opt = tuple_key_info[tuple_bit].key_opt; 5619 offset = tuple_key_info[tuple_bit].offset; 5620 moffset = tuple_key_info[tuple_bit].moffset; 5621 5622 switch (key_opt) { 5623 case KEY_OPT_U8: 5624 calc_x(*key_x, p[offset], p[moffset]); 5625 calc_y(*key_y, p[offset], p[moffset]); 5626 5627 return true; 5628 case KEY_OPT_LE16: 5629 calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5630 calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5631 *(__le16 *)key_x = cpu_to_le16(tmp_x_s); 5632 *(__le16 *)key_y = cpu_to_le16(tmp_y_s); 5633 5634 return true; 5635 case KEY_OPT_LE32: 5636 calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5637 calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5638 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5639 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5640 5641 return true; 5642 case KEY_OPT_MAC: 5643 for (i = 0; i < ETH_ALEN; i++) { 5644 calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i], 5645 p[moffset + i]); 5646 calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i], 5647 p[moffset + i]); 5648 } 5649 5650 return true; 5651 case KEY_OPT_IP: 5652 ip_offset = IPV4_INDEX * sizeof(u32); 5653 calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]), 5654 *(u32 *)(&p[moffset + ip_offset])); 5655 calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]), 5656 *(u32 *)(&p[moffset + ip_offset])); 5657 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5658 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5659 5660 return true; 5661 default: 5662 return false; 5663 } 5664 } 5665 5666 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 5667 u8 vf_id, u8 network_port_id) 5668 { 5669 u32 port_number = 0; 5670 5671 if (port_type == HOST_PORT) { 5672 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S, 5673 pf_id); 5674 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S, 5675 vf_id); 5676 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT); 5677 } else { 5678 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M, 5679 HCLGE_NETWORK_PORT_ID_S, network_port_id); 5680 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT); 5681 } 5682 5683 return port_number; 5684 } 5685 5686 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg, 5687 __le32 *key_x, __le32 *key_y, 5688 struct hclge_fd_rule *rule) 5689 { 5690 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number; 5691 u8 cur_pos = 0, tuple_size, shift_bits; 5692 unsigned int i; 5693 5694 for (i = 0; i < MAX_META_DATA; i++) { 5695 tuple_size = meta_data_key_info[i].key_length; 5696 tuple_bit = key_cfg->meta_data_active & BIT(i); 5697 5698 switch (tuple_bit) { 5699 case BIT(ROCE_TYPE): 5700 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET); 5701 cur_pos += tuple_size; 5702 break; 5703 case BIT(DST_VPORT): 5704 port_number = hclge_get_port_number(HOST_PORT, 0, 5705 rule->vf_id, 0); 5706 hnae3_set_field(meta_data, 5707 GENMASK(cur_pos + tuple_size, cur_pos), 5708 cur_pos, port_number); 5709 cur_pos += tuple_size; 5710 break; 5711 default: 5712 break; 5713 } 5714 } 5715 5716 calc_x(tmp_x, meta_data, 0xFFFFFFFF); 5717 calc_y(tmp_y, meta_data, 0xFFFFFFFF); 5718 shift_bits = sizeof(meta_data) * 8 - cur_pos; 5719 5720 *key_x = cpu_to_le32(tmp_x << shift_bits); 5721 *key_y = cpu_to_le32(tmp_y << shift_bits); 5722 } 5723 5724 /* A complete key is combined with meta data key and tuple key. 5725 * Meta data key is stored at the MSB region, and tuple key is stored at 5726 * the LSB region, unused bits will be filled 0. 5727 */ 5728 static int hclge_config_key(struct hclge_dev *hdev, u8 stage, 5729 struct hclge_fd_rule *rule) 5730 { 5731 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage]; 5732 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES]; 5733 u8 *cur_key_x, *cur_key_y; 5734 u8 meta_data_region; 5735 u8 tuple_size; 5736 int ret; 5737 u32 i; 5738 5739 memset(key_x, 0, sizeof(key_x)); 5740 memset(key_y, 0, sizeof(key_y)); 5741 cur_key_x = key_x; 5742 cur_key_y = key_y; 5743 5744 for (i = 0; i < MAX_TUPLE; i++) { 5745 bool tuple_valid; 5746 5747 tuple_size = tuple_key_info[i].key_length / 8; 5748 if (!(key_cfg->tuple_active & BIT(i))) 5749 continue; 5750 5751 tuple_valid = hclge_fd_convert_tuple(i, cur_key_x, 5752 cur_key_y, rule); 5753 if (tuple_valid) { 5754 cur_key_x += tuple_size; 5755 cur_key_y += tuple_size; 5756 } 5757 } 5758 5759 meta_data_region = hdev->fd_cfg.max_key_length / 8 - 5760 MAX_META_DATA_LENGTH / 8; 5761 5762 hclge_fd_convert_meta_data(key_cfg, 5763 (__le32 *)(key_x + meta_data_region), 5764 (__le32 *)(key_y + meta_data_region), 5765 rule); 5766 5767 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y, 5768 true); 5769 if (ret) { 5770 dev_err(&hdev->pdev->dev, 5771 "fd key_y config fail, loc=%u, ret=%d\n", 5772 rule->queue_id, ret); 5773 return ret; 5774 } 5775 5776 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x, 5777 true); 5778 if (ret) 5779 dev_err(&hdev->pdev->dev, 5780 "fd key_x config fail, loc=%u, ret=%d\n", 5781 rule->queue_id, ret); 5782 return ret; 5783 } 5784 5785 static int hclge_config_action(struct hclge_dev *hdev, u8 stage, 5786 struct hclge_fd_rule *rule) 5787 { 5788 struct hclge_vport *vport = hdev->vport; 5789 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5790 struct hclge_fd_ad_data ad_data; 5791 5792 memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data)); 5793 ad_data.ad_id = rule->location; 5794 5795 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 5796 ad_data.drop_packet = true; 5797 } else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) { 5798 ad_data.override_tc = true; 5799 ad_data.queue_id = 5800 kinfo->tc_info.tqp_offset[rule->cls_flower.tc]; 5801 ad_data.tc_size = 5802 ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]); 5803 } else { 5804 ad_data.forward_to_direct_queue = true; 5805 ad_data.queue_id = rule->queue_id; 5806 } 5807 5808 if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) { 5809 ad_data.use_counter = true; 5810 ad_data.counter_id = rule->vf_id % 5811 hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]; 5812 } else { 5813 ad_data.use_counter = false; 5814 ad_data.counter_id = 0; 5815 } 5816 5817 ad_data.use_next_stage = false; 5818 ad_data.next_input_key = 0; 5819 5820 ad_data.write_rule_id_to_bd = true; 5821 ad_data.rule_id = rule->location; 5822 5823 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data); 5824 } 5825 5826 static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec, 5827 u32 *unused_tuple) 5828 { 5829 if (!spec || !unused_tuple) 5830 return -EINVAL; 5831 5832 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5833 5834 if (!spec->ip4src) 5835 *unused_tuple |= BIT(INNER_SRC_IP); 5836 5837 if (!spec->ip4dst) 5838 *unused_tuple |= BIT(INNER_DST_IP); 5839 5840 if (!spec->psrc) 5841 *unused_tuple |= BIT(INNER_SRC_PORT); 5842 5843 if (!spec->pdst) 5844 *unused_tuple |= BIT(INNER_DST_PORT); 5845 5846 if (!spec->tos) 5847 *unused_tuple |= BIT(INNER_IP_TOS); 5848 5849 return 0; 5850 } 5851 5852 static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec, 5853 u32 *unused_tuple) 5854 { 5855 if (!spec || !unused_tuple) 5856 return -EINVAL; 5857 5858 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5859 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5860 5861 if (!spec->ip4src) 5862 *unused_tuple |= BIT(INNER_SRC_IP); 5863 5864 if (!spec->ip4dst) 5865 *unused_tuple |= BIT(INNER_DST_IP); 5866 5867 if (!spec->tos) 5868 *unused_tuple |= BIT(INNER_IP_TOS); 5869 5870 if (!spec->proto) 5871 *unused_tuple |= BIT(INNER_IP_PROTO); 5872 5873 if (spec->l4_4_bytes) 5874 return -EOPNOTSUPP; 5875 5876 if (spec->ip_ver != ETH_RX_NFC_IP4) 5877 return -EOPNOTSUPP; 5878 5879 return 0; 5880 } 5881 5882 static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec, 5883 u32 *unused_tuple) 5884 { 5885 if (!spec || !unused_tuple) 5886 return -EINVAL; 5887 5888 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5889 5890 /* check whether src/dst ip address used */ 5891 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5892 *unused_tuple |= BIT(INNER_SRC_IP); 5893 5894 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5895 *unused_tuple |= BIT(INNER_DST_IP); 5896 5897 if (!spec->psrc) 5898 *unused_tuple |= BIT(INNER_SRC_PORT); 5899 5900 if (!spec->pdst) 5901 *unused_tuple |= BIT(INNER_DST_PORT); 5902 5903 if (!spec->tclass) 5904 *unused_tuple |= BIT(INNER_IP_TOS); 5905 5906 return 0; 5907 } 5908 5909 static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec, 5910 u32 *unused_tuple) 5911 { 5912 if (!spec || !unused_tuple) 5913 return -EINVAL; 5914 5915 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5916 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5917 5918 /* check whether src/dst ip address used */ 5919 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5920 *unused_tuple |= BIT(INNER_SRC_IP); 5921 5922 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5923 *unused_tuple |= BIT(INNER_DST_IP); 5924 5925 if (!spec->l4_proto) 5926 *unused_tuple |= BIT(INNER_IP_PROTO); 5927 5928 if (!spec->tclass) 5929 *unused_tuple |= BIT(INNER_IP_TOS); 5930 5931 if (spec->l4_4_bytes) 5932 return -EOPNOTSUPP; 5933 5934 return 0; 5935 } 5936 5937 static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple) 5938 { 5939 if (!spec || !unused_tuple) 5940 return -EINVAL; 5941 5942 *unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5943 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) | 5944 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO); 5945 5946 if (is_zero_ether_addr(spec->h_source)) 5947 *unused_tuple |= BIT(INNER_SRC_MAC); 5948 5949 if (is_zero_ether_addr(spec->h_dest)) 5950 *unused_tuple |= BIT(INNER_DST_MAC); 5951 5952 if (!spec->h_proto) 5953 *unused_tuple |= BIT(INNER_ETH_TYPE); 5954 5955 return 0; 5956 } 5957 5958 static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev, 5959 struct ethtool_rx_flow_spec *fs, 5960 u32 *unused_tuple) 5961 { 5962 if (fs->flow_type & FLOW_EXT) { 5963 if (fs->h_ext.vlan_etype) { 5964 dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n"); 5965 return -EOPNOTSUPP; 5966 } 5967 5968 if (!fs->h_ext.vlan_tci) 5969 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 5970 5971 if (fs->m_ext.vlan_tci && 5972 be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) { 5973 dev_err(&hdev->pdev->dev, 5974 "failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n", 5975 ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1); 5976 return -EINVAL; 5977 } 5978 } else { 5979 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 5980 } 5981 5982 if (fs->flow_type & FLOW_MAC_EXT) { 5983 if (hdev->fd_cfg.fd_mode != 5984 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 5985 dev_err(&hdev->pdev->dev, 5986 "FLOW_MAC_EXT is not supported in current fd mode!\n"); 5987 return -EOPNOTSUPP; 5988 } 5989 5990 if (is_zero_ether_addr(fs->h_ext.h_dest)) 5991 *unused_tuple |= BIT(INNER_DST_MAC); 5992 else 5993 *unused_tuple &= ~BIT(INNER_DST_MAC); 5994 } 5995 5996 return 0; 5997 } 5998 5999 static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple, 6000 struct hclge_fd_user_def_info *info) 6001 { 6002 switch (flow_type) { 6003 case ETHER_FLOW: 6004 info->layer = HCLGE_FD_USER_DEF_L2; 6005 *unused_tuple &= ~BIT(INNER_L2_RSV); 6006 break; 6007 case IP_USER_FLOW: 6008 case IPV6_USER_FLOW: 6009 info->layer = HCLGE_FD_USER_DEF_L3; 6010 *unused_tuple &= ~BIT(INNER_L3_RSV); 6011 break; 6012 case TCP_V4_FLOW: 6013 case UDP_V4_FLOW: 6014 case TCP_V6_FLOW: 6015 case UDP_V6_FLOW: 6016 info->layer = HCLGE_FD_USER_DEF_L4; 6017 *unused_tuple &= ~BIT(INNER_L4_RSV); 6018 break; 6019 default: 6020 return -EOPNOTSUPP; 6021 } 6022 6023 return 0; 6024 } 6025 6026 static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs) 6027 { 6028 return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0; 6029 } 6030 6031 static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev, 6032 struct ethtool_rx_flow_spec *fs, 6033 u32 *unused_tuple, 6034 struct hclge_fd_user_def_info *info) 6035 { 6036 u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active; 6037 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6038 u16 data, offset, data_mask, offset_mask; 6039 int ret; 6040 6041 info->layer = HCLGE_FD_USER_DEF_NONE; 6042 *unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 6043 6044 if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs)) 6045 return 0; 6046 6047 /* user-def data from ethtool is 64 bit value, the bit0~15 is used 6048 * for data, and bit32~47 is used for offset. 6049 */ 6050 data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6051 data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6052 offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6053 offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6054 6055 if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) { 6056 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n"); 6057 return -EOPNOTSUPP; 6058 } 6059 6060 if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) { 6061 dev_err(&hdev->pdev->dev, 6062 "user-def offset[%u] should be no more than %u\n", 6063 offset, HCLGE_FD_MAX_USER_DEF_OFFSET); 6064 return -EINVAL; 6065 } 6066 6067 if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) { 6068 dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n"); 6069 return -EINVAL; 6070 } 6071 6072 ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info); 6073 if (ret) { 6074 dev_err(&hdev->pdev->dev, 6075 "unsupported flow type for user-def bytes, ret = %d\n", 6076 ret); 6077 return ret; 6078 } 6079 6080 info->data = data; 6081 info->data_mask = data_mask; 6082 info->offset = offset; 6083 6084 return 0; 6085 } 6086 6087 static int hclge_fd_check_spec(struct hclge_dev *hdev, 6088 struct ethtool_rx_flow_spec *fs, 6089 u32 *unused_tuple, 6090 struct hclge_fd_user_def_info *info) 6091 { 6092 u32 flow_type; 6093 int ret; 6094 6095 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 6096 dev_err(&hdev->pdev->dev, 6097 "failed to config fd rules, invalid rule location: %u, max is %u\n.", 6098 fs->location, 6099 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1); 6100 return -EINVAL; 6101 } 6102 6103 ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info); 6104 if (ret) 6105 return ret; 6106 6107 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6108 switch (flow_type) { 6109 case SCTP_V4_FLOW: 6110 case TCP_V4_FLOW: 6111 case UDP_V4_FLOW: 6112 ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec, 6113 unused_tuple); 6114 break; 6115 case IP_USER_FLOW: 6116 ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec, 6117 unused_tuple); 6118 break; 6119 case SCTP_V6_FLOW: 6120 case TCP_V6_FLOW: 6121 case UDP_V6_FLOW: 6122 ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec, 6123 unused_tuple); 6124 break; 6125 case IPV6_USER_FLOW: 6126 ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec, 6127 unused_tuple); 6128 break; 6129 case ETHER_FLOW: 6130 if (hdev->fd_cfg.fd_mode != 6131 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6132 dev_err(&hdev->pdev->dev, 6133 "ETHER_FLOW is not supported in current fd mode!\n"); 6134 return -EOPNOTSUPP; 6135 } 6136 6137 ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec, 6138 unused_tuple); 6139 break; 6140 default: 6141 dev_err(&hdev->pdev->dev, 6142 "unsupported protocol type, protocol type = %#x\n", 6143 flow_type); 6144 return -EOPNOTSUPP; 6145 } 6146 6147 if (ret) { 6148 dev_err(&hdev->pdev->dev, 6149 "failed to check flow union tuple, ret = %d\n", 6150 ret); 6151 return ret; 6152 } 6153 6154 return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple); 6155 } 6156 6157 static void hclge_fd_get_tcpip4_tuple(struct ethtool_rx_flow_spec *fs, 6158 struct hclge_fd_rule *rule, u8 ip_proto) 6159 { 6160 rule->tuples.src_ip[IPV4_INDEX] = 6161 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src); 6162 rule->tuples_mask.src_ip[IPV4_INDEX] = 6163 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src); 6164 6165 rule->tuples.dst_ip[IPV4_INDEX] = 6166 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst); 6167 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6168 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst); 6169 6170 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc); 6171 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc); 6172 6173 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst); 6174 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst); 6175 6176 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos; 6177 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos; 6178 6179 rule->tuples.ether_proto = ETH_P_IP; 6180 rule->tuples_mask.ether_proto = 0xFFFF; 6181 6182 rule->tuples.ip_proto = ip_proto; 6183 rule->tuples_mask.ip_proto = 0xFF; 6184 } 6185 6186 static void hclge_fd_get_ip4_tuple(struct ethtool_rx_flow_spec *fs, 6187 struct hclge_fd_rule *rule) 6188 { 6189 rule->tuples.src_ip[IPV4_INDEX] = 6190 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src); 6191 rule->tuples_mask.src_ip[IPV4_INDEX] = 6192 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src); 6193 6194 rule->tuples.dst_ip[IPV4_INDEX] = 6195 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst); 6196 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6197 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst); 6198 6199 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos; 6200 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos; 6201 6202 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto; 6203 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto; 6204 6205 rule->tuples.ether_proto = ETH_P_IP; 6206 rule->tuples_mask.ether_proto = 0xFFFF; 6207 } 6208 6209 static void hclge_fd_get_tcpip6_tuple(struct ethtool_rx_flow_spec *fs, 6210 struct hclge_fd_rule *rule, u8 ip_proto) 6211 { 6212 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.tcp_ip6_spec.ip6src, 6213 IPV6_SIZE); 6214 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.tcp_ip6_spec.ip6src, 6215 IPV6_SIZE); 6216 6217 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.tcp_ip6_spec.ip6dst, 6218 IPV6_SIZE); 6219 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.tcp_ip6_spec.ip6dst, 6220 IPV6_SIZE); 6221 6222 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc); 6223 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc); 6224 6225 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst); 6226 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst); 6227 6228 rule->tuples.ether_proto = ETH_P_IPV6; 6229 rule->tuples_mask.ether_proto = 0xFFFF; 6230 6231 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6232 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6233 6234 rule->tuples.ip_proto = ip_proto; 6235 rule->tuples_mask.ip_proto = 0xFF; 6236 } 6237 6238 static void hclge_fd_get_ip6_tuple(struct ethtool_rx_flow_spec *fs, 6239 struct hclge_fd_rule *rule) 6240 { 6241 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.usr_ip6_spec.ip6src, 6242 IPV6_SIZE); 6243 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.usr_ip6_spec.ip6src, 6244 IPV6_SIZE); 6245 6246 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.usr_ip6_spec.ip6dst, 6247 IPV6_SIZE); 6248 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.usr_ip6_spec.ip6dst, 6249 IPV6_SIZE); 6250 6251 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto; 6252 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto; 6253 6254 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6255 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6256 6257 rule->tuples.ether_proto = ETH_P_IPV6; 6258 rule->tuples_mask.ether_proto = 0xFFFF; 6259 } 6260 6261 static void hclge_fd_get_ether_tuple(struct ethtool_rx_flow_spec *fs, 6262 struct hclge_fd_rule *rule) 6263 { 6264 ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source); 6265 ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source); 6266 6267 ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest); 6268 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest); 6269 6270 rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto); 6271 rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto); 6272 } 6273 6274 static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info, 6275 struct hclge_fd_rule *rule) 6276 { 6277 switch (info->layer) { 6278 case HCLGE_FD_USER_DEF_L2: 6279 rule->tuples.l2_user_def = info->data; 6280 rule->tuples_mask.l2_user_def = info->data_mask; 6281 break; 6282 case HCLGE_FD_USER_DEF_L3: 6283 rule->tuples.l3_user_def = info->data; 6284 rule->tuples_mask.l3_user_def = info->data_mask; 6285 break; 6286 case HCLGE_FD_USER_DEF_L4: 6287 rule->tuples.l4_user_def = (u32)info->data << 16; 6288 rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16; 6289 break; 6290 default: 6291 break; 6292 } 6293 6294 rule->ep.user_def = *info; 6295 } 6296 6297 static int hclge_fd_get_tuple(struct ethtool_rx_flow_spec *fs, 6298 struct hclge_fd_rule *rule, 6299 struct hclge_fd_user_def_info *info) 6300 { 6301 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6302 6303 switch (flow_type) { 6304 case SCTP_V4_FLOW: 6305 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_SCTP); 6306 break; 6307 case TCP_V4_FLOW: 6308 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_TCP); 6309 break; 6310 case UDP_V4_FLOW: 6311 hclge_fd_get_tcpip4_tuple(fs, rule, IPPROTO_UDP); 6312 break; 6313 case IP_USER_FLOW: 6314 hclge_fd_get_ip4_tuple(fs, rule); 6315 break; 6316 case SCTP_V6_FLOW: 6317 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_SCTP); 6318 break; 6319 case TCP_V6_FLOW: 6320 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_TCP); 6321 break; 6322 case UDP_V6_FLOW: 6323 hclge_fd_get_tcpip6_tuple(fs, rule, IPPROTO_UDP); 6324 break; 6325 case IPV6_USER_FLOW: 6326 hclge_fd_get_ip6_tuple(fs, rule); 6327 break; 6328 case ETHER_FLOW: 6329 hclge_fd_get_ether_tuple(fs, rule); 6330 break; 6331 default: 6332 return -EOPNOTSUPP; 6333 } 6334 6335 if (fs->flow_type & FLOW_EXT) { 6336 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci); 6337 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci); 6338 hclge_fd_get_user_def_tuple(info, rule); 6339 } 6340 6341 if (fs->flow_type & FLOW_MAC_EXT) { 6342 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest); 6343 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest); 6344 } 6345 6346 return 0; 6347 } 6348 6349 static int hclge_fd_config_rule(struct hclge_dev *hdev, 6350 struct hclge_fd_rule *rule) 6351 { 6352 int ret; 6353 6354 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule); 6355 if (ret) 6356 return ret; 6357 6358 return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule); 6359 } 6360 6361 static int hclge_add_fd_entry_common(struct hclge_dev *hdev, 6362 struct hclge_fd_rule *rule) 6363 { 6364 int ret; 6365 6366 spin_lock_bh(&hdev->fd_rule_lock); 6367 6368 if (hdev->fd_active_type != rule->rule_type && 6369 (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6370 hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) { 6371 dev_err(&hdev->pdev->dev, 6372 "mode conflict(new type %d, active type %d), please delete existent rules first\n", 6373 rule->rule_type, hdev->fd_active_type); 6374 spin_unlock_bh(&hdev->fd_rule_lock); 6375 return -EINVAL; 6376 } 6377 6378 ret = hclge_fd_check_user_def_refcnt(hdev, rule); 6379 if (ret) 6380 goto out; 6381 6382 ret = hclge_clear_arfs_rules(hdev); 6383 if (ret) 6384 goto out; 6385 6386 ret = hclge_fd_config_rule(hdev, rule); 6387 if (ret) 6388 goto out; 6389 6390 rule->state = HCLGE_FD_ACTIVE; 6391 hdev->fd_active_type = rule->rule_type; 6392 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 6393 6394 out: 6395 spin_unlock_bh(&hdev->fd_rule_lock); 6396 return ret; 6397 } 6398 6399 static bool hclge_is_cls_flower_active(struct hnae3_handle *handle) 6400 { 6401 struct hclge_vport *vport = hclge_get_vport(handle); 6402 struct hclge_dev *hdev = vport->back; 6403 6404 return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE; 6405 } 6406 6407 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie, 6408 u16 *vport_id, u8 *action, u16 *queue_id) 6409 { 6410 struct hclge_vport *vport = hdev->vport; 6411 6412 if (ring_cookie == RX_CLS_FLOW_DISC) { 6413 *action = HCLGE_FD_ACTION_DROP_PACKET; 6414 } else { 6415 u32 ring = ethtool_get_flow_spec_ring(ring_cookie); 6416 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie); 6417 u16 tqps; 6418 6419 /* To keep consistent with user's configuration, minus 1 when 6420 * printing 'vf', because vf id from ethtool is added 1 for vf. 6421 */ 6422 if (vf > hdev->num_req_vfs) { 6423 dev_err(&hdev->pdev->dev, 6424 "Error: vf id (%u) should be less than %u\n", 6425 vf - 1U, hdev->num_req_vfs); 6426 return -EINVAL; 6427 } 6428 6429 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id; 6430 tqps = hdev->vport[vf].nic.kinfo.num_tqps; 6431 6432 if (ring >= tqps) { 6433 dev_err(&hdev->pdev->dev, 6434 "Error: queue id (%u) > max tqp num (%u)\n", 6435 ring, tqps - 1U); 6436 return -EINVAL; 6437 } 6438 6439 *action = HCLGE_FD_ACTION_SELECT_QUEUE; 6440 *queue_id = ring; 6441 } 6442 6443 return 0; 6444 } 6445 6446 static int hclge_add_fd_entry(struct hnae3_handle *handle, 6447 struct ethtool_rxnfc *cmd) 6448 { 6449 struct hclge_vport *vport = hclge_get_vport(handle); 6450 struct hclge_dev *hdev = vport->back; 6451 struct hclge_fd_user_def_info info; 6452 u16 dst_vport_id = 0, q_index = 0; 6453 struct ethtool_rx_flow_spec *fs; 6454 struct hclge_fd_rule *rule; 6455 u32 unused = 0; 6456 u8 action; 6457 int ret; 6458 6459 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 6460 dev_err(&hdev->pdev->dev, 6461 "flow table director is not supported\n"); 6462 return -EOPNOTSUPP; 6463 } 6464 6465 if (!hdev->fd_en) { 6466 dev_err(&hdev->pdev->dev, 6467 "please enable flow director first\n"); 6468 return -EOPNOTSUPP; 6469 } 6470 6471 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6472 6473 ret = hclge_fd_check_spec(hdev, fs, &unused, &info); 6474 if (ret) 6475 return ret; 6476 6477 ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id, 6478 &action, &q_index); 6479 if (ret) 6480 return ret; 6481 6482 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 6483 if (!rule) 6484 return -ENOMEM; 6485 6486 ret = hclge_fd_get_tuple(fs, rule, &info); 6487 if (ret) { 6488 kfree(rule); 6489 return ret; 6490 } 6491 6492 rule->flow_type = fs->flow_type; 6493 rule->location = fs->location; 6494 rule->unused_tuple = unused; 6495 rule->vf_id = dst_vport_id; 6496 rule->queue_id = q_index; 6497 rule->action = action; 6498 rule->rule_type = HCLGE_FD_EP_ACTIVE; 6499 6500 ret = hclge_add_fd_entry_common(hdev, rule); 6501 if (ret) 6502 kfree(rule); 6503 6504 return ret; 6505 } 6506 6507 static int hclge_del_fd_entry(struct hnae3_handle *handle, 6508 struct ethtool_rxnfc *cmd) 6509 { 6510 struct hclge_vport *vport = hclge_get_vport(handle); 6511 struct hclge_dev *hdev = vport->back; 6512 struct ethtool_rx_flow_spec *fs; 6513 int ret; 6514 6515 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6516 return -EOPNOTSUPP; 6517 6518 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6519 6520 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6521 return -EINVAL; 6522 6523 spin_lock_bh(&hdev->fd_rule_lock); 6524 if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6525 !test_bit(fs->location, hdev->fd_bmap)) { 6526 dev_err(&hdev->pdev->dev, 6527 "Delete fail, rule %u is inexistent\n", fs->location); 6528 spin_unlock_bh(&hdev->fd_rule_lock); 6529 return -ENOENT; 6530 } 6531 6532 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location, 6533 NULL, false); 6534 if (ret) 6535 goto out; 6536 6537 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL); 6538 6539 out: 6540 spin_unlock_bh(&hdev->fd_rule_lock); 6541 return ret; 6542 } 6543 6544 static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev, 6545 bool clear_list) 6546 { 6547 struct hclge_fd_rule *rule; 6548 struct hlist_node *node; 6549 u16 location; 6550 6551 spin_lock_bh(&hdev->fd_rule_lock); 6552 6553 for_each_set_bit(location, hdev->fd_bmap, 6554 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6555 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location, 6556 NULL, false); 6557 6558 if (clear_list) { 6559 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, 6560 rule_node) { 6561 hlist_del(&rule->rule_node); 6562 kfree(rule); 6563 } 6564 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 6565 hdev->hclge_fd_rule_num = 0; 6566 bitmap_zero(hdev->fd_bmap, 6567 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 6568 } 6569 6570 spin_unlock_bh(&hdev->fd_rule_lock); 6571 } 6572 6573 static void hclge_del_all_fd_entries(struct hclge_dev *hdev) 6574 { 6575 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6576 return; 6577 6578 hclge_clear_fd_rules_in_list(hdev, true); 6579 hclge_fd_disable_user_def(hdev); 6580 } 6581 6582 static int hclge_restore_fd_entries(struct hnae3_handle *handle) 6583 { 6584 struct hclge_vport *vport = hclge_get_vport(handle); 6585 struct hclge_dev *hdev = vport->back; 6586 struct hclge_fd_rule *rule; 6587 struct hlist_node *node; 6588 6589 /* Return ok here, because reset error handling will check this 6590 * return value. If error is returned here, the reset process will 6591 * fail. 6592 */ 6593 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6594 return 0; 6595 6596 /* if fd is disabled, should not restore it when reset */ 6597 if (!hdev->fd_en) 6598 return 0; 6599 6600 spin_lock_bh(&hdev->fd_rule_lock); 6601 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6602 if (rule->state == HCLGE_FD_ACTIVE) 6603 rule->state = HCLGE_FD_TO_ADD; 6604 } 6605 spin_unlock_bh(&hdev->fd_rule_lock); 6606 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 6607 6608 return 0; 6609 } 6610 6611 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle, 6612 struct ethtool_rxnfc *cmd) 6613 { 6614 struct hclge_vport *vport = hclge_get_vport(handle); 6615 struct hclge_dev *hdev = vport->back; 6616 6617 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev) || hclge_is_cls_flower_active(handle)) 6618 return -EOPNOTSUPP; 6619 6620 cmd->rule_cnt = hdev->hclge_fd_rule_num; 6621 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6622 6623 return 0; 6624 } 6625 6626 static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule, 6627 struct ethtool_tcpip4_spec *spec, 6628 struct ethtool_tcpip4_spec *spec_mask) 6629 { 6630 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6631 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6632 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6633 6634 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6635 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6636 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6637 6638 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6639 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6640 0 : cpu_to_be16(rule->tuples_mask.src_port); 6641 6642 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6643 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6644 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6645 6646 spec->tos = rule->tuples.ip_tos; 6647 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6648 0 : rule->tuples_mask.ip_tos; 6649 } 6650 6651 static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule, 6652 struct ethtool_usrip4_spec *spec, 6653 struct ethtool_usrip4_spec *spec_mask) 6654 { 6655 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6656 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6657 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6658 6659 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6660 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6661 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6662 6663 spec->tos = rule->tuples.ip_tos; 6664 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6665 0 : rule->tuples_mask.ip_tos; 6666 6667 spec->proto = rule->tuples.ip_proto; 6668 spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6669 0 : rule->tuples_mask.ip_proto; 6670 6671 spec->ip_ver = ETH_RX_NFC_IP4; 6672 } 6673 6674 static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule, 6675 struct ethtool_tcpip6_spec *spec, 6676 struct ethtool_tcpip6_spec *spec_mask) 6677 { 6678 cpu_to_be32_array(spec->ip6src, 6679 rule->tuples.src_ip, IPV6_SIZE); 6680 cpu_to_be32_array(spec->ip6dst, 6681 rule->tuples.dst_ip, IPV6_SIZE); 6682 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6683 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6684 else 6685 cpu_to_be32_array(spec_mask->ip6src, rule->tuples_mask.src_ip, 6686 IPV6_SIZE); 6687 6688 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6689 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6690 else 6691 cpu_to_be32_array(spec_mask->ip6dst, rule->tuples_mask.dst_ip, 6692 IPV6_SIZE); 6693 6694 spec->tclass = rule->tuples.ip_tos; 6695 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6696 0 : rule->tuples_mask.ip_tos; 6697 6698 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6699 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6700 0 : cpu_to_be16(rule->tuples_mask.src_port); 6701 6702 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6703 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6704 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6705 } 6706 6707 static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule, 6708 struct ethtool_usrip6_spec *spec, 6709 struct ethtool_usrip6_spec *spec_mask) 6710 { 6711 cpu_to_be32_array(spec->ip6src, rule->tuples.src_ip, IPV6_SIZE); 6712 cpu_to_be32_array(spec->ip6dst, rule->tuples.dst_ip, IPV6_SIZE); 6713 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6714 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6715 else 6716 cpu_to_be32_array(spec_mask->ip6src, 6717 rule->tuples_mask.src_ip, IPV6_SIZE); 6718 6719 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6720 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6721 else 6722 cpu_to_be32_array(spec_mask->ip6dst, 6723 rule->tuples_mask.dst_ip, IPV6_SIZE); 6724 6725 spec->tclass = rule->tuples.ip_tos; 6726 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6727 0 : rule->tuples_mask.ip_tos; 6728 6729 spec->l4_proto = rule->tuples.ip_proto; 6730 spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6731 0 : rule->tuples_mask.ip_proto; 6732 } 6733 6734 static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule, 6735 struct ethhdr *spec, 6736 struct ethhdr *spec_mask) 6737 { 6738 ether_addr_copy(spec->h_source, rule->tuples.src_mac); 6739 ether_addr_copy(spec->h_dest, rule->tuples.dst_mac); 6740 6741 if (rule->unused_tuple & BIT(INNER_SRC_MAC)) 6742 eth_zero_addr(spec_mask->h_source); 6743 else 6744 ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac); 6745 6746 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6747 eth_zero_addr(spec_mask->h_dest); 6748 else 6749 ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac); 6750 6751 spec->h_proto = cpu_to_be16(rule->tuples.ether_proto); 6752 spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ? 6753 0 : cpu_to_be16(rule->tuples_mask.ether_proto); 6754 } 6755 6756 static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs, 6757 struct hclge_fd_rule *rule) 6758 { 6759 if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) == 6760 HCLGE_FD_TUPLE_USER_DEF_TUPLES) { 6761 fs->h_ext.data[0] = 0; 6762 fs->h_ext.data[1] = 0; 6763 fs->m_ext.data[0] = 0; 6764 fs->m_ext.data[1] = 0; 6765 } else { 6766 fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset); 6767 fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data); 6768 fs->m_ext.data[0] = 6769 cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK); 6770 fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask); 6771 } 6772 } 6773 6774 static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs, 6775 struct hclge_fd_rule *rule) 6776 { 6777 if (fs->flow_type & FLOW_EXT) { 6778 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1); 6779 fs->m_ext.vlan_tci = 6780 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ? 6781 0 : cpu_to_be16(rule->tuples_mask.vlan_tag1); 6782 6783 hclge_fd_get_user_def_info(fs, rule); 6784 } 6785 6786 if (fs->flow_type & FLOW_MAC_EXT) { 6787 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac); 6788 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6789 eth_zero_addr(fs->m_u.ether_spec.h_dest); 6790 else 6791 ether_addr_copy(fs->m_u.ether_spec.h_dest, 6792 rule->tuples_mask.dst_mac); 6793 } 6794 } 6795 6796 static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev, 6797 u16 location) 6798 { 6799 struct hclge_fd_rule *rule = NULL; 6800 struct hlist_node *node2; 6801 6802 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) { 6803 if (rule->location == location) 6804 return rule; 6805 else if (rule->location > location) 6806 return NULL; 6807 } 6808 6809 return NULL; 6810 } 6811 6812 static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs, 6813 struct hclge_fd_rule *rule) 6814 { 6815 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 6816 fs->ring_cookie = RX_CLS_FLOW_DISC; 6817 } else { 6818 u64 vf_id; 6819 6820 fs->ring_cookie = rule->queue_id; 6821 vf_id = rule->vf_id; 6822 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 6823 fs->ring_cookie |= vf_id; 6824 } 6825 } 6826 6827 static int hclge_get_fd_rule_info(struct hnae3_handle *handle, 6828 struct ethtool_rxnfc *cmd) 6829 { 6830 struct hclge_vport *vport = hclge_get_vport(handle); 6831 struct hclge_fd_rule *rule = NULL; 6832 struct hclge_dev *hdev = vport->back; 6833 struct ethtool_rx_flow_spec *fs; 6834 6835 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6836 return -EOPNOTSUPP; 6837 6838 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6839 6840 spin_lock_bh(&hdev->fd_rule_lock); 6841 6842 rule = hclge_get_fd_rule(hdev, fs->location); 6843 if (!rule) { 6844 spin_unlock_bh(&hdev->fd_rule_lock); 6845 return -ENOENT; 6846 } 6847 6848 fs->flow_type = rule->flow_type; 6849 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 6850 case SCTP_V4_FLOW: 6851 case TCP_V4_FLOW: 6852 case UDP_V4_FLOW: 6853 hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec, 6854 &fs->m_u.tcp_ip4_spec); 6855 break; 6856 case IP_USER_FLOW: 6857 hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec, 6858 &fs->m_u.usr_ip4_spec); 6859 break; 6860 case SCTP_V6_FLOW: 6861 case TCP_V6_FLOW: 6862 case UDP_V6_FLOW: 6863 hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec, 6864 &fs->m_u.tcp_ip6_spec); 6865 break; 6866 case IPV6_USER_FLOW: 6867 hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec, 6868 &fs->m_u.usr_ip6_spec); 6869 break; 6870 /* The flow type of fd rule has been checked before adding in to rule 6871 * list. As other flow types have been handled, it must be ETHER_FLOW 6872 * for the default case 6873 */ 6874 default: 6875 hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec, 6876 &fs->m_u.ether_spec); 6877 break; 6878 } 6879 6880 hclge_fd_get_ext_info(fs, rule); 6881 6882 hclge_fd_get_ring_cookie(fs, rule); 6883 6884 spin_unlock_bh(&hdev->fd_rule_lock); 6885 6886 return 0; 6887 } 6888 6889 static int hclge_get_all_rules(struct hnae3_handle *handle, 6890 struct ethtool_rxnfc *cmd, u32 *rule_locs) 6891 { 6892 struct hclge_vport *vport = hclge_get_vport(handle); 6893 struct hclge_dev *hdev = vport->back; 6894 struct hclge_fd_rule *rule; 6895 struct hlist_node *node2; 6896 int cnt = 0; 6897 6898 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6899 return -EOPNOTSUPP; 6900 6901 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6902 6903 spin_lock_bh(&hdev->fd_rule_lock); 6904 hlist_for_each_entry_safe(rule, node2, 6905 &hdev->fd_rule_list, rule_node) { 6906 if (cnt == cmd->rule_cnt) { 6907 spin_unlock_bh(&hdev->fd_rule_lock); 6908 return -EMSGSIZE; 6909 } 6910 6911 if (rule->state == HCLGE_FD_TO_DEL) 6912 continue; 6913 6914 rule_locs[cnt] = rule->location; 6915 cnt++; 6916 } 6917 6918 spin_unlock_bh(&hdev->fd_rule_lock); 6919 6920 cmd->rule_cnt = cnt; 6921 6922 return 0; 6923 } 6924 6925 static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys, 6926 struct hclge_fd_rule_tuples *tuples) 6927 { 6928 #define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32 6929 #define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32 6930 6931 tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto); 6932 tuples->ip_proto = fkeys->basic.ip_proto; 6933 tuples->dst_port = be16_to_cpu(fkeys->ports.dst); 6934 6935 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 6936 tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src); 6937 tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst); 6938 } else { 6939 int i; 6940 6941 for (i = 0; i < IPV6_SIZE; i++) { 6942 tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]); 6943 tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]); 6944 } 6945 } 6946 } 6947 6948 /* traverse all rules, check whether an existed rule has the same tuples */ 6949 static struct hclge_fd_rule * 6950 hclge_fd_search_flow_keys(struct hclge_dev *hdev, 6951 const struct hclge_fd_rule_tuples *tuples) 6952 { 6953 struct hclge_fd_rule *rule = NULL; 6954 struct hlist_node *node; 6955 6956 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6957 if (!memcmp(tuples, &rule->tuples, sizeof(*tuples))) 6958 return rule; 6959 } 6960 6961 return NULL; 6962 } 6963 6964 static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples, 6965 struct hclge_fd_rule *rule) 6966 { 6967 rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 6968 BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) | 6969 BIT(INNER_SRC_PORT); 6970 rule->action = 0; 6971 rule->vf_id = 0; 6972 rule->rule_type = HCLGE_FD_ARFS_ACTIVE; 6973 rule->state = HCLGE_FD_TO_ADD; 6974 if (tuples->ether_proto == ETH_P_IP) { 6975 if (tuples->ip_proto == IPPROTO_TCP) 6976 rule->flow_type = TCP_V4_FLOW; 6977 else 6978 rule->flow_type = UDP_V4_FLOW; 6979 } else { 6980 if (tuples->ip_proto == IPPROTO_TCP) 6981 rule->flow_type = TCP_V6_FLOW; 6982 else 6983 rule->flow_type = UDP_V6_FLOW; 6984 } 6985 memcpy(&rule->tuples, tuples, sizeof(rule->tuples)); 6986 memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask)); 6987 } 6988 6989 static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id, 6990 u16 flow_id, struct flow_keys *fkeys) 6991 { 6992 struct hclge_vport *vport = hclge_get_vport(handle); 6993 struct hclge_fd_rule_tuples new_tuples = {}; 6994 struct hclge_dev *hdev = vport->back; 6995 struct hclge_fd_rule *rule; 6996 u16 bit_id; 6997 6998 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6999 return -EOPNOTSUPP; 7000 7001 /* when there is already fd rule existed add by user, 7002 * arfs should not work 7003 */ 7004 spin_lock_bh(&hdev->fd_rule_lock); 7005 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE && 7006 hdev->fd_active_type != HCLGE_FD_RULE_NONE) { 7007 spin_unlock_bh(&hdev->fd_rule_lock); 7008 return -EOPNOTSUPP; 7009 } 7010 7011 hclge_fd_get_flow_tuples(fkeys, &new_tuples); 7012 7013 /* check is there flow director filter existed for this flow, 7014 * if not, create a new filter for it; 7015 * if filter exist with different queue id, modify the filter; 7016 * if filter exist with same queue id, do nothing 7017 */ 7018 rule = hclge_fd_search_flow_keys(hdev, &new_tuples); 7019 if (!rule) { 7020 bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM); 7021 if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7022 spin_unlock_bh(&hdev->fd_rule_lock); 7023 return -ENOSPC; 7024 } 7025 7026 rule = kzalloc(sizeof(*rule), GFP_ATOMIC); 7027 if (!rule) { 7028 spin_unlock_bh(&hdev->fd_rule_lock); 7029 return -ENOMEM; 7030 } 7031 7032 rule->location = bit_id; 7033 rule->arfs.flow_id = flow_id; 7034 rule->queue_id = queue_id; 7035 hclge_fd_build_arfs_rule(&new_tuples, rule); 7036 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 7037 hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE; 7038 } else if (rule->queue_id != queue_id) { 7039 rule->queue_id = queue_id; 7040 rule->state = HCLGE_FD_TO_ADD; 7041 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7042 hclge_task_schedule(hdev, 0); 7043 } 7044 spin_unlock_bh(&hdev->fd_rule_lock); 7045 return rule->location; 7046 } 7047 7048 static void hclge_rfs_filter_expire(struct hclge_dev *hdev) 7049 { 7050 #ifdef CONFIG_RFS_ACCEL 7051 struct hnae3_handle *handle = &hdev->vport[0].nic; 7052 struct hclge_fd_rule *rule; 7053 struct hlist_node *node; 7054 7055 spin_lock_bh(&hdev->fd_rule_lock); 7056 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) { 7057 spin_unlock_bh(&hdev->fd_rule_lock); 7058 return; 7059 } 7060 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7061 if (rule->state != HCLGE_FD_ACTIVE) 7062 continue; 7063 if (rps_may_expire_flow(handle->netdev, rule->queue_id, 7064 rule->arfs.flow_id, rule->location)) { 7065 rule->state = HCLGE_FD_TO_DEL; 7066 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7067 } 7068 } 7069 spin_unlock_bh(&hdev->fd_rule_lock); 7070 #endif 7071 } 7072 7073 /* make sure being called after lock up with fd_rule_lock */ 7074 static int hclge_clear_arfs_rules(struct hclge_dev *hdev) 7075 { 7076 #ifdef CONFIG_RFS_ACCEL 7077 struct hclge_fd_rule *rule; 7078 struct hlist_node *node; 7079 int ret; 7080 7081 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) 7082 return 0; 7083 7084 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7085 switch (rule->state) { 7086 case HCLGE_FD_TO_DEL: 7087 case HCLGE_FD_ACTIVE: 7088 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7089 rule->location, NULL, false); 7090 if (ret) 7091 return ret; 7092 fallthrough; 7093 case HCLGE_FD_TO_ADD: 7094 hclge_fd_dec_rule_cnt(hdev, rule->location); 7095 hlist_del(&rule->rule_node); 7096 kfree(rule); 7097 break; 7098 default: 7099 break; 7100 } 7101 } 7102 hclge_sync_fd_state(hdev); 7103 7104 #endif 7105 return 0; 7106 } 7107 7108 static void hclge_get_cls_key_basic(const struct flow_rule *flow, 7109 struct hclge_fd_rule *rule) 7110 { 7111 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) { 7112 struct flow_match_basic match; 7113 u16 ethtype_key, ethtype_mask; 7114 7115 flow_rule_match_basic(flow, &match); 7116 ethtype_key = ntohs(match.key->n_proto); 7117 ethtype_mask = ntohs(match.mask->n_proto); 7118 7119 if (ethtype_key == ETH_P_ALL) { 7120 ethtype_key = 0; 7121 ethtype_mask = 0; 7122 } 7123 rule->tuples.ether_proto = ethtype_key; 7124 rule->tuples_mask.ether_proto = ethtype_mask; 7125 rule->tuples.ip_proto = match.key->ip_proto; 7126 rule->tuples_mask.ip_proto = match.mask->ip_proto; 7127 } else { 7128 rule->unused_tuple |= BIT(INNER_IP_PROTO); 7129 rule->unused_tuple |= BIT(INNER_ETH_TYPE); 7130 } 7131 } 7132 7133 static void hclge_get_cls_key_mac(const struct flow_rule *flow, 7134 struct hclge_fd_rule *rule) 7135 { 7136 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 7137 struct flow_match_eth_addrs match; 7138 7139 flow_rule_match_eth_addrs(flow, &match); 7140 ether_addr_copy(rule->tuples.dst_mac, match.key->dst); 7141 ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst); 7142 ether_addr_copy(rule->tuples.src_mac, match.key->src); 7143 ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src); 7144 } else { 7145 rule->unused_tuple |= BIT(INNER_DST_MAC); 7146 rule->unused_tuple |= BIT(INNER_SRC_MAC); 7147 } 7148 } 7149 7150 static void hclge_get_cls_key_vlan(const struct flow_rule *flow, 7151 struct hclge_fd_rule *rule) 7152 { 7153 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) { 7154 struct flow_match_vlan match; 7155 7156 flow_rule_match_vlan(flow, &match); 7157 rule->tuples.vlan_tag1 = match.key->vlan_id | 7158 (match.key->vlan_priority << VLAN_PRIO_SHIFT); 7159 rule->tuples_mask.vlan_tag1 = match.mask->vlan_id | 7160 (match.mask->vlan_priority << VLAN_PRIO_SHIFT); 7161 } else { 7162 rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST); 7163 } 7164 } 7165 7166 static void hclge_get_cls_key_ip(const struct flow_rule *flow, 7167 struct hclge_fd_rule *rule) 7168 { 7169 u16 addr_type = 0; 7170 7171 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) { 7172 struct flow_match_control match; 7173 7174 flow_rule_match_control(flow, &match); 7175 addr_type = match.key->addr_type; 7176 } 7177 7178 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { 7179 struct flow_match_ipv4_addrs match; 7180 7181 flow_rule_match_ipv4_addrs(flow, &match); 7182 rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src); 7183 rule->tuples_mask.src_ip[IPV4_INDEX] = 7184 be32_to_cpu(match.mask->src); 7185 rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst); 7186 rule->tuples_mask.dst_ip[IPV4_INDEX] = 7187 be32_to_cpu(match.mask->dst); 7188 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { 7189 struct flow_match_ipv6_addrs match; 7190 7191 flow_rule_match_ipv6_addrs(flow, &match); 7192 be32_to_cpu_array(rule->tuples.src_ip, match.key->src.s6_addr32, 7193 IPV6_SIZE); 7194 be32_to_cpu_array(rule->tuples_mask.src_ip, 7195 match.mask->src.s6_addr32, IPV6_SIZE); 7196 be32_to_cpu_array(rule->tuples.dst_ip, match.key->dst.s6_addr32, 7197 IPV6_SIZE); 7198 be32_to_cpu_array(rule->tuples_mask.dst_ip, 7199 match.mask->dst.s6_addr32, IPV6_SIZE); 7200 } else { 7201 rule->unused_tuple |= BIT(INNER_SRC_IP); 7202 rule->unused_tuple |= BIT(INNER_DST_IP); 7203 } 7204 } 7205 7206 static void hclge_get_cls_key_port(const struct flow_rule *flow, 7207 struct hclge_fd_rule *rule) 7208 { 7209 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) { 7210 struct flow_match_ports match; 7211 7212 flow_rule_match_ports(flow, &match); 7213 7214 rule->tuples.src_port = be16_to_cpu(match.key->src); 7215 rule->tuples_mask.src_port = be16_to_cpu(match.mask->src); 7216 rule->tuples.dst_port = be16_to_cpu(match.key->dst); 7217 rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst); 7218 } else { 7219 rule->unused_tuple |= BIT(INNER_SRC_PORT); 7220 rule->unused_tuple |= BIT(INNER_DST_PORT); 7221 } 7222 } 7223 7224 static int hclge_parse_cls_flower(struct hclge_dev *hdev, 7225 struct flow_cls_offload *cls_flower, 7226 struct hclge_fd_rule *rule) 7227 { 7228 struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower); 7229 struct flow_dissector *dissector = flow->match.dissector; 7230 7231 if (dissector->used_keys & 7232 ~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) | 7233 BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) | 7234 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 7235 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) | 7236 BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | 7237 BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | 7238 BIT_ULL(FLOW_DISSECTOR_KEY_PORTS))) { 7239 dev_err(&hdev->pdev->dev, "unsupported key set: %#llx\n", 7240 dissector->used_keys); 7241 return -EOPNOTSUPP; 7242 } 7243 7244 hclge_get_cls_key_basic(flow, rule); 7245 hclge_get_cls_key_mac(flow, rule); 7246 hclge_get_cls_key_vlan(flow, rule); 7247 hclge_get_cls_key_ip(flow, rule); 7248 hclge_get_cls_key_port(flow, rule); 7249 7250 return 0; 7251 } 7252 7253 static int hclge_check_cls_flower(struct hclge_dev *hdev, 7254 struct flow_cls_offload *cls_flower, int tc) 7255 { 7256 u32 prio = cls_flower->common.prio; 7257 7258 if (tc < 0 || tc > hdev->tc_max) { 7259 dev_err(&hdev->pdev->dev, "invalid traffic class\n"); 7260 return -EINVAL; 7261 } 7262 7263 if (prio == 0 || 7264 prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7265 dev_err(&hdev->pdev->dev, 7266 "prio %u should be in range[1, %u]\n", 7267 prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 7268 return -EINVAL; 7269 } 7270 7271 if (test_bit(prio - 1, hdev->fd_bmap)) { 7272 dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio); 7273 return -EINVAL; 7274 } 7275 return 0; 7276 } 7277 7278 static int hclge_add_cls_flower(struct hnae3_handle *handle, 7279 struct flow_cls_offload *cls_flower, 7280 int tc) 7281 { 7282 struct hclge_vport *vport = hclge_get_vport(handle); 7283 struct hclge_dev *hdev = vport->back; 7284 struct hclge_fd_rule *rule; 7285 int ret; 7286 7287 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 7288 dev_err(&hdev->pdev->dev, 7289 "cls flower is not supported\n"); 7290 return -EOPNOTSUPP; 7291 } 7292 7293 ret = hclge_check_cls_flower(hdev, cls_flower, tc); 7294 if (ret) { 7295 dev_err(&hdev->pdev->dev, 7296 "failed to check cls flower params, ret = %d\n", ret); 7297 return ret; 7298 } 7299 7300 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 7301 if (!rule) 7302 return -ENOMEM; 7303 7304 ret = hclge_parse_cls_flower(hdev, cls_flower, rule); 7305 if (ret) { 7306 kfree(rule); 7307 return ret; 7308 } 7309 7310 rule->action = HCLGE_FD_ACTION_SELECT_TC; 7311 rule->cls_flower.tc = tc; 7312 rule->location = cls_flower->common.prio - 1; 7313 rule->vf_id = 0; 7314 rule->cls_flower.cookie = cls_flower->cookie; 7315 rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE; 7316 7317 ret = hclge_add_fd_entry_common(hdev, rule); 7318 if (ret) 7319 kfree(rule); 7320 7321 return ret; 7322 } 7323 7324 static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev, 7325 unsigned long cookie) 7326 { 7327 struct hclge_fd_rule *rule; 7328 struct hlist_node *node; 7329 7330 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7331 if (rule->cls_flower.cookie == cookie) 7332 return rule; 7333 } 7334 7335 return NULL; 7336 } 7337 7338 static int hclge_del_cls_flower(struct hnae3_handle *handle, 7339 struct flow_cls_offload *cls_flower) 7340 { 7341 struct hclge_vport *vport = hclge_get_vport(handle); 7342 struct hclge_dev *hdev = vport->back; 7343 struct hclge_fd_rule *rule; 7344 int ret; 7345 7346 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7347 return -EOPNOTSUPP; 7348 7349 spin_lock_bh(&hdev->fd_rule_lock); 7350 7351 rule = hclge_find_cls_flower(hdev, cls_flower->cookie); 7352 if (!rule) { 7353 spin_unlock_bh(&hdev->fd_rule_lock); 7354 return -EINVAL; 7355 } 7356 7357 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location, 7358 NULL, false); 7359 if (ret) { 7360 /* if tcam config fail, set rule state to TO_DEL, 7361 * so the rule will be deleted when periodic 7362 * task being scheduled. 7363 */ 7364 hclge_update_fd_list(hdev, HCLGE_FD_TO_DEL, rule->location, NULL); 7365 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7366 spin_unlock_bh(&hdev->fd_rule_lock); 7367 return ret; 7368 } 7369 7370 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL); 7371 spin_unlock_bh(&hdev->fd_rule_lock); 7372 7373 return 0; 7374 } 7375 7376 static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist) 7377 { 7378 struct hclge_fd_rule *rule; 7379 struct hlist_node *node; 7380 int ret = 0; 7381 7382 if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state)) 7383 return; 7384 7385 spin_lock_bh(&hdev->fd_rule_lock); 7386 7387 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 7388 switch (rule->state) { 7389 case HCLGE_FD_TO_ADD: 7390 ret = hclge_fd_config_rule(hdev, rule); 7391 if (ret) 7392 goto out; 7393 rule->state = HCLGE_FD_ACTIVE; 7394 break; 7395 case HCLGE_FD_TO_DEL: 7396 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7397 rule->location, NULL, false); 7398 if (ret) 7399 goto out; 7400 hclge_fd_dec_rule_cnt(hdev, rule->location); 7401 hclge_fd_free_node(hdev, rule); 7402 break; 7403 default: 7404 break; 7405 } 7406 } 7407 7408 out: 7409 if (ret) 7410 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7411 7412 spin_unlock_bh(&hdev->fd_rule_lock); 7413 } 7414 7415 static void hclge_sync_fd_table(struct hclge_dev *hdev) 7416 { 7417 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7418 return; 7419 7420 if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) { 7421 bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE; 7422 7423 hclge_clear_fd_rules_in_list(hdev, clear_list); 7424 } 7425 7426 hclge_sync_fd_user_def_cfg(hdev, false); 7427 7428 hclge_sync_fd_list(hdev, &hdev->fd_rule_list); 7429 } 7430 7431 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle) 7432 { 7433 struct hclge_vport *vport = hclge_get_vport(handle); 7434 struct hclge_dev *hdev = vport->back; 7435 7436 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) || 7437 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING); 7438 } 7439 7440 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle) 7441 { 7442 struct hclge_vport *vport = hclge_get_vport(handle); 7443 struct hclge_dev *hdev = vport->back; 7444 7445 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 7446 } 7447 7448 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle) 7449 { 7450 struct hclge_vport *vport = hclge_get_vport(handle); 7451 struct hclge_dev *hdev = vport->back; 7452 7453 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 7454 } 7455 7456 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle) 7457 { 7458 struct hclge_vport *vport = hclge_get_vport(handle); 7459 struct hclge_dev *hdev = vport->back; 7460 7461 return hdev->rst_stats.hw_reset_done_cnt; 7462 } 7463 7464 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable) 7465 { 7466 struct hclge_vport *vport = hclge_get_vport(handle); 7467 struct hclge_dev *hdev = vport->back; 7468 7469 hdev->fd_en = enable; 7470 7471 if (!enable) 7472 set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state); 7473 else 7474 hclge_restore_fd_entries(handle); 7475 7476 hclge_task_schedule(hdev, 0); 7477 } 7478 7479 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 7480 { 7481 #define HCLGE_LINK_STATUS_WAIT_CNT 3 7482 7483 struct hclge_desc desc; 7484 struct hclge_config_mac_mode_cmd *req = 7485 (struct hclge_config_mac_mode_cmd *)desc.data; 7486 u32 loop_en = 0; 7487 int ret; 7488 7489 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 7490 7491 if (enable) { 7492 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U); 7493 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U); 7494 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U); 7495 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U); 7496 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U); 7497 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U); 7498 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U); 7499 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U); 7500 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U); 7501 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U); 7502 } 7503 7504 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7505 7506 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7507 if (ret) { 7508 dev_err(&hdev->pdev->dev, 7509 "mac enable fail, ret =%d.\n", ret); 7510 return; 7511 } 7512 7513 if (!enable) 7514 hclge_mac_link_status_wait(hdev, HCLGE_LINK_STATUS_DOWN, 7515 HCLGE_LINK_STATUS_WAIT_CNT); 7516 } 7517 7518 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid, 7519 u8 switch_param, u8 param_mask) 7520 { 7521 struct hclge_mac_vlan_switch_cmd *req; 7522 struct hclge_desc desc; 7523 u32 func_id; 7524 int ret; 7525 7526 func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0); 7527 req = (struct hclge_mac_vlan_switch_cmd *)desc.data; 7528 7529 /* read current config parameter */ 7530 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM, 7531 true); 7532 req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL; 7533 req->func_id = cpu_to_le32(func_id); 7534 7535 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7536 if (ret) { 7537 dev_err(&hdev->pdev->dev, 7538 "read mac vlan switch parameter fail, ret = %d\n", ret); 7539 return ret; 7540 } 7541 7542 /* modify and write new config parameter */ 7543 hclge_comm_cmd_reuse_desc(&desc, false); 7544 req->switch_param = (req->switch_param & param_mask) | switch_param; 7545 req->param_mask = param_mask; 7546 7547 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7548 if (ret) 7549 dev_err(&hdev->pdev->dev, 7550 "set mac vlan switch parameter fail, ret = %d\n", ret); 7551 return ret; 7552 } 7553 7554 static void hclge_phy_link_status_wait(struct hclge_dev *hdev, 7555 int link_ret) 7556 { 7557 #define HCLGE_PHY_LINK_STATUS_NUM 200 7558 7559 struct phy_device *phydev = hdev->hw.mac.phydev; 7560 int i = 0; 7561 int ret; 7562 7563 do { 7564 ret = phy_read_status(phydev); 7565 if (ret) { 7566 dev_err(&hdev->pdev->dev, 7567 "phy update link status fail, ret = %d\n", ret); 7568 return; 7569 } 7570 7571 if (phydev->link == link_ret) 7572 break; 7573 7574 msleep(HCLGE_LINK_STATUS_MS); 7575 } while (++i < HCLGE_PHY_LINK_STATUS_NUM); 7576 } 7577 7578 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 7579 int wait_cnt) 7580 { 7581 int link_status; 7582 int i = 0; 7583 int ret; 7584 7585 do { 7586 ret = hclge_get_mac_link_status(hdev, &link_status); 7587 if (ret) 7588 return ret; 7589 if (link_status == link_ret) 7590 return 0; 7591 7592 msleep(HCLGE_LINK_STATUS_MS); 7593 } while (++i < wait_cnt); 7594 return -EBUSY; 7595 } 7596 7597 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en, 7598 bool is_phy) 7599 { 7600 #define HCLGE_MAC_LINK_STATUS_NUM 100 7601 7602 int link_ret; 7603 7604 link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 7605 7606 if (is_phy) 7607 hclge_phy_link_status_wait(hdev, link_ret); 7608 7609 return hclge_mac_link_status_wait(hdev, link_ret, 7610 HCLGE_MAC_LINK_STATUS_NUM); 7611 } 7612 7613 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) 7614 { 7615 struct hclge_config_mac_mode_cmd *req; 7616 struct hclge_desc desc; 7617 u32 loop_en; 7618 int ret; 7619 7620 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 7621 /* 1 Read out the MAC mode config at first */ 7622 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 7623 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7624 if (ret) { 7625 dev_err(&hdev->pdev->dev, 7626 "mac loopback get fail, ret =%d.\n", ret); 7627 return ret; 7628 } 7629 7630 /* 2 Then setup the loopback flag */ 7631 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 7632 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 7633 7634 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7635 7636 /* 3 Config mac work mode with loopback flag 7637 * and its original configure parameters 7638 */ 7639 hclge_comm_cmd_reuse_desc(&desc, false); 7640 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7641 if (ret) 7642 dev_err(&hdev->pdev->dev, 7643 "mac loopback set fail, ret =%d.\n", ret); 7644 return ret; 7645 } 7646 7647 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en, 7648 enum hnae3_loop loop_mode) 7649 { 7650 struct hclge_common_lb_cmd *req; 7651 struct hclge_desc desc; 7652 u8 loop_mode_b; 7653 int ret; 7654 7655 req = (struct hclge_common_lb_cmd *)desc.data; 7656 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false); 7657 7658 switch (loop_mode) { 7659 case HNAE3_LOOP_SERIAL_SERDES: 7660 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 7661 break; 7662 case HNAE3_LOOP_PARALLEL_SERDES: 7663 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B; 7664 break; 7665 case HNAE3_LOOP_PHY: 7666 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B; 7667 break; 7668 default: 7669 dev_err(&hdev->pdev->dev, 7670 "unsupported loopback mode %d\n", loop_mode); 7671 return -ENOTSUPP; 7672 } 7673 7674 req->mask = loop_mode_b; 7675 if (en) 7676 req->enable = loop_mode_b; 7677 7678 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7679 if (ret) 7680 dev_err(&hdev->pdev->dev, 7681 "failed to send loopback cmd, loop_mode = %d, ret = %d\n", 7682 loop_mode, ret); 7683 7684 return ret; 7685 } 7686 7687 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev) 7688 { 7689 #define HCLGE_COMMON_LB_RETRY_MS 10 7690 #define HCLGE_COMMON_LB_RETRY_NUM 100 7691 7692 struct hclge_common_lb_cmd *req; 7693 struct hclge_desc desc; 7694 u32 i = 0; 7695 int ret; 7696 7697 req = (struct hclge_common_lb_cmd *)desc.data; 7698 7699 do { 7700 msleep(HCLGE_COMMON_LB_RETRY_MS); 7701 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, 7702 true); 7703 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7704 if (ret) { 7705 dev_err(&hdev->pdev->dev, 7706 "failed to get loopback done status, ret = %d\n", 7707 ret); 7708 return ret; 7709 } 7710 } while (++i < HCLGE_COMMON_LB_RETRY_NUM && 7711 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B)); 7712 7713 if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) { 7714 dev_err(&hdev->pdev->dev, "wait loopback timeout\n"); 7715 return -EBUSY; 7716 } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) { 7717 dev_err(&hdev->pdev->dev, "failed to do loopback test\n"); 7718 return -EIO; 7719 } 7720 7721 return 0; 7722 } 7723 7724 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en, 7725 enum hnae3_loop loop_mode) 7726 { 7727 int ret; 7728 7729 ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode); 7730 if (ret) 7731 return ret; 7732 7733 return hclge_cfg_common_loopback_wait(hdev); 7734 } 7735 7736 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en, 7737 enum hnae3_loop loop_mode) 7738 { 7739 int ret; 7740 7741 ret = hclge_cfg_common_loopback(hdev, en, loop_mode); 7742 if (ret) 7743 return ret; 7744 7745 hclge_cfg_mac_mode(hdev, en); 7746 7747 ret = hclge_mac_phy_link_status_wait(hdev, en, false); 7748 if (ret) 7749 dev_err(&hdev->pdev->dev, 7750 "serdes loopback config mac mode timeout\n"); 7751 7752 return ret; 7753 } 7754 7755 static int hclge_enable_phy_loopback(struct hclge_dev *hdev, 7756 struct phy_device *phydev) 7757 { 7758 int ret; 7759 7760 if (!phydev->suspended) { 7761 ret = phy_suspend(phydev); 7762 if (ret) 7763 return ret; 7764 } 7765 7766 ret = phy_resume(phydev); 7767 if (ret) 7768 return ret; 7769 7770 return phy_loopback(phydev, true); 7771 } 7772 7773 static int hclge_disable_phy_loopback(struct hclge_dev *hdev, 7774 struct phy_device *phydev) 7775 { 7776 int ret; 7777 7778 ret = phy_loopback(phydev, false); 7779 if (ret) 7780 return ret; 7781 7782 return phy_suspend(phydev); 7783 } 7784 7785 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en) 7786 { 7787 struct phy_device *phydev = hdev->hw.mac.phydev; 7788 int ret; 7789 7790 if (!phydev) { 7791 if (hnae3_dev_phy_imp_supported(hdev)) 7792 return hclge_set_common_loopback(hdev, en, 7793 HNAE3_LOOP_PHY); 7794 return -ENOTSUPP; 7795 } 7796 7797 if (en) 7798 ret = hclge_enable_phy_loopback(hdev, phydev); 7799 else 7800 ret = hclge_disable_phy_loopback(hdev, phydev); 7801 if (ret) { 7802 dev_err(&hdev->pdev->dev, 7803 "set phy loopback fail, ret = %d\n", ret); 7804 return ret; 7805 } 7806 7807 hclge_cfg_mac_mode(hdev, en); 7808 7809 ret = hclge_mac_phy_link_status_wait(hdev, en, true); 7810 if (ret) 7811 dev_err(&hdev->pdev->dev, 7812 "phy loopback config mac mode timeout\n"); 7813 7814 return ret; 7815 } 7816 7817 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id, 7818 u16 stream_id, bool enable) 7819 { 7820 struct hclge_desc desc; 7821 struct hclge_cfg_com_tqp_queue_cmd *req = 7822 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 7823 7824 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 7825 req->tqp_id = cpu_to_le16(tqp_id); 7826 req->stream_id = cpu_to_le16(stream_id); 7827 if (enable) 7828 req->enable |= 1U << HCLGE_TQP_ENABLE_B; 7829 7830 return hclge_cmd_send(&hdev->hw, &desc, 1); 7831 } 7832 7833 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable) 7834 { 7835 struct hclge_vport *vport = hclge_get_vport(handle); 7836 struct hclge_dev *hdev = vport->back; 7837 int ret; 7838 u16 i; 7839 7840 for (i = 0; i < handle->kinfo.num_tqps; i++) { 7841 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable); 7842 if (ret) 7843 return ret; 7844 } 7845 return 0; 7846 } 7847 7848 static int hclge_set_loopback(struct hnae3_handle *handle, 7849 enum hnae3_loop loop_mode, bool en) 7850 { 7851 struct hclge_vport *vport = hclge_get_vport(handle); 7852 struct hclge_dev *hdev = vport->back; 7853 int ret = 0; 7854 7855 /* Loopback can be enabled in three places: SSU, MAC, and serdes. By 7856 * default, SSU loopback is enabled, so if the SMAC and the DMAC are 7857 * the same, the packets are looped back in the SSU. If SSU loopback 7858 * is disabled, packets can reach MAC even if SMAC is the same as DMAC. 7859 */ 7860 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 7861 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B); 7862 7863 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param, 7864 HCLGE_SWITCH_ALW_LPBK_MASK); 7865 if (ret) 7866 return ret; 7867 } 7868 7869 switch (loop_mode) { 7870 case HNAE3_LOOP_APP: 7871 ret = hclge_set_app_loopback(hdev, en); 7872 break; 7873 case HNAE3_LOOP_SERIAL_SERDES: 7874 case HNAE3_LOOP_PARALLEL_SERDES: 7875 ret = hclge_set_common_loopback(hdev, en, loop_mode); 7876 break; 7877 case HNAE3_LOOP_PHY: 7878 ret = hclge_set_phy_loopback(hdev, en); 7879 break; 7880 case HNAE3_LOOP_EXTERNAL: 7881 break; 7882 default: 7883 ret = -ENOTSUPP; 7884 dev_err(&hdev->pdev->dev, 7885 "loop_mode %d is not supported\n", loop_mode); 7886 break; 7887 } 7888 7889 if (ret) 7890 return ret; 7891 7892 ret = hclge_tqp_enable(handle, en); 7893 if (ret) 7894 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n", 7895 en ? "enable" : "disable", ret); 7896 7897 return ret; 7898 } 7899 7900 static int hclge_set_default_loopback(struct hclge_dev *hdev) 7901 { 7902 int ret; 7903 7904 ret = hclge_set_app_loopback(hdev, false); 7905 if (ret) 7906 return ret; 7907 7908 ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES); 7909 if (ret) 7910 return ret; 7911 7912 return hclge_cfg_common_loopback(hdev, false, 7913 HNAE3_LOOP_PARALLEL_SERDES); 7914 } 7915 7916 static void hclge_flush_link_update(struct hclge_dev *hdev) 7917 { 7918 #define HCLGE_FLUSH_LINK_TIMEOUT 100000 7919 7920 unsigned long last = hdev->serv_processed_cnt; 7921 int i = 0; 7922 7923 while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) && 7924 i++ < HCLGE_FLUSH_LINK_TIMEOUT && 7925 last == hdev->serv_processed_cnt) 7926 usleep_range(1, 1); 7927 } 7928 7929 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable) 7930 { 7931 struct hclge_vport *vport = hclge_get_vport(handle); 7932 struct hclge_dev *hdev = vport->back; 7933 7934 if (enable) { 7935 hclge_task_schedule(hdev, 0); 7936 } else { 7937 /* Set the DOWN flag here to disable link updating */ 7938 set_bit(HCLGE_STATE_DOWN, &hdev->state); 7939 7940 /* flush memory to make sure DOWN is seen by service task */ 7941 smp_mb__before_atomic(); 7942 hclge_flush_link_update(hdev); 7943 } 7944 } 7945 7946 static int hclge_ae_start(struct hnae3_handle *handle) 7947 { 7948 struct hclge_vport *vport = hclge_get_vport(handle); 7949 struct hclge_dev *hdev = vport->back; 7950 7951 /* mac enable */ 7952 hclge_cfg_mac_mode(hdev, true); 7953 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 7954 hdev->hw.mac.link = 0; 7955 7956 /* reset tqp stats */ 7957 hclge_comm_reset_tqp_stats(handle); 7958 7959 hclge_mac_start_phy(hdev); 7960 7961 return 0; 7962 } 7963 7964 static void hclge_ae_stop(struct hnae3_handle *handle) 7965 { 7966 struct hclge_vport *vport = hclge_get_vport(handle); 7967 struct hclge_dev *hdev = vport->back; 7968 7969 set_bit(HCLGE_STATE_DOWN, &hdev->state); 7970 spin_lock_bh(&hdev->fd_rule_lock); 7971 hclge_clear_arfs_rules(hdev); 7972 spin_unlock_bh(&hdev->fd_rule_lock); 7973 7974 /* If it is not PF reset or FLR, the firmware will disable the MAC, 7975 * so it only need to stop phy here. 7976 */ 7977 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { 7978 hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE, 7979 HCLGE_PFC_DISABLE); 7980 if (hdev->reset_type != HNAE3_FUNC_RESET && 7981 hdev->reset_type != HNAE3_FLR_RESET) { 7982 hclge_mac_stop_phy(hdev); 7983 hclge_update_link_status(hdev); 7984 return; 7985 } 7986 } 7987 7988 hclge_reset_tqp(handle); 7989 7990 hclge_config_mac_tnl_int(hdev, false); 7991 7992 /* Mac disable */ 7993 hclge_cfg_mac_mode(hdev, false); 7994 7995 hclge_mac_stop_phy(hdev); 7996 7997 /* reset tqp stats */ 7998 hclge_comm_reset_tqp_stats(handle); 7999 hclge_update_link_status(hdev); 8000 } 8001 8002 int hclge_vport_start(struct hclge_vport *vport) 8003 { 8004 struct hclge_dev *hdev = vport->back; 8005 8006 set_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8007 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8008 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 8009 vport->last_active_jiffies = jiffies; 8010 vport->need_notify = 0; 8011 8012 if (test_bit(vport->vport_id, hdev->vport_config_block)) { 8013 if (vport->vport_id) { 8014 hclge_restore_mac_table_common(vport); 8015 hclge_restore_vport_vlan_table(vport); 8016 } else { 8017 hclge_restore_hw_table(hdev); 8018 } 8019 } 8020 8021 clear_bit(vport->vport_id, hdev->vport_config_block); 8022 8023 return 0; 8024 } 8025 8026 void hclge_vport_stop(struct hclge_vport *vport) 8027 { 8028 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 8029 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8030 vport->need_notify = 0; 8031 } 8032 8033 static int hclge_client_start(struct hnae3_handle *handle) 8034 { 8035 struct hclge_vport *vport = hclge_get_vport(handle); 8036 8037 return hclge_vport_start(vport); 8038 } 8039 8040 static void hclge_client_stop(struct hnae3_handle *handle) 8041 { 8042 struct hclge_vport *vport = hclge_get_vport(handle); 8043 8044 hclge_vport_stop(vport); 8045 } 8046 8047 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 8048 u16 cmdq_resp, u8 resp_code, 8049 enum hclge_mac_vlan_tbl_opcode op) 8050 { 8051 struct hclge_dev *hdev = vport->back; 8052 8053 if (cmdq_resp) { 8054 dev_err(&hdev->pdev->dev, 8055 "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n", 8056 cmdq_resp); 8057 return -EIO; 8058 } 8059 8060 if (op == HCLGE_MAC_VLAN_ADD) { 8061 if (!resp_code || resp_code == 1) 8062 return 0; 8063 else if (resp_code == HCLGE_ADD_UC_OVERFLOW || 8064 resp_code == HCLGE_ADD_MC_OVERFLOW) 8065 return -ENOSPC; 8066 8067 dev_err(&hdev->pdev->dev, 8068 "add mac addr failed for undefined, code=%u.\n", 8069 resp_code); 8070 return -EIO; 8071 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 8072 if (!resp_code) { 8073 return 0; 8074 } else if (resp_code == 1) { 8075 dev_dbg(&hdev->pdev->dev, 8076 "remove mac addr failed for miss.\n"); 8077 return -ENOENT; 8078 } 8079 8080 dev_err(&hdev->pdev->dev, 8081 "remove mac addr failed for undefined, code=%u.\n", 8082 resp_code); 8083 return -EIO; 8084 } else if (op == HCLGE_MAC_VLAN_LKUP) { 8085 if (!resp_code) { 8086 return 0; 8087 } else if (resp_code == 1) { 8088 dev_dbg(&hdev->pdev->dev, 8089 "lookup mac addr failed for miss.\n"); 8090 return -ENOENT; 8091 } 8092 8093 dev_err(&hdev->pdev->dev, 8094 "lookup mac addr failed for undefined, code=%u.\n", 8095 resp_code); 8096 return -EIO; 8097 } 8098 8099 dev_err(&hdev->pdev->dev, 8100 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op); 8101 8102 return -EINVAL; 8103 } 8104 8105 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 8106 { 8107 #define HCLGE_VF_NUM_IN_FIRST_DESC 192 8108 8109 unsigned int word_num; 8110 unsigned int bit_num; 8111 8112 if (vfid > 255 || vfid < 0) 8113 return -EIO; 8114 8115 if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) { 8116 word_num = vfid / 32; 8117 bit_num = vfid % 32; 8118 if (clr) 8119 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8120 else 8121 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 8122 } else { 8123 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32; 8124 bit_num = vfid % 32; 8125 if (clr) 8126 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8127 else 8128 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 8129 } 8130 8131 return 0; 8132 } 8133 8134 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 8135 { 8136 #define HCLGE_DESC_NUMBER 3 8137 #define HCLGE_FUNC_NUMBER_PER_DESC 6 8138 int i, j; 8139 8140 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 8141 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 8142 if (desc[i].data[j]) 8143 return false; 8144 8145 return true; 8146 } 8147 8148 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 8149 const u8 *addr, bool is_mc) 8150 { 8151 const unsigned char *mac_addr = addr; 8152 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 8153 (mac_addr[0]) | (mac_addr[1] << 8); 8154 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 8155 8156 hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8157 if (is_mc) { 8158 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 8159 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8160 } 8161 8162 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 8163 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 8164 } 8165 8166 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 8167 struct hclge_mac_vlan_tbl_entry_cmd *req) 8168 { 8169 struct hclge_dev *hdev = vport->back; 8170 struct hclge_desc desc; 8171 u8 resp_code; 8172 u16 retval; 8173 int ret; 8174 8175 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 8176 8177 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8178 8179 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8180 if (ret) { 8181 dev_err(&hdev->pdev->dev, 8182 "del mac addr failed for cmd_send, ret =%d.\n", 8183 ret); 8184 return ret; 8185 } 8186 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8187 retval = le16_to_cpu(desc.retval); 8188 8189 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8190 HCLGE_MAC_VLAN_REMOVE); 8191 } 8192 8193 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 8194 struct hclge_mac_vlan_tbl_entry_cmd *req, 8195 struct hclge_desc *desc, 8196 bool is_mc) 8197 { 8198 struct hclge_dev *hdev = vport->back; 8199 u8 resp_code; 8200 u16 retval; 8201 int ret; 8202 8203 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 8204 if (is_mc) { 8205 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8206 memcpy(desc[0].data, 8207 req, 8208 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8209 hclge_cmd_setup_basic_desc(&desc[1], 8210 HCLGE_OPC_MAC_VLAN_ADD, 8211 true); 8212 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8213 hclge_cmd_setup_basic_desc(&desc[2], 8214 HCLGE_OPC_MAC_VLAN_ADD, 8215 true); 8216 ret = hclge_cmd_send(&hdev->hw, desc, 3); 8217 } else { 8218 memcpy(desc[0].data, 8219 req, 8220 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8221 ret = hclge_cmd_send(&hdev->hw, desc, 1); 8222 } 8223 if (ret) { 8224 dev_err(&hdev->pdev->dev, 8225 "lookup mac addr failed for cmd_send, ret =%d.\n", 8226 ret); 8227 return ret; 8228 } 8229 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 8230 retval = le16_to_cpu(desc[0].retval); 8231 8232 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8233 HCLGE_MAC_VLAN_LKUP); 8234 } 8235 8236 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 8237 struct hclge_mac_vlan_tbl_entry_cmd *req, 8238 struct hclge_desc *mc_desc) 8239 { 8240 struct hclge_dev *hdev = vport->back; 8241 int cfg_status; 8242 u8 resp_code; 8243 u16 retval; 8244 int ret; 8245 8246 if (!mc_desc) { 8247 struct hclge_desc desc; 8248 8249 hclge_cmd_setup_basic_desc(&desc, 8250 HCLGE_OPC_MAC_VLAN_ADD, 8251 false); 8252 memcpy(desc.data, req, 8253 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8254 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8255 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8256 retval = le16_to_cpu(desc.retval); 8257 8258 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8259 resp_code, 8260 HCLGE_MAC_VLAN_ADD); 8261 } else { 8262 hclge_comm_cmd_reuse_desc(&mc_desc[0], false); 8263 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8264 hclge_comm_cmd_reuse_desc(&mc_desc[1], false); 8265 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8266 hclge_comm_cmd_reuse_desc(&mc_desc[2], false); 8267 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT); 8268 memcpy(mc_desc[0].data, req, 8269 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8270 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 8271 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 8272 retval = le16_to_cpu(mc_desc[0].retval); 8273 8274 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8275 resp_code, 8276 HCLGE_MAC_VLAN_ADD); 8277 } 8278 8279 if (ret) { 8280 dev_err(&hdev->pdev->dev, 8281 "add mac addr failed for cmd_send, ret =%d.\n", 8282 ret); 8283 return ret; 8284 } 8285 8286 return cfg_status; 8287 } 8288 8289 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 8290 u16 *allocated_size) 8291 { 8292 struct hclge_umv_spc_alc_cmd *req; 8293 struct hclge_desc desc; 8294 int ret; 8295 8296 req = (struct hclge_umv_spc_alc_cmd *)desc.data; 8297 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false); 8298 8299 req->space_size = cpu_to_le32(space_size); 8300 8301 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8302 if (ret) { 8303 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n", 8304 ret); 8305 return ret; 8306 } 8307 8308 *allocated_size = le32_to_cpu(desc.data[1]); 8309 8310 return 0; 8311 } 8312 8313 static int hclge_init_umv_space(struct hclge_dev *hdev) 8314 { 8315 u16 allocated_size = 0; 8316 int ret; 8317 8318 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size); 8319 if (ret) 8320 return ret; 8321 8322 if (allocated_size < hdev->wanted_umv_size) 8323 dev_warn(&hdev->pdev->dev, 8324 "failed to alloc umv space, want %u, get %u\n", 8325 hdev->wanted_umv_size, allocated_size); 8326 8327 hdev->max_umv_size = allocated_size; 8328 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1); 8329 hdev->share_umv_size = hdev->priv_umv_size + 8330 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8331 8332 if (hdev->ae_dev->dev_specs.mc_mac_size) 8333 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps); 8334 8335 return 0; 8336 } 8337 8338 static void hclge_reset_umv_space(struct hclge_dev *hdev) 8339 { 8340 struct hclge_vport *vport; 8341 int i; 8342 8343 for (i = 0; i < hdev->num_alloc_vport; i++) { 8344 vport = &hdev->vport[i]; 8345 vport->used_umv_num = 0; 8346 } 8347 8348 mutex_lock(&hdev->vport_lock); 8349 hdev->share_umv_size = hdev->priv_umv_size + 8350 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8351 mutex_unlock(&hdev->vport_lock); 8352 8353 hdev->used_mc_mac_num = 0; 8354 } 8355 8356 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock) 8357 { 8358 struct hclge_dev *hdev = vport->back; 8359 bool is_full; 8360 8361 if (need_lock) 8362 mutex_lock(&hdev->vport_lock); 8363 8364 is_full = (vport->used_umv_num >= hdev->priv_umv_size && 8365 hdev->share_umv_size == 0); 8366 8367 if (need_lock) 8368 mutex_unlock(&hdev->vport_lock); 8369 8370 return is_full; 8371 } 8372 8373 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free) 8374 { 8375 struct hclge_dev *hdev = vport->back; 8376 8377 if (is_free) { 8378 if (vport->used_umv_num > hdev->priv_umv_size) 8379 hdev->share_umv_size++; 8380 8381 if (vport->used_umv_num > 0) 8382 vport->used_umv_num--; 8383 } else { 8384 if (vport->used_umv_num >= hdev->priv_umv_size && 8385 hdev->share_umv_size > 0) 8386 hdev->share_umv_size--; 8387 vport->used_umv_num++; 8388 } 8389 } 8390 8391 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list, 8392 const u8 *mac_addr) 8393 { 8394 struct hclge_mac_node *mac_node, *tmp; 8395 8396 list_for_each_entry_safe(mac_node, tmp, list, node) 8397 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 8398 return mac_node; 8399 8400 return NULL; 8401 } 8402 8403 static void hclge_update_mac_node(struct hclge_mac_node *mac_node, 8404 enum HCLGE_MAC_NODE_STATE state) 8405 { 8406 switch (state) { 8407 /* from set_rx_mode or tmp_add_list */ 8408 case HCLGE_MAC_TO_ADD: 8409 if (mac_node->state == HCLGE_MAC_TO_DEL) 8410 mac_node->state = HCLGE_MAC_ACTIVE; 8411 break; 8412 /* only from set_rx_mode */ 8413 case HCLGE_MAC_TO_DEL: 8414 if (mac_node->state == HCLGE_MAC_TO_ADD) { 8415 list_del(&mac_node->node); 8416 kfree(mac_node); 8417 } else { 8418 mac_node->state = HCLGE_MAC_TO_DEL; 8419 } 8420 break; 8421 /* only from tmp_add_list, the mac_node->state won't be 8422 * ACTIVE. 8423 */ 8424 case HCLGE_MAC_ACTIVE: 8425 if (mac_node->state == HCLGE_MAC_TO_ADD) 8426 mac_node->state = HCLGE_MAC_ACTIVE; 8427 8428 break; 8429 } 8430 } 8431 8432 int hclge_update_mac_list(struct hclge_vport *vport, 8433 enum HCLGE_MAC_NODE_STATE state, 8434 enum HCLGE_MAC_ADDR_TYPE mac_type, 8435 const unsigned char *addr) 8436 { 8437 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8438 struct hclge_dev *hdev = vport->back; 8439 struct hclge_mac_node *mac_node; 8440 struct list_head *list; 8441 8442 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8443 &vport->uc_mac_list : &vport->mc_mac_list; 8444 8445 spin_lock_bh(&vport->mac_list_lock); 8446 8447 /* if the mac addr is already in the mac list, no need to add a new 8448 * one into it, just check the mac addr state, convert it to a new 8449 * state, or just remove it, or do nothing. 8450 */ 8451 mac_node = hclge_find_mac_node(list, addr); 8452 if (mac_node) { 8453 hclge_update_mac_node(mac_node, state); 8454 spin_unlock_bh(&vport->mac_list_lock); 8455 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8456 return 0; 8457 } 8458 8459 /* if this address is never added, unnecessary to delete */ 8460 if (state == HCLGE_MAC_TO_DEL) { 8461 spin_unlock_bh(&vport->mac_list_lock); 8462 hnae3_format_mac_addr(format_mac_addr, addr); 8463 dev_err(&hdev->pdev->dev, 8464 "failed to delete address %s from mac list\n", 8465 format_mac_addr); 8466 return -ENOENT; 8467 } 8468 8469 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 8470 if (!mac_node) { 8471 spin_unlock_bh(&vport->mac_list_lock); 8472 return -ENOMEM; 8473 } 8474 8475 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8476 8477 mac_node->state = state; 8478 ether_addr_copy(mac_node->mac_addr, addr); 8479 list_add_tail(&mac_node->node, list); 8480 8481 spin_unlock_bh(&vport->mac_list_lock); 8482 8483 return 0; 8484 } 8485 8486 static int hclge_add_uc_addr(struct hnae3_handle *handle, 8487 const unsigned char *addr) 8488 { 8489 struct hclge_vport *vport = hclge_get_vport(handle); 8490 8491 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC, 8492 addr); 8493 } 8494 8495 int hclge_add_uc_addr_common(struct hclge_vport *vport, 8496 const unsigned char *addr) 8497 { 8498 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8499 struct hclge_dev *hdev = vport->back; 8500 struct hclge_mac_vlan_tbl_entry_cmd req; 8501 struct hclge_desc desc; 8502 u16 egress_port = 0; 8503 int ret; 8504 8505 /* mac addr check */ 8506 if (is_zero_ether_addr(addr) || 8507 is_broadcast_ether_addr(addr) || 8508 is_multicast_ether_addr(addr)) { 8509 hnae3_format_mac_addr(format_mac_addr, addr); 8510 dev_err(&hdev->pdev->dev, 8511 "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n", 8512 format_mac_addr, is_zero_ether_addr(addr), 8513 is_broadcast_ether_addr(addr), 8514 is_multicast_ether_addr(addr)); 8515 return -EINVAL; 8516 } 8517 8518 memset(&req, 0, sizeof(req)); 8519 8520 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 8521 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 8522 8523 req.egress_port = cpu_to_le16(egress_port); 8524 8525 hclge_prepare_mac_addr(&req, addr, false); 8526 8527 /* Lookup the mac address in the mac_vlan table, and add 8528 * it if the entry is inexistent. Repeated unicast entry 8529 * is not allowed in the mac vlan table. 8530 */ 8531 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 8532 if (ret == -ENOENT) { 8533 mutex_lock(&hdev->vport_lock); 8534 if (!hclge_is_umv_space_full(vport, false)) { 8535 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL); 8536 if (!ret) 8537 hclge_update_umv_space(vport, false); 8538 mutex_unlock(&hdev->vport_lock); 8539 return ret; 8540 } 8541 mutex_unlock(&hdev->vport_lock); 8542 8543 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE)) 8544 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n", 8545 hdev->priv_umv_size); 8546 8547 return -ENOSPC; 8548 } 8549 8550 /* check if we just hit the duplicate */ 8551 if (!ret) 8552 return -EEXIST; 8553 8554 return ret; 8555 } 8556 8557 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 8558 const unsigned char *addr) 8559 { 8560 struct hclge_vport *vport = hclge_get_vport(handle); 8561 8562 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC, 8563 addr); 8564 } 8565 8566 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 8567 const unsigned char *addr) 8568 { 8569 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8570 struct hclge_dev *hdev = vport->back; 8571 struct hclge_mac_vlan_tbl_entry_cmd req; 8572 int ret; 8573 8574 /* mac addr check */ 8575 if (is_zero_ether_addr(addr) || 8576 is_broadcast_ether_addr(addr) || 8577 is_multicast_ether_addr(addr)) { 8578 hnae3_format_mac_addr(format_mac_addr, addr); 8579 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n", 8580 format_mac_addr); 8581 return -EINVAL; 8582 } 8583 8584 memset(&req, 0, sizeof(req)); 8585 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 8586 hclge_prepare_mac_addr(&req, addr, false); 8587 ret = hclge_remove_mac_vlan_tbl(vport, &req); 8588 if (!ret || ret == -ENOENT) { 8589 mutex_lock(&hdev->vport_lock); 8590 hclge_update_umv_space(vport, true); 8591 mutex_unlock(&hdev->vport_lock); 8592 return 0; 8593 } 8594 8595 return ret; 8596 } 8597 8598 static int hclge_add_mc_addr(struct hnae3_handle *handle, 8599 const unsigned char *addr) 8600 { 8601 struct hclge_vport *vport = hclge_get_vport(handle); 8602 8603 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC, 8604 addr); 8605 } 8606 8607 int hclge_add_mc_addr_common(struct hclge_vport *vport, 8608 const unsigned char *addr) 8609 { 8610 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8611 struct hclge_dev *hdev = vport->back; 8612 struct hclge_mac_vlan_tbl_entry_cmd req; 8613 struct hclge_desc desc[3]; 8614 bool is_new_addr = false; 8615 int status; 8616 8617 /* mac addr check */ 8618 if (!is_multicast_ether_addr(addr)) { 8619 hnae3_format_mac_addr(format_mac_addr, addr); 8620 dev_err(&hdev->pdev->dev, 8621 "Add mc mac err! invalid mac:%s.\n", 8622 format_mac_addr); 8623 return -EINVAL; 8624 } 8625 memset(&req, 0, sizeof(req)); 8626 hclge_prepare_mac_addr(&req, addr, true); 8627 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8628 if (status) { 8629 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) && 8630 hdev->used_mc_mac_num >= 8631 hdev->ae_dev->dev_specs.mc_mac_size) 8632 goto err_no_space; 8633 8634 is_new_addr = true; 8635 8636 /* This mac addr do not exist, add new entry for it */ 8637 memset(desc[0].data, 0, sizeof(desc[0].data)); 8638 memset(desc[1].data, 0, sizeof(desc[0].data)); 8639 memset(desc[2].data, 0, sizeof(desc[0].data)); 8640 } 8641 status = hclge_update_desc_vfid(desc, vport->vport_id, false); 8642 if (status) 8643 return status; 8644 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8645 if (status == -ENOSPC) 8646 goto err_no_space; 8647 else if (!status && is_new_addr) 8648 hdev->used_mc_mac_num++; 8649 8650 return status; 8651 8652 err_no_space: 8653 /* if already overflow, not to print each time */ 8654 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) { 8655 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8656 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n"); 8657 } 8658 8659 return -ENOSPC; 8660 } 8661 8662 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 8663 const unsigned char *addr) 8664 { 8665 struct hclge_vport *vport = hclge_get_vport(handle); 8666 8667 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC, 8668 addr); 8669 } 8670 8671 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 8672 const unsigned char *addr) 8673 { 8674 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8675 struct hclge_dev *hdev = vport->back; 8676 struct hclge_mac_vlan_tbl_entry_cmd req; 8677 enum hclge_comm_cmd_status status; 8678 struct hclge_desc desc[3]; 8679 8680 /* mac addr check */ 8681 if (!is_multicast_ether_addr(addr)) { 8682 hnae3_format_mac_addr(format_mac_addr, addr); 8683 dev_dbg(&hdev->pdev->dev, 8684 "Remove mc mac err! invalid mac:%s.\n", 8685 format_mac_addr); 8686 return -EINVAL; 8687 } 8688 8689 memset(&req, 0, sizeof(req)); 8690 hclge_prepare_mac_addr(&req, addr, true); 8691 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8692 if (!status) { 8693 /* This mac addr exist, remove this handle's VFID for it */ 8694 status = hclge_update_desc_vfid(desc, vport->vport_id, true); 8695 if (status) 8696 return status; 8697 8698 if (hclge_is_all_function_id_zero(desc)) { 8699 /* All the vfid is zero, so need to delete this entry */ 8700 status = hclge_remove_mac_vlan_tbl(vport, &req); 8701 if (!status) 8702 hdev->used_mc_mac_num--; 8703 } else { 8704 /* Not all the vfid is zero, update the vfid */ 8705 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8706 } 8707 } else if (status == -ENOENT) { 8708 status = 0; 8709 } 8710 8711 return status; 8712 } 8713 8714 static void hclge_sync_vport_mac_list(struct hclge_vport *vport, 8715 struct list_head *list, 8716 enum HCLGE_MAC_ADDR_TYPE mac_type) 8717 { 8718 int (*sync)(struct hclge_vport *vport, const unsigned char *addr); 8719 struct hclge_mac_node *mac_node, *tmp; 8720 int ret; 8721 8722 if (mac_type == HCLGE_MAC_ADDR_UC) 8723 sync = hclge_add_uc_addr_common; 8724 else 8725 sync = hclge_add_mc_addr_common; 8726 8727 list_for_each_entry_safe(mac_node, tmp, list, node) { 8728 ret = sync(vport, mac_node->mac_addr); 8729 if (!ret) { 8730 mac_node->state = HCLGE_MAC_ACTIVE; 8731 } else { 8732 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8733 &vport->state); 8734 8735 /* If one unicast mac address is existing in hardware, 8736 * we need to try whether other unicast mac addresses 8737 * are new addresses that can be added. 8738 * Multicast mac address can be reusable, even though 8739 * there is no space to add new multicast mac address, 8740 * we should check whether other mac addresses are 8741 * existing in hardware for reuse. 8742 */ 8743 if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) || 8744 (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC)) 8745 break; 8746 } 8747 } 8748 } 8749 8750 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport, 8751 struct list_head *list, 8752 enum HCLGE_MAC_ADDR_TYPE mac_type) 8753 { 8754 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 8755 struct hclge_mac_node *mac_node, *tmp; 8756 int ret; 8757 8758 if (mac_type == HCLGE_MAC_ADDR_UC) 8759 unsync = hclge_rm_uc_addr_common; 8760 else 8761 unsync = hclge_rm_mc_addr_common; 8762 8763 list_for_each_entry_safe(mac_node, tmp, list, node) { 8764 ret = unsync(vport, mac_node->mac_addr); 8765 if (!ret || ret == -ENOENT) { 8766 list_del(&mac_node->node); 8767 kfree(mac_node); 8768 } else { 8769 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8770 &vport->state); 8771 break; 8772 } 8773 } 8774 } 8775 8776 static bool hclge_sync_from_add_list(struct list_head *add_list, 8777 struct list_head *mac_list) 8778 { 8779 struct hclge_mac_node *mac_node, *tmp, *new_node; 8780 bool all_added = true; 8781 8782 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 8783 if (mac_node->state == HCLGE_MAC_TO_ADD) 8784 all_added = false; 8785 8786 /* if the mac address from tmp_add_list is not in the 8787 * uc/mc_mac_list, it means have received a TO_DEL request 8788 * during the time window of adding the mac address into mac 8789 * table. if mac_node state is ACTIVE, then change it to TO_DEL, 8790 * then it will be removed at next time. else it must be TO_ADD, 8791 * this address hasn't been added into mac table, 8792 * so just remove the mac node. 8793 */ 8794 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8795 if (new_node) { 8796 hclge_update_mac_node(new_node, mac_node->state); 8797 list_del(&mac_node->node); 8798 kfree(mac_node); 8799 } else if (mac_node->state == HCLGE_MAC_ACTIVE) { 8800 mac_node->state = HCLGE_MAC_TO_DEL; 8801 list_move_tail(&mac_node->node, mac_list); 8802 } else { 8803 list_del(&mac_node->node); 8804 kfree(mac_node); 8805 } 8806 } 8807 8808 return all_added; 8809 } 8810 8811 static void hclge_sync_from_del_list(struct list_head *del_list, 8812 struct list_head *mac_list) 8813 { 8814 struct hclge_mac_node *mac_node, *tmp, *new_node; 8815 8816 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 8817 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8818 if (new_node) { 8819 /* If the mac addr exists in the mac list, it means 8820 * received a new TO_ADD request during the time window 8821 * of configuring the mac address. For the mac node 8822 * state is TO_ADD, and the address is already in the 8823 * in the hardware(due to delete fail), so we just need 8824 * to change the mac node state to ACTIVE. 8825 */ 8826 new_node->state = HCLGE_MAC_ACTIVE; 8827 list_del(&mac_node->node); 8828 kfree(mac_node); 8829 } else { 8830 list_move_tail(&mac_node->node, mac_list); 8831 } 8832 } 8833 } 8834 8835 static void hclge_update_overflow_flags(struct hclge_vport *vport, 8836 enum HCLGE_MAC_ADDR_TYPE mac_type, 8837 bool is_all_added) 8838 { 8839 if (mac_type == HCLGE_MAC_ADDR_UC) { 8840 if (is_all_added) 8841 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE; 8842 else if (hclge_is_umv_space_full(vport, true)) 8843 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE; 8844 } else { 8845 if (is_all_added) 8846 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE; 8847 else 8848 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8849 } 8850 } 8851 8852 static void hclge_sync_vport_mac_table(struct hclge_vport *vport, 8853 enum HCLGE_MAC_ADDR_TYPE mac_type) 8854 { 8855 struct hclge_mac_node *mac_node, *tmp, *new_node; 8856 struct list_head tmp_add_list, tmp_del_list; 8857 struct list_head *list; 8858 bool all_added; 8859 8860 INIT_LIST_HEAD(&tmp_add_list); 8861 INIT_LIST_HEAD(&tmp_del_list); 8862 8863 /* move the mac addr to the tmp_add_list and tmp_del_list, then 8864 * we can add/delete these mac addr outside the spin lock 8865 */ 8866 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8867 &vport->uc_mac_list : &vport->mc_mac_list; 8868 8869 spin_lock_bh(&vport->mac_list_lock); 8870 8871 list_for_each_entry_safe(mac_node, tmp, list, node) { 8872 switch (mac_node->state) { 8873 case HCLGE_MAC_TO_DEL: 8874 list_move_tail(&mac_node->node, &tmp_del_list); 8875 break; 8876 case HCLGE_MAC_TO_ADD: 8877 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 8878 if (!new_node) 8879 goto stop_traverse; 8880 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 8881 new_node->state = mac_node->state; 8882 list_add_tail(&new_node->node, &tmp_add_list); 8883 break; 8884 default: 8885 break; 8886 } 8887 } 8888 8889 stop_traverse: 8890 spin_unlock_bh(&vport->mac_list_lock); 8891 8892 /* delete first, in order to get max mac table space for adding */ 8893 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 8894 hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type); 8895 8896 /* if some mac addresses were added/deleted fail, move back to the 8897 * mac_list, and retry at next time. 8898 */ 8899 spin_lock_bh(&vport->mac_list_lock); 8900 8901 hclge_sync_from_del_list(&tmp_del_list, list); 8902 all_added = hclge_sync_from_add_list(&tmp_add_list, list); 8903 8904 spin_unlock_bh(&vport->mac_list_lock); 8905 8906 hclge_update_overflow_flags(vport, mac_type, all_added); 8907 } 8908 8909 static bool hclge_need_sync_mac_table(struct hclge_vport *vport) 8910 { 8911 struct hclge_dev *hdev = vport->back; 8912 8913 if (test_bit(vport->vport_id, hdev->vport_config_block)) 8914 return false; 8915 8916 if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state)) 8917 return true; 8918 8919 return false; 8920 } 8921 8922 static void hclge_sync_mac_table(struct hclge_dev *hdev) 8923 { 8924 int i; 8925 8926 for (i = 0; i < hdev->num_alloc_vport; i++) { 8927 struct hclge_vport *vport = &hdev->vport[i]; 8928 8929 if (!hclge_need_sync_mac_table(vport)) 8930 continue; 8931 8932 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC); 8933 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC); 8934 } 8935 } 8936 8937 static void hclge_build_del_list(struct list_head *list, 8938 bool is_del_list, 8939 struct list_head *tmp_del_list) 8940 { 8941 struct hclge_mac_node *mac_cfg, *tmp; 8942 8943 list_for_each_entry_safe(mac_cfg, tmp, list, node) { 8944 switch (mac_cfg->state) { 8945 case HCLGE_MAC_TO_DEL: 8946 case HCLGE_MAC_ACTIVE: 8947 list_move_tail(&mac_cfg->node, tmp_del_list); 8948 break; 8949 case HCLGE_MAC_TO_ADD: 8950 if (is_del_list) { 8951 list_del(&mac_cfg->node); 8952 kfree(mac_cfg); 8953 } 8954 break; 8955 } 8956 } 8957 } 8958 8959 static void hclge_unsync_del_list(struct hclge_vport *vport, 8960 int (*unsync)(struct hclge_vport *vport, 8961 const unsigned char *addr), 8962 bool is_del_list, 8963 struct list_head *tmp_del_list) 8964 { 8965 struct hclge_mac_node *mac_cfg, *tmp; 8966 int ret; 8967 8968 list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) { 8969 ret = unsync(vport, mac_cfg->mac_addr); 8970 if (!ret || ret == -ENOENT) { 8971 /* clear all mac addr from hardware, but remain these 8972 * mac addr in the mac list, and restore them after 8973 * vf reset finished. 8974 */ 8975 if (!is_del_list && 8976 mac_cfg->state == HCLGE_MAC_ACTIVE) { 8977 mac_cfg->state = HCLGE_MAC_TO_ADD; 8978 } else { 8979 list_del(&mac_cfg->node); 8980 kfree(mac_cfg); 8981 } 8982 } else if (is_del_list) { 8983 mac_cfg->state = HCLGE_MAC_TO_DEL; 8984 } 8985 } 8986 } 8987 8988 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 8989 enum HCLGE_MAC_ADDR_TYPE mac_type) 8990 { 8991 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 8992 struct hclge_dev *hdev = vport->back; 8993 struct list_head tmp_del_list, *list; 8994 8995 if (mac_type == HCLGE_MAC_ADDR_UC) { 8996 list = &vport->uc_mac_list; 8997 unsync = hclge_rm_uc_addr_common; 8998 } else { 8999 list = &vport->mc_mac_list; 9000 unsync = hclge_rm_mc_addr_common; 9001 } 9002 9003 INIT_LIST_HEAD(&tmp_del_list); 9004 9005 if (!is_del_list) 9006 set_bit(vport->vport_id, hdev->vport_config_block); 9007 9008 spin_lock_bh(&vport->mac_list_lock); 9009 9010 hclge_build_del_list(list, is_del_list, &tmp_del_list); 9011 9012 spin_unlock_bh(&vport->mac_list_lock); 9013 9014 hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list); 9015 9016 spin_lock_bh(&vport->mac_list_lock); 9017 9018 hclge_sync_from_del_list(&tmp_del_list, list); 9019 9020 spin_unlock_bh(&vport->mac_list_lock); 9021 } 9022 9023 /* remove all mac address when uninitailize */ 9024 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport, 9025 enum HCLGE_MAC_ADDR_TYPE mac_type) 9026 { 9027 struct hclge_mac_node *mac_node, *tmp; 9028 struct hclge_dev *hdev = vport->back; 9029 struct list_head tmp_del_list, *list; 9030 9031 INIT_LIST_HEAD(&tmp_del_list); 9032 9033 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 9034 &vport->uc_mac_list : &vport->mc_mac_list; 9035 9036 spin_lock_bh(&vport->mac_list_lock); 9037 9038 list_for_each_entry_safe(mac_node, tmp, list, node) { 9039 switch (mac_node->state) { 9040 case HCLGE_MAC_TO_DEL: 9041 case HCLGE_MAC_ACTIVE: 9042 list_move_tail(&mac_node->node, &tmp_del_list); 9043 break; 9044 case HCLGE_MAC_TO_ADD: 9045 list_del(&mac_node->node); 9046 kfree(mac_node); 9047 break; 9048 } 9049 } 9050 9051 spin_unlock_bh(&vport->mac_list_lock); 9052 9053 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 9054 9055 if (!list_empty(&tmp_del_list)) 9056 dev_warn(&hdev->pdev->dev, 9057 "uninit %s mac list for vport %u not completely.\n", 9058 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc", 9059 vport->vport_id); 9060 9061 list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) { 9062 list_del(&mac_node->node); 9063 kfree(mac_node); 9064 } 9065 } 9066 9067 static void hclge_uninit_mac_table(struct hclge_dev *hdev) 9068 { 9069 struct hclge_vport *vport; 9070 int i; 9071 9072 for (i = 0; i < hdev->num_alloc_vport; i++) { 9073 vport = &hdev->vport[i]; 9074 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC); 9075 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC); 9076 } 9077 } 9078 9079 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 9080 u16 cmdq_resp, u8 resp_code) 9081 { 9082 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 9083 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 9084 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 9085 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 9086 9087 int return_status; 9088 9089 if (cmdq_resp) { 9090 dev_err(&hdev->pdev->dev, 9091 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 9092 cmdq_resp); 9093 return -EIO; 9094 } 9095 9096 switch (resp_code) { 9097 case HCLGE_ETHERTYPE_SUCCESS_ADD: 9098 case HCLGE_ETHERTYPE_ALREADY_ADD: 9099 return_status = 0; 9100 break; 9101 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 9102 dev_err(&hdev->pdev->dev, 9103 "add mac ethertype failed for manager table overflow.\n"); 9104 return_status = -EIO; 9105 break; 9106 case HCLGE_ETHERTYPE_KEY_CONFLICT: 9107 dev_err(&hdev->pdev->dev, 9108 "add mac ethertype failed for key conflict.\n"); 9109 return_status = -EIO; 9110 break; 9111 default: 9112 dev_err(&hdev->pdev->dev, 9113 "add mac ethertype failed for undefined, code=%u.\n", 9114 resp_code); 9115 return_status = -EIO; 9116 } 9117 9118 return return_status; 9119 } 9120 9121 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf, 9122 u8 *mac_addr) 9123 { 9124 struct hclge_vport *vport = hclge_get_vport(handle); 9125 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9126 struct hclge_dev *hdev = vport->back; 9127 9128 vport = hclge_get_vf_vport(hdev, vf); 9129 if (!vport) 9130 return -EINVAL; 9131 9132 hnae3_format_mac_addr(format_mac_addr, mac_addr); 9133 if (ether_addr_equal(mac_addr, vport->vf_info.mac)) { 9134 dev_info(&hdev->pdev->dev, 9135 "Specified MAC(=%s) is same as before, no change committed!\n", 9136 format_mac_addr); 9137 return 0; 9138 } 9139 9140 ether_addr_copy(vport->vf_info.mac, mac_addr); 9141 9142 /* there is a timewindow for PF to know VF unalive, it may 9143 * cause send mailbox fail, but it doesn't matter, VF will 9144 * query it when reinit. 9145 */ 9146 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) { 9147 dev_info(&hdev->pdev->dev, 9148 "MAC of VF %d has been set to %s, and it will be reinitialized!\n", 9149 vf, format_mac_addr); 9150 (void)hclge_inform_reset_assert_to_vf(vport); 9151 return 0; 9152 } 9153 9154 dev_info(&hdev->pdev->dev, 9155 "MAC of VF %d has been set to %s, will be active after VF reset\n", 9156 vf, format_mac_addr); 9157 return 0; 9158 } 9159 9160 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 9161 const struct hclge_mac_mgr_tbl_entry_cmd *req) 9162 { 9163 struct hclge_desc desc; 9164 u8 resp_code; 9165 u16 retval; 9166 int ret; 9167 9168 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 9169 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 9170 9171 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9172 if (ret) { 9173 dev_err(&hdev->pdev->dev, 9174 "add mac ethertype failed for cmd_send, ret =%d.\n", 9175 ret); 9176 return ret; 9177 } 9178 9179 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 9180 retval = le16_to_cpu(desc.retval); 9181 9182 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 9183 } 9184 9185 static int init_mgr_tbl(struct hclge_dev *hdev) 9186 { 9187 int ret; 9188 int i; 9189 9190 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 9191 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 9192 if (ret) { 9193 dev_err(&hdev->pdev->dev, 9194 "add mac ethertype failed, ret =%d.\n", 9195 ret); 9196 return ret; 9197 } 9198 } 9199 9200 return 0; 9201 } 9202 9203 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 9204 { 9205 struct hclge_vport *vport = hclge_get_vport(handle); 9206 struct hclge_dev *hdev = vport->back; 9207 9208 ether_addr_copy(p, hdev->hw.mac.mac_addr); 9209 } 9210 9211 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 9212 const u8 *old_addr, const u8 *new_addr) 9213 { 9214 struct list_head *list = &vport->uc_mac_list; 9215 struct hclge_mac_node *old_node, *new_node; 9216 9217 new_node = hclge_find_mac_node(list, new_addr); 9218 if (!new_node) { 9219 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 9220 if (!new_node) 9221 return -ENOMEM; 9222 9223 new_node->state = HCLGE_MAC_TO_ADD; 9224 ether_addr_copy(new_node->mac_addr, new_addr); 9225 list_add(&new_node->node, list); 9226 } else { 9227 if (new_node->state == HCLGE_MAC_TO_DEL) 9228 new_node->state = HCLGE_MAC_ACTIVE; 9229 9230 /* make sure the new addr is in the list head, avoid dev 9231 * addr may be not re-added into mac table for the umv space 9232 * limitation after global/imp reset which will clear mac 9233 * table by hardware. 9234 */ 9235 list_move(&new_node->node, list); 9236 } 9237 9238 if (old_addr && !ether_addr_equal(old_addr, new_addr)) { 9239 old_node = hclge_find_mac_node(list, old_addr); 9240 if (old_node) { 9241 if (old_node->state == HCLGE_MAC_TO_ADD) { 9242 list_del(&old_node->node); 9243 kfree(old_node); 9244 } else { 9245 old_node->state = HCLGE_MAC_TO_DEL; 9246 } 9247 } 9248 } 9249 9250 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 9251 9252 return 0; 9253 } 9254 9255 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p, 9256 bool is_first) 9257 { 9258 const unsigned char *new_addr = (const unsigned char *)p; 9259 struct hclge_vport *vport = hclge_get_vport(handle); 9260 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9261 struct hclge_dev *hdev = vport->back; 9262 unsigned char *old_addr = NULL; 9263 int ret; 9264 9265 /* mac addr check */ 9266 if (is_zero_ether_addr(new_addr) || 9267 is_broadcast_ether_addr(new_addr) || 9268 is_multicast_ether_addr(new_addr)) { 9269 hnae3_format_mac_addr(format_mac_addr, new_addr); 9270 dev_err(&hdev->pdev->dev, 9271 "change uc mac err! invalid mac: %s.\n", 9272 format_mac_addr); 9273 return -EINVAL; 9274 } 9275 9276 ret = hclge_pause_addr_cfg(hdev, new_addr); 9277 if (ret) { 9278 dev_err(&hdev->pdev->dev, 9279 "failed to configure mac pause address, ret = %d\n", 9280 ret); 9281 return ret; 9282 } 9283 9284 if (!is_first) 9285 old_addr = hdev->hw.mac.mac_addr; 9286 9287 spin_lock_bh(&vport->mac_list_lock); 9288 ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr); 9289 if (ret) { 9290 hnae3_format_mac_addr(format_mac_addr, new_addr); 9291 dev_err(&hdev->pdev->dev, 9292 "failed to change the mac addr:%s, ret = %d\n", 9293 format_mac_addr, ret); 9294 spin_unlock_bh(&vport->mac_list_lock); 9295 9296 if (!is_first) 9297 hclge_pause_addr_cfg(hdev, old_addr); 9298 9299 return ret; 9300 } 9301 /* we must update dev addr with spin lock protect, preventing dev addr 9302 * being removed by set_rx_mode path. 9303 */ 9304 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 9305 spin_unlock_bh(&vport->mac_list_lock); 9306 9307 hclge_task_schedule(hdev, 0); 9308 9309 return 0; 9310 } 9311 9312 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd) 9313 { 9314 struct mii_ioctl_data *data = if_mii(ifr); 9315 9316 if (!hnae3_dev_phy_imp_supported(hdev)) 9317 return -EOPNOTSUPP; 9318 9319 switch (cmd) { 9320 case SIOCGMIIPHY: 9321 data->phy_id = hdev->hw.mac.phy_addr; 9322 /* this command reads phy id and register at the same time */ 9323 fallthrough; 9324 case SIOCGMIIREG: 9325 data->val_out = hclge_read_phy_reg(hdev, data->reg_num); 9326 return 0; 9327 9328 case SIOCSMIIREG: 9329 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in); 9330 default: 9331 return -EOPNOTSUPP; 9332 } 9333 } 9334 9335 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr, 9336 int cmd) 9337 { 9338 struct hclge_vport *vport = hclge_get_vport(handle); 9339 struct hclge_dev *hdev = vport->back; 9340 9341 switch (cmd) { 9342 case SIOCGHWTSTAMP: 9343 return hclge_ptp_get_cfg(hdev, ifr); 9344 case SIOCSHWTSTAMP: 9345 return hclge_ptp_set_cfg(hdev, ifr); 9346 default: 9347 if (!hdev->hw.mac.phydev) 9348 return hclge_mii_ioctl(hdev, ifr, cmd); 9349 } 9350 9351 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd); 9352 } 9353 9354 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id, 9355 bool bypass_en) 9356 { 9357 struct hclge_port_vlan_filter_bypass_cmd *req; 9358 struct hclge_desc desc; 9359 int ret; 9360 9361 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false); 9362 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 9363 req->vf_id = vf_id; 9364 hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B, 9365 bypass_en ? 1 : 0); 9366 9367 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9368 if (ret) 9369 dev_err(&hdev->pdev->dev, 9370 "failed to set vport%u port vlan filter bypass state, ret = %d.\n", 9371 vf_id, ret); 9372 9373 return ret; 9374 } 9375 9376 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 9377 u8 fe_type, bool filter_en, u8 vf_id) 9378 { 9379 struct hclge_vlan_filter_ctrl_cmd *req; 9380 struct hclge_desc desc; 9381 int ret; 9382 9383 /* read current vlan filter parameter */ 9384 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 9385 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 9386 req->vlan_type = vlan_type; 9387 req->vf_id = vf_id; 9388 9389 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9390 if (ret) { 9391 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n", 9392 vf_id, ret); 9393 return ret; 9394 } 9395 9396 /* modify and write new config parameter */ 9397 hclge_comm_cmd_reuse_desc(&desc, false); 9398 req->vlan_fe = filter_en ? 9399 (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type); 9400 9401 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9402 if (ret) 9403 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n", 9404 vf_id, ret); 9405 9406 return ret; 9407 } 9408 9409 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable) 9410 { 9411 struct hclge_dev *hdev = vport->back; 9412 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 9413 int ret; 9414 9415 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9416 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9417 HCLGE_FILTER_FE_EGRESS_V1_B, 9418 enable, vport->vport_id); 9419 9420 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9421 HCLGE_FILTER_FE_EGRESS, enable, 9422 vport->vport_id); 9423 if (ret) 9424 return ret; 9425 9426 if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) { 9427 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id, 9428 !enable); 9429 } else if (!vport->vport_id) { 9430 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 9431 enable = false; 9432 9433 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9434 HCLGE_FILTER_FE_INGRESS, 9435 enable, 0); 9436 } 9437 9438 return ret; 9439 } 9440 9441 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport) 9442 { 9443 struct hnae3_handle *handle = &vport->nic; 9444 struct hclge_vport_vlan_cfg *vlan, *tmp; 9445 struct hclge_dev *hdev = vport->back; 9446 9447 if (vport->vport_id) { 9448 if (vport->port_base_vlan_cfg.state != 9449 HNAE3_PORT_BASE_VLAN_DISABLE) 9450 return true; 9451 9452 if (vport->vf_info.trusted && vport->vf_info.request_uc_en) 9453 return false; 9454 } else if (handle->netdev_flags & HNAE3_USER_UPE) { 9455 return false; 9456 } 9457 9458 if (!vport->req_vlan_fltr_en) 9459 return false; 9460 9461 /* compatible with former device, always enable vlan filter */ 9462 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 9463 return true; 9464 9465 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) 9466 if (vlan->vlan_id != 0) 9467 return true; 9468 9469 return false; 9470 } 9471 9472 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) 9473 { 9474 struct hclge_dev *hdev = vport->back; 9475 bool need_en; 9476 int ret; 9477 9478 mutex_lock(&hdev->vport_lock); 9479 9480 vport->req_vlan_fltr_en = request_en; 9481 9482 need_en = hclge_need_enable_vport_vlan_filter(vport); 9483 if (need_en == vport->cur_vlan_fltr_en) { 9484 mutex_unlock(&hdev->vport_lock); 9485 return 0; 9486 } 9487 9488 ret = hclge_set_vport_vlan_filter(vport, need_en); 9489 if (ret) { 9490 mutex_unlock(&hdev->vport_lock); 9491 return ret; 9492 } 9493 9494 vport->cur_vlan_fltr_en = need_en; 9495 9496 mutex_unlock(&hdev->vport_lock); 9497 9498 return 0; 9499 } 9500 9501 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 9502 { 9503 struct hclge_vport *vport = hclge_get_vport(handle); 9504 9505 return hclge_enable_vport_vlan_filter(vport, enable); 9506 } 9507 9508 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid, 9509 bool is_kill, u16 vlan, 9510 struct hclge_desc *desc) 9511 { 9512 struct hclge_vlan_filter_vf_cfg_cmd *req0; 9513 struct hclge_vlan_filter_vf_cfg_cmd *req1; 9514 u8 vf_byte_val; 9515 u8 vf_byte_off; 9516 int ret; 9517 9518 hclge_cmd_setup_basic_desc(&desc[0], 9519 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9520 hclge_cmd_setup_basic_desc(&desc[1], 9521 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9522 9523 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 9524 9525 vf_byte_off = vfid / 8; 9526 vf_byte_val = 1 << (vfid % 8); 9527 9528 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9529 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 9530 9531 req0->vlan_id = cpu_to_le16(vlan); 9532 req0->vlan_cfg = is_kill; 9533 9534 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 9535 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 9536 else 9537 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 9538 9539 ret = hclge_cmd_send(&hdev->hw, desc, 2); 9540 if (ret) { 9541 dev_err(&hdev->pdev->dev, 9542 "Send vf vlan command fail, ret =%d.\n", 9543 ret); 9544 return ret; 9545 } 9546 9547 return 0; 9548 } 9549 9550 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid, 9551 bool is_kill, struct hclge_desc *desc) 9552 { 9553 struct hclge_vlan_filter_vf_cfg_cmd *req; 9554 9555 req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9556 9557 if (!is_kill) { 9558 #define HCLGE_VF_VLAN_NO_ENTRY 2 9559 if (!req->resp_code || req->resp_code == 1) 9560 return 0; 9561 9562 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 9563 set_bit(vfid, hdev->vf_vlan_full); 9564 dev_warn(&hdev->pdev->dev, 9565 "vf vlan table is full, vf vlan filter is disabled\n"); 9566 return 0; 9567 } 9568 9569 dev_err(&hdev->pdev->dev, 9570 "Add vf vlan filter fail, ret =%u.\n", 9571 req->resp_code); 9572 } else { 9573 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 9574 if (!req->resp_code) 9575 return 0; 9576 9577 /* vf vlan filter is disabled when vf vlan table is full, 9578 * then new vlan id will not be added into vf vlan table. 9579 * Just return 0 without warning, avoid massive verbose 9580 * print logs when unload. 9581 */ 9582 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) 9583 return 0; 9584 9585 dev_err(&hdev->pdev->dev, 9586 "Kill vf vlan filter fail, ret =%u.\n", 9587 req->resp_code); 9588 } 9589 9590 return -EIO; 9591 } 9592 9593 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid, 9594 bool is_kill, u16 vlan) 9595 { 9596 struct hclge_vport *vport = &hdev->vport[vfid]; 9597 struct hclge_desc desc[2]; 9598 int ret; 9599 9600 /* if vf vlan table is full, firmware will close vf vlan filter, it 9601 * is unable and unnecessary to add new vlan id to vf vlan filter. 9602 * If spoof check is enable, and vf vlan is full, it shouldn't add 9603 * new vlan, because tx packets with these vlan id will be dropped. 9604 */ 9605 if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) { 9606 if (vport->vf_info.spoofchk && vlan) { 9607 dev_err(&hdev->pdev->dev, 9608 "Can't add vlan due to spoof check is on and vf vlan table is full\n"); 9609 return -EPERM; 9610 } 9611 return 0; 9612 } 9613 9614 ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc); 9615 if (ret) 9616 return ret; 9617 9618 return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc); 9619 } 9620 9621 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 9622 u16 vlan_id, bool is_kill) 9623 { 9624 struct hclge_vlan_filter_pf_cfg_cmd *req; 9625 struct hclge_desc desc; 9626 u8 vlan_offset_byte_val; 9627 u8 vlan_offset_byte; 9628 u8 vlan_offset_160; 9629 int ret; 9630 9631 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 9632 9633 vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP; 9634 vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) / 9635 HCLGE_VLAN_BYTE_SIZE; 9636 vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE); 9637 9638 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 9639 req->vlan_offset = vlan_offset_160; 9640 req->vlan_cfg = is_kill; 9641 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 9642 9643 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9644 if (ret) 9645 dev_err(&hdev->pdev->dev, 9646 "port vlan command, send fail, ret =%d.\n", ret); 9647 return ret; 9648 } 9649 9650 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id, 9651 u16 vlan_id, bool is_kill) 9652 { 9653 /* vlan 0 may be added twice when 8021q module is enabled */ 9654 if (!is_kill && !vlan_id && 9655 test_bit(vport_id, hdev->vlan_table[vlan_id])) 9656 return false; 9657 9658 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 9659 dev_warn(&hdev->pdev->dev, 9660 "Add port vlan failed, vport %u is already in vlan %u\n", 9661 vport_id, vlan_id); 9662 return false; 9663 } 9664 9665 if (is_kill && 9666 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 9667 dev_warn(&hdev->pdev->dev, 9668 "Delete port vlan failed, vport %u is not in vlan %u\n", 9669 vport_id, vlan_id); 9670 return false; 9671 } 9672 9673 return true; 9674 } 9675 9676 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 9677 u16 vport_id, u16 vlan_id, 9678 bool is_kill) 9679 { 9680 u16 vport_idx, vport_num = 0; 9681 int ret; 9682 9683 if (is_kill && !vlan_id) 9684 return 0; 9685 9686 if (vlan_id >= VLAN_N_VID) 9687 return -EINVAL; 9688 9689 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id); 9690 if (ret) { 9691 dev_err(&hdev->pdev->dev, 9692 "Set %u vport vlan filter config fail, ret =%d.\n", 9693 vport_id, ret); 9694 return ret; 9695 } 9696 9697 if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill)) 9698 return 0; 9699 9700 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 9701 vport_num++; 9702 9703 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 9704 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 9705 is_kill); 9706 9707 return ret; 9708 } 9709 9710 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 9711 { 9712 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 9713 struct hclge_vport_vtag_tx_cfg_cmd *req; 9714 struct hclge_dev *hdev = vport->back; 9715 struct hclge_desc desc; 9716 u16 bmap_index; 9717 int status; 9718 9719 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 9720 9721 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 9722 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 9723 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 9724 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 9725 vcfg->accept_tag1 ? 1 : 0); 9726 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 9727 vcfg->accept_untag1 ? 1 : 0); 9728 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 9729 vcfg->accept_tag2 ? 1 : 0); 9730 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 9731 vcfg->accept_untag2 ? 1 : 0); 9732 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 9733 vcfg->insert_tag1_en ? 1 : 0); 9734 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 9735 vcfg->insert_tag2_en ? 1 : 0); 9736 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B, 9737 vcfg->tag_shift_mode_en ? 1 : 0); 9738 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 9739 9740 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9741 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9742 HCLGE_VF_NUM_PER_BYTE; 9743 req->vf_bitmap[bmap_index] = 9744 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9745 9746 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9747 if (status) 9748 dev_err(&hdev->pdev->dev, 9749 "Send port txvlan cfg command fail, ret =%d\n", 9750 status); 9751 9752 return status; 9753 } 9754 9755 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 9756 { 9757 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 9758 struct hclge_vport_vtag_rx_cfg_cmd *req; 9759 struct hclge_dev *hdev = vport->back; 9760 struct hclge_desc desc; 9761 u16 bmap_index; 9762 int status; 9763 9764 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 9765 9766 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 9767 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 9768 vcfg->strip_tag1_en ? 1 : 0); 9769 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 9770 vcfg->strip_tag2_en ? 1 : 0); 9771 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 9772 vcfg->vlan1_vlan_prionly ? 1 : 0); 9773 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 9774 vcfg->vlan2_vlan_prionly ? 1 : 0); 9775 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B, 9776 vcfg->strip_tag1_discard_en ? 1 : 0); 9777 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B, 9778 vcfg->strip_tag2_discard_en ? 1 : 0); 9779 9780 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9781 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9782 HCLGE_VF_NUM_PER_BYTE; 9783 req->vf_bitmap[bmap_index] = 9784 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9785 9786 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9787 if (status) 9788 dev_err(&hdev->pdev->dev, 9789 "Send port rxvlan cfg command fail, ret =%d\n", 9790 status); 9791 9792 return status; 9793 } 9794 9795 static int hclge_vlan_offload_cfg(struct hclge_vport *vport, 9796 u16 port_base_vlan_state, 9797 u16 vlan_tag, u8 qos) 9798 { 9799 int ret; 9800 9801 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9802 vport->txvlan_cfg.accept_tag1 = true; 9803 vport->txvlan_cfg.insert_tag1_en = false; 9804 vport->txvlan_cfg.default_tag1 = 0; 9805 } else { 9806 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev); 9807 9808 vport->txvlan_cfg.accept_tag1 = 9809 ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3; 9810 vport->txvlan_cfg.insert_tag1_en = true; 9811 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) | 9812 vlan_tag; 9813 } 9814 9815 vport->txvlan_cfg.accept_untag1 = true; 9816 9817 /* accept_tag2 and accept_untag2 are not supported on 9818 * pdev revision(0x20), new revision support them, 9819 * this two fields can not be configured by user. 9820 */ 9821 vport->txvlan_cfg.accept_tag2 = true; 9822 vport->txvlan_cfg.accept_untag2 = true; 9823 vport->txvlan_cfg.insert_tag2_en = false; 9824 vport->txvlan_cfg.default_tag2 = 0; 9825 vport->txvlan_cfg.tag_shift_mode_en = true; 9826 9827 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9828 vport->rxvlan_cfg.strip_tag1_en = false; 9829 vport->rxvlan_cfg.strip_tag2_en = 9830 vport->rxvlan_cfg.rx_vlan_offload_en; 9831 vport->rxvlan_cfg.strip_tag2_discard_en = false; 9832 } else { 9833 vport->rxvlan_cfg.strip_tag1_en = 9834 vport->rxvlan_cfg.rx_vlan_offload_en; 9835 vport->rxvlan_cfg.strip_tag2_en = true; 9836 vport->rxvlan_cfg.strip_tag2_discard_en = true; 9837 } 9838 9839 vport->rxvlan_cfg.strip_tag1_discard_en = false; 9840 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 9841 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 9842 9843 ret = hclge_set_vlan_tx_offload_cfg(vport); 9844 if (ret) 9845 return ret; 9846 9847 return hclge_set_vlan_rx_offload_cfg(vport); 9848 } 9849 9850 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 9851 { 9852 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 9853 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 9854 struct hclge_desc desc; 9855 int status; 9856 9857 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 9858 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 9859 rx_req->ot_fst_vlan_type = 9860 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 9861 rx_req->ot_sec_vlan_type = 9862 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 9863 rx_req->in_fst_vlan_type = 9864 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 9865 rx_req->in_sec_vlan_type = 9866 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 9867 9868 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9869 if (status) { 9870 dev_err(&hdev->pdev->dev, 9871 "Send rxvlan protocol type command fail, ret =%d\n", 9872 status); 9873 return status; 9874 } 9875 9876 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 9877 9878 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data; 9879 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 9880 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 9881 9882 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9883 if (status) 9884 dev_err(&hdev->pdev->dev, 9885 "Send txvlan protocol type command fail, ret =%d\n", 9886 status); 9887 9888 return status; 9889 } 9890 9891 static int hclge_init_vlan_filter(struct hclge_dev *hdev) 9892 { 9893 struct hclge_vport *vport; 9894 int ret; 9895 int i; 9896 9897 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9898 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9899 HCLGE_FILTER_FE_EGRESS_V1_B, 9900 true, 0); 9901 9902 /* for revision 0x21, vf vlan filter is per function */ 9903 for (i = 0; i < hdev->num_alloc_vport; i++) { 9904 vport = &hdev->vport[i]; 9905 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9906 HCLGE_FILTER_FE_EGRESS, true, 9907 vport->vport_id); 9908 if (ret) 9909 return ret; 9910 vport->cur_vlan_fltr_en = true; 9911 } 9912 9913 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9914 HCLGE_FILTER_FE_INGRESS, true, 0); 9915 } 9916 9917 static int hclge_init_vlan_type(struct hclge_dev *hdev) 9918 { 9919 hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q; 9920 hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q; 9921 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q; 9922 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q; 9923 hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q; 9924 hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q; 9925 9926 return hclge_set_vlan_protocol_type(hdev); 9927 } 9928 9929 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev) 9930 { 9931 struct hclge_port_base_vlan_config *cfg; 9932 struct hclge_vport *vport; 9933 int ret; 9934 int i; 9935 9936 for (i = 0; i < hdev->num_alloc_vport; i++) { 9937 vport = &hdev->vport[i]; 9938 cfg = &vport->port_base_vlan_cfg; 9939 9940 ret = hclge_vlan_offload_cfg(vport, cfg->state, 9941 cfg->vlan_info.vlan_tag, 9942 cfg->vlan_info.qos); 9943 if (ret) 9944 return ret; 9945 } 9946 return 0; 9947 } 9948 9949 static int hclge_init_vlan_config(struct hclge_dev *hdev) 9950 { 9951 struct hnae3_handle *handle = &hdev->vport[0].nic; 9952 int ret; 9953 9954 ret = hclge_init_vlan_filter(hdev); 9955 if (ret) 9956 return ret; 9957 9958 ret = hclge_init_vlan_type(hdev); 9959 if (ret) 9960 return ret; 9961 9962 ret = hclge_init_vport_vlan_offload(hdev); 9963 if (ret) 9964 return ret; 9965 9966 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 9967 } 9968 9969 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 9970 bool writen_to_tbl) 9971 { 9972 struct hclge_vport_vlan_cfg *vlan, *tmp; 9973 struct hclge_dev *hdev = vport->back; 9974 9975 mutex_lock(&hdev->vport_lock); 9976 9977 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 9978 if (vlan->vlan_id == vlan_id) { 9979 mutex_unlock(&hdev->vport_lock); 9980 return; 9981 } 9982 } 9983 9984 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 9985 if (!vlan) { 9986 mutex_unlock(&hdev->vport_lock); 9987 return; 9988 } 9989 9990 vlan->hd_tbl_status = writen_to_tbl; 9991 vlan->vlan_id = vlan_id; 9992 9993 list_add_tail(&vlan->node, &vport->vlan_list); 9994 mutex_unlock(&hdev->vport_lock); 9995 } 9996 9997 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport) 9998 { 9999 struct hclge_vport_vlan_cfg *vlan, *tmp; 10000 struct hclge_dev *hdev = vport->back; 10001 int ret; 10002 10003 mutex_lock(&hdev->vport_lock); 10004 10005 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10006 if (!vlan->hd_tbl_status) { 10007 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10008 vport->vport_id, 10009 vlan->vlan_id, false); 10010 if (ret) { 10011 dev_err(&hdev->pdev->dev, 10012 "restore vport vlan list failed, ret=%d\n", 10013 ret); 10014 10015 mutex_unlock(&hdev->vport_lock); 10016 return ret; 10017 } 10018 } 10019 vlan->hd_tbl_status = true; 10020 } 10021 10022 mutex_unlock(&hdev->vport_lock); 10023 10024 return 0; 10025 } 10026 10027 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10028 bool is_write_tbl) 10029 { 10030 struct hclge_vport_vlan_cfg *vlan, *tmp; 10031 struct hclge_dev *hdev = vport->back; 10032 10033 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10034 if (vlan->vlan_id == vlan_id) { 10035 if (is_write_tbl && vlan->hd_tbl_status) 10036 hclge_set_vlan_filter_hw(hdev, 10037 htons(ETH_P_8021Q), 10038 vport->vport_id, 10039 vlan_id, 10040 true); 10041 10042 list_del(&vlan->node); 10043 kfree(vlan); 10044 break; 10045 } 10046 } 10047 } 10048 10049 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list) 10050 { 10051 struct hclge_vport_vlan_cfg *vlan, *tmp; 10052 struct hclge_dev *hdev = vport->back; 10053 10054 mutex_lock(&hdev->vport_lock); 10055 10056 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10057 if (vlan->hd_tbl_status) 10058 hclge_set_vlan_filter_hw(hdev, 10059 htons(ETH_P_8021Q), 10060 vport->vport_id, 10061 vlan->vlan_id, 10062 true); 10063 10064 vlan->hd_tbl_status = false; 10065 if (is_del_list) { 10066 list_del(&vlan->node); 10067 kfree(vlan); 10068 } 10069 } 10070 clear_bit(vport->vport_id, hdev->vf_vlan_full); 10071 mutex_unlock(&hdev->vport_lock); 10072 } 10073 10074 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev) 10075 { 10076 struct hclge_vport_vlan_cfg *vlan, *tmp; 10077 struct hclge_vport *vport; 10078 int i; 10079 10080 mutex_lock(&hdev->vport_lock); 10081 10082 for (i = 0; i < hdev->num_alloc_vport; i++) { 10083 vport = &hdev->vport[i]; 10084 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10085 list_del(&vlan->node); 10086 kfree(vlan); 10087 } 10088 } 10089 10090 mutex_unlock(&hdev->vport_lock); 10091 } 10092 10093 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev) 10094 { 10095 struct hclge_vlan_info *vlan_info; 10096 struct hclge_vport *vport; 10097 u16 vlan_proto; 10098 u16 vlan_id; 10099 u16 state; 10100 int vf_id; 10101 int ret; 10102 10103 /* PF should restore all vfs port base vlan */ 10104 for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) { 10105 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM]; 10106 vlan_info = vport->port_base_vlan_cfg.tbl_sta ? 10107 &vport->port_base_vlan_cfg.vlan_info : 10108 &vport->port_base_vlan_cfg.old_vlan_info; 10109 10110 vlan_id = vlan_info->vlan_tag; 10111 vlan_proto = vlan_info->vlan_proto; 10112 state = vport->port_base_vlan_cfg.state; 10113 10114 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) { 10115 clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]); 10116 ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto), 10117 vport->vport_id, 10118 vlan_id, false); 10119 vport->port_base_vlan_cfg.tbl_sta = ret == 0; 10120 } 10121 } 10122 } 10123 10124 void hclge_restore_vport_vlan_table(struct hclge_vport *vport) 10125 { 10126 struct hclge_vport_vlan_cfg *vlan, *tmp; 10127 struct hclge_dev *hdev = vport->back; 10128 int ret; 10129 10130 mutex_lock(&hdev->vport_lock); 10131 10132 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10133 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10134 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10135 vport->vport_id, 10136 vlan->vlan_id, false); 10137 if (ret) 10138 break; 10139 vlan->hd_tbl_status = true; 10140 } 10141 } 10142 10143 mutex_unlock(&hdev->vport_lock); 10144 } 10145 10146 /* For global reset and imp reset, hardware will clear the mac table, 10147 * so we change the mac address state from ACTIVE to TO_ADD, then they 10148 * can be restored in the service task after reset complete. Furtherly, 10149 * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to 10150 * be restored after reset, so just remove these mac nodes from mac_list. 10151 */ 10152 static void hclge_mac_node_convert_for_reset(struct list_head *list) 10153 { 10154 struct hclge_mac_node *mac_node, *tmp; 10155 10156 list_for_each_entry_safe(mac_node, tmp, list, node) { 10157 if (mac_node->state == HCLGE_MAC_ACTIVE) { 10158 mac_node->state = HCLGE_MAC_TO_ADD; 10159 } else if (mac_node->state == HCLGE_MAC_TO_DEL) { 10160 list_del(&mac_node->node); 10161 kfree(mac_node); 10162 } 10163 } 10164 } 10165 10166 void hclge_restore_mac_table_common(struct hclge_vport *vport) 10167 { 10168 spin_lock_bh(&vport->mac_list_lock); 10169 10170 hclge_mac_node_convert_for_reset(&vport->uc_mac_list); 10171 hclge_mac_node_convert_for_reset(&vport->mc_mac_list); 10172 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 10173 10174 spin_unlock_bh(&vport->mac_list_lock); 10175 } 10176 10177 static void hclge_restore_hw_table(struct hclge_dev *hdev) 10178 { 10179 struct hclge_vport *vport = &hdev->vport[0]; 10180 struct hnae3_handle *handle = &vport->nic; 10181 10182 hclge_restore_mac_table_common(vport); 10183 hclge_restore_vport_port_base_vlan_config(hdev); 10184 hclge_restore_vport_vlan_table(vport); 10185 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 10186 hclge_restore_fd_entries(handle); 10187 } 10188 10189 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 10190 { 10191 struct hclge_vport *vport = hclge_get_vport(handle); 10192 10193 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10194 vport->rxvlan_cfg.strip_tag1_en = false; 10195 vport->rxvlan_cfg.strip_tag2_en = enable; 10196 vport->rxvlan_cfg.strip_tag2_discard_en = false; 10197 } else { 10198 vport->rxvlan_cfg.strip_tag1_en = enable; 10199 vport->rxvlan_cfg.strip_tag2_en = true; 10200 vport->rxvlan_cfg.strip_tag2_discard_en = true; 10201 } 10202 10203 vport->rxvlan_cfg.strip_tag1_discard_en = false; 10204 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 10205 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 10206 vport->rxvlan_cfg.rx_vlan_offload_en = enable; 10207 10208 return hclge_set_vlan_rx_offload_cfg(vport); 10209 } 10210 10211 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport) 10212 { 10213 struct hclge_dev *hdev = vport->back; 10214 10215 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 10216 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state); 10217 } 10218 10219 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport, 10220 u16 port_base_vlan_state, 10221 struct hclge_vlan_info *new_info, 10222 struct hclge_vlan_info *old_info) 10223 { 10224 struct hclge_dev *hdev = vport->back; 10225 int ret; 10226 10227 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) { 10228 hclge_rm_vport_all_vlan_table(vport, false); 10229 /* force clear VLAN 0 */ 10230 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0); 10231 if (ret) 10232 return ret; 10233 return hclge_set_vlan_filter_hw(hdev, 10234 htons(new_info->vlan_proto), 10235 vport->vport_id, 10236 new_info->vlan_tag, 10237 false); 10238 } 10239 10240 vport->port_base_vlan_cfg.tbl_sta = false; 10241 10242 /* force add VLAN 0 */ 10243 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0); 10244 if (ret) 10245 return ret; 10246 10247 ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto), 10248 vport->vport_id, old_info->vlan_tag, 10249 true); 10250 if (ret) 10251 return ret; 10252 10253 return hclge_add_vport_all_vlan_table(vport); 10254 } 10255 10256 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg, 10257 const struct hclge_vlan_info *old_cfg) 10258 { 10259 if (new_cfg->vlan_tag != old_cfg->vlan_tag) 10260 return true; 10261 10262 if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0)) 10263 return true; 10264 10265 return false; 10266 } 10267 10268 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport, 10269 struct hclge_vlan_info *new_info, 10270 struct hclge_vlan_info *old_info) 10271 { 10272 struct hclge_dev *hdev = vport->back; 10273 int ret; 10274 10275 /* add new VLAN tag */ 10276 ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto), 10277 vport->vport_id, new_info->vlan_tag, 10278 false); 10279 if (ret) 10280 return ret; 10281 10282 vport->port_base_vlan_cfg.tbl_sta = false; 10283 /* remove old VLAN tag */ 10284 if (old_info->vlan_tag == 0) 10285 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, 10286 true, 0); 10287 else 10288 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10289 vport->vport_id, 10290 old_info->vlan_tag, true); 10291 if (ret) 10292 dev_err(&hdev->pdev->dev, 10293 "failed to clear vport%u port base vlan %u, ret = %d.\n", 10294 vport->vport_id, old_info->vlan_tag, ret); 10295 10296 return ret; 10297 } 10298 10299 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 10300 struct hclge_vlan_info *vlan_info) 10301 { 10302 struct hnae3_handle *nic = &vport->nic; 10303 struct hclge_vlan_info *old_vlan_info; 10304 int ret; 10305 10306 old_vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10307 10308 ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag, 10309 vlan_info->qos); 10310 if (ret) 10311 return ret; 10312 10313 if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info)) 10314 goto out; 10315 10316 if (state == HNAE3_PORT_BASE_VLAN_MODIFY) 10317 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info, 10318 old_vlan_info); 10319 else 10320 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info, 10321 old_vlan_info); 10322 if (ret) 10323 return ret; 10324 10325 out: 10326 vport->port_base_vlan_cfg.state = state; 10327 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 10328 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 10329 else 10330 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 10331 10332 vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info; 10333 vport->port_base_vlan_cfg.vlan_info = *vlan_info; 10334 vport->port_base_vlan_cfg.tbl_sta = true; 10335 hclge_set_vport_vlan_fltr_change(vport); 10336 10337 return 0; 10338 } 10339 10340 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport, 10341 enum hnae3_port_base_vlan_state state, 10342 u16 vlan, u8 qos) 10343 { 10344 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10345 if (!vlan && !qos) 10346 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10347 10348 return HNAE3_PORT_BASE_VLAN_ENABLE; 10349 } 10350 10351 if (!vlan && !qos) 10352 return HNAE3_PORT_BASE_VLAN_DISABLE; 10353 10354 if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan && 10355 vport->port_base_vlan_cfg.vlan_info.qos == qos) 10356 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10357 10358 return HNAE3_PORT_BASE_VLAN_MODIFY; 10359 } 10360 10361 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 10362 u16 vlan, u8 qos, __be16 proto) 10363 { 10364 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 10365 struct hclge_vport *vport = hclge_get_vport(handle); 10366 struct hclge_dev *hdev = vport->back; 10367 struct hclge_vlan_info vlan_info; 10368 u16 state; 10369 int ret; 10370 10371 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 10372 return -EOPNOTSUPP; 10373 10374 vport = hclge_get_vf_vport(hdev, vfid); 10375 if (!vport) 10376 return -EINVAL; 10377 10378 /* qos is a 3 bits value, so can not be bigger than 7 */ 10379 if (vlan > VLAN_N_VID - 1 || qos > 7) 10380 return -EINVAL; 10381 if (proto != htons(ETH_P_8021Q)) 10382 return -EPROTONOSUPPORT; 10383 10384 state = hclge_get_port_base_vlan_state(vport, 10385 vport->port_base_vlan_cfg.state, 10386 vlan, qos); 10387 if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE) 10388 return 0; 10389 10390 vlan_info.vlan_tag = vlan; 10391 vlan_info.qos = qos; 10392 vlan_info.vlan_proto = ntohs(proto); 10393 10394 ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info); 10395 if (ret) { 10396 dev_err(&hdev->pdev->dev, 10397 "failed to update port base vlan for vf %d, ret = %d\n", 10398 vfid, ret); 10399 return ret; 10400 } 10401 10402 /* there is a timewindow for PF to know VF unalive, it may 10403 * cause send mailbox fail, but it doesn't matter, VF will 10404 * query it when reinit. 10405 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based 10406 * VLAN state. 10407 */ 10408 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 10409 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 10410 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0], 10411 vport->vport_id, 10412 state, 10413 &vlan_info); 10414 else 10415 set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, 10416 &vport->need_notify); 10417 } 10418 return 0; 10419 } 10420 10421 static void hclge_clear_vf_vlan(struct hclge_dev *hdev) 10422 { 10423 struct hclge_vlan_info *vlan_info; 10424 struct hclge_vport *vport; 10425 int ret; 10426 int vf; 10427 10428 /* clear port base vlan for all vf */ 10429 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 10430 vport = &hdev->vport[vf]; 10431 vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10432 10433 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10434 vport->vport_id, 10435 vlan_info->vlan_tag, true); 10436 if (ret) 10437 dev_err(&hdev->pdev->dev, 10438 "failed to clear vf vlan for vf%d, ret = %d\n", 10439 vf - HCLGE_VF_VPORT_START_NUM, ret); 10440 } 10441 } 10442 10443 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 10444 u16 vlan_id, bool is_kill) 10445 { 10446 struct hclge_vport *vport = hclge_get_vport(handle); 10447 struct hclge_dev *hdev = vport->back; 10448 bool writen_to_tbl = false; 10449 int ret = 0; 10450 10451 /* When device is resetting or reset failed, firmware is unable to 10452 * handle mailbox. Just record the vlan id, and remove it after 10453 * reset finished. 10454 */ 10455 mutex_lock(&hdev->vport_lock); 10456 if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 10457 test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) { 10458 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10459 mutex_unlock(&hdev->vport_lock); 10460 return -EBUSY; 10461 } else if (!is_kill && test_bit(vlan_id, vport->vlan_del_fail_bmap)) { 10462 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10463 } 10464 mutex_unlock(&hdev->vport_lock); 10465 10466 /* when port base vlan enabled, we use port base vlan as the vlan 10467 * filter entry. In this case, we don't update vlan filter table 10468 * when user add new vlan or remove exist vlan, just update the vport 10469 * vlan list. The vlan id in vlan list will be writen in vlan filter 10470 * table until port base vlan disabled 10471 */ 10472 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10473 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, 10474 vlan_id, is_kill); 10475 writen_to_tbl = true; 10476 } 10477 10478 if (!ret) { 10479 if (!is_kill) { 10480 hclge_add_vport_vlan_table(vport, vlan_id, 10481 writen_to_tbl); 10482 } else if (is_kill && vlan_id != 0) { 10483 mutex_lock(&hdev->vport_lock); 10484 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10485 mutex_unlock(&hdev->vport_lock); 10486 } 10487 } else if (is_kill) { 10488 /* when remove hw vlan filter failed, record the vlan id, 10489 * and try to remove it from hw later, to be consistence 10490 * with stack 10491 */ 10492 mutex_lock(&hdev->vport_lock); 10493 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10494 mutex_unlock(&hdev->vport_lock); 10495 } 10496 10497 hclge_set_vport_vlan_fltr_change(vport); 10498 10499 return ret; 10500 } 10501 10502 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev) 10503 { 10504 struct hclge_vport *vport; 10505 int ret; 10506 u16 i; 10507 10508 for (i = 0; i < hdev->num_alloc_vport; i++) { 10509 vport = &hdev->vport[i]; 10510 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10511 &vport->state)) 10512 continue; 10513 10514 ret = hclge_enable_vport_vlan_filter(vport, 10515 vport->req_vlan_fltr_en); 10516 if (ret) { 10517 dev_err(&hdev->pdev->dev, 10518 "failed to sync vlan filter state for vport%u, ret = %d\n", 10519 vport->vport_id, ret); 10520 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10521 &vport->state); 10522 return; 10523 } 10524 } 10525 } 10526 10527 static void hclge_sync_vlan_filter(struct hclge_dev *hdev) 10528 { 10529 #define HCLGE_MAX_SYNC_COUNT 60 10530 10531 int i, ret, sync_cnt = 0; 10532 u16 vlan_id; 10533 10534 mutex_lock(&hdev->vport_lock); 10535 /* start from vport 1 for PF is always alive */ 10536 for (i = 0; i < hdev->num_alloc_vport; i++) { 10537 struct hclge_vport *vport = &hdev->vport[i]; 10538 10539 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10540 VLAN_N_VID); 10541 while (vlan_id != VLAN_N_VID) { 10542 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10543 vport->vport_id, vlan_id, 10544 true); 10545 if (ret && ret != -EINVAL) { 10546 mutex_unlock(&hdev->vport_lock); 10547 return; 10548 } 10549 10550 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10551 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10552 hclge_set_vport_vlan_fltr_change(vport); 10553 10554 sync_cnt++; 10555 if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) { 10556 mutex_unlock(&hdev->vport_lock); 10557 return; 10558 } 10559 10560 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10561 VLAN_N_VID); 10562 } 10563 } 10564 mutex_unlock(&hdev->vport_lock); 10565 10566 hclge_sync_vlan_fltr_state(hdev); 10567 } 10568 10569 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps) 10570 { 10571 struct hclge_config_max_frm_size_cmd *req; 10572 struct hclge_desc desc; 10573 10574 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 10575 10576 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 10577 req->max_frm_size = cpu_to_le16(new_mps); 10578 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 10579 10580 return hclge_cmd_send(&hdev->hw, &desc, 1); 10581 } 10582 10583 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 10584 { 10585 struct hclge_vport *vport = hclge_get_vport(handle); 10586 10587 return hclge_set_vport_mtu(vport, new_mtu); 10588 } 10589 10590 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) 10591 { 10592 struct hclge_dev *hdev = vport->back; 10593 int i, max_frm_size, ret; 10594 10595 /* HW supprt 2 layer vlan */ 10596 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 10597 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 10598 max_frm_size > hdev->ae_dev->dev_specs.max_frm_size) 10599 return -EINVAL; 10600 10601 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 10602 mutex_lock(&hdev->vport_lock); 10603 /* VF's mps must fit within hdev->mps */ 10604 if (vport->vport_id && max_frm_size > hdev->mps) { 10605 mutex_unlock(&hdev->vport_lock); 10606 return -EINVAL; 10607 } else if (vport->vport_id) { 10608 vport->mps = max_frm_size; 10609 mutex_unlock(&hdev->vport_lock); 10610 return 0; 10611 } 10612 10613 /* PF's mps must be greater then VF's mps */ 10614 for (i = 1; i < hdev->num_alloc_vport; i++) 10615 if (max_frm_size < hdev->vport[i].mps) { 10616 dev_err(&hdev->pdev->dev, 10617 "failed to set pf mtu for less than vport %d, mps = %u.\n", 10618 i, hdev->vport[i].mps); 10619 mutex_unlock(&hdev->vport_lock); 10620 return -EINVAL; 10621 } 10622 10623 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 10624 10625 ret = hclge_set_mac_mtu(hdev, max_frm_size); 10626 if (ret) { 10627 dev_err(&hdev->pdev->dev, 10628 "Change mtu fail, ret =%d\n", ret); 10629 goto out; 10630 } 10631 10632 hdev->mps = max_frm_size; 10633 vport->mps = max_frm_size; 10634 10635 ret = hclge_buffer_alloc(hdev); 10636 if (ret) 10637 dev_err(&hdev->pdev->dev, 10638 "Allocate buffer fail, ret =%d\n", ret); 10639 10640 out: 10641 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 10642 mutex_unlock(&hdev->vport_lock); 10643 return ret; 10644 } 10645 10646 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id, 10647 bool enable) 10648 { 10649 struct hclge_reset_tqp_queue_cmd *req; 10650 struct hclge_desc desc; 10651 int ret; 10652 10653 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 10654 10655 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10656 req->tqp_id = cpu_to_le16(queue_id); 10657 if (enable) 10658 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U); 10659 10660 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10661 if (ret) { 10662 dev_err(&hdev->pdev->dev, 10663 "Send tqp reset cmd error, status =%d\n", ret); 10664 return ret; 10665 } 10666 10667 return 0; 10668 } 10669 10670 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id, 10671 u8 *reset_status) 10672 { 10673 struct hclge_reset_tqp_queue_cmd *req; 10674 struct hclge_desc desc; 10675 int ret; 10676 10677 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 10678 10679 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10680 req->tqp_id = cpu_to_le16(queue_id); 10681 10682 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10683 if (ret) { 10684 dev_err(&hdev->pdev->dev, 10685 "Get reset status error, status =%d\n", ret); 10686 return ret; 10687 } 10688 10689 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 10690 10691 return 0; 10692 } 10693 10694 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id) 10695 { 10696 struct hclge_comm_tqp *tqp; 10697 struct hnae3_queue *queue; 10698 10699 queue = handle->kinfo.tqp[queue_id]; 10700 tqp = container_of(queue, struct hclge_comm_tqp, q); 10701 10702 return tqp->index; 10703 } 10704 10705 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle) 10706 { 10707 struct hclge_vport *vport = hclge_get_vport(handle); 10708 struct hclge_dev *hdev = vport->back; 10709 u16 reset_try_times = 0; 10710 u8 reset_status; 10711 u16 queue_gid; 10712 int ret; 10713 u16 i; 10714 10715 for (i = 0; i < handle->kinfo.num_tqps; i++) { 10716 queue_gid = hclge_covert_handle_qid_global(handle, i); 10717 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true); 10718 if (ret) { 10719 dev_err(&hdev->pdev->dev, 10720 "failed to send reset tqp cmd, ret = %d\n", 10721 ret); 10722 return ret; 10723 } 10724 10725 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 10726 ret = hclge_get_reset_status(hdev, queue_gid, 10727 &reset_status); 10728 if (ret) 10729 return ret; 10730 10731 if (reset_status) 10732 break; 10733 10734 /* Wait for tqp hw reset */ 10735 usleep_range(1000, 1200); 10736 } 10737 10738 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 10739 dev_err(&hdev->pdev->dev, 10740 "wait for tqp hw reset timeout\n"); 10741 return -ETIME; 10742 } 10743 10744 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false); 10745 if (ret) { 10746 dev_err(&hdev->pdev->dev, 10747 "failed to deassert soft reset, ret = %d\n", 10748 ret); 10749 return ret; 10750 } 10751 reset_try_times = 0; 10752 } 10753 return 0; 10754 } 10755 10756 static int hclge_reset_rcb(struct hnae3_handle *handle) 10757 { 10758 #define HCLGE_RESET_RCB_NOT_SUPPORT 0U 10759 #define HCLGE_RESET_RCB_SUCCESS 1U 10760 10761 struct hclge_vport *vport = hclge_get_vport(handle); 10762 struct hclge_dev *hdev = vport->back; 10763 struct hclge_reset_cmd *req; 10764 struct hclge_desc desc; 10765 u8 return_status; 10766 u16 queue_gid; 10767 int ret; 10768 10769 queue_gid = hclge_covert_handle_qid_global(handle, 0); 10770 10771 req = (struct hclge_reset_cmd *)desc.data; 10772 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 10773 hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1); 10774 req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid); 10775 req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps); 10776 10777 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10778 if (ret) { 10779 dev_err(&hdev->pdev->dev, 10780 "failed to send rcb reset cmd, ret = %d\n", ret); 10781 return ret; 10782 } 10783 10784 return_status = req->fun_reset_rcb_return_status; 10785 if (return_status == HCLGE_RESET_RCB_SUCCESS) 10786 return 0; 10787 10788 if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) { 10789 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n", 10790 return_status); 10791 return -EIO; 10792 } 10793 10794 /* if reset rcb cmd is unsupported, we need to send reset tqp cmd 10795 * again to reset all tqps 10796 */ 10797 return hclge_reset_tqp_cmd(handle); 10798 } 10799 10800 int hclge_reset_tqp(struct hnae3_handle *handle) 10801 { 10802 struct hclge_vport *vport = hclge_get_vport(handle); 10803 struct hclge_dev *hdev = vport->back; 10804 int ret; 10805 10806 /* only need to disable PF's tqp */ 10807 if (!vport->vport_id) { 10808 ret = hclge_tqp_enable(handle, false); 10809 if (ret) { 10810 dev_err(&hdev->pdev->dev, 10811 "failed to disable tqp, ret = %d\n", ret); 10812 return ret; 10813 } 10814 } 10815 10816 return hclge_reset_rcb(handle); 10817 } 10818 10819 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 10820 { 10821 struct hclge_vport *vport = hclge_get_vport(handle); 10822 struct hclge_dev *hdev = vport->back; 10823 10824 return hdev->fw_version; 10825 } 10826 10827 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10828 { 10829 struct phy_device *phydev = hdev->hw.mac.phydev; 10830 10831 if (!phydev) 10832 return; 10833 10834 phy_set_asym_pause(phydev, rx_en, tx_en); 10835 } 10836 10837 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10838 { 10839 int ret; 10840 10841 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 10842 return 0; 10843 10844 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 10845 if (ret) 10846 dev_err(&hdev->pdev->dev, 10847 "configure pauseparam error, ret = %d.\n", ret); 10848 10849 return ret; 10850 } 10851 10852 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 10853 { 10854 struct phy_device *phydev = hdev->hw.mac.phydev; 10855 u16 remote_advertising = 0; 10856 u16 local_advertising; 10857 u32 rx_pause, tx_pause; 10858 u8 flowctl; 10859 10860 if (!phydev->link) 10861 return 0; 10862 10863 if (!phydev->autoneg) 10864 return hclge_mac_pause_setup_hw(hdev); 10865 10866 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising); 10867 10868 if (phydev->pause) 10869 remote_advertising = LPA_PAUSE_CAP; 10870 10871 if (phydev->asym_pause) 10872 remote_advertising |= LPA_PAUSE_ASYM; 10873 10874 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 10875 remote_advertising); 10876 tx_pause = flowctl & FLOW_CTRL_TX; 10877 rx_pause = flowctl & FLOW_CTRL_RX; 10878 10879 if (phydev->duplex == HCLGE_MAC_HALF) { 10880 tx_pause = 0; 10881 rx_pause = 0; 10882 } 10883 10884 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 10885 } 10886 10887 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 10888 u32 *rx_en, u32 *tx_en) 10889 { 10890 struct hclge_vport *vport = hclge_get_vport(handle); 10891 struct hclge_dev *hdev = vport->back; 10892 u8 media_type = hdev->hw.mac.media_type; 10893 10894 *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ? 10895 hclge_get_autoneg(handle) : 0; 10896 10897 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 10898 *rx_en = 0; 10899 *tx_en = 0; 10900 return; 10901 } 10902 10903 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 10904 *rx_en = 1; 10905 *tx_en = 0; 10906 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 10907 *tx_en = 1; 10908 *rx_en = 0; 10909 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 10910 *rx_en = 1; 10911 *tx_en = 1; 10912 } else { 10913 *rx_en = 0; 10914 *tx_en = 0; 10915 } 10916 } 10917 10918 static void hclge_record_user_pauseparam(struct hclge_dev *hdev, 10919 u32 rx_en, u32 tx_en) 10920 { 10921 if (rx_en && tx_en) 10922 hdev->fc_mode_last_time = HCLGE_FC_FULL; 10923 else if (rx_en && !tx_en) 10924 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 10925 else if (!rx_en && tx_en) 10926 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 10927 else 10928 hdev->fc_mode_last_time = HCLGE_FC_NONE; 10929 10930 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 10931 } 10932 10933 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 10934 u32 rx_en, u32 tx_en) 10935 { 10936 struct hclge_vport *vport = hclge_get_vport(handle); 10937 struct hclge_dev *hdev = vport->back; 10938 struct phy_device *phydev = hdev->hw.mac.phydev; 10939 u32 fc_autoneg; 10940 10941 if (phydev || hnae3_dev_phy_imp_supported(hdev)) { 10942 fc_autoneg = hclge_get_autoneg(handle); 10943 if (auto_neg != fc_autoneg) { 10944 dev_info(&hdev->pdev->dev, 10945 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 10946 return -EOPNOTSUPP; 10947 } 10948 } 10949 10950 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 10951 dev_info(&hdev->pdev->dev, 10952 "Priority flow control enabled. Cannot set link flow control.\n"); 10953 return -EOPNOTSUPP; 10954 } 10955 10956 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 10957 10958 hclge_record_user_pauseparam(hdev, rx_en, tx_en); 10959 10960 if (!auto_neg || hnae3_dev_phy_imp_supported(hdev)) 10961 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 10962 10963 if (phydev) 10964 return phy_start_aneg(phydev); 10965 10966 return -EOPNOTSUPP; 10967 } 10968 10969 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 10970 u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num) 10971 { 10972 struct hclge_vport *vport = hclge_get_vport(handle); 10973 struct hclge_dev *hdev = vport->back; 10974 10975 if (speed) 10976 *speed = hdev->hw.mac.speed; 10977 if (duplex) 10978 *duplex = hdev->hw.mac.duplex; 10979 if (auto_neg) 10980 *auto_neg = hdev->hw.mac.autoneg; 10981 if (lane_num) 10982 *lane_num = hdev->hw.mac.lane_num; 10983 } 10984 10985 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type, 10986 u8 *module_type) 10987 { 10988 struct hclge_vport *vport = hclge_get_vport(handle); 10989 struct hclge_dev *hdev = vport->back; 10990 10991 /* When nic is down, the service task is not running, doesn't update 10992 * the port information per second. Query the port information before 10993 * return the media type, ensure getting the correct media information. 10994 */ 10995 hclge_update_port_info(hdev); 10996 10997 if (media_type) 10998 *media_type = hdev->hw.mac.media_type; 10999 11000 if (module_type) 11001 *module_type = hdev->hw.mac.module_type; 11002 } 11003 11004 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 11005 u8 *tp_mdix_ctrl, u8 *tp_mdix) 11006 { 11007 struct hclge_vport *vport = hclge_get_vport(handle); 11008 struct hclge_dev *hdev = vport->back; 11009 struct phy_device *phydev = hdev->hw.mac.phydev; 11010 int mdix_ctrl, mdix, is_resolved; 11011 unsigned int retval; 11012 11013 if (!phydev) { 11014 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11015 *tp_mdix = ETH_TP_MDI_INVALID; 11016 return; 11017 } 11018 11019 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 11020 11021 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 11022 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 11023 HCLGE_PHY_MDIX_CTRL_S); 11024 11025 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 11026 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 11027 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 11028 11029 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 11030 11031 switch (mdix_ctrl) { 11032 case 0x0: 11033 *tp_mdix_ctrl = ETH_TP_MDI; 11034 break; 11035 case 0x1: 11036 *tp_mdix_ctrl = ETH_TP_MDI_X; 11037 break; 11038 case 0x3: 11039 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 11040 break; 11041 default: 11042 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11043 break; 11044 } 11045 11046 if (!is_resolved) 11047 *tp_mdix = ETH_TP_MDI_INVALID; 11048 else if (mdix) 11049 *tp_mdix = ETH_TP_MDI_X; 11050 else 11051 *tp_mdix = ETH_TP_MDI; 11052 } 11053 11054 static void hclge_info_show(struct hclge_dev *hdev) 11055 { 11056 struct hnae3_handle *handle = &hdev->vport->nic; 11057 struct device *dev = &hdev->pdev->dev; 11058 11059 dev_info(dev, "PF info begin:\n"); 11060 11061 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 11062 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 11063 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 11064 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 11065 dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs); 11066 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 11067 dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size); 11068 dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size); 11069 dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size); 11070 dev_info(dev, "This is %s PF\n", 11071 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main"); 11072 dev_info(dev, "DCB %s\n", 11073 handle->kinfo.tc_info.dcb_ets_active ? "enable" : "disable"); 11074 dev_info(dev, "MQPRIO %s\n", 11075 handle->kinfo.tc_info.mqprio_active ? "enable" : "disable"); 11076 dev_info(dev, "Default tx spare buffer size: %u\n", 11077 hdev->tx_spare_buf_size); 11078 11079 dev_info(dev, "PF info end.\n"); 11080 } 11081 11082 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 11083 struct hclge_vport *vport) 11084 { 11085 struct hnae3_client *client = vport->nic.client; 11086 struct hclge_dev *hdev = ae_dev->priv; 11087 int rst_cnt = hdev->rst_stats.reset_cnt; 11088 int ret; 11089 11090 ret = client->ops->init_instance(&vport->nic); 11091 if (ret) 11092 return ret; 11093 11094 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11095 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11096 rst_cnt != hdev->rst_stats.reset_cnt) { 11097 ret = -EBUSY; 11098 goto init_nic_err; 11099 } 11100 11101 /* Enable nic hw error interrupts */ 11102 ret = hclge_config_nic_hw_error(hdev, true); 11103 if (ret) { 11104 dev_err(&ae_dev->pdev->dev, 11105 "fail(%d) to enable hw error interrupts\n", ret); 11106 goto init_nic_err; 11107 } 11108 11109 hnae3_set_client_init_flag(client, ae_dev, 1); 11110 11111 if (netif_msg_drv(&hdev->vport->nic)) 11112 hclge_info_show(hdev); 11113 11114 return ret; 11115 11116 init_nic_err: 11117 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11118 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11119 msleep(HCLGE_WAIT_RESET_DONE); 11120 11121 client->ops->uninit_instance(&vport->nic, 0); 11122 11123 return ret; 11124 } 11125 11126 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 11127 struct hclge_vport *vport) 11128 { 11129 struct hclge_dev *hdev = ae_dev->priv; 11130 struct hnae3_client *client; 11131 int rst_cnt; 11132 int ret; 11133 11134 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 11135 !hdev->nic_client) 11136 return 0; 11137 11138 client = hdev->roce_client; 11139 ret = hclge_init_roce_base_info(vport); 11140 if (ret) 11141 return ret; 11142 11143 rst_cnt = hdev->rst_stats.reset_cnt; 11144 ret = client->ops->init_instance(&vport->roce); 11145 if (ret) 11146 return ret; 11147 11148 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11149 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11150 rst_cnt != hdev->rst_stats.reset_cnt) { 11151 ret = -EBUSY; 11152 goto init_roce_err; 11153 } 11154 11155 /* Enable roce ras interrupts */ 11156 ret = hclge_config_rocee_ras_interrupt(hdev, true); 11157 if (ret) { 11158 dev_err(&ae_dev->pdev->dev, 11159 "fail(%d) to enable roce ras interrupts\n", ret); 11160 goto init_roce_err; 11161 } 11162 11163 hnae3_set_client_init_flag(client, ae_dev, 1); 11164 11165 return 0; 11166 11167 init_roce_err: 11168 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11169 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11170 msleep(HCLGE_WAIT_RESET_DONE); 11171 11172 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11173 11174 return ret; 11175 } 11176 11177 static int hclge_init_client_instance(struct hnae3_client *client, 11178 struct hnae3_ae_dev *ae_dev) 11179 { 11180 struct hclge_dev *hdev = ae_dev->priv; 11181 struct hclge_vport *vport = &hdev->vport[0]; 11182 int ret; 11183 11184 switch (client->type) { 11185 case HNAE3_CLIENT_KNIC: 11186 hdev->nic_client = client; 11187 vport->nic.client = client; 11188 ret = hclge_init_nic_client_instance(ae_dev, vport); 11189 if (ret) 11190 goto clear_nic; 11191 11192 ret = hclge_init_roce_client_instance(ae_dev, vport); 11193 if (ret) 11194 goto clear_roce; 11195 11196 break; 11197 case HNAE3_CLIENT_ROCE: 11198 if (hnae3_dev_roce_supported(hdev)) { 11199 hdev->roce_client = client; 11200 vport->roce.client = client; 11201 } 11202 11203 ret = hclge_init_roce_client_instance(ae_dev, vport); 11204 if (ret) 11205 goto clear_roce; 11206 11207 break; 11208 default: 11209 return -EINVAL; 11210 } 11211 11212 return 0; 11213 11214 clear_nic: 11215 hdev->nic_client = NULL; 11216 vport->nic.client = NULL; 11217 return ret; 11218 clear_roce: 11219 hdev->roce_client = NULL; 11220 vport->roce.client = NULL; 11221 return ret; 11222 } 11223 11224 static void hclge_uninit_client_instance(struct hnae3_client *client, 11225 struct hnae3_ae_dev *ae_dev) 11226 { 11227 struct hclge_dev *hdev = ae_dev->priv; 11228 struct hclge_vport *vport = &hdev->vport[0]; 11229 11230 if (hdev->roce_client) { 11231 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11232 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11233 msleep(HCLGE_WAIT_RESET_DONE); 11234 11235 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11236 hdev->roce_client = NULL; 11237 vport->roce.client = NULL; 11238 } 11239 if (client->type == HNAE3_CLIENT_ROCE) 11240 return; 11241 if (hdev->nic_client && client->ops->uninit_instance) { 11242 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11243 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11244 msleep(HCLGE_WAIT_RESET_DONE); 11245 11246 client->ops->uninit_instance(&vport->nic, 0); 11247 hdev->nic_client = NULL; 11248 vport->nic.client = NULL; 11249 } 11250 } 11251 11252 static int hclge_dev_mem_map(struct hclge_dev *hdev) 11253 { 11254 struct pci_dev *pdev = hdev->pdev; 11255 struct hclge_hw *hw = &hdev->hw; 11256 11257 /* for device does not have device memory, return directly */ 11258 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR))) 11259 return 0; 11260 11261 hw->hw.mem_base = 11262 devm_ioremap_wc(&pdev->dev, 11263 pci_resource_start(pdev, HCLGE_MEM_BAR), 11264 pci_resource_len(pdev, HCLGE_MEM_BAR)); 11265 if (!hw->hw.mem_base) { 11266 dev_err(&pdev->dev, "failed to map device memory\n"); 11267 return -EFAULT; 11268 } 11269 11270 return 0; 11271 } 11272 11273 static int hclge_pci_init(struct hclge_dev *hdev) 11274 { 11275 struct pci_dev *pdev = hdev->pdev; 11276 struct hclge_hw *hw; 11277 int ret; 11278 11279 ret = pci_enable_device(pdev); 11280 if (ret) { 11281 dev_err(&pdev->dev, "failed to enable PCI device\n"); 11282 return ret; 11283 } 11284 11285 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 11286 if (ret) { 11287 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 11288 if (ret) { 11289 dev_err(&pdev->dev, 11290 "can't set consistent PCI DMA"); 11291 goto err_disable_device; 11292 } 11293 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 11294 } 11295 11296 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 11297 if (ret) { 11298 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 11299 goto err_disable_device; 11300 } 11301 11302 pci_set_master(pdev); 11303 hw = &hdev->hw; 11304 hw->hw.io_base = pcim_iomap(pdev, 2, 0); 11305 if (!hw->hw.io_base) { 11306 dev_err(&pdev->dev, "Can't map configuration register space\n"); 11307 ret = -ENOMEM; 11308 goto err_release_regions; 11309 } 11310 11311 ret = hclge_dev_mem_map(hdev); 11312 if (ret) 11313 goto err_unmap_io_base; 11314 11315 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 11316 11317 return 0; 11318 11319 err_unmap_io_base: 11320 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11321 err_release_regions: 11322 pci_release_regions(pdev); 11323 err_disable_device: 11324 pci_disable_device(pdev); 11325 11326 return ret; 11327 } 11328 11329 static void hclge_pci_uninit(struct hclge_dev *hdev) 11330 { 11331 struct pci_dev *pdev = hdev->pdev; 11332 11333 if (hdev->hw.hw.mem_base) 11334 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 11335 11336 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11337 pci_free_irq_vectors(pdev); 11338 pci_release_mem_regions(pdev); 11339 pci_disable_device(pdev); 11340 } 11341 11342 static void hclge_state_init(struct hclge_dev *hdev) 11343 { 11344 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 11345 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11346 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 11347 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11348 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 11349 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 11350 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 11351 } 11352 11353 static void hclge_state_uninit(struct hclge_dev *hdev) 11354 { 11355 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11356 set_bit(HCLGE_STATE_REMOVING, &hdev->state); 11357 11358 if (hdev->reset_timer.function) 11359 del_timer_sync(&hdev->reset_timer); 11360 if (hdev->service_task.work.func) 11361 cancel_delayed_work_sync(&hdev->service_task); 11362 } 11363 11364 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 11365 enum hnae3_reset_type rst_type) 11366 { 11367 #define HCLGE_RESET_RETRY_WAIT_MS 500 11368 #define HCLGE_RESET_RETRY_CNT 5 11369 11370 struct hclge_dev *hdev = ae_dev->priv; 11371 int retry_cnt = 0; 11372 int ret; 11373 11374 while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) { 11375 down(&hdev->reset_sem); 11376 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11377 hdev->reset_type = rst_type; 11378 ret = hclge_reset_prepare(hdev); 11379 if (!ret && !hdev->reset_pending) 11380 break; 11381 11382 dev_err(&hdev->pdev->dev, 11383 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 11384 ret, hdev->reset_pending, retry_cnt); 11385 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11386 up(&hdev->reset_sem); 11387 msleep(HCLGE_RESET_RETRY_WAIT_MS); 11388 } 11389 11390 /* disable misc vector before reset done */ 11391 hclge_enable_vector(&hdev->misc_vector, false); 11392 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 11393 11394 if (hdev->reset_type == HNAE3_FLR_RESET) 11395 hdev->rst_stats.flr_rst_cnt++; 11396 } 11397 11398 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev) 11399 { 11400 struct hclge_dev *hdev = ae_dev->priv; 11401 int ret; 11402 11403 hclge_enable_vector(&hdev->misc_vector, true); 11404 11405 ret = hclge_reset_rebuild(hdev); 11406 if (ret) 11407 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret); 11408 11409 hdev->reset_type = HNAE3_NONE_RESET; 11410 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11411 up(&hdev->reset_sem); 11412 } 11413 11414 static void hclge_clear_resetting_state(struct hclge_dev *hdev) 11415 { 11416 u16 i; 11417 11418 for (i = 0; i < hdev->num_alloc_vport; i++) { 11419 struct hclge_vport *vport = &hdev->vport[i]; 11420 int ret; 11421 11422 /* Send cmd to clear vport's FUNC_RST_ING */ 11423 ret = hclge_set_vf_rst(hdev, vport->vport_id, false); 11424 if (ret) 11425 dev_warn(&hdev->pdev->dev, 11426 "clear vport(%u) rst failed %d!\n", 11427 vport->vport_id, ret); 11428 } 11429 } 11430 11431 static int hclge_clear_hw_resource(struct hclge_dev *hdev) 11432 { 11433 struct hclge_desc desc; 11434 int ret; 11435 11436 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false); 11437 11438 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11439 /* This new command is only supported by new firmware, it will 11440 * fail with older firmware. Error value -EOPNOSUPP can only be 11441 * returned by older firmware running this command, to keep code 11442 * backward compatible we will override this value and return 11443 * success. 11444 */ 11445 if (ret && ret != -EOPNOTSUPP) { 11446 dev_err(&hdev->pdev->dev, 11447 "failed to clear hw resource, ret = %d\n", ret); 11448 return ret; 11449 } 11450 return 0; 11451 } 11452 11453 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev) 11454 { 11455 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11456 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1); 11457 } 11458 11459 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev) 11460 { 11461 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11462 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0); 11463 } 11464 11465 static struct hclge_wol_info *hclge_get_wol_info(struct hnae3_handle *handle) 11466 { 11467 struct hclge_vport *vport = hclge_get_vport(handle); 11468 11469 return &vport->back->hw.mac.wol; 11470 } 11471 11472 static int hclge_get_wol_supported_mode(struct hclge_dev *hdev, 11473 u32 *wol_supported) 11474 { 11475 struct hclge_query_wol_supported_cmd *wol_supported_cmd; 11476 struct hclge_desc desc; 11477 int ret; 11478 11479 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_GET_SUPPORTED_MODE, 11480 true); 11481 wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)desc.data; 11482 11483 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11484 if (ret) { 11485 dev_err(&hdev->pdev->dev, 11486 "failed to query wol supported, ret = %d\n", ret); 11487 return ret; 11488 } 11489 11490 *wol_supported = le32_to_cpu(wol_supported_cmd->supported_wake_mode); 11491 11492 return 0; 11493 } 11494 11495 static int hclge_set_wol_cfg(struct hclge_dev *hdev, 11496 struct hclge_wol_info *wol_info) 11497 { 11498 struct hclge_wol_cfg_cmd *wol_cfg_cmd; 11499 struct hclge_desc desc; 11500 int ret; 11501 11502 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, false); 11503 wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)desc.data; 11504 wol_cfg_cmd->wake_on_lan_mode = cpu_to_le32(wol_info->wol_current_mode); 11505 wol_cfg_cmd->sopass_size = wol_info->wol_sopass_size; 11506 memcpy(wol_cfg_cmd->sopass, wol_info->wol_sopass, SOPASS_MAX); 11507 11508 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11509 if (ret) 11510 dev_err(&hdev->pdev->dev, 11511 "failed to set wol config, ret = %d\n", ret); 11512 11513 return ret; 11514 } 11515 11516 static int hclge_update_wol(struct hclge_dev *hdev) 11517 { 11518 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11519 11520 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11521 return 0; 11522 11523 return hclge_set_wol_cfg(hdev, wol_info); 11524 } 11525 11526 static int hclge_init_wol(struct hclge_dev *hdev) 11527 { 11528 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 11529 int ret; 11530 11531 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 11532 return 0; 11533 11534 memset(wol_info, 0, sizeof(struct hclge_wol_info)); 11535 ret = hclge_get_wol_supported_mode(hdev, 11536 &wol_info->wol_support_mode); 11537 if (ret) { 11538 wol_info->wol_support_mode = 0; 11539 return ret; 11540 } 11541 11542 return hclge_update_wol(hdev); 11543 } 11544 11545 static void hclge_get_wol(struct hnae3_handle *handle, 11546 struct ethtool_wolinfo *wol) 11547 { 11548 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11549 11550 wol->supported = wol_info->wol_support_mode; 11551 wol->wolopts = wol_info->wol_current_mode; 11552 if (wol_info->wol_current_mode & WAKE_MAGICSECURE) 11553 memcpy(wol->sopass, wol_info->wol_sopass, SOPASS_MAX); 11554 } 11555 11556 static int hclge_set_wol(struct hnae3_handle *handle, 11557 struct ethtool_wolinfo *wol) 11558 { 11559 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 11560 struct hclge_vport *vport = hclge_get_vport(handle); 11561 u32 wol_mode; 11562 int ret; 11563 11564 wol_mode = wol->wolopts; 11565 if (wol_mode & ~wol_info->wol_support_mode) 11566 return -EINVAL; 11567 11568 wol_info->wol_current_mode = wol_mode; 11569 if (wol_mode & WAKE_MAGICSECURE) { 11570 memcpy(wol_info->wol_sopass, wol->sopass, SOPASS_MAX); 11571 wol_info->wol_sopass_size = SOPASS_MAX; 11572 } else { 11573 wol_info->wol_sopass_size = 0; 11574 } 11575 11576 ret = hclge_set_wol_cfg(vport->back, wol_info); 11577 if (ret) 11578 wol_info->wol_current_mode = 0; 11579 11580 return ret; 11581 } 11582 11583 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 11584 { 11585 struct pci_dev *pdev = ae_dev->pdev; 11586 struct hclge_dev *hdev; 11587 int ret; 11588 11589 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 11590 if (!hdev) 11591 return -ENOMEM; 11592 11593 hdev->pdev = pdev; 11594 hdev->ae_dev = ae_dev; 11595 hdev->reset_type = HNAE3_NONE_RESET; 11596 hdev->reset_level = HNAE3_FUNC_RESET; 11597 ae_dev->priv = hdev; 11598 11599 /* HW supprt 2 layer vlan */ 11600 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 11601 11602 mutex_init(&hdev->vport_lock); 11603 spin_lock_init(&hdev->fd_rule_lock); 11604 sema_init(&hdev->reset_sem, 1); 11605 11606 ret = hclge_pci_init(hdev); 11607 if (ret) 11608 goto out; 11609 11610 ret = hclge_devlink_init(hdev); 11611 if (ret) 11612 goto err_pci_uninit; 11613 11614 /* Firmware command queue initialize */ 11615 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 11616 if (ret) 11617 goto err_devlink_uninit; 11618 11619 /* Firmware command initialize */ 11620 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 11621 true, hdev->reset_pending); 11622 if (ret) 11623 goto err_cmd_uninit; 11624 11625 ret = hclge_clear_hw_resource(hdev); 11626 if (ret) 11627 goto err_cmd_uninit; 11628 11629 ret = hclge_get_cap(hdev); 11630 if (ret) 11631 goto err_cmd_uninit; 11632 11633 ret = hclge_query_dev_specs(hdev); 11634 if (ret) { 11635 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n", 11636 ret); 11637 goto err_cmd_uninit; 11638 } 11639 11640 ret = hclge_configure(hdev); 11641 if (ret) { 11642 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 11643 goto err_cmd_uninit; 11644 } 11645 11646 ret = hclge_init_msi(hdev); 11647 if (ret) { 11648 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 11649 goto err_cmd_uninit; 11650 } 11651 11652 ret = hclge_misc_irq_init(hdev); 11653 if (ret) 11654 goto err_msi_uninit; 11655 11656 ret = hclge_alloc_tqps(hdev); 11657 if (ret) { 11658 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 11659 goto err_msi_irq_uninit; 11660 } 11661 11662 ret = hclge_alloc_vport(hdev); 11663 if (ret) 11664 goto err_msi_irq_uninit; 11665 11666 ret = hclge_map_tqp(hdev); 11667 if (ret) 11668 goto err_msi_irq_uninit; 11669 11670 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { 11671 clear_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps); 11672 if (hnae3_dev_phy_imp_supported(hdev)) 11673 ret = hclge_update_tp_port_info(hdev); 11674 else 11675 ret = hclge_mac_mdio_config(hdev); 11676 11677 if (ret) 11678 goto err_msi_irq_uninit; 11679 } 11680 11681 ret = hclge_init_umv_space(hdev); 11682 if (ret) 11683 goto err_mdiobus_unreg; 11684 11685 ret = hclge_mac_init(hdev); 11686 if (ret) { 11687 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 11688 goto err_mdiobus_unreg; 11689 } 11690 11691 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 11692 if (ret) { 11693 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 11694 goto err_mdiobus_unreg; 11695 } 11696 11697 ret = hclge_config_gro(hdev); 11698 if (ret) 11699 goto err_mdiobus_unreg; 11700 11701 ret = hclge_init_vlan_config(hdev); 11702 if (ret) { 11703 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 11704 goto err_mdiobus_unreg; 11705 } 11706 11707 ret = hclge_tm_schd_init(hdev); 11708 if (ret) { 11709 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 11710 goto err_mdiobus_unreg; 11711 } 11712 11713 ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev, 11714 &hdev->rss_cfg); 11715 if (ret) { 11716 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 11717 goto err_mdiobus_unreg; 11718 } 11719 11720 ret = hclge_rss_init_hw(hdev); 11721 if (ret) { 11722 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 11723 goto err_mdiobus_unreg; 11724 } 11725 11726 ret = init_mgr_tbl(hdev); 11727 if (ret) { 11728 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 11729 goto err_mdiobus_unreg; 11730 } 11731 11732 ret = hclge_init_fd_config(hdev); 11733 if (ret) { 11734 dev_err(&pdev->dev, 11735 "fd table init fail, ret=%d\n", ret); 11736 goto err_mdiobus_unreg; 11737 } 11738 11739 ret = hclge_ptp_init(hdev); 11740 if (ret) 11741 goto err_mdiobus_unreg; 11742 11743 ret = hclge_update_port_info(hdev); 11744 if (ret) 11745 goto err_mdiobus_unreg; 11746 11747 INIT_KFIFO(hdev->mac_tnl_log); 11748 11749 hclge_dcb_ops_set(hdev); 11750 11751 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0); 11752 INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task); 11753 11754 hclge_clear_all_event_cause(hdev); 11755 hclge_clear_resetting_state(hdev); 11756 11757 /* Log and clear the hw errors those already occurred */ 11758 if (hnae3_dev_ras_imp_supported(hdev)) 11759 hclge_handle_occurred_error(hdev); 11760 else 11761 hclge_handle_all_hns_hw_errors(ae_dev); 11762 11763 /* request delayed reset for the error recovery because an immediate 11764 * global reset on a PF affecting pending initialization of other PFs 11765 */ 11766 if (ae_dev->hw_err_reset_req) { 11767 enum hnae3_reset_type reset_level; 11768 11769 reset_level = hclge_get_reset_level(ae_dev, 11770 &ae_dev->hw_err_reset_req); 11771 hclge_set_def_reset_request(ae_dev, reset_level); 11772 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 11773 } 11774 11775 hclge_init_rxd_adv_layout(hdev); 11776 11777 /* Enable MISC vector(vector0) */ 11778 hclge_enable_vector(&hdev->misc_vector, true); 11779 11780 ret = hclge_init_wol(hdev); 11781 if (ret) 11782 dev_warn(&pdev->dev, 11783 "failed to wake on lan init, ret = %d\n", ret); 11784 11785 hclge_state_init(hdev); 11786 hdev->last_reset_time = jiffies; 11787 11788 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", 11789 HCLGE_DRIVER_NAME); 11790 11791 hclge_task_schedule(hdev, round_jiffies_relative(HZ)); 11792 11793 return 0; 11794 11795 err_mdiobus_unreg: 11796 if (hdev->hw.mac.phydev) 11797 mdiobus_unregister(hdev->hw.mac.mdio_bus); 11798 err_msi_irq_uninit: 11799 hclge_misc_irq_uninit(hdev); 11800 err_msi_uninit: 11801 pci_free_irq_vectors(pdev); 11802 err_cmd_uninit: 11803 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 11804 err_devlink_uninit: 11805 hclge_devlink_uninit(hdev); 11806 err_pci_uninit: 11807 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11808 pci_release_regions(pdev); 11809 pci_disable_device(pdev); 11810 out: 11811 mutex_destroy(&hdev->vport_lock); 11812 return ret; 11813 } 11814 11815 static void hclge_stats_clear(struct hclge_dev *hdev) 11816 { 11817 memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats)); 11818 memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats)); 11819 } 11820 11821 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11822 { 11823 return hclge_config_switch_param(hdev, vf, enable, 11824 HCLGE_SWITCH_ANTI_SPOOF_MASK); 11825 } 11826 11827 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11828 { 11829 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 11830 HCLGE_FILTER_FE_NIC_INGRESS_B, 11831 enable, vf); 11832 } 11833 11834 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) 11835 { 11836 int ret; 11837 11838 ret = hclge_set_mac_spoofchk(hdev, vf, enable); 11839 if (ret) { 11840 dev_err(&hdev->pdev->dev, 11841 "Set vf %d mac spoof check %s failed, ret=%d\n", 11842 vf, enable ? "on" : "off", ret); 11843 return ret; 11844 } 11845 11846 ret = hclge_set_vlan_spoofchk(hdev, vf, enable); 11847 if (ret) 11848 dev_err(&hdev->pdev->dev, 11849 "Set vf %d vlan spoof check %s failed, ret=%d\n", 11850 vf, enable ? "on" : "off", ret); 11851 11852 return ret; 11853 } 11854 11855 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf, 11856 bool enable) 11857 { 11858 struct hclge_vport *vport = hclge_get_vport(handle); 11859 struct hclge_dev *hdev = vport->back; 11860 u32 new_spoofchk = enable ? 1 : 0; 11861 int ret; 11862 11863 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11864 return -EOPNOTSUPP; 11865 11866 vport = hclge_get_vf_vport(hdev, vf); 11867 if (!vport) 11868 return -EINVAL; 11869 11870 if (vport->vf_info.spoofchk == new_spoofchk) 11871 return 0; 11872 11873 if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full)) 11874 dev_warn(&hdev->pdev->dev, 11875 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n", 11876 vf); 11877 else if (enable && hclge_is_umv_space_full(vport, true)) 11878 dev_warn(&hdev->pdev->dev, 11879 "vf %d mac table is full, enable spoof check may cause its packet send fail\n", 11880 vf); 11881 11882 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable); 11883 if (ret) 11884 return ret; 11885 11886 vport->vf_info.spoofchk = new_spoofchk; 11887 return 0; 11888 } 11889 11890 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev) 11891 { 11892 struct hclge_vport *vport = hdev->vport; 11893 int ret; 11894 int i; 11895 11896 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11897 return 0; 11898 11899 /* resume the vf spoof check state after reset */ 11900 for (i = 0; i < hdev->num_alloc_vport; i++) { 11901 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, 11902 vport->vf_info.spoofchk); 11903 if (ret) 11904 return ret; 11905 11906 vport++; 11907 } 11908 11909 return 0; 11910 } 11911 11912 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable) 11913 { 11914 struct hclge_vport *vport = hclge_get_vport(handle); 11915 struct hclge_dev *hdev = vport->back; 11916 u32 new_trusted = enable ? 1 : 0; 11917 11918 vport = hclge_get_vf_vport(hdev, vf); 11919 if (!vport) 11920 return -EINVAL; 11921 11922 if (vport->vf_info.trusted == new_trusted) 11923 return 0; 11924 11925 vport->vf_info.trusted = new_trusted; 11926 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 11927 hclge_task_schedule(hdev, 0); 11928 11929 return 0; 11930 } 11931 11932 static void hclge_reset_vf_rate(struct hclge_dev *hdev) 11933 { 11934 int ret; 11935 int vf; 11936 11937 /* reset vf rate to default value */ 11938 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 11939 struct hclge_vport *vport = &hdev->vport[vf]; 11940 11941 vport->vf_info.max_tx_rate = 0; 11942 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); 11943 if (ret) 11944 dev_err(&hdev->pdev->dev, 11945 "vf%d failed to reset to default, ret=%d\n", 11946 vf - HCLGE_VF_VPORT_START_NUM, ret); 11947 } 11948 } 11949 11950 static int hclge_vf_rate_param_check(struct hclge_dev *hdev, 11951 int min_tx_rate, int max_tx_rate) 11952 { 11953 if (min_tx_rate != 0 || 11954 max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) { 11955 dev_err(&hdev->pdev->dev, 11956 "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n", 11957 min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed); 11958 return -EINVAL; 11959 } 11960 11961 return 0; 11962 } 11963 11964 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf, 11965 int min_tx_rate, int max_tx_rate, bool force) 11966 { 11967 struct hclge_vport *vport = hclge_get_vport(handle); 11968 struct hclge_dev *hdev = vport->back; 11969 int ret; 11970 11971 ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate); 11972 if (ret) 11973 return ret; 11974 11975 vport = hclge_get_vf_vport(hdev, vf); 11976 if (!vport) 11977 return -EINVAL; 11978 11979 if (!force && max_tx_rate == vport->vf_info.max_tx_rate) 11980 return 0; 11981 11982 ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); 11983 if (ret) 11984 return ret; 11985 11986 vport->vf_info.max_tx_rate = max_tx_rate; 11987 11988 return 0; 11989 } 11990 11991 static int hclge_resume_vf_rate(struct hclge_dev *hdev) 11992 { 11993 struct hnae3_handle *handle = &hdev->vport->nic; 11994 struct hclge_vport *vport; 11995 int ret; 11996 int vf; 11997 11998 /* resume the vf max_tx_rate after reset */ 11999 for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) { 12000 vport = hclge_get_vf_vport(hdev, vf); 12001 if (!vport) 12002 return -EINVAL; 12003 12004 /* zero means max rate, after reset, firmware already set it to 12005 * max rate, so just continue. 12006 */ 12007 if (!vport->vf_info.max_tx_rate) 12008 continue; 12009 12010 ret = hclge_set_vf_rate(handle, vf, 0, 12011 vport->vf_info.max_tx_rate, true); 12012 if (ret) { 12013 dev_err(&hdev->pdev->dev, 12014 "vf%d failed to resume tx_rate:%u, ret=%d\n", 12015 vf, vport->vf_info.max_tx_rate, ret); 12016 return ret; 12017 } 12018 } 12019 12020 return 0; 12021 } 12022 12023 static void hclge_reset_vport_state(struct hclge_dev *hdev) 12024 { 12025 struct hclge_vport *vport = hdev->vport; 12026 int i; 12027 12028 for (i = 0; i < hdev->num_alloc_vport; i++) { 12029 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12030 vport++; 12031 } 12032 } 12033 12034 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 12035 { 12036 struct hclge_dev *hdev = ae_dev->priv; 12037 struct pci_dev *pdev = ae_dev->pdev; 12038 int ret; 12039 12040 set_bit(HCLGE_STATE_DOWN, &hdev->state); 12041 12042 hclge_stats_clear(hdev); 12043 /* NOTE: pf reset needn't to clear or restore pf and vf table entry. 12044 * so here should not clean table in memory. 12045 */ 12046 if (hdev->reset_type == HNAE3_IMP_RESET || 12047 hdev->reset_type == HNAE3_GLOBAL_RESET) { 12048 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 12049 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full)); 12050 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport); 12051 hclge_reset_umv_space(hdev); 12052 } 12053 12054 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 12055 true, hdev->reset_pending); 12056 if (ret) { 12057 dev_err(&pdev->dev, "Cmd queue init failed\n"); 12058 return ret; 12059 } 12060 12061 ret = hclge_map_tqp(hdev); 12062 if (ret) { 12063 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 12064 return ret; 12065 } 12066 12067 ret = hclge_mac_init(hdev); 12068 if (ret) { 12069 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 12070 return ret; 12071 } 12072 12073 ret = hclge_tp_port_init(hdev); 12074 if (ret) { 12075 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n", 12076 ret); 12077 return ret; 12078 } 12079 12080 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 12081 if (ret) { 12082 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 12083 return ret; 12084 } 12085 12086 ret = hclge_config_gro(hdev); 12087 if (ret) 12088 return ret; 12089 12090 ret = hclge_init_vlan_config(hdev); 12091 if (ret) { 12092 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 12093 return ret; 12094 } 12095 12096 ret = hclge_tm_init_hw(hdev, true); 12097 if (ret) { 12098 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 12099 return ret; 12100 } 12101 12102 ret = hclge_rss_init_hw(hdev); 12103 if (ret) { 12104 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 12105 return ret; 12106 } 12107 12108 ret = init_mgr_tbl(hdev); 12109 if (ret) { 12110 dev_err(&pdev->dev, 12111 "failed to reinit manager table, ret = %d\n", ret); 12112 return ret; 12113 } 12114 12115 ret = hclge_init_fd_config(hdev); 12116 if (ret) { 12117 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret); 12118 return ret; 12119 } 12120 12121 ret = hclge_ptp_init(hdev); 12122 if (ret) 12123 return ret; 12124 12125 /* Log and clear the hw errors those already occurred */ 12126 if (hnae3_dev_ras_imp_supported(hdev)) 12127 hclge_handle_occurred_error(hdev); 12128 else 12129 hclge_handle_all_hns_hw_errors(ae_dev); 12130 12131 /* Re-enable the hw error interrupts because 12132 * the interrupts get disabled on global reset. 12133 */ 12134 ret = hclge_config_nic_hw_error(hdev, true); 12135 if (ret) { 12136 dev_err(&pdev->dev, 12137 "fail(%d) to re-enable NIC hw error interrupts\n", 12138 ret); 12139 return ret; 12140 } 12141 12142 if (hdev->roce_client) { 12143 ret = hclge_config_rocee_ras_interrupt(hdev, true); 12144 if (ret) { 12145 dev_err(&pdev->dev, 12146 "fail(%d) to re-enable roce ras interrupts\n", 12147 ret); 12148 return ret; 12149 } 12150 } 12151 12152 hclge_reset_vport_state(hdev); 12153 ret = hclge_reset_vport_spoofchk(hdev); 12154 if (ret) 12155 return ret; 12156 12157 ret = hclge_resume_vf_rate(hdev); 12158 if (ret) 12159 return ret; 12160 12161 hclge_init_rxd_adv_layout(hdev); 12162 12163 ret = hclge_update_wol(hdev); 12164 if (ret) 12165 dev_warn(&pdev->dev, 12166 "failed to update wol config, ret = %d\n", ret); 12167 12168 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 12169 HCLGE_DRIVER_NAME); 12170 12171 return 0; 12172 } 12173 12174 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 12175 { 12176 struct hclge_dev *hdev = ae_dev->priv; 12177 struct hclge_mac *mac = &hdev->hw.mac; 12178 12179 hclge_reset_vf_rate(hdev); 12180 hclge_clear_vf_vlan(hdev); 12181 hclge_state_uninit(hdev); 12182 hclge_ptp_uninit(hdev); 12183 hclge_uninit_rxd_adv_layout(hdev); 12184 hclge_uninit_mac_table(hdev); 12185 hclge_del_all_fd_entries(hdev); 12186 12187 if (mac->phydev) 12188 mdiobus_unregister(mac->mdio_bus); 12189 12190 /* Disable MISC vector(vector0) */ 12191 hclge_enable_vector(&hdev->misc_vector, false); 12192 synchronize_irq(hdev->misc_vector.vector_irq); 12193 12194 /* Disable all hw interrupts */ 12195 hclge_config_mac_tnl_int(hdev, false); 12196 hclge_config_nic_hw_error(hdev, false); 12197 hclge_config_rocee_ras_interrupt(hdev, false); 12198 12199 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 12200 hclge_misc_irq_uninit(hdev); 12201 hclge_devlink_uninit(hdev); 12202 hclge_pci_uninit(hdev); 12203 hclge_uninit_vport_vlan_table(hdev); 12204 mutex_destroy(&hdev->vport_lock); 12205 ae_dev->priv = NULL; 12206 } 12207 12208 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 12209 { 12210 struct hclge_vport *vport = hclge_get_vport(handle); 12211 struct hclge_dev *hdev = vport->back; 12212 12213 return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps); 12214 } 12215 12216 static void hclge_get_channels(struct hnae3_handle *handle, 12217 struct ethtool_channels *ch) 12218 { 12219 ch->max_combined = hclge_get_max_channels(handle); 12220 ch->other_count = 1; 12221 ch->max_other = 1; 12222 ch->combined_count = handle->kinfo.rss_size; 12223 } 12224 12225 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 12226 u16 *alloc_tqps, u16 *max_rss_size) 12227 { 12228 struct hclge_vport *vport = hclge_get_vport(handle); 12229 struct hclge_dev *hdev = vport->back; 12230 12231 *alloc_tqps = vport->alloc_tqps; 12232 *max_rss_size = hdev->pf_rss_size_max; 12233 } 12234 12235 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle) 12236 { 12237 struct hclge_vport *vport = hclge_get_vport(handle); 12238 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 12239 struct hclge_dev *hdev = vport->back; 12240 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 12241 u16 tc_valid[HCLGE_MAX_TC_NUM]; 12242 u16 roundup_size; 12243 unsigned int i; 12244 12245 roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size); 12246 roundup_size = ilog2(roundup_size); 12247 /* Set the RSS TC mode according to the new RSS size */ 12248 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 12249 tc_valid[i] = 0; 12250 12251 if (!(hdev->hw_tc_map & BIT(i))) 12252 continue; 12253 12254 tc_valid[i] = 1; 12255 tc_size[i] = roundup_size; 12256 tc_offset[i] = vport->nic.kinfo.rss_size * i; 12257 } 12258 12259 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 12260 tc_size); 12261 } 12262 12263 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 12264 bool rxfh_configured) 12265 { 12266 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 12267 struct hclge_vport *vport = hclge_get_vport(handle); 12268 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 12269 struct hclge_dev *hdev = vport->back; 12270 u16 cur_rss_size = kinfo->rss_size; 12271 u16 cur_tqps = kinfo->num_tqps; 12272 u32 *rss_indir; 12273 unsigned int i; 12274 int ret; 12275 12276 kinfo->req_rss_size = new_tqps_num; 12277 12278 ret = hclge_tm_vport_map_update(hdev); 12279 if (ret) { 12280 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret); 12281 return ret; 12282 } 12283 12284 ret = hclge_set_rss_tc_mode_cfg(handle); 12285 if (ret) 12286 return ret; 12287 12288 /* RSS indirection table has been configured by user */ 12289 if (rxfh_configured) 12290 goto out; 12291 12292 /* Reinitializes the rss indirect table according to the new RSS size */ 12293 rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32), 12294 GFP_KERNEL); 12295 if (!rss_indir) 12296 return -ENOMEM; 12297 12298 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 12299 rss_indir[i] = i % kinfo->rss_size; 12300 12301 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 12302 if (ret) 12303 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 12304 ret); 12305 12306 kfree(rss_indir); 12307 12308 out: 12309 if (!ret) 12310 dev_info(&hdev->pdev->dev, 12311 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 12312 cur_rss_size, kinfo->rss_size, 12313 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 12314 12315 return ret; 12316 } 12317 12318 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 12319 { 12320 struct hclge_set_led_state_cmd *req; 12321 struct hclge_desc desc; 12322 int ret; 12323 12324 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 12325 12326 req = (struct hclge_set_led_state_cmd *)desc.data; 12327 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 12328 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 12329 12330 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12331 if (ret) 12332 dev_err(&hdev->pdev->dev, 12333 "Send set led state cmd error, ret =%d\n", ret); 12334 12335 return ret; 12336 } 12337 12338 enum hclge_led_status { 12339 HCLGE_LED_OFF, 12340 HCLGE_LED_ON, 12341 HCLGE_LED_NO_CHANGE = 0xFF, 12342 }; 12343 12344 static int hclge_set_led_id(struct hnae3_handle *handle, 12345 enum ethtool_phys_id_state status) 12346 { 12347 struct hclge_vport *vport = hclge_get_vport(handle); 12348 struct hclge_dev *hdev = vport->back; 12349 12350 switch (status) { 12351 case ETHTOOL_ID_ACTIVE: 12352 return hclge_set_led_status(hdev, HCLGE_LED_ON); 12353 case ETHTOOL_ID_INACTIVE: 12354 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 12355 default: 12356 return -EINVAL; 12357 } 12358 } 12359 12360 static void hclge_get_link_mode(struct hnae3_handle *handle, 12361 unsigned long *supported, 12362 unsigned long *advertising) 12363 { 12364 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 12365 struct hclge_vport *vport = hclge_get_vport(handle); 12366 struct hclge_dev *hdev = vport->back; 12367 unsigned int idx = 0; 12368 12369 for (; idx < size; idx++) { 12370 supported[idx] = hdev->hw.mac.supported[idx]; 12371 advertising[idx] = hdev->hw.mac.advertising[idx]; 12372 } 12373 } 12374 12375 static int hclge_gro_en(struct hnae3_handle *handle, bool enable) 12376 { 12377 struct hclge_vport *vport = hclge_get_vport(handle); 12378 struct hclge_dev *hdev = vport->back; 12379 bool gro_en_old = hdev->gro_en; 12380 int ret; 12381 12382 hdev->gro_en = enable; 12383 ret = hclge_config_gro(hdev); 12384 if (ret) 12385 hdev->gro_en = gro_en_old; 12386 12387 return ret; 12388 } 12389 12390 static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport) 12391 { 12392 struct hnae3_handle *handle = &vport->nic; 12393 struct hclge_dev *hdev = vport->back; 12394 bool uc_en = false; 12395 bool mc_en = false; 12396 u8 tmp_flags; 12397 bool bc_en; 12398 int ret; 12399 12400 if (vport->last_promisc_flags != vport->overflow_promisc_flags) { 12401 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12402 vport->last_promisc_flags = vport->overflow_promisc_flags; 12403 } 12404 12405 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12406 &vport->state)) 12407 return 0; 12408 12409 /* for PF */ 12410 if (!vport->vport_id) { 12411 tmp_flags = handle->netdev_flags | vport->last_promisc_flags; 12412 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE, 12413 tmp_flags & HNAE3_MPE); 12414 if (!ret) 12415 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 12416 &vport->state); 12417 else 12418 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12419 &vport->state); 12420 return ret; 12421 } 12422 12423 /* for VF */ 12424 if (vport->vf_info.trusted) { 12425 uc_en = vport->vf_info.request_uc_en > 0 || 12426 vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE; 12427 mc_en = vport->vf_info.request_mc_en > 0 || 12428 vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE; 12429 } 12430 bc_en = vport->vf_info.request_bc_en > 0; 12431 12432 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en, 12433 mc_en, bc_en); 12434 if (ret) { 12435 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12436 return ret; 12437 } 12438 hclge_set_vport_vlan_fltr_change(vport); 12439 12440 return 0; 12441 } 12442 12443 static void hclge_sync_promisc_mode(struct hclge_dev *hdev) 12444 { 12445 struct hclge_vport *vport; 12446 int ret; 12447 u16 i; 12448 12449 for (i = 0; i < hdev->num_alloc_vport; i++) { 12450 vport = &hdev->vport[i]; 12451 12452 ret = hclge_sync_vport_promisc_mode(vport); 12453 if (ret) 12454 return; 12455 } 12456 } 12457 12458 static bool hclge_module_existed(struct hclge_dev *hdev) 12459 { 12460 struct hclge_desc desc; 12461 u32 existed; 12462 int ret; 12463 12464 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true); 12465 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12466 if (ret) { 12467 dev_err(&hdev->pdev->dev, 12468 "failed to get SFP exist state, ret = %d\n", ret); 12469 return false; 12470 } 12471 12472 existed = le32_to_cpu(desc.data[0]); 12473 12474 return existed != 0; 12475 } 12476 12477 /* need 6 bds(total 140 bytes) in one reading 12478 * return the number of bytes actually read, 0 means read failed. 12479 */ 12480 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset, 12481 u32 len, u8 *data) 12482 { 12483 struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM]; 12484 struct hclge_sfp_info_bd0_cmd *sfp_info_bd0; 12485 u16 read_len; 12486 u16 copy_len; 12487 int ret; 12488 int i; 12489 12490 /* setup all 6 bds to read module eeprom info. */ 12491 for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12492 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM, 12493 true); 12494 12495 /* bd0~bd4 need next flag */ 12496 if (i < HCLGE_SFP_INFO_CMD_NUM - 1) 12497 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12498 } 12499 12500 /* setup bd0, this bd contains offset and read length. */ 12501 sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data; 12502 sfp_info_bd0->offset = cpu_to_le16((u16)offset); 12503 read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN); 12504 sfp_info_bd0->read_len = cpu_to_le16(read_len); 12505 12506 ret = hclge_cmd_send(&hdev->hw, desc, i); 12507 if (ret) { 12508 dev_err(&hdev->pdev->dev, 12509 "failed to get SFP eeprom info, ret = %d\n", ret); 12510 return 0; 12511 } 12512 12513 /* copy sfp info from bd0 to out buffer. */ 12514 copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN); 12515 memcpy(data, sfp_info_bd0->data, copy_len); 12516 read_len = copy_len; 12517 12518 /* copy sfp info from bd1~bd5 to out buffer if needed. */ 12519 for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12520 if (read_len >= len) 12521 return read_len; 12522 12523 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN); 12524 memcpy(data + read_len, desc[i].data, copy_len); 12525 read_len += copy_len; 12526 } 12527 12528 return read_len; 12529 } 12530 12531 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset, 12532 u32 len, u8 *data) 12533 { 12534 struct hclge_vport *vport = hclge_get_vport(handle); 12535 struct hclge_dev *hdev = vport->back; 12536 u32 read_len = 0; 12537 u16 data_len; 12538 12539 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 12540 return -EOPNOTSUPP; 12541 12542 if (!hclge_module_existed(hdev)) 12543 return -ENXIO; 12544 12545 while (read_len < len) { 12546 data_len = hclge_get_sfp_eeprom_info(hdev, 12547 offset + read_len, 12548 len - read_len, 12549 data + read_len); 12550 if (!data_len) 12551 return -EIO; 12552 12553 read_len += data_len; 12554 } 12555 12556 return 0; 12557 } 12558 12559 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle, 12560 u32 *status_code) 12561 { 12562 struct hclge_vport *vport = hclge_get_vport(handle); 12563 struct hclge_dev *hdev = vport->back; 12564 struct hclge_desc desc; 12565 int ret; 12566 12567 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 12568 return -EOPNOTSUPP; 12569 12570 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true); 12571 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12572 if (ret) { 12573 dev_err(&hdev->pdev->dev, 12574 "failed to query link diagnosis info, ret = %d\n", ret); 12575 return ret; 12576 } 12577 12578 *status_code = le32_to_cpu(desc.data[0]); 12579 return 0; 12580 } 12581 12582 /* After disable sriov, VF still has some config and info need clean, 12583 * which configed by PF. 12584 */ 12585 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid) 12586 { 12587 struct hclge_dev *hdev = vport->back; 12588 struct hclge_vlan_info vlan_info; 12589 int ret; 12590 12591 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 12592 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 12593 vport->need_notify = 0; 12594 vport->mps = 0; 12595 12596 /* after disable sriov, clean VF rate configured by PF */ 12597 ret = hclge_tm_qs_shaper_cfg(vport, 0); 12598 if (ret) 12599 dev_err(&hdev->pdev->dev, 12600 "failed to clean vf%d rate config, ret = %d\n", 12601 vfid, ret); 12602 12603 vlan_info.vlan_tag = 0; 12604 vlan_info.qos = 0; 12605 vlan_info.vlan_proto = ETH_P_8021Q; 12606 ret = hclge_update_port_base_vlan_cfg(vport, 12607 HNAE3_PORT_BASE_VLAN_DISABLE, 12608 &vlan_info); 12609 if (ret) 12610 dev_err(&hdev->pdev->dev, 12611 "failed to clean vf%d port base vlan, ret = %d\n", 12612 vfid, ret); 12613 12614 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false); 12615 if (ret) 12616 dev_err(&hdev->pdev->dev, 12617 "failed to clean vf%d spoof config, ret = %d\n", 12618 vfid, ret); 12619 12620 memset(&vport->vf_info, 0, sizeof(vport->vf_info)); 12621 } 12622 12623 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs) 12624 { 12625 struct hclge_dev *hdev = ae_dev->priv; 12626 struct hclge_vport *vport; 12627 int i; 12628 12629 for (i = 0; i < num_vfs; i++) { 12630 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 12631 12632 hclge_clear_vport_vf_info(vport, i); 12633 } 12634 } 12635 12636 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode, 12637 u8 *priority) 12638 { 12639 struct hclge_vport *vport = hclge_get_vport(h); 12640 12641 if (dscp >= HNAE3_MAX_DSCP) 12642 return -EINVAL; 12643 12644 if (tc_mode) 12645 *tc_mode = vport->nic.kinfo.tc_map_mode; 12646 if (priority) 12647 *priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 : 12648 vport->nic.kinfo.dscp_prio[dscp]; 12649 12650 return 0; 12651 } 12652 12653 static const struct hnae3_ae_ops hclge_ops = { 12654 .init_ae_dev = hclge_init_ae_dev, 12655 .uninit_ae_dev = hclge_uninit_ae_dev, 12656 .reset_prepare = hclge_reset_prepare_general, 12657 .reset_done = hclge_reset_done, 12658 .init_client_instance = hclge_init_client_instance, 12659 .uninit_client_instance = hclge_uninit_client_instance, 12660 .map_ring_to_vector = hclge_map_ring_to_vector, 12661 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 12662 .get_vector = hclge_get_vector, 12663 .put_vector = hclge_put_vector, 12664 .set_promisc_mode = hclge_set_promisc_mode, 12665 .request_update_promisc_mode = hclge_request_update_promisc_mode, 12666 .set_loopback = hclge_set_loopback, 12667 .start = hclge_ae_start, 12668 .stop = hclge_ae_stop, 12669 .client_start = hclge_client_start, 12670 .client_stop = hclge_client_stop, 12671 .get_status = hclge_get_status, 12672 .get_ksettings_an_result = hclge_get_ksettings_an_result, 12673 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 12674 .get_media_type = hclge_get_media_type, 12675 .check_port_speed = hclge_check_port_speed, 12676 .get_fec_stats = hclge_get_fec_stats, 12677 .get_fec = hclge_get_fec, 12678 .set_fec = hclge_set_fec, 12679 .get_rss_key_size = hclge_comm_get_rss_key_size, 12680 .get_rss = hclge_get_rss, 12681 .set_rss = hclge_set_rss, 12682 .set_rss_tuple = hclge_set_rss_tuple, 12683 .get_rss_tuple = hclge_get_rss_tuple, 12684 .get_tc_size = hclge_get_tc_size, 12685 .get_mac_addr = hclge_get_mac_addr, 12686 .set_mac_addr = hclge_set_mac_addr, 12687 .do_ioctl = hclge_do_ioctl, 12688 .add_uc_addr = hclge_add_uc_addr, 12689 .rm_uc_addr = hclge_rm_uc_addr, 12690 .add_mc_addr = hclge_add_mc_addr, 12691 .rm_mc_addr = hclge_rm_mc_addr, 12692 .set_autoneg = hclge_set_autoneg, 12693 .get_autoneg = hclge_get_autoneg, 12694 .restart_autoneg = hclge_restart_autoneg, 12695 .halt_autoneg = hclge_halt_autoneg, 12696 .get_pauseparam = hclge_get_pauseparam, 12697 .set_pauseparam = hclge_set_pauseparam, 12698 .set_mtu = hclge_set_mtu, 12699 .reset_queue = hclge_reset_tqp, 12700 .get_stats = hclge_get_stats, 12701 .get_mac_stats = hclge_get_mac_stat, 12702 .update_stats = hclge_update_stats, 12703 .get_strings = hclge_get_strings, 12704 .get_sset_count = hclge_get_sset_count, 12705 .get_fw_version = hclge_get_fw_version, 12706 .get_mdix_mode = hclge_get_mdix_mode, 12707 .enable_vlan_filter = hclge_enable_vlan_filter, 12708 .set_vlan_filter = hclge_set_vlan_filter, 12709 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 12710 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 12711 .reset_event = hclge_reset_event, 12712 .get_reset_level = hclge_get_reset_level, 12713 .set_default_reset_request = hclge_set_def_reset_request, 12714 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 12715 .set_channels = hclge_set_channels, 12716 .get_channels = hclge_get_channels, 12717 .get_regs_len = hclge_get_regs_len, 12718 .get_regs = hclge_get_regs, 12719 .set_led_id = hclge_set_led_id, 12720 .get_link_mode = hclge_get_link_mode, 12721 .add_fd_entry = hclge_add_fd_entry, 12722 .del_fd_entry = hclge_del_fd_entry, 12723 .get_fd_rule_cnt = hclge_get_fd_rule_cnt, 12724 .get_fd_rule_info = hclge_get_fd_rule_info, 12725 .get_fd_all_rules = hclge_get_all_rules, 12726 .enable_fd = hclge_enable_fd, 12727 .add_arfs_entry = hclge_add_fd_entry_by_arfs, 12728 .dbg_read_cmd = hclge_dbg_read_cmd, 12729 .handle_hw_ras_error = hclge_handle_hw_ras_error, 12730 .get_hw_reset_stat = hclge_get_hw_reset_stat, 12731 .ae_dev_resetting = hclge_ae_dev_resetting, 12732 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt, 12733 .set_gro_en = hclge_gro_en, 12734 .get_global_queue_id = hclge_covert_handle_qid_global, 12735 .set_timer_task = hclge_set_timer_task, 12736 .mac_connect_phy = hclge_mac_connect_phy, 12737 .mac_disconnect_phy = hclge_mac_disconnect_phy, 12738 .get_vf_config = hclge_get_vf_config, 12739 .set_vf_link_state = hclge_set_vf_link_state, 12740 .set_vf_spoofchk = hclge_set_vf_spoofchk, 12741 .set_vf_trust = hclge_set_vf_trust, 12742 .set_vf_rate = hclge_set_vf_rate, 12743 .set_vf_mac = hclge_set_vf_mac, 12744 .get_module_eeprom = hclge_get_module_eeprom, 12745 .get_cmdq_stat = hclge_get_cmdq_stat, 12746 .add_cls_flower = hclge_add_cls_flower, 12747 .del_cls_flower = hclge_del_cls_flower, 12748 .cls_flower_active = hclge_is_cls_flower_active, 12749 .get_phy_link_ksettings = hclge_get_phy_link_ksettings, 12750 .set_phy_link_ksettings = hclge_set_phy_link_ksettings, 12751 .set_tx_hwts_info = hclge_ptp_set_tx_info, 12752 .get_rx_hwts = hclge_ptp_get_rx_hwts, 12753 .get_ts_info = hclge_ptp_get_ts_info, 12754 .get_link_diagnosis_info = hclge_get_link_diagnosis_info, 12755 .clean_vf_config = hclge_clean_vport_config, 12756 .get_dscp_prio = hclge_get_dscp_prio, 12757 .get_wol = hclge_get_wol, 12758 .set_wol = hclge_set_wol, 12759 }; 12760 12761 static struct hnae3_ae_algo ae_algo = { 12762 .ops = &hclge_ops, 12763 .pdev_id_table = ae_algo_pci_tbl, 12764 }; 12765 12766 static int __init hclge_init(void) 12767 { 12768 pr_info("%s is initializing\n", HCLGE_NAME); 12769 12770 hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGE_NAME); 12771 if (!hclge_wq) { 12772 pr_err("%s: failed to create workqueue\n", HCLGE_NAME); 12773 return -ENOMEM; 12774 } 12775 12776 hnae3_register_ae_algo(&ae_algo); 12777 12778 return 0; 12779 } 12780 12781 static void __exit hclge_exit(void) 12782 { 12783 hnae3_unregister_ae_algo_prepare(&ae_algo); 12784 hnae3_unregister_ae_algo(&ae_algo); 12785 destroy_workqueue(hclge_wq); 12786 } 12787 module_init(hclge_init); 12788 module_exit(hclge_exit); 12789 12790 MODULE_LICENSE("GPL"); 12791 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 12792 MODULE_DESCRIPTION("HCLGE Driver"); 12793 MODULE_VERSION(HCLGE_MOD_VERSION); 12794