1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/pci.h> 13 #include <linux/platform_device.h> 14 #include <linux/if_vlan.h> 15 #include <linux/crash_dump.h> 16 #include <net/ipv6.h> 17 #include <net/rtnetlink.h> 18 #include "hclge_cmd.h" 19 #include "hclge_dcb.h" 20 #include "hclge_main.h" 21 #include "hclge_mbx.h" 22 #include "hclge_mdio.h" 23 #include "hclge_tm.h" 24 #include "hclge_err.h" 25 #include "hnae3.h" 26 #include "hclge_devlink.h" 27 #include "hclge_comm_cmd.h" 28 29 #define HCLGE_NAME "hclge" 30 31 #define HCLGE_BUF_SIZE_UNIT 256U 32 #define HCLGE_BUF_MUL_BY 2 33 #define HCLGE_BUF_DIV_BY 2 34 #define NEED_RESERVE_TC_NUM 2 35 #define BUF_MAX_PERCENT 100 36 #define BUF_RESERVE_PERCENT 90 37 38 #define HCLGE_RESET_MAX_FAIL_CNT 5 39 #define HCLGE_RESET_SYNC_TIME 100 40 #define HCLGE_PF_RESET_SYNC_TIME 20 41 #define HCLGE_PF_RESET_SYNC_CNT 1500 42 43 /* Get DFX BD number offset */ 44 #define HCLGE_DFX_BIOS_BD_OFFSET 1 45 #define HCLGE_DFX_SSU_0_BD_OFFSET 2 46 #define HCLGE_DFX_SSU_1_BD_OFFSET 3 47 #define HCLGE_DFX_IGU_BD_OFFSET 4 48 #define HCLGE_DFX_RPU_0_BD_OFFSET 5 49 #define HCLGE_DFX_RPU_1_BD_OFFSET 6 50 #define HCLGE_DFX_NCSI_BD_OFFSET 7 51 #define HCLGE_DFX_RTC_BD_OFFSET 8 52 #define HCLGE_DFX_PPP_BD_OFFSET 9 53 #define HCLGE_DFX_RCB_BD_OFFSET 10 54 #define HCLGE_DFX_TQP_BD_OFFSET 11 55 #define HCLGE_DFX_SSU_2_BD_OFFSET 12 56 57 #define HCLGE_LINK_STATUS_MS 10 58 59 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps); 60 static int hclge_init_vlan_config(struct hclge_dev *hdev); 61 static void hclge_sync_vlan_filter(struct hclge_dev *hdev); 62 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 63 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle); 64 static void hclge_rfs_filter_expire(struct hclge_dev *hdev); 65 static int hclge_clear_arfs_rules(struct hclge_dev *hdev); 66 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 67 unsigned long *addr); 68 static int hclge_set_default_loopback(struct hclge_dev *hdev); 69 70 static void hclge_sync_mac_table(struct hclge_dev *hdev); 71 static void hclge_restore_hw_table(struct hclge_dev *hdev); 72 static void hclge_sync_promisc_mode(struct hclge_dev *hdev); 73 static void hclge_sync_fd_table(struct hclge_dev *hdev); 74 static void hclge_update_fec_stats(struct hclge_dev *hdev); 75 76 static struct hnae3_ae_algo ae_algo; 77 78 static struct workqueue_struct *hclge_wq; 79 80 static const struct pci_device_id ae_algo_pci_tbl[] = { 81 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 83 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, 84 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, 85 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, 86 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, 87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, 88 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0}, 89 /* required last entry */ 90 {0, } 91 }; 92 93 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 94 95 static const u32 cmdq_reg_addr_list[] = {HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG, 96 HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG, 97 HCLGE_COMM_NIC_CSQ_DEPTH_REG, 98 HCLGE_COMM_NIC_CSQ_TAIL_REG, 99 HCLGE_COMM_NIC_CSQ_HEAD_REG, 100 HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG, 101 HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG, 102 HCLGE_COMM_NIC_CRQ_DEPTH_REG, 103 HCLGE_COMM_NIC_CRQ_TAIL_REG, 104 HCLGE_COMM_NIC_CRQ_HEAD_REG, 105 HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, 106 HCLGE_COMM_CMDQ_INTR_STS_REG, 107 HCLGE_COMM_CMDQ_INTR_EN_REG, 108 HCLGE_COMM_CMDQ_INTR_GEN_REG}; 109 110 static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE, 111 HCLGE_PF_OTHER_INT_REG, 112 HCLGE_MISC_RESET_STS_REG, 113 HCLGE_MISC_VECTOR_INT_STS, 114 HCLGE_GLOBAL_RESET_REG, 115 HCLGE_FUN_RST_ING, 116 HCLGE_GRO_EN_REG}; 117 118 static const u32 ring_reg_addr_list[] = {HCLGE_RING_RX_ADDR_L_REG, 119 HCLGE_RING_RX_ADDR_H_REG, 120 HCLGE_RING_RX_BD_NUM_REG, 121 HCLGE_RING_RX_BD_LENGTH_REG, 122 HCLGE_RING_RX_MERGE_EN_REG, 123 HCLGE_RING_RX_TAIL_REG, 124 HCLGE_RING_RX_HEAD_REG, 125 HCLGE_RING_RX_FBD_NUM_REG, 126 HCLGE_RING_RX_OFFSET_REG, 127 HCLGE_RING_RX_FBD_OFFSET_REG, 128 HCLGE_RING_RX_STASH_REG, 129 HCLGE_RING_RX_BD_ERR_REG, 130 HCLGE_RING_TX_ADDR_L_REG, 131 HCLGE_RING_TX_ADDR_H_REG, 132 HCLGE_RING_TX_BD_NUM_REG, 133 HCLGE_RING_TX_PRIORITY_REG, 134 HCLGE_RING_TX_TC_REG, 135 HCLGE_RING_TX_MERGE_EN_REG, 136 HCLGE_RING_TX_TAIL_REG, 137 HCLGE_RING_TX_HEAD_REG, 138 HCLGE_RING_TX_FBD_NUM_REG, 139 HCLGE_RING_TX_OFFSET_REG, 140 HCLGE_RING_TX_EBD_NUM_REG, 141 HCLGE_RING_TX_EBD_OFFSET_REG, 142 HCLGE_RING_TX_BD_ERR_REG, 143 HCLGE_RING_EN_REG}; 144 145 static const u32 tqp_intr_reg_addr_list[] = {HCLGE_TQP_INTR_CTRL_REG, 146 HCLGE_TQP_INTR_GL0_REG, 147 HCLGE_TQP_INTR_GL1_REG, 148 HCLGE_TQP_INTR_GL2_REG, 149 HCLGE_TQP_INTR_RL_REG}; 150 151 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 152 "App Loopback test", 153 "Serdes serial Loopback test", 154 "Serdes parallel Loopback test", 155 "Phy Loopback test" 156 }; 157 158 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 159 {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 160 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 161 {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 162 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 163 {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 164 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)}, 165 {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 166 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)}, 167 {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 168 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)}, 169 {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 170 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)}, 171 {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 172 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)}, 173 {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 174 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 175 {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 176 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 177 {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 178 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 179 {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 180 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 181 {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 182 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 183 {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 184 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 185 {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 186 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 187 {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 188 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 189 {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 190 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)}, 191 {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 192 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)}, 193 {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 194 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)}, 195 {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 196 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)}, 197 {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 198 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)}, 199 {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 200 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)}, 201 {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 202 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)}, 203 {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 204 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)}, 205 {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 206 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)}, 207 {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 208 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 209 {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 210 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 211 {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 212 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 213 {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 214 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 215 {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 216 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 217 {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 218 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 219 {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 220 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 221 {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 222 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 223 {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 224 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)}, 225 {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 226 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)}, 227 {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 228 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)}, 229 {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 230 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)}, 231 {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 232 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)}, 233 {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 234 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)}, 235 {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 236 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)}, 237 {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 238 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)}, 239 {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 240 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 241 {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 242 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 243 {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 244 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 245 {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 246 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 247 {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 248 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 249 {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 250 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 251 {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 252 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 253 {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 254 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 255 {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 256 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 257 {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 258 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 259 {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 260 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 261 {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 262 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 263 {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 264 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 265 {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 266 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 267 {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 268 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 269 {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 270 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 271 {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 272 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 273 {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 274 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 275 {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 277 {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 279 {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 281 {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 283 {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 285 {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 287 {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 288 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 289 {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 290 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 291 {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 292 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 293 {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 294 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 295 {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 296 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 297 {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 298 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 299 {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 300 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 301 {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 302 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 303 {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 304 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 305 {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 306 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 307 {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 308 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 309 {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 310 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 311 {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 312 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 313 {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 314 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 315 {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 316 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 317 {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 318 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 319 {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 320 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 321 {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 322 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 323 {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 324 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 325 {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 326 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 327 {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 328 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 329 {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 330 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 331 {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 332 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 333 {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 334 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 335 {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 336 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 337 {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 338 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 339 340 {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 341 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 342 {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 343 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 344 {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 345 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 346 {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 347 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 348 {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 349 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 350 {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 351 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 352 {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 354 {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 356 {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 358 {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 360 {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 361 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 362 {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 363 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 364 }; 365 366 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 367 { 368 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 369 .ethter_type = cpu_to_le16(ETH_P_LLDP), 370 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e}, 371 .i_port_bitmap = 0x1, 372 }, 373 }; 374 375 static const u32 hclge_dfx_bd_offset_list[] = { 376 HCLGE_DFX_BIOS_BD_OFFSET, 377 HCLGE_DFX_SSU_0_BD_OFFSET, 378 HCLGE_DFX_SSU_1_BD_OFFSET, 379 HCLGE_DFX_IGU_BD_OFFSET, 380 HCLGE_DFX_RPU_0_BD_OFFSET, 381 HCLGE_DFX_RPU_1_BD_OFFSET, 382 HCLGE_DFX_NCSI_BD_OFFSET, 383 HCLGE_DFX_RTC_BD_OFFSET, 384 HCLGE_DFX_PPP_BD_OFFSET, 385 HCLGE_DFX_RCB_BD_OFFSET, 386 HCLGE_DFX_TQP_BD_OFFSET, 387 HCLGE_DFX_SSU_2_BD_OFFSET 388 }; 389 390 static const enum hclge_opcode_type hclge_dfx_reg_opcode_list[] = { 391 HCLGE_OPC_DFX_BIOS_COMMON_REG, 392 HCLGE_OPC_DFX_SSU_REG_0, 393 HCLGE_OPC_DFX_SSU_REG_1, 394 HCLGE_OPC_DFX_IGU_EGU_REG, 395 HCLGE_OPC_DFX_RPU_REG_0, 396 HCLGE_OPC_DFX_RPU_REG_1, 397 HCLGE_OPC_DFX_NCSI_REG, 398 HCLGE_OPC_DFX_RTC_REG, 399 HCLGE_OPC_DFX_PPP_REG, 400 HCLGE_OPC_DFX_RCB_REG, 401 HCLGE_OPC_DFX_TQP_REG, 402 HCLGE_OPC_DFX_SSU_REG_2 403 }; 404 405 static const struct key_info meta_data_key_info[] = { 406 { PACKET_TYPE_ID, 6 }, 407 { IP_FRAGEMENT, 1 }, 408 { ROCE_TYPE, 1 }, 409 { NEXT_KEY, 5 }, 410 { VLAN_NUMBER, 2 }, 411 { SRC_VPORT, 12 }, 412 { DST_VPORT, 12 }, 413 { TUNNEL_PACKET, 1 }, 414 }; 415 416 static const struct key_info tuple_key_info[] = { 417 { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 }, 418 { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 }, 419 { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 }, 420 { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 421 { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 }, 422 { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 }, 423 { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 }, 424 { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 }, 425 { OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 }, 426 { OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 }, 427 { OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 }, 428 { OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 }, 429 { OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 }, 430 { OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 }, 431 { OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 }, 432 { OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 }, 433 { INNER_DST_MAC, 48, KEY_OPT_MAC, 434 offsetof(struct hclge_fd_rule, tuples.dst_mac), 435 offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) }, 436 { INNER_SRC_MAC, 48, KEY_OPT_MAC, 437 offsetof(struct hclge_fd_rule, tuples.src_mac), 438 offsetof(struct hclge_fd_rule, tuples_mask.src_mac) }, 439 { INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16, 440 offsetof(struct hclge_fd_rule, tuples.vlan_tag1), 441 offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) }, 442 { INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 }, 443 { INNER_ETH_TYPE, 16, KEY_OPT_LE16, 444 offsetof(struct hclge_fd_rule, tuples.ether_proto), 445 offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) }, 446 { INNER_L2_RSV, 16, KEY_OPT_LE16, 447 offsetof(struct hclge_fd_rule, tuples.l2_user_def), 448 offsetof(struct hclge_fd_rule, tuples_mask.l2_user_def) }, 449 { INNER_IP_TOS, 8, KEY_OPT_U8, 450 offsetof(struct hclge_fd_rule, tuples.ip_tos), 451 offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) }, 452 { INNER_IP_PROTO, 8, KEY_OPT_U8, 453 offsetof(struct hclge_fd_rule, tuples.ip_proto), 454 offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) }, 455 { INNER_SRC_IP, 32, KEY_OPT_IP, 456 offsetof(struct hclge_fd_rule, tuples.src_ip), 457 offsetof(struct hclge_fd_rule, tuples_mask.src_ip) }, 458 { INNER_DST_IP, 32, KEY_OPT_IP, 459 offsetof(struct hclge_fd_rule, tuples.dst_ip), 460 offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) }, 461 { INNER_L3_RSV, 16, KEY_OPT_LE16, 462 offsetof(struct hclge_fd_rule, tuples.l3_user_def), 463 offsetof(struct hclge_fd_rule, tuples_mask.l3_user_def) }, 464 { INNER_SRC_PORT, 16, KEY_OPT_LE16, 465 offsetof(struct hclge_fd_rule, tuples.src_port), 466 offsetof(struct hclge_fd_rule, tuples_mask.src_port) }, 467 { INNER_DST_PORT, 16, KEY_OPT_LE16, 468 offsetof(struct hclge_fd_rule, tuples.dst_port), 469 offsetof(struct hclge_fd_rule, tuples_mask.dst_port) }, 470 { INNER_L4_RSV, 32, KEY_OPT_LE32, 471 offsetof(struct hclge_fd_rule, tuples.l4_user_def), 472 offsetof(struct hclge_fd_rule, tuples_mask.l4_user_def) }, 473 }; 474 475 /** 476 * hclge_cmd_send - send command to command queue 477 * @hw: pointer to the hw struct 478 * @desc: prefilled descriptor for describing the command 479 * @num : the number of descriptors to be sent 480 * 481 * This is the main send command for command queue, it 482 * sends the queue, cleans the queue, etc 483 **/ 484 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 485 { 486 return hclge_comm_cmd_send(&hw->hw, desc, num); 487 } 488 489 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev) 490 { 491 #define HCLGE_MAC_CMD_NUM 21 492 493 u64 *data = (u64 *)(&hdev->mac_stats); 494 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 495 __le64 *desc_data; 496 u32 data_size; 497 int ret; 498 u32 i; 499 500 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 501 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 502 if (ret) { 503 dev_err(&hdev->pdev->dev, 504 "Get MAC pkt stats fail, status = %d.\n", ret); 505 506 return ret; 507 } 508 509 /* The first desc has a 64-bit header, so data size need to minus 1 */ 510 data_size = sizeof(desc) / (sizeof(u64)) - 1; 511 512 desc_data = (__le64 *)(&desc[0].data[0]); 513 for (i = 0; i < data_size; i++) { 514 /* data memory is continuous becase only the first desc has a 515 * header in this command 516 */ 517 *data += le64_to_cpu(*desc_data); 518 data++; 519 desc_data++; 520 } 521 522 return 0; 523 } 524 525 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev) 526 { 527 #define HCLGE_REG_NUM_PER_DESC 4 528 529 u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num; 530 u64 *data = (u64 *)(&hdev->mac_stats); 531 struct hclge_desc *desc; 532 __le64 *desc_data; 533 u32 data_size; 534 u32 desc_num; 535 int ret; 536 u32 i; 537 538 /* The first desc has a 64-bit header, so need to consider it */ 539 desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1; 540 541 /* This may be called inside atomic sections, 542 * so GFP_ATOMIC is more suitalbe here 543 */ 544 desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC); 545 if (!desc) 546 return -ENOMEM; 547 548 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true); 549 ret = hclge_cmd_send(&hdev->hw, desc, desc_num); 550 if (ret) { 551 kfree(desc); 552 return ret; 553 } 554 555 data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num); 556 557 desc_data = (__le64 *)(&desc[0].data[0]); 558 for (i = 0; i < data_size; i++) { 559 /* data memory is continuous becase only the first desc has a 560 * header in this command 561 */ 562 *data += le64_to_cpu(*desc_data); 563 data++; 564 desc_data++; 565 } 566 567 kfree(desc); 568 569 return 0; 570 } 571 572 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num) 573 { 574 struct hclge_desc desc; 575 int ret; 576 577 /* Driver needs total register number of both valid registers and 578 * reserved registers, but the old firmware only returns number 579 * of valid registers in device V2. To be compatible with these 580 * devices, driver uses a fixed value. 581 */ 582 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) { 583 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1; 584 return 0; 585 } 586 587 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true); 588 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 589 if (ret) { 590 dev_err(&hdev->pdev->dev, 591 "failed to query mac statistic reg number, ret = %d\n", 592 ret); 593 return ret; 594 } 595 596 *reg_num = le32_to_cpu(desc.data[0]); 597 if (*reg_num == 0) { 598 dev_err(&hdev->pdev->dev, 599 "mac statistic reg number is invalid!\n"); 600 return -ENODATA; 601 } 602 603 return 0; 604 } 605 606 int hclge_mac_update_stats(struct hclge_dev *hdev) 607 { 608 /* The firmware supports the new statistics acquisition method */ 609 if (hdev->ae_dev->dev_specs.mac_stats_num) 610 return hclge_mac_update_stats_complete(hdev); 611 else 612 return hclge_mac_update_stats_defective(hdev); 613 } 614 615 static int hclge_comm_get_count(struct hclge_dev *hdev, 616 const struct hclge_comm_stats_str strs[], 617 u32 size) 618 { 619 int count = 0; 620 u32 i; 621 622 for (i = 0; i < size; i++) 623 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num) 624 count++; 625 626 return count; 627 } 628 629 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, 630 const struct hclge_comm_stats_str strs[], 631 int size, u64 *data) 632 { 633 u64 *buf = data; 634 u32 i; 635 636 for (i = 0; i < size; i++) { 637 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 638 continue; 639 640 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset); 641 buf++; 642 } 643 644 return buf; 645 } 646 647 static u8 *hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, 648 const struct hclge_comm_stats_str strs[], 649 int size, u8 *data) 650 { 651 char *buff = (char *)data; 652 u32 i; 653 654 if (stringset != ETH_SS_STATS) 655 return buff; 656 657 for (i = 0; i < size; i++) { 658 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 659 continue; 660 661 snprintf(buff, ETH_GSTRING_LEN, "%s", strs[i].desc); 662 buff = buff + ETH_GSTRING_LEN; 663 } 664 665 return (u8 *)buff; 666 } 667 668 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 669 { 670 struct hnae3_handle *handle; 671 int status; 672 673 handle = &hdev->vport[0].nic; 674 if (handle->client) { 675 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 676 if (status) { 677 dev_err(&hdev->pdev->dev, 678 "Update TQPS stats fail, status = %d.\n", 679 status); 680 } 681 } 682 683 hclge_update_fec_stats(hdev); 684 685 status = hclge_mac_update_stats(hdev); 686 if (status) 687 dev_err(&hdev->pdev->dev, 688 "Update MAC stats fail, status = %d.\n", status); 689 } 690 691 static void hclge_update_stats(struct hnae3_handle *handle, 692 struct net_device_stats *net_stats) 693 { 694 struct hclge_vport *vport = hclge_get_vport(handle); 695 struct hclge_dev *hdev = vport->back; 696 int status; 697 698 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 699 return; 700 701 status = hclge_mac_update_stats(hdev); 702 if (status) 703 dev_err(&hdev->pdev->dev, 704 "Update MAC stats fail, status = %d.\n", 705 status); 706 707 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 708 if (status) 709 dev_err(&hdev->pdev->dev, 710 "Update TQPS stats fail, status = %d.\n", 711 status); 712 713 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 714 } 715 716 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 717 { 718 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \ 719 HNAE3_SUPPORT_PHY_LOOPBACK | \ 720 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \ 721 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) 722 723 struct hclge_vport *vport = hclge_get_vport(handle); 724 struct hclge_dev *hdev = vport->back; 725 int count = 0; 726 727 /* Loopback test support rules: 728 * mac: only GE mode support 729 * serdes: all mac mode will support include GE/XGE/LGE/CGE 730 * phy: only support when phy device exist on board 731 */ 732 if (stringset == ETH_SS_TEST) { 733 /* clear loopback bit flags at first */ 734 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 735 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 || 736 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 737 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 738 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 739 count += 1; 740 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; 741 } 742 743 count += 2; 744 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; 745 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; 746 747 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv && 748 hdev->hw.mac.phydev->drv->set_loopback) || 749 hnae3_dev_phy_imp_supported(hdev)) { 750 count += 1; 751 handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK; 752 } 753 } else if (stringset == ETH_SS_STATS) { 754 count = hclge_comm_get_count(hdev, g_mac_stats_string, 755 ARRAY_SIZE(g_mac_stats_string)) + 756 hclge_comm_tqps_get_sset_count(handle); 757 } 758 759 return count; 760 } 761 762 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset, 763 u8 *data) 764 { 765 struct hclge_vport *vport = hclge_get_vport(handle); 766 struct hclge_dev *hdev = vport->back; 767 u8 *p = (char *)data; 768 int size; 769 770 if (stringset == ETH_SS_STATS) { 771 size = ARRAY_SIZE(g_mac_stats_string); 772 p = hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, 773 size, p); 774 p = hclge_comm_tqps_get_strings(handle, p); 775 } else if (stringset == ETH_SS_TEST) { 776 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { 777 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_APP], 778 ETH_GSTRING_LEN); 779 p += ETH_GSTRING_LEN; 780 } 781 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { 782 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES], 783 ETH_GSTRING_LEN); 784 p += ETH_GSTRING_LEN; 785 } 786 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { 787 memcpy(p, 788 hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES], 789 ETH_GSTRING_LEN); 790 p += ETH_GSTRING_LEN; 791 } 792 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 793 memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_PHY], 794 ETH_GSTRING_LEN); 795 p += ETH_GSTRING_LEN; 796 } 797 } 798 } 799 800 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 801 { 802 struct hclge_vport *vport = hclge_get_vport(handle); 803 struct hclge_dev *hdev = vport->back; 804 u64 *p; 805 806 p = hclge_comm_get_stats(hdev, g_mac_stats_string, 807 ARRAY_SIZE(g_mac_stats_string), data); 808 p = hclge_comm_tqps_get_stats(handle, p); 809 } 810 811 static void hclge_get_mac_stat(struct hnae3_handle *handle, 812 struct hns3_mac_stats *mac_stats) 813 { 814 struct hclge_vport *vport = hclge_get_vport(handle); 815 struct hclge_dev *hdev = vport->back; 816 817 hclge_update_stats(handle, NULL); 818 819 mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num; 820 mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num; 821 } 822 823 static int hclge_parse_func_status(struct hclge_dev *hdev, 824 struct hclge_func_status_cmd *status) 825 { 826 #define HCLGE_MAC_ID_MASK 0xF 827 828 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 829 return -EINVAL; 830 831 /* Set the pf to main pf */ 832 if (status->pf_state & HCLGE_PF_STATE_MAIN) 833 hdev->flag |= HCLGE_FLAG_MAIN; 834 else 835 hdev->flag &= ~HCLGE_FLAG_MAIN; 836 837 hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK; 838 return 0; 839 } 840 841 static int hclge_query_function_status(struct hclge_dev *hdev) 842 { 843 #define HCLGE_QUERY_MAX_CNT 5 844 845 struct hclge_func_status_cmd *req; 846 struct hclge_desc desc; 847 int timeout = 0; 848 int ret; 849 850 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 851 req = (struct hclge_func_status_cmd *)desc.data; 852 853 do { 854 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 855 if (ret) { 856 dev_err(&hdev->pdev->dev, 857 "query function status failed %d.\n", ret); 858 return ret; 859 } 860 861 /* Check pf reset is done */ 862 if (req->pf_state) 863 break; 864 usleep_range(1000, 2000); 865 } while (timeout++ < HCLGE_QUERY_MAX_CNT); 866 867 return hclge_parse_func_status(hdev, req); 868 } 869 870 static int hclge_query_pf_resource(struct hclge_dev *hdev) 871 { 872 struct hclge_pf_res_cmd *req; 873 struct hclge_desc desc; 874 int ret; 875 876 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 877 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 878 if (ret) { 879 dev_err(&hdev->pdev->dev, 880 "query pf resource failed %d.\n", ret); 881 return ret; 882 } 883 884 req = (struct hclge_pf_res_cmd *)desc.data; 885 hdev->num_tqps = le16_to_cpu(req->tqp_num) + 886 le16_to_cpu(req->ext_tqp_num); 887 hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 888 889 if (req->tx_buf_size) 890 hdev->tx_buf_size = 891 le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S; 892 else 893 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 894 895 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT); 896 897 if (req->dv_buf_size) 898 hdev->dv_buf_size = 899 le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S; 900 else 901 hdev->dv_buf_size = HCLGE_DEFAULT_DV; 902 903 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT); 904 905 hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic); 906 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) { 907 dev_err(&hdev->pdev->dev, 908 "only %u msi resources available, not enough for pf(min:2).\n", 909 hdev->num_nic_msi); 910 return -EINVAL; 911 } 912 913 if (hnae3_dev_roce_supported(hdev)) { 914 hdev->num_roce_msi = 915 le16_to_cpu(req->pf_intr_vector_number_roce); 916 917 /* PF should have NIC vectors and Roce vectors, 918 * NIC vectors are queued before Roce vectors. 919 */ 920 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi; 921 } else { 922 hdev->num_msi = hdev->num_nic_msi; 923 } 924 925 return 0; 926 } 927 928 static int hclge_parse_speed(u8 speed_cmd, u32 *speed) 929 { 930 switch (speed_cmd) { 931 case HCLGE_FW_MAC_SPEED_10M: 932 *speed = HCLGE_MAC_SPEED_10M; 933 break; 934 case HCLGE_FW_MAC_SPEED_100M: 935 *speed = HCLGE_MAC_SPEED_100M; 936 break; 937 case HCLGE_FW_MAC_SPEED_1G: 938 *speed = HCLGE_MAC_SPEED_1G; 939 break; 940 case HCLGE_FW_MAC_SPEED_10G: 941 *speed = HCLGE_MAC_SPEED_10G; 942 break; 943 case HCLGE_FW_MAC_SPEED_25G: 944 *speed = HCLGE_MAC_SPEED_25G; 945 break; 946 case HCLGE_FW_MAC_SPEED_40G: 947 *speed = HCLGE_MAC_SPEED_40G; 948 break; 949 case HCLGE_FW_MAC_SPEED_50G: 950 *speed = HCLGE_MAC_SPEED_50G; 951 break; 952 case HCLGE_FW_MAC_SPEED_100G: 953 *speed = HCLGE_MAC_SPEED_100G; 954 break; 955 case HCLGE_FW_MAC_SPEED_200G: 956 *speed = HCLGE_MAC_SPEED_200G; 957 break; 958 default: 959 return -EINVAL; 960 } 961 962 return 0; 963 } 964 965 static const struct hclge_speed_bit_map speed_bit_map[] = { 966 {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT}, 967 {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT}, 968 {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT}, 969 {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT}, 970 {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT}, 971 {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT}, 972 {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BIT}, 973 {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BIT}, 974 {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT}, 975 }; 976 977 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit) 978 { 979 u16 i; 980 981 for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) { 982 if (speed == speed_bit_map[i].speed) { 983 *speed_bit = speed_bit_map[i].speed_bit; 984 return 0; 985 } 986 } 987 988 return -EINVAL; 989 } 990 991 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed) 992 { 993 struct hclge_vport *vport = hclge_get_vport(handle); 994 struct hclge_dev *hdev = vport->back; 995 u32 speed_ability = hdev->hw.mac.speed_ability; 996 u32 speed_bit = 0; 997 int ret; 998 999 ret = hclge_get_speed_bit(speed, &speed_bit); 1000 if (ret) 1001 return ret; 1002 1003 if (speed_bit & speed_ability) 1004 return 0; 1005 1006 return -EINVAL; 1007 } 1008 1009 static void hclge_update_fec_support(struct hclge_mac *mac) 1010 { 1011 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported); 1012 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported); 1013 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported); 1014 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1015 1016 if (mac->fec_ability & BIT(HNAE3_FEC_BASER)) 1017 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1018 mac->supported); 1019 if (mac->fec_ability & BIT(HNAE3_FEC_RS)) 1020 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1021 mac->supported); 1022 if (mac->fec_ability & BIT(HNAE3_FEC_LLRS)) 1023 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1024 mac->supported); 1025 if (mac->fec_ability & BIT(HNAE3_FEC_NONE)) 1026 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1027 mac->supported); 1028 } 1029 1030 static void hclge_convert_setting_sr(u16 speed_ability, 1031 unsigned long *link_mode) 1032 { 1033 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1034 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1035 link_mode); 1036 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1037 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1038 link_mode); 1039 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1040 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 1041 link_mode); 1042 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1043 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 1044 link_mode); 1045 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1046 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 1047 link_mode); 1048 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1049 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 1050 link_mode); 1051 } 1052 1053 static void hclge_convert_setting_lr(u16 speed_ability, 1054 unsigned long *link_mode) 1055 { 1056 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1057 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 1058 link_mode); 1059 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1060 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1061 link_mode); 1062 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1063 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 1064 link_mode); 1065 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1066 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 1067 link_mode); 1068 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1069 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 1070 link_mode); 1071 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1072 linkmode_set_bit( 1073 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 1074 link_mode); 1075 } 1076 1077 static void hclge_convert_setting_cr(u16 speed_ability, 1078 unsigned long *link_mode) 1079 { 1080 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1081 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 1082 link_mode); 1083 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1084 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 1085 link_mode); 1086 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1087 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 1088 link_mode); 1089 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1090 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 1091 link_mode); 1092 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1093 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 1094 link_mode); 1095 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1096 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT, 1097 link_mode); 1098 } 1099 1100 static void hclge_convert_setting_kr(u16 speed_ability, 1101 unsigned long *link_mode) 1102 { 1103 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1104 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 1105 link_mode); 1106 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1107 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1108 link_mode); 1109 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1110 linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 1111 link_mode); 1112 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1113 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 1114 link_mode); 1115 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1116 linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 1117 link_mode); 1118 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1119 linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 1120 link_mode); 1121 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1122 linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 1123 link_mode); 1124 } 1125 1126 static void hclge_convert_setting_fec(struct hclge_mac *mac) 1127 { 1128 /* If firmware has reported fec_ability, don't need to convert by speed */ 1129 if (mac->fec_ability) 1130 goto out; 1131 1132 switch (mac->speed) { 1133 case HCLGE_MAC_SPEED_10G: 1134 case HCLGE_MAC_SPEED_40G: 1135 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) | 1136 BIT(HNAE3_FEC_NONE); 1137 break; 1138 case HCLGE_MAC_SPEED_25G: 1139 case HCLGE_MAC_SPEED_50G: 1140 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) | 1141 BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE); 1142 break; 1143 case HCLGE_MAC_SPEED_100G: 1144 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1145 BIT(HNAE3_FEC_NONE); 1146 break; 1147 case HCLGE_MAC_SPEED_200G: 1148 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1149 BIT(HNAE3_FEC_LLRS); 1150 break; 1151 default: 1152 mac->fec_ability = 0; 1153 break; 1154 } 1155 1156 out: 1157 hclge_update_fec_support(mac); 1158 } 1159 1160 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 1161 u16 speed_ability) 1162 { 1163 struct hclge_mac *mac = &hdev->hw.mac; 1164 1165 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1166 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1167 mac->supported); 1168 1169 hclge_convert_setting_sr(speed_ability, mac->supported); 1170 hclge_convert_setting_lr(speed_ability, mac->supported); 1171 hclge_convert_setting_cr(speed_ability, mac->supported); 1172 if (hnae3_dev_fec_supported(hdev)) 1173 hclge_convert_setting_fec(mac); 1174 1175 if (hnae3_dev_pause_supported(hdev)) 1176 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1177 1178 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported); 1179 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1180 } 1181 1182 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev, 1183 u16 speed_ability) 1184 { 1185 struct hclge_mac *mac = &hdev->hw.mac; 1186 1187 hclge_convert_setting_kr(speed_ability, mac->supported); 1188 if (hnae3_dev_fec_supported(hdev)) 1189 hclge_convert_setting_fec(mac); 1190 1191 if (hnae3_dev_pause_supported(hdev)) 1192 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1193 1194 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported); 1195 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1196 } 1197 1198 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev, 1199 u16 speed_ability) 1200 { 1201 unsigned long *supported = hdev->hw.mac.supported; 1202 1203 /* default to support all speed for GE port */ 1204 if (!speed_ability) 1205 speed_ability = HCLGE_SUPPORT_GE; 1206 1207 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1208 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1209 supported); 1210 1211 if (speed_ability & HCLGE_SUPPORT_100M_BIT) { 1212 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1213 supported); 1214 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1215 supported); 1216 } 1217 1218 if (speed_ability & HCLGE_SUPPORT_10M_BIT) { 1219 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported); 1220 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported); 1221 } 1222 1223 if (hnae3_dev_pause_supported(hdev)) { 1224 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1225 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 1226 } 1227 1228 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 1229 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 1230 } 1231 1232 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 1233 { 1234 u8 media_type = hdev->hw.mac.media_type; 1235 1236 if (media_type == HNAE3_MEDIA_TYPE_FIBER) 1237 hclge_parse_fiber_link_mode(hdev, speed_ability); 1238 else if (media_type == HNAE3_MEDIA_TYPE_COPPER) 1239 hclge_parse_copper_link_mode(hdev, speed_ability); 1240 else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE) 1241 hclge_parse_backplane_link_mode(hdev, speed_ability); 1242 } 1243 1244 static u32 hclge_get_max_speed(u16 speed_ability) 1245 { 1246 if (speed_ability & HCLGE_SUPPORT_200G_BIT) 1247 return HCLGE_MAC_SPEED_200G; 1248 1249 if (speed_ability & HCLGE_SUPPORT_100G_BIT) 1250 return HCLGE_MAC_SPEED_100G; 1251 1252 if (speed_ability & HCLGE_SUPPORT_50G_BIT) 1253 return HCLGE_MAC_SPEED_50G; 1254 1255 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1256 return HCLGE_MAC_SPEED_40G; 1257 1258 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1259 return HCLGE_MAC_SPEED_25G; 1260 1261 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1262 return HCLGE_MAC_SPEED_10G; 1263 1264 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1265 return HCLGE_MAC_SPEED_1G; 1266 1267 if (speed_ability & HCLGE_SUPPORT_100M_BIT) 1268 return HCLGE_MAC_SPEED_100M; 1269 1270 if (speed_ability & HCLGE_SUPPORT_10M_BIT) 1271 return HCLGE_MAC_SPEED_10M; 1272 1273 return HCLGE_MAC_SPEED_1G; 1274 } 1275 1276 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1277 { 1278 #define HCLGE_TX_SPARE_SIZE_UNIT 4096 1279 #define SPEED_ABILITY_EXT_SHIFT 8 1280 1281 struct hclge_cfg_param_cmd *req; 1282 u64 mac_addr_tmp_high; 1283 u16 speed_ability_ext; 1284 u64 mac_addr_tmp; 1285 unsigned int i; 1286 1287 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1288 1289 /* get the configuration */ 1290 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1291 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1292 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1293 HCLGE_CFG_TQP_DESC_N_M, 1294 HCLGE_CFG_TQP_DESC_N_S); 1295 1296 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1297 HCLGE_CFG_PHY_ADDR_M, 1298 HCLGE_CFG_PHY_ADDR_S); 1299 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1300 HCLGE_CFG_MEDIA_TP_M, 1301 HCLGE_CFG_MEDIA_TP_S); 1302 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1303 HCLGE_CFG_RX_BUF_LEN_M, 1304 HCLGE_CFG_RX_BUF_LEN_S); 1305 /* get mac_address */ 1306 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1307 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1308 HCLGE_CFG_MAC_ADDR_H_M, 1309 HCLGE_CFG_MAC_ADDR_H_S); 1310 1311 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1312 1313 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1314 HCLGE_CFG_DEFAULT_SPEED_M, 1315 HCLGE_CFG_DEFAULT_SPEED_S); 1316 cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1317 HCLGE_CFG_RSS_SIZE_M, 1318 HCLGE_CFG_RSS_SIZE_S); 1319 1320 for (i = 0; i < ETH_ALEN; i++) 1321 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1322 1323 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1324 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1325 1326 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1327 HCLGE_CFG_SPEED_ABILITY_M, 1328 HCLGE_CFG_SPEED_ABILITY_S); 1329 speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]), 1330 HCLGE_CFG_SPEED_ABILITY_EXT_M, 1331 HCLGE_CFG_SPEED_ABILITY_EXT_S); 1332 cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT; 1333 1334 cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]), 1335 HCLGE_CFG_VLAN_FLTR_CAP_M, 1336 HCLGE_CFG_VLAN_FLTR_CAP_S); 1337 1338 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]), 1339 HCLGE_CFG_UMV_TBL_SPACE_M, 1340 HCLGE_CFG_UMV_TBL_SPACE_S); 1341 1342 cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]), 1343 HCLGE_CFG_PF_RSS_SIZE_M, 1344 HCLGE_CFG_PF_RSS_SIZE_S); 1345 1346 /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a 1347 * power of 2, instead of reading out directly. This would 1348 * be more flexible for future changes and expansions. 1349 * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S, 1350 * it does not make sense if PF's field is 0. In this case, PF and VF 1351 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S. 1352 */ 1353 cfg->pf_rss_size_max = cfg->pf_rss_size_max ? 1354 1U << cfg->pf_rss_size_max : 1355 cfg->vf_rss_size_max; 1356 1357 /* The unit of the tx spare buffer size queried from configuration 1358 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is 1359 * needed here. 1360 */ 1361 cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]), 1362 HCLGE_CFG_TX_SPARE_BUF_SIZE_M, 1363 HCLGE_CFG_TX_SPARE_BUF_SIZE_S); 1364 cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT; 1365 } 1366 1367 /* hclge_get_cfg: query the static parameter from flash 1368 * @hdev: pointer to struct hclge_dev 1369 * @hcfg: the config structure to be getted 1370 */ 1371 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1372 { 1373 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1374 struct hclge_cfg_param_cmd *req; 1375 unsigned int i; 1376 int ret; 1377 1378 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1379 u32 offset = 0; 1380 1381 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1382 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1383 true); 1384 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1385 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1386 /* Len should be united by 4 bytes when send to hardware */ 1387 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1388 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1389 req->offset = cpu_to_le32(offset); 1390 } 1391 1392 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1393 if (ret) { 1394 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1395 return ret; 1396 } 1397 1398 hclge_parse_cfg(hcfg, desc); 1399 1400 return 0; 1401 } 1402 1403 static void hclge_set_default_dev_specs(struct hclge_dev *hdev) 1404 { 1405 #define HCLGE_MAX_NON_TSO_BD_NUM 8U 1406 1407 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1408 1409 ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1410 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1411 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1412 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE; 1413 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL; 1414 ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME; 1415 ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM; 1416 ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1417 } 1418 1419 static void hclge_parse_dev_specs(struct hclge_dev *hdev, 1420 struct hclge_desc *desc) 1421 { 1422 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1423 struct hclge_dev_specs_0_cmd *req0; 1424 struct hclge_dev_specs_1_cmd *req1; 1425 1426 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data; 1427 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data; 1428 1429 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 1430 ae_dev->dev_specs.rss_ind_tbl_size = 1431 le16_to_cpu(req0->rss_ind_tbl_size); 1432 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 1433 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 1434 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate); 1435 ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num); 1436 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 1437 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 1438 ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size); 1439 ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size); 1440 } 1441 1442 static void hclge_check_dev_specs(struct hclge_dev *hdev) 1443 { 1444 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 1445 1446 if (!dev_specs->max_non_tso_bd_num) 1447 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1448 if (!dev_specs->rss_ind_tbl_size) 1449 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1450 if (!dev_specs->rss_key_size) 1451 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1452 if (!dev_specs->max_tm_rate) 1453 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE; 1454 if (!dev_specs->max_qset_num) 1455 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM; 1456 if (!dev_specs->max_int_gl) 1457 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL; 1458 if (!dev_specs->max_frm_size) 1459 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME; 1460 if (!dev_specs->umv_size) 1461 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1462 } 1463 1464 static int hclge_query_mac_stats_num(struct hclge_dev *hdev) 1465 { 1466 u32 reg_num = 0; 1467 int ret; 1468 1469 ret = hclge_mac_query_reg_num(hdev, ®_num); 1470 if (ret && ret != -EOPNOTSUPP) 1471 return ret; 1472 1473 hdev->ae_dev->dev_specs.mac_stats_num = reg_num; 1474 return 0; 1475 } 1476 1477 static int hclge_query_dev_specs(struct hclge_dev *hdev) 1478 { 1479 struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM]; 1480 int ret; 1481 int i; 1482 1483 ret = hclge_query_mac_stats_num(hdev); 1484 if (ret) 1485 return ret; 1486 1487 /* set default specifications as devices lower than version V3 do not 1488 * support querying specifications from firmware. 1489 */ 1490 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 1491 hclge_set_default_dev_specs(hdev); 1492 return 0; 1493 } 1494 1495 for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1496 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, 1497 true); 1498 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 1499 } 1500 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 1501 1502 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM); 1503 if (ret) 1504 return ret; 1505 1506 hclge_parse_dev_specs(hdev, desc); 1507 hclge_check_dev_specs(hdev); 1508 1509 return 0; 1510 } 1511 1512 static int hclge_get_cap(struct hclge_dev *hdev) 1513 { 1514 int ret; 1515 1516 ret = hclge_query_function_status(hdev); 1517 if (ret) { 1518 dev_err(&hdev->pdev->dev, 1519 "query function status error %d.\n", ret); 1520 return ret; 1521 } 1522 1523 /* get pf resource */ 1524 return hclge_query_pf_resource(hdev); 1525 } 1526 1527 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev) 1528 { 1529 #define HCLGE_MIN_TX_DESC 64 1530 #define HCLGE_MIN_RX_DESC 64 1531 1532 if (!is_kdump_kernel()) 1533 return; 1534 1535 dev_info(&hdev->pdev->dev, 1536 "Running kdump kernel. Using minimal resources\n"); 1537 1538 /* minimal queue pairs equals to the number of vports */ 1539 hdev->num_tqps = hdev->num_req_vfs + 1; 1540 hdev->num_tx_desc = HCLGE_MIN_TX_DESC; 1541 hdev->num_rx_desc = HCLGE_MIN_RX_DESC; 1542 } 1543 1544 static void hclge_init_tc_config(struct hclge_dev *hdev) 1545 { 1546 unsigned int i; 1547 1548 if (hdev->tc_max > HNAE3_MAX_TC || 1549 hdev->tc_max < 1) { 1550 dev_warn(&hdev->pdev->dev, "TC num = %u.\n", 1551 hdev->tc_max); 1552 hdev->tc_max = 1; 1553 } 1554 1555 /* Dev does not support DCB */ 1556 if (!hnae3_dev_dcb_supported(hdev)) { 1557 hdev->tc_max = 1; 1558 hdev->pfc_max = 0; 1559 } else { 1560 hdev->pfc_max = hdev->tc_max; 1561 } 1562 1563 hdev->tm_info.num_tc = 1; 1564 1565 /* Currently not support uncontiuous tc */ 1566 for (i = 0; i < hdev->tm_info.num_tc; i++) 1567 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1568 1569 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1570 } 1571 1572 static int hclge_configure(struct hclge_dev *hdev) 1573 { 1574 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1575 struct hclge_cfg cfg; 1576 int ret; 1577 1578 ret = hclge_get_cfg(hdev, &cfg); 1579 if (ret) 1580 return ret; 1581 1582 hdev->base_tqp_pid = 0; 1583 hdev->vf_rss_size_max = cfg.vf_rss_size_max; 1584 hdev->pf_rss_size_max = cfg.pf_rss_size_max; 1585 hdev->rx_buf_len = cfg.rx_buf_len; 1586 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1587 hdev->hw.mac.media_type = cfg.media_type; 1588 hdev->hw.mac.phy_addr = cfg.phy_addr; 1589 hdev->num_tx_desc = cfg.tqp_desc_num; 1590 hdev->num_rx_desc = cfg.tqp_desc_num; 1591 hdev->tm_info.num_pg = 1; 1592 hdev->tc_max = cfg.tc_num; 1593 hdev->tm_info.hw_pfc_map = 0; 1594 if (cfg.umv_space) 1595 hdev->wanted_umv_size = cfg.umv_space; 1596 else 1597 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size; 1598 hdev->tx_spare_buf_size = cfg.tx_spare_buf_size; 1599 hdev->gro_en = true; 1600 if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF) 1601 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 1602 1603 if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 1604 hdev->fd_en = true; 1605 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 1606 } 1607 1608 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1609 if (ret) { 1610 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n", 1611 cfg.default_speed, ret); 1612 return ret; 1613 } 1614 1615 hclge_parse_link_mode(hdev, cfg.speed_ability); 1616 1617 hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability); 1618 1619 hclge_init_tc_config(hdev); 1620 hclge_init_kdump_kernel_config(hdev); 1621 1622 return ret; 1623 } 1624 1625 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min, 1626 u16 tso_mss_max) 1627 { 1628 struct hclge_cfg_tso_status_cmd *req; 1629 struct hclge_desc desc; 1630 1631 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1632 1633 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1634 req->tso_mss_min = cpu_to_le16(tso_mss_min); 1635 req->tso_mss_max = cpu_to_le16(tso_mss_max); 1636 1637 return hclge_cmd_send(&hdev->hw, &desc, 1); 1638 } 1639 1640 static int hclge_config_gro(struct hclge_dev *hdev) 1641 { 1642 struct hclge_cfg_gro_status_cmd *req; 1643 struct hclge_desc desc; 1644 int ret; 1645 1646 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 1647 return 0; 1648 1649 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false); 1650 req = (struct hclge_cfg_gro_status_cmd *)desc.data; 1651 1652 req->gro_en = hdev->gro_en ? 1 : 0; 1653 1654 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1655 if (ret) 1656 dev_err(&hdev->pdev->dev, 1657 "GRO hardware config cmd failed, ret = %d\n", ret); 1658 1659 return ret; 1660 } 1661 1662 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1663 { 1664 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1665 struct hclge_comm_tqp *tqp; 1666 int i; 1667 1668 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1669 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 1670 if (!hdev->htqp) 1671 return -ENOMEM; 1672 1673 tqp = hdev->htqp; 1674 1675 for (i = 0; i < hdev->num_tqps; i++) { 1676 tqp->dev = &hdev->pdev->dev; 1677 tqp->index = i; 1678 1679 tqp->q.ae_algo = &ae_algo; 1680 tqp->q.buf_size = hdev->rx_buf_len; 1681 tqp->q.tx_desc_num = hdev->num_tx_desc; 1682 tqp->q.rx_desc_num = hdev->num_rx_desc; 1683 1684 /* need an extended offset to configure queues >= 1685 * HCLGE_TQP_MAX_SIZE_DEV_V2 1686 */ 1687 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2) 1688 tqp->q.io_base = hdev->hw.hw.io_base + 1689 HCLGE_TQP_REG_OFFSET + 1690 i * HCLGE_TQP_REG_SIZE; 1691 else 1692 tqp->q.io_base = hdev->hw.hw.io_base + 1693 HCLGE_TQP_REG_OFFSET + 1694 HCLGE_TQP_EXT_REG_OFFSET + 1695 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) * 1696 HCLGE_TQP_REG_SIZE; 1697 1698 /* when device supports tx push and has device memory, 1699 * the queue can execute push mode or doorbell mode on 1700 * device memory. 1701 */ 1702 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 1703 tqp->q.mem_base = hdev->hw.hw.mem_base + 1704 HCLGE_TQP_MEM_OFFSET(hdev, i); 1705 1706 tqp++; 1707 } 1708 1709 return 0; 1710 } 1711 1712 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1713 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1714 { 1715 struct hclge_tqp_map_cmd *req; 1716 struct hclge_desc desc; 1717 int ret; 1718 1719 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1720 1721 req = (struct hclge_tqp_map_cmd *)desc.data; 1722 req->tqp_id = cpu_to_le16(tqp_pid); 1723 req->tqp_vf = func_id; 1724 req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B; 1725 if (!is_pf) 1726 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B; 1727 req->tqp_vid = cpu_to_le16(tqp_vid); 1728 1729 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1730 if (ret) 1731 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1732 1733 return ret; 1734 } 1735 1736 static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) 1737 { 1738 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1739 struct hclge_dev *hdev = vport->back; 1740 int i, alloced; 1741 1742 for (i = 0, alloced = 0; i < hdev->num_tqps && 1743 alloced < num_tqps; i++) { 1744 if (!hdev->htqp[i].alloced) { 1745 hdev->htqp[i].q.handle = &vport->nic; 1746 hdev->htqp[i].q.tqp_index = alloced; 1747 hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc; 1748 hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc; 1749 kinfo->tqp[alloced] = &hdev->htqp[i].q; 1750 hdev->htqp[i].alloced = true; 1751 alloced++; 1752 } 1753 } 1754 vport->alloc_tqps = alloced; 1755 kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max, 1756 vport->alloc_tqps / hdev->tm_info.num_tc); 1757 1758 /* ensure one to one mapping between irq and queue at default */ 1759 kinfo->rss_size = min_t(u16, kinfo->rss_size, 1760 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc); 1761 1762 return 0; 1763 } 1764 1765 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps, 1766 u16 num_tx_desc, u16 num_rx_desc) 1767 1768 { 1769 struct hnae3_handle *nic = &vport->nic; 1770 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1771 struct hclge_dev *hdev = vport->back; 1772 int ret; 1773 1774 kinfo->num_tx_desc = num_tx_desc; 1775 kinfo->num_rx_desc = num_rx_desc; 1776 1777 kinfo->rx_buf_len = hdev->rx_buf_len; 1778 kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size; 1779 1780 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps, 1781 sizeof(struct hnae3_queue *), GFP_KERNEL); 1782 if (!kinfo->tqp) 1783 return -ENOMEM; 1784 1785 ret = hclge_assign_tqp(vport, num_tqps); 1786 if (ret) 1787 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1788 1789 return ret; 1790 } 1791 1792 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1793 struct hclge_vport *vport) 1794 { 1795 struct hnae3_handle *nic = &vport->nic; 1796 struct hnae3_knic_private_info *kinfo; 1797 u16 i; 1798 1799 kinfo = &nic->kinfo; 1800 for (i = 0; i < vport->alloc_tqps; i++) { 1801 struct hclge_comm_tqp *q = 1802 container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); 1803 bool is_pf; 1804 int ret; 1805 1806 is_pf = !(vport->vport_id); 1807 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1808 i, is_pf); 1809 if (ret) 1810 return ret; 1811 } 1812 1813 return 0; 1814 } 1815 1816 static int hclge_map_tqp(struct hclge_dev *hdev) 1817 { 1818 struct hclge_vport *vport = hdev->vport; 1819 u16 i, num_vport; 1820 1821 num_vport = hdev->num_req_vfs + 1; 1822 for (i = 0; i < num_vport; i++) { 1823 int ret; 1824 1825 ret = hclge_map_tqp_to_vport(hdev, vport); 1826 if (ret) 1827 return ret; 1828 1829 vport++; 1830 } 1831 1832 return 0; 1833 } 1834 1835 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1836 { 1837 struct hnae3_handle *nic = &vport->nic; 1838 struct hclge_dev *hdev = vport->back; 1839 int ret; 1840 1841 nic->pdev = hdev->pdev; 1842 nic->ae_algo = &ae_algo; 1843 nic->numa_node_mask = hdev->numa_node_mask; 1844 nic->kinfo.io_base = hdev->hw.hw.io_base; 1845 1846 ret = hclge_knic_setup(vport, num_tqps, 1847 hdev->num_tx_desc, hdev->num_rx_desc); 1848 if (ret) 1849 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret); 1850 1851 return ret; 1852 } 1853 1854 static int hclge_alloc_vport(struct hclge_dev *hdev) 1855 { 1856 struct pci_dev *pdev = hdev->pdev; 1857 struct hclge_vport *vport; 1858 u32 tqp_main_vport; 1859 u32 tqp_per_vport; 1860 int num_vport, i; 1861 int ret; 1862 1863 /* We need to alloc a vport for main NIC of PF */ 1864 num_vport = hdev->num_req_vfs + 1; 1865 1866 if (hdev->num_tqps < num_vport) { 1867 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)", 1868 hdev->num_tqps, num_vport); 1869 return -EINVAL; 1870 } 1871 1872 /* Alloc the same number of TQPs for every vport */ 1873 tqp_per_vport = hdev->num_tqps / num_vport; 1874 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1875 1876 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1877 GFP_KERNEL); 1878 if (!vport) 1879 return -ENOMEM; 1880 1881 hdev->vport = vport; 1882 hdev->num_alloc_vport = num_vport; 1883 1884 if (IS_ENABLED(CONFIG_PCI_IOV)) 1885 hdev->num_alloc_vfs = hdev->num_req_vfs; 1886 1887 for (i = 0; i < num_vport; i++) { 1888 vport->back = hdev; 1889 vport->vport_id = i; 1890 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO; 1891 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 1892 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE; 1893 vport->port_base_vlan_cfg.tbl_sta = true; 1894 vport->rxvlan_cfg.rx_vlan_offload_en = true; 1895 vport->req_vlan_fltr_en = true; 1896 INIT_LIST_HEAD(&vport->vlan_list); 1897 INIT_LIST_HEAD(&vport->uc_mac_list); 1898 INIT_LIST_HEAD(&vport->mc_mac_list); 1899 spin_lock_init(&vport->mac_list_lock); 1900 1901 if (i == 0) 1902 ret = hclge_vport_setup(vport, tqp_main_vport); 1903 else 1904 ret = hclge_vport_setup(vport, tqp_per_vport); 1905 if (ret) { 1906 dev_err(&pdev->dev, 1907 "vport setup failed for vport %d, %d\n", 1908 i, ret); 1909 return ret; 1910 } 1911 1912 vport++; 1913 } 1914 1915 return 0; 1916 } 1917 1918 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1919 struct hclge_pkt_buf_alloc *buf_alloc) 1920 { 1921 /* TX buffer size is unit by 128 byte */ 1922 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1923 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1924 struct hclge_tx_buff_alloc_cmd *req; 1925 struct hclge_desc desc; 1926 int ret; 1927 u8 i; 1928 1929 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1930 1931 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1932 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1933 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1934 1935 req->tx_pkt_buff[i] = 1936 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1937 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1938 } 1939 1940 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1941 if (ret) 1942 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1943 ret); 1944 1945 return ret; 1946 } 1947 1948 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1949 struct hclge_pkt_buf_alloc *buf_alloc) 1950 { 1951 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1952 1953 if (ret) 1954 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1955 1956 return ret; 1957 } 1958 1959 static u32 hclge_get_tc_num(struct hclge_dev *hdev) 1960 { 1961 unsigned int i; 1962 u32 cnt = 0; 1963 1964 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1965 if (hdev->hw_tc_map & BIT(i)) 1966 cnt++; 1967 return cnt; 1968 } 1969 1970 /* Get the number of pfc enabled TCs, which have private buffer */ 1971 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1972 struct hclge_pkt_buf_alloc *buf_alloc) 1973 { 1974 struct hclge_priv_buf *priv; 1975 unsigned int i; 1976 int cnt = 0; 1977 1978 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1979 priv = &buf_alloc->priv_buf[i]; 1980 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1981 priv->enable) 1982 cnt++; 1983 } 1984 1985 return cnt; 1986 } 1987 1988 /* Get the number of pfc disabled TCs, which have private buffer */ 1989 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1990 struct hclge_pkt_buf_alloc *buf_alloc) 1991 { 1992 struct hclge_priv_buf *priv; 1993 unsigned int i; 1994 int cnt = 0; 1995 1996 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1997 priv = &buf_alloc->priv_buf[i]; 1998 if (hdev->hw_tc_map & BIT(i) && 1999 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 2000 priv->enable) 2001 cnt++; 2002 } 2003 2004 return cnt; 2005 } 2006 2007 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 2008 { 2009 struct hclge_priv_buf *priv; 2010 u32 rx_priv = 0; 2011 int i; 2012 2013 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2014 priv = &buf_alloc->priv_buf[i]; 2015 if (priv->enable) 2016 rx_priv += priv->buf_size; 2017 } 2018 return rx_priv; 2019 } 2020 2021 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 2022 { 2023 u32 i, total_tx_size = 0; 2024 2025 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 2026 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 2027 2028 return total_tx_size; 2029 } 2030 2031 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 2032 struct hclge_pkt_buf_alloc *buf_alloc, 2033 u32 rx_all) 2034 { 2035 u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 2036 u32 tc_num = hclge_get_tc_num(hdev); 2037 u32 shared_buf, aligned_mps; 2038 u32 rx_priv; 2039 int i; 2040 2041 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2042 2043 if (hnae3_dev_dcb_supported(hdev)) 2044 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps + 2045 hdev->dv_buf_size; 2046 else 2047 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF 2048 + hdev->dv_buf_size; 2049 2050 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 2051 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc), 2052 HCLGE_BUF_SIZE_UNIT); 2053 2054 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 2055 if (rx_all < rx_priv + shared_std) 2056 return false; 2057 2058 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT); 2059 buf_alloc->s_buf.buf_size = shared_buf; 2060 if (hnae3_dev_dcb_supported(hdev)) { 2061 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size; 2062 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 2063 - roundup(aligned_mps / HCLGE_BUF_DIV_BY, 2064 HCLGE_BUF_SIZE_UNIT); 2065 } else { 2066 buf_alloc->s_buf.self.high = aligned_mps + 2067 HCLGE_NON_DCB_ADDITIONAL_BUF; 2068 buf_alloc->s_buf.self.low = aligned_mps; 2069 } 2070 2071 if (hnae3_dev_dcb_supported(hdev)) { 2072 hi_thrd = shared_buf - hdev->dv_buf_size; 2073 2074 if (tc_num <= NEED_RESERVE_TC_NUM) 2075 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 2076 / BUF_MAX_PERCENT; 2077 2078 if (tc_num) 2079 hi_thrd = hi_thrd / tc_num; 2080 2081 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps); 2082 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT); 2083 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY; 2084 } else { 2085 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF; 2086 lo_thrd = aligned_mps; 2087 } 2088 2089 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2090 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 2091 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 2092 } 2093 2094 return true; 2095 } 2096 2097 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 2098 struct hclge_pkt_buf_alloc *buf_alloc) 2099 { 2100 u32 i, total_size; 2101 2102 total_size = hdev->pkt_buf_size; 2103 2104 /* alloc tx buffer for all enabled tc */ 2105 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2106 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2107 2108 if (hdev->hw_tc_map & BIT(i)) { 2109 if (total_size < hdev->tx_buf_size) 2110 return -ENOMEM; 2111 2112 priv->tx_buf_size = hdev->tx_buf_size; 2113 } else { 2114 priv->tx_buf_size = 0; 2115 } 2116 2117 total_size -= priv->tx_buf_size; 2118 } 2119 2120 return 0; 2121 } 2122 2123 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max, 2124 struct hclge_pkt_buf_alloc *buf_alloc) 2125 { 2126 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2127 u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2128 unsigned int i; 2129 2130 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2131 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2132 2133 priv->enable = 0; 2134 priv->wl.low = 0; 2135 priv->wl.high = 0; 2136 priv->buf_size = 0; 2137 2138 if (!(hdev->hw_tc_map & BIT(i))) 2139 continue; 2140 2141 priv->enable = 1; 2142 2143 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 2144 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT; 2145 priv->wl.high = roundup(priv->wl.low + aligned_mps, 2146 HCLGE_BUF_SIZE_UNIT); 2147 } else { 2148 priv->wl.low = 0; 2149 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) : 2150 aligned_mps; 2151 } 2152 2153 priv->buf_size = priv->wl.high + hdev->dv_buf_size; 2154 } 2155 2156 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2157 } 2158 2159 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev, 2160 struct hclge_pkt_buf_alloc *buf_alloc) 2161 { 2162 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2163 int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 2164 int i; 2165 2166 /* let the last to be cleared first */ 2167 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2168 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2169 unsigned int mask = BIT((unsigned int)i); 2170 2171 if (hdev->hw_tc_map & mask && 2172 !(hdev->tm_info.hw_pfc_map & mask)) { 2173 /* Clear the no pfc TC private buffer */ 2174 priv->wl.low = 0; 2175 priv->wl.high = 0; 2176 priv->buf_size = 0; 2177 priv->enable = 0; 2178 no_pfc_priv_num--; 2179 } 2180 2181 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2182 no_pfc_priv_num == 0) 2183 break; 2184 } 2185 2186 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2187 } 2188 2189 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev, 2190 struct hclge_pkt_buf_alloc *buf_alloc) 2191 { 2192 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2193 int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 2194 int i; 2195 2196 /* let the last to be cleared first */ 2197 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2198 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2199 unsigned int mask = BIT((unsigned int)i); 2200 2201 if (hdev->hw_tc_map & mask && 2202 hdev->tm_info.hw_pfc_map & mask) { 2203 /* Reduce the number of pfc TC with private buffer */ 2204 priv->wl.low = 0; 2205 priv->enable = 0; 2206 priv->wl.high = 0; 2207 priv->buf_size = 0; 2208 pfc_priv_num--; 2209 } 2210 2211 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2212 pfc_priv_num == 0) 2213 break; 2214 } 2215 2216 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2217 } 2218 2219 static int hclge_only_alloc_priv_buff(struct hclge_dev *hdev, 2220 struct hclge_pkt_buf_alloc *buf_alloc) 2221 { 2222 #define COMPENSATE_BUFFER 0x3C00 2223 #define COMPENSATE_HALF_MPS_NUM 5 2224 #define PRIV_WL_GAP 0x1800 2225 2226 u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2227 u32 tc_num = hclge_get_tc_num(hdev); 2228 u32 half_mps = hdev->mps >> 1; 2229 u32 min_rx_priv; 2230 unsigned int i; 2231 2232 if (tc_num) 2233 rx_priv = rx_priv / tc_num; 2234 2235 if (tc_num <= NEED_RESERVE_TC_NUM) 2236 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 2237 2238 min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER + 2239 COMPENSATE_HALF_MPS_NUM * half_mps; 2240 min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT); 2241 rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT); 2242 if (rx_priv < min_rx_priv) 2243 return false; 2244 2245 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2246 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2247 2248 priv->enable = 0; 2249 priv->wl.low = 0; 2250 priv->wl.high = 0; 2251 priv->buf_size = 0; 2252 2253 if (!(hdev->hw_tc_map & BIT(i))) 2254 continue; 2255 2256 priv->enable = 1; 2257 priv->buf_size = rx_priv; 2258 priv->wl.high = rx_priv - hdev->dv_buf_size; 2259 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 2260 } 2261 2262 buf_alloc->s_buf.buf_size = 0; 2263 2264 return true; 2265 } 2266 2267 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 2268 * @hdev: pointer to struct hclge_dev 2269 * @buf_alloc: pointer to buffer calculation data 2270 * @return: 0: calculate successful, negative: fail 2271 */ 2272 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 2273 struct hclge_pkt_buf_alloc *buf_alloc) 2274 { 2275 /* When DCB is not supported, rx private buffer is not allocated. */ 2276 if (!hnae3_dev_dcb_supported(hdev)) { 2277 u32 rx_all = hdev->pkt_buf_size; 2278 2279 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 2280 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 2281 return -ENOMEM; 2282 2283 return 0; 2284 } 2285 2286 if (hclge_only_alloc_priv_buff(hdev, buf_alloc)) 2287 return 0; 2288 2289 if (hclge_rx_buf_calc_all(hdev, true, buf_alloc)) 2290 return 0; 2291 2292 /* try to decrease the buffer size */ 2293 if (hclge_rx_buf_calc_all(hdev, false, buf_alloc)) 2294 return 0; 2295 2296 if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc)) 2297 return 0; 2298 2299 if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc)) 2300 return 0; 2301 2302 return -ENOMEM; 2303 } 2304 2305 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 2306 struct hclge_pkt_buf_alloc *buf_alloc) 2307 { 2308 struct hclge_rx_priv_buff_cmd *req; 2309 struct hclge_desc desc; 2310 int ret; 2311 int i; 2312 2313 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 2314 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 2315 2316 /* Alloc private buffer TCs */ 2317 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2318 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2319 2320 req->buf_num[i] = 2321 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 2322 req->buf_num[i] |= 2323 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 2324 } 2325 2326 req->shared_buf = 2327 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 2328 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 2329 2330 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2331 if (ret) 2332 dev_err(&hdev->pdev->dev, 2333 "rx private buffer alloc cmd failed %d\n", ret); 2334 2335 return ret; 2336 } 2337 2338 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 2339 struct hclge_pkt_buf_alloc *buf_alloc) 2340 { 2341 struct hclge_rx_priv_wl_buf *req; 2342 struct hclge_priv_buf *priv; 2343 struct hclge_desc desc[2]; 2344 int i, j; 2345 int ret; 2346 2347 for (i = 0; i < 2; i++) { 2348 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 2349 false); 2350 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 2351 2352 /* The first descriptor set the NEXT bit to 1 */ 2353 if (i == 0) 2354 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2355 else 2356 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2357 2358 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2359 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 2360 2361 priv = &buf_alloc->priv_buf[idx]; 2362 req->tc_wl[j].high = 2363 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 2364 req->tc_wl[j].high |= 2365 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2366 req->tc_wl[j].low = 2367 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 2368 req->tc_wl[j].low |= 2369 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2370 } 2371 } 2372 2373 /* Send 2 descriptor at one time */ 2374 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2375 if (ret) 2376 dev_err(&hdev->pdev->dev, 2377 "rx private waterline config cmd failed %d\n", 2378 ret); 2379 return ret; 2380 } 2381 2382 static int hclge_common_thrd_config(struct hclge_dev *hdev, 2383 struct hclge_pkt_buf_alloc *buf_alloc) 2384 { 2385 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 2386 struct hclge_rx_com_thrd *req; 2387 struct hclge_desc desc[2]; 2388 struct hclge_tc_thrd *tc; 2389 int i, j; 2390 int ret; 2391 2392 for (i = 0; i < 2; i++) { 2393 hclge_cmd_setup_basic_desc(&desc[i], 2394 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 2395 req = (struct hclge_rx_com_thrd *)&desc[i].data; 2396 2397 /* The first descriptor set the NEXT bit to 1 */ 2398 if (i == 0) 2399 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2400 else 2401 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2402 2403 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2404 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 2405 2406 req->com_thrd[j].high = 2407 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 2408 req->com_thrd[j].high |= 2409 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2410 req->com_thrd[j].low = 2411 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 2412 req->com_thrd[j].low |= 2413 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2414 } 2415 } 2416 2417 /* Send 2 descriptors at one time */ 2418 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2419 if (ret) 2420 dev_err(&hdev->pdev->dev, 2421 "common threshold config cmd failed %d\n", ret); 2422 return ret; 2423 } 2424 2425 static int hclge_common_wl_config(struct hclge_dev *hdev, 2426 struct hclge_pkt_buf_alloc *buf_alloc) 2427 { 2428 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 2429 struct hclge_rx_com_wl *req; 2430 struct hclge_desc desc; 2431 int ret; 2432 2433 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 2434 2435 req = (struct hclge_rx_com_wl *)desc.data; 2436 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 2437 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2438 2439 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 2440 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2441 2442 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2443 if (ret) 2444 dev_err(&hdev->pdev->dev, 2445 "common waterline config cmd failed %d\n", ret); 2446 2447 return ret; 2448 } 2449 2450 int hclge_buffer_alloc(struct hclge_dev *hdev) 2451 { 2452 struct hclge_pkt_buf_alloc *pkt_buf; 2453 int ret; 2454 2455 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); 2456 if (!pkt_buf) 2457 return -ENOMEM; 2458 2459 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 2460 if (ret) { 2461 dev_err(&hdev->pdev->dev, 2462 "could not calc tx buffer size for all TCs %d\n", ret); 2463 goto out; 2464 } 2465 2466 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 2467 if (ret) { 2468 dev_err(&hdev->pdev->dev, 2469 "could not alloc tx buffers %d\n", ret); 2470 goto out; 2471 } 2472 2473 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 2474 if (ret) { 2475 dev_err(&hdev->pdev->dev, 2476 "could not calc rx priv buffer size for all TCs %d\n", 2477 ret); 2478 goto out; 2479 } 2480 2481 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 2482 if (ret) { 2483 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 2484 ret); 2485 goto out; 2486 } 2487 2488 if (hnae3_dev_dcb_supported(hdev)) { 2489 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2490 if (ret) { 2491 dev_err(&hdev->pdev->dev, 2492 "could not configure rx private waterline %d\n", 2493 ret); 2494 goto out; 2495 } 2496 2497 ret = hclge_common_thrd_config(hdev, pkt_buf); 2498 if (ret) { 2499 dev_err(&hdev->pdev->dev, 2500 "could not configure common threshold %d\n", 2501 ret); 2502 goto out; 2503 } 2504 } 2505 2506 ret = hclge_common_wl_config(hdev, pkt_buf); 2507 if (ret) 2508 dev_err(&hdev->pdev->dev, 2509 "could not configure common waterline %d\n", ret); 2510 2511 out: 2512 kfree(pkt_buf); 2513 return ret; 2514 } 2515 2516 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2517 { 2518 struct hnae3_handle *roce = &vport->roce; 2519 struct hnae3_handle *nic = &vport->nic; 2520 struct hclge_dev *hdev = vport->back; 2521 2522 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2523 2524 if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi) 2525 return -EINVAL; 2526 2527 roce->rinfo.base_vector = hdev->num_nic_msi; 2528 2529 roce->rinfo.netdev = nic->kinfo.netdev; 2530 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2531 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2532 2533 roce->pdev = nic->pdev; 2534 roce->ae_algo = nic->ae_algo; 2535 roce->numa_node_mask = nic->numa_node_mask; 2536 2537 return 0; 2538 } 2539 2540 static int hclge_init_msi(struct hclge_dev *hdev) 2541 { 2542 struct pci_dev *pdev = hdev->pdev; 2543 int vectors; 2544 int i; 2545 2546 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2547 hdev->num_msi, 2548 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2549 if (vectors < 0) { 2550 dev_err(&pdev->dev, 2551 "failed(%d) to allocate MSI/MSI-X vectors\n", 2552 vectors); 2553 return vectors; 2554 } 2555 if (vectors < hdev->num_msi) 2556 dev_warn(&hdev->pdev->dev, 2557 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2558 hdev->num_msi, vectors); 2559 2560 hdev->num_msi = vectors; 2561 hdev->num_msi_left = vectors; 2562 2563 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2564 sizeof(u16), GFP_KERNEL); 2565 if (!hdev->vector_status) { 2566 pci_free_irq_vectors(pdev); 2567 return -ENOMEM; 2568 } 2569 2570 for (i = 0; i < hdev->num_msi; i++) 2571 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2572 2573 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2574 sizeof(int), GFP_KERNEL); 2575 if (!hdev->vector_irq) { 2576 pci_free_irq_vectors(pdev); 2577 return -ENOMEM; 2578 } 2579 2580 return 0; 2581 } 2582 2583 static u8 hclge_check_speed_dup(u8 duplex, int speed) 2584 { 2585 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 2586 duplex = HCLGE_MAC_FULL; 2587 2588 return duplex; 2589 } 2590 2591 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = { 2592 {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M}, 2593 {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M}, 2594 {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G}, 2595 {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G}, 2596 {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G}, 2597 {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G}, 2598 {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G}, 2599 {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G}, 2600 {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G}, 2601 }; 2602 2603 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw) 2604 { 2605 u16 i; 2606 2607 for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) { 2608 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) { 2609 *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw; 2610 return 0; 2611 } 2612 } 2613 2614 return -EINVAL; 2615 } 2616 2617 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 2618 u8 duplex, u8 lane_num) 2619 { 2620 struct hclge_config_mac_speed_dup_cmd *req; 2621 struct hclge_desc desc; 2622 u32 speed_fw; 2623 int ret; 2624 2625 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2626 2627 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2628 2629 if (duplex) 2630 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1); 2631 2632 ret = hclge_convert_to_fw_speed(speed, &speed_fw); 2633 if (ret) { 2634 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2635 return ret; 2636 } 2637 2638 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S, 2639 speed_fw); 2640 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2641 1); 2642 req->lane_num = lane_num; 2643 2644 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2645 if (ret) { 2646 dev_err(&hdev->pdev->dev, 2647 "mac speed/duplex config cmd failed %d.\n", ret); 2648 return ret; 2649 } 2650 2651 return 0; 2652 } 2653 2654 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num) 2655 { 2656 struct hclge_mac *mac = &hdev->hw.mac; 2657 int ret; 2658 2659 duplex = hclge_check_speed_dup(duplex, speed); 2660 if (!mac->support_autoneg && mac->speed == speed && 2661 mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0)) 2662 return 0; 2663 2664 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num); 2665 if (ret) 2666 return ret; 2667 2668 hdev->hw.mac.speed = speed; 2669 hdev->hw.mac.duplex = duplex; 2670 if (!lane_num) 2671 hdev->hw.mac.lane_num = lane_num; 2672 2673 return 0; 2674 } 2675 2676 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2677 u8 duplex, u8 lane_num) 2678 { 2679 struct hclge_vport *vport = hclge_get_vport(handle); 2680 struct hclge_dev *hdev = vport->back; 2681 2682 return hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num); 2683 } 2684 2685 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2686 { 2687 struct hclge_config_auto_neg_cmd *req; 2688 struct hclge_desc desc; 2689 u32 flag = 0; 2690 int ret; 2691 2692 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2693 2694 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2695 if (enable) 2696 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U); 2697 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2698 2699 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2700 if (ret) 2701 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2702 ret); 2703 2704 return ret; 2705 } 2706 2707 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2708 { 2709 struct hclge_vport *vport = hclge_get_vport(handle); 2710 struct hclge_dev *hdev = vport->back; 2711 2712 if (!hdev->hw.mac.support_autoneg) { 2713 if (enable) { 2714 dev_err(&hdev->pdev->dev, 2715 "autoneg is not supported by current port\n"); 2716 return -EOPNOTSUPP; 2717 } else { 2718 return 0; 2719 } 2720 } 2721 2722 return hclge_set_autoneg_en(hdev, enable); 2723 } 2724 2725 static int hclge_get_autoneg(struct hnae3_handle *handle) 2726 { 2727 struct hclge_vport *vport = hclge_get_vport(handle); 2728 struct hclge_dev *hdev = vport->back; 2729 struct phy_device *phydev = hdev->hw.mac.phydev; 2730 2731 if (phydev) 2732 return phydev->autoneg; 2733 2734 return hdev->hw.mac.autoneg; 2735 } 2736 2737 static int hclge_restart_autoneg(struct hnae3_handle *handle) 2738 { 2739 struct hclge_vport *vport = hclge_get_vport(handle); 2740 struct hclge_dev *hdev = vport->back; 2741 int ret; 2742 2743 dev_dbg(&hdev->pdev->dev, "restart autoneg\n"); 2744 2745 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2746 if (ret) 2747 return ret; 2748 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2749 } 2750 2751 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt) 2752 { 2753 struct hclge_vport *vport = hclge_get_vport(handle); 2754 struct hclge_dev *hdev = vport->back; 2755 2756 if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) 2757 return hclge_set_autoneg_en(hdev, !halt); 2758 2759 return 0; 2760 } 2761 2762 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev, 2763 struct hclge_desc *desc, u32 desc_len) 2764 { 2765 u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2; 2766 u32 desc_index = 0; 2767 u32 data_index = 0; 2768 u32 i; 2769 2770 for (i = 0; i < lane_size; i++) { 2771 if (data_index >= HCLGE_DESC_DATA_LEN) { 2772 desc_index++; 2773 data_index = 0; 2774 } 2775 2776 if (desc_index >= desc_len) 2777 return; 2778 2779 hdev->fec_stats.per_lanes[i] += 2780 le32_to_cpu(desc[desc_index].data[data_index]); 2781 data_index++; 2782 } 2783 } 2784 2785 static void hclge_parse_fec_stats(struct hclge_dev *hdev, 2786 struct hclge_desc *desc, u32 desc_len) 2787 { 2788 struct hclge_query_fec_stats_cmd *req; 2789 2790 req = (struct hclge_query_fec_stats_cmd *)desc[0].data; 2791 2792 hdev->fec_stats.base_r_lane_num = req->base_r_lane_num; 2793 hdev->fec_stats.rs_corr_blocks += 2794 le32_to_cpu(req->rs_fec_corr_blocks); 2795 hdev->fec_stats.rs_uncorr_blocks += 2796 le32_to_cpu(req->rs_fec_uncorr_blocks); 2797 hdev->fec_stats.rs_error_blocks += 2798 le32_to_cpu(req->rs_fec_error_blocks); 2799 hdev->fec_stats.base_r_corr_blocks += 2800 le32_to_cpu(req->base_r_fec_corr_blocks); 2801 hdev->fec_stats.base_r_uncorr_blocks += 2802 le32_to_cpu(req->base_r_fec_uncorr_blocks); 2803 2804 hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1); 2805 } 2806 2807 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev) 2808 { 2809 struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM]; 2810 int ret; 2811 u32 i; 2812 2813 for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) { 2814 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS, 2815 true); 2816 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1)) 2817 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2818 } 2819 2820 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM); 2821 if (ret) 2822 return ret; 2823 2824 hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM); 2825 2826 return 0; 2827 } 2828 2829 static void hclge_update_fec_stats(struct hclge_dev *hdev) 2830 { 2831 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2832 int ret; 2833 2834 if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || 2835 test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state)) 2836 return; 2837 2838 ret = hclge_update_fec_stats_hw(hdev); 2839 if (ret) 2840 dev_err(&hdev->pdev->dev, 2841 "failed to update fec stats, ret = %d\n", ret); 2842 2843 clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state); 2844 } 2845 2846 static void hclge_get_fec_stats_total(struct hclge_dev *hdev, 2847 struct ethtool_fec_stats *fec_stats) 2848 { 2849 fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks; 2850 fec_stats->uncorrectable_blocks.total = 2851 hdev->fec_stats.rs_uncorr_blocks; 2852 } 2853 2854 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev, 2855 struct ethtool_fec_stats *fec_stats) 2856 { 2857 u32 i; 2858 2859 if (hdev->fec_stats.base_r_lane_num == 0 || 2860 hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) { 2861 dev_err(&hdev->pdev->dev, 2862 "fec stats lane number(%llu) is invalid\n", 2863 hdev->fec_stats.base_r_lane_num); 2864 return; 2865 } 2866 2867 for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) { 2868 fec_stats->corrected_blocks.lanes[i] = 2869 hdev->fec_stats.base_r_corr_per_lanes[i]; 2870 fec_stats->uncorrectable_blocks.lanes[i] = 2871 hdev->fec_stats.base_r_uncorr_per_lanes[i]; 2872 } 2873 } 2874 2875 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev, 2876 struct ethtool_fec_stats *fec_stats) 2877 { 2878 u32 fec_mode = hdev->hw.mac.fec_mode; 2879 2880 switch (fec_mode) { 2881 case BIT(HNAE3_FEC_RS): 2882 case BIT(HNAE3_FEC_LLRS): 2883 hclge_get_fec_stats_total(hdev, fec_stats); 2884 break; 2885 case BIT(HNAE3_FEC_BASER): 2886 hclge_get_fec_stats_lanes(hdev, fec_stats); 2887 break; 2888 default: 2889 dev_err(&hdev->pdev->dev, 2890 "fec stats is not supported by current fec mode(0x%x)\n", 2891 fec_mode); 2892 break; 2893 } 2894 } 2895 2896 static void hclge_get_fec_stats(struct hnae3_handle *handle, 2897 struct ethtool_fec_stats *fec_stats) 2898 { 2899 struct hclge_vport *vport = hclge_get_vport(handle); 2900 struct hclge_dev *hdev = vport->back; 2901 u32 fec_mode = hdev->hw.mac.fec_mode; 2902 2903 if (fec_mode == BIT(HNAE3_FEC_NONE) || 2904 fec_mode == BIT(HNAE3_FEC_AUTO) || 2905 fec_mode == BIT(HNAE3_FEC_USER_DEF)) 2906 return; 2907 2908 hclge_update_fec_stats(hdev); 2909 2910 hclge_comm_get_fec_stats(hdev, fec_stats); 2911 } 2912 2913 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode) 2914 { 2915 struct hclge_config_fec_cmd *req; 2916 struct hclge_desc desc; 2917 int ret; 2918 2919 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false); 2920 2921 req = (struct hclge_config_fec_cmd *)desc.data; 2922 if (fec_mode & BIT(HNAE3_FEC_AUTO)) 2923 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1); 2924 if (fec_mode & BIT(HNAE3_FEC_RS)) 2925 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2926 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS); 2927 if (fec_mode & BIT(HNAE3_FEC_LLRS)) 2928 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2929 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS); 2930 if (fec_mode & BIT(HNAE3_FEC_BASER)) 2931 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2932 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER); 2933 2934 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2935 if (ret) 2936 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret); 2937 2938 return ret; 2939 } 2940 2941 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode) 2942 { 2943 struct hclge_vport *vport = hclge_get_vport(handle); 2944 struct hclge_dev *hdev = vport->back; 2945 struct hclge_mac *mac = &hdev->hw.mac; 2946 int ret; 2947 2948 if (fec_mode && !(mac->fec_ability & fec_mode)) { 2949 dev_err(&hdev->pdev->dev, "unsupported fec mode\n"); 2950 return -EINVAL; 2951 } 2952 2953 ret = hclge_set_fec_hw(hdev, fec_mode); 2954 if (ret) 2955 return ret; 2956 2957 mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF); 2958 return 0; 2959 } 2960 2961 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability, 2962 u8 *fec_mode) 2963 { 2964 struct hclge_vport *vport = hclge_get_vport(handle); 2965 struct hclge_dev *hdev = vport->back; 2966 struct hclge_mac *mac = &hdev->hw.mac; 2967 2968 if (fec_ability) 2969 *fec_ability = mac->fec_ability; 2970 if (fec_mode) 2971 *fec_mode = mac->fec_mode; 2972 } 2973 2974 static int hclge_mac_init(struct hclge_dev *hdev) 2975 { 2976 struct hclge_mac *mac = &hdev->hw.mac; 2977 int ret; 2978 2979 hdev->support_sfp_query = true; 2980 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 2981 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed, 2982 hdev->hw.mac.duplex, hdev->hw.mac.lane_num); 2983 if (ret) 2984 return ret; 2985 2986 if (hdev->hw.mac.support_autoneg) { 2987 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg); 2988 if (ret) 2989 return ret; 2990 } 2991 2992 mac->link = 0; 2993 2994 if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { 2995 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode); 2996 if (ret) 2997 return ret; 2998 } 2999 3000 ret = hclge_set_mac_mtu(hdev, hdev->mps); 3001 if (ret) { 3002 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret); 3003 return ret; 3004 } 3005 3006 ret = hclge_set_default_loopback(hdev); 3007 if (ret) 3008 return ret; 3009 3010 ret = hclge_buffer_alloc(hdev); 3011 if (ret) 3012 dev_err(&hdev->pdev->dev, 3013 "allocate buffer fail, ret=%d\n", ret); 3014 3015 return ret; 3016 } 3017 3018 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 3019 { 3020 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3021 !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) { 3022 hdev->last_mbx_scheduled = jiffies; 3023 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3024 } 3025 } 3026 3027 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 3028 { 3029 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3030 test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) && 3031 !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) { 3032 hdev->last_rst_scheduled = jiffies; 3033 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3034 } 3035 } 3036 3037 static void hclge_errhand_task_schedule(struct hclge_dev *hdev) 3038 { 3039 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3040 !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 3041 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 3042 } 3043 3044 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time) 3045 { 3046 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 3047 !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 3048 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time); 3049 } 3050 3051 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status) 3052 { 3053 struct hclge_link_status_cmd *req; 3054 struct hclge_desc desc; 3055 int ret; 3056 3057 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 3058 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3059 if (ret) { 3060 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 3061 ret); 3062 return ret; 3063 } 3064 3065 req = (struct hclge_link_status_cmd *)desc.data; 3066 *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ? 3067 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 3068 3069 return 0; 3070 } 3071 3072 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status) 3073 { 3074 struct phy_device *phydev = hdev->hw.mac.phydev; 3075 3076 *link_status = HCLGE_LINK_STATUS_DOWN; 3077 3078 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) 3079 return 0; 3080 3081 if (phydev && (phydev->state != PHY_RUNNING || !phydev->link)) 3082 return 0; 3083 3084 return hclge_get_mac_link_status(hdev, link_status); 3085 } 3086 3087 static void hclge_push_link_status(struct hclge_dev *hdev) 3088 { 3089 struct hclge_vport *vport; 3090 int ret; 3091 u16 i; 3092 3093 for (i = 0; i < pci_num_vf(hdev->pdev); i++) { 3094 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 3095 3096 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) || 3097 vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO) 3098 continue; 3099 3100 ret = hclge_push_vf_link_status(vport); 3101 if (ret) { 3102 dev_err(&hdev->pdev->dev, 3103 "failed to push link status to vf%u, ret = %d\n", 3104 i, ret); 3105 } 3106 } 3107 } 3108 3109 static void hclge_update_link_status(struct hclge_dev *hdev) 3110 { 3111 struct hnae3_handle *rhandle = &hdev->vport[0].roce; 3112 struct hnae3_handle *handle = &hdev->vport[0].nic; 3113 struct hnae3_client *rclient = hdev->roce_client; 3114 struct hnae3_client *client = hdev->nic_client; 3115 int state; 3116 int ret; 3117 3118 if (!client) 3119 return; 3120 3121 if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state)) 3122 return; 3123 3124 ret = hclge_get_mac_phy_link(hdev, &state); 3125 if (ret) { 3126 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3127 return; 3128 } 3129 3130 if (state != hdev->hw.mac.link) { 3131 hdev->hw.mac.link = state; 3132 client->ops->link_status_change(handle, state); 3133 hclge_config_mac_tnl_int(hdev, state); 3134 if (rclient && rclient->ops->link_status_change) 3135 rclient->ops->link_status_change(rhandle, state); 3136 3137 hclge_push_link_status(hdev); 3138 } 3139 3140 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3141 } 3142 3143 static void hclge_update_speed_advertising(struct hclge_mac *mac) 3144 { 3145 u32 speed_ability; 3146 3147 if (hclge_get_speed_bit(mac->speed, &speed_ability)) 3148 return; 3149 3150 switch (mac->module_type) { 3151 case HNAE3_MODULE_TYPE_FIBRE_LR: 3152 hclge_convert_setting_lr(speed_ability, mac->advertising); 3153 break; 3154 case HNAE3_MODULE_TYPE_FIBRE_SR: 3155 case HNAE3_MODULE_TYPE_AOC: 3156 hclge_convert_setting_sr(speed_ability, mac->advertising); 3157 break; 3158 case HNAE3_MODULE_TYPE_CR: 3159 hclge_convert_setting_cr(speed_ability, mac->advertising); 3160 break; 3161 case HNAE3_MODULE_TYPE_KR: 3162 hclge_convert_setting_kr(speed_ability, mac->advertising); 3163 break; 3164 default: 3165 break; 3166 } 3167 } 3168 3169 static void hclge_update_fec_advertising(struct hclge_mac *mac) 3170 { 3171 if (mac->fec_mode & BIT(HNAE3_FEC_RS)) 3172 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 3173 mac->advertising); 3174 else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS)) 3175 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 3176 mac->advertising); 3177 else if (mac->fec_mode & BIT(HNAE3_FEC_BASER)) 3178 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 3179 mac->advertising); 3180 else 3181 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 3182 mac->advertising); 3183 } 3184 3185 static void hclge_update_pause_advertising(struct hclge_dev *hdev) 3186 { 3187 struct hclge_mac *mac = &hdev->hw.mac; 3188 bool rx_en, tx_en; 3189 3190 switch (hdev->fc_mode_last_time) { 3191 case HCLGE_FC_RX_PAUSE: 3192 rx_en = true; 3193 tx_en = false; 3194 break; 3195 case HCLGE_FC_TX_PAUSE: 3196 rx_en = false; 3197 tx_en = true; 3198 break; 3199 case HCLGE_FC_FULL: 3200 rx_en = true; 3201 tx_en = true; 3202 break; 3203 default: 3204 rx_en = false; 3205 tx_en = false; 3206 break; 3207 } 3208 3209 linkmode_set_pause(mac->advertising, tx_en, rx_en); 3210 } 3211 3212 static void hclge_update_advertising(struct hclge_dev *hdev) 3213 { 3214 struct hclge_mac *mac = &hdev->hw.mac; 3215 3216 linkmode_zero(mac->advertising); 3217 hclge_update_speed_advertising(mac); 3218 hclge_update_fec_advertising(mac); 3219 hclge_update_pause_advertising(hdev); 3220 } 3221 3222 static void hclge_update_port_capability(struct hclge_dev *hdev, 3223 struct hclge_mac *mac) 3224 { 3225 if (hnae3_dev_fec_supported(hdev)) 3226 hclge_convert_setting_fec(mac); 3227 3228 /* firmware can not identify back plane type, the media type 3229 * read from configuration can help deal it 3230 */ 3231 if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE && 3232 mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN) 3233 mac->module_type = HNAE3_MODULE_TYPE_KR; 3234 else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3235 mac->module_type = HNAE3_MODULE_TYPE_TP; 3236 3237 if (mac->support_autoneg) { 3238 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported); 3239 linkmode_copy(mac->advertising, mac->supported); 3240 } else { 3241 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3242 mac->supported); 3243 hclge_update_advertising(hdev); 3244 } 3245 } 3246 3247 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed) 3248 { 3249 struct hclge_sfp_info_cmd *resp; 3250 struct hclge_desc desc; 3251 int ret; 3252 3253 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3254 resp = (struct hclge_sfp_info_cmd *)desc.data; 3255 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3256 if (ret == -EOPNOTSUPP) { 3257 dev_warn(&hdev->pdev->dev, 3258 "IMP do not support get SFP speed %d\n", ret); 3259 return ret; 3260 } else if (ret) { 3261 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret); 3262 return ret; 3263 } 3264 3265 *speed = le32_to_cpu(resp->speed); 3266 3267 return 0; 3268 } 3269 3270 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac) 3271 { 3272 struct hclge_sfp_info_cmd *resp; 3273 struct hclge_desc desc; 3274 int ret; 3275 3276 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3277 resp = (struct hclge_sfp_info_cmd *)desc.data; 3278 3279 resp->query_type = QUERY_ACTIVE_SPEED; 3280 3281 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3282 if (ret == -EOPNOTSUPP) { 3283 dev_warn(&hdev->pdev->dev, 3284 "IMP does not support get SFP info %d\n", ret); 3285 return ret; 3286 } else if (ret) { 3287 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret); 3288 return ret; 3289 } 3290 3291 /* In some case, mac speed get from IMP may be 0, it shouldn't be 3292 * set to mac->speed. 3293 */ 3294 if (!le32_to_cpu(resp->speed)) 3295 return 0; 3296 3297 mac->speed = le32_to_cpu(resp->speed); 3298 /* if resp->speed_ability is 0, it means it's an old version 3299 * firmware, do not update these params 3300 */ 3301 if (resp->speed_ability) { 3302 mac->module_type = le32_to_cpu(resp->module_type); 3303 mac->speed_ability = le32_to_cpu(resp->speed_ability); 3304 mac->autoneg = resp->autoneg; 3305 mac->support_autoneg = resp->autoneg_ability; 3306 mac->speed_type = QUERY_ACTIVE_SPEED; 3307 mac->lane_num = resp->lane_num; 3308 if (!resp->active_fec) 3309 mac->fec_mode = 0; 3310 else 3311 mac->fec_mode = BIT(resp->active_fec); 3312 mac->fec_ability = resp->fec_ability; 3313 } else { 3314 mac->speed_type = QUERY_SFP_SPEED; 3315 } 3316 3317 return 0; 3318 } 3319 3320 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle, 3321 struct ethtool_link_ksettings *cmd) 3322 { 3323 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3324 struct hclge_vport *vport = hclge_get_vport(handle); 3325 struct hclge_phy_link_ksetting_0_cmd *req0; 3326 struct hclge_phy_link_ksetting_1_cmd *req1; 3327 u32 supported, advertising, lp_advertising; 3328 struct hclge_dev *hdev = vport->back; 3329 int ret; 3330 3331 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3332 true); 3333 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3334 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3335 true); 3336 3337 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3338 if (ret) { 3339 dev_err(&hdev->pdev->dev, 3340 "failed to get phy link ksetting, ret = %d.\n", ret); 3341 return ret; 3342 } 3343 3344 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3345 cmd->base.autoneg = req0->autoneg; 3346 cmd->base.speed = le32_to_cpu(req0->speed); 3347 cmd->base.duplex = req0->duplex; 3348 cmd->base.port = req0->port; 3349 cmd->base.transceiver = req0->transceiver; 3350 cmd->base.phy_address = req0->phy_address; 3351 cmd->base.eth_tp_mdix = req0->eth_tp_mdix; 3352 cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl; 3353 supported = le32_to_cpu(req0->supported); 3354 advertising = le32_to_cpu(req0->advertising); 3355 lp_advertising = le32_to_cpu(req0->lp_advertising); 3356 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3357 supported); 3358 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3359 advertising); 3360 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 3361 lp_advertising); 3362 3363 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3364 cmd->base.master_slave_cfg = req1->master_slave_cfg; 3365 cmd->base.master_slave_state = req1->master_slave_state; 3366 3367 return 0; 3368 } 3369 3370 static int 3371 hclge_set_phy_link_ksettings(struct hnae3_handle *handle, 3372 const struct ethtool_link_ksettings *cmd) 3373 { 3374 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3375 struct hclge_vport *vport = hclge_get_vport(handle); 3376 struct hclge_phy_link_ksetting_0_cmd *req0; 3377 struct hclge_phy_link_ksetting_1_cmd *req1; 3378 struct hclge_dev *hdev = vport->back; 3379 u32 advertising; 3380 int ret; 3381 3382 if (cmd->base.autoneg == AUTONEG_DISABLE && 3383 ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) || 3384 (cmd->base.duplex != DUPLEX_HALF && 3385 cmd->base.duplex != DUPLEX_FULL))) 3386 return -EINVAL; 3387 3388 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3389 false); 3390 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3391 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3392 false); 3393 3394 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3395 req0->autoneg = cmd->base.autoneg; 3396 req0->speed = cpu_to_le32(cmd->base.speed); 3397 req0->duplex = cmd->base.duplex; 3398 ethtool_convert_link_mode_to_legacy_u32(&advertising, 3399 cmd->link_modes.advertising); 3400 req0->advertising = cpu_to_le32(advertising); 3401 req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; 3402 3403 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3404 req1->master_slave_cfg = cmd->base.master_slave_cfg; 3405 3406 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3407 if (ret) { 3408 dev_err(&hdev->pdev->dev, 3409 "failed to set phy link ksettings, ret = %d.\n", ret); 3410 return ret; 3411 } 3412 3413 hdev->hw.mac.autoneg = cmd->base.autoneg; 3414 hdev->hw.mac.speed = cmd->base.speed; 3415 hdev->hw.mac.duplex = cmd->base.duplex; 3416 linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising); 3417 3418 return 0; 3419 } 3420 3421 static int hclge_update_tp_port_info(struct hclge_dev *hdev) 3422 { 3423 struct ethtool_link_ksettings cmd; 3424 int ret; 3425 3426 if (!hnae3_dev_phy_imp_supported(hdev)) 3427 return 0; 3428 3429 ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd); 3430 if (ret) 3431 return ret; 3432 3433 hdev->hw.mac.autoneg = cmd.base.autoneg; 3434 hdev->hw.mac.speed = cmd.base.speed; 3435 hdev->hw.mac.duplex = cmd.base.duplex; 3436 3437 return 0; 3438 } 3439 3440 static int hclge_tp_port_init(struct hclge_dev *hdev) 3441 { 3442 struct ethtool_link_ksettings cmd; 3443 3444 if (!hnae3_dev_phy_imp_supported(hdev)) 3445 return 0; 3446 3447 cmd.base.autoneg = hdev->hw.mac.autoneg; 3448 cmd.base.speed = hdev->hw.mac.speed; 3449 cmd.base.duplex = hdev->hw.mac.duplex; 3450 linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising); 3451 3452 return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd); 3453 } 3454 3455 static int hclge_update_port_info(struct hclge_dev *hdev) 3456 { 3457 struct hclge_mac *mac = &hdev->hw.mac; 3458 int speed; 3459 int ret; 3460 3461 /* get the port info from SFP cmd if not copper port */ 3462 if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3463 return hclge_update_tp_port_info(hdev); 3464 3465 /* if IMP does not support get SFP/qSFP info, return directly */ 3466 if (!hdev->support_sfp_query) 3467 return 0; 3468 3469 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3470 speed = mac->speed; 3471 ret = hclge_get_sfp_info(hdev, mac); 3472 } else { 3473 speed = HCLGE_MAC_SPEED_UNKNOWN; 3474 ret = hclge_get_sfp_speed(hdev, &speed); 3475 } 3476 3477 if (ret == -EOPNOTSUPP) { 3478 hdev->support_sfp_query = false; 3479 return ret; 3480 } else if (ret) { 3481 return ret; 3482 } 3483 3484 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3485 if (mac->speed_type == QUERY_ACTIVE_SPEED) { 3486 hclge_update_port_capability(hdev, mac); 3487 if (mac->speed != speed) 3488 (void)hclge_tm_port_shaper_cfg(hdev); 3489 return 0; 3490 } 3491 return hclge_cfg_mac_speed_dup(hdev, mac->speed, 3492 HCLGE_MAC_FULL, mac->lane_num); 3493 } else { 3494 if (speed == HCLGE_MAC_SPEED_UNKNOWN) 3495 return 0; /* do nothing if no SFP */ 3496 3497 /* must config full duplex for SFP */ 3498 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0); 3499 } 3500 } 3501 3502 static int hclge_get_status(struct hnae3_handle *handle) 3503 { 3504 struct hclge_vport *vport = hclge_get_vport(handle); 3505 struct hclge_dev *hdev = vport->back; 3506 3507 hclge_update_link_status(hdev); 3508 3509 return hdev->hw.mac.link; 3510 } 3511 3512 static struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf) 3513 { 3514 if (!pci_num_vf(hdev->pdev)) { 3515 dev_err(&hdev->pdev->dev, 3516 "SRIOV is disabled, can not get vport(%d) info.\n", vf); 3517 return NULL; 3518 } 3519 3520 if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) { 3521 dev_err(&hdev->pdev->dev, 3522 "vf id(%d) is out of range(0 <= vfid < %d)\n", 3523 vf, pci_num_vf(hdev->pdev)); 3524 return NULL; 3525 } 3526 3527 /* VF start from 1 in vport */ 3528 vf += HCLGE_VF_VPORT_START_NUM; 3529 return &hdev->vport[vf]; 3530 } 3531 3532 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf, 3533 struct ifla_vf_info *ivf) 3534 { 3535 struct hclge_vport *vport = hclge_get_vport(handle); 3536 struct hclge_dev *hdev = vport->back; 3537 3538 vport = hclge_get_vf_vport(hdev, vf); 3539 if (!vport) 3540 return -EINVAL; 3541 3542 ivf->vf = vf; 3543 ivf->linkstate = vport->vf_info.link_state; 3544 ivf->spoofchk = vport->vf_info.spoofchk; 3545 ivf->trusted = vport->vf_info.trusted; 3546 ivf->min_tx_rate = 0; 3547 ivf->max_tx_rate = vport->vf_info.max_tx_rate; 3548 ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag; 3549 ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto); 3550 ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos; 3551 ether_addr_copy(ivf->mac, vport->vf_info.mac); 3552 3553 return 0; 3554 } 3555 3556 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, 3557 int link_state) 3558 { 3559 struct hclge_vport *vport = hclge_get_vport(handle); 3560 struct hclge_dev *hdev = vport->back; 3561 int link_state_old; 3562 int ret; 3563 3564 vport = hclge_get_vf_vport(hdev, vf); 3565 if (!vport) 3566 return -EINVAL; 3567 3568 link_state_old = vport->vf_info.link_state; 3569 vport->vf_info.link_state = link_state; 3570 3571 /* return success directly if the VF is unalive, VF will 3572 * query link state itself when it starts work. 3573 */ 3574 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3575 return 0; 3576 3577 ret = hclge_push_vf_link_status(vport); 3578 if (ret) { 3579 vport->vf_info.link_state = link_state_old; 3580 dev_err(&hdev->pdev->dev, 3581 "failed to push vf%d link status, ret = %d\n", vf, ret); 3582 } 3583 3584 return ret; 3585 } 3586 3587 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 3588 { 3589 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; 3590 3591 /* fetch the events from their corresponding regs */ 3592 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 3593 msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 3594 hw_err_src_reg = hclge_read_dev(&hdev->hw, 3595 HCLGE_RAS_PF_OTHER_INT_STS_REG); 3596 3597 /* Assumption: If by any chance reset and mailbox events are reported 3598 * together then we will only process reset event in this go and will 3599 * defer the processing of the mailbox events. Since, we would have not 3600 * cleared RX CMDQ event this time we would receive again another 3601 * interrupt from H/W just for the mailbox. 3602 * 3603 * check for vector0 reset event sources 3604 */ 3605 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { 3606 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); 3607 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); 3608 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3609 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3610 hdev->rst_stats.imp_rst_cnt++; 3611 return HCLGE_VECTOR0_EVENT_RST; 3612 } 3613 3614 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { 3615 dev_info(&hdev->pdev->dev, "global reset interrupt\n"); 3616 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3617 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); 3618 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3619 hdev->rst_stats.global_rst_cnt++; 3620 return HCLGE_VECTOR0_EVENT_RST; 3621 } 3622 3623 /* check for vector0 msix event and hardware error event source */ 3624 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK || 3625 hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK) 3626 return HCLGE_VECTOR0_EVENT_ERR; 3627 3628 /* check for vector0 ptp event source */ 3629 if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) { 3630 *clearval = msix_src_reg; 3631 return HCLGE_VECTOR0_EVENT_PTP; 3632 } 3633 3634 /* check for vector0 mailbox(=CMDQ RX) event source */ 3635 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 3636 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 3637 *clearval = cmdq_src_reg; 3638 return HCLGE_VECTOR0_EVENT_MBX; 3639 } 3640 3641 /* print other vector0 event source */ 3642 dev_info(&hdev->pdev->dev, 3643 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n", 3644 cmdq_src_reg, hw_err_src_reg, msix_src_reg); 3645 3646 return HCLGE_VECTOR0_EVENT_OTHER; 3647 } 3648 3649 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 3650 u32 regclr) 3651 { 3652 switch (event_type) { 3653 case HCLGE_VECTOR0_EVENT_PTP: 3654 case HCLGE_VECTOR0_EVENT_RST: 3655 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 3656 break; 3657 case HCLGE_VECTOR0_EVENT_MBX: 3658 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 3659 break; 3660 default: 3661 break; 3662 } 3663 } 3664 3665 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 3666 { 3667 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 3668 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 3669 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 3670 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 3671 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 3672 } 3673 3674 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 3675 { 3676 writel(enable ? 1 : 0, vector->addr); 3677 } 3678 3679 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 3680 { 3681 struct hclge_dev *hdev = data; 3682 unsigned long flags; 3683 u32 clearval = 0; 3684 u32 event_cause; 3685 3686 hclge_enable_vector(&hdev->misc_vector, false); 3687 event_cause = hclge_check_event_cause(hdev, &clearval); 3688 3689 /* vector 0 interrupt is shared with reset and mailbox source events. */ 3690 switch (event_cause) { 3691 case HCLGE_VECTOR0_EVENT_ERR: 3692 hclge_errhand_task_schedule(hdev); 3693 break; 3694 case HCLGE_VECTOR0_EVENT_RST: 3695 hclge_reset_task_schedule(hdev); 3696 break; 3697 case HCLGE_VECTOR0_EVENT_PTP: 3698 spin_lock_irqsave(&hdev->ptp->lock, flags); 3699 hclge_ptp_clean_tx_hwts(hdev); 3700 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 3701 break; 3702 case HCLGE_VECTOR0_EVENT_MBX: 3703 /* If we are here then, 3704 * 1. Either we are not handling any mbx task and we are not 3705 * scheduled as well 3706 * OR 3707 * 2. We could be handling a mbx task but nothing more is 3708 * scheduled. 3709 * In both cases, we should schedule mbx task as there are more 3710 * mbx messages reported by this interrupt. 3711 */ 3712 hclge_mbx_task_schedule(hdev); 3713 break; 3714 default: 3715 dev_warn(&hdev->pdev->dev, 3716 "received unknown or unhandled event of vector0\n"); 3717 break; 3718 } 3719 3720 hclge_clear_event_cause(hdev, event_cause, clearval); 3721 3722 /* Enable interrupt if it is not caused by reset event or error event */ 3723 if (event_cause == HCLGE_VECTOR0_EVENT_PTP || 3724 event_cause == HCLGE_VECTOR0_EVENT_MBX || 3725 event_cause == HCLGE_VECTOR0_EVENT_OTHER) 3726 hclge_enable_vector(&hdev->misc_vector, true); 3727 3728 return IRQ_HANDLED; 3729 } 3730 3731 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 3732 { 3733 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 3734 dev_warn(&hdev->pdev->dev, 3735 "vector(vector_id %d) has been freed.\n", vector_id); 3736 return; 3737 } 3738 3739 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 3740 hdev->num_msi_left += 1; 3741 hdev->num_msi_used -= 1; 3742 } 3743 3744 static void hclge_get_misc_vector(struct hclge_dev *hdev) 3745 { 3746 struct hclge_misc_vector *vector = &hdev->misc_vector; 3747 3748 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 3749 3750 vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 3751 hdev->vector_status[0] = 0; 3752 3753 hdev->num_msi_left -= 1; 3754 hdev->num_msi_used += 1; 3755 } 3756 3757 static int hclge_misc_irq_init(struct hclge_dev *hdev) 3758 { 3759 int ret; 3760 3761 hclge_get_misc_vector(hdev); 3762 3763 /* this would be explicitly freed in the end */ 3764 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 3765 HCLGE_NAME, pci_name(hdev->pdev)); 3766 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 3767 0, hdev->misc_vector.name, hdev); 3768 if (ret) { 3769 hclge_free_vector(hdev, 0); 3770 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 3771 hdev->misc_vector.vector_irq); 3772 } 3773 3774 return ret; 3775 } 3776 3777 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 3778 { 3779 free_irq(hdev->misc_vector.vector_irq, hdev); 3780 hclge_free_vector(hdev, 0); 3781 } 3782 3783 int hclge_notify_client(struct hclge_dev *hdev, 3784 enum hnae3_reset_notify_type type) 3785 { 3786 struct hnae3_handle *handle = &hdev->vport[0].nic; 3787 struct hnae3_client *client = hdev->nic_client; 3788 int ret; 3789 3790 if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client) 3791 return 0; 3792 3793 if (!client->ops->reset_notify) 3794 return -EOPNOTSUPP; 3795 3796 ret = client->ops->reset_notify(handle, type); 3797 if (ret) 3798 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 3799 type, ret); 3800 3801 return ret; 3802 } 3803 3804 static int hclge_notify_roce_client(struct hclge_dev *hdev, 3805 enum hnae3_reset_notify_type type) 3806 { 3807 struct hnae3_handle *handle = &hdev->vport[0].roce; 3808 struct hnae3_client *client = hdev->roce_client; 3809 int ret; 3810 3811 if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client) 3812 return 0; 3813 3814 if (!client->ops->reset_notify) 3815 return -EOPNOTSUPP; 3816 3817 ret = client->ops->reset_notify(handle, type); 3818 if (ret) 3819 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 3820 type, ret); 3821 3822 return ret; 3823 } 3824 3825 static int hclge_reset_wait(struct hclge_dev *hdev) 3826 { 3827 #define HCLGE_RESET_WATI_MS 100 3828 #define HCLGE_RESET_WAIT_CNT 350 3829 3830 u32 val, reg, reg_bit; 3831 u32 cnt = 0; 3832 3833 switch (hdev->reset_type) { 3834 case HNAE3_IMP_RESET: 3835 reg = HCLGE_GLOBAL_RESET_REG; 3836 reg_bit = HCLGE_IMP_RESET_BIT; 3837 break; 3838 case HNAE3_GLOBAL_RESET: 3839 reg = HCLGE_GLOBAL_RESET_REG; 3840 reg_bit = HCLGE_GLOBAL_RESET_BIT; 3841 break; 3842 case HNAE3_FUNC_RESET: 3843 reg = HCLGE_FUN_RST_ING; 3844 reg_bit = HCLGE_FUN_RST_ING_B; 3845 break; 3846 default: 3847 dev_err(&hdev->pdev->dev, 3848 "Wait for unsupported reset type: %d\n", 3849 hdev->reset_type); 3850 return -EINVAL; 3851 } 3852 3853 val = hclge_read_dev(&hdev->hw, reg); 3854 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 3855 msleep(HCLGE_RESET_WATI_MS); 3856 val = hclge_read_dev(&hdev->hw, reg); 3857 cnt++; 3858 } 3859 3860 if (cnt >= HCLGE_RESET_WAIT_CNT) { 3861 dev_warn(&hdev->pdev->dev, 3862 "Wait for reset timeout: %d\n", hdev->reset_type); 3863 return -EBUSY; 3864 } 3865 3866 return 0; 3867 } 3868 3869 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset) 3870 { 3871 struct hclge_vf_rst_cmd *req; 3872 struct hclge_desc desc; 3873 3874 req = (struct hclge_vf_rst_cmd *)desc.data; 3875 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false); 3876 req->dest_vfid = func_id; 3877 3878 if (reset) 3879 req->vf_rst = 0x1; 3880 3881 return hclge_cmd_send(&hdev->hw, &desc, 1); 3882 } 3883 3884 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset) 3885 { 3886 int i; 3887 3888 for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) { 3889 struct hclge_vport *vport = &hdev->vport[i]; 3890 int ret; 3891 3892 /* Send cmd to set/clear VF's FUNC_RST_ING */ 3893 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset); 3894 if (ret) { 3895 dev_err(&hdev->pdev->dev, 3896 "set vf(%u) rst failed %d!\n", 3897 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3898 ret); 3899 return ret; 3900 } 3901 3902 if (!reset || !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3903 continue; 3904 3905 /* Inform VF to process the reset. 3906 * hclge_inform_reset_assert_to_vf may fail if VF 3907 * driver is not loaded. 3908 */ 3909 ret = hclge_inform_reset_assert_to_vf(vport); 3910 if (ret) 3911 dev_warn(&hdev->pdev->dev, 3912 "inform reset to vf(%u) failed %d!\n", 3913 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3914 ret); 3915 } 3916 3917 return 0; 3918 } 3919 3920 static void hclge_mailbox_service_task(struct hclge_dev *hdev) 3921 { 3922 if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) || 3923 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) || 3924 test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 3925 return; 3926 3927 if (time_is_before_jiffies(hdev->last_mbx_scheduled + 3928 HCLGE_MBX_SCHED_TIMEOUT)) 3929 dev_warn(&hdev->pdev->dev, 3930 "mbx service task is scheduled after %ums on cpu%u!\n", 3931 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled), 3932 smp_processor_id()); 3933 3934 hclge_mbx_handler(hdev); 3935 3936 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 3937 } 3938 3939 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev) 3940 { 3941 struct hclge_pf_rst_sync_cmd *req; 3942 struct hclge_desc desc; 3943 int cnt = 0; 3944 int ret; 3945 3946 req = (struct hclge_pf_rst_sync_cmd *)desc.data; 3947 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true); 3948 3949 do { 3950 /* vf need to down netdev by mbx during PF or FLR reset */ 3951 hclge_mailbox_service_task(hdev); 3952 3953 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3954 /* for compatible with old firmware, wait 3955 * 100 ms for VF to stop IO 3956 */ 3957 if (ret == -EOPNOTSUPP) { 3958 msleep(HCLGE_RESET_SYNC_TIME); 3959 return; 3960 } else if (ret) { 3961 dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n", 3962 ret); 3963 return; 3964 } else if (req->all_vf_ready) { 3965 return; 3966 } 3967 msleep(HCLGE_PF_RESET_SYNC_TIME); 3968 hclge_comm_cmd_reuse_desc(&desc, true); 3969 } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT); 3970 3971 dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n"); 3972 } 3973 3974 void hclge_report_hw_error(struct hclge_dev *hdev, 3975 enum hnae3_hw_error_type type) 3976 { 3977 struct hnae3_client *client = hdev->nic_client; 3978 3979 if (!client || !client->ops->process_hw_error || 3980 !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) 3981 return; 3982 3983 client->ops->process_hw_error(&hdev->vport[0].nic, type); 3984 } 3985 3986 static void hclge_handle_imp_error(struct hclge_dev *hdev) 3987 { 3988 u32 reg_val; 3989 3990 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 3991 if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { 3992 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); 3993 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); 3994 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 3995 } 3996 3997 if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { 3998 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); 3999 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); 4000 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 4001 } 4002 } 4003 4004 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 4005 { 4006 struct hclge_desc desc; 4007 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 4008 int ret; 4009 4010 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 4011 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 4012 req->fun_reset_vfid = func_id; 4013 4014 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4015 if (ret) 4016 dev_err(&hdev->pdev->dev, 4017 "send function reset cmd fail, status =%d\n", ret); 4018 4019 return ret; 4020 } 4021 4022 static void hclge_do_reset(struct hclge_dev *hdev) 4023 { 4024 struct hnae3_handle *handle = &hdev->vport[0].nic; 4025 struct pci_dev *pdev = hdev->pdev; 4026 u32 val; 4027 4028 if (hclge_get_hw_reset_stat(handle)) { 4029 dev_info(&pdev->dev, "hardware reset not finish\n"); 4030 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n", 4031 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING), 4032 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 4033 return; 4034 } 4035 4036 switch (hdev->reset_type) { 4037 case HNAE3_IMP_RESET: 4038 dev_info(&pdev->dev, "IMP reset requested\n"); 4039 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4040 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1); 4041 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val); 4042 break; 4043 case HNAE3_GLOBAL_RESET: 4044 dev_info(&pdev->dev, "global reset requested\n"); 4045 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 4046 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 4047 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 4048 break; 4049 case HNAE3_FUNC_RESET: 4050 dev_info(&pdev->dev, "PF reset requested\n"); 4051 /* schedule again to check later */ 4052 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); 4053 hclge_reset_task_schedule(hdev); 4054 break; 4055 default: 4056 dev_warn(&pdev->dev, 4057 "unsupported reset type: %d\n", hdev->reset_type); 4058 break; 4059 } 4060 } 4061 4062 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 4063 unsigned long *addr) 4064 { 4065 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 4066 struct hclge_dev *hdev = ae_dev->priv; 4067 4068 /* return the highest priority reset level amongst all */ 4069 if (test_bit(HNAE3_IMP_RESET, addr)) { 4070 rst_level = HNAE3_IMP_RESET; 4071 clear_bit(HNAE3_IMP_RESET, addr); 4072 clear_bit(HNAE3_GLOBAL_RESET, addr); 4073 clear_bit(HNAE3_FUNC_RESET, addr); 4074 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) { 4075 rst_level = HNAE3_GLOBAL_RESET; 4076 clear_bit(HNAE3_GLOBAL_RESET, addr); 4077 clear_bit(HNAE3_FUNC_RESET, addr); 4078 } else if (test_bit(HNAE3_FUNC_RESET, addr)) { 4079 rst_level = HNAE3_FUNC_RESET; 4080 clear_bit(HNAE3_FUNC_RESET, addr); 4081 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 4082 rst_level = HNAE3_FLR_RESET; 4083 clear_bit(HNAE3_FLR_RESET, addr); 4084 } 4085 4086 if (hdev->reset_type != HNAE3_NONE_RESET && 4087 rst_level < hdev->reset_type) 4088 return HNAE3_NONE_RESET; 4089 4090 return rst_level; 4091 } 4092 4093 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 4094 { 4095 u32 clearval = 0; 4096 4097 switch (hdev->reset_type) { 4098 case HNAE3_IMP_RESET: 4099 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 4100 break; 4101 case HNAE3_GLOBAL_RESET: 4102 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 4103 break; 4104 default: 4105 break; 4106 } 4107 4108 if (!clearval) 4109 return; 4110 4111 /* For revision 0x20, the reset interrupt source 4112 * can only be cleared after hardware reset done 4113 */ 4114 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 4115 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, 4116 clearval); 4117 4118 hclge_enable_vector(&hdev->misc_vector, true); 4119 } 4120 4121 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable) 4122 { 4123 u32 reg_val; 4124 4125 reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 4126 if (enable) 4127 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY; 4128 else 4129 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY; 4130 4131 hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val); 4132 } 4133 4134 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev) 4135 { 4136 int ret; 4137 4138 ret = hclge_set_all_vf_rst(hdev, true); 4139 if (ret) 4140 return ret; 4141 4142 hclge_func_reset_sync_vf(hdev); 4143 4144 return 0; 4145 } 4146 4147 static int hclge_reset_prepare_wait(struct hclge_dev *hdev) 4148 { 4149 u32 reg_val; 4150 int ret = 0; 4151 4152 switch (hdev->reset_type) { 4153 case HNAE3_FUNC_RESET: 4154 ret = hclge_func_reset_notify_vf(hdev); 4155 if (ret) 4156 return ret; 4157 4158 ret = hclge_func_reset_cmd(hdev, 0); 4159 if (ret) { 4160 dev_err(&hdev->pdev->dev, 4161 "asserting function reset fail %d!\n", ret); 4162 return ret; 4163 } 4164 4165 /* After performaning pf reset, it is not necessary to do the 4166 * mailbox handling or send any command to firmware, because 4167 * any mailbox handling or command to firmware is only valid 4168 * after hclge_comm_cmd_init is called. 4169 */ 4170 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 4171 hdev->rst_stats.pf_rst_cnt++; 4172 break; 4173 case HNAE3_FLR_RESET: 4174 ret = hclge_func_reset_notify_vf(hdev); 4175 if (ret) 4176 return ret; 4177 break; 4178 case HNAE3_IMP_RESET: 4179 hclge_handle_imp_error(hdev); 4180 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4181 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, 4182 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); 4183 break; 4184 default: 4185 break; 4186 } 4187 4188 /* inform hardware that preparatory work is done */ 4189 msleep(HCLGE_RESET_SYNC_TIME); 4190 hclge_reset_handshake(hdev, true); 4191 dev_info(&hdev->pdev->dev, "prepare wait ok\n"); 4192 4193 return ret; 4194 } 4195 4196 static void hclge_show_rst_info(struct hclge_dev *hdev) 4197 { 4198 char *buf; 4199 4200 buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL); 4201 if (!buf) 4202 return; 4203 4204 hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN); 4205 4206 dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf); 4207 4208 kfree(buf); 4209 } 4210 4211 static bool hclge_reset_err_handle(struct hclge_dev *hdev) 4212 { 4213 #define MAX_RESET_FAIL_CNT 5 4214 4215 if (hdev->reset_pending) { 4216 dev_info(&hdev->pdev->dev, "Reset pending %lu\n", 4217 hdev->reset_pending); 4218 return true; 4219 } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) & 4220 HCLGE_RESET_INT_M) { 4221 dev_info(&hdev->pdev->dev, 4222 "reset failed because new reset interrupt\n"); 4223 hclge_clear_reset_cause(hdev); 4224 return false; 4225 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { 4226 hdev->rst_stats.reset_fail_cnt++; 4227 set_bit(hdev->reset_type, &hdev->reset_pending); 4228 dev_info(&hdev->pdev->dev, 4229 "re-schedule reset task(%u)\n", 4230 hdev->rst_stats.reset_fail_cnt); 4231 return true; 4232 } 4233 4234 hclge_clear_reset_cause(hdev); 4235 4236 /* recover the handshake status when reset fail */ 4237 hclge_reset_handshake(hdev, true); 4238 4239 dev_err(&hdev->pdev->dev, "Reset fail!\n"); 4240 4241 hclge_show_rst_info(hdev); 4242 4243 set_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4244 4245 return false; 4246 } 4247 4248 static void hclge_update_reset_level(struct hclge_dev *hdev) 4249 { 4250 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4251 enum hnae3_reset_type reset_level; 4252 4253 /* reset request will not be set during reset, so clear 4254 * pending reset request to avoid unnecessary reset 4255 * caused by the same reason. 4256 */ 4257 hclge_get_reset_level(ae_dev, &hdev->reset_request); 4258 4259 /* if default_reset_request has a higher level reset request, 4260 * it should be handled as soon as possible. since some errors 4261 * need this kind of reset to fix. 4262 */ 4263 reset_level = hclge_get_reset_level(ae_dev, 4264 &hdev->default_reset_request); 4265 if (reset_level != HNAE3_NONE_RESET) 4266 set_bit(reset_level, &hdev->reset_request); 4267 } 4268 4269 static int hclge_set_rst_done(struct hclge_dev *hdev) 4270 { 4271 struct hclge_pf_rst_done_cmd *req; 4272 struct hclge_desc desc; 4273 int ret; 4274 4275 req = (struct hclge_pf_rst_done_cmd *)desc.data; 4276 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false); 4277 req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT; 4278 4279 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4280 /* To be compatible with the old firmware, which does not support 4281 * command HCLGE_OPC_PF_RST_DONE, just print a warning and 4282 * return success 4283 */ 4284 if (ret == -EOPNOTSUPP) { 4285 dev_warn(&hdev->pdev->dev, 4286 "current firmware does not support command(0x%x)!\n", 4287 HCLGE_OPC_PF_RST_DONE); 4288 return 0; 4289 } else if (ret) { 4290 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n", 4291 ret); 4292 } 4293 4294 return ret; 4295 } 4296 4297 static int hclge_reset_prepare_up(struct hclge_dev *hdev) 4298 { 4299 int ret = 0; 4300 4301 switch (hdev->reset_type) { 4302 case HNAE3_FUNC_RESET: 4303 case HNAE3_FLR_RESET: 4304 ret = hclge_set_all_vf_rst(hdev, false); 4305 break; 4306 case HNAE3_GLOBAL_RESET: 4307 case HNAE3_IMP_RESET: 4308 ret = hclge_set_rst_done(hdev); 4309 break; 4310 default: 4311 break; 4312 } 4313 4314 /* clear up the handshake status after re-initialize done */ 4315 hclge_reset_handshake(hdev, false); 4316 4317 return ret; 4318 } 4319 4320 static int hclge_reset_stack(struct hclge_dev *hdev) 4321 { 4322 int ret; 4323 4324 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 4325 if (ret) 4326 return ret; 4327 4328 ret = hclge_reset_ae_dev(hdev->ae_dev); 4329 if (ret) 4330 return ret; 4331 4332 return hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 4333 } 4334 4335 static int hclge_reset_prepare(struct hclge_dev *hdev) 4336 { 4337 int ret; 4338 4339 hdev->rst_stats.reset_cnt++; 4340 /* perform reset of the stack & ae device for a client */ 4341 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 4342 if (ret) 4343 return ret; 4344 4345 rtnl_lock(); 4346 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 4347 rtnl_unlock(); 4348 if (ret) 4349 return ret; 4350 4351 return hclge_reset_prepare_wait(hdev); 4352 } 4353 4354 static int hclge_reset_rebuild(struct hclge_dev *hdev) 4355 { 4356 int ret; 4357 4358 hdev->rst_stats.hw_reset_done_cnt++; 4359 4360 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 4361 if (ret) 4362 return ret; 4363 4364 rtnl_lock(); 4365 ret = hclge_reset_stack(hdev); 4366 rtnl_unlock(); 4367 if (ret) 4368 return ret; 4369 4370 hclge_clear_reset_cause(hdev); 4371 4372 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 4373 /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1 4374 * times 4375 */ 4376 if (ret && 4377 hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1) 4378 return ret; 4379 4380 ret = hclge_reset_prepare_up(hdev); 4381 if (ret) 4382 return ret; 4383 4384 rtnl_lock(); 4385 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT); 4386 rtnl_unlock(); 4387 if (ret) 4388 return ret; 4389 4390 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT); 4391 if (ret) 4392 return ret; 4393 4394 hdev->last_reset_time = jiffies; 4395 hdev->rst_stats.reset_fail_cnt = 0; 4396 hdev->rst_stats.reset_done_cnt++; 4397 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4398 4399 hclge_update_reset_level(hdev); 4400 4401 return 0; 4402 } 4403 4404 static void hclge_reset(struct hclge_dev *hdev) 4405 { 4406 if (hclge_reset_prepare(hdev)) 4407 goto err_reset; 4408 4409 if (hclge_reset_wait(hdev)) 4410 goto err_reset; 4411 4412 if (hclge_reset_rebuild(hdev)) 4413 goto err_reset; 4414 4415 return; 4416 4417 err_reset: 4418 if (hclge_reset_err_handle(hdev)) 4419 hclge_reset_task_schedule(hdev); 4420 } 4421 4422 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) 4423 { 4424 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4425 struct hclge_dev *hdev = ae_dev->priv; 4426 4427 /* We might end up getting called broadly because of 2 below cases: 4428 * 1. Recoverable error was conveyed through APEI and only way to bring 4429 * normalcy is to reset. 4430 * 2. A new reset request from the stack due to timeout 4431 * 4432 * check if this is a new reset request and we are not here just because 4433 * last reset attempt did not succeed and watchdog hit us again. We will 4434 * know this if last reset request did not occur very recently (watchdog 4435 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 4436 * In case of new request we reset the "reset level" to PF reset. 4437 * And if it is a repeat reset request of the most recent one then we 4438 * want to make sure we throttle the reset request. Therefore, we will 4439 * not allow it again before 3*HZ times. 4440 */ 4441 4442 if (time_before(jiffies, (hdev->last_reset_time + 4443 HCLGE_RESET_INTERVAL))) { 4444 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 4445 return; 4446 } 4447 4448 if (hdev->default_reset_request) { 4449 hdev->reset_level = 4450 hclge_get_reset_level(ae_dev, 4451 &hdev->default_reset_request); 4452 } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) { 4453 hdev->reset_level = HNAE3_FUNC_RESET; 4454 } 4455 4456 dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n", 4457 hdev->reset_level); 4458 4459 /* request reset & schedule reset task */ 4460 set_bit(hdev->reset_level, &hdev->reset_request); 4461 hclge_reset_task_schedule(hdev); 4462 4463 if (hdev->reset_level < HNAE3_GLOBAL_RESET) 4464 hdev->reset_level++; 4465 } 4466 4467 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 4468 enum hnae3_reset_type rst_type) 4469 { 4470 struct hclge_dev *hdev = ae_dev->priv; 4471 4472 set_bit(rst_type, &hdev->default_reset_request); 4473 } 4474 4475 static void hclge_reset_timer(struct timer_list *t) 4476 { 4477 struct hclge_dev *hdev = from_timer(hdev, t, reset_timer); 4478 4479 /* if default_reset_request has no value, it means that this reset 4480 * request has already be handled, so just return here 4481 */ 4482 if (!hdev->default_reset_request) 4483 return; 4484 4485 dev_info(&hdev->pdev->dev, 4486 "triggering reset in reset timer\n"); 4487 hclge_reset_event(hdev->pdev, NULL); 4488 } 4489 4490 static void hclge_reset_subtask(struct hclge_dev *hdev) 4491 { 4492 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4493 4494 /* check if there is any ongoing reset in the hardware. This status can 4495 * be checked from reset_pending. If there is then, we need to wait for 4496 * hardware to complete reset. 4497 * a. If we are able to figure out in reasonable time that hardware 4498 * has fully resetted then, we can proceed with driver, client 4499 * reset. 4500 * b. else, we can come back later to check this status so re-sched 4501 * now. 4502 */ 4503 hdev->last_reset_time = jiffies; 4504 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending); 4505 if (hdev->reset_type != HNAE3_NONE_RESET) 4506 hclge_reset(hdev); 4507 4508 /* check if we got any *new* reset requests to be honored */ 4509 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request); 4510 if (hdev->reset_type != HNAE3_NONE_RESET) 4511 hclge_do_reset(hdev); 4512 4513 hdev->reset_type = HNAE3_NONE_RESET; 4514 } 4515 4516 static void hclge_handle_err_reset_request(struct hclge_dev *hdev) 4517 { 4518 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4519 enum hnae3_reset_type reset_type; 4520 4521 if (ae_dev->hw_err_reset_req) { 4522 reset_type = hclge_get_reset_level(ae_dev, 4523 &ae_dev->hw_err_reset_req); 4524 hclge_set_def_reset_request(ae_dev, reset_type); 4525 } 4526 4527 if (hdev->default_reset_request && ae_dev->ops->reset_event) 4528 ae_dev->ops->reset_event(hdev->pdev, NULL); 4529 4530 /* enable interrupt after error handling complete */ 4531 hclge_enable_vector(&hdev->misc_vector, true); 4532 } 4533 4534 static void hclge_handle_err_recovery(struct hclge_dev *hdev) 4535 { 4536 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4537 4538 ae_dev->hw_err_reset_req = 0; 4539 4540 if (hclge_find_error_source(hdev)) { 4541 hclge_handle_error_info_log(ae_dev); 4542 hclge_handle_mac_tnl(hdev); 4543 } 4544 4545 hclge_handle_err_reset_request(hdev); 4546 } 4547 4548 static void hclge_misc_err_recovery(struct hclge_dev *hdev) 4549 { 4550 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4551 struct device *dev = &hdev->pdev->dev; 4552 u32 msix_sts_reg; 4553 4554 msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 4555 if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) { 4556 if (hclge_handle_hw_msix_error 4557 (hdev, &hdev->default_reset_request)) 4558 dev_info(dev, "received msix interrupt 0x%x\n", 4559 msix_sts_reg); 4560 } 4561 4562 hclge_handle_hw_ras_error(ae_dev); 4563 4564 hclge_handle_err_reset_request(hdev); 4565 } 4566 4567 static void hclge_errhand_service_task(struct hclge_dev *hdev) 4568 { 4569 if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 4570 return; 4571 4572 if (hnae3_dev_ras_imp_supported(hdev)) 4573 hclge_handle_err_recovery(hdev); 4574 else 4575 hclge_misc_err_recovery(hdev); 4576 } 4577 4578 static void hclge_reset_service_task(struct hclge_dev *hdev) 4579 { 4580 if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 4581 return; 4582 4583 if (time_is_before_jiffies(hdev->last_rst_scheduled + 4584 HCLGE_RESET_SCHED_TIMEOUT)) 4585 dev_warn(&hdev->pdev->dev, 4586 "reset service task is scheduled after %ums on cpu%u!\n", 4587 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled), 4588 smp_processor_id()); 4589 4590 down(&hdev->reset_sem); 4591 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4592 4593 hclge_reset_subtask(hdev); 4594 4595 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4596 up(&hdev->reset_sem); 4597 } 4598 4599 static void hclge_update_vport_alive(struct hclge_dev *hdev) 4600 { 4601 int i; 4602 4603 /* start from vport 1 for PF is always alive */ 4604 for (i = 1; i < hdev->num_alloc_vport; i++) { 4605 struct hclge_vport *vport = &hdev->vport[i]; 4606 4607 if (time_after(jiffies, vport->last_active_jiffies + 8 * HZ)) 4608 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 4609 4610 /* If vf is not alive, set to default value */ 4611 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 4612 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 4613 } 4614 } 4615 4616 static void hclge_periodic_service_task(struct hclge_dev *hdev) 4617 { 4618 unsigned long delta = round_jiffies_relative(HZ); 4619 4620 if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 4621 return; 4622 4623 /* Always handle the link updating to make sure link state is 4624 * updated when it is triggered by mbx. 4625 */ 4626 hclge_update_link_status(hdev); 4627 hclge_sync_mac_table(hdev); 4628 hclge_sync_promisc_mode(hdev); 4629 hclge_sync_fd_table(hdev); 4630 4631 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 4632 delta = jiffies - hdev->last_serv_processed; 4633 4634 if (delta < round_jiffies_relative(HZ)) { 4635 delta = round_jiffies_relative(HZ) - delta; 4636 goto out; 4637 } 4638 } 4639 4640 hdev->serv_processed_cnt++; 4641 hclge_update_vport_alive(hdev); 4642 4643 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) { 4644 hdev->last_serv_processed = jiffies; 4645 goto out; 4646 } 4647 4648 if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL)) 4649 hclge_update_stats_for_all(hdev); 4650 4651 hclge_update_port_info(hdev); 4652 hclge_sync_vlan_filter(hdev); 4653 4654 if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL)) 4655 hclge_rfs_filter_expire(hdev); 4656 4657 hdev->last_serv_processed = jiffies; 4658 4659 out: 4660 hclge_task_schedule(hdev, delta); 4661 } 4662 4663 static void hclge_ptp_service_task(struct hclge_dev *hdev) 4664 { 4665 unsigned long flags; 4666 4667 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) || 4668 !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) || 4669 !time_is_before_jiffies(hdev->ptp->tx_start + HZ)) 4670 return; 4671 4672 /* to prevent concurrence with the irq handler */ 4673 spin_lock_irqsave(&hdev->ptp->lock, flags); 4674 4675 /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq 4676 * handler may handle it just before spin_lock_irqsave(). 4677 */ 4678 if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) 4679 hclge_ptp_clean_tx_hwts(hdev); 4680 4681 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 4682 } 4683 4684 static void hclge_service_task(struct work_struct *work) 4685 { 4686 struct hclge_dev *hdev = 4687 container_of(work, struct hclge_dev, service_task.work); 4688 4689 hclge_errhand_service_task(hdev); 4690 hclge_reset_service_task(hdev); 4691 hclge_ptp_service_task(hdev); 4692 hclge_mailbox_service_task(hdev); 4693 hclge_periodic_service_task(hdev); 4694 4695 /* Handle error recovery, reset and mbx again in case periodical task 4696 * delays the handling by calling hclge_task_schedule() in 4697 * hclge_periodic_service_task(). 4698 */ 4699 hclge_errhand_service_task(hdev); 4700 hclge_reset_service_task(hdev); 4701 hclge_mailbox_service_task(hdev); 4702 } 4703 4704 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 4705 { 4706 /* VF handle has no client */ 4707 if (!handle->client) 4708 return container_of(handle, struct hclge_vport, nic); 4709 else if (handle->client->type == HNAE3_CLIENT_ROCE) 4710 return container_of(handle, struct hclge_vport, roce); 4711 else 4712 return container_of(handle, struct hclge_vport, nic); 4713 } 4714 4715 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx, 4716 struct hnae3_vector_info *vector_info) 4717 { 4718 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 64 4719 4720 vector_info->vector = pci_irq_vector(hdev->pdev, idx); 4721 4722 /* need an extend offset to config vector >= 64 */ 4723 if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2) 4724 vector_info->io_addr = hdev->hw.hw.io_base + 4725 HCLGE_VECTOR_REG_BASE + 4726 (idx - 1) * HCLGE_VECTOR_REG_OFFSET; 4727 else 4728 vector_info->io_addr = hdev->hw.hw.io_base + 4729 HCLGE_VECTOR_EXT_REG_BASE + 4730 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4731 HCLGE_VECTOR_REG_OFFSET_H + 4732 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4733 HCLGE_VECTOR_REG_OFFSET; 4734 4735 hdev->vector_status[idx] = hdev->vport[0].vport_id; 4736 hdev->vector_irq[idx] = vector_info->vector; 4737 } 4738 4739 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 4740 struct hnae3_vector_info *vector_info) 4741 { 4742 struct hclge_vport *vport = hclge_get_vport(handle); 4743 struct hnae3_vector_info *vector = vector_info; 4744 struct hclge_dev *hdev = vport->back; 4745 int alloc = 0; 4746 u16 i = 0; 4747 u16 j; 4748 4749 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num); 4750 vector_num = min(hdev->num_msi_left, vector_num); 4751 4752 for (j = 0; j < vector_num; j++) { 4753 while (++i < hdev->num_nic_msi) { 4754 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 4755 hclge_get_vector_info(hdev, i, vector); 4756 vector++; 4757 alloc++; 4758 4759 break; 4760 } 4761 } 4762 } 4763 hdev->num_msi_left -= alloc; 4764 hdev->num_msi_used += alloc; 4765 4766 return alloc; 4767 } 4768 4769 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 4770 { 4771 int i; 4772 4773 for (i = 0; i < hdev->num_msi; i++) 4774 if (vector == hdev->vector_irq[i]) 4775 return i; 4776 4777 return -EINVAL; 4778 } 4779 4780 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 4781 { 4782 struct hclge_vport *vport = hclge_get_vport(handle); 4783 struct hclge_dev *hdev = vport->back; 4784 int vector_id; 4785 4786 vector_id = hclge_get_vector_index(hdev, vector); 4787 if (vector_id < 0) { 4788 dev_err(&hdev->pdev->dev, 4789 "Get vector index fail. vector = %d\n", vector); 4790 return vector_id; 4791 } 4792 4793 hclge_free_vector(hdev, vector_id); 4794 4795 return 0; 4796 } 4797 4798 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 4799 u8 *key, u8 *hfunc) 4800 { 4801 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4802 struct hclge_vport *vport = hclge_get_vport(handle); 4803 struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg; 4804 4805 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 4806 4807 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 4808 ae_dev->dev_specs.rss_ind_tbl_size); 4809 4810 return 0; 4811 } 4812 4813 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 4814 const u8 *key, const u8 hfunc) 4815 { 4816 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4817 struct hclge_vport *vport = hclge_get_vport(handle); 4818 struct hclge_dev *hdev = vport->back; 4819 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 4820 int ret, i; 4821 4822 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc); 4823 if (ret) { 4824 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc); 4825 return ret; 4826 } 4827 4828 /* Update the shadow RSS table with user specified qids */ 4829 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 4830 rss_cfg->rss_indirection_tbl[i] = indir[i]; 4831 4832 /* Update the hardware */ 4833 return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw, 4834 rss_cfg->rss_indirection_tbl); 4835 } 4836 4837 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 4838 struct ethtool_rxnfc *nfc) 4839 { 4840 struct hclge_vport *vport = hclge_get_vport(handle); 4841 struct hclge_dev *hdev = vport->back; 4842 int ret; 4843 4844 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 4845 &hdev->rss_cfg, nfc); 4846 if (ret) { 4847 dev_err(&hdev->pdev->dev, 4848 "failed to set rss tuple, ret = %d.\n", ret); 4849 return ret; 4850 } 4851 4852 hclge_comm_get_rss_type(&vport->nic, &hdev->rss_cfg.rss_tuple_sets); 4853 return 0; 4854 } 4855 4856 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 4857 struct ethtool_rxnfc *nfc) 4858 { 4859 struct hclge_vport *vport = hclge_get_vport(handle); 4860 u8 tuple_sets; 4861 int ret; 4862 4863 nfc->data = 0; 4864 4865 ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type, 4866 &tuple_sets); 4867 if (ret || !tuple_sets) 4868 return ret; 4869 4870 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 4871 4872 return 0; 4873 } 4874 4875 static int hclge_get_tc_size(struct hnae3_handle *handle) 4876 { 4877 struct hclge_vport *vport = hclge_get_vport(handle); 4878 struct hclge_dev *hdev = vport->back; 4879 4880 return hdev->pf_rss_size_max; 4881 } 4882 4883 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev) 4884 { 4885 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 4886 struct hclge_vport *vport = hdev->vport; 4887 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 4888 u16 tc_valid[HCLGE_MAX_TC_NUM] = {0}; 4889 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 4890 struct hnae3_tc_info *tc_info; 4891 u16 roundup_size; 4892 u16 rss_size; 4893 int i; 4894 4895 tc_info = &vport->nic.kinfo.tc_info; 4896 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 4897 rss_size = tc_info->tqp_count[i]; 4898 tc_valid[i] = 0; 4899 4900 if (!(hdev->hw_tc_map & BIT(i))) 4901 continue; 4902 4903 /* tc_size set to hardware is the log2 of roundup power of two 4904 * of rss_size, the acutal queue size is limited by indirection 4905 * table. 4906 */ 4907 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size || 4908 rss_size == 0) { 4909 dev_err(&hdev->pdev->dev, 4910 "Configure rss tc size failed, invalid TC_SIZE = %u\n", 4911 rss_size); 4912 return -EINVAL; 4913 } 4914 4915 roundup_size = roundup_pow_of_two(rss_size); 4916 roundup_size = ilog2(roundup_size); 4917 4918 tc_valid[i] = 1; 4919 tc_size[i] = roundup_size; 4920 tc_offset[i] = tc_info->tqp_offset[i]; 4921 } 4922 4923 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 4924 tc_size); 4925 } 4926 4927 int hclge_rss_init_hw(struct hclge_dev *hdev) 4928 { 4929 u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl; 4930 u8 *key = hdev->rss_cfg.rss_hash_key; 4931 u8 hfunc = hdev->rss_cfg.rss_algo; 4932 int ret; 4933 4934 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 4935 rss_indir); 4936 if (ret) 4937 return ret; 4938 4939 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key); 4940 if (ret) 4941 return ret; 4942 4943 ret = hclge_comm_set_rss_input_tuple(&hdev->vport[0].nic, 4944 &hdev->hw.hw, true, 4945 &hdev->rss_cfg); 4946 if (ret) 4947 return ret; 4948 4949 return hclge_init_rss_tc_mode(hdev); 4950 } 4951 4952 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 4953 int vector_id, bool en, 4954 struct hnae3_ring_chain_node *ring_chain) 4955 { 4956 struct hclge_dev *hdev = vport->back; 4957 struct hnae3_ring_chain_node *node; 4958 struct hclge_desc desc; 4959 struct hclge_ctrl_vector_chain_cmd *req = 4960 (struct hclge_ctrl_vector_chain_cmd *)desc.data; 4961 enum hclge_comm_cmd_status status; 4962 enum hclge_opcode_type op; 4963 u16 tqp_type_and_id; 4964 int i; 4965 4966 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 4967 hclge_cmd_setup_basic_desc(&desc, op, false); 4968 req->int_vector_id_l = hnae3_get_field(vector_id, 4969 HCLGE_VECTOR_ID_L_M, 4970 HCLGE_VECTOR_ID_L_S); 4971 req->int_vector_id_h = hnae3_get_field(vector_id, 4972 HCLGE_VECTOR_ID_H_M, 4973 HCLGE_VECTOR_ID_H_S); 4974 4975 i = 0; 4976 for (node = ring_chain; node; node = node->next) { 4977 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 4978 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 4979 HCLGE_INT_TYPE_S, 4980 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 4981 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 4982 HCLGE_TQP_ID_S, node->tqp_index); 4983 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 4984 HCLGE_INT_GL_IDX_S, 4985 hnae3_get_field(node->int_gl_idx, 4986 HNAE3_RING_GL_IDX_M, 4987 HNAE3_RING_GL_IDX_S)); 4988 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 4989 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 4990 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 4991 req->vfid = vport->vport_id; 4992 4993 status = hclge_cmd_send(&hdev->hw, &desc, 1); 4994 if (status) { 4995 dev_err(&hdev->pdev->dev, 4996 "Map TQP fail, status is %d.\n", 4997 status); 4998 return -EIO; 4999 } 5000 i = 0; 5001 5002 hclge_cmd_setup_basic_desc(&desc, 5003 op, 5004 false); 5005 req->int_vector_id_l = 5006 hnae3_get_field(vector_id, 5007 HCLGE_VECTOR_ID_L_M, 5008 HCLGE_VECTOR_ID_L_S); 5009 req->int_vector_id_h = 5010 hnae3_get_field(vector_id, 5011 HCLGE_VECTOR_ID_H_M, 5012 HCLGE_VECTOR_ID_H_S); 5013 } 5014 } 5015 5016 if (i > 0) { 5017 req->int_cause_num = i; 5018 req->vfid = vport->vport_id; 5019 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5020 if (status) { 5021 dev_err(&hdev->pdev->dev, 5022 "Map TQP fail, status is %d.\n", status); 5023 return -EIO; 5024 } 5025 } 5026 5027 return 0; 5028 } 5029 5030 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector, 5031 struct hnae3_ring_chain_node *ring_chain) 5032 { 5033 struct hclge_vport *vport = hclge_get_vport(handle); 5034 struct hclge_dev *hdev = vport->back; 5035 int vector_id; 5036 5037 vector_id = hclge_get_vector_index(hdev, vector); 5038 if (vector_id < 0) { 5039 dev_err(&hdev->pdev->dev, 5040 "failed to get vector index. vector=%d\n", vector); 5041 return vector_id; 5042 } 5043 5044 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 5045 } 5046 5047 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector, 5048 struct hnae3_ring_chain_node *ring_chain) 5049 { 5050 struct hclge_vport *vport = hclge_get_vport(handle); 5051 struct hclge_dev *hdev = vport->back; 5052 int vector_id, ret; 5053 5054 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 5055 return 0; 5056 5057 vector_id = hclge_get_vector_index(hdev, vector); 5058 if (vector_id < 0) { 5059 dev_err(&handle->pdev->dev, 5060 "Get vector index fail. ret =%d\n", vector_id); 5061 return vector_id; 5062 } 5063 5064 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 5065 if (ret) 5066 dev_err(&handle->pdev->dev, 5067 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 5068 vector_id, ret); 5069 5070 return ret; 5071 } 5072 5073 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id, 5074 bool en_uc, bool en_mc, bool en_bc) 5075 { 5076 struct hclge_vport *vport = &hdev->vport[vf_id]; 5077 struct hnae3_handle *handle = &vport->nic; 5078 struct hclge_promisc_cfg_cmd *req; 5079 struct hclge_desc desc; 5080 bool uc_tx_en = en_uc; 5081 u8 promisc_cfg = 0; 5082 int ret; 5083 5084 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 5085 5086 req = (struct hclge_promisc_cfg_cmd *)desc.data; 5087 req->vf_id = vf_id; 5088 5089 if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags)) 5090 uc_tx_en = false; 5091 5092 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0); 5093 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0); 5094 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0); 5095 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0); 5096 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0); 5097 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0); 5098 req->extend_promisc = promisc_cfg; 5099 5100 /* to be compatible with DEVICE_VERSION_V1/2 */ 5101 promisc_cfg = 0; 5102 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0); 5103 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0); 5104 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0); 5105 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1); 5106 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1); 5107 req->promisc = promisc_cfg; 5108 5109 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5110 if (ret) 5111 dev_err(&hdev->pdev->dev, 5112 "failed to set vport %u promisc mode, ret = %d.\n", 5113 vf_id, ret); 5114 5115 return ret; 5116 } 5117 5118 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 5119 bool en_mc_pmc, bool en_bc_pmc) 5120 { 5121 return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id, 5122 en_uc_pmc, en_mc_pmc, en_bc_pmc); 5123 } 5124 5125 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 5126 bool en_mc_pmc) 5127 { 5128 struct hclge_vport *vport = hclge_get_vport(handle); 5129 struct hclge_dev *hdev = vport->back; 5130 bool en_bc_pmc = true; 5131 5132 /* For device whose version below V2, if broadcast promisc enabled, 5133 * vlan filter is always bypassed. So broadcast promisc should be 5134 * disabled until user enable promisc mode 5135 */ 5136 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 5137 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false; 5138 5139 return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc, 5140 en_bc_pmc); 5141 } 5142 5143 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle) 5144 { 5145 struct hclge_vport *vport = hclge_get_vport(handle); 5146 5147 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5148 } 5149 5150 static void hclge_sync_fd_state(struct hclge_dev *hdev) 5151 { 5152 if (hlist_empty(&hdev->fd_rule_list)) 5153 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 5154 } 5155 5156 static void hclge_fd_inc_rule_cnt(struct hclge_dev *hdev, u16 location) 5157 { 5158 if (!test_bit(location, hdev->fd_bmap)) { 5159 set_bit(location, hdev->fd_bmap); 5160 hdev->hclge_fd_rule_num++; 5161 } 5162 } 5163 5164 static void hclge_fd_dec_rule_cnt(struct hclge_dev *hdev, u16 location) 5165 { 5166 if (test_bit(location, hdev->fd_bmap)) { 5167 clear_bit(location, hdev->fd_bmap); 5168 hdev->hclge_fd_rule_num--; 5169 } 5170 } 5171 5172 static void hclge_fd_free_node(struct hclge_dev *hdev, 5173 struct hclge_fd_rule *rule) 5174 { 5175 hlist_del(&rule->rule_node); 5176 kfree(rule); 5177 hclge_sync_fd_state(hdev); 5178 } 5179 5180 static void hclge_update_fd_rule_node(struct hclge_dev *hdev, 5181 struct hclge_fd_rule *old_rule, 5182 struct hclge_fd_rule *new_rule, 5183 enum HCLGE_FD_NODE_STATE state) 5184 { 5185 switch (state) { 5186 case HCLGE_FD_TO_ADD: 5187 case HCLGE_FD_ACTIVE: 5188 /* 1) if the new state is TO_ADD, just replace the old rule 5189 * with the same location, no matter its state, because the 5190 * new rule will be configured to the hardware. 5191 * 2) if the new state is ACTIVE, it means the new rule 5192 * has been configured to the hardware, so just replace 5193 * the old rule node with the same location. 5194 * 3) for it doesn't add a new node to the list, so it's 5195 * unnecessary to update the rule number and fd_bmap. 5196 */ 5197 new_rule->rule_node.next = old_rule->rule_node.next; 5198 new_rule->rule_node.pprev = old_rule->rule_node.pprev; 5199 memcpy(old_rule, new_rule, sizeof(*old_rule)); 5200 kfree(new_rule); 5201 break; 5202 case HCLGE_FD_DELETED: 5203 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5204 hclge_fd_free_node(hdev, old_rule); 5205 break; 5206 case HCLGE_FD_TO_DEL: 5207 /* if new request is TO_DEL, and old rule is existent 5208 * 1) the state of old rule is TO_DEL, we need do nothing, 5209 * because we delete rule by location, other rule content 5210 * is unncessary. 5211 * 2) the state of old rule is ACTIVE, we need to change its 5212 * state to TO_DEL, so the rule will be deleted when periodic 5213 * task being scheduled. 5214 * 3) the state of old rule is TO_ADD, it means the rule hasn't 5215 * been added to hardware, so we just delete the rule node from 5216 * fd_rule_list directly. 5217 */ 5218 if (old_rule->state == HCLGE_FD_TO_ADD) { 5219 hclge_fd_dec_rule_cnt(hdev, old_rule->location); 5220 hclge_fd_free_node(hdev, old_rule); 5221 return; 5222 } 5223 old_rule->state = HCLGE_FD_TO_DEL; 5224 break; 5225 } 5226 } 5227 5228 static struct hclge_fd_rule *hclge_find_fd_rule(struct hlist_head *hlist, 5229 u16 location, 5230 struct hclge_fd_rule **parent) 5231 { 5232 struct hclge_fd_rule *rule; 5233 struct hlist_node *node; 5234 5235 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 5236 if (rule->location == location) 5237 return rule; 5238 else if (rule->location > location) 5239 return NULL; 5240 /* record the parent node, use to keep the nodes in fd_rule_list 5241 * in ascend order. 5242 */ 5243 *parent = rule; 5244 } 5245 5246 return NULL; 5247 } 5248 5249 /* insert fd rule node in ascend order according to rule->location */ 5250 static void hclge_fd_insert_rule_node(struct hlist_head *hlist, 5251 struct hclge_fd_rule *rule, 5252 struct hclge_fd_rule *parent) 5253 { 5254 INIT_HLIST_NODE(&rule->rule_node); 5255 5256 if (parent) 5257 hlist_add_behind(&rule->rule_node, &parent->rule_node); 5258 else 5259 hlist_add_head(&rule->rule_node, hlist); 5260 } 5261 5262 static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev, 5263 struct hclge_fd_user_def_cfg *cfg) 5264 { 5265 struct hclge_fd_user_def_cfg_cmd *req; 5266 struct hclge_desc desc; 5267 u16 data = 0; 5268 int ret; 5269 5270 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_USER_DEF_OP, false); 5271 5272 req = (struct hclge_fd_user_def_cfg_cmd *)desc.data; 5273 5274 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[0].ref_cnt > 0); 5275 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5276 HCLGE_FD_USER_DEF_OFT_S, cfg[0].offset); 5277 req->ol2_cfg = cpu_to_le16(data); 5278 5279 data = 0; 5280 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[1].ref_cnt > 0); 5281 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5282 HCLGE_FD_USER_DEF_OFT_S, cfg[1].offset); 5283 req->ol3_cfg = cpu_to_le16(data); 5284 5285 data = 0; 5286 hnae3_set_bit(data, HCLGE_FD_USER_DEF_EN_B, cfg[2].ref_cnt > 0); 5287 hnae3_set_field(data, HCLGE_FD_USER_DEF_OFT_M, 5288 HCLGE_FD_USER_DEF_OFT_S, cfg[2].offset); 5289 req->ol4_cfg = cpu_to_le16(data); 5290 5291 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5292 if (ret) 5293 dev_err(&hdev->pdev->dev, 5294 "failed to set fd user def data, ret= %d\n", ret); 5295 return ret; 5296 } 5297 5298 static void hclge_sync_fd_user_def_cfg(struct hclge_dev *hdev, bool locked) 5299 { 5300 int ret; 5301 5302 if (!test_and_clear_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state)) 5303 return; 5304 5305 if (!locked) 5306 spin_lock_bh(&hdev->fd_rule_lock); 5307 5308 ret = hclge_fd_set_user_def_cmd(hdev, hdev->fd_cfg.user_def_cfg); 5309 if (ret) 5310 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5311 5312 if (!locked) 5313 spin_unlock_bh(&hdev->fd_rule_lock); 5314 } 5315 5316 static int hclge_fd_check_user_def_refcnt(struct hclge_dev *hdev, 5317 struct hclge_fd_rule *rule) 5318 { 5319 struct hlist_head *hlist = &hdev->fd_rule_list; 5320 struct hclge_fd_rule *fd_rule, *parent = NULL; 5321 struct hclge_fd_user_def_info *info, *old_info; 5322 struct hclge_fd_user_def_cfg *cfg; 5323 5324 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5325 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5326 return 0; 5327 5328 /* for valid layer is start from 1, so need minus 1 to get the cfg */ 5329 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5330 info = &rule->ep.user_def; 5331 5332 if (!cfg->ref_cnt || cfg->offset == info->offset) 5333 return 0; 5334 5335 if (cfg->ref_cnt > 1) 5336 goto error; 5337 5338 fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent); 5339 if (fd_rule) { 5340 old_info = &fd_rule->ep.user_def; 5341 if (info->layer == old_info->layer) 5342 return 0; 5343 } 5344 5345 error: 5346 dev_err(&hdev->pdev->dev, 5347 "No available offset for layer%d fd rule, each layer only support one user def offset.\n", 5348 info->layer + 1); 5349 return -ENOSPC; 5350 } 5351 5352 static void hclge_fd_inc_user_def_refcnt(struct hclge_dev *hdev, 5353 struct hclge_fd_rule *rule) 5354 { 5355 struct hclge_fd_user_def_cfg *cfg; 5356 5357 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5358 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5359 return; 5360 5361 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5362 if (!cfg->ref_cnt) { 5363 cfg->offset = rule->ep.user_def.offset; 5364 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5365 } 5366 cfg->ref_cnt++; 5367 } 5368 5369 static void hclge_fd_dec_user_def_refcnt(struct hclge_dev *hdev, 5370 struct hclge_fd_rule *rule) 5371 { 5372 struct hclge_fd_user_def_cfg *cfg; 5373 5374 if (!rule || rule->rule_type != HCLGE_FD_EP_ACTIVE || 5375 rule->ep.user_def.layer == HCLGE_FD_USER_DEF_NONE) 5376 return; 5377 5378 cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1]; 5379 if (!cfg->ref_cnt) 5380 return; 5381 5382 cfg->ref_cnt--; 5383 if (!cfg->ref_cnt) { 5384 cfg->offset = 0; 5385 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 5386 } 5387 } 5388 5389 static void hclge_update_fd_list(struct hclge_dev *hdev, 5390 enum HCLGE_FD_NODE_STATE state, u16 location, 5391 struct hclge_fd_rule *new_rule) 5392 { 5393 struct hlist_head *hlist = &hdev->fd_rule_list; 5394 struct hclge_fd_rule *fd_rule, *parent = NULL; 5395 5396 fd_rule = hclge_find_fd_rule(hlist, location, &parent); 5397 if (fd_rule) { 5398 hclge_fd_dec_user_def_refcnt(hdev, fd_rule); 5399 if (state == HCLGE_FD_ACTIVE) 5400 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5401 hclge_sync_fd_user_def_cfg(hdev, true); 5402 5403 hclge_update_fd_rule_node(hdev, fd_rule, new_rule, state); 5404 return; 5405 } 5406 5407 /* it's unlikely to fail here, because we have checked the rule 5408 * exist before. 5409 */ 5410 if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) { 5411 dev_warn(&hdev->pdev->dev, 5412 "failed to delete fd rule %u, it's inexistent\n", 5413 location); 5414 return; 5415 } 5416 5417 hclge_fd_inc_user_def_refcnt(hdev, new_rule); 5418 hclge_sync_fd_user_def_cfg(hdev, true); 5419 5420 hclge_fd_insert_rule_node(hlist, new_rule, parent); 5421 hclge_fd_inc_rule_cnt(hdev, new_rule->location); 5422 5423 if (state == HCLGE_FD_TO_ADD) { 5424 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 5425 hclge_task_schedule(hdev, 0); 5426 } 5427 } 5428 5429 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode) 5430 { 5431 struct hclge_get_fd_mode_cmd *req; 5432 struct hclge_desc desc; 5433 int ret; 5434 5435 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true); 5436 5437 req = (struct hclge_get_fd_mode_cmd *)desc.data; 5438 5439 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5440 if (ret) { 5441 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret); 5442 return ret; 5443 } 5444 5445 *fd_mode = req->mode; 5446 5447 return ret; 5448 } 5449 5450 static int hclge_get_fd_allocation(struct hclge_dev *hdev, 5451 u32 *stage1_entry_num, 5452 u32 *stage2_entry_num, 5453 u16 *stage1_counter_num, 5454 u16 *stage2_counter_num) 5455 { 5456 struct hclge_get_fd_allocation_cmd *req; 5457 struct hclge_desc desc; 5458 int ret; 5459 5460 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true); 5461 5462 req = (struct hclge_get_fd_allocation_cmd *)desc.data; 5463 5464 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5465 if (ret) { 5466 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n", 5467 ret); 5468 return ret; 5469 } 5470 5471 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num); 5472 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num); 5473 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num); 5474 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num); 5475 5476 return ret; 5477 } 5478 5479 static int hclge_set_fd_key_config(struct hclge_dev *hdev, 5480 enum HCLGE_FD_STAGE stage_num) 5481 { 5482 struct hclge_set_fd_key_config_cmd *req; 5483 struct hclge_fd_key_cfg *stage; 5484 struct hclge_desc desc; 5485 int ret; 5486 5487 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false); 5488 5489 req = (struct hclge_set_fd_key_config_cmd *)desc.data; 5490 stage = &hdev->fd_cfg.key_cfg[stage_num]; 5491 req->stage = stage_num; 5492 req->key_select = stage->key_sel; 5493 req->inner_sipv6_word_en = stage->inner_sipv6_word_en; 5494 req->inner_dipv6_word_en = stage->inner_dipv6_word_en; 5495 req->outer_sipv6_word_en = stage->outer_sipv6_word_en; 5496 req->outer_dipv6_word_en = stage->outer_dipv6_word_en; 5497 req->tuple_mask = cpu_to_le32(~stage->tuple_active); 5498 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active); 5499 5500 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5501 if (ret) 5502 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret); 5503 5504 return ret; 5505 } 5506 5507 static void hclge_fd_disable_user_def(struct hclge_dev *hdev) 5508 { 5509 struct hclge_fd_user_def_cfg *cfg = hdev->fd_cfg.user_def_cfg; 5510 5511 spin_lock_bh(&hdev->fd_rule_lock); 5512 memset(cfg, 0, sizeof(hdev->fd_cfg.user_def_cfg)); 5513 spin_unlock_bh(&hdev->fd_rule_lock); 5514 5515 hclge_fd_set_user_def_cmd(hdev, cfg); 5516 } 5517 5518 static int hclge_init_fd_config(struct hclge_dev *hdev) 5519 { 5520 #define LOW_2_WORDS 0x03 5521 struct hclge_fd_key_cfg *key_cfg; 5522 int ret; 5523 5524 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 5525 return 0; 5526 5527 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode); 5528 if (ret) 5529 return ret; 5530 5531 switch (hdev->fd_cfg.fd_mode) { 5532 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1: 5533 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH; 5534 break; 5535 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1: 5536 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2; 5537 break; 5538 default: 5539 dev_err(&hdev->pdev->dev, 5540 "Unsupported flow director mode %u\n", 5541 hdev->fd_cfg.fd_mode); 5542 return -EOPNOTSUPP; 5543 } 5544 5545 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1]; 5546 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE; 5547 key_cfg->inner_sipv6_word_en = LOW_2_WORDS; 5548 key_cfg->inner_dipv6_word_en = LOW_2_WORDS; 5549 key_cfg->outer_sipv6_word_en = 0; 5550 key_cfg->outer_dipv6_word_en = 0; 5551 5552 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) | 5553 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) | 5554 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 5555 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5556 5557 /* If use max 400bit key, we can support tuples for ether type */ 5558 if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 5559 key_cfg->tuple_active |= 5560 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC); 5561 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5562 key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 5563 } 5564 5565 /* roce_type is used to filter roce frames 5566 * dst_vport is used to specify the rule 5567 */ 5568 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT); 5569 5570 ret = hclge_get_fd_allocation(hdev, 5571 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1], 5572 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2], 5573 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1], 5574 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]); 5575 if (ret) 5576 return ret; 5577 5578 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1); 5579 } 5580 5581 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x, 5582 int loc, u8 *key, bool is_add) 5583 { 5584 struct hclge_fd_tcam_config_1_cmd *req1; 5585 struct hclge_fd_tcam_config_2_cmd *req2; 5586 struct hclge_fd_tcam_config_3_cmd *req3; 5587 struct hclge_desc desc[3]; 5588 int ret; 5589 5590 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false); 5591 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5592 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false); 5593 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 5594 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false); 5595 5596 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 5597 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 5598 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 5599 5600 req1->stage = stage; 5601 req1->xy_sel = sel_x ? 1 : 0; 5602 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0); 5603 req1->index = cpu_to_le32(loc); 5604 req1->entry_vld = sel_x ? is_add : 0; 5605 5606 if (key) { 5607 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data)); 5608 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)], 5609 sizeof(req2->tcam_data)); 5610 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) + 5611 sizeof(req2->tcam_data)], sizeof(req3->tcam_data)); 5612 } 5613 5614 ret = hclge_cmd_send(&hdev->hw, desc, 3); 5615 if (ret) 5616 dev_err(&hdev->pdev->dev, 5617 "config tcam key fail, ret=%d\n", 5618 ret); 5619 5620 return ret; 5621 } 5622 5623 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc, 5624 struct hclge_fd_ad_data *action) 5625 { 5626 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 5627 struct hclge_fd_ad_config_cmd *req; 5628 struct hclge_desc desc; 5629 u64 ad_data = 0; 5630 int ret; 5631 5632 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false); 5633 5634 req = (struct hclge_fd_ad_config_cmd *)desc.data; 5635 req->index = cpu_to_le32(loc); 5636 req->stage = stage; 5637 5638 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B, 5639 action->write_rule_id_to_bd); 5640 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S, 5641 action->rule_id); 5642 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) { 5643 hnae3_set_bit(ad_data, HCLGE_FD_AD_TC_OVRD_B, 5644 action->override_tc); 5645 hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M, 5646 HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size); 5647 } 5648 ad_data <<= 32; 5649 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet); 5650 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B, 5651 action->forward_to_direct_queue); 5652 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S, 5653 action->queue_id); 5654 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter); 5655 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M, 5656 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id); 5657 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage); 5658 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S, 5659 action->counter_id); 5660 5661 req->ad_data = cpu_to_le64(ad_data); 5662 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5663 if (ret) 5664 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret); 5665 5666 return ret; 5667 } 5668 5669 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y, 5670 struct hclge_fd_rule *rule) 5671 { 5672 int offset, moffset, ip_offset; 5673 enum HCLGE_FD_KEY_OPT key_opt; 5674 u16 tmp_x_s, tmp_y_s; 5675 u32 tmp_x_l, tmp_y_l; 5676 u8 *p = (u8 *)rule; 5677 int i; 5678 5679 if (rule->unused_tuple & BIT(tuple_bit)) 5680 return true; 5681 5682 key_opt = tuple_key_info[tuple_bit].key_opt; 5683 offset = tuple_key_info[tuple_bit].offset; 5684 moffset = tuple_key_info[tuple_bit].moffset; 5685 5686 switch (key_opt) { 5687 case KEY_OPT_U8: 5688 calc_x(*key_x, p[offset], p[moffset]); 5689 calc_y(*key_y, p[offset], p[moffset]); 5690 5691 return true; 5692 case KEY_OPT_LE16: 5693 calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5694 calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset])); 5695 *(__le16 *)key_x = cpu_to_le16(tmp_x_s); 5696 *(__le16 *)key_y = cpu_to_le16(tmp_y_s); 5697 5698 return true; 5699 case KEY_OPT_LE32: 5700 calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5701 calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset])); 5702 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5703 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5704 5705 return true; 5706 case KEY_OPT_MAC: 5707 for (i = 0; i < ETH_ALEN; i++) { 5708 calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i], 5709 p[moffset + i]); 5710 calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i], 5711 p[moffset + i]); 5712 } 5713 5714 return true; 5715 case KEY_OPT_IP: 5716 ip_offset = IPV4_INDEX * sizeof(u32); 5717 calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]), 5718 *(u32 *)(&p[moffset + ip_offset])); 5719 calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]), 5720 *(u32 *)(&p[moffset + ip_offset])); 5721 *(__le32 *)key_x = cpu_to_le32(tmp_x_l); 5722 *(__le32 *)key_y = cpu_to_le32(tmp_y_l); 5723 5724 return true; 5725 default: 5726 return false; 5727 } 5728 } 5729 5730 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 5731 u8 vf_id, u8 network_port_id) 5732 { 5733 u32 port_number = 0; 5734 5735 if (port_type == HOST_PORT) { 5736 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S, 5737 pf_id); 5738 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S, 5739 vf_id); 5740 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT); 5741 } else { 5742 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M, 5743 HCLGE_NETWORK_PORT_ID_S, network_port_id); 5744 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT); 5745 } 5746 5747 return port_number; 5748 } 5749 5750 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg, 5751 __le32 *key_x, __le32 *key_y, 5752 struct hclge_fd_rule *rule) 5753 { 5754 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number; 5755 u8 cur_pos = 0, tuple_size, shift_bits; 5756 unsigned int i; 5757 5758 for (i = 0; i < MAX_META_DATA; i++) { 5759 tuple_size = meta_data_key_info[i].key_length; 5760 tuple_bit = key_cfg->meta_data_active & BIT(i); 5761 5762 switch (tuple_bit) { 5763 case BIT(ROCE_TYPE): 5764 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET); 5765 cur_pos += tuple_size; 5766 break; 5767 case BIT(DST_VPORT): 5768 port_number = hclge_get_port_number(HOST_PORT, 0, 5769 rule->vf_id, 0); 5770 hnae3_set_field(meta_data, 5771 GENMASK(cur_pos + tuple_size, cur_pos), 5772 cur_pos, port_number); 5773 cur_pos += tuple_size; 5774 break; 5775 default: 5776 break; 5777 } 5778 } 5779 5780 calc_x(tmp_x, meta_data, 0xFFFFFFFF); 5781 calc_y(tmp_y, meta_data, 0xFFFFFFFF); 5782 shift_bits = sizeof(meta_data) * 8 - cur_pos; 5783 5784 *key_x = cpu_to_le32(tmp_x << shift_bits); 5785 *key_y = cpu_to_le32(tmp_y << shift_bits); 5786 } 5787 5788 /* A complete key is combined with meta data key and tuple key. 5789 * Meta data key is stored at the MSB region, and tuple key is stored at 5790 * the LSB region, unused bits will be filled 0. 5791 */ 5792 static int hclge_config_key(struct hclge_dev *hdev, u8 stage, 5793 struct hclge_fd_rule *rule) 5794 { 5795 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage]; 5796 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES]; 5797 u8 *cur_key_x, *cur_key_y; 5798 u8 meta_data_region; 5799 u8 tuple_size; 5800 int ret; 5801 u32 i; 5802 5803 memset(key_x, 0, sizeof(key_x)); 5804 memset(key_y, 0, sizeof(key_y)); 5805 cur_key_x = key_x; 5806 cur_key_y = key_y; 5807 5808 for (i = 0; i < MAX_TUPLE; i++) { 5809 bool tuple_valid; 5810 5811 tuple_size = tuple_key_info[i].key_length / 8; 5812 if (!(key_cfg->tuple_active & BIT(i))) 5813 continue; 5814 5815 tuple_valid = hclge_fd_convert_tuple(i, cur_key_x, 5816 cur_key_y, rule); 5817 if (tuple_valid) { 5818 cur_key_x += tuple_size; 5819 cur_key_y += tuple_size; 5820 } 5821 } 5822 5823 meta_data_region = hdev->fd_cfg.max_key_length / 8 - 5824 MAX_META_DATA_LENGTH / 8; 5825 5826 hclge_fd_convert_meta_data(key_cfg, 5827 (__le32 *)(key_x + meta_data_region), 5828 (__le32 *)(key_y + meta_data_region), 5829 rule); 5830 5831 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y, 5832 true); 5833 if (ret) { 5834 dev_err(&hdev->pdev->dev, 5835 "fd key_y config fail, loc=%u, ret=%d\n", 5836 rule->queue_id, ret); 5837 return ret; 5838 } 5839 5840 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x, 5841 true); 5842 if (ret) 5843 dev_err(&hdev->pdev->dev, 5844 "fd key_x config fail, loc=%u, ret=%d\n", 5845 rule->queue_id, ret); 5846 return ret; 5847 } 5848 5849 static int hclge_config_action(struct hclge_dev *hdev, u8 stage, 5850 struct hclge_fd_rule *rule) 5851 { 5852 struct hclge_vport *vport = hdev->vport; 5853 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 5854 struct hclge_fd_ad_data ad_data; 5855 5856 memset(&ad_data, 0, sizeof(struct hclge_fd_ad_data)); 5857 ad_data.ad_id = rule->location; 5858 5859 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 5860 ad_data.drop_packet = true; 5861 } else if (rule->action == HCLGE_FD_ACTION_SELECT_TC) { 5862 ad_data.override_tc = true; 5863 ad_data.queue_id = 5864 kinfo->tc_info.tqp_offset[rule->cls_flower.tc]; 5865 ad_data.tc_size = 5866 ilog2(kinfo->tc_info.tqp_count[rule->cls_flower.tc]); 5867 } else { 5868 ad_data.forward_to_direct_queue = true; 5869 ad_data.queue_id = rule->queue_id; 5870 } 5871 5872 if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) { 5873 ad_data.use_counter = true; 5874 ad_data.counter_id = rule->vf_id % 5875 hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]; 5876 } else { 5877 ad_data.use_counter = false; 5878 ad_data.counter_id = 0; 5879 } 5880 5881 ad_data.use_next_stage = false; 5882 ad_data.next_input_key = 0; 5883 5884 ad_data.write_rule_id_to_bd = true; 5885 ad_data.rule_id = rule->location; 5886 5887 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data); 5888 } 5889 5890 static int hclge_fd_check_tcpip4_tuple(struct ethtool_tcpip4_spec *spec, 5891 u32 *unused_tuple) 5892 { 5893 if (!spec || !unused_tuple) 5894 return -EINVAL; 5895 5896 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5897 5898 if (!spec->ip4src) 5899 *unused_tuple |= BIT(INNER_SRC_IP); 5900 5901 if (!spec->ip4dst) 5902 *unused_tuple |= BIT(INNER_DST_IP); 5903 5904 if (!spec->psrc) 5905 *unused_tuple |= BIT(INNER_SRC_PORT); 5906 5907 if (!spec->pdst) 5908 *unused_tuple |= BIT(INNER_DST_PORT); 5909 5910 if (!spec->tos) 5911 *unused_tuple |= BIT(INNER_IP_TOS); 5912 5913 return 0; 5914 } 5915 5916 static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec, 5917 u32 *unused_tuple) 5918 { 5919 if (!spec || !unused_tuple) 5920 return -EINVAL; 5921 5922 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5923 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5924 5925 if (!spec->ip4src) 5926 *unused_tuple |= BIT(INNER_SRC_IP); 5927 5928 if (!spec->ip4dst) 5929 *unused_tuple |= BIT(INNER_DST_IP); 5930 5931 if (!spec->tos) 5932 *unused_tuple |= BIT(INNER_IP_TOS); 5933 5934 if (!spec->proto) 5935 *unused_tuple |= BIT(INNER_IP_PROTO); 5936 5937 if (spec->l4_4_bytes) 5938 return -EOPNOTSUPP; 5939 5940 if (spec->ip_ver != ETH_RX_NFC_IP4) 5941 return -EOPNOTSUPP; 5942 5943 return 0; 5944 } 5945 5946 static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec, 5947 u32 *unused_tuple) 5948 { 5949 if (!spec || !unused_tuple) 5950 return -EINVAL; 5951 5952 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC); 5953 5954 /* check whether src/dst ip address used */ 5955 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5956 *unused_tuple |= BIT(INNER_SRC_IP); 5957 5958 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5959 *unused_tuple |= BIT(INNER_DST_IP); 5960 5961 if (!spec->psrc) 5962 *unused_tuple |= BIT(INNER_SRC_PORT); 5963 5964 if (!spec->pdst) 5965 *unused_tuple |= BIT(INNER_DST_PORT); 5966 5967 if (!spec->tclass) 5968 *unused_tuple |= BIT(INNER_IP_TOS); 5969 5970 return 0; 5971 } 5972 5973 static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec, 5974 u32 *unused_tuple) 5975 { 5976 if (!spec || !unused_tuple) 5977 return -EINVAL; 5978 5979 *unused_tuple |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 5980 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT); 5981 5982 /* check whether src/dst ip address used */ 5983 if (ipv6_addr_any((struct in6_addr *)spec->ip6src)) 5984 *unused_tuple |= BIT(INNER_SRC_IP); 5985 5986 if (ipv6_addr_any((struct in6_addr *)spec->ip6dst)) 5987 *unused_tuple |= BIT(INNER_DST_IP); 5988 5989 if (!spec->l4_proto) 5990 *unused_tuple |= BIT(INNER_IP_PROTO); 5991 5992 if (!spec->tclass) 5993 *unused_tuple |= BIT(INNER_IP_TOS); 5994 5995 if (spec->l4_4_bytes) 5996 return -EOPNOTSUPP; 5997 5998 return 0; 5999 } 6000 6001 static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple) 6002 { 6003 if (!spec || !unused_tuple) 6004 return -EINVAL; 6005 6006 *unused_tuple |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) | 6007 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) | 6008 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO); 6009 6010 if (is_zero_ether_addr(spec->h_source)) 6011 *unused_tuple |= BIT(INNER_SRC_MAC); 6012 6013 if (is_zero_ether_addr(spec->h_dest)) 6014 *unused_tuple |= BIT(INNER_DST_MAC); 6015 6016 if (!spec->h_proto) 6017 *unused_tuple |= BIT(INNER_ETH_TYPE); 6018 6019 return 0; 6020 } 6021 6022 static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev, 6023 struct ethtool_rx_flow_spec *fs, 6024 u32 *unused_tuple) 6025 { 6026 if (fs->flow_type & FLOW_EXT) { 6027 if (fs->h_ext.vlan_etype) { 6028 dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n"); 6029 return -EOPNOTSUPP; 6030 } 6031 6032 if (!fs->h_ext.vlan_tci) 6033 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6034 6035 if (fs->m_ext.vlan_tci && 6036 be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) { 6037 dev_err(&hdev->pdev->dev, 6038 "failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n", 6039 ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1); 6040 return -EINVAL; 6041 } 6042 } else { 6043 *unused_tuple |= BIT(INNER_VLAN_TAG_FST); 6044 } 6045 6046 if (fs->flow_type & FLOW_MAC_EXT) { 6047 if (hdev->fd_cfg.fd_mode != 6048 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6049 dev_err(&hdev->pdev->dev, 6050 "FLOW_MAC_EXT is not supported in current fd mode!\n"); 6051 return -EOPNOTSUPP; 6052 } 6053 6054 if (is_zero_ether_addr(fs->h_ext.h_dest)) 6055 *unused_tuple |= BIT(INNER_DST_MAC); 6056 else 6057 *unused_tuple &= ~BIT(INNER_DST_MAC); 6058 } 6059 6060 return 0; 6061 } 6062 6063 static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple, 6064 struct hclge_fd_user_def_info *info) 6065 { 6066 switch (flow_type) { 6067 case ETHER_FLOW: 6068 info->layer = HCLGE_FD_USER_DEF_L2; 6069 *unused_tuple &= ~BIT(INNER_L2_RSV); 6070 break; 6071 case IP_USER_FLOW: 6072 case IPV6_USER_FLOW: 6073 info->layer = HCLGE_FD_USER_DEF_L3; 6074 *unused_tuple &= ~BIT(INNER_L3_RSV); 6075 break; 6076 case TCP_V4_FLOW: 6077 case UDP_V4_FLOW: 6078 case TCP_V6_FLOW: 6079 case UDP_V6_FLOW: 6080 info->layer = HCLGE_FD_USER_DEF_L4; 6081 *unused_tuple &= ~BIT(INNER_L4_RSV); 6082 break; 6083 default: 6084 return -EOPNOTSUPP; 6085 } 6086 6087 return 0; 6088 } 6089 6090 static bool hclge_fd_is_user_def_all_masked(struct ethtool_rx_flow_spec *fs) 6091 { 6092 return be32_to_cpu(fs->m_ext.data[1] | fs->m_ext.data[0]) == 0; 6093 } 6094 6095 static int hclge_fd_parse_user_def_field(struct hclge_dev *hdev, 6096 struct ethtool_rx_flow_spec *fs, 6097 u32 *unused_tuple, 6098 struct hclge_fd_user_def_info *info) 6099 { 6100 u32 tuple_active = hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1].tuple_active; 6101 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6102 u16 data, offset, data_mask, offset_mask; 6103 int ret; 6104 6105 info->layer = HCLGE_FD_USER_DEF_NONE; 6106 *unused_tuple |= HCLGE_FD_TUPLE_USER_DEF_TUPLES; 6107 6108 if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs)) 6109 return 0; 6110 6111 /* user-def data from ethtool is 64 bit value, the bit0~15 is used 6112 * for data, and bit32~47 is used for offset. 6113 */ 6114 data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6115 data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA; 6116 offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6117 offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6118 6119 if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) { 6120 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n"); 6121 return -EOPNOTSUPP; 6122 } 6123 6124 if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) { 6125 dev_err(&hdev->pdev->dev, 6126 "user-def offset[%u] should be no more than %u\n", 6127 offset, HCLGE_FD_MAX_USER_DEF_OFFSET); 6128 return -EINVAL; 6129 } 6130 6131 if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) { 6132 dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n"); 6133 return -EINVAL; 6134 } 6135 6136 ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info); 6137 if (ret) { 6138 dev_err(&hdev->pdev->dev, 6139 "unsupported flow type for user-def bytes, ret = %d\n", 6140 ret); 6141 return ret; 6142 } 6143 6144 info->data = data; 6145 info->data_mask = data_mask; 6146 info->offset = offset; 6147 6148 return 0; 6149 } 6150 6151 static int hclge_fd_check_spec(struct hclge_dev *hdev, 6152 struct ethtool_rx_flow_spec *fs, 6153 u32 *unused_tuple, 6154 struct hclge_fd_user_def_info *info) 6155 { 6156 u32 flow_type; 6157 int ret; 6158 6159 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 6160 dev_err(&hdev->pdev->dev, 6161 "failed to config fd rules, invalid rule location: %u, max is %u\n.", 6162 fs->location, 6163 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1); 6164 return -EINVAL; 6165 } 6166 6167 ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info); 6168 if (ret) 6169 return ret; 6170 6171 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6172 switch (flow_type) { 6173 case SCTP_V4_FLOW: 6174 case TCP_V4_FLOW: 6175 case UDP_V4_FLOW: 6176 ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec, 6177 unused_tuple); 6178 break; 6179 case IP_USER_FLOW: 6180 ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec, 6181 unused_tuple); 6182 break; 6183 case SCTP_V6_FLOW: 6184 case TCP_V6_FLOW: 6185 case UDP_V6_FLOW: 6186 ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec, 6187 unused_tuple); 6188 break; 6189 case IPV6_USER_FLOW: 6190 ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec, 6191 unused_tuple); 6192 break; 6193 case ETHER_FLOW: 6194 if (hdev->fd_cfg.fd_mode != 6195 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) { 6196 dev_err(&hdev->pdev->dev, 6197 "ETHER_FLOW is not supported in current fd mode!\n"); 6198 return -EOPNOTSUPP; 6199 } 6200 6201 ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec, 6202 unused_tuple); 6203 break; 6204 default: 6205 dev_err(&hdev->pdev->dev, 6206 "unsupported protocol type, protocol type = %#x\n", 6207 flow_type); 6208 return -EOPNOTSUPP; 6209 } 6210 6211 if (ret) { 6212 dev_err(&hdev->pdev->dev, 6213 "failed to check flow union tuple, ret = %d\n", 6214 ret); 6215 return ret; 6216 } 6217 6218 return hclge_fd_check_ext_tuple(hdev, fs, unused_tuple); 6219 } 6220 6221 static void hclge_fd_get_tcpip4_tuple(struct hclge_dev *hdev, 6222 struct ethtool_rx_flow_spec *fs, 6223 struct hclge_fd_rule *rule, u8 ip_proto) 6224 { 6225 rule->tuples.src_ip[IPV4_INDEX] = 6226 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src); 6227 rule->tuples_mask.src_ip[IPV4_INDEX] = 6228 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src); 6229 6230 rule->tuples.dst_ip[IPV4_INDEX] = 6231 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst); 6232 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6233 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst); 6234 6235 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc); 6236 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc); 6237 6238 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst); 6239 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst); 6240 6241 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos; 6242 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos; 6243 6244 rule->tuples.ether_proto = ETH_P_IP; 6245 rule->tuples_mask.ether_proto = 0xFFFF; 6246 6247 rule->tuples.ip_proto = ip_proto; 6248 rule->tuples_mask.ip_proto = 0xFF; 6249 } 6250 6251 static void hclge_fd_get_ip4_tuple(struct hclge_dev *hdev, 6252 struct ethtool_rx_flow_spec *fs, 6253 struct hclge_fd_rule *rule) 6254 { 6255 rule->tuples.src_ip[IPV4_INDEX] = 6256 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src); 6257 rule->tuples_mask.src_ip[IPV4_INDEX] = 6258 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src); 6259 6260 rule->tuples.dst_ip[IPV4_INDEX] = 6261 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst); 6262 rule->tuples_mask.dst_ip[IPV4_INDEX] = 6263 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst); 6264 6265 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos; 6266 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos; 6267 6268 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto; 6269 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto; 6270 6271 rule->tuples.ether_proto = ETH_P_IP; 6272 rule->tuples_mask.ether_proto = 0xFFFF; 6273 } 6274 6275 static void hclge_fd_get_tcpip6_tuple(struct hclge_dev *hdev, 6276 struct ethtool_rx_flow_spec *fs, 6277 struct hclge_fd_rule *rule, u8 ip_proto) 6278 { 6279 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.tcp_ip6_spec.ip6src, 6280 IPV6_SIZE); 6281 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.tcp_ip6_spec.ip6src, 6282 IPV6_SIZE); 6283 6284 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.tcp_ip6_spec.ip6dst, 6285 IPV6_SIZE); 6286 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.tcp_ip6_spec.ip6dst, 6287 IPV6_SIZE); 6288 6289 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc); 6290 rule->tuples_mask.src_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc); 6291 6292 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst); 6293 rule->tuples_mask.dst_port = be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst); 6294 6295 rule->tuples.ether_proto = ETH_P_IPV6; 6296 rule->tuples_mask.ether_proto = 0xFFFF; 6297 6298 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6299 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6300 6301 rule->tuples.ip_proto = ip_proto; 6302 rule->tuples_mask.ip_proto = 0xFF; 6303 } 6304 6305 static void hclge_fd_get_ip6_tuple(struct hclge_dev *hdev, 6306 struct ethtool_rx_flow_spec *fs, 6307 struct hclge_fd_rule *rule) 6308 { 6309 be32_to_cpu_array(rule->tuples.src_ip, fs->h_u.usr_ip6_spec.ip6src, 6310 IPV6_SIZE); 6311 be32_to_cpu_array(rule->tuples_mask.src_ip, fs->m_u.usr_ip6_spec.ip6src, 6312 IPV6_SIZE); 6313 6314 be32_to_cpu_array(rule->tuples.dst_ip, fs->h_u.usr_ip6_spec.ip6dst, 6315 IPV6_SIZE); 6316 be32_to_cpu_array(rule->tuples_mask.dst_ip, fs->m_u.usr_ip6_spec.ip6dst, 6317 IPV6_SIZE); 6318 6319 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto; 6320 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto; 6321 6322 rule->tuples.ip_tos = fs->h_u.tcp_ip6_spec.tclass; 6323 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip6_spec.tclass; 6324 6325 rule->tuples.ether_proto = ETH_P_IPV6; 6326 rule->tuples_mask.ether_proto = 0xFFFF; 6327 } 6328 6329 static void hclge_fd_get_ether_tuple(struct hclge_dev *hdev, 6330 struct ethtool_rx_flow_spec *fs, 6331 struct hclge_fd_rule *rule) 6332 { 6333 ether_addr_copy(rule->tuples.src_mac, fs->h_u.ether_spec.h_source); 6334 ether_addr_copy(rule->tuples_mask.src_mac, fs->m_u.ether_spec.h_source); 6335 6336 ether_addr_copy(rule->tuples.dst_mac, fs->h_u.ether_spec.h_dest); 6337 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_u.ether_spec.h_dest); 6338 6339 rule->tuples.ether_proto = be16_to_cpu(fs->h_u.ether_spec.h_proto); 6340 rule->tuples_mask.ether_proto = be16_to_cpu(fs->m_u.ether_spec.h_proto); 6341 } 6342 6343 static void hclge_fd_get_user_def_tuple(struct hclge_fd_user_def_info *info, 6344 struct hclge_fd_rule *rule) 6345 { 6346 switch (info->layer) { 6347 case HCLGE_FD_USER_DEF_L2: 6348 rule->tuples.l2_user_def = info->data; 6349 rule->tuples_mask.l2_user_def = info->data_mask; 6350 break; 6351 case HCLGE_FD_USER_DEF_L3: 6352 rule->tuples.l3_user_def = info->data; 6353 rule->tuples_mask.l3_user_def = info->data_mask; 6354 break; 6355 case HCLGE_FD_USER_DEF_L4: 6356 rule->tuples.l4_user_def = (u32)info->data << 16; 6357 rule->tuples_mask.l4_user_def = (u32)info->data_mask << 16; 6358 break; 6359 default: 6360 break; 6361 } 6362 6363 rule->ep.user_def = *info; 6364 } 6365 6366 static int hclge_fd_get_tuple(struct hclge_dev *hdev, 6367 struct ethtool_rx_flow_spec *fs, 6368 struct hclge_fd_rule *rule, 6369 struct hclge_fd_user_def_info *info) 6370 { 6371 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT); 6372 6373 switch (flow_type) { 6374 case SCTP_V4_FLOW: 6375 hclge_fd_get_tcpip4_tuple(hdev, fs, rule, IPPROTO_SCTP); 6376 break; 6377 case TCP_V4_FLOW: 6378 hclge_fd_get_tcpip4_tuple(hdev, fs, rule, IPPROTO_TCP); 6379 break; 6380 case UDP_V4_FLOW: 6381 hclge_fd_get_tcpip4_tuple(hdev, fs, rule, IPPROTO_UDP); 6382 break; 6383 case IP_USER_FLOW: 6384 hclge_fd_get_ip4_tuple(hdev, fs, rule); 6385 break; 6386 case SCTP_V6_FLOW: 6387 hclge_fd_get_tcpip6_tuple(hdev, fs, rule, IPPROTO_SCTP); 6388 break; 6389 case TCP_V6_FLOW: 6390 hclge_fd_get_tcpip6_tuple(hdev, fs, rule, IPPROTO_TCP); 6391 break; 6392 case UDP_V6_FLOW: 6393 hclge_fd_get_tcpip6_tuple(hdev, fs, rule, IPPROTO_UDP); 6394 break; 6395 case IPV6_USER_FLOW: 6396 hclge_fd_get_ip6_tuple(hdev, fs, rule); 6397 break; 6398 case ETHER_FLOW: 6399 hclge_fd_get_ether_tuple(hdev, fs, rule); 6400 break; 6401 default: 6402 return -EOPNOTSUPP; 6403 } 6404 6405 if (fs->flow_type & FLOW_EXT) { 6406 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci); 6407 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci); 6408 hclge_fd_get_user_def_tuple(info, rule); 6409 } 6410 6411 if (fs->flow_type & FLOW_MAC_EXT) { 6412 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest); 6413 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest); 6414 } 6415 6416 return 0; 6417 } 6418 6419 static int hclge_fd_config_rule(struct hclge_dev *hdev, 6420 struct hclge_fd_rule *rule) 6421 { 6422 int ret; 6423 6424 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule); 6425 if (ret) 6426 return ret; 6427 6428 return hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule); 6429 } 6430 6431 static int hclge_add_fd_entry_common(struct hclge_dev *hdev, 6432 struct hclge_fd_rule *rule) 6433 { 6434 int ret; 6435 6436 spin_lock_bh(&hdev->fd_rule_lock); 6437 6438 if (hdev->fd_active_type != rule->rule_type && 6439 (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6440 hdev->fd_active_type == HCLGE_FD_EP_ACTIVE)) { 6441 dev_err(&hdev->pdev->dev, 6442 "mode conflict(new type %d, active type %d), please delete existent rules first\n", 6443 rule->rule_type, hdev->fd_active_type); 6444 spin_unlock_bh(&hdev->fd_rule_lock); 6445 return -EINVAL; 6446 } 6447 6448 ret = hclge_fd_check_user_def_refcnt(hdev, rule); 6449 if (ret) 6450 goto out; 6451 6452 ret = hclge_clear_arfs_rules(hdev); 6453 if (ret) 6454 goto out; 6455 6456 ret = hclge_fd_config_rule(hdev, rule); 6457 if (ret) 6458 goto out; 6459 6460 rule->state = HCLGE_FD_ACTIVE; 6461 hdev->fd_active_type = rule->rule_type; 6462 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 6463 6464 out: 6465 spin_unlock_bh(&hdev->fd_rule_lock); 6466 return ret; 6467 } 6468 6469 static bool hclge_is_cls_flower_active(struct hnae3_handle *handle) 6470 { 6471 struct hclge_vport *vport = hclge_get_vport(handle); 6472 struct hclge_dev *hdev = vport->back; 6473 6474 return hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE; 6475 } 6476 6477 static int hclge_fd_parse_ring_cookie(struct hclge_dev *hdev, u64 ring_cookie, 6478 u16 *vport_id, u8 *action, u16 *queue_id) 6479 { 6480 struct hclge_vport *vport = hdev->vport; 6481 6482 if (ring_cookie == RX_CLS_FLOW_DISC) { 6483 *action = HCLGE_FD_ACTION_DROP_PACKET; 6484 } else { 6485 u32 ring = ethtool_get_flow_spec_ring(ring_cookie); 6486 u8 vf = ethtool_get_flow_spec_ring_vf(ring_cookie); 6487 u16 tqps; 6488 6489 /* To keep consistent with user's configuration, minus 1 when 6490 * printing 'vf', because vf id from ethtool is added 1 for vf. 6491 */ 6492 if (vf > hdev->num_req_vfs) { 6493 dev_err(&hdev->pdev->dev, 6494 "Error: vf id (%u) should be less than %u\n", 6495 vf - 1U, hdev->num_req_vfs); 6496 return -EINVAL; 6497 } 6498 6499 *vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id; 6500 tqps = hdev->vport[vf].nic.kinfo.num_tqps; 6501 6502 if (ring >= tqps) { 6503 dev_err(&hdev->pdev->dev, 6504 "Error: queue id (%u) > max tqp num (%u)\n", 6505 ring, tqps - 1U); 6506 return -EINVAL; 6507 } 6508 6509 *action = HCLGE_FD_ACTION_SELECT_QUEUE; 6510 *queue_id = ring; 6511 } 6512 6513 return 0; 6514 } 6515 6516 static int hclge_add_fd_entry(struct hnae3_handle *handle, 6517 struct ethtool_rxnfc *cmd) 6518 { 6519 struct hclge_vport *vport = hclge_get_vport(handle); 6520 struct hclge_dev *hdev = vport->back; 6521 struct hclge_fd_user_def_info info; 6522 u16 dst_vport_id = 0, q_index = 0; 6523 struct ethtool_rx_flow_spec *fs; 6524 struct hclge_fd_rule *rule; 6525 u32 unused = 0; 6526 u8 action; 6527 int ret; 6528 6529 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 6530 dev_err(&hdev->pdev->dev, 6531 "flow table director is not supported\n"); 6532 return -EOPNOTSUPP; 6533 } 6534 6535 if (!hdev->fd_en) { 6536 dev_err(&hdev->pdev->dev, 6537 "please enable flow director first\n"); 6538 return -EOPNOTSUPP; 6539 } 6540 6541 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6542 6543 ret = hclge_fd_check_spec(hdev, fs, &unused, &info); 6544 if (ret) 6545 return ret; 6546 6547 ret = hclge_fd_parse_ring_cookie(hdev, fs->ring_cookie, &dst_vport_id, 6548 &action, &q_index); 6549 if (ret) 6550 return ret; 6551 6552 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 6553 if (!rule) 6554 return -ENOMEM; 6555 6556 ret = hclge_fd_get_tuple(hdev, fs, rule, &info); 6557 if (ret) { 6558 kfree(rule); 6559 return ret; 6560 } 6561 6562 rule->flow_type = fs->flow_type; 6563 rule->location = fs->location; 6564 rule->unused_tuple = unused; 6565 rule->vf_id = dst_vport_id; 6566 rule->queue_id = q_index; 6567 rule->action = action; 6568 rule->rule_type = HCLGE_FD_EP_ACTIVE; 6569 6570 ret = hclge_add_fd_entry_common(hdev, rule); 6571 if (ret) 6572 kfree(rule); 6573 6574 return ret; 6575 } 6576 6577 static int hclge_del_fd_entry(struct hnae3_handle *handle, 6578 struct ethtool_rxnfc *cmd) 6579 { 6580 struct hclge_vport *vport = hclge_get_vport(handle); 6581 struct hclge_dev *hdev = vport->back; 6582 struct ethtool_rx_flow_spec *fs; 6583 int ret; 6584 6585 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6586 return -EOPNOTSUPP; 6587 6588 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6589 6590 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6591 return -EINVAL; 6592 6593 spin_lock_bh(&hdev->fd_rule_lock); 6594 if (hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE || 6595 !test_bit(fs->location, hdev->fd_bmap)) { 6596 dev_err(&hdev->pdev->dev, 6597 "Delete fail, rule %u is inexistent\n", fs->location); 6598 spin_unlock_bh(&hdev->fd_rule_lock); 6599 return -ENOENT; 6600 } 6601 6602 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, fs->location, 6603 NULL, false); 6604 if (ret) 6605 goto out; 6606 6607 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, fs->location, NULL); 6608 6609 out: 6610 spin_unlock_bh(&hdev->fd_rule_lock); 6611 return ret; 6612 } 6613 6614 static void hclge_clear_fd_rules_in_list(struct hclge_dev *hdev, 6615 bool clear_list) 6616 { 6617 struct hclge_fd_rule *rule; 6618 struct hlist_node *node; 6619 u16 location; 6620 6621 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6622 return; 6623 6624 spin_lock_bh(&hdev->fd_rule_lock); 6625 6626 for_each_set_bit(location, hdev->fd_bmap, 6627 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) 6628 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, location, 6629 NULL, false); 6630 6631 if (clear_list) { 6632 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, 6633 rule_node) { 6634 hlist_del(&rule->rule_node); 6635 kfree(rule); 6636 } 6637 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 6638 hdev->hclge_fd_rule_num = 0; 6639 bitmap_zero(hdev->fd_bmap, 6640 hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 6641 } 6642 6643 spin_unlock_bh(&hdev->fd_rule_lock); 6644 } 6645 6646 static void hclge_del_all_fd_entries(struct hclge_dev *hdev) 6647 { 6648 hclge_clear_fd_rules_in_list(hdev, true); 6649 hclge_fd_disable_user_def(hdev); 6650 } 6651 6652 static int hclge_restore_fd_entries(struct hnae3_handle *handle) 6653 { 6654 struct hclge_vport *vport = hclge_get_vport(handle); 6655 struct hclge_dev *hdev = vport->back; 6656 struct hclge_fd_rule *rule; 6657 struct hlist_node *node; 6658 6659 /* Return ok here, because reset error handling will check this 6660 * return value. If error is returned here, the reset process will 6661 * fail. 6662 */ 6663 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6664 return 0; 6665 6666 /* if fd is disabled, should not restore it when reset */ 6667 if (!hdev->fd_en) 6668 return 0; 6669 6670 spin_lock_bh(&hdev->fd_rule_lock); 6671 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 6672 if (rule->state == HCLGE_FD_ACTIVE) 6673 rule->state = HCLGE_FD_TO_ADD; 6674 } 6675 spin_unlock_bh(&hdev->fd_rule_lock); 6676 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 6677 6678 return 0; 6679 } 6680 6681 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle, 6682 struct ethtool_rxnfc *cmd) 6683 { 6684 struct hclge_vport *vport = hclge_get_vport(handle); 6685 struct hclge_dev *hdev = vport->back; 6686 6687 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev) || hclge_is_cls_flower_active(handle)) 6688 return -EOPNOTSUPP; 6689 6690 cmd->rule_cnt = hdev->hclge_fd_rule_num; 6691 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6692 6693 return 0; 6694 } 6695 6696 static void hclge_fd_get_tcpip4_info(struct hclge_fd_rule *rule, 6697 struct ethtool_tcpip4_spec *spec, 6698 struct ethtool_tcpip4_spec *spec_mask) 6699 { 6700 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6701 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6702 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6703 6704 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6705 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6706 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6707 6708 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6709 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6710 0 : cpu_to_be16(rule->tuples_mask.src_port); 6711 6712 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6713 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6714 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6715 6716 spec->tos = rule->tuples.ip_tos; 6717 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6718 0 : rule->tuples_mask.ip_tos; 6719 } 6720 6721 static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule, 6722 struct ethtool_usrip4_spec *spec, 6723 struct ethtool_usrip4_spec *spec_mask) 6724 { 6725 spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]); 6726 spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 6727 0 : cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]); 6728 6729 spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]); 6730 spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 6731 0 : cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]); 6732 6733 spec->tos = rule->tuples.ip_tos; 6734 spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6735 0 : rule->tuples_mask.ip_tos; 6736 6737 spec->proto = rule->tuples.ip_proto; 6738 spec_mask->proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6739 0 : rule->tuples_mask.ip_proto; 6740 6741 spec->ip_ver = ETH_RX_NFC_IP4; 6742 } 6743 6744 static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule, 6745 struct ethtool_tcpip6_spec *spec, 6746 struct ethtool_tcpip6_spec *spec_mask) 6747 { 6748 cpu_to_be32_array(spec->ip6src, 6749 rule->tuples.src_ip, IPV6_SIZE); 6750 cpu_to_be32_array(spec->ip6dst, 6751 rule->tuples.dst_ip, IPV6_SIZE); 6752 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6753 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6754 else 6755 cpu_to_be32_array(spec_mask->ip6src, rule->tuples_mask.src_ip, 6756 IPV6_SIZE); 6757 6758 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6759 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6760 else 6761 cpu_to_be32_array(spec_mask->ip6dst, rule->tuples_mask.dst_ip, 6762 IPV6_SIZE); 6763 6764 spec->tclass = rule->tuples.ip_tos; 6765 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6766 0 : rule->tuples_mask.ip_tos; 6767 6768 spec->psrc = cpu_to_be16(rule->tuples.src_port); 6769 spec_mask->psrc = rule->unused_tuple & BIT(INNER_SRC_PORT) ? 6770 0 : cpu_to_be16(rule->tuples_mask.src_port); 6771 6772 spec->pdst = cpu_to_be16(rule->tuples.dst_port); 6773 spec_mask->pdst = rule->unused_tuple & BIT(INNER_DST_PORT) ? 6774 0 : cpu_to_be16(rule->tuples_mask.dst_port); 6775 } 6776 6777 static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule, 6778 struct ethtool_usrip6_spec *spec, 6779 struct ethtool_usrip6_spec *spec_mask) 6780 { 6781 cpu_to_be32_array(spec->ip6src, rule->tuples.src_ip, IPV6_SIZE); 6782 cpu_to_be32_array(spec->ip6dst, rule->tuples.dst_ip, IPV6_SIZE); 6783 if (rule->unused_tuple & BIT(INNER_SRC_IP)) 6784 memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src)); 6785 else 6786 cpu_to_be32_array(spec_mask->ip6src, 6787 rule->tuples_mask.src_ip, IPV6_SIZE); 6788 6789 if (rule->unused_tuple & BIT(INNER_DST_IP)) 6790 memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst)); 6791 else 6792 cpu_to_be32_array(spec_mask->ip6dst, 6793 rule->tuples_mask.dst_ip, IPV6_SIZE); 6794 6795 spec->tclass = rule->tuples.ip_tos; 6796 spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 6797 0 : rule->tuples_mask.ip_tos; 6798 6799 spec->l4_proto = rule->tuples.ip_proto; 6800 spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 6801 0 : rule->tuples_mask.ip_proto; 6802 } 6803 6804 static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule, 6805 struct ethhdr *spec, 6806 struct ethhdr *spec_mask) 6807 { 6808 ether_addr_copy(spec->h_source, rule->tuples.src_mac); 6809 ether_addr_copy(spec->h_dest, rule->tuples.dst_mac); 6810 6811 if (rule->unused_tuple & BIT(INNER_SRC_MAC)) 6812 eth_zero_addr(spec_mask->h_source); 6813 else 6814 ether_addr_copy(spec_mask->h_source, rule->tuples_mask.src_mac); 6815 6816 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6817 eth_zero_addr(spec_mask->h_dest); 6818 else 6819 ether_addr_copy(spec_mask->h_dest, rule->tuples_mask.dst_mac); 6820 6821 spec->h_proto = cpu_to_be16(rule->tuples.ether_proto); 6822 spec_mask->h_proto = rule->unused_tuple & BIT(INNER_ETH_TYPE) ? 6823 0 : cpu_to_be16(rule->tuples_mask.ether_proto); 6824 } 6825 6826 static void hclge_fd_get_user_def_info(struct ethtool_rx_flow_spec *fs, 6827 struct hclge_fd_rule *rule) 6828 { 6829 if ((rule->unused_tuple & HCLGE_FD_TUPLE_USER_DEF_TUPLES) == 6830 HCLGE_FD_TUPLE_USER_DEF_TUPLES) { 6831 fs->h_ext.data[0] = 0; 6832 fs->h_ext.data[1] = 0; 6833 fs->m_ext.data[0] = 0; 6834 fs->m_ext.data[1] = 0; 6835 } else { 6836 fs->h_ext.data[0] = cpu_to_be32(rule->ep.user_def.offset); 6837 fs->h_ext.data[1] = cpu_to_be32(rule->ep.user_def.data); 6838 fs->m_ext.data[0] = 6839 cpu_to_be32(HCLGE_FD_USER_DEF_OFFSET_UNMASK); 6840 fs->m_ext.data[1] = cpu_to_be32(rule->ep.user_def.data_mask); 6841 } 6842 } 6843 6844 static void hclge_fd_get_ext_info(struct ethtool_rx_flow_spec *fs, 6845 struct hclge_fd_rule *rule) 6846 { 6847 if (fs->flow_type & FLOW_EXT) { 6848 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1); 6849 fs->m_ext.vlan_tci = 6850 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ? 6851 0 : cpu_to_be16(rule->tuples_mask.vlan_tag1); 6852 6853 hclge_fd_get_user_def_info(fs, rule); 6854 } 6855 6856 if (fs->flow_type & FLOW_MAC_EXT) { 6857 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac); 6858 if (rule->unused_tuple & BIT(INNER_DST_MAC)) 6859 eth_zero_addr(fs->m_u.ether_spec.h_dest); 6860 else 6861 ether_addr_copy(fs->m_u.ether_spec.h_dest, 6862 rule->tuples_mask.dst_mac); 6863 } 6864 } 6865 6866 static struct hclge_fd_rule *hclge_get_fd_rule(struct hclge_dev *hdev, 6867 u16 location) 6868 { 6869 struct hclge_fd_rule *rule = NULL; 6870 struct hlist_node *node2; 6871 6872 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) { 6873 if (rule->location == location) 6874 return rule; 6875 else if (rule->location > location) 6876 return NULL; 6877 } 6878 6879 return NULL; 6880 } 6881 6882 static void hclge_fd_get_ring_cookie(struct ethtool_rx_flow_spec *fs, 6883 struct hclge_fd_rule *rule) 6884 { 6885 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) { 6886 fs->ring_cookie = RX_CLS_FLOW_DISC; 6887 } else { 6888 u64 vf_id; 6889 6890 fs->ring_cookie = rule->queue_id; 6891 vf_id = rule->vf_id; 6892 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 6893 fs->ring_cookie |= vf_id; 6894 } 6895 } 6896 6897 static int hclge_get_fd_rule_info(struct hnae3_handle *handle, 6898 struct ethtool_rxnfc *cmd) 6899 { 6900 struct hclge_vport *vport = hclge_get_vport(handle); 6901 struct hclge_fd_rule *rule = NULL; 6902 struct hclge_dev *hdev = vport->back; 6903 struct ethtool_rx_flow_spec *fs; 6904 6905 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6906 return -EOPNOTSUPP; 6907 6908 fs = (struct ethtool_rx_flow_spec *)&cmd->fs; 6909 6910 spin_lock_bh(&hdev->fd_rule_lock); 6911 6912 rule = hclge_get_fd_rule(hdev, fs->location); 6913 if (!rule) { 6914 spin_unlock_bh(&hdev->fd_rule_lock); 6915 return -ENOENT; 6916 } 6917 6918 fs->flow_type = rule->flow_type; 6919 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 6920 case SCTP_V4_FLOW: 6921 case TCP_V4_FLOW: 6922 case UDP_V4_FLOW: 6923 hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec, 6924 &fs->m_u.tcp_ip4_spec); 6925 break; 6926 case IP_USER_FLOW: 6927 hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec, 6928 &fs->m_u.usr_ip4_spec); 6929 break; 6930 case SCTP_V6_FLOW: 6931 case TCP_V6_FLOW: 6932 case UDP_V6_FLOW: 6933 hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec, 6934 &fs->m_u.tcp_ip6_spec); 6935 break; 6936 case IPV6_USER_FLOW: 6937 hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec, 6938 &fs->m_u.usr_ip6_spec); 6939 break; 6940 /* The flow type of fd rule has been checked before adding in to rule 6941 * list. As other flow types have been handled, it must be ETHER_FLOW 6942 * for the default case 6943 */ 6944 default: 6945 hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec, 6946 &fs->m_u.ether_spec); 6947 break; 6948 } 6949 6950 hclge_fd_get_ext_info(fs, rule); 6951 6952 hclge_fd_get_ring_cookie(fs, rule); 6953 6954 spin_unlock_bh(&hdev->fd_rule_lock); 6955 6956 return 0; 6957 } 6958 6959 static int hclge_get_all_rules(struct hnae3_handle *handle, 6960 struct ethtool_rxnfc *cmd, u32 *rule_locs) 6961 { 6962 struct hclge_vport *vport = hclge_get_vport(handle); 6963 struct hclge_dev *hdev = vport->back; 6964 struct hclge_fd_rule *rule; 6965 struct hlist_node *node2; 6966 int cnt = 0; 6967 6968 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 6969 return -EOPNOTSUPP; 6970 6971 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 6972 6973 spin_lock_bh(&hdev->fd_rule_lock); 6974 hlist_for_each_entry_safe(rule, node2, 6975 &hdev->fd_rule_list, rule_node) { 6976 if (cnt == cmd->rule_cnt) { 6977 spin_unlock_bh(&hdev->fd_rule_lock); 6978 return -EMSGSIZE; 6979 } 6980 6981 if (rule->state == HCLGE_FD_TO_DEL) 6982 continue; 6983 6984 rule_locs[cnt] = rule->location; 6985 cnt++; 6986 } 6987 6988 spin_unlock_bh(&hdev->fd_rule_lock); 6989 6990 cmd->rule_cnt = cnt; 6991 6992 return 0; 6993 } 6994 6995 static void hclge_fd_get_flow_tuples(const struct flow_keys *fkeys, 6996 struct hclge_fd_rule_tuples *tuples) 6997 { 6998 #define flow_ip6_src fkeys->addrs.v6addrs.src.in6_u.u6_addr32 6999 #define flow_ip6_dst fkeys->addrs.v6addrs.dst.in6_u.u6_addr32 7000 7001 tuples->ether_proto = be16_to_cpu(fkeys->basic.n_proto); 7002 tuples->ip_proto = fkeys->basic.ip_proto; 7003 tuples->dst_port = be16_to_cpu(fkeys->ports.dst); 7004 7005 if (fkeys->basic.n_proto == htons(ETH_P_IP)) { 7006 tuples->src_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.src); 7007 tuples->dst_ip[3] = be32_to_cpu(fkeys->addrs.v4addrs.dst); 7008 } else { 7009 int i; 7010 7011 for (i = 0; i < IPV6_SIZE; i++) { 7012 tuples->src_ip[i] = be32_to_cpu(flow_ip6_src[i]); 7013 tuples->dst_ip[i] = be32_to_cpu(flow_ip6_dst[i]); 7014 } 7015 } 7016 } 7017 7018 /* traverse all rules, check whether an existed rule has the same tuples */ 7019 static struct hclge_fd_rule * 7020 hclge_fd_search_flow_keys(struct hclge_dev *hdev, 7021 const struct hclge_fd_rule_tuples *tuples) 7022 { 7023 struct hclge_fd_rule *rule = NULL; 7024 struct hlist_node *node; 7025 7026 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7027 if (!memcmp(tuples, &rule->tuples, sizeof(*tuples))) 7028 return rule; 7029 } 7030 7031 return NULL; 7032 } 7033 7034 static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples, 7035 struct hclge_fd_rule *rule) 7036 { 7037 rule->unused_tuple = BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) | 7038 BIT(INNER_VLAN_TAG_FST) | BIT(INNER_IP_TOS) | 7039 BIT(INNER_SRC_PORT); 7040 rule->action = 0; 7041 rule->vf_id = 0; 7042 rule->rule_type = HCLGE_FD_ARFS_ACTIVE; 7043 rule->state = HCLGE_FD_TO_ADD; 7044 if (tuples->ether_proto == ETH_P_IP) { 7045 if (tuples->ip_proto == IPPROTO_TCP) 7046 rule->flow_type = TCP_V4_FLOW; 7047 else 7048 rule->flow_type = UDP_V4_FLOW; 7049 } else { 7050 if (tuples->ip_proto == IPPROTO_TCP) 7051 rule->flow_type = TCP_V6_FLOW; 7052 else 7053 rule->flow_type = UDP_V6_FLOW; 7054 } 7055 memcpy(&rule->tuples, tuples, sizeof(rule->tuples)); 7056 memset(&rule->tuples_mask, 0xFF, sizeof(rule->tuples_mask)); 7057 } 7058 7059 static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id, 7060 u16 flow_id, struct flow_keys *fkeys) 7061 { 7062 struct hclge_vport *vport = hclge_get_vport(handle); 7063 struct hclge_fd_rule_tuples new_tuples = {}; 7064 struct hclge_dev *hdev = vport->back; 7065 struct hclge_fd_rule *rule; 7066 u16 bit_id; 7067 7068 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7069 return -EOPNOTSUPP; 7070 7071 /* when there is already fd rule existed add by user, 7072 * arfs should not work 7073 */ 7074 spin_lock_bh(&hdev->fd_rule_lock); 7075 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE && 7076 hdev->fd_active_type != HCLGE_FD_RULE_NONE) { 7077 spin_unlock_bh(&hdev->fd_rule_lock); 7078 return -EOPNOTSUPP; 7079 } 7080 7081 hclge_fd_get_flow_tuples(fkeys, &new_tuples); 7082 7083 /* check is there flow director filter existed for this flow, 7084 * if not, create a new filter for it; 7085 * if filter exist with different queue id, modify the filter; 7086 * if filter exist with same queue id, do nothing 7087 */ 7088 rule = hclge_fd_search_flow_keys(hdev, &new_tuples); 7089 if (!rule) { 7090 bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM); 7091 if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7092 spin_unlock_bh(&hdev->fd_rule_lock); 7093 return -ENOSPC; 7094 } 7095 7096 rule = kzalloc(sizeof(*rule), GFP_ATOMIC); 7097 if (!rule) { 7098 spin_unlock_bh(&hdev->fd_rule_lock); 7099 return -ENOMEM; 7100 } 7101 7102 rule->location = bit_id; 7103 rule->arfs.flow_id = flow_id; 7104 rule->queue_id = queue_id; 7105 hclge_fd_build_arfs_rule(&new_tuples, rule); 7106 hclge_update_fd_list(hdev, rule->state, rule->location, rule); 7107 hdev->fd_active_type = HCLGE_FD_ARFS_ACTIVE; 7108 } else if (rule->queue_id != queue_id) { 7109 rule->queue_id = queue_id; 7110 rule->state = HCLGE_FD_TO_ADD; 7111 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7112 hclge_task_schedule(hdev, 0); 7113 } 7114 spin_unlock_bh(&hdev->fd_rule_lock); 7115 return rule->location; 7116 } 7117 7118 static void hclge_rfs_filter_expire(struct hclge_dev *hdev) 7119 { 7120 #ifdef CONFIG_RFS_ACCEL 7121 struct hnae3_handle *handle = &hdev->vport[0].nic; 7122 struct hclge_fd_rule *rule; 7123 struct hlist_node *node; 7124 7125 spin_lock_bh(&hdev->fd_rule_lock); 7126 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) { 7127 spin_unlock_bh(&hdev->fd_rule_lock); 7128 return; 7129 } 7130 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7131 if (rule->state != HCLGE_FD_ACTIVE) 7132 continue; 7133 if (rps_may_expire_flow(handle->netdev, rule->queue_id, 7134 rule->arfs.flow_id, rule->location)) { 7135 rule->state = HCLGE_FD_TO_DEL; 7136 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7137 } 7138 } 7139 spin_unlock_bh(&hdev->fd_rule_lock); 7140 #endif 7141 } 7142 7143 /* make sure being called after lock up with fd_rule_lock */ 7144 static int hclge_clear_arfs_rules(struct hclge_dev *hdev) 7145 { 7146 #ifdef CONFIG_RFS_ACCEL 7147 struct hclge_fd_rule *rule; 7148 struct hlist_node *node; 7149 int ret; 7150 7151 if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE) 7152 return 0; 7153 7154 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7155 switch (rule->state) { 7156 case HCLGE_FD_TO_DEL: 7157 case HCLGE_FD_ACTIVE: 7158 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7159 rule->location, NULL, false); 7160 if (ret) 7161 return ret; 7162 fallthrough; 7163 case HCLGE_FD_TO_ADD: 7164 hclge_fd_dec_rule_cnt(hdev, rule->location); 7165 hlist_del(&rule->rule_node); 7166 kfree(rule); 7167 break; 7168 default: 7169 break; 7170 } 7171 } 7172 hclge_sync_fd_state(hdev); 7173 7174 #endif 7175 return 0; 7176 } 7177 7178 static void hclge_get_cls_key_basic(const struct flow_rule *flow, 7179 struct hclge_fd_rule *rule) 7180 { 7181 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_BASIC)) { 7182 struct flow_match_basic match; 7183 u16 ethtype_key, ethtype_mask; 7184 7185 flow_rule_match_basic(flow, &match); 7186 ethtype_key = ntohs(match.key->n_proto); 7187 ethtype_mask = ntohs(match.mask->n_proto); 7188 7189 if (ethtype_key == ETH_P_ALL) { 7190 ethtype_key = 0; 7191 ethtype_mask = 0; 7192 } 7193 rule->tuples.ether_proto = ethtype_key; 7194 rule->tuples_mask.ether_proto = ethtype_mask; 7195 rule->tuples.ip_proto = match.key->ip_proto; 7196 rule->tuples_mask.ip_proto = match.mask->ip_proto; 7197 } else { 7198 rule->unused_tuple |= BIT(INNER_IP_PROTO); 7199 rule->unused_tuple |= BIT(INNER_ETH_TYPE); 7200 } 7201 } 7202 7203 static void hclge_get_cls_key_mac(const struct flow_rule *flow, 7204 struct hclge_fd_rule *rule) 7205 { 7206 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 7207 struct flow_match_eth_addrs match; 7208 7209 flow_rule_match_eth_addrs(flow, &match); 7210 ether_addr_copy(rule->tuples.dst_mac, match.key->dst); 7211 ether_addr_copy(rule->tuples_mask.dst_mac, match.mask->dst); 7212 ether_addr_copy(rule->tuples.src_mac, match.key->src); 7213 ether_addr_copy(rule->tuples_mask.src_mac, match.mask->src); 7214 } else { 7215 rule->unused_tuple |= BIT(INNER_DST_MAC); 7216 rule->unused_tuple |= BIT(INNER_SRC_MAC); 7217 } 7218 } 7219 7220 static void hclge_get_cls_key_vlan(const struct flow_rule *flow, 7221 struct hclge_fd_rule *rule) 7222 { 7223 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_VLAN)) { 7224 struct flow_match_vlan match; 7225 7226 flow_rule_match_vlan(flow, &match); 7227 rule->tuples.vlan_tag1 = match.key->vlan_id | 7228 (match.key->vlan_priority << VLAN_PRIO_SHIFT); 7229 rule->tuples_mask.vlan_tag1 = match.mask->vlan_id | 7230 (match.mask->vlan_priority << VLAN_PRIO_SHIFT); 7231 } else { 7232 rule->unused_tuple |= BIT(INNER_VLAN_TAG_FST); 7233 } 7234 } 7235 7236 static void hclge_get_cls_key_ip(const struct flow_rule *flow, 7237 struct hclge_fd_rule *rule) 7238 { 7239 u16 addr_type = 0; 7240 7241 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_CONTROL)) { 7242 struct flow_match_control match; 7243 7244 flow_rule_match_control(flow, &match); 7245 addr_type = match.key->addr_type; 7246 } 7247 7248 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { 7249 struct flow_match_ipv4_addrs match; 7250 7251 flow_rule_match_ipv4_addrs(flow, &match); 7252 rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(match.key->src); 7253 rule->tuples_mask.src_ip[IPV4_INDEX] = 7254 be32_to_cpu(match.mask->src); 7255 rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(match.key->dst); 7256 rule->tuples_mask.dst_ip[IPV4_INDEX] = 7257 be32_to_cpu(match.mask->dst); 7258 } else if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { 7259 struct flow_match_ipv6_addrs match; 7260 7261 flow_rule_match_ipv6_addrs(flow, &match); 7262 be32_to_cpu_array(rule->tuples.src_ip, match.key->src.s6_addr32, 7263 IPV6_SIZE); 7264 be32_to_cpu_array(rule->tuples_mask.src_ip, 7265 match.mask->src.s6_addr32, IPV6_SIZE); 7266 be32_to_cpu_array(rule->tuples.dst_ip, match.key->dst.s6_addr32, 7267 IPV6_SIZE); 7268 be32_to_cpu_array(rule->tuples_mask.dst_ip, 7269 match.mask->dst.s6_addr32, IPV6_SIZE); 7270 } else { 7271 rule->unused_tuple |= BIT(INNER_SRC_IP); 7272 rule->unused_tuple |= BIT(INNER_DST_IP); 7273 } 7274 } 7275 7276 static void hclge_get_cls_key_port(const struct flow_rule *flow, 7277 struct hclge_fd_rule *rule) 7278 { 7279 if (flow_rule_match_key(flow, FLOW_DISSECTOR_KEY_PORTS)) { 7280 struct flow_match_ports match; 7281 7282 flow_rule_match_ports(flow, &match); 7283 7284 rule->tuples.src_port = be16_to_cpu(match.key->src); 7285 rule->tuples_mask.src_port = be16_to_cpu(match.mask->src); 7286 rule->tuples.dst_port = be16_to_cpu(match.key->dst); 7287 rule->tuples_mask.dst_port = be16_to_cpu(match.mask->dst); 7288 } else { 7289 rule->unused_tuple |= BIT(INNER_SRC_PORT); 7290 rule->unused_tuple |= BIT(INNER_DST_PORT); 7291 } 7292 } 7293 7294 static int hclge_parse_cls_flower(struct hclge_dev *hdev, 7295 struct flow_cls_offload *cls_flower, 7296 struct hclge_fd_rule *rule) 7297 { 7298 struct flow_rule *flow = flow_cls_offload_flow_rule(cls_flower); 7299 struct flow_dissector *dissector = flow->match.dissector; 7300 7301 if (dissector->used_keys & 7302 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | 7303 BIT(FLOW_DISSECTOR_KEY_BASIC) | 7304 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | 7305 BIT(FLOW_DISSECTOR_KEY_VLAN) | 7306 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | 7307 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | 7308 BIT(FLOW_DISSECTOR_KEY_PORTS))) { 7309 dev_err(&hdev->pdev->dev, "unsupported key set: %#x\n", 7310 dissector->used_keys); 7311 return -EOPNOTSUPP; 7312 } 7313 7314 hclge_get_cls_key_basic(flow, rule); 7315 hclge_get_cls_key_mac(flow, rule); 7316 hclge_get_cls_key_vlan(flow, rule); 7317 hclge_get_cls_key_ip(flow, rule); 7318 hclge_get_cls_key_port(flow, rule); 7319 7320 return 0; 7321 } 7322 7323 static int hclge_check_cls_flower(struct hclge_dev *hdev, 7324 struct flow_cls_offload *cls_flower, int tc) 7325 { 7326 u32 prio = cls_flower->common.prio; 7327 7328 if (tc < 0 || tc > hdev->tc_max) { 7329 dev_err(&hdev->pdev->dev, "invalid traffic class\n"); 7330 return -EINVAL; 7331 } 7332 7333 if (prio == 0 || 7334 prio > hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) { 7335 dev_err(&hdev->pdev->dev, 7336 "prio %u should be in range[1, %u]\n", 7337 prio, hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]); 7338 return -EINVAL; 7339 } 7340 7341 if (test_bit(prio - 1, hdev->fd_bmap)) { 7342 dev_err(&hdev->pdev->dev, "prio %u is already used\n", prio); 7343 return -EINVAL; 7344 } 7345 return 0; 7346 } 7347 7348 static int hclge_add_cls_flower(struct hnae3_handle *handle, 7349 struct flow_cls_offload *cls_flower, 7350 int tc) 7351 { 7352 struct hclge_vport *vport = hclge_get_vport(handle); 7353 struct hclge_dev *hdev = vport->back; 7354 struct hclge_fd_rule *rule; 7355 int ret; 7356 7357 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 7358 dev_err(&hdev->pdev->dev, 7359 "cls flower is not supported\n"); 7360 return -EOPNOTSUPP; 7361 } 7362 7363 ret = hclge_check_cls_flower(hdev, cls_flower, tc); 7364 if (ret) { 7365 dev_err(&hdev->pdev->dev, 7366 "failed to check cls flower params, ret = %d\n", ret); 7367 return ret; 7368 } 7369 7370 rule = kzalloc(sizeof(*rule), GFP_KERNEL); 7371 if (!rule) 7372 return -ENOMEM; 7373 7374 ret = hclge_parse_cls_flower(hdev, cls_flower, rule); 7375 if (ret) { 7376 kfree(rule); 7377 return ret; 7378 } 7379 7380 rule->action = HCLGE_FD_ACTION_SELECT_TC; 7381 rule->cls_flower.tc = tc; 7382 rule->location = cls_flower->common.prio - 1; 7383 rule->vf_id = 0; 7384 rule->cls_flower.cookie = cls_flower->cookie; 7385 rule->rule_type = HCLGE_FD_TC_FLOWER_ACTIVE; 7386 7387 ret = hclge_add_fd_entry_common(hdev, rule); 7388 if (ret) 7389 kfree(rule); 7390 7391 return ret; 7392 } 7393 7394 static struct hclge_fd_rule *hclge_find_cls_flower(struct hclge_dev *hdev, 7395 unsigned long cookie) 7396 { 7397 struct hclge_fd_rule *rule; 7398 struct hlist_node *node; 7399 7400 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 7401 if (rule->cls_flower.cookie == cookie) 7402 return rule; 7403 } 7404 7405 return NULL; 7406 } 7407 7408 static int hclge_del_cls_flower(struct hnae3_handle *handle, 7409 struct flow_cls_offload *cls_flower) 7410 { 7411 struct hclge_vport *vport = hclge_get_vport(handle); 7412 struct hclge_dev *hdev = vport->back; 7413 struct hclge_fd_rule *rule; 7414 int ret; 7415 7416 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) 7417 return -EOPNOTSUPP; 7418 7419 spin_lock_bh(&hdev->fd_rule_lock); 7420 7421 rule = hclge_find_cls_flower(hdev, cls_flower->cookie); 7422 if (!rule) { 7423 spin_unlock_bh(&hdev->fd_rule_lock); 7424 return -EINVAL; 7425 } 7426 7427 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location, 7428 NULL, false); 7429 if (ret) { 7430 spin_unlock_bh(&hdev->fd_rule_lock); 7431 return ret; 7432 } 7433 7434 hclge_update_fd_list(hdev, HCLGE_FD_DELETED, rule->location, NULL); 7435 spin_unlock_bh(&hdev->fd_rule_lock); 7436 7437 return 0; 7438 } 7439 7440 static void hclge_sync_fd_list(struct hclge_dev *hdev, struct hlist_head *hlist) 7441 { 7442 struct hclge_fd_rule *rule; 7443 struct hlist_node *node; 7444 int ret = 0; 7445 7446 if (!test_and_clear_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state)) 7447 return; 7448 7449 spin_lock_bh(&hdev->fd_rule_lock); 7450 7451 hlist_for_each_entry_safe(rule, node, hlist, rule_node) { 7452 switch (rule->state) { 7453 case HCLGE_FD_TO_ADD: 7454 ret = hclge_fd_config_rule(hdev, rule); 7455 if (ret) 7456 goto out; 7457 rule->state = HCLGE_FD_ACTIVE; 7458 break; 7459 case HCLGE_FD_TO_DEL: 7460 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, 7461 rule->location, NULL, false); 7462 if (ret) 7463 goto out; 7464 hclge_fd_dec_rule_cnt(hdev, rule->location); 7465 hclge_fd_free_node(hdev, rule); 7466 break; 7467 default: 7468 break; 7469 } 7470 } 7471 7472 out: 7473 if (ret) 7474 set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state); 7475 7476 spin_unlock_bh(&hdev->fd_rule_lock); 7477 } 7478 7479 static void hclge_sync_fd_table(struct hclge_dev *hdev) 7480 { 7481 if (test_and_clear_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state)) { 7482 bool clear_list = hdev->fd_active_type == HCLGE_FD_ARFS_ACTIVE; 7483 7484 hclge_clear_fd_rules_in_list(hdev, clear_list); 7485 } 7486 7487 hclge_sync_fd_user_def_cfg(hdev, false); 7488 7489 hclge_sync_fd_list(hdev, &hdev->fd_rule_list); 7490 } 7491 7492 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle) 7493 { 7494 struct hclge_vport *vport = hclge_get_vport(handle); 7495 struct hclge_dev *hdev = vport->back; 7496 7497 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) || 7498 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING); 7499 } 7500 7501 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle) 7502 { 7503 struct hclge_vport *vport = hclge_get_vport(handle); 7504 struct hclge_dev *hdev = vport->back; 7505 7506 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 7507 } 7508 7509 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle) 7510 { 7511 struct hclge_vport *vport = hclge_get_vport(handle); 7512 struct hclge_dev *hdev = vport->back; 7513 7514 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 7515 } 7516 7517 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle) 7518 { 7519 struct hclge_vport *vport = hclge_get_vport(handle); 7520 struct hclge_dev *hdev = vport->back; 7521 7522 return hdev->rst_stats.hw_reset_done_cnt; 7523 } 7524 7525 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable) 7526 { 7527 struct hclge_vport *vport = hclge_get_vport(handle); 7528 struct hclge_dev *hdev = vport->back; 7529 7530 hdev->fd_en = enable; 7531 7532 if (!enable) 7533 set_bit(HCLGE_STATE_FD_CLEAR_ALL, &hdev->state); 7534 else 7535 hclge_restore_fd_entries(handle); 7536 7537 hclge_task_schedule(hdev, 0); 7538 } 7539 7540 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 7541 { 7542 struct hclge_desc desc; 7543 struct hclge_config_mac_mode_cmd *req = 7544 (struct hclge_config_mac_mode_cmd *)desc.data; 7545 u32 loop_en = 0; 7546 int ret; 7547 7548 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 7549 7550 if (enable) { 7551 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U); 7552 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U); 7553 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U); 7554 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U); 7555 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U); 7556 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U); 7557 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U); 7558 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U); 7559 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U); 7560 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U); 7561 } 7562 7563 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7564 7565 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7566 if (ret) 7567 dev_err(&hdev->pdev->dev, 7568 "mac enable fail, ret =%d.\n", ret); 7569 } 7570 7571 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid, 7572 u8 switch_param, u8 param_mask) 7573 { 7574 struct hclge_mac_vlan_switch_cmd *req; 7575 struct hclge_desc desc; 7576 u32 func_id; 7577 int ret; 7578 7579 func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0); 7580 req = (struct hclge_mac_vlan_switch_cmd *)desc.data; 7581 7582 /* read current config parameter */ 7583 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM, 7584 true); 7585 req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL; 7586 req->func_id = cpu_to_le32(func_id); 7587 7588 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7589 if (ret) { 7590 dev_err(&hdev->pdev->dev, 7591 "read mac vlan switch parameter fail, ret = %d\n", ret); 7592 return ret; 7593 } 7594 7595 /* modify and write new config parameter */ 7596 hclge_comm_cmd_reuse_desc(&desc, false); 7597 req->switch_param = (req->switch_param & param_mask) | switch_param; 7598 req->param_mask = param_mask; 7599 7600 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7601 if (ret) 7602 dev_err(&hdev->pdev->dev, 7603 "set mac vlan switch parameter fail, ret = %d\n", ret); 7604 return ret; 7605 } 7606 7607 static void hclge_phy_link_status_wait(struct hclge_dev *hdev, 7608 int link_ret) 7609 { 7610 #define HCLGE_PHY_LINK_STATUS_NUM 200 7611 7612 struct phy_device *phydev = hdev->hw.mac.phydev; 7613 int i = 0; 7614 int ret; 7615 7616 do { 7617 ret = phy_read_status(phydev); 7618 if (ret) { 7619 dev_err(&hdev->pdev->dev, 7620 "phy update link status fail, ret = %d\n", ret); 7621 return; 7622 } 7623 7624 if (phydev->link == link_ret) 7625 break; 7626 7627 msleep(HCLGE_LINK_STATUS_MS); 7628 } while (++i < HCLGE_PHY_LINK_STATUS_NUM); 7629 } 7630 7631 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret) 7632 { 7633 #define HCLGE_MAC_LINK_STATUS_NUM 100 7634 7635 int link_status; 7636 int i = 0; 7637 int ret; 7638 7639 do { 7640 ret = hclge_get_mac_link_status(hdev, &link_status); 7641 if (ret) 7642 return ret; 7643 if (link_status == link_ret) 7644 return 0; 7645 7646 msleep(HCLGE_LINK_STATUS_MS); 7647 } while (++i < HCLGE_MAC_LINK_STATUS_NUM); 7648 return -EBUSY; 7649 } 7650 7651 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en, 7652 bool is_phy) 7653 { 7654 int link_ret; 7655 7656 link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 7657 7658 if (is_phy) 7659 hclge_phy_link_status_wait(hdev, link_ret); 7660 7661 return hclge_mac_link_status_wait(hdev, link_ret); 7662 } 7663 7664 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) 7665 { 7666 struct hclge_config_mac_mode_cmd *req; 7667 struct hclge_desc desc; 7668 u32 loop_en; 7669 int ret; 7670 7671 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 7672 /* 1 Read out the MAC mode config at first */ 7673 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 7674 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7675 if (ret) { 7676 dev_err(&hdev->pdev->dev, 7677 "mac loopback get fail, ret =%d.\n", ret); 7678 return ret; 7679 } 7680 7681 /* 2 Then setup the loopback flag */ 7682 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 7683 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 7684 7685 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 7686 7687 /* 3 Config mac work mode with loopback flag 7688 * and its original configure parameters 7689 */ 7690 hclge_comm_cmd_reuse_desc(&desc, false); 7691 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7692 if (ret) 7693 dev_err(&hdev->pdev->dev, 7694 "mac loopback set fail, ret =%d.\n", ret); 7695 return ret; 7696 } 7697 7698 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en, 7699 enum hnae3_loop loop_mode) 7700 { 7701 struct hclge_common_lb_cmd *req; 7702 struct hclge_desc desc; 7703 u8 loop_mode_b; 7704 int ret; 7705 7706 req = (struct hclge_common_lb_cmd *)desc.data; 7707 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false); 7708 7709 switch (loop_mode) { 7710 case HNAE3_LOOP_SERIAL_SERDES: 7711 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 7712 break; 7713 case HNAE3_LOOP_PARALLEL_SERDES: 7714 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B; 7715 break; 7716 case HNAE3_LOOP_PHY: 7717 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B; 7718 break; 7719 default: 7720 dev_err(&hdev->pdev->dev, 7721 "unsupported loopback mode %d\n", loop_mode); 7722 return -ENOTSUPP; 7723 } 7724 7725 req->mask = loop_mode_b; 7726 if (en) 7727 req->enable = loop_mode_b; 7728 7729 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7730 if (ret) 7731 dev_err(&hdev->pdev->dev, 7732 "failed to send loopback cmd, loop_mode = %d, ret = %d\n", 7733 loop_mode, ret); 7734 7735 return ret; 7736 } 7737 7738 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev) 7739 { 7740 #define HCLGE_COMMON_LB_RETRY_MS 10 7741 #define HCLGE_COMMON_LB_RETRY_NUM 100 7742 7743 struct hclge_common_lb_cmd *req; 7744 struct hclge_desc desc; 7745 u32 i = 0; 7746 int ret; 7747 7748 req = (struct hclge_common_lb_cmd *)desc.data; 7749 7750 do { 7751 msleep(HCLGE_COMMON_LB_RETRY_MS); 7752 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, 7753 true); 7754 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7755 if (ret) { 7756 dev_err(&hdev->pdev->dev, 7757 "failed to get loopback done status, ret = %d\n", 7758 ret); 7759 return ret; 7760 } 7761 } while (++i < HCLGE_COMMON_LB_RETRY_NUM && 7762 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B)); 7763 7764 if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) { 7765 dev_err(&hdev->pdev->dev, "wait loopback timeout\n"); 7766 return -EBUSY; 7767 } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) { 7768 dev_err(&hdev->pdev->dev, "failed to do loopback test\n"); 7769 return -EIO; 7770 } 7771 7772 return 0; 7773 } 7774 7775 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en, 7776 enum hnae3_loop loop_mode) 7777 { 7778 int ret; 7779 7780 ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode); 7781 if (ret) 7782 return ret; 7783 7784 return hclge_cfg_common_loopback_wait(hdev); 7785 } 7786 7787 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en, 7788 enum hnae3_loop loop_mode) 7789 { 7790 int ret; 7791 7792 ret = hclge_cfg_common_loopback(hdev, en, loop_mode); 7793 if (ret) 7794 return ret; 7795 7796 hclge_cfg_mac_mode(hdev, en); 7797 7798 ret = hclge_mac_phy_link_status_wait(hdev, en, false); 7799 if (ret) 7800 dev_err(&hdev->pdev->dev, 7801 "serdes loopback config mac mode timeout\n"); 7802 7803 return ret; 7804 } 7805 7806 static int hclge_enable_phy_loopback(struct hclge_dev *hdev, 7807 struct phy_device *phydev) 7808 { 7809 int ret; 7810 7811 if (!phydev->suspended) { 7812 ret = phy_suspend(phydev); 7813 if (ret) 7814 return ret; 7815 } 7816 7817 ret = phy_resume(phydev); 7818 if (ret) 7819 return ret; 7820 7821 return phy_loopback(phydev, true); 7822 } 7823 7824 static int hclge_disable_phy_loopback(struct hclge_dev *hdev, 7825 struct phy_device *phydev) 7826 { 7827 int ret; 7828 7829 ret = phy_loopback(phydev, false); 7830 if (ret) 7831 return ret; 7832 7833 return phy_suspend(phydev); 7834 } 7835 7836 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en) 7837 { 7838 struct phy_device *phydev = hdev->hw.mac.phydev; 7839 int ret; 7840 7841 if (!phydev) { 7842 if (hnae3_dev_phy_imp_supported(hdev)) 7843 return hclge_set_common_loopback(hdev, en, 7844 HNAE3_LOOP_PHY); 7845 return -ENOTSUPP; 7846 } 7847 7848 if (en) 7849 ret = hclge_enable_phy_loopback(hdev, phydev); 7850 else 7851 ret = hclge_disable_phy_loopback(hdev, phydev); 7852 if (ret) { 7853 dev_err(&hdev->pdev->dev, 7854 "set phy loopback fail, ret = %d\n", ret); 7855 return ret; 7856 } 7857 7858 hclge_cfg_mac_mode(hdev, en); 7859 7860 ret = hclge_mac_phy_link_status_wait(hdev, en, true); 7861 if (ret) 7862 dev_err(&hdev->pdev->dev, 7863 "phy loopback config mac mode timeout\n"); 7864 7865 return ret; 7866 } 7867 7868 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id, 7869 u16 stream_id, bool enable) 7870 { 7871 struct hclge_desc desc; 7872 struct hclge_cfg_com_tqp_queue_cmd *req = 7873 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 7874 7875 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 7876 req->tqp_id = cpu_to_le16(tqp_id); 7877 req->stream_id = cpu_to_le16(stream_id); 7878 if (enable) 7879 req->enable |= 1U << HCLGE_TQP_ENABLE_B; 7880 7881 return hclge_cmd_send(&hdev->hw, &desc, 1); 7882 } 7883 7884 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable) 7885 { 7886 struct hclge_vport *vport = hclge_get_vport(handle); 7887 struct hclge_dev *hdev = vport->back; 7888 int ret; 7889 u16 i; 7890 7891 for (i = 0; i < handle->kinfo.num_tqps; i++) { 7892 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable); 7893 if (ret) 7894 return ret; 7895 } 7896 return 0; 7897 } 7898 7899 static int hclge_set_loopback(struct hnae3_handle *handle, 7900 enum hnae3_loop loop_mode, bool en) 7901 { 7902 struct hclge_vport *vport = hclge_get_vport(handle); 7903 struct hclge_dev *hdev = vport->back; 7904 int ret; 7905 7906 /* Loopback can be enabled in three places: SSU, MAC, and serdes. By 7907 * default, SSU loopback is enabled, so if the SMAC and the DMAC are 7908 * the same, the packets are looped back in the SSU. If SSU loopback 7909 * is disabled, packets can reach MAC even if SMAC is the same as DMAC. 7910 */ 7911 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 7912 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B); 7913 7914 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param, 7915 HCLGE_SWITCH_ALW_LPBK_MASK); 7916 if (ret) 7917 return ret; 7918 } 7919 7920 switch (loop_mode) { 7921 case HNAE3_LOOP_APP: 7922 ret = hclge_set_app_loopback(hdev, en); 7923 break; 7924 case HNAE3_LOOP_SERIAL_SERDES: 7925 case HNAE3_LOOP_PARALLEL_SERDES: 7926 ret = hclge_set_common_loopback(hdev, en, loop_mode); 7927 break; 7928 case HNAE3_LOOP_PHY: 7929 ret = hclge_set_phy_loopback(hdev, en); 7930 break; 7931 default: 7932 ret = -ENOTSUPP; 7933 dev_err(&hdev->pdev->dev, 7934 "loop_mode %d is not supported\n", loop_mode); 7935 break; 7936 } 7937 7938 if (ret) 7939 return ret; 7940 7941 ret = hclge_tqp_enable(handle, en); 7942 if (ret) 7943 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n", 7944 en ? "enable" : "disable", ret); 7945 7946 return ret; 7947 } 7948 7949 static int hclge_set_default_loopback(struct hclge_dev *hdev) 7950 { 7951 int ret; 7952 7953 ret = hclge_set_app_loopback(hdev, false); 7954 if (ret) 7955 return ret; 7956 7957 ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES); 7958 if (ret) 7959 return ret; 7960 7961 return hclge_cfg_common_loopback(hdev, false, 7962 HNAE3_LOOP_PARALLEL_SERDES); 7963 } 7964 7965 static void hclge_flush_link_update(struct hclge_dev *hdev) 7966 { 7967 #define HCLGE_FLUSH_LINK_TIMEOUT 100000 7968 7969 unsigned long last = hdev->serv_processed_cnt; 7970 int i = 0; 7971 7972 while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) && 7973 i++ < HCLGE_FLUSH_LINK_TIMEOUT && 7974 last == hdev->serv_processed_cnt) 7975 usleep_range(1, 1); 7976 } 7977 7978 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable) 7979 { 7980 struct hclge_vport *vport = hclge_get_vport(handle); 7981 struct hclge_dev *hdev = vport->back; 7982 7983 if (enable) { 7984 hclge_task_schedule(hdev, 0); 7985 } else { 7986 /* Set the DOWN flag here to disable link updating */ 7987 set_bit(HCLGE_STATE_DOWN, &hdev->state); 7988 7989 /* flush memory to make sure DOWN is seen by service task */ 7990 smp_mb__before_atomic(); 7991 hclge_flush_link_update(hdev); 7992 } 7993 } 7994 7995 static int hclge_ae_start(struct hnae3_handle *handle) 7996 { 7997 struct hclge_vport *vport = hclge_get_vport(handle); 7998 struct hclge_dev *hdev = vport->back; 7999 8000 /* mac enable */ 8001 hclge_cfg_mac_mode(hdev, true); 8002 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 8003 hdev->hw.mac.link = 0; 8004 8005 /* reset tqp stats */ 8006 hclge_comm_reset_tqp_stats(handle); 8007 8008 hclge_mac_start_phy(hdev); 8009 8010 return 0; 8011 } 8012 8013 static void hclge_ae_stop(struct hnae3_handle *handle) 8014 { 8015 struct hclge_vport *vport = hclge_get_vport(handle); 8016 struct hclge_dev *hdev = vport->back; 8017 8018 set_bit(HCLGE_STATE_DOWN, &hdev->state); 8019 spin_lock_bh(&hdev->fd_rule_lock); 8020 hclge_clear_arfs_rules(hdev); 8021 spin_unlock_bh(&hdev->fd_rule_lock); 8022 8023 /* If it is not PF reset or FLR, the firmware will disable the MAC, 8024 * so it only need to stop phy here. 8025 */ 8026 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) && 8027 hdev->reset_type != HNAE3_FUNC_RESET && 8028 hdev->reset_type != HNAE3_FLR_RESET) { 8029 hclge_mac_stop_phy(hdev); 8030 hclge_update_link_status(hdev); 8031 return; 8032 } 8033 8034 hclge_reset_tqp(handle); 8035 8036 hclge_config_mac_tnl_int(hdev, false); 8037 8038 /* Mac disable */ 8039 hclge_cfg_mac_mode(hdev, false); 8040 8041 hclge_mac_stop_phy(hdev); 8042 8043 /* reset tqp stats */ 8044 hclge_comm_reset_tqp_stats(handle); 8045 hclge_update_link_status(hdev); 8046 } 8047 8048 int hclge_vport_start(struct hclge_vport *vport) 8049 { 8050 struct hclge_dev *hdev = vport->back; 8051 8052 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8053 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 8054 vport->last_active_jiffies = jiffies; 8055 8056 if (test_bit(vport->vport_id, hdev->vport_config_block)) { 8057 if (vport->vport_id) { 8058 hclge_restore_mac_table_common(vport); 8059 hclge_restore_vport_vlan_table(vport); 8060 } else { 8061 hclge_restore_hw_table(hdev); 8062 } 8063 } 8064 8065 clear_bit(vport->vport_id, hdev->vport_config_block); 8066 8067 return 0; 8068 } 8069 8070 void hclge_vport_stop(struct hclge_vport *vport) 8071 { 8072 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 8073 } 8074 8075 static int hclge_client_start(struct hnae3_handle *handle) 8076 { 8077 struct hclge_vport *vport = hclge_get_vport(handle); 8078 8079 return hclge_vport_start(vport); 8080 } 8081 8082 static void hclge_client_stop(struct hnae3_handle *handle) 8083 { 8084 struct hclge_vport *vport = hclge_get_vport(handle); 8085 8086 hclge_vport_stop(vport); 8087 } 8088 8089 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 8090 u16 cmdq_resp, u8 resp_code, 8091 enum hclge_mac_vlan_tbl_opcode op) 8092 { 8093 struct hclge_dev *hdev = vport->back; 8094 8095 if (cmdq_resp) { 8096 dev_err(&hdev->pdev->dev, 8097 "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n", 8098 cmdq_resp); 8099 return -EIO; 8100 } 8101 8102 if (op == HCLGE_MAC_VLAN_ADD) { 8103 if (!resp_code || resp_code == 1) 8104 return 0; 8105 else if (resp_code == HCLGE_ADD_UC_OVERFLOW || 8106 resp_code == HCLGE_ADD_MC_OVERFLOW) 8107 return -ENOSPC; 8108 8109 dev_err(&hdev->pdev->dev, 8110 "add mac addr failed for undefined, code=%u.\n", 8111 resp_code); 8112 return -EIO; 8113 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 8114 if (!resp_code) { 8115 return 0; 8116 } else if (resp_code == 1) { 8117 dev_dbg(&hdev->pdev->dev, 8118 "remove mac addr failed for miss.\n"); 8119 return -ENOENT; 8120 } 8121 8122 dev_err(&hdev->pdev->dev, 8123 "remove mac addr failed for undefined, code=%u.\n", 8124 resp_code); 8125 return -EIO; 8126 } else if (op == HCLGE_MAC_VLAN_LKUP) { 8127 if (!resp_code) { 8128 return 0; 8129 } else if (resp_code == 1) { 8130 dev_dbg(&hdev->pdev->dev, 8131 "lookup mac addr failed for miss.\n"); 8132 return -ENOENT; 8133 } 8134 8135 dev_err(&hdev->pdev->dev, 8136 "lookup mac addr failed for undefined, code=%u.\n", 8137 resp_code); 8138 return -EIO; 8139 } 8140 8141 dev_err(&hdev->pdev->dev, 8142 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op); 8143 8144 return -EINVAL; 8145 } 8146 8147 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 8148 { 8149 #define HCLGE_VF_NUM_IN_FIRST_DESC 192 8150 8151 unsigned int word_num; 8152 unsigned int bit_num; 8153 8154 if (vfid > 255 || vfid < 0) 8155 return -EIO; 8156 8157 if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) { 8158 word_num = vfid / 32; 8159 bit_num = vfid % 32; 8160 if (clr) 8161 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8162 else 8163 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 8164 } else { 8165 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32; 8166 bit_num = vfid % 32; 8167 if (clr) 8168 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); 8169 else 8170 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 8171 } 8172 8173 return 0; 8174 } 8175 8176 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 8177 { 8178 #define HCLGE_DESC_NUMBER 3 8179 #define HCLGE_FUNC_NUMBER_PER_DESC 6 8180 int i, j; 8181 8182 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 8183 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 8184 if (desc[i].data[j]) 8185 return false; 8186 8187 return true; 8188 } 8189 8190 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 8191 const u8 *addr, bool is_mc) 8192 { 8193 const unsigned char *mac_addr = addr; 8194 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 8195 (mac_addr[0]) | (mac_addr[1] << 8); 8196 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 8197 8198 hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8199 if (is_mc) { 8200 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 8201 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 8202 } 8203 8204 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 8205 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 8206 } 8207 8208 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 8209 struct hclge_mac_vlan_tbl_entry_cmd *req) 8210 { 8211 struct hclge_dev *hdev = vport->back; 8212 struct hclge_desc desc; 8213 u8 resp_code; 8214 u16 retval; 8215 int ret; 8216 8217 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 8218 8219 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8220 8221 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8222 if (ret) { 8223 dev_err(&hdev->pdev->dev, 8224 "del mac addr failed for cmd_send, ret =%d.\n", 8225 ret); 8226 return ret; 8227 } 8228 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8229 retval = le16_to_cpu(desc.retval); 8230 8231 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8232 HCLGE_MAC_VLAN_REMOVE); 8233 } 8234 8235 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 8236 struct hclge_mac_vlan_tbl_entry_cmd *req, 8237 struct hclge_desc *desc, 8238 bool is_mc) 8239 { 8240 struct hclge_dev *hdev = vport->back; 8241 u8 resp_code; 8242 u16 retval; 8243 int ret; 8244 8245 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 8246 if (is_mc) { 8247 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8248 memcpy(desc[0].data, 8249 req, 8250 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8251 hclge_cmd_setup_basic_desc(&desc[1], 8252 HCLGE_OPC_MAC_VLAN_ADD, 8253 true); 8254 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8255 hclge_cmd_setup_basic_desc(&desc[2], 8256 HCLGE_OPC_MAC_VLAN_ADD, 8257 true); 8258 ret = hclge_cmd_send(&hdev->hw, desc, 3); 8259 } else { 8260 memcpy(desc[0].data, 8261 req, 8262 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8263 ret = hclge_cmd_send(&hdev->hw, desc, 1); 8264 } 8265 if (ret) { 8266 dev_err(&hdev->pdev->dev, 8267 "lookup mac addr failed for cmd_send, ret =%d.\n", 8268 ret); 8269 return ret; 8270 } 8271 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 8272 retval = le16_to_cpu(desc[0].retval); 8273 8274 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 8275 HCLGE_MAC_VLAN_LKUP); 8276 } 8277 8278 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 8279 struct hclge_mac_vlan_tbl_entry_cmd *req, 8280 struct hclge_desc *mc_desc) 8281 { 8282 struct hclge_dev *hdev = vport->back; 8283 int cfg_status; 8284 u8 resp_code; 8285 u16 retval; 8286 int ret; 8287 8288 if (!mc_desc) { 8289 struct hclge_desc desc; 8290 8291 hclge_cmd_setup_basic_desc(&desc, 8292 HCLGE_OPC_MAC_VLAN_ADD, 8293 false); 8294 memcpy(desc.data, req, 8295 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8296 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8297 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 8298 retval = le16_to_cpu(desc.retval); 8299 8300 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8301 resp_code, 8302 HCLGE_MAC_VLAN_ADD); 8303 } else { 8304 hclge_comm_cmd_reuse_desc(&mc_desc[0], false); 8305 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8306 hclge_comm_cmd_reuse_desc(&mc_desc[1], false); 8307 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 8308 hclge_comm_cmd_reuse_desc(&mc_desc[2], false); 8309 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT); 8310 memcpy(mc_desc[0].data, req, 8311 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 8312 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 8313 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 8314 retval = le16_to_cpu(mc_desc[0].retval); 8315 8316 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 8317 resp_code, 8318 HCLGE_MAC_VLAN_ADD); 8319 } 8320 8321 if (ret) { 8322 dev_err(&hdev->pdev->dev, 8323 "add mac addr failed for cmd_send, ret =%d.\n", 8324 ret); 8325 return ret; 8326 } 8327 8328 return cfg_status; 8329 } 8330 8331 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 8332 u16 *allocated_size) 8333 { 8334 struct hclge_umv_spc_alc_cmd *req; 8335 struct hclge_desc desc; 8336 int ret; 8337 8338 req = (struct hclge_umv_spc_alc_cmd *)desc.data; 8339 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false); 8340 8341 req->space_size = cpu_to_le32(space_size); 8342 8343 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8344 if (ret) { 8345 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n", 8346 ret); 8347 return ret; 8348 } 8349 8350 *allocated_size = le32_to_cpu(desc.data[1]); 8351 8352 return 0; 8353 } 8354 8355 static int hclge_init_umv_space(struct hclge_dev *hdev) 8356 { 8357 u16 allocated_size = 0; 8358 int ret; 8359 8360 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size); 8361 if (ret) 8362 return ret; 8363 8364 if (allocated_size < hdev->wanted_umv_size) 8365 dev_warn(&hdev->pdev->dev, 8366 "failed to alloc umv space, want %u, get %u\n", 8367 hdev->wanted_umv_size, allocated_size); 8368 8369 hdev->max_umv_size = allocated_size; 8370 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1); 8371 hdev->share_umv_size = hdev->priv_umv_size + 8372 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8373 8374 if (hdev->ae_dev->dev_specs.mc_mac_size) 8375 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps); 8376 8377 return 0; 8378 } 8379 8380 static void hclge_reset_umv_space(struct hclge_dev *hdev) 8381 { 8382 struct hclge_vport *vport; 8383 int i; 8384 8385 for (i = 0; i < hdev->num_alloc_vport; i++) { 8386 vport = &hdev->vport[i]; 8387 vport->used_umv_num = 0; 8388 } 8389 8390 mutex_lock(&hdev->vport_lock); 8391 hdev->share_umv_size = hdev->priv_umv_size + 8392 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 8393 mutex_unlock(&hdev->vport_lock); 8394 8395 hdev->used_mc_mac_num = 0; 8396 } 8397 8398 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock) 8399 { 8400 struct hclge_dev *hdev = vport->back; 8401 bool is_full; 8402 8403 if (need_lock) 8404 mutex_lock(&hdev->vport_lock); 8405 8406 is_full = (vport->used_umv_num >= hdev->priv_umv_size && 8407 hdev->share_umv_size == 0); 8408 8409 if (need_lock) 8410 mutex_unlock(&hdev->vport_lock); 8411 8412 return is_full; 8413 } 8414 8415 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free) 8416 { 8417 struct hclge_dev *hdev = vport->back; 8418 8419 if (is_free) { 8420 if (vport->used_umv_num > hdev->priv_umv_size) 8421 hdev->share_umv_size++; 8422 8423 if (vport->used_umv_num > 0) 8424 vport->used_umv_num--; 8425 } else { 8426 if (vport->used_umv_num >= hdev->priv_umv_size && 8427 hdev->share_umv_size > 0) 8428 hdev->share_umv_size--; 8429 vport->used_umv_num++; 8430 } 8431 } 8432 8433 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list, 8434 const u8 *mac_addr) 8435 { 8436 struct hclge_mac_node *mac_node, *tmp; 8437 8438 list_for_each_entry_safe(mac_node, tmp, list, node) 8439 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 8440 return mac_node; 8441 8442 return NULL; 8443 } 8444 8445 static void hclge_update_mac_node(struct hclge_mac_node *mac_node, 8446 enum HCLGE_MAC_NODE_STATE state) 8447 { 8448 switch (state) { 8449 /* from set_rx_mode or tmp_add_list */ 8450 case HCLGE_MAC_TO_ADD: 8451 if (mac_node->state == HCLGE_MAC_TO_DEL) 8452 mac_node->state = HCLGE_MAC_ACTIVE; 8453 break; 8454 /* only from set_rx_mode */ 8455 case HCLGE_MAC_TO_DEL: 8456 if (mac_node->state == HCLGE_MAC_TO_ADD) { 8457 list_del(&mac_node->node); 8458 kfree(mac_node); 8459 } else { 8460 mac_node->state = HCLGE_MAC_TO_DEL; 8461 } 8462 break; 8463 /* only from tmp_add_list, the mac_node->state won't be 8464 * ACTIVE. 8465 */ 8466 case HCLGE_MAC_ACTIVE: 8467 if (mac_node->state == HCLGE_MAC_TO_ADD) 8468 mac_node->state = HCLGE_MAC_ACTIVE; 8469 8470 break; 8471 } 8472 } 8473 8474 int hclge_update_mac_list(struct hclge_vport *vport, 8475 enum HCLGE_MAC_NODE_STATE state, 8476 enum HCLGE_MAC_ADDR_TYPE mac_type, 8477 const unsigned char *addr) 8478 { 8479 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8480 struct hclge_dev *hdev = vport->back; 8481 struct hclge_mac_node *mac_node; 8482 struct list_head *list; 8483 8484 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8485 &vport->uc_mac_list : &vport->mc_mac_list; 8486 8487 spin_lock_bh(&vport->mac_list_lock); 8488 8489 /* if the mac addr is already in the mac list, no need to add a new 8490 * one into it, just check the mac addr state, convert it to a new 8491 * state, or just remove it, or do nothing. 8492 */ 8493 mac_node = hclge_find_mac_node(list, addr); 8494 if (mac_node) { 8495 hclge_update_mac_node(mac_node, state); 8496 spin_unlock_bh(&vport->mac_list_lock); 8497 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8498 return 0; 8499 } 8500 8501 /* if this address is never added, unnecessary to delete */ 8502 if (state == HCLGE_MAC_TO_DEL) { 8503 spin_unlock_bh(&vport->mac_list_lock); 8504 hnae3_format_mac_addr(format_mac_addr, addr); 8505 dev_err(&hdev->pdev->dev, 8506 "failed to delete address %s from mac list\n", 8507 format_mac_addr); 8508 return -ENOENT; 8509 } 8510 8511 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC); 8512 if (!mac_node) { 8513 spin_unlock_bh(&vport->mac_list_lock); 8514 return -ENOMEM; 8515 } 8516 8517 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8518 8519 mac_node->state = state; 8520 ether_addr_copy(mac_node->mac_addr, addr); 8521 list_add_tail(&mac_node->node, list); 8522 8523 spin_unlock_bh(&vport->mac_list_lock); 8524 8525 return 0; 8526 } 8527 8528 static int hclge_add_uc_addr(struct hnae3_handle *handle, 8529 const unsigned char *addr) 8530 { 8531 struct hclge_vport *vport = hclge_get_vport(handle); 8532 8533 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC, 8534 addr); 8535 } 8536 8537 int hclge_add_uc_addr_common(struct hclge_vport *vport, 8538 const unsigned char *addr) 8539 { 8540 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8541 struct hclge_dev *hdev = vport->back; 8542 struct hclge_mac_vlan_tbl_entry_cmd req; 8543 struct hclge_desc desc; 8544 u16 egress_port = 0; 8545 int ret; 8546 8547 /* mac addr check */ 8548 if (is_zero_ether_addr(addr) || 8549 is_broadcast_ether_addr(addr) || 8550 is_multicast_ether_addr(addr)) { 8551 hnae3_format_mac_addr(format_mac_addr, addr); 8552 dev_err(&hdev->pdev->dev, 8553 "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n", 8554 format_mac_addr, is_zero_ether_addr(addr), 8555 is_broadcast_ether_addr(addr), 8556 is_multicast_ether_addr(addr)); 8557 return -EINVAL; 8558 } 8559 8560 memset(&req, 0, sizeof(req)); 8561 8562 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 8563 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 8564 8565 req.egress_port = cpu_to_le16(egress_port); 8566 8567 hclge_prepare_mac_addr(&req, addr, false); 8568 8569 /* Lookup the mac address in the mac_vlan table, and add 8570 * it if the entry is inexistent. Repeated unicast entry 8571 * is not allowed in the mac vlan table. 8572 */ 8573 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 8574 if (ret == -ENOENT) { 8575 mutex_lock(&hdev->vport_lock); 8576 if (!hclge_is_umv_space_full(vport, false)) { 8577 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL); 8578 if (!ret) 8579 hclge_update_umv_space(vport, false); 8580 mutex_unlock(&hdev->vport_lock); 8581 return ret; 8582 } 8583 mutex_unlock(&hdev->vport_lock); 8584 8585 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE)) 8586 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n", 8587 hdev->priv_umv_size); 8588 8589 return -ENOSPC; 8590 } 8591 8592 /* check if we just hit the duplicate */ 8593 if (!ret) 8594 return -EEXIST; 8595 8596 return ret; 8597 } 8598 8599 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 8600 const unsigned char *addr) 8601 { 8602 struct hclge_vport *vport = hclge_get_vport(handle); 8603 8604 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC, 8605 addr); 8606 } 8607 8608 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 8609 const unsigned char *addr) 8610 { 8611 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8612 struct hclge_dev *hdev = vport->back; 8613 struct hclge_mac_vlan_tbl_entry_cmd req; 8614 int ret; 8615 8616 /* mac addr check */ 8617 if (is_zero_ether_addr(addr) || 8618 is_broadcast_ether_addr(addr) || 8619 is_multicast_ether_addr(addr)) { 8620 hnae3_format_mac_addr(format_mac_addr, addr); 8621 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n", 8622 format_mac_addr); 8623 return -EINVAL; 8624 } 8625 8626 memset(&req, 0, sizeof(req)); 8627 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 8628 hclge_prepare_mac_addr(&req, addr, false); 8629 ret = hclge_remove_mac_vlan_tbl(vport, &req); 8630 if (!ret || ret == -ENOENT) { 8631 mutex_lock(&hdev->vport_lock); 8632 hclge_update_umv_space(vport, true); 8633 mutex_unlock(&hdev->vport_lock); 8634 return 0; 8635 } 8636 8637 return ret; 8638 } 8639 8640 static int hclge_add_mc_addr(struct hnae3_handle *handle, 8641 const unsigned char *addr) 8642 { 8643 struct hclge_vport *vport = hclge_get_vport(handle); 8644 8645 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC, 8646 addr); 8647 } 8648 8649 int hclge_add_mc_addr_common(struct hclge_vport *vport, 8650 const unsigned char *addr) 8651 { 8652 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8653 struct hclge_dev *hdev = vport->back; 8654 struct hclge_mac_vlan_tbl_entry_cmd req; 8655 struct hclge_desc desc[3]; 8656 bool is_new_addr = false; 8657 int status; 8658 8659 /* mac addr check */ 8660 if (!is_multicast_ether_addr(addr)) { 8661 hnae3_format_mac_addr(format_mac_addr, addr); 8662 dev_err(&hdev->pdev->dev, 8663 "Add mc mac err! invalid mac:%s.\n", 8664 format_mac_addr); 8665 return -EINVAL; 8666 } 8667 memset(&req, 0, sizeof(req)); 8668 hclge_prepare_mac_addr(&req, addr, true); 8669 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8670 if (status) { 8671 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) && 8672 hdev->used_mc_mac_num >= 8673 hdev->ae_dev->dev_specs.mc_mac_size) 8674 goto err_no_space; 8675 8676 is_new_addr = true; 8677 8678 /* This mac addr do not exist, add new entry for it */ 8679 memset(desc[0].data, 0, sizeof(desc[0].data)); 8680 memset(desc[1].data, 0, sizeof(desc[0].data)); 8681 memset(desc[2].data, 0, sizeof(desc[0].data)); 8682 } 8683 status = hclge_update_desc_vfid(desc, vport->vport_id, false); 8684 if (status) 8685 return status; 8686 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8687 if (status == -ENOSPC) 8688 goto err_no_space; 8689 else if (!status && is_new_addr) 8690 hdev->used_mc_mac_num++; 8691 8692 return status; 8693 8694 err_no_space: 8695 /* if already overflow, not to print each time */ 8696 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) { 8697 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8698 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n"); 8699 } 8700 8701 return -ENOSPC; 8702 } 8703 8704 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 8705 const unsigned char *addr) 8706 { 8707 struct hclge_vport *vport = hclge_get_vport(handle); 8708 8709 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC, 8710 addr); 8711 } 8712 8713 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 8714 const unsigned char *addr) 8715 { 8716 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 8717 struct hclge_dev *hdev = vport->back; 8718 struct hclge_mac_vlan_tbl_entry_cmd req; 8719 enum hclge_comm_cmd_status status; 8720 struct hclge_desc desc[3]; 8721 8722 /* mac addr check */ 8723 if (!is_multicast_ether_addr(addr)) { 8724 hnae3_format_mac_addr(format_mac_addr, addr); 8725 dev_dbg(&hdev->pdev->dev, 8726 "Remove mc mac err! invalid mac:%s.\n", 8727 format_mac_addr); 8728 return -EINVAL; 8729 } 8730 8731 memset(&req, 0, sizeof(req)); 8732 hclge_prepare_mac_addr(&req, addr, true); 8733 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 8734 if (!status) { 8735 /* This mac addr exist, remove this handle's VFID for it */ 8736 status = hclge_update_desc_vfid(desc, vport->vport_id, true); 8737 if (status) 8738 return status; 8739 8740 if (hclge_is_all_function_id_zero(desc)) { 8741 /* All the vfid is zero, so need to delete this entry */ 8742 status = hclge_remove_mac_vlan_tbl(vport, &req); 8743 if (!status) 8744 hdev->used_mc_mac_num--; 8745 } else { 8746 /* Not all the vfid is zero, update the vfid */ 8747 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 8748 } 8749 } else if (status == -ENOENT) { 8750 status = 0; 8751 } 8752 8753 return status; 8754 } 8755 8756 static void hclge_sync_vport_mac_list(struct hclge_vport *vport, 8757 struct list_head *list, 8758 enum HCLGE_MAC_ADDR_TYPE mac_type) 8759 { 8760 int (*sync)(struct hclge_vport *vport, const unsigned char *addr); 8761 struct hclge_mac_node *mac_node, *tmp; 8762 int ret; 8763 8764 if (mac_type == HCLGE_MAC_ADDR_UC) 8765 sync = hclge_add_uc_addr_common; 8766 else 8767 sync = hclge_add_mc_addr_common; 8768 8769 list_for_each_entry_safe(mac_node, tmp, list, node) { 8770 ret = sync(vport, mac_node->mac_addr); 8771 if (!ret) { 8772 mac_node->state = HCLGE_MAC_ACTIVE; 8773 } else { 8774 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8775 &vport->state); 8776 8777 /* If one unicast mac address is existing in hardware, 8778 * we need to try whether other unicast mac addresses 8779 * are new addresses that can be added. 8780 * Multicast mac address can be reusable, even though 8781 * there is no space to add new multicast mac address, 8782 * we should check whether other mac addresses are 8783 * existing in hardware for reuse. 8784 */ 8785 if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) || 8786 (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC)) 8787 break; 8788 } 8789 } 8790 } 8791 8792 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport, 8793 struct list_head *list, 8794 enum HCLGE_MAC_ADDR_TYPE mac_type) 8795 { 8796 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 8797 struct hclge_mac_node *mac_node, *tmp; 8798 int ret; 8799 8800 if (mac_type == HCLGE_MAC_ADDR_UC) 8801 unsync = hclge_rm_uc_addr_common; 8802 else 8803 unsync = hclge_rm_mc_addr_common; 8804 8805 list_for_each_entry_safe(mac_node, tmp, list, node) { 8806 ret = unsync(vport, mac_node->mac_addr); 8807 if (!ret || ret == -ENOENT) { 8808 list_del(&mac_node->node); 8809 kfree(mac_node); 8810 } else { 8811 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 8812 &vport->state); 8813 break; 8814 } 8815 } 8816 } 8817 8818 static bool hclge_sync_from_add_list(struct list_head *add_list, 8819 struct list_head *mac_list) 8820 { 8821 struct hclge_mac_node *mac_node, *tmp, *new_node; 8822 bool all_added = true; 8823 8824 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 8825 if (mac_node->state == HCLGE_MAC_TO_ADD) 8826 all_added = false; 8827 8828 /* if the mac address from tmp_add_list is not in the 8829 * uc/mc_mac_list, it means have received a TO_DEL request 8830 * during the time window of adding the mac address into mac 8831 * table. if mac_node state is ACTIVE, then change it to TO_DEL, 8832 * then it will be removed at next time. else it must be TO_ADD, 8833 * this address hasn't been added into mac table, 8834 * so just remove the mac node. 8835 */ 8836 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8837 if (new_node) { 8838 hclge_update_mac_node(new_node, mac_node->state); 8839 list_del(&mac_node->node); 8840 kfree(mac_node); 8841 } else if (mac_node->state == HCLGE_MAC_ACTIVE) { 8842 mac_node->state = HCLGE_MAC_TO_DEL; 8843 list_move_tail(&mac_node->node, mac_list); 8844 } else { 8845 list_del(&mac_node->node); 8846 kfree(mac_node); 8847 } 8848 } 8849 8850 return all_added; 8851 } 8852 8853 static void hclge_sync_from_del_list(struct list_head *del_list, 8854 struct list_head *mac_list) 8855 { 8856 struct hclge_mac_node *mac_node, *tmp, *new_node; 8857 8858 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 8859 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 8860 if (new_node) { 8861 /* If the mac addr exists in the mac list, it means 8862 * received a new TO_ADD request during the time window 8863 * of configuring the mac address. For the mac node 8864 * state is TO_ADD, and the address is already in the 8865 * in the hardware(due to delete fail), so we just need 8866 * to change the mac node state to ACTIVE. 8867 */ 8868 new_node->state = HCLGE_MAC_ACTIVE; 8869 list_del(&mac_node->node); 8870 kfree(mac_node); 8871 } else { 8872 list_move_tail(&mac_node->node, mac_list); 8873 } 8874 } 8875 } 8876 8877 static void hclge_update_overflow_flags(struct hclge_vport *vport, 8878 enum HCLGE_MAC_ADDR_TYPE mac_type, 8879 bool is_all_added) 8880 { 8881 if (mac_type == HCLGE_MAC_ADDR_UC) { 8882 if (is_all_added) 8883 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE; 8884 else 8885 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE; 8886 } else { 8887 if (is_all_added) 8888 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE; 8889 else 8890 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 8891 } 8892 } 8893 8894 static void hclge_sync_vport_mac_table(struct hclge_vport *vport, 8895 enum HCLGE_MAC_ADDR_TYPE mac_type) 8896 { 8897 struct hclge_mac_node *mac_node, *tmp, *new_node; 8898 struct list_head tmp_add_list, tmp_del_list; 8899 struct list_head *list; 8900 bool all_added; 8901 8902 INIT_LIST_HEAD(&tmp_add_list); 8903 INIT_LIST_HEAD(&tmp_del_list); 8904 8905 /* move the mac addr to the tmp_add_list and tmp_del_list, then 8906 * we can add/delete these mac addr outside the spin lock 8907 */ 8908 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 8909 &vport->uc_mac_list : &vport->mc_mac_list; 8910 8911 spin_lock_bh(&vport->mac_list_lock); 8912 8913 list_for_each_entry_safe(mac_node, tmp, list, node) { 8914 switch (mac_node->state) { 8915 case HCLGE_MAC_TO_DEL: 8916 list_move_tail(&mac_node->node, &tmp_del_list); 8917 break; 8918 case HCLGE_MAC_TO_ADD: 8919 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 8920 if (!new_node) 8921 goto stop_traverse; 8922 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 8923 new_node->state = mac_node->state; 8924 list_add_tail(&new_node->node, &tmp_add_list); 8925 break; 8926 default: 8927 break; 8928 } 8929 } 8930 8931 stop_traverse: 8932 spin_unlock_bh(&vport->mac_list_lock); 8933 8934 /* delete first, in order to get max mac table space for adding */ 8935 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 8936 hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type); 8937 8938 /* if some mac addresses were added/deleted fail, move back to the 8939 * mac_list, and retry at next time. 8940 */ 8941 spin_lock_bh(&vport->mac_list_lock); 8942 8943 hclge_sync_from_del_list(&tmp_del_list, list); 8944 all_added = hclge_sync_from_add_list(&tmp_add_list, list); 8945 8946 spin_unlock_bh(&vport->mac_list_lock); 8947 8948 hclge_update_overflow_flags(vport, mac_type, all_added); 8949 } 8950 8951 static bool hclge_need_sync_mac_table(struct hclge_vport *vport) 8952 { 8953 struct hclge_dev *hdev = vport->back; 8954 8955 if (test_bit(vport->vport_id, hdev->vport_config_block)) 8956 return false; 8957 8958 if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state)) 8959 return true; 8960 8961 return false; 8962 } 8963 8964 static void hclge_sync_mac_table(struct hclge_dev *hdev) 8965 { 8966 int i; 8967 8968 for (i = 0; i < hdev->num_alloc_vport; i++) { 8969 struct hclge_vport *vport = &hdev->vport[i]; 8970 8971 if (!hclge_need_sync_mac_table(vport)) 8972 continue; 8973 8974 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC); 8975 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC); 8976 } 8977 } 8978 8979 static void hclge_build_del_list(struct list_head *list, 8980 bool is_del_list, 8981 struct list_head *tmp_del_list) 8982 { 8983 struct hclge_mac_node *mac_cfg, *tmp; 8984 8985 list_for_each_entry_safe(mac_cfg, tmp, list, node) { 8986 switch (mac_cfg->state) { 8987 case HCLGE_MAC_TO_DEL: 8988 case HCLGE_MAC_ACTIVE: 8989 list_move_tail(&mac_cfg->node, tmp_del_list); 8990 break; 8991 case HCLGE_MAC_TO_ADD: 8992 if (is_del_list) { 8993 list_del(&mac_cfg->node); 8994 kfree(mac_cfg); 8995 } 8996 break; 8997 } 8998 } 8999 } 9000 9001 static void hclge_unsync_del_list(struct hclge_vport *vport, 9002 int (*unsync)(struct hclge_vport *vport, 9003 const unsigned char *addr), 9004 bool is_del_list, 9005 struct list_head *tmp_del_list) 9006 { 9007 struct hclge_mac_node *mac_cfg, *tmp; 9008 int ret; 9009 9010 list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) { 9011 ret = unsync(vport, mac_cfg->mac_addr); 9012 if (!ret || ret == -ENOENT) { 9013 /* clear all mac addr from hardware, but remain these 9014 * mac addr in the mac list, and restore them after 9015 * vf reset finished. 9016 */ 9017 if (!is_del_list && 9018 mac_cfg->state == HCLGE_MAC_ACTIVE) { 9019 mac_cfg->state = HCLGE_MAC_TO_ADD; 9020 } else { 9021 list_del(&mac_cfg->node); 9022 kfree(mac_cfg); 9023 } 9024 } else if (is_del_list) { 9025 mac_cfg->state = HCLGE_MAC_TO_DEL; 9026 } 9027 } 9028 } 9029 9030 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 9031 enum HCLGE_MAC_ADDR_TYPE mac_type) 9032 { 9033 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 9034 struct hclge_dev *hdev = vport->back; 9035 struct list_head tmp_del_list, *list; 9036 9037 if (mac_type == HCLGE_MAC_ADDR_UC) { 9038 list = &vport->uc_mac_list; 9039 unsync = hclge_rm_uc_addr_common; 9040 } else { 9041 list = &vport->mc_mac_list; 9042 unsync = hclge_rm_mc_addr_common; 9043 } 9044 9045 INIT_LIST_HEAD(&tmp_del_list); 9046 9047 if (!is_del_list) 9048 set_bit(vport->vport_id, hdev->vport_config_block); 9049 9050 spin_lock_bh(&vport->mac_list_lock); 9051 9052 hclge_build_del_list(list, is_del_list, &tmp_del_list); 9053 9054 spin_unlock_bh(&vport->mac_list_lock); 9055 9056 hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list); 9057 9058 spin_lock_bh(&vport->mac_list_lock); 9059 9060 hclge_sync_from_del_list(&tmp_del_list, list); 9061 9062 spin_unlock_bh(&vport->mac_list_lock); 9063 } 9064 9065 /* remove all mac address when uninitailize */ 9066 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport, 9067 enum HCLGE_MAC_ADDR_TYPE mac_type) 9068 { 9069 struct hclge_mac_node *mac_node, *tmp; 9070 struct hclge_dev *hdev = vport->back; 9071 struct list_head tmp_del_list, *list; 9072 9073 INIT_LIST_HEAD(&tmp_del_list); 9074 9075 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 9076 &vport->uc_mac_list : &vport->mc_mac_list; 9077 9078 spin_lock_bh(&vport->mac_list_lock); 9079 9080 list_for_each_entry_safe(mac_node, tmp, list, node) { 9081 switch (mac_node->state) { 9082 case HCLGE_MAC_TO_DEL: 9083 case HCLGE_MAC_ACTIVE: 9084 list_move_tail(&mac_node->node, &tmp_del_list); 9085 break; 9086 case HCLGE_MAC_TO_ADD: 9087 list_del(&mac_node->node); 9088 kfree(mac_node); 9089 break; 9090 } 9091 } 9092 9093 spin_unlock_bh(&vport->mac_list_lock); 9094 9095 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 9096 9097 if (!list_empty(&tmp_del_list)) 9098 dev_warn(&hdev->pdev->dev, 9099 "uninit %s mac list for vport %u not completely.\n", 9100 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc", 9101 vport->vport_id); 9102 9103 list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) { 9104 list_del(&mac_node->node); 9105 kfree(mac_node); 9106 } 9107 } 9108 9109 static void hclge_uninit_mac_table(struct hclge_dev *hdev) 9110 { 9111 struct hclge_vport *vport; 9112 int i; 9113 9114 for (i = 0; i < hdev->num_alloc_vport; i++) { 9115 vport = &hdev->vport[i]; 9116 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC); 9117 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC); 9118 } 9119 } 9120 9121 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 9122 u16 cmdq_resp, u8 resp_code) 9123 { 9124 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 9125 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 9126 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 9127 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 9128 9129 int return_status; 9130 9131 if (cmdq_resp) { 9132 dev_err(&hdev->pdev->dev, 9133 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 9134 cmdq_resp); 9135 return -EIO; 9136 } 9137 9138 switch (resp_code) { 9139 case HCLGE_ETHERTYPE_SUCCESS_ADD: 9140 case HCLGE_ETHERTYPE_ALREADY_ADD: 9141 return_status = 0; 9142 break; 9143 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 9144 dev_err(&hdev->pdev->dev, 9145 "add mac ethertype failed for manager table overflow.\n"); 9146 return_status = -EIO; 9147 break; 9148 case HCLGE_ETHERTYPE_KEY_CONFLICT: 9149 dev_err(&hdev->pdev->dev, 9150 "add mac ethertype failed for key conflict.\n"); 9151 return_status = -EIO; 9152 break; 9153 default: 9154 dev_err(&hdev->pdev->dev, 9155 "add mac ethertype failed for undefined, code=%u.\n", 9156 resp_code); 9157 return_status = -EIO; 9158 } 9159 9160 return return_status; 9161 } 9162 9163 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf, 9164 u8 *mac_addr) 9165 { 9166 struct hclge_vport *vport = hclge_get_vport(handle); 9167 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9168 struct hclge_dev *hdev = vport->back; 9169 9170 vport = hclge_get_vf_vport(hdev, vf); 9171 if (!vport) 9172 return -EINVAL; 9173 9174 hnae3_format_mac_addr(format_mac_addr, mac_addr); 9175 if (ether_addr_equal(mac_addr, vport->vf_info.mac)) { 9176 dev_info(&hdev->pdev->dev, 9177 "Specified MAC(=%s) is same as before, no change committed!\n", 9178 format_mac_addr); 9179 return 0; 9180 } 9181 9182 ether_addr_copy(vport->vf_info.mac, mac_addr); 9183 9184 /* there is a timewindow for PF to know VF unalive, it may 9185 * cause send mailbox fail, but it doesn't matter, VF will 9186 * query it when reinit. 9187 */ 9188 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) { 9189 dev_info(&hdev->pdev->dev, 9190 "MAC of VF %d has been set to %s, and it will be reinitialized!\n", 9191 vf, format_mac_addr); 9192 (void)hclge_inform_reset_assert_to_vf(vport); 9193 return 0; 9194 } 9195 9196 dev_info(&hdev->pdev->dev, "MAC of VF %d has been set to %s\n", 9197 vf, format_mac_addr); 9198 return 0; 9199 } 9200 9201 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 9202 const struct hclge_mac_mgr_tbl_entry_cmd *req) 9203 { 9204 struct hclge_desc desc; 9205 u8 resp_code; 9206 u16 retval; 9207 int ret; 9208 9209 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 9210 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 9211 9212 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9213 if (ret) { 9214 dev_err(&hdev->pdev->dev, 9215 "add mac ethertype failed for cmd_send, ret =%d.\n", 9216 ret); 9217 return ret; 9218 } 9219 9220 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 9221 retval = le16_to_cpu(desc.retval); 9222 9223 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 9224 } 9225 9226 static int init_mgr_tbl(struct hclge_dev *hdev) 9227 { 9228 int ret; 9229 int i; 9230 9231 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 9232 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 9233 if (ret) { 9234 dev_err(&hdev->pdev->dev, 9235 "add mac ethertype failed, ret =%d.\n", 9236 ret); 9237 return ret; 9238 } 9239 } 9240 9241 return 0; 9242 } 9243 9244 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 9245 { 9246 struct hclge_vport *vport = hclge_get_vport(handle); 9247 struct hclge_dev *hdev = vport->back; 9248 9249 ether_addr_copy(p, hdev->hw.mac.mac_addr); 9250 } 9251 9252 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 9253 const u8 *old_addr, const u8 *new_addr) 9254 { 9255 struct list_head *list = &vport->uc_mac_list; 9256 struct hclge_mac_node *old_node, *new_node; 9257 9258 new_node = hclge_find_mac_node(list, new_addr); 9259 if (!new_node) { 9260 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC); 9261 if (!new_node) 9262 return -ENOMEM; 9263 9264 new_node->state = HCLGE_MAC_TO_ADD; 9265 ether_addr_copy(new_node->mac_addr, new_addr); 9266 list_add(&new_node->node, list); 9267 } else { 9268 if (new_node->state == HCLGE_MAC_TO_DEL) 9269 new_node->state = HCLGE_MAC_ACTIVE; 9270 9271 /* make sure the new addr is in the list head, avoid dev 9272 * addr may be not re-added into mac table for the umv space 9273 * limitation after global/imp reset which will clear mac 9274 * table by hardware. 9275 */ 9276 list_move(&new_node->node, list); 9277 } 9278 9279 if (old_addr && !ether_addr_equal(old_addr, new_addr)) { 9280 old_node = hclge_find_mac_node(list, old_addr); 9281 if (old_node) { 9282 if (old_node->state == HCLGE_MAC_TO_ADD) { 9283 list_del(&old_node->node); 9284 kfree(old_node); 9285 } else { 9286 old_node->state = HCLGE_MAC_TO_DEL; 9287 } 9288 } 9289 } 9290 9291 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 9292 9293 return 0; 9294 } 9295 9296 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p, 9297 bool is_first) 9298 { 9299 const unsigned char *new_addr = (const unsigned char *)p; 9300 struct hclge_vport *vport = hclge_get_vport(handle); 9301 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 9302 struct hclge_dev *hdev = vport->back; 9303 unsigned char *old_addr = NULL; 9304 int ret; 9305 9306 /* mac addr check */ 9307 if (is_zero_ether_addr(new_addr) || 9308 is_broadcast_ether_addr(new_addr) || 9309 is_multicast_ether_addr(new_addr)) { 9310 hnae3_format_mac_addr(format_mac_addr, new_addr); 9311 dev_err(&hdev->pdev->dev, 9312 "change uc mac err! invalid mac: %s.\n", 9313 format_mac_addr); 9314 return -EINVAL; 9315 } 9316 9317 ret = hclge_pause_addr_cfg(hdev, new_addr); 9318 if (ret) { 9319 dev_err(&hdev->pdev->dev, 9320 "failed to configure mac pause address, ret = %d\n", 9321 ret); 9322 return ret; 9323 } 9324 9325 if (!is_first) 9326 old_addr = hdev->hw.mac.mac_addr; 9327 9328 spin_lock_bh(&vport->mac_list_lock); 9329 ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr); 9330 if (ret) { 9331 hnae3_format_mac_addr(format_mac_addr, new_addr); 9332 dev_err(&hdev->pdev->dev, 9333 "failed to change the mac addr:%s, ret = %d\n", 9334 format_mac_addr, ret); 9335 spin_unlock_bh(&vport->mac_list_lock); 9336 9337 if (!is_first) 9338 hclge_pause_addr_cfg(hdev, old_addr); 9339 9340 return ret; 9341 } 9342 /* we must update dev addr with spin lock protect, preventing dev addr 9343 * being removed by set_rx_mode path. 9344 */ 9345 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 9346 spin_unlock_bh(&vport->mac_list_lock); 9347 9348 hclge_task_schedule(hdev, 0); 9349 9350 return 0; 9351 } 9352 9353 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd) 9354 { 9355 struct mii_ioctl_data *data = if_mii(ifr); 9356 9357 if (!hnae3_dev_phy_imp_supported(hdev)) 9358 return -EOPNOTSUPP; 9359 9360 switch (cmd) { 9361 case SIOCGMIIPHY: 9362 data->phy_id = hdev->hw.mac.phy_addr; 9363 /* this command reads phy id and register at the same time */ 9364 fallthrough; 9365 case SIOCGMIIREG: 9366 data->val_out = hclge_read_phy_reg(hdev, data->reg_num); 9367 return 0; 9368 9369 case SIOCSMIIREG: 9370 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in); 9371 default: 9372 return -EOPNOTSUPP; 9373 } 9374 } 9375 9376 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr, 9377 int cmd) 9378 { 9379 struct hclge_vport *vport = hclge_get_vport(handle); 9380 struct hclge_dev *hdev = vport->back; 9381 9382 switch (cmd) { 9383 case SIOCGHWTSTAMP: 9384 return hclge_ptp_get_cfg(hdev, ifr); 9385 case SIOCSHWTSTAMP: 9386 return hclge_ptp_set_cfg(hdev, ifr); 9387 default: 9388 if (!hdev->hw.mac.phydev) 9389 return hclge_mii_ioctl(hdev, ifr, cmd); 9390 } 9391 9392 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd); 9393 } 9394 9395 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id, 9396 bool bypass_en) 9397 { 9398 struct hclge_port_vlan_filter_bypass_cmd *req; 9399 struct hclge_desc desc; 9400 int ret; 9401 9402 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false); 9403 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 9404 req->vf_id = vf_id; 9405 hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B, 9406 bypass_en ? 1 : 0); 9407 9408 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9409 if (ret) 9410 dev_err(&hdev->pdev->dev, 9411 "failed to set vport%u port vlan filter bypass state, ret = %d.\n", 9412 vf_id, ret); 9413 9414 return ret; 9415 } 9416 9417 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 9418 u8 fe_type, bool filter_en, u8 vf_id) 9419 { 9420 struct hclge_vlan_filter_ctrl_cmd *req; 9421 struct hclge_desc desc; 9422 int ret; 9423 9424 /* read current vlan filter parameter */ 9425 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 9426 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 9427 req->vlan_type = vlan_type; 9428 req->vf_id = vf_id; 9429 9430 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9431 if (ret) { 9432 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n", 9433 vf_id, ret); 9434 return ret; 9435 } 9436 9437 /* modify and write new config parameter */ 9438 hclge_comm_cmd_reuse_desc(&desc, false); 9439 req->vlan_fe = filter_en ? 9440 (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type); 9441 9442 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9443 if (ret) 9444 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n", 9445 vf_id, ret); 9446 9447 return ret; 9448 } 9449 9450 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable) 9451 { 9452 struct hclge_dev *hdev = vport->back; 9453 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 9454 int ret; 9455 9456 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9457 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9458 HCLGE_FILTER_FE_EGRESS_V1_B, 9459 enable, vport->vport_id); 9460 9461 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9462 HCLGE_FILTER_FE_EGRESS, enable, 9463 vport->vport_id); 9464 if (ret) 9465 return ret; 9466 9467 if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) { 9468 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id, 9469 !enable); 9470 } else if (!vport->vport_id) { 9471 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 9472 enable = false; 9473 9474 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9475 HCLGE_FILTER_FE_INGRESS, 9476 enable, 0); 9477 } 9478 9479 return ret; 9480 } 9481 9482 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport) 9483 { 9484 struct hnae3_handle *handle = &vport->nic; 9485 struct hclge_vport_vlan_cfg *vlan, *tmp; 9486 struct hclge_dev *hdev = vport->back; 9487 9488 if (vport->vport_id) { 9489 if (vport->port_base_vlan_cfg.state != 9490 HNAE3_PORT_BASE_VLAN_DISABLE) 9491 return true; 9492 9493 if (vport->vf_info.trusted && vport->vf_info.request_uc_en) 9494 return false; 9495 } else if (handle->netdev_flags & HNAE3_USER_UPE) { 9496 return false; 9497 } 9498 9499 if (!vport->req_vlan_fltr_en) 9500 return false; 9501 9502 /* compatible with former device, always enable vlan filter */ 9503 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 9504 return true; 9505 9506 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) 9507 if (vlan->vlan_id != 0) 9508 return true; 9509 9510 return false; 9511 } 9512 9513 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) 9514 { 9515 struct hclge_dev *hdev = vport->back; 9516 bool need_en; 9517 int ret; 9518 9519 mutex_lock(&hdev->vport_lock); 9520 9521 vport->req_vlan_fltr_en = request_en; 9522 9523 need_en = hclge_need_enable_vport_vlan_filter(vport); 9524 if (need_en == vport->cur_vlan_fltr_en) { 9525 mutex_unlock(&hdev->vport_lock); 9526 return 0; 9527 } 9528 9529 ret = hclge_set_vport_vlan_filter(vport, need_en); 9530 if (ret) { 9531 mutex_unlock(&hdev->vport_lock); 9532 return ret; 9533 } 9534 9535 vport->cur_vlan_fltr_en = need_en; 9536 9537 mutex_unlock(&hdev->vport_lock); 9538 9539 return 0; 9540 } 9541 9542 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 9543 { 9544 struct hclge_vport *vport = hclge_get_vport(handle); 9545 9546 return hclge_enable_vport_vlan_filter(vport, enable); 9547 } 9548 9549 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid, 9550 bool is_kill, u16 vlan, 9551 struct hclge_desc *desc) 9552 { 9553 struct hclge_vlan_filter_vf_cfg_cmd *req0; 9554 struct hclge_vlan_filter_vf_cfg_cmd *req1; 9555 u8 vf_byte_val; 9556 u8 vf_byte_off; 9557 int ret; 9558 9559 hclge_cmd_setup_basic_desc(&desc[0], 9560 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9561 hclge_cmd_setup_basic_desc(&desc[1], 9562 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 9563 9564 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 9565 9566 vf_byte_off = vfid / 8; 9567 vf_byte_val = 1 << (vfid % 8); 9568 9569 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9570 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 9571 9572 req0->vlan_id = cpu_to_le16(vlan); 9573 req0->vlan_cfg = is_kill; 9574 9575 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 9576 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 9577 else 9578 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 9579 9580 ret = hclge_cmd_send(&hdev->hw, desc, 2); 9581 if (ret) { 9582 dev_err(&hdev->pdev->dev, 9583 "Send vf vlan command fail, ret =%d.\n", 9584 ret); 9585 return ret; 9586 } 9587 9588 return 0; 9589 } 9590 9591 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid, 9592 bool is_kill, struct hclge_desc *desc) 9593 { 9594 struct hclge_vlan_filter_vf_cfg_cmd *req; 9595 9596 req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 9597 9598 if (!is_kill) { 9599 #define HCLGE_VF_VLAN_NO_ENTRY 2 9600 if (!req->resp_code || req->resp_code == 1) 9601 return 0; 9602 9603 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 9604 set_bit(vfid, hdev->vf_vlan_full); 9605 dev_warn(&hdev->pdev->dev, 9606 "vf vlan table is full, vf vlan filter is disabled\n"); 9607 return 0; 9608 } 9609 9610 dev_err(&hdev->pdev->dev, 9611 "Add vf vlan filter fail, ret =%u.\n", 9612 req->resp_code); 9613 } else { 9614 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 9615 if (!req->resp_code) 9616 return 0; 9617 9618 /* vf vlan filter is disabled when vf vlan table is full, 9619 * then new vlan id will not be added into vf vlan table. 9620 * Just return 0 without warning, avoid massive verbose 9621 * print logs when unload. 9622 */ 9623 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) 9624 return 0; 9625 9626 dev_err(&hdev->pdev->dev, 9627 "Kill vf vlan filter fail, ret =%u.\n", 9628 req->resp_code); 9629 } 9630 9631 return -EIO; 9632 } 9633 9634 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid, 9635 bool is_kill, u16 vlan) 9636 { 9637 struct hclge_vport *vport = &hdev->vport[vfid]; 9638 struct hclge_desc desc[2]; 9639 int ret; 9640 9641 /* if vf vlan table is full, firmware will close vf vlan filter, it 9642 * is unable and unnecessary to add new vlan id to vf vlan filter. 9643 * If spoof check is enable, and vf vlan is full, it shouldn't add 9644 * new vlan, because tx packets with these vlan id will be dropped. 9645 */ 9646 if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) { 9647 if (vport->vf_info.spoofchk && vlan) { 9648 dev_err(&hdev->pdev->dev, 9649 "Can't add vlan due to spoof check is on and vf vlan table is full\n"); 9650 return -EPERM; 9651 } 9652 return 0; 9653 } 9654 9655 ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc); 9656 if (ret) 9657 return ret; 9658 9659 return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc); 9660 } 9661 9662 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 9663 u16 vlan_id, bool is_kill) 9664 { 9665 struct hclge_vlan_filter_pf_cfg_cmd *req; 9666 struct hclge_desc desc; 9667 u8 vlan_offset_byte_val; 9668 u8 vlan_offset_byte; 9669 u8 vlan_offset_160; 9670 int ret; 9671 9672 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 9673 9674 vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP; 9675 vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) / 9676 HCLGE_VLAN_BYTE_SIZE; 9677 vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE); 9678 9679 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 9680 req->vlan_offset = vlan_offset_160; 9681 req->vlan_cfg = is_kill; 9682 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 9683 9684 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9685 if (ret) 9686 dev_err(&hdev->pdev->dev, 9687 "port vlan command, send fail, ret =%d.\n", ret); 9688 return ret; 9689 } 9690 9691 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id, 9692 u16 vlan_id, bool is_kill) 9693 { 9694 /* vlan 0 may be added twice when 8021q module is enabled */ 9695 if (!is_kill && !vlan_id && 9696 test_bit(vport_id, hdev->vlan_table[vlan_id])) 9697 return false; 9698 9699 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 9700 dev_warn(&hdev->pdev->dev, 9701 "Add port vlan failed, vport %u is already in vlan %u\n", 9702 vport_id, vlan_id); 9703 return false; 9704 } 9705 9706 if (is_kill && 9707 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 9708 dev_warn(&hdev->pdev->dev, 9709 "Delete port vlan failed, vport %u is not in vlan %u\n", 9710 vport_id, vlan_id); 9711 return false; 9712 } 9713 9714 return true; 9715 } 9716 9717 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 9718 u16 vport_id, u16 vlan_id, 9719 bool is_kill) 9720 { 9721 u16 vport_idx, vport_num = 0; 9722 int ret; 9723 9724 if (is_kill && !vlan_id) 9725 return 0; 9726 9727 if (vlan_id >= VLAN_N_VID) 9728 return -EINVAL; 9729 9730 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id); 9731 if (ret) { 9732 dev_err(&hdev->pdev->dev, 9733 "Set %u vport vlan filter config fail, ret =%d.\n", 9734 vport_id, ret); 9735 return ret; 9736 } 9737 9738 if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill)) 9739 return 0; 9740 9741 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 9742 vport_num++; 9743 9744 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 9745 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 9746 is_kill); 9747 9748 return ret; 9749 } 9750 9751 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 9752 { 9753 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 9754 struct hclge_vport_vtag_tx_cfg_cmd *req; 9755 struct hclge_dev *hdev = vport->back; 9756 struct hclge_desc desc; 9757 u16 bmap_index; 9758 int status; 9759 9760 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 9761 9762 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 9763 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 9764 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 9765 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 9766 vcfg->accept_tag1 ? 1 : 0); 9767 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 9768 vcfg->accept_untag1 ? 1 : 0); 9769 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 9770 vcfg->accept_tag2 ? 1 : 0); 9771 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 9772 vcfg->accept_untag2 ? 1 : 0); 9773 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 9774 vcfg->insert_tag1_en ? 1 : 0); 9775 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 9776 vcfg->insert_tag2_en ? 1 : 0); 9777 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B, 9778 vcfg->tag_shift_mode_en ? 1 : 0); 9779 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 9780 9781 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9782 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9783 HCLGE_VF_NUM_PER_BYTE; 9784 req->vf_bitmap[bmap_index] = 9785 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9786 9787 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9788 if (status) 9789 dev_err(&hdev->pdev->dev, 9790 "Send port txvlan cfg command fail, ret =%d\n", 9791 status); 9792 9793 return status; 9794 } 9795 9796 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 9797 { 9798 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 9799 struct hclge_vport_vtag_rx_cfg_cmd *req; 9800 struct hclge_dev *hdev = vport->back; 9801 struct hclge_desc desc; 9802 u16 bmap_index; 9803 int status; 9804 9805 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 9806 9807 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 9808 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 9809 vcfg->strip_tag1_en ? 1 : 0); 9810 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 9811 vcfg->strip_tag2_en ? 1 : 0); 9812 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 9813 vcfg->vlan1_vlan_prionly ? 1 : 0); 9814 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 9815 vcfg->vlan2_vlan_prionly ? 1 : 0); 9816 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B, 9817 vcfg->strip_tag1_discard_en ? 1 : 0); 9818 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B, 9819 vcfg->strip_tag2_discard_en ? 1 : 0); 9820 9821 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 9822 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 9823 HCLGE_VF_NUM_PER_BYTE; 9824 req->vf_bitmap[bmap_index] = 9825 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 9826 9827 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9828 if (status) 9829 dev_err(&hdev->pdev->dev, 9830 "Send port rxvlan cfg command fail, ret =%d\n", 9831 status); 9832 9833 return status; 9834 } 9835 9836 static int hclge_vlan_offload_cfg(struct hclge_vport *vport, 9837 u16 port_base_vlan_state, 9838 u16 vlan_tag, u8 qos) 9839 { 9840 int ret; 9841 9842 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9843 vport->txvlan_cfg.accept_tag1 = true; 9844 vport->txvlan_cfg.insert_tag1_en = false; 9845 vport->txvlan_cfg.default_tag1 = 0; 9846 } else { 9847 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev); 9848 9849 vport->txvlan_cfg.accept_tag1 = 9850 ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3; 9851 vport->txvlan_cfg.insert_tag1_en = true; 9852 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) | 9853 vlan_tag; 9854 } 9855 9856 vport->txvlan_cfg.accept_untag1 = true; 9857 9858 /* accept_tag2 and accept_untag2 are not supported on 9859 * pdev revision(0x20), new revision support them, 9860 * this two fields can not be configured by user. 9861 */ 9862 vport->txvlan_cfg.accept_tag2 = true; 9863 vport->txvlan_cfg.accept_untag2 = true; 9864 vport->txvlan_cfg.insert_tag2_en = false; 9865 vport->txvlan_cfg.default_tag2 = 0; 9866 vport->txvlan_cfg.tag_shift_mode_en = true; 9867 9868 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 9869 vport->rxvlan_cfg.strip_tag1_en = false; 9870 vport->rxvlan_cfg.strip_tag2_en = 9871 vport->rxvlan_cfg.rx_vlan_offload_en; 9872 vport->rxvlan_cfg.strip_tag2_discard_en = false; 9873 } else { 9874 vport->rxvlan_cfg.strip_tag1_en = 9875 vport->rxvlan_cfg.rx_vlan_offload_en; 9876 vport->rxvlan_cfg.strip_tag2_en = true; 9877 vport->rxvlan_cfg.strip_tag2_discard_en = true; 9878 } 9879 9880 vport->rxvlan_cfg.strip_tag1_discard_en = false; 9881 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 9882 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 9883 9884 ret = hclge_set_vlan_tx_offload_cfg(vport); 9885 if (ret) 9886 return ret; 9887 9888 return hclge_set_vlan_rx_offload_cfg(vport); 9889 } 9890 9891 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 9892 { 9893 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 9894 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 9895 struct hclge_desc desc; 9896 int status; 9897 9898 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 9899 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 9900 rx_req->ot_fst_vlan_type = 9901 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 9902 rx_req->ot_sec_vlan_type = 9903 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 9904 rx_req->in_fst_vlan_type = 9905 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 9906 rx_req->in_sec_vlan_type = 9907 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 9908 9909 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9910 if (status) { 9911 dev_err(&hdev->pdev->dev, 9912 "Send rxvlan protocol type command fail, ret =%d\n", 9913 status); 9914 return status; 9915 } 9916 9917 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 9918 9919 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data; 9920 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 9921 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 9922 9923 status = hclge_cmd_send(&hdev->hw, &desc, 1); 9924 if (status) 9925 dev_err(&hdev->pdev->dev, 9926 "Send txvlan protocol type command fail, ret =%d\n", 9927 status); 9928 9929 return status; 9930 } 9931 9932 static int hclge_init_vlan_filter(struct hclge_dev *hdev) 9933 { 9934 struct hclge_vport *vport; 9935 int ret; 9936 int i; 9937 9938 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9939 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9940 HCLGE_FILTER_FE_EGRESS_V1_B, 9941 true, 0); 9942 9943 /* for revision 0x21, vf vlan filter is per function */ 9944 for (i = 0; i < hdev->num_alloc_vport; i++) { 9945 vport = &hdev->vport[i]; 9946 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9947 HCLGE_FILTER_FE_EGRESS, true, 9948 vport->vport_id); 9949 if (ret) 9950 return ret; 9951 vport->cur_vlan_fltr_en = true; 9952 } 9953 9954 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 9955 HCLGE_FILTER_FE_INGRESS, true, 0); 9956 } 9957 9958 static int hclge_init_vlan_type(struct hclge_dev *hdev) 9959 { 9960 hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q; 9961 hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q; 9962 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q; 9963 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q; 9964 hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q; 9965 hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q; 9966 9967 return hclge_set_vlan_protocol_type(hdev); 9968 } 9969 9970 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev) 9971 { 9972 struct hclge_port_base_vlan_config *cfg; 9973 struct hclge_vport *vport; 9974 int ret; 9975 int i; 9976 9977 for (i = 0; i < hdev->num_alloc_vport; i++) { 9978 vport = &hdev->vport[i]; 9979 cfg = &vport->port_base_vlan_cfg; 9980 9981 ret = hclge_vlan_offload_cfg(vport, cfg->state, 9982 cfg->vlan_info.vlan_tag, 9983 cfg->vlan_info.qos); 9984 if (ret) 9985 return ret; 9986 } 9987 return 0; 9988 } 9989 9990 static int hclge_init_vlan_config(struct hclge_dev *hdev) 9991 { 9992 struct hnae3_handle *handle = &hdev->vport[0].nic; 9993 int ret; 9994 9995 ret = hclge_init_vlan_filter(hdev); 9996 if (ret) 9997 return ret; 9998 9999 ret = hclge_init_vlan_type(hdev); 10000 if (ret) 10001 return ret; 10002 10003 ret = hclge_init_vport_vlan_offload(hdev); 10004 if (ret) 10005 return ret; 10006 10007 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 10008 } 10009 10010 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10011 bool writen_to_tbl) 10012 { 10013 struct hclge_vport_vlan_cfg *vlan, *tmp; 10014 struct hclge_dev *hdev = vport->back; 10015 10016 mutex_lock(&hdev->vport_lock); 10017 10018 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10019 if (vlan->vlan_id == vlan_id) { 10020 mutex_unlock(&hdev->vport_lock); 10021 return; 10022 } 10023 } 10024 10025 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 10026 if (!vlan) { 10027 mutex_unlock(&hdev->vport_lock); 10028 return; 10029 } 10030 10031 vlan->hd_tbl_status = writen_to_tbl; 10032 vlan->vlan_id = vlan_id; 10033 10034 list_add_tail(&vlan->node, &vport->vlan_list); 10035 mutex_unlock(&hdev->vport_lock); 10036 } 10037 10038 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport) 10039 { 10040 struct hclge_vport_vlan_cfg *vlan, *tmp; 10041 struct hclge_dev *hdev = vport->back; 10042 int ret; 10043 10044 mutex_lock(&hdev->vport_lock); 10045 10046 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10047 if (!vlan->hd_tbl_status) { 10048 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10049 vport->vport_id, 10050 vlan->vlan_id, false); 10051 if (ret) { 10052 dev_err(&hdev->pdev->dev, 10053 "restore vport vlan list failed, ret=%d\n", 10054 ret); 10055 10056 mutex_unlock(&hdev->vport_lock); 10057 return ret; 10058 } 10059 } 10060 vlan->hd_tbl_status = true; 10061 } 10062 10063 mutex_unlock(&hdev->vport_lock); 10064 10065 return 0; 10066 } 10067 10068 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 10069 bool is_write_tbl) 10070 { 10071 struct hclge_vport_vlan_cfg *vlan, *tmp; 10072 struct hclge_dev *hdev = vport->back; 10073 10074 mutex_lock(&hdev->vport_lock); 10075 10076 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10077 if (vlan->vlan_id == vlan_id) { 10078 if (is_write_tbl && vlan->hd_tbl_status) 10079 hclge_set_vlan_filter_hw(hdev, 10080 htons(ETH_P_8021Q), 10081 vport->vport_id, 10082 vlan_id, 10083 true); 10084 10085 list_del(&vlan->node); 10086 kfree(vlan); 10087 break; 10088 } 10089 } 10090 10091 mutex_unlock(&hdev->vport_lock); 10092 } 10093 10094 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list) 10095 { 10096 struct hclge_vport_vlan_cfg *vlan, *tmp; 10097 struct hclge_dev *hdev = vport->back; 10098 10099 mutex_lock(&hdev->vport_lock); 10100 10101 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10102 if (vlan->hd_tbl_status) 10103 hclge_set_vlan_filter_hw(hdev, 10104 htons(ETH_P_8021Q), 10105 vport->vport_id, 10106 vlan->vlan_id, 10107 true); 10108 10109 vlan->hd_tbl_status = false; 10110 if (is_del_list) { 10111 list_del(&vlan->node); 10112 kfree(vlan); 10113 } 10114 } 10115 clear_bit(vport->vport_id, hdev->vf_vlan_full); 10116 mutex_unlock(&hdev->vport_lock); 10117 } 10118 10119 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev) 10120 { 10121 struct hclge_vport_vlan_cfg *vlan, *tmp; 10122 struct hclge_vport *vport; 10123 int i; 10124 10125 mutex_lock(&hdev->vport_lock); 10126 10127 for (i = 0; i < hdev->num_alloc_vport; i++) { 10128 vport = &hdev->vport[i]; 10129 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10130 list_del(&vlan->node); 10131 kfree(vlan); 10132 } 10133 } 10134 10135 mutex_unlock(&hdev->vport_lock); 10136 } 10137 10138 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev) 10139 { 10140 struct hclge_vlan_info *vlan_info; 10141 struct hclge_vport *vport; 10142 u16 vlan_proto; 10143 u16 vlan_id; 10144 u16 state; 10145 int vf_id; 10146 int ret; 10147 10148 /* PF should restore all vfs port base vlan */ 10149 for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) { 10150 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM]; 10151 vlan_info = vport->port_base_vlan_cfg.tbl_sta ? 10152 &vport->port_base_vlan_cfg.vlan_info : 10153 &vport->port_base_vlan_cfg.old_vlan_info; 10154 10155 vlan_id = vlan_info->vlan_tag; 10156 vlan_proto = vlan_info->vlan_proto; 10157 state = vport->port_base_vlan_cfg.state; 10158 10159 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) { 10160 clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]); 10161 ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto), 10162 vport->vport_id, 10163 vlan_id, false); 10164 vport->port_base_vlan_cfg.tbl_sta = ret == 0; 10165 } 10166 } 10167 } 10168 10169 void hclge_restore_vport_vlan_table(struct hclge_vport *vport) 10170 { 10171 struct hclge_vport_vlan_cfg *vlan, *tmp; 10172 struct hclge_dev *hdev = vport->back; 10173 int ret; 10174 10175 mutex_lock(&hdev->vport_lock); 10176 10177 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10178 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 10179 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10180 vport->vport_id, 10181 vlan->vlan_id, false); 10182 if (ret) 10183 break; 10184 vlan->hd_tbl_status = true; 10185 } 10186 } 10187 10188 mutex_unlock(&hdev->vport_lock); 10189 } 10190 10191 /* For global reset and imp reset, hardware will clear the mac table, 10192 * so we change the mac address state from ACTIVE to TO_ADD, then they 10193 * can be restored in the service task after reset complete. Furtherly, 10194 * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to 10195 * be restored after reset, so just remove these mac nodes from mac_list. 10196 */ 10197 static void hclge_mac_node_convert_for_reset(struct list_head *list) 10198 { 10199 struct hclge_mac_node *mac_node, *tmp; 10200 10201 list_for_each_entry_safe(mac_node, tmp, list, node) { 10202 if (mac_node->state == HCLGE_MAC_ACTIVE) { 10203 mac_node->state = HCLGE_MAC_TO_ADD; 10204 } else if (mac_node->state == HCLGE_MAC_TO_DEL) { 10205 list_del(&mac_node->node); 10206 kfree(mac_node); 10207 } 10208 } 10209 } 10210 10211 void hclge_restore_mac_table_common(struct hclge_vport *vport) 10212 { 10213 spin_lock_bh(&vport->mac_list_lock); 10214 10215 hclge_mac_node_convert_for_reset(&vport->uc_mac_list); 10216 hclge_mac_node_convert_for_reset(&vport->mc_mac_list); 10217 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 10218 10219 spin_unlock_bh(&vport->mac_list_lock); 10220 } 10221 10222 static void hclge_restore_hw_table(struct hclge_dev *hdev) 10223 { 10224 struct hclge_vport *vport = &hdev->vport[0]; 10225 struct hnae3_handle *handle = &vport->nic; 10226 10227 hclge_restore_mac_table_common(vport); 10228 hclge_restore_vport_port_base_vlan_config(hdev); 10229 hclge_restore_vport_vlan_table(vport); 10230 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 10231 hclge_restore_fd_entries(handle); 10232 } 10233 10234 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 10235 { 10236 struct hclge_vport *vport = hclge_get_vport(handle); 10237 10238 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10239 vport->rxvlan_cfg.strip_tag1_en = false; 10240 vport->rxvlan_cfg.strip_tag2_en = enable; 10241 vport->rxvlan_cfg.strip_tag2_discard_en = false; 10242 } else { 10243 vport->rxvlan_cfg.strip_tag1_en = enable; 10244 vport->rxvlan_cfg.strip_tag2_en = true; 10245 vport->rxvlan_cfg.strip_tag2_discard_en = true; 10246 } 10247 10248 vport->rxvlan_cfg.strip_tag1_discard_en = false; 10249 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 10250 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 10251 vport->rxvlan_cfg.rx_vlan_offload_en = enable; 10252 10253 return hclge_set_vlan_rx_offload_cfg(vport); 10254 } 10255 10256 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport) 10257 { 10258 struct hclge_dev *hdev = vport->back; 10259 10260 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 10261 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state); 10262 } 10263 10264 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport, 10265 u16 port_base_vlan_state, 10266 struct hclge_vlan_info *new_info, 10267 struct hclge_vlan_info *old_info) 10268 { 10269 struct hclge_dev *hdev = vport->back; 10270 int ret; 10271 10272 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) { 10273 hclge_rm_vport_all_vlan_table(vport, false); 10274 /* force clear VLAN 0 */ 10275 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0); 10276 if (ret) 10277 return ret; 10278 return hclge_set_vlan_filter_hw(hdev, 10279 htons(new_info->vlan_proto), 10280 vport->vport_id, 10281 new_info->vlan_tag, 10282 false); 10283 } 10284 10285 vport->port_base_vlan_cfg.tbl_sta = false; 10286 10287 /* force add VLAN 0 */ 10288 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0); 10289 if (ret) 10290 return ret; 10291 10292 ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto), 10293 vport->vport_id, old_info->vlan_tag, 10294 true); 10295 if (ret) 10296 return ret; 10297 10298 return hclge_add_vport_all_vlan_table(vport); 10299 } 10300 10301 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg, 10302 const struct hclge_vlan_info *old_cfg) 10303 { 10304 if (new_cfg->vlan_tag != old_cfg->vlan_tag) 10305 return true; 10306 10307 if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0)) 10308 return true; 10309 10310 return false; 10311 } 10312 10313 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport, 10314 struct hclge_vlan_info *new_info, 10315 struct hclge_vlan_info *old_info) 10316 { 10317 struct hclge_dev *hdev = vport->back; 10318 int ret; 10319 10320 /* add new VLAN tag */ 10321 ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto), 10322 vport->vport_id, new_info->vlan_tag, 10323 false); 10324 if (ret) 10325 return ret; 10326 10327 vport->port_base_vlan_cfg.tbl_sta = false; 10328 /* remove old VLAN tag */ 10329 if (old_info->vlan_tag == 0) 10330 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, 10331 true, 0); 10332 else 10333 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10334 vport->vport_id, 10335 old_info->vlan_tag, true); 10336 if (ret) 10337 dev_err(&hdev->pdev->dev, 10338 "failed to clear vport%u port base vlan %u, ret = %d.\n", 10339 vport->vport_id, old_info->vlan_tag, ret); 10340 10341 return ret; 10342 } 10343 10344 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 10345 struct hclge_vlan_info *vlan_info) 10346 { 10347 struct hnae3_handle *nic = &vport->nic; 10348 struct hclge_vlan_info *old_vlan_info; 10349 int ret; 10350 10351 old_vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10352 10353 ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag, 10354 vlan_info->qos); 10355 if (ret) 10356 return ret; 10357 10358 if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info)) 10359 goto out; 10360 10361 if (state == HNAE3_PORT_BASE_VLAN_MODIFY) 10362 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info, 10363 old_vlan_info); 10364 else 10365 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info, 10366 old_vlan_info); 10367 if (ret) 10368 return ret; 10369 10370 out: 10371 vport->port_base_vlan_cfg.state = state; 10372 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 10373 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 10374 else 10375 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 10376 10377 vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info; 10378 vport->port_base_vlan_cfg.vlan_info = *vlan_info; 10379 vport->port_base_vlan_cfg.tbl_sta = true; 10380 hclge_set_vport_vlan_fltr_change(vport); 10381 10382 return 0; 10383 } 10384 10385 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport, 10386 enum hnae3_port_base_vlan_state state, 10387 u16 vlan, u8 qos) 10388 { 10389 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10390 if (!vlan && !qos) 10391 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10392 10393 return HNAE3_PORT_BASE_VLAN_ENABLE; 10394 } 10395 10396 if (!vlan && !qos) 10397 return HNAE3_PORT_BASE_VLAN_DISABLE; 10398 10399 if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan && 10400 vport->port_base_vlan_cfg.vlan_info.qos == qos) 10401 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 10402 10403 return HNAE3_PORT_BASE_VLAN_MODIFY; 10404 } 10405 10406 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 10407 u16 vlan, u8 qos, __be16 proto) 10408 { 10409 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 10410 struct hclge_vport *vport = hclge_get_vport(handle); 10411 struct hclge_dev *hdev = vport->back; 10412 struct hclge_vlan_info vlan_info; 10413 u16 state; 10414 int ret; 10415 10416 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 10417 return -EOPNOTSUPP; 10418 10419 vport = hclge_get_vf_vport(hdev, vfid); 10420 if (!vport) 10421 return -EINVAL; 10422 10423 /* qos is a 3 bits value, so can not be bigger than 7 */ 10424 if (vlan > VLAN_N_VID - 1 || qos > 7) 10425 return -EINVAL; 10426 if (proto != htons(ETH_P_8021Q)) 10427 return -EPROTONOSUPPORT; 10428 10429 state = hclge_get_port_base_vlan_state(vport, 10430 vport->port_base_vlan_cfg.state, 10431 vlan, qos); 10432 if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE) 10433 return 0; 10434 10435 vlan_info.vlan_tag = vlan; 10436 vlan_info.qos = qos; 10437 vlan_info.vlan_proto = ntohs(proto); 10438 10439 ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info); 10440 if (ret) { 10441 dev_err(&hdev->pdev->dev, 10442 "failed to update port base vlan for vf %d, ret = %d\n", 10443 vfid, ret); 10444 return ret; 10445 } 10446 10447 /* there is a timewindow for PF to know VF unalive, it may 10448 * cause send mailbox fail, but it doesn't matter, VF will 10449 * query it when reinit. 10450 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based 10451 * VLAN state. 10452 */ 10453 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3 && 10454 test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 10455 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0], 10456 vport->vport_id, 10457 state, &vlan_info); 10458 10459 return 0; 10460 } 10461 10462 static void hclge_clear_vf_vlan(struct hclge_dev *hdev) 10463 { 10464 struct hclge_vlan_info *vlan_info; 10465 struct hclge_vport *vport; 10466 int ret; 10467 int vf; 10468 10469 /* clear port base vlan for all vf */ 10470 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 10471 vport = &hdev->vport[vf]; 10472 vlan_info = &vport->port_base_vlan_cfg.vlan_info; 10473 10474 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10475 vport->vport_id, 10476 vlan_info->vlan_tag, true); 10477 if (ret) 10478 dev_err(&hdev->pdev->dev, 10479 "failed to clear vf vlan for vf%d, ret = %d\n", 10480 vf - HCLGE_VF_VPORT_START_NUM, ret); 10481 } 10482 } 10483 10484 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 10485 u16 vlan_id, bool is_kill) 10486 { 10487 struct hclge_vport *vport = hclge_get_vport(handle); 10488 struct hclge_dev *hdev = vport->back; 10489 bool writen_to_tbl = false; 10490 int ret = 0; 10491 10492 /* When device is resetting or reset failed, firmware is unable to 10493 * handle mailbox. Just record the vlan id, and remove it after 10494 * reset finished. 10495 */ 10496 if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 10497 test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) { 10498 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10499 return -EBUSY; 10500 } 10501 10502 /* when port base vlan enabled, we use port base vlan as the vlan 10503 * filter entry. In this case, we don't update vlan filter table 10504 * when user add new vlan or remove exist vlan, just update the vport 10505 * vlan list. The vlan id in vlan list will be writen in vlan filter 10506 * table until port base vlan disabled 10507 */ 10508 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 10509 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, 10510 vlan_id, is_kill); 10511 writen_to_tbl = true; 10512 } 10513 10514 if (!ret) { 10515 if (!is_kill) 10516 hclge_add_vport_vlan_table(vport, vlan_id, 10517 writen_to_tbl); 10518 else if (is_kill && vlan_id != 0) 10519 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10520 } else if (is_kill) { 10521 /* when remove hw vlan filter failed, record the vlan id, 10522 * and try to remove it from hw later, to be consistence 10523 * with stack 10524 */ 10525 set_bit(vlan_id, vport->vlan_del_fail_bmap); 10526 } 10527 10528 hclge_set_vport_vlan_fltr_change(vport); 10529 10530 return ret; 10531 } 10532 10533 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev) 10534 { 10535 struct hclge_vport *vport; 10536 int ret; 10537 u16 i; 10538 10539 for (i = 0; i < hdev->num_alloc_vport; i++) { 10540 vport = &hdev->vport[i]; 10541 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10542 &vport->state)) 10543 continue; 10544 10545 ret = hclge_enable_vport_vlan_filter(vport, 10546 vport->req_vlan_fltr_en); 10547 if (ret) { 10548 dev_err(&hdev->pdev->dev, 10549 "failed to sync vlan filter state for vport%u, ret = %d\n", 10550 vport->vport_id, ret); 10551 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10552 &vport->state); 10553 return; 10554 } 10555 } 10556 } 10557 10558 static void hclge_sync_vlan_filter(struct hclge_dev *hdev) 10559 { 10560 #define HCLGE_MAX_SYNC_COUNT 60 10561 10562 int i, ret, sync_cnt = 0; 10563 u16 vlan_id; 10564 10565 /* start from vport 1 for PF is always alive */ 10566 for (i = 0; i < hdev->num_alloc_vport; i++) { 10567 struct hclge_vport *vport = &hdev->vport[i]; 10568 10569 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10570 VLAN_N_VID); 10571 while (vlan_id != VLAN_N_VID) { 10572 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 10573 vport->vport_id, vlan_id, 10574 true); 10575 if (ret && ret != -EINVAL) 10576 return; 10577 10578 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 10579 hclge_rm_vport_vlan_table(vport, vlan_id, false); 10580 hclge_set_vport_vlan_fltr_change(vport); 10581 10582 sync_cnt++; 10583 if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) 10584 return; 10585 10586 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 10587 VLAN_N_VID); 10588 } 10589 } 10590 10591 hclge_sync_vlan_fltr_state(hdev); 10592 } 10593 10594 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps) 10595 { 10596 struct hclge_config_max_frm_size_cmd *req; 10597 struct hclge_desc desc; 10598 10599 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 10600 10601 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 10602 req->max_frm_size = cpu_to_le16(new_mps); 10603 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 10604 10605 return hclge_cmd_send(&hdev->hw, &desc, 1); 10606 } 10607 10608 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 10609 { 10610 struct hclge_vport *vport = hclge_get_vport(handle); 10611 10612 return hclge_set_vport_mtu(vport, new_mtu); 10613 } 10614 10615 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) 10616 { 10617 struct hclge_dev *hdev = vport->back; 10618 int i, max_frm_size, ret; 10619 10620 /* HW supprt 2 layer vlan */ 10621 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 10622 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 10623 max_frm_size > hdev->ae_dev->dev_specs.max_frm_size) 10624 return -EINVAL; 10625 10626 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 10627 mutex_lock(&hdev->vport_lock); 10628 /* VF's mps must fit within hdev->mps */ 10629 if (vport->vport_id && max_frm_size > hdev->mps) { 10630 mutex_unlock(&hdev->vport_lock); 10631 return -EINVAL; 10632 } else if (vport->vport_id) { 10633 vport->mps = max_frm_size; 10634 mutex_unlock(&hdev->vport_lock); 10635 return 0; 10636 } 10637 10638 /* PF's mps must be greater then VF's mps */ 10639 for (i = 1; i < hdev->num_alloc_vport; i++) 10640 if (max_frm_size < hdev->vport[i].mps) { 10641 dev_err(&hdev->pdev->dev, 10642 "failed to set pf mtu for less than vport %d, mps = %u.\n", 10643 i, hdev->vport[i].mps); 10644 mutex_unlock(&hdev->vport_lock); 10645 return -EINVAL; 10646 } 10647 10648 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 10649 10650 ret = hclge_set_mac_mtu(hdev, max_frm_size); 10651 if (ret) { 10652 dev_err(&hdev->pdev->dev, 10653 "Change mtu fail, ret =%d\n", ret); 10654 goto out; 10655 } 10656 10657 hdev->mps = max_frm_size; 10658 vport->mps = max_frm_size; 10659 10660 ret = hclge_buffer_alloc(hdev); 10661 if (ret) 10662 dev_err(&hdev->pdev->dev, 10663 "Allocate buffer fail, ret =%d\n", ret); 10664 10665 out: 10666 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 10667 mutex_unlock(&hdev->vport_lock); 10668 return ret; 10669 } 10670 10671 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id, 10672 bool enable) 10673 { 10674 struct hclge_reset_tqp_queue_cmd *req; 10675 struct hclge_desc desc; 10676 int ret; 10677 10678 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 10679 10680 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10681 req->tqp_id = cpu_to_le16(queue_id); 10682 if (enable) 10683 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U); 10684 10685 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10686 if (ret) { 10687 dev_err(&hdev->pdev->dev, 10688 "Send tqp reset cmd error, status =%d\n", ret); 10689 return ret; 10690 } 10691 10692 return 0; 10693 } 10694 10695 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id, 10696 u8 *reset_status) 10697 { 10698 struct hclge_reset_tqp_queue_cmd *req; 10699 struct hclge_desc desc; 10700 int ret; 10701 10702 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 10703 10704 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 10705 req->tqp_id = cpu_to_le16(queue_id); 10706 10707 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10708 if (ret) { 10709 dev_err(&hdev->pdev->dev, 10710 "Get reset status error, status =%d\n", ret); 10711 return ret; 10712 } 10713 10714 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 10715 10716 return 0; 10717 } 10718 10719 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id) 10720 { 10721 struct hclge_comm_tqp *tqp; 10722 struct hnae3_queue *queue; 10723 10724 queue = handle->kinfo.tqp[queue_id]; 10725 tqp = container_of(queue, struct hclge_comm_tqp, q); 10726 10727 return tqp->index; 10728 } 10729 10730 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle) 10731 { 10732 struct hclge_vport *vport = hclge_get_vport(handle); 10733 struct hclge_dev *hdev = vport->back; 10734 u16 reset_try_times = 0; 10735 u8 reset_status; 10736 u16 queue_gid; 10737 int ret; 10738 u16 i; 10739 10740 for (i = 0; i < handle->kinfo.num_tqps; i++) { 10741 queue_gid = hclge_covert_handle_qid_global(handle, i); 10742 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true); 10743 if (ret) { 10744 dev_err(&hdev->pdev->dev, 10745 "failed to send reset tqp cmd, ret = %d\n", 10746 ret); 10747 return ret; 10748 } 10749 10750 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 10751 ret = hclge_get_reset_status(hdev, queue_gid, 10752 &reset_status); 10753 if (ret) 10754 return ret; 10755 10756 if (reset_status) 10757 break; 10758 10759 /* Wait for tqp hw reset */ 10760 usleep_range(1000, 1200); 10761 } 10762 10763 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 10764 dev_err(&hdev->pdev->dev, 10765 "wait for tqp hw reset timeout\n"); 10766 return -ETIME; 10767 } 10768 10769 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false); 10770 if (ret) { 10771 dev_err(&hdev->pdev->dev, 10772 "failed to deassert soft reset, ret = %d\n", 10773 ret); 10774 return ret; 10775 } 10776 reset_try_times = 0; 10777 } 10778 return 0; 10779 } 10780 10781 static int hclge_reset_rcb(struct hnae3_handle *handle) 10782 { 10783 #define HCLGE_RESET_RCB_NOT_SUPPORT 0U 10784 #define HCLGE_RESET_RCB_SUCCESS 1U 10785 10786 struct hclge_vport *vport = hclge_get_vport(handle); 10787 struct hclge_dev *hdev = vport->back; 10788 struct hclge_reset_cmd *req; 10789 struct hclge_desc desc; 10790 u8 return_status; 10791 u16 queue_gid; 10792 int ret; 10793 10794 queue_gid = hclge_covert_handle_qid_global(handle, 0); 10795 10796 req = (struct hclge_reset_cmd *)desc.data; 10797 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 10798 hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1); 10799 req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid); 10800 req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps); 10801 10802 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10803 if (ret) { 10804 dev_err(&hdev->pdev->dev, 10805 "failed to send rcb reset cmd, ret = %d\n", ret); 10806 return ret; 10807 } 10808 10809 return_status = req->fun_reset_rcb_return_status; 10810 if (return_status == HCLGE_RESET_RCB_SUCCESS) 10811 return 0; 10812 10813 if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) { 10814 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n", 10815 return_status); 10816 return -EIO; 10817 } 10818 10819 /* if reset rcb cmd is unsupported, we need to send reset tqp cmd 10820 * again to reset all tqps 10821 */ 10822 return hclge_reset_tqp_cmd(handle); 10823 } 10824 10825 int hclge_reset_tqp(struct hnae3_handle *handle) 10826 { 10827 struct hclge_vport *vport = hclge_get_vport(handle); 10828 struct hclge_dev *hdev = vport->back; 10829 int ret; 10830 10831 /* only need to disable PF's tqp */ 10832 if (!vport->vport_id) { 10833 ret = hclge_tqp_enable(handle, false); 10834 if (ret) { 10835 dev_err(&hdev->pdev->dev, 10836 "failed to disable tqp, ret = %d\n", ret); 10837 return ret; 10838 } 10839 } 10840 10841 return hclge_reset_rcb(handle); 10842 } 10843 10844 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 10845 { 10846 struct hclge_vport *vport = hclge_get_vport(handle); 10847 struct hclge_dev *hdev = vport->back; 10848 10849 return hdev->fw_version; 10850 } 10851 10852 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10853 { 10854 struct phy_device *phydev = hdev->hw.mac.phydev; 10855 10856 if (!phydev) 10857 return; 10858 10859 phy_set_asym_pause(phydev, rx_en, tx_en); 10860 } 10861 10862 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 10863 { 10864 int ret; 10865 10866 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 10867 return 0; 10868 10869 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 10870 if (ret) 10871 dev_err(&hdev->pdev->dev, 10872 "configure pauseparam error, ret = %d.\n", ret); 10873 10874 return ret; 10875 } 10876 10877 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 10878 { 10879 struct phy_device *phydev = hdev->hw.mac.phydev; 10880 u16 remote_advertising = 0; 10881 u16 local_advertising; 10882 u32 rx_pause, tx_pause; 10883 u8 flowctl; 10884 10885 if (!phydev->link || !phydev->autoneg) 10886 return 0; 10887 10888 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising); 10889 10890 if (phydev->pause) 10891 remote_advertising = LPA_PAUSE_CAP; 10892 10893 if (phydev->asym_pause) 10894 remote_advertising |= LPA_PAUSE_ASYM; 10895 10896 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 10897 remote_advertising); 10898 tx_pause = flowctl & FLOW_CTRL_TX; 10899 rx_pause = flowctl & FLOW_CTRL_RX; 10900 10901 if (phydev->duplex == HCLGE_MAC_HALF) { 10902 tx_pause = 0; 10903 rx_pause = 0; 10904 } 10905 10906 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 10907 } 10908 10909 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 10910 u32 *rx_en, u32 *tx_en) 10911 { 10912 struct hclge_vport *vport = hclge_get_vport(handle); 10913 struct hclge_dev *hdev = vport->back; 10914 u8 media_type = hdev->hw.mac.media_type; 10915 10916 *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ? 10917 hclge_get_autoneg(handle) : 0; 10918 10919 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 10920 *rx_en = 0; 10921 *tx_en = 0; 10922 return; 10923 } 10924 10925 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 10926 *rx_en = 1; 10927 *tx_en = 0; 10928 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 10929 *tx_en = 1; 10930 *rx_en = 0; 10931 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 10932 *rx_en = 1; 10933 *tx_en = 1; 10934 } else { 10935 *rx_en = 0; 10936 *tx_en = 0; 10937 } 10938 } 10939 10940 static void hclge_record_user_pauseparam(struct hclge_dev *hdev, 10941 u32 rx_en, u32 tx_en) 10942 { 10943 if (rx_en && tx_en) 10944 hdev->fc_mode_last_time = HCLGE_FC_FULL; 10945 else if (rx_en && !tx_en) 10946 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 10947 else if (!rx_en && tx_en) 10948 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 10949 else 10950 hdev->fc_mode_last_time = HCLGE_FC_NONE; 10951 10952 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 10953 } 10954 10955 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 10956 u32 rx_en, u32 tx_en) 10957 { 10958 struct hclge_vport *vport = hclge_get_vport(handle); 10959 struct hclge_dev *hdev = vport->back; 10960 struct phy_device *phydev = hdev->hw.mac.phydev; 10961 u32 fc_autoneg; 10962 10963 if (phydev || hnae3_dev_phy_imp_supported(hdev)) { 10964 fc_autoneg = hclge_get_autoneg(handle); 10965 if (auto_neg != fc_autoneg) { 10966 dev_info(&hdev->pdev->dev, 10967 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 10968 return -EOPNOTSUPP; 10969 } 10970 } 10971 10972 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 10973 dev_info(&hdev->pdev->dev, 10974 "Priority flow control enabled. Cannot set link flow control.\n"); 10975 return -EOPNOTSUPP; 10976 } 10977 10978 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 10979 10980 hclge_record_user_pauseparam(hdev, rx_en, tx_en); 10981 10982 if (!auto_neg || hnae3_dev_phy_imp_supported(hdev)) 10983 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 10984 10985 if (phydev) 10986 return phy_start_aneg(phydev); 10987 10988 return -EOPNOTSUPP; 10989 } 10990 10991 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 10992 u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num) 10993 { 10994 struct hclge_vport *vport = hclge_get_vport(handle); 10995 struct hclge_dev *hdev = vport->back; 10996 10997 if (speed) 10998 *speed = hdev->hw.mac.speed; 10999 if (duplex) 11000 *duplex = hdev->hw.mac.duplex; 11001 if (auto_neg) 11002 *auto_neg = hdev->hw.mac.autoneg; 11003 if (lane_num) 11004 *lane_num = hdev->hw.mac.lane_num; 11005 } 11006 11007 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type, 11008 u8 *module_type) 11009 { 11010 struct hclge_vport *vport = hclge_get_vport(handle); 11011 struct hclge_dev *hdev = vport->back; 11012 11013 /* When nic is down, the service task is not running, doesn't update 11014 * the port information per second. Query the port information before 11015 * return the media type, ensure getting the correct media information. 11016 */ 11017 hclge_update_port_info(hdev); 11018 11019 if (media_type) 11020 *media_type = hdev->hw.mac.media_type; 11021 11022 if (module_type) 11023 *module_type = hdev->hw.mac.module_type; 11024 } 11025 11026 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 11027 u8 *tp_mdix_ctrl, u8 *tp_mdix) 11028 { 11029 struct hclge_vport *vport = hclge_get_vport(handle); 11030 struct hclge_dev *hdev = vport->back; 11031 struct phy_device *phydev = hdev->hw.mac.phydev; 11032 int mdix_ctrl, mdix, is_resolved; 11033 unsigned int retval; 11034 11035 if (!phydev) { 11036 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11037 *tp_mdix = ETH_TP_MDI_INVALID; 11038 return; 11039 } 11040 11041 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 11042 11043 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 11044 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 11045 HCLGE_PHY_MDIX_CTRL_S); 11046 11047 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 11048 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 11049 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 11050 11051 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 11052 11053 switch (mdix_ctrl) { 11054 case 0x0: 11055 *tp_mdix_ctrl = ETH_TP_MDI; 11056 break; 11057 case 0x1: 11058 *tp_mdix_ctrl = ETH_TP_MDI_X; 11059 break; 11060 case 0x3: 11061 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 11062 break; 11063 default: 11064 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 11065 break; 11066 } 11067 11068 if (!is_resolved) 11069 *tp_mdix = ETH_TP_MDI_INVALID; 11070 else if (mdix) 11071 *tp_mdix = ETH_TP_MDI_X; 11072 else 11073 *tp_mdix = ETH_TP_MDI; 11074 } 11075 11076 static void hclge_info_show(struct hclge_dev *hdev) 11077 { 11078 struct device *dev = &hdev->pdev->dev; 11079 11080 dev_info(dev, "PF info begin:\n"); 11081 11082 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 11083 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 11084 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 11085 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 11086 dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs); 11087 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 11088 dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size); 11089 dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size); 11090 dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size); 11091 dev_info(dev, "This is %s PF\n", 11092 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main"); 11093 dev_info(dev, "DCB %s\n", 11094 hdev->flag & HCLGE_FLAG_DCB_ENABLE ? "enable" : "disable"); 11095 dev_info(dev, "MQPRIO %s\n", 11096 hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE ? "enable" : "disable"); 11097 dev_info(dev, "Default tx spare buffer size: %u\n", 11098 hdev->tx_spare_buf_size); 11099 11100 dev_info(dev, "PF info end.\n"); 11101 } 11102 11103 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 11104 struct hclge_vport *vport) 11105 { 11106 struct hnae3_client *client = vport->nic.client; 11107 struct hclge_dev *hdev = ae_dev->priv; 11108 int rst_cnt = hdev->rst_stats.reset_cnt; 11109 int ret; 11110 11111 ret = client->ops->init_instance(&vport->nic); 11112 if (ret) 11113 return ret; 11114 11115 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11116 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11117 rst_cnt != hdev->rst_stats.reset_cnt) { 11118 ret = -EBUSY; 11119 goto init_nic_err; 11120 } 11121 11122 /* Enable nic hw error interrupts */ 11123 ret = hclge_config_nic_hw_error(hdev, true); 11124 if (ret) { 11125 dev_err(&ae_dev->pdev->dev, 11126 "fail(%d) to enable hw error interrupts\n", ret); 11127 goto init_nic_err; 11128 } 11129 11130 hnae3_set_client_init_flag(client, ae_dev, 1); 11131 11132 if (netif_msg_drv(&hdev->vport->nic)) 11133 hclge_info_show(hdev); 11134 11135 return ret; 11136 11137 init_nic_err: 11138 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11139 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11140 msleep(HCLGE_WAIT_RESET_DONE); 11141 11142 client->ops->uninit_instance(&vport->nic, 0); 11143 11144 return ret; 11145 } 11146 11147 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 11148 struct hclge_vport *vport) 11149 { 11150 struct hclge_dev *hdev = ae_dev->priv; 11151 struct hnae3_client *client; 11152 int rst_cnt; 11153 int ret; 11154 11155 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 11156 !hdev->nic_client) 11157 return 0; 11158 11159 client = hdev->roce_client; 11160 ret = hclge_init_roce_base_info(vport); 11161 if (ret) 11162 return ret; 11163 11164 rst_cnt = hdev->rst_stats.reset_cnt; 11165 ret = client->ops->init_instance(&vport->roce); 11166 if (ret) 11167 return ret; 11168 11169 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11170 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 11171 rst_cnt != hdev->rst_stats.reset_cnt) { 11172 ret = -EBUSY; 11173 goto init_roce_err; 11174 } 11175 11176 /* Enable roce ras interrupts */ 11177 ret = hclge_config_rocee_ras_interrupt(hdev, true); 11178 if (ret) { 11179 dev_err(&ae_dev->pdev->dev, 11180 "fail(%d) to enable roce ras interrupts\n", ret); 11181 goto init_roce_err; 11182 } 11183 11184 hnae3_set_client_init_flag(client, ae_dev, 1); 11185 11186 return 0; 11187 11188 init_roce_err: 11189 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11190 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11191 msleep(HCLGE_WAIT_RESET_DONE); 11192 11193 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11194 11195 return ret; 11196 } 11197 11198 static int hclge_init_client_instance(struct hnae3_client *client, 11199 struct hnae3_ae_dev *ae_dev) 11200 { 11201 struct hclge_dev *hdev = ae_dev->priv; 11202 struct hclge_vport *vport = &hdev->vport[0]; 11203 int ret; 11204 11205 switch (client->type) { 11206 case HNAE3_CLIENT_KNIC: 11207 hdev->nic_client = client; 11208 vport->nic.client = client; 11209 ret = hclge_init_nic_client_instance(ae_dev, vport); 11210 if (ret) 11211 goto clear_nic; 11212 11213 ret = hclge_init_roce_client_instance(ae_dev, vport); 11214 if (ret) 11215 goto clear_roce; 11216 11217 break; 11218 case HNAE3_CLIENT_ROCE: 11219 if (hnae3_dev_roce_supported(hdev)) { 11220 hdev->roce_client = client; 11221 vport->roce.client = client; 11222 } 11223 11224 ret = hclge_init_roce_client_instance(ae_dev, vport); 11225 if (ret) 11226 goto clear_roce; 11227 11228 break; 11229 default: 11230 return -EINVAL; 11231 } 11232 11233 return 0; 11234 11235 clear_nic: 11236 hdev->nic_client = NULL; 11237 vport->nic.client = NULL; 11238 return ret; 11239 clear_roce: 11240 hdev->roce_client = NULL; 11241 vport->roce.client = NULL; 11242 return ret; 11243 } 11244 11245 static void hclge_uninit_client_instance(struct hnae3_client *client, 11246 struct hnae3_ae_dev *ae_dev) 11247 { 11248 struct hclge_dev *hdev = ae_dev->priv; 11249 struct hclge_vport *vport = &hdev->vport[0]; 11250 11251 if (hdev->roce_client) { 11252 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 11253 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11254 msleep(HCLGE_WAIT_RESET_DONE); 11255 11256 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 11257 hdev->roce_client = NULL; 11258 vport->roce.client = NULL; 11259 } 11260 if (client->type == HNAE3_CLIENT_ROCE) 11261 return; 11262 if (hdev->nic_client && client->ops->uninit_instance) { 11263 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 11264 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 11265 msleep(HCLGE_WAIT_RESET_DONE); 11266 11267 client->ops->uninit_instance(&vport->nic, 0); 11268 hdev->nic_client = NULL; 11269 vport->nic.client = NULL; 11270 } 11271 } 11272 11273 static int hclge_dev_mem_map(struct hclge_dev *hdev) 11274 { 11275 struct pci_dev *pdev = hdev->pdev; 11276 struct hclge_hw *hw = &hdev->hw; 11277 11278 /* for device does not have device memory, return directly */ 11279 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR))) 11280 return 0; 11281 11282 hw->hw.mem_base = 11283 devm_ioremap_wc(&pdev->dev, 11284 pci_resource_start(pdev, HCLGE_MEM_BAR), 11285 pci_resource_len(pdev, HCLGE_MEM_BAR)); 11286 if (!hw->hw.mem_base) { 11287 dev_err(&pdev->dev, "failed to map device memory\n"); 11288 return -EFAULT; 11289 } 11290 11291 return 0; 11292 } 11293 11294 static int hclge_pci_init(struct hclge_dev *hdev) 11295 { 11296 struct pci_dev *pdev = hdev->pdev; 11297 struct hclge_hw *hw; 11298 int ret; 11299 11300 ret = pci_enable_device(pdev); 11301 if (ret) { 11302 dev_err(&pdev->dev, "failed to enable PCI device\n"); 11303 return ret; 11304 } 11305 11306 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 11307 if (ret) { 11308 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 11309 if (ret) { 11310 dev_err(&pdev->dev, 11311 "can't set consistent PCI DMA"); 11312 goto err_disable_device; 11313 } 11314 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); 11315 } 11316 11317 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 11318 if (ret) { 11319 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 11320 goto err_disable_device; 11321 } 11322 11323 pci_set_master(pdev); 11324 hw = &hdev->hw; 11325 hw->hw.io_base = pcim_iomap(pdev, 2, 0); 11326 if (!hw->hw.io_base) { 11327 dev_err(&pdev->dev, "Can't map configuration register space\n"); 11328 ret = -ENOMEM; 11329 goto err_clr_master; 11330 } 11331 11332 ret = hclge_dev_mem_map(hdev); 11333 if (ret) 11334 goto err_unmap_io_base; 11335 11336 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 11337 11338 return 0; 11339 11340 err_unmap_io_base: 11341 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11342 err_clr_master: 11343 pci_clear_master(pdev); 11344 pci_release_regions(pdev); 11345 err_disable_device: 11346 pci_disable_device(pdev); 11347 11348 return ret; 11349 } 11350 11351 static void hclge_pci_uninit(struct hclge_dev *hdev) 11352 { 11353 struct pci_dev *pdev = hdev->pdev; 11354 11355 if (hdev->hw.hw.mem_base) 11356 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 11357 11358 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11359 pci_free_irq_vectors(pdev); 11360 pci_clear_master(pdev); 11361 pci_release_mem_regions(pdev); 11362 pci_disable_device(pdev); 11363 } 11364 11365 static void hclge_state_init(struct hclge_dev *hdev) 11366 { 11367 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 11368 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11369 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 11370 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11371 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 11372 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 11373 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 11374 } 11375 11376 static void hclge_state_uninit(struct hclge_dev *hdev) 11377 { 11378 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11379 set_bit(HCLGE_STATE_REMOVING, &hdev->state); 11380 11381 if (hdev->reset_timer.function) 11382 del_timer_sync(&hdev->reset_timer); 11383 if (hdev->service_task.work.func) 11384 cancel_delayed_work_sync(&hdev->service_task); 11385 } 11386 11387 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 11388 enum hnae3_reset_type rst_type) 11389 { 11390 #define HCLGE_RESET_RETRY_WAIT_MS 500 11391 #define HCLGE_RESET_RETRY_CNT 5 11392 11393 struct hclge_dev *hdev = ae_dev->priv; 11394 int retry_cnt = 0; 11395 int ret; 11396 11397 while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) { 11398 down(&hdev->reset_sem); 11399 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11400 hdev->reset_type = rst_type; 11401 ret = hclge_reset_prepare(hdev); 11402 if (!ret && !hdev->reset_pending) 11403 break; 11404 11405 dev_err(&hdev->pdev->dev, 11406 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 11407 ret, hdev->reset_pending, retry_cnt); 11408 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11409 up(&hdev->reset_sem); 11410 msleep(HCLGE_RESET_RETRY_WAIT_MS); 11411 } 11412 11413 /* disable misc vector before reset done */ 11414 hclge_enable_vector(&hdev->misc_vector, false); 11415 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 11416 11417 if (hdev->reset_type == HNAE3_FLR_RESET) 11418 hdev->rst_stats.flr_rst_cnt++; 11419 } 11420 11421 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev) 11422 { 11423 struct hclge_dev *hdev = ae_dev->priv; 11424 int ret; 11425 11426 hclge_enable_vector(&hdev->misc_vector, true); 11427 11428 ret = hclge_reset_rebuild(hdev); 11429 if (ret) 11430 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret); 11431 11432 hdev->reset_type = HNAE3_NONE_RESET; 11433 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 11434 up(&hdev->reset_sem); 11435 } 11436 11437 static void hclge_clear_resetting_state(struct hclge_dev *hdev) 11438 { 11439 u16 i; 11440 11441 for (i = 0; i < hdev->num_alloc_vport; i++) { 11442 struct hclge_vport *vport = &hdev->vport[i]; 11443 int ret; 11444 11445 /* Send cmd to clear vport's FUNC_RST_ING */ 11446 ret = hclge_set_vf_rst(hdev, vport->vport_id, false); 11447 if (ret) 11448 dev_warn(&hdev->pdev->dev, 11449 "clear vport(%u) rst failed %d!\n", 11450 vport->vport_id, ret); 11451 } 11452 } 11453 11454 static int hclge_clear_hw_resource(struct hclge_dev *hdev) 11455 { 11456 struct hclge_desc desc; 11457 int ret; 11458 11459 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false); 11460 11461 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 11462 /* This new command is only supported by new firmware, it will 11463 * fail with older firmware. Error value -EOPNOSUPP can only be 11464 * returned by older firmware running this command, to keep code 11465 * backward compatible we will override this value and return 11466 * success. 11467 */ 11468 if (ret && ret != -EOPNOTSUPP) { 11469 dev_err(&hdev->pdev->dev, 11470 "failed to clear hw resource, ret = %d\n", ret); 11471 return ret; 11472 } 11473 return 0; 11474 } 11475 11476 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev) 11477 { 11478 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11479 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1); 11480 } 11481 11482 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev) 11483 { 11484 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 11485 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0); 11486 } 11487 11488 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 11489 { 11490 struct pci_dev *pdev = ae_dev->pdev; 11491 struct hclge_dev *hdev; 11492 int ret; 11493 11494 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 11495 if (!hdev) 11496 return -ENOMEM; 11497 11498 hdev->pdev = pdev; 11499 hdev->ae_dev = ae_dev; 11500 hdev->reset_type = HNAE3_NONE_RESET; 11501 hdev->reset_level = HNAE3_FUNC_RESET; 11502 ae_dev->priv = hdev; 11503 11504 /* HW supprt 2 layer vlan */ 11505 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 11506 11507 mutex_init(&hdev->vport_lock); 11508 spin_lock_init(&hdev->fd_rule_lock); 11509 sema_init(&hdev->reset_sem, 1); 11510 11511 ret = hclge_pci_init(hdev); 11512 if (ret) 11513 goto out; 11514 11515 ret = hclge_devlink_init(hdev); 11516 if (ret) 11517 goto err_pci_uninit; 11518 11519 /* Firmware command queue initialize */ 11520 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 11521 if (ret) 11522 goto err_devlink_uninit; 11523 11524 /* Firmware command initialize */ 11525 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 11526 true, hdev->reset_pending); 11527 if (ret) 11528 goto err_cmd_uninit; 11529 11530 ret = hclge_clear_hw_resource(hdev); 11531 if (ret) 11532 goto err_cmd_uninit; 11533 11534 ret = hclge_get_cap(hdev); 11535 if (ret) 11536 goto err_cmd_uninit; 11537 11538 ret = hclge_query_dev_specs(hdev); 11539 if (ret) { 11540 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n", 11541 ret); 11542 goto err_cmd_uninit; 11543 } 11544 11545 ret = hclge_configure(hdev); 11546 if (ret) { 11547 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 11548 goto err_cmd_uninit; 11549 } 11550 11551 ret = hclge_init_msi(hdev); 11552 if (ret) { 11553 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 11554 goto err_cmd_uninit; 11555 } 11556 11557 ret = hclge_misc_irq_init(hdev); 11558 if (ret) 11559 goto err_msi_uninit; 11560 11561 ret = hclge_alloc_tqps(hdev); 11562 if (ret) { 11563 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 11564 goto err_msi_irq_uninit; 11565 } 11566 11567 ret = hclge_alloc_vport(hdev); 11568 if (ret) 11569 goto err_msi_irq_uninit; 11570 11571 ret = hclge_map_tqp(hdev); 11572 if (ret) 11573 goto err_msi_irq_uninit; 11574 11575 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER && 11576 !hnae3_dev_phy_imp_supported(hdev)) { 11577 ret = hclge_mac_mdio_config(hdev); 11578 if (ret) 11579 goto err_msi_irq_uninit; 11580 } 11581 11582 ret = hclge_init_umv_space(hdev); 11583 if (ret) 11584 goto err_mdiobus_unreg; 11585 11586 ret = hclge_mac_init(hdev); 11587 if (ret) { 11588 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 11589 goto err_mdiobus_unreg; 11590 } 11591 11592 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 11593 if (ret) { 11594 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 11595 goto err_mdiobus_unreg; 11596 } 11597 11598 ret = hclge_config_gro(hdev); 11599 if (ret) 11600 goto err_mdiobus_unreg; 11601 11602 ret = hclge_init_vlan_config(hdev); 11603 if (ret) { 11604 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 11605 goto err_mdiobus_unreg; 11606 } 11607 11608 ret = hclge_tm_schd_init(hdev); 11609 if (ret) { 11610 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 11611 goto err_mdiobus_unreg; 11612 } 11613 11614 ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev, 11615 &hdev->rss_cfg); 11616 if (ret) { 11617 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 11618 goto err_mdiobus_unreg; 11619 } 11620 11621 ret = hclge_rss_init_hw(hdev); 11622 if (ret) { 11623 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 11624 goto err_mdiobus_unreg; 11625 } 11626 11627 ret = init_mgr_tbl(hdev); 11628 if (ret) { 11629 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 11630 goto err_mdiobus_unreg; 11631 } 11632 11633 ret = hclge_init_fd_config(hdev); 11634 if (ret) { 11635 dev_err(&pdev->dev, 11636 "fd table init fail, ret=%d\n", ret); 11637 goto err_mdiobus_unreg; 11638 } 11639 11640 ret = hclge_ptp_init(hdev); 11641 if (ret) 11642 goto err_mdiobus_unreg; 11643 11644 ret = hclge_update_port_info(hdev); 11645 if (ret) 11646 goto err_mdiobus_unreg; 11647 11648 INIT_KFIFO(hdev->mac_tnl_log); 11649 11650 hclge_dcb_ops_set(hdev); 11651 11652 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0); 11653 INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task); 11654 11655 hclge_clear_all_event_cause(hdev); 11656 hclge_clear_resetting_state(hdev); 11657 11658 /* Log and clear the hw errors those already occurred */ 11659 if (hnae3_dev_ras_imp_supported(hdev)) 11660 hclge_handle_occurred_error(hdev); 11661 else 11662 hclge_handle_all_hns_hw_errors(ae_dev); 11663 11664 /* request delayed reset for the error recovery because an immediate 11665 * global reset on a PF affecting pending initialization of other PFs 11666 */ 11667 if (ae_dev->hw_err_reset_req) { 11668 enum hnae3_reset_type reset_level; 11669 11670 reset_level = hclge_get_reset_level(ae_dev, 11671 &ae_dev->hw_err_reset_req); 11672 hclge_set_def_reset_request(ae_dev, reset_level); 11673 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 11674 } 11675 11676 hclge_init_rxd_adv_layout(hdev); 11677 11678 /* Enable MISC vector(vector0) */ 11679 hclge_enable_vector(&hdev->misc_vector, true); 11680 11681 hclge_state_init(hdev); 11682 hdev->last_reset_time = jiffies; 11683 11684 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", 11685 HCLGE_DRIVER_NAME); 11686 11687 hclge_task_schedule(hdev, round_jiffies_relative(HZ)); 11688 11689 return 0; 11690 11691 err_mdiobus_unreg: 11692 if (hdev->hw.mac.phydev) 11693 mdiobus_unregister(hdev->hw.mac.mdio_bus); 11694 err_msi_irq_uninit: 11695 hclge_misc_irq_uninit(hdev); 11696 err_msi_uninit: 11697 pci_free_irq_vectors(pdev); 11698 err_cmd_uninit: 11699 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 11700 err_devlink_uninit: 11701 hclge_devlink_uninit(hdev); 11702 err_pci_uninit: 11703 pcim_iounmap(pdev, hdev->hw.hw.io_base); 11704 pci_clear_master(pdev); 11705 pci_release_regions(pdev); 11706 pci_disable_device(pdev); 11707 out: 11708 mutex_destroy(&hdev->vport_lock); 11709 return ret; 11710 } 11711 11712 static void hclge_stats_clear(struct hclge_dev *hdev) 11713 { 11714 memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats)); 11715 memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats)); 11716 } 11717 11718 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11719 { 11720 return hclge_config_switch_param(hdev, vf, enable, 11721 HCLGE_SWITCH_ANTI_SPOOF_MASK); 11722 } 11723 11724 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 11725 { 11726 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 11727 HCLGE_FILTER_FE_NIC_INGRESS_B, 11728 enable, vf); 11729 } 11730 11731 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) 11732 { 11733 int ret; 11734 11735 ret = hclge_set_mac_spoofchk(hdev, vf, enable); 11736 if (ret) { 11737 dev_err(&hdev->pdev->dev, 11738 "Set vf %d mac spoof check %s failed, ret=%d\n", 11739 vf, enable ? "on" : "off", ret); 11740 return ret; 11741 } 11742 11743 ret = hclge_set_vlan_spoofchk(hdev, vf, enable); 11744 if (ret) 11745 dev_err(&hdev->pdev->dev, 11746 "Set vf %d vlan spoof check %s failed, ret=%d\n", 11747 vf, enable ? "on" : "off", ret); 11748 11749 return ret; 11750 } 11751 11752 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf, 11753 bool enable) 11754 { 11755 struct hclge_vport *vport = hclge_get_vport(handle); 11756 struct hclge_dev *hdev = vport->back; 11757 u32 new_spoofchk = enable ? 1 : 0; 11758 int ret; 11759 11760 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11761 return -EOPNOTSUPP; 11762 11763 vport = hclge_get_vf_vport(hdev, vf); 11764 if (!vport) 11765 return -EINVAL; 11766 11767 if (vport->vf_info.spoofchk == new_spoofchk) 11768 return 0; 11769 11770 if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full)) 11771 dev_warn(&hdev->pdev->dev, 11772 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n", 11773 vf); 11774 else if (enable && hclge_is_umv_space_full(vport, true)) 11775 dev_warn(&hdev->pdev->dev, 11776 "vf %d mac table is full, enable spoof check may cause its packet send fail\n", 11777 vf); 11778 11779 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable); 11780 if (ret) 11781 return ret; 11782 11783 vport->vf_info.spoofchk = new_spoofchk; 11784 return 0; 11785 } 11786 11787 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev) 11788 { 11789 struct hclge_vport *vport = hdev->vport; 11790 int ret; 11791 int i; 11792 11793 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 11794 return 0; 11795 11796 /* resume the vf spoof check state after reset */ 11797 for (i = 0; i < hdev->num_alloc_vport; i++) { 11798 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, 11799 vport->vf_info.spoofchk); 11800 if (ret) 11801 return ret; 11802 11803 vport++; 11804 } 11805 11806 return 0; 11807 } 11808 11809 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable) 11810 { 11811 struct hclge_vport *vport = hclge_get_vport(handle); 11812 struct hclge_dev *hdev = vport->back; 11813 u32 new_trusted = enable ? 1 : 0; 11814 11815 vport = hclge_get_vf_vport(hdev, vf); 11816 if (!vport) 11817 return -EINVAL; 11818 11819 if (vport->vf_info.trusted == new_trusted) 11820 return 0; 11821 11822 vport->vf_info.trusted = new_trusted; 11823 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 11824 hclge_task_schedule(hdev, 0); 11825 11826 return 0; 11827 } 11828 11829 static void hclge_reset_vf_rate(struct hclge_dev *hdev) 11830 { 11831 int ret; 11832 int vf; 11833 11834 /* reset vf rate to default value */ 11835 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 11836 struct hclge_vport *vport = &hdev->vport[vf]; 11837 11838 vport->vf_info.max_tx_rate = 0; 11839 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); 11840 if (ret) 11841 dev_err(&hdev->pdev->dev, 11842 "vf%d failed to reset to default, ret=%d\n", 11843 vf - HCLGE_VF_VPORT_START_NUM, ret); 11844 } 11845 } 11846 11847 static int hclge_vf_rate_param_check(struct hclge_dev *hdev, 11848 int min_tx_rate, int max_tx_rate) 11849 { 11850 if (min_tx_rate != 0 || 11851 max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) { 11852 dev_err(&hdev->pdev->dev, 11853 "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n", 11854 min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed); 11855 return -EINVAL; 11856 } 11857 11858 return 0; 11859 } 11860 11861 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf, 11862 int min_tx_rate, int max_tx_rate, bool force) 11863 { 11864 struct hclge_vport *vport = hclge_get_vport(handle); 11865 struct hclge_dev *hdev = vport->back; 11866 int ret; 11867 11868 ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate); 11869 if (ret) 11870 return ret; 11871 11872 vport = hclge_get_vf_vport(hdev, vf); 11873 if (!vport) 11874 return -EINVAL; 11875 11876 if (!force && max_tx_rate == vport->vf_info.max_tx_rate) 11877 return 0; 11878 11879 ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); 11880 if (ret) 11881 return ret; 11882 11883 vport->vf_info.max_tx_rate = max_tx_rate; 11884 11885 return 0; 11886 } 11887 11888 static int hclge_resume_vf_rate(struct hclge_dev *hdev) 11889 { 11890 struct hnae3_handle *handle = &hdev->vport->nic; 11891 struct hclge_vport *vport; 11892 int ret; 11893 int vf; 11894 11895 /* resume the vf max_tx_rate after reset */ 11896 for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) { 11897 vport = hclge_get_vf_vport(hdev, vf); 11898 if (!vport) 11899 return -EINVAL; 11900 11901 /* zero means max rate, after reset, firmware already set it to 11902 * max rate, so just continue. 11903 */ 11904 if (!vport->vf_info.max_tx_rate) 11905 continue; 11906 11907 ret = hclge_set_vf_rate(handle, vf, 0, 11908 vport->vf_info.max_tx_rate, true); 11909 if (ret) { 11910 dev_err(&hdev->pdev->dev, 11911 "vf%d failed to resume tx_rate:%u, ret=%d\n", 11912 vf, vport->vf_info.max_tx_rate, ret); 11913 return ret; 11914 } 11915 } 11916 11917 return 0; 11918 } 11919 11920 static void hclge_reset_vport_state(struct hclge_dev *hdev) 11921 { 11922 struct hclge_vport *vport = hdev->vport; 11923 int i; 11924 11925 for (i = 0; i < hdev->num_alloc_vport; i++) { 11926 hclge_vport_stop(vport); 11927 vport++; 11928 } 11929 } 11930 11931 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 11932 { 11933 struct hclge_dev *hdev = ae_dev->priv; 11934 struct pci_dev *pdev = ae_dev->pdev; 11935 int ret; 11936 11937 set_bit(HCLGE_STATE_DOWN, &hdev->state); 11938 11939 hclge_stats_clear(hdev); 11940 /* NOTE: pf reset needn't to clear or restore pf and vf table entry. 11941 * so here should not clean table in memory. 11942 */ 11943 if (hdev->reset_type == HNAE3_IMP_RESET || 11944 hdev->reset_type == HNAE3_GLOBAL_RESET) { 11945 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 11946 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full)); 11947 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport); 11948 hclge_reset_umv_space(hdev); 11949 } 11950 11951 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 11952 true, hdev->reset_pending); 11953 if (ret) { 11954 dev_err(&pdev->dev, "Cmd queue init failed\n"); 11955 return ret; 11956 } 11957 11958 ret = hclge_map_tqp(hdev); 11959 if (ret) { 11960 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 11961 return ret; 11962 } 11963 11964 ret = hclge_mac_init(hdev); 11965 if (ret) { 11966 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 11967 return ret; 11968 } 11969 11970 ret = hclge_tp_port_init(hdev); 11971 if (ret) { 11972 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n", 11973 ret); 11974 return ret; 11975 } 11976 11977 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 11978 if (ret) { 11979 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 11980 return ret; 11981 } 11982 11983 ret = hclge_config_gro(hdev); 11984 if (ret) 11985 return ret; 11986 11987 ret = hclge_init_vlan_config(hdev); 11988 if (ret) { 11989 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 11990 return ret; 11991 } 11992 11993 ret = hclge_tm_init_hw(hdev, true); 11994 if (ret) { 11995 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 11996 return ret; 11997 } 11998 11999 ret = hclge_rss_init_hw(hdev); 12000 if (ret) { 12001 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 12002 return ret; 12003 } 12004 12005 ret = init_mgr_tbl(hdev); 12006 if (ret) { 12007 dev_err(&pdev->dev, 12008 "failed to reinit manager table, ret = %d\n", ret); 12009 return ret; 12010 } 12011 12012 ret = hclge_init_fd_config(hdev); 12013 if (ret) { 12014 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret); 12015 return ret; 12016 } 12017 12018 ret = hclge_ptp_init(hdev); 12019 if (ret) 12020 return ret; 12021 12022 /* Log and clear the hw errors those already occurred */ 12023 if (hnae3_dev_ras_imp_supported(hdev)) 12024 hclge_handle_occurred_error(hdev); 12025 else 12026 hclge_handle_all_hns_hw_errors(ae_dev); 12027 12028 /* Re-enable the hw error interrupts because 12029 * the interrupts get disabled on global reset. 12030 */ 12031 ret = hclge_config_nic_hw_error(hdev, true); 12032 if (ret) { 12033 dev_err(&pdev->dev, 12034 "fail(%d) to re-enable NIC hw error interrupts\n", 12035 ret); 12036 return ret; 12037 } 12038 12039 if (hdev->roce_client) { 12040 ret = hclge_config_rocee_ras_interrupt(hdev, true); 12041 if (ret) { 12042 dev_err(&pdev->dev, 12043 "fail(%d) to re-enable roce ras interrupts\n", 12044 ret); 12045 return ret; 12046 } 12047 } 12048 12049 hclge_reset_vport_state(hdev); 12050 ret = hclge_reset_vport_spoofchk(hdev); 12051 if (ret) 12052 return ret; 12053 12054 ret = hclge_resume_vf_rate(hdev); 12055 if (ret) 12056 return ret; 12057 12058 hclge_init_rxd_adv_layout(hdev); 12059 12060 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 12061 HCLGE_DRIVER_NAME); 12062 12063 return 0; 12064 } 12065 12066 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 12067 { 12068 struct hclge_dev *hdev = ae_dev->priv; 12069 struct hclge_mac *mac = &hdev->hw.mac; 12070 12071 hclge_reset_vf_rate(hdev); 12072 hclge_clear_vf_vlan(hdev); 12073 hclge_state_uninit(hdev); 12074 hclge_ptp_uninit(hdev); 12075 hclge_uninit_rxd_adv_layout(hdev); 12076 hclge_uninit_mac_table(hdev); 12077 hclge_del_all_fd_entries(hdev); 12078 12079 if (mac->phydev) 12080 mdiobus_unregister(mac->mdio_bus); 12081 12082 /* Disable MISC vector(vector0) */ 12083 hclge_enable_vector(&hdev->misc_vector, false); 12084 synchronize_irq(hdev->misc_vector.vector_irq); 12085 12086 /* Disable all hw interrupts */ 12087 hclge_config_mac_tnl_int(hdev, false); 12088 hclge_config_nic_hw_error(hdev, false); 12089 hclge_config_rocee_ras_interrupt(hdev, false); 12090 12091 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 12092 hclge_misc_irq_uninit(hdev); 12093 hclge_devlink_uninit(hdev); 12094 hclge_pci_uninit(hdev); 12095 hclge_uninit_vport_vlan_table(hdev); 12096 mutex_destroy(&hdev->vport_lock); 12097 ae_dev->priv = NULL; 12098 } 12099 12100 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 12101 { 12102 struct hclge_vport *vport = hclge_get_vport(handle); 12103 struct hclge_dev *hdev = vport->back; 12104 12105 return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps); 12106 } 12107 12108 static void hclge_get_channels(struct hnae3_handle *handle, 12109 struct ethtool_channels *ch) 12110 { 12111 ch->max_combined = hclge_get_max_channels(handle); 12112 ch->other_count = 1; 12113 ch->max_other = 1; 12114 ch->combined_count = handle->kinfo.rss_size; 12115 } 12116 12117 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 12118 u16 *alloc_tqps, u16 *max_rss_size) 12119 { 12120 struct hclge_vport *vport = hclge_get_vport(handle); 12121 struct hclge_dev *hdev = vport->back; 12122 12123 *alloc_tqps = vport->alloc_tqps; 12124 *max_rss_size = hdev->pf_rss_size_max; 12125 } 12126 12127 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle) 12128 { 12129 struct hclge_vport *vport = hclge_get_vport(handle); 12130 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 12131 struct hclge_dev *hdev = vport->back; 12132 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 12133 u16 tc_valid[HCLGE_MAX_TC_NUM]; 12134 u16 roundup_size; 12135 unsigned int i; 12136 12137 roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size); 12138 roundup_size = ilog2(roundup_size); 12139 /* Set the RSS TC mode according to the new RSS size */ 12140 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 12141 tc_valid[i] = 0; 12142 12143 if (!(hdev->hw_tc_map & BIT(i))) 12144 continue; 12145 12146 tc_valid[i] = 1; 12147 tc_size[i] = roundup_size; 12148 tc_offset[i] = vport->nic.kinfo.rss_size * i; 12149 } 12150 12151 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 12152 tc_size); 12153 } 12154 12155 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 12156 bool rxfh_configured) 12157 { 12158 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 12159 struct hclge_vport *vport = hclge_get_vport(handle); 12160 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 12161 struct hclge_dev *hdev = vport->back; 12162 u16 cur_rss_size = kinfo->rss_size; 12163 u16 cur_tqps = kinfo->num_tqps; 12164 u32 *rss_indir; 12165 unsigned int i; 12166 int ret; 12167 12168 kinfo->req_rss_size = new_tqps_num; 12169 12170 ret = hclge_tm_vport_map_update(hdev); 12171 if (ret) { 12172 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret); 12173 return ret; 12174 } 12175 12176 ret = hclge_set_rss_tc_mode_cfg(handle); 12177 if (ret) 12178 return ret; 12179 12180 /* RSS indirection table has been configured by user */ 12181 if (rxfh_configured) 12182 goto out; 12183 12184 /* Reinitializes the rss indirect table according to the new RSS size */ 12185 rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32), 12186 GFP_KERNEL); 12187 if (!rss_indir) 12188 return -ENOMEM; 12189 12190 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 12191 rss_indir[i] = i % kinfo->rss_size; 12192 12193 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 12194 if (ret) 12195 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 12196 ret); 12197 12198 kfree(rss_indir); 12199 12200 out: 12201 if (!ret) 12202 dev_info(&hdev->pdev->dev, 12203 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 12204 cur_rss_size, kinfo->rss_size, 12205 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 12206 12207 return ret; 12208 } 12209 12210 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit, 12211 u32 *regs_num_64_bit) 12212 { 12213 struct hclge_desc desc; 12214 u32 total_num; 12215 int ret; 12216 12217 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true); 12218 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12219 if (ret) { 12220 dev_err(&hdev->pdev->dev, 12221 "Query register number cmd failed, ret = %d.\n", ret); 12222 return ret; 12223 } 12224 12225 *regs_num_32_bit = le32_to_cpu(desc.data[0]); 12226 *regs_num_64_bit = le32_to_cpu(desc.data[1]); 12227 12228 total_num = *regs_num_32_bit + *regs_num_64_bit; 12229 if (!total_num) 12230 return -EINVAL; 12231 12232 return 0; 12233 } 12234 12235 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num, 12236 void *data) 12237 { 12238 #define HCLGE_32_BIT_REG_RTN_DATANUM 8 12239 #define HCLGE_32_BIT_DESC_NODATA_LEN 2 12240 12241 struct hclge_desc *desc; 12242 u32 *reg_val = data; 12243 __le32 *desc_data; 12244 int nodata_num; 12245 int cmd_num; 12246 int i, k, n; 12247 int ret; 12248 12249 if (regs_num == 0) 12250 return 0; 12251 12252 nodata_num = HCLGE_32_BIT_DESC_NODATA_LEN; 12253 cmd_num = DIV_ROUND_UP(regs_num + nodata_num, 12254 HCLGE_32_BIT_REG_RTN_DATANUM); 12255 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 12256 if (!desc) 12257 return -ENOMEM; 12258 12259 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true); 12260 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 12261 if (ret) { 12262 dev_err(&hdev->pdev->dev, 12263 "Query 32 bit register cmd failed, ret = %d.\n", ret); 12264 kfree(desc); 12265 return ret; 12266 } 12267 12268 for (i = 0; i < cmd_num; i++) { 12269 if (i == 0) { 12270 desc_data = (__le32 *)(&desc[i].data[0]); 12271 n = HCLGE_32_BIT_REG_RTN_DATANUM - nodata_num; 12272 } else { 12273 desc_data = (__le32 *)(&desc[i]); 12274 n = HCLGE_32_BIT_REG_RTN_DATANUM; 12275 } 12276 for (k = 0; k < n; k++) { 12277 *reg_val++ = le32_to_cpu(*desc_data++); 12278 12279 regs_num--; 12280 if (!regs_num) 12281 break; 12282 } 12283 } 12284 12285 kfree(desc); 12286 return 0; 12287 } 12288 12289 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num, 12290 void *data) 12291 { 12292 #define HCLGE_64_BIT_REG_RTN_DATANUM 4 12293 #define HCLGE_64_BIT_DESC_NODATA_LEN 1 12294 12295 struct hclge_desc *desc; 12296 u64 *reg_val = data; 12297 __le64 *desc_data; 12298 int nodata_len; 12299 int cmd_num; 12300 int i, k, n; 12301 int ret; 12302 12303 if (regs_num == 0) 12304 return 0; 12305 12306 nodata_len = HCLGE_64_BIT_DESC_NODATA_LEN; 12307 cmd_num = DIV_ROUND_UP(regs_num + nodata_len, 12308 HCLGE_64_BIT_REG_RTN_DATANUM); 12309 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); 12310 if (!desc) 12311 return -ENOMEM; 12312 12313 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true); 12314 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); 12315 if (ret) { 12316 dev_err(&hdev->pdev->dev, 12317 "Query 64 bit register cmd failed, ret = %d.\n", ret); 12318 kfree(desc); 12319 return ret; 12320 } 12321 12322 for (i = 0; i < cmd_num; i++) { 12323 if (i == 0) { 12324 desc_data = (__le64 *)(&desc[i].data[0]); 12325 n = HCLGE_64_BIT_REG_RTN_DATANUM - nodata_len; 12326 } else { 12327 desc_data = (__le64 *)(&desc[i]); 12328 n = HCLGE_64_BIT_REG_RTN_DATANUM; 12329 } 12330 for (k = 0; k < n; k++) { 12331 *reg_val++ = le64_to_cpu(*desc_data++); 12332 12333 regs_num--; 12334 if (!regs_num) 12335 break; 12336 } 12337 } 12338 12339 kfree(desc); 12340 return 0; 12341 } 12342 12343 #define MAX_SEPARATE_NUM 4 12344 #define SEPARATOR_VALUE 0xFDFCFBFA 12345 #define REG_NUM_PER_LINE 4 12346 #define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32)) 12347 #define REG_SEPARATOR_LINE 1 12348 #define REG_NUM_REMAIN_MASK 3 12349 12350 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc) 12351 { 12352 int i; 12353 12354 /* initialize command BD except the last one */ 12355 for (i = 0; i < HCLGE_GET_DFX_REG_TYPE_CNT - 1; i++) { 12356 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM, 12357 true); 12358 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12359 } 12360 12361 /* initialize the last command BD */ 12362 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM, true); 12363 12364 return hclge_cmd_send(&hdev->hw, desc, HCLGE_GET_DFX_REG_TYPE_CNT); 12365 } 12366 12367 static int hclge_get_dfx_reg_bd_num(struct hclge_dev *hdev, 12368 int *bd_num_list, 12369 u32 type_num) 12370 { 12371 u32 entries_per_desc, desc_index, index, offset, i; 12372 struct hclge_desc desc[HCLGE_GET_DFX_REG_TYPE_CNT]; 12373 int ret; 12374 12375 ret = hclge_query_bd_num_cmd_send(hdev, desc); 12376 if (ret) { 12377 dev_err(&hdev->pdev->dev, 12378 "Get dfx bd num fail, status is %d.\n", ret); 12379 return ret; 12380 } 12381 12382 entries_per_desc = ARRAY_SIZE(desc[0].data); 12383 for (i = 0; i < type_num; i++) { 12384 offset = hclge_dfx_bd_offset_list[i]; 12385 index = offset % entries_per_desc; 12386 desc_index = offset / entries_per_desc; 12387 bd_num_list[i] = le32_to_cpu(desc[desc_index].data[index]); 12388 } 12389 12390 return ret; 12391 } 12392 12393 static int hclge_dfx_reg_cmd_send(struct hclge_dev *hdev, 12394 struct hclge_desc *desc_src, int bd_num, 12395 enum hclge_opcode_type cmd) 12396 { 12397 struct hclge_desc *desc = desc_src; 12398 int i, ret; 12399 12400 hclge_cmd_setup_basic_desc(desc, cmd, true); 12401 for (i = 0; i < bd_num - 1; i++) { 12402 desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12403 desc++; 12404 hclge_cmd_setup_basic_desc(desc, cmd, true); 12405 } 12406 12407 desc = desc_src; 12408 ret = hclge_cmd_send(&hdev->hw, desc, bd_num); 12409 if (ret) 12410 dev_err(&hdev->pdev->dev, 12411 "Query dfx reg cmd(0x%x) send fail, status is %d.\n", 12412 cmd, ret); 12413 12414 return ret; 12415 } 12416 12417 static int hclge_dfx_reg_fetch_data(struct hclge_desc *desc_src, int bd_num, 12418 void *data) 12419 { 12420 int entries_per_desc, reg_num, separator_num, desc_index, index, i; 12421 struct hclge_desc *desc = desc_src; 12422 u32 *reg = data; 12423 12424 entries_per_desc = ARRAY_SIZE(desc->data); 12425 reg_num = entries_per_desc * bd_num; 12426 separator_num = REG_NUM_PER_LINE - (reg_num & REG_NUM_REMAIN_MASK); 12427 for (i = 0; i < reg_num; i++) { 12428 index = i % entries_per_desc; 12429 desc_index = i / entries_per_desc; 12430 *reg++ = le32_to_cpu(desc[desc_index].data[index]); 12431 } 12432 for (i = 0; i < separator_num; i++) 12433 *reg++ = SEPARATOR_VALUE; 12434 12435 return reg_num + separator_num; 12436 } 12437 12438 static int hclge_get_dfx_reg_len(struct hclge_dev *hdev, int *len) 12439 { 12440 u32 dfx_reg_type_num = ARRAY_SIZE(hclge_dfx_bd_offset_list); 12441 int data_len_per_desc, bd_num, i; 12442 int *bd_num_list; 12443 u32 data_len; 12444 int ret; 12445 12446 bd_num_list = kcalloc(dfx_reg_type_num, sizeof(int), GFP_KERNEL); 12447 if (!bd_num_list) 12448 return -ENOMEM; 12449 12450 ret = hclge_get_dfx_reg_bd_num(hdev, bd_num_list, dfx_reg_type_num); 12451 if (ret) { 12452 dev_err(&hdev->pdev->dev, 12453 "Get dfx reg bd num fail, status is %d.\n", ret); 12454 goto out; 12455 } 12456 12457 data_len_per_desc = sizeof_field(struct hclge_desc, data); 12458 *len = 0; 12459 for (i = 0; i < dfx_reg_type_num; i++) { 12460 bd_num = bd_num_list[i]; 12461 data_len = data_len_per_desc * bd_num; 12462 *len += (data_len / REG_LEN_PER_LINE + 1) * REG_LEN_PER_LINE; 12463 } 12464 12465 out: 12466 kfree(bd_num_list); 12467 return ret; 12468 } 12469 12470 static int hclge_get_dfx_reg(struct hclge_dev *hdev, void *data) 12471 { 12472 u32 dfx_reg_type_num = ARRAY_SIZE(hclge_dfx_bd_offset_list); 12473 int bd_num, bd_num_max, buf_len, i; 12474 struct hclge_desc *desc_src; 12475 int *bd_num_list; 12476 u32 *reg = data; 12477 int ret; 12478 12479 bd_num_list = kcalloc(dfx_reg_type_num, sizeof(int), GFP_KERNEL); 12480 if (!bd_num_list) 12481 return -ENOMEM; 12482 12483 ret = hclge_get_dfx_reg_bd_num(hdev, bd_num_list, dfx_reg_type_num); 12484 if (ret) { 12485 dev_err(&hdev->pdev->dev, 12486 "Get dfx reg bd num fail, status is %d.\n", ret); 12487 goto out; 12488 } 12489 12490 bd_num_max = bd_num_list[0]; 12491 for (i = 1; i < dfx_reg_type_num; i++) 12492 bd_num_max = max_t(int, bd_num_max, bd_num_list[i]); 12493 12494 buf_len = sizeof(*desc_src) * bd_num_max; 12495 desc_src = kzalloc(buf_len, GFP_KERNEL); 12496 if (!desc_src) { 12497 ret = -ENOMEM; 12498 goto out; 12499 } 12500 12501 for (i = 0; i < dfx_reg_type_num; i++) { 12502 bd_num = bd_num_list[i]; 12503 ret = hclge_dfx_reg_cmd_send(hdev, desc_src, bd_num, 12504 hclge_dfx_reg_opcode_list[i]); 12505 if (ret) { 12506 dev_err(&hdev->pdev->dev, 12507 "Get dfx reg fail, status is %d.\n", ret); 12508 break; 12509 } 12510 12511 reg += hclge_dfx_reg_fetch_data(desc_src, bd_num, reg); 12512 } 12513 12514 kfree(desc_src); 12515 out: 12516 kfree(bd_num_list); 12517 return ret; 12518 } 12519 12520 static int hclge_fetch_pf_reg(struct hclge_dev *hdev, void *data, 12521 struct hnae3_knic_private_info *kinfo) 12522 { 12523 #define HCLGE_RING_REG_OFFSET 0x200 12524 #define HCLGE_RING_INT_REG_OFFSET 0x4 12525 12526 int i, j, reg_num, separator_num; 12527 int data_num_sum; 12528 u32 *reg = data; 12529 12530 /* fetching per-PF registers valus from PF PCIe register space */ 12531 reg_num = ARRAY_SIZE(cmdq_reg_addr_list); 12532 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12533 for (i = 0; i < reg_num; i++) 12534 *reg++ = hclge_read_dev(&hdev->hw, cmdq_reg_addr_list[i]); 12535 for (i = 0; i < separator_num; i++) 12536 *reg++ = SEPARATOR_VALUE; 12537 data_num_sum = reg_num + separator_num; 12538 12539 reg_num = ARRAY_SIZE(common_reg_addr_list); 12540 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12541 for (i = 0; i < reg_num; i++) 12542 *reg++ = hclge_read_dev(&hdev->hw, common_reg_addr_list[i]); 12543 for (i = 0; i < separator_num; i++) 12544 *reg++ = SEPARATOR_VALUE; 12545 data_num_sum += reg_num + separator_num; 12546 12547 reg_num = ARRAY_SIZE(ring_reg_addr_list); 12548 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12549 for (j = 0; j < kinfo->num_tqps; j++) { 12550 for (i = 0; i < reg_num; i++) 12551 *reg++ = hclge_read_dev(&hdev->hw, 12552 ring_reg_addr_list[i] + 12553 HCLGE_RING_REG_OFFSET * j); 12554 for (i = 0; i < separator_num; i++) 12555 *reg++ = SEPARATOR_VALUE; 12556 } 12557 data_num_sum += (reg_num + separator_num) * kinfo->num_tqps; 12558 12559 reg_num = ARRAY_SIZE(tqp_intr_reg_addr_list); 12560 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12561 for (j = 0; j < hdev->num_msi_used - 1; j++) { 12562 for (i = 0; i < reg_num; i++) 12563 *reg++ = hclge_read_dev(&hdev->hw, 12564 tqp_intr_reg_addr_list[i] + 12565 HCLGE_RING_INT_REG_OFFSET * j); 12566 for (i = 0; i < separator_num; i++) 12567 *reg++ = SEPARATOR_VALUE; 12568 } 12569 data_num_sum += (reg_num + separator_num) * (hdev->num_msi_used - 1); 12570 12571 return data_num_sum; 12572 } 12573 12574 static int hclge_get_regs_len(struct hnae3_handle *handle) 12575 { 12576 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines; 12577 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 12578 struct hclge_vport *vport = hclge_get_vport(handle); 12579 struct hclge_dev *hdev = vport->back; 12580 int regs_num_32_bit, regs_num_64_bit, dfx_regs_len; 12581 int regs_lines_32_bit, regs_lines_64_bit; 12582 int ret; 12583 12584 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 12585 if (ret) { 12586 dev_err(&hdev->pdev->dev, 12587 "Get register number failed, ret = %d.\n", ret); 12588 return ret; 12589 } 12590 12591 ret = hclge_get_dfx_reg_len(hdev, &dfx_regs_len); 12592 if (ret) { 12593 dev_err(&hdev->pdev->dev, 12594 "Get dfx reg len failed, ret = %d.\n", ret); 12595 return ret; 12596 } 12597 12598 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 12599 REG_SEPARATOR_LINE; 12600 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 12601 REG_SEPARATOR_LINE; 12602 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 12603 REG_SEPARATOR_LINE; 12604 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 12605 REG_SEPARATOR_LINE; 12606 regs_lines_32_bit = regs_num_32_bit * sizeof(u32) / REG_LEN_PER_LINE + 12607 REG_SEPARATOR_LINE; 12608 regs_lines_64_bit = regs_num_64_bit * sizeof(u64) / REG_LEN_PER_LINE + 12609 REG_SEPARATOR_LINE; 12610 12611 return (cmdq_lines + common_lines + ring_lines * kinfo->num_tqps + 12612 tqp_intr_lines * (hdev->num_msi_used - 1) + regs_lines_32_bit + 12613 regs_lines_64_bit) * REG_LEN_PER_LINE + dfx_regs_len; 12614 } 12615 12616 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version, 12617 void *data) 12618 { 12619 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 12620 struct hclge_vport *vport = hclge_get_vport(handle); 12621 struct hclge_dev *hdev = vport->back; 12622 u32 regs_num_32_bit, regs_num_64_bit; 12623 int i, reg_num, separator_num, ret; 12624 u32 *reg = data; 12625 12626 *version = hdev->fw_version; 12627 12628 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); 12629 if (ret) { 12630 dev_err(&hdev->pdev->dev, 12631 "Get register number failed, ret = %d.\n", ret); 12632 return; 12633 } 12634 12635 reg += hclge_fetch_pf_reg(hdev, reg, kinfo); 12636 12637 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, reg); 12638 if (ret) { 12639 dev_err(&hdev->pdev->dev, 12640 "Get 32 bit register failed, ret = %d.\n", ret); 12641 return; 12642 } 12643 reg_num = regs_num_32_bit; 12644 reg += reg_num; 12645 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12646 for (i = 0; i < separator_num; i++) 12647 *reg++ = SEPARATOR_VALUE; 12648 12649 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, reg); 12650 if (ret) { 12651 dev_err(&hdev->pdev->dev, 12652 "Get 64 bit register failed, ret = %d.\n", ret); 12653 return; 12654 } 12655 reg_num = regs_num_64_bit * 2; 12656 reg += reg_num; 12657 separator_num = MAX_SEPARATE_NUM - (reg_num & REG_NUM_REMAIN_MASK); 12658 for (i = 0; i < separator_num; i++) 12659 *reg++ = SEPARATOR_VALUE; 12660 12661 ret = hclge_get_dfx_reg(hdev, reg); 12662 if (ret) 12663 dev_err(&hdev->pdev->dev, 12664 "Get dfx register failed, ret = %d.\n", ret); 12665 } 12666 12667 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 12668 { 12669 struct hclge_set_led_state_cmd *req; 12670 struct hclge_desc desc; 12671 int ret; 12672 12673 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 12674 12675 req = (struct hclge_set_led_state_cmd *)desc.data; 12676 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 12677 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 12678 12679 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12680 if (ret) 12681 dev_err(&hdev->pdev->dev, 12682 "Send set led state cmd error, ret =%d\n", ret); 12683 12684 return ret; 12685 } 12686 12687 enum hclge_led_status { 12688 HCLGE_LED_OFF, 12689 HCLGE_LED_ON, 12690 HCLGE_LED_NO_CHANGE = 0xFF, 12691 }; 12692 12693 static int hclge_set_led_id(struct hnae3_handle *handle, 12694 enum ethtool_phys_id_state status) 12695 { 12696 struct hclge_vport *vport = hclge_get_vport(handle); 12697 struct hclge_dev *hdev = vport->back; 12698 12699 switch (status) { 12700 case ETHTOOL_ID_ACTIVE: 12701 return hclge_set_led_status(hdev, HCLGE_LED_ON); 12702 case ETHTOOL_ID_INACTIVE: 12703 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 12704 default: 12705 return -EINVAL; 12706 } 12707 } 12708 12709 static void hclge_get_link_mode(struct hnae3_handle *handle, 12710 unsigned long *supported, 12711 unsigned long *advertising) 12712 { 12713 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 12714 struct hclge_vport *vport = hclge_get_vport(handle); 12715 struct hclge_dev *hdev = vport->back; 12716 unsigned int idx = 0; 12717 12718 for (; idx < size; idx++) { 12719 supported[idx] = hdev->hw.mac.supported[idx]; 12720 advertising[idx] = hdev->hw.mac.advertising[idx]; 12721 } 12722 } 12723 12724 static int hclge_gro_en(struct hnae3_handle *handle, bool enable) 12725 { 12726 struct hclge_vport *vport = hclge_get_vport(handle); 12727 struct hclge_dev *hdev = vport->back; 12728 bool gro_en_old = hdev->gro_en; 12729 int ret; 12730 12731 hdev->gro_en = enable; 12732 ret = hclge_config_gro(hdev); 12733 if (ret) 12734 hdev->gro_en = gro_en_old; 12735 12736 return ret; 12737 } 12738 12739 static void hclge_sync_promisc_mode(struct hclge_dev *hdev) 12740 { 12741 struct hclge_vport *vport = &hdev->vport[0]; 12742 struct hnae3_handle *handle = &vport->nic; 12743 u8 tmp_flags; 12744 int ret; 12745 u16 i; 12746 12747 if (vport->last_promisc_flags != vport->overflow_promisc_flags) { 12748 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 12749 vport->last_promisc_flags = vport->overflow_promisc_flags; 12750 } 12751 12752 if (test_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state)) { 12753 tmp_flags = handle->netdev_flags | vport->last_promisc_flags; 12754 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE, 12755 tmp_flags & HNAE3_MPE); 12756 if (!ret) { 12757 clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12758 &vport->state); 12759 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 12760 &vport->state); 12761 } 12762 } 12763 12764 for (i = 1; i < hdev->num_alloc_vport; i++) { 12765 bool uc_en = false; 12766 bool mc_en = false; 12767 bool bc_en; 12768 12769 vport = &hdev->vport[i]; 12770 12771 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12772 &vport->state)) 12773 continue; 12774 12775 if (vport->vf_info.trusted) { 12776 uc_en = vport->vf_info.request_uc_en > 0 || 12777 vport->overflow_promisc_flags & 12778 HNAE3_OVERFLOW_UPE; 12779 mc_en = vport->vf_info.request_mc_en > 0 || 12780 vport->overflow_promisc_flags & 12781 HNAE3_OVERFLOW_MPE; 12782 } 12783 bc_en = vport->vf_info.request_bc_en > 0; 12784 12785 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en, 12786 mc_en, bc_en); 12787 if (ret) { 12788 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 12789 &vport->state); 12790 return; 12791 } 12792 hclge_set_vport_vlan_fltr_change(vport); 12793 } 12794 } 12795 12796 static bool hclge_module_existed(struct hclge_dev *hdev) 12797 { 12798 struct hclge_desc desc; 12799 u32 existed; 12800 int ret; 12801 12802 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true); 12803 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12804 if (ret) { 12805 dev_err(&hdev->pdev->dev, 12806 "failed to get SFP exist state, ret = %d\n", ret); 12807 return false; 12808 } 12809 12810 existed = le32_to_cpu(desc.data[0]); 12811 12812 return existed != 0; 12813 } 12814 12815 /* need 6 bds(total 140 bytes) in one reading 12816 * return the number of bytes actually read, 0 means read failed. 12817 */ 12818 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset, 12819 u32 len, u8 *data) 12820 { 12821 struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM]; 12822 struct hclge_sfp_info_bd0_cmd *sfp_info_bd0; 12823 u16 read_len; 12824 u16 copy_len; 12825 int ret; 12826 int i; 12827 12828 /* setup all 6 bds to read module eeprom info. */ 12829 for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12830 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM, 12831 true); 12832 12833 /* bd0~bd4 need next flag */ 12834 if (i < HCLGE_SFP_INFO_CMD_NUM - 1) 12835 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 12836 } 12837 12838 /* setup bd0, this bd contains offset and read length. */ 12839 sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data; 12840 sfp_info_bd0->offset = cpu_to_le16((u16)offset); 12841 read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN); 12842 sfp_info_bd0->read_len = cpu_to_le16(read_len); 12843 12844 ret = hclge_cmd_send(&hdev->hw, desc, i); 12845 if (ret) { 12846 dev_err(&hdev->pdev->dev, 12847 "failed to get SFP eeprom info, ret = %d\n", ret); 12848 return 0; 12849 } 12850 12851 /* copy sfp info from bd0 to out buffer. */ 12852 copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN); 12853 memcpy(data, sfp_info_bd0->data, copy_len); 12854 read_len = copy_len; 12855 12856 /* copy sfp info from bd1~bd5 to out buffer if needed. */ 12857 for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 12858 if (read_len >= len) 12859 return read_len; 12860 12861 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN); 12862 memcpy(data + read_len, desc[i].data, copy_len); 12863 read_len += copy_len; 12864 } 12865 12866 return read_len; 12867 } 12868 12869 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset, 12870 u32 len, u8 *data) 12871 { 12872 struct hclge_vport *vport = hclge_get_vport(handle); 12873 struct hclge_dev *hdev = vport->back; 12874 u32 read_len = 0; 12875 u16 data_len; 12876 12877 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 12878 return -EOPNOTSUPP; 12879 12880 if (!hclge_module_existed(hdev)) 12881 return -ENXIO; 12882 12883 while (read_len < len) { 12884 data_len = hclge_get_sfp_eeprom_info(hdev, 12885 offset + read_len, 12886 len - read_len, 12887 data + read_len); 12888 if (!data_len) 12889 return -EIO; 12890 12891 read_len += data_len; 12892 } 12893 12894 return 0; 12895 } 12896 12897 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle, 12898 u32 *status_code) 12899 { 12900 struct hclge_vport *vport = hclge_get_vport(handle); 12901 struct hclge_dev *hdev = vport->back; 12902 struct hclge_desc desc; 12903 int ret; 12904 12905 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 12906 return -EOPNOTSUPP; 12907 12908 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true); 12909 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 12910 if (ret) { 12911 dev_err(&hdev->pdev->dev, 12912 "failed to query link diagnosis info, ret = %d\n", ret); 12913 return ret; 12914 } 12915 12916 *status_code = le32_to_cpu(desc.data[0]); 12917 return 0; 12918 } 12919 12920 /* After disable sriov, VF still has some config and info need clean, 12921 * which configed by PF. 12922 */ 12923 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid) 12924 { 12925 struct hclge_dev *hdev = vport->back; 12926 struct hclge_vlan_info vlan_info; 12927 int ret; 12928 12929 /* after disable sriov, clean VF rate configured by PF */ 12930 ret = hclge_tm_qs_shaper_cfg(vport, 0); 12931 if (ret) 12932 dev_err(&hdev->pdev->dev, 12933 "failed to clean vf%d rate config, ret = %d\n", 12934 vfid, ret); 12935 12936 vlan_info.vlan_tag = 0; 12937 vlan_info.qos = 0; 12938 vlan_info.vlan_proto = ETH_P_8021Q; 12939 ret = hclge_update_port_base_vlan_cfg(vport, 12940 HNAE3_PORT_BASE_VLAN_DISABLE, 12941 &vlan_info); 12942 if (ret) 12943 dev_err(&hdev->pdev->dev, 12944 "failed to clean vf%d port base vlan, ret = %d\n", 12945 vfid, ret); 12946 12947 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false); 12948 if (ret) 12949 dev_err(&hdev->pdev->dev, 12950 "failed to clean vf%d spoof config, ret = %d\n", 12951 vfid, ret); 12952 12953 memset(&vport->vf_info, 0, sizeof(vport->vf_info)); 12954 } 12955 12956 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs) 12957 { 12958 struct hclge_dev *hdev = ae_dev->priv; 12959 struct hclge_vport *vport; 12960 int i; 12961 12962 for (i = 0; i < num_vfs; i++) { 12963 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 12964 12965 hclge_clear_vport_vf_info(vport, i); 12966 } 12967 } 12968 12969 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode, 12970 u8 *priority) 12971 { 12972 struct hclge_vport *vport = hclge_get_vport(h); 12973 struct hclge_dev *hdev = vport->back; 12974 12975 if (dscp >= HCLGE_MAX_DSCP) 12976 return -EINVAL; 12977 12978 if (tc_mode) 12979 *tc_mode = vport->nic.kinfo.tc_map_mode; 12980 if (priority) 12981 *priority = hdev->tm_info.dscp_prio[dscp] == HCLGE_PRIO_ID_INVALID ? 0 : 12982 hdev->tm_info.dscp_prio[dscp]; 12983 12984 return 0; 12985 } 12986 12987 static const struct hnae3_ae_ops hclge_ops = { 12988 .init_ae_dev = hclge_init_ae_dev, 12989 .uninit_ae_dev = hclge_uninit_ae_dev, 12990 .reset_prepare = hclge_reset_prepare_general, 12991 .reset_done = hclge_reset_done, 12992 .init_client_instance = hclge_init_client_instance, 12993 .uninit_client_instance = hclge_uninit_client_instance, 12994 .map_ring_to_vector = hclge_map_ring_to_vector, 12995 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 12996 .get_vector = hclge_get_vector, 12997 .put_vector = hclge_put_vector, 12998 .set_promisc_mode = hclge_set_promisc_mode, 12999 .request_update_promisc_mode = hclge_request_update_promisc_mode, 13000 .set_loopback = hclge_set_loopback, 13001 .start = hclge_ae_start, 13002 .stop = hclge_ae_stop, 13003 .client_start = hclge_client_start, 13004 .client_stop = hclge_client_stop, 13005 .get_status = hclge_get_status, 13006 .get_ksettings_an_result = hclge_get_ksettings_an_result, 13007 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 13008 .get_media_type = hclge_get_media_type, 13009 .check_port_speed = hclge_check_port_speed, 13010 .get_fec_stats = hclge_get_fec_stats, 13011 .get_fec = hclge_get_fec, 13012 .set_fec = hclge_set_fec, 13013 .get_rss_key_size = hclge_comm_get_rss_key_size, 13014 .get_rss = hclge_get_rss, 13015 .set_rss = hclge_set_rss, 13016 .set_rss_tuple = hclge_set_rss_tuple, 13017 .get_rss_tuple = hclge_get_rss_tuple, 13018 .get_tc_size = hclge_get_tc_size, 13019 .get_mac_addr = hclge_get_mac_addr, 13020 .set_mac_addr = hclge_set_mac_addr, 13021 .do_ioctl = hclge_do_ioctl, 13022 .add_uc_addr = hclge_add_uc_addr, 13023 .rm_uc_addr = hclge_rm_uc_addr, 13024 .add_mc_addr = hclge_add_mc_addr, 13025 .rm_mc_addr = hclge_rm_mc_addr, 13026 .set_autoneg = hclge_set_autoneg, 13027 .get_autoneg = hclge_get_autoneg, 13028 .restart_autoneg = hclge_restart_autoneg, 13029 .halt_autoneg = hclge_halt_autoneg, 13030 .get_pauseparam = hclge_get_pauseparam, 13031 .set_pauseparam = hclge_set_pauseparam, 13032 .set_mtu = hclge_set_mtu, 13033 .reset_queue = hclge_reset_tqp, 13034 .get_stats = hclge_get_stats, 13035 .get_mac_stats = hclge_get_mac_stat, 13036 .update_stats = hclge_update_stats, 13037 .get_strings = hclge_get_strings, 13038 .get_sset_count = hclge_get_sset_count, 13039 .get_fw_version = hclge_get_fw_version, 13040 .get_mdix_mode = hclge_get_mdix_mode, 13041 .enable_vlan_filter = hclge_enable_vlan_filter, 13042 .set_vlan_filter = hclge_set_vlan_filter, 13043 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 13044 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 13045 .reset_event = hclge_reset_event, 13046 .get_reset_level = hclge_get_reset_level, 13047 .set_default_reset_request = hclge_set_def_reset_request, 13048 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 13049 .set_channels = hclge_set_channels, 13050 .get_channels = hclge_get_channels, 13051 .get_regs_len = hclge_get_regs_len, 13052 .get_regs = hclge_get_regs, 13053 .set_led_id = hclge_set_led_id, 13054 .get_link_mode = hclge_get_link_mode, 13055 .add_fd_entry = hclge_add_fd_entry, 13056 .del_fd_entry = hclge_del_fd_entry, 13057 .get_fd_rule_cnt = hclge_get_fd_rule_cnt, 13058 .get_fd_rule_info = hclge_get_fd_rule_info, 13059 .get_fd_all_rules = hclge_get_all_rules, 13060 .enable_fd = hclge_enable_fd, 13061 .add_arfs_entry = hclge_add_fd_entry_by_arfs, 13062 .dbg_read_cmd = hclge_dbg_read_cmd, 13063 .handle_hw_ras_error = hclge_handle_hw_ras_error, 13064 .get_hw_reset_stat = hclge_get_hw_reset_stat, 13065 .ae_dev_resetting = hclge_ae_dev_resetting, 13066 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt, 13067 .set_gro_en = hclge_gro_en, 13068 .get_global_queue_id = hclge_covert_handle_qid_global, 13069 .set_timer_task = hclge_set_timer_task, 13070 .mac_connect_phy = hclge_mac_connect_phy, 13071 .mac_disconnect_phy = hclge_mac_disconnect_phy, 13072 .get_vf_config = hclge_get_vf_config, 13073 .set_vf_link_state = hclge_set_vf_link_state, 13074 .set_vf_spoofchk = hclge_set_vf_spoofchk, 13075 .set_vf_trust = hclge_set_vf_trust, 13076 .set_vf_rate = hclge_set_vf_rate, 13077 .set_vf_mac = hclge_set_vf_mac, 13078 .get_module_eeprom = hclge_get_module_eeprom, 13079 .get_cmdq_stat = hclge_get_cmdq_stat, 13080 .add_cls_flower = hclge_add_cls_flower, 13081 .del_cls_flower = hclge_del_cls_flower, 13082 .cls_flower_active = hclge_is_cls_flower_active, 13083 .get_phy_link_ksettings = hclge_get_phy_link_ksettings, 13084 .set_phy_link_ksettings = hclge_set_phy_link_ksettings, 13085 .set_tx_hwts_info = hclge_ptp_set_tx_info, 13086 .get_rx_hwts = hclge_ptp_get_rx_hwts, 13087 .get_ts_info = hclge_ptp_get_ts_info, 13088 .get_link_diagnosis_info = hclge_get_link_diagnosis_info, 13089 .clean_vf_config = hclge_clean_vport_config, 13090 .get_dscp_prio = hclge_get_dscp_prio, 13091 }; 13092 13093 static struct hnae3_ae_algo ae_algo = { 13094 .ops = &hclge_ops, 13095 .pdev_id_table = ae_algo_pci_tbl, 13096 }; 13097 13098 static int hclge_init(void) 13099 { 13100 pr_info("%s is initializing\n", HCLGE_NAME); 13101 13102 hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, HCLGE_NAME); 13103 if (!hclge_wq) { 13104 pr_err("%s: failed to create workqueue\n", HCLGE_NAME); 13105 return -ENOMEM; 13106 } 13107 13108 hnae3_register_ae_algo(&ae_algo); 13109 13110 return 0; 13111 } 13112 13113 static void hclge_exit(void) 13114 { 13115 hnae3_unregister_ae_algo_prepare(&ae_algo); 13116 hnae3_unregister_ae_algo(&ae_algo); 13117 destroy_workqueue(hclge_wq); 13118 } 13119 module_init(hclge_init); 13120 module_exit(hclge_exit); 13121 13122 MODULE_LICENSE("GPL"); 13123 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 13124 MODULE_DESCRIPTION("HCLGE Driver"); 13125 MODULE_VERSION(HCLGE_MOD_VERSION); 13126