1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3 4 #ifndef __HCLGE_ERR_H 5 #define __HCLGE_ERR_H 6 7 #include "hclge_main.h" 8 9 #define HCLGE_RAS_PF_OTHER_INT_STS_REG 0x20B00 10 #define HCLGE_RAS_REG_FE_MASK 0xFF 11 #define HCLGE_RAS_REG_NFE_MASK 0xFF00 12 #define HCLGE_RAS_REG_NFE_SHIFT 8 13 14 #define HCLGE_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000 15 #define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000 16 #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN 0x300 17 #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x300 18 #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF 19 #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF 20 #define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN 0xFFFF0000 21 #define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK 0xFFFF0000 22 #define HCLGE_IMP_RD_POISON_ERR_INT_EN 0x0100 23 #define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100 24 #define HCLGE_TQP_ECC_ERR_INT_EN 0x0FFF 25 #define HCLGE_TQP_ECC_ERR_INT_EN_MASK 0x0FFF 26 #define HCLGE_IGU_ERR_INT_EN 0x0000066F 27 #define HCLGE_IGU_ERR_INT_EN_MASK 0x000F 28 #define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF 29 #define HCLGE_IGU_TNL_ERR_INT_EN_MASK 0x003F 30 #define HCLGE_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF 31 #define HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF 32 #define HCLGE_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF 33 #define HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF 34 #define HCLGE_PPP_PF_ERR_INT_EN 0x0003 35 #define HCLGE_PPP_PF_ERR_INT_EN_MASK 0x0003 36 #define HCLGE_PPP_MPF_ECC_ERR_INT2_EN 0x003F 37 #define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F 38 #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN 0x003F 39 #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F 40 #define HCLGE_TM_SCH_ECC_ERR_INT_EN 0x3 41 #define HCLGE_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF 42 #define HCLGE_NCSI_ERR_INT_EN 0x3 43 #define HCLGE_NCSI_ERR_INT_TYPE 0x9 44 45 #define HCLGE_IMP_TCM_ECC_INT_MASK 0xFFFF 46 #define HCLGE_IMP_ITCM4_ECC_INT_MASK 0x3 47 #define HCLGE_CMDQ_ECC_INT_MASK 0xFFFF 48 #define HCLGE_CMDQ_ROC_ECC_INT_SHIFT 16 49 #define HCLGE_TQP_ECC_INT_MASK 0xFFF 50 #define HCLGE_TQP_ECC_INT_SHIFT 16 51 #define HCLGE_IMP_TCM_ECC_CLR_MASK 0xFFFF 52 #define HCLGE_IMP_ITCM4_ECC_CLR_MASK 0x3 53 #define HCLGE_CMDQ_NIC_ECC_CLR_MASK 0xFFFF 54 #define HCLGE_CMDQ_ROCEE_ECC_CLR_MASK 0xFFFF0000 55 #define HCLGE_TQP_IMP_ERR_CLR_MASK 0x0FFF0001 56 #define HCLGE_IGU_COM_INT_MASK 0xF 57 #define HCLGE_IGU_EGU_TNL_INT_MASK 0x3F 58 #define HCLGE_PPP_PF_INT_MASK 0x100 59 60 enum hclge_err_int_type { 61 HCLGE_ERR_INT_MSIX = 0, 62 HCLGE_ERR_INT_RAS_CE = 1, 63 HCLGE_ERR_INT_RAS_NFE = 2, 64 HCLGE_ERR_INT_RAS_FE = 3, 65 }; 66 67 struct hclge_hw_blk { 68 u32 msk; 69 const char *name; 70 int (*enable_error)(struct hclge_dev *hdev, bool en); 71 void (*process_error)(struct hclge_dev *hdev, 72 enum hclge_err_int_type type); 73 }; 74 75 struct hclge_hw_error { 76 u32 int_msk; 77 const char *msg; 78 }; 79 80 int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state); 81 int hclge_enable_tm_hw_error(struct hclge_dev *hdev, bool en); 82 pci_ers_result_t hclge_process_ras_hw_error(struct hnae3_ae_dev *ae_dev); 83 #endif 84