1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (c) 2016-2017 Hisilicon Limited. */ 3 4 #include "hclge_err.h" 5 6 static const struct hclge_hw_error hclge_imp_tcm_ecc_int[] = { 7 { .int_msk = BIT(1), .msg = "imp_itcm0_ecc_mbit_err", 8 .reset_level = HNAE3_NONE_RESET }, 9 { .int_msk = BIT(3), .msg = "imp_itcm1_ecc_mbit_err", 10 .reset_level = HNAE3_NONE_RESET }, 11 { .int_msk = BIT(5), .msg = "imp_itcm2_ecc_mbit_err", 12 .reset_level = HNAE3_NONE_RESET }, 13 { .int_msk = BIT(7), .msg = "imp_itcm3_ecc_mbit_err", 14 .reset_level = HNAE3_NONE_RESET }, 15 { .int_msk = BIT(9), .msg = "imp_dtcm0_mem0_ecc_mbit_err", 16 .reset_level = HNAE3_NONE_RESET }, 17 { .int_msk = BIT(11), .msg = "imp_dtcm0_mem1_ecc_mbit_err", 18 .reset_level = HNAE3_NONE_RESET }, 19 { .int_msk = BIT(13), .msg = "imp_dtcm1_mem0_ecc_mbit_err", 20 .reset_level = HNAE3_NONE_RESET }, 21 { .int_msk = BIT(15), .msg = "imp_dtcm1_mem1_ecc_mbit_err", 22 .reset_level = HNAE3_NONE_RESET }, 23 { .int_msk = BIT(17), .msg = "imp_itcm4_ecc_mbit_err", 24 .reset_level = HNAE3_NONE_RESET }, 25 { /* sentinel */ } 26 }; 27 28 static const struct hclge_hw_error hclge_cmdq_nic_mem_ecc_int[] = { 29 { .int_msk = BIT(1), .msg = "cmdq_nic_rx_depth_ecc_mbit_err", 30 .reset_level = HNAE3_NONE_RESET }, 31 { .int_msk = BIT(3), .msg = "cmdq_nic_tx_depth_ecc_mbit_err", 32 .reset_level = HNAE3_NONE_RESET }, 33 { .int_msk = BIT(5), .msg = "cmdq_nic_rx_tail_ecc_mbit_err", 34 .reset_level = HNAE3_NONE_RESET }, 35 { .int_msk = BIT(7), .msg = "cmdq_nic_tx_tail_ecc_mbit_err", 36 .reset_level = HNAE3_NONE_RESET }, 37 { .int_msk = BIT(9), .msg = "cmdq_nic_rx_head_ecc_mbit_err", 38 .reset_level = HNAE3_NONE_RESET }, 39 { .int_msk = BIT(11), .msg = "cmdq_nic_tx_head_ecc_mbit_err", 40 .reset_level = HNAE3_NONE_RESET }, 41 { .int_msk = BIT(13), .msg = "cmdq_nic_rx_addr_ecc_mbit_err", 42 .reset_level = HNAE3_NONE_RESET }, 43 { .int_msk = BIT(15), .msg = "cmdq_nic_tx_addr_ecc_mbit_err", 44 .reset_level = HNAE3_NONE_RESET }, 45 { .int_msk = BIT(17), .msg = "cmdq_rocee_rx_depth_ecc_mbit_err", 46 .reset_level = HNAE3_NONE_RESET }, 47 { .int_msk = BIT(19), .msg = "cmdq_rocee_tx_depth_ecc_mbit_err", 48 .reset_level = HNAE3_NONE_RESET }, 49 { .int_msk = BIT(21), .msg = "cmdq_rocee_rx_tail_ecc_mbit_err", 50 .reset_level = HNAE3_NONE_RESET }, 51 { .int_msk = BIT(23), .msg = "cmdq_rocee_tx_tail_ecc_mbit_err", 52 .reset_level = HNAE3_NONE_RESET }, 53 { .int_msk = BIT(25), .msg = "cmdq_rocee_rx_head_ecc_mbit_err", 54 .reset_level = HNAE3_NONE_RESET }, 55 { .int_msk = BIT(27), .msg = "cmdq_rocee_tx_head_ecc_mbit_err", 56 .reset_level = HNAE3_NONE_RESET }, 57 { .int_msk = BIT(29), .msg = "cmdq_rocee_rx_addr_ecc_mbit_err", 58 .reset_level = HNAE3_NONE_RESET }, 59 { .int_msk = BIT(31), .msg = "cmdq_rocee_tx_addr_ecc_mbit_err", 60 .reset_level = HNAE3_NONE_RESET }, 61 { /* sentinel */ } 62 }; 63 64 static const struct hclge_hw_error hclge_tqp_int_ecc_int[] = { 65 { .int_msk = BIT(6), .msg = "tqp_int_cfg_even_ecc_mbit_err", 66 .reset_level = HNAE3_NONE_RESET }, 67 { .int_msk = BIT(7), .msg = "tqp_int_cfg_odd_ecc_mbit_err", 68 .reset_level = HNAE3_NONE_RESET }, 69 { .int_msk = BIT(8), .msg = "tqp_int_ctrl_even_ecc_mbit_err", 70 .reset_level = HNAE3_NONE_RESET }, 71 { .int_msk = BIT(9), .msg = "tqp_int_ctrl_odd_ecc_mbit_err", 72 .reset_level = HNAE3_NONE_RESET }, 73 { .int_msk = BIT(10), .msg = "tx_que_scan_int_ecc_mbit_err", 74 .reset_level = HNAE3_NONE_RESET }, 75 { .int_msk = BIT(11), .msg = "rx_que_scan_int_ecc_mbit_err", 76 .reset_level = HNAE3_NONE_RESET }, 77 { /* sentinel */ } 78 }; 79 80 static const struct hclge_hw_error hclge_msix_sram_ecc_int[] = { 81 { .int_msk = BIT(1), .msg = "msix_nic_ecc_mbit_err", 82 .reset_level = HNAE3_NONE_RESET }, 83 { .int_msk = BIT(3), .msg = "msix_rocee_ecc_mbit_err", 84 .reset_level = HNAE3_NONE_RESET }, 85 { /* sentinel */ } 86 }; 87 88 static const struct hclge_hw_error hclge_igu_int[] = { 89 { .int_msk = BIT(0), .msg = "igu_rx_buf0_ecc_mbit_err", 90 .reset_level = HNAE3_GLOBAL_RESET }, 91 { .int_msk = BIT(2), .msg = "igu_rx_buf1_ecc_mbit_err", 92 .reset_level = HNAE3_GLOBAL_RESET }, 93 { /* sentinel */ } 94 }; 95 96 static const struct hclge_hw_error hclge_igu_egu_tnl_int[] = { 97 { .int_msk = BIT(0), .msg = "rx_buf_overflow", 98 .reset_level = HNAE3_GLOBAL_RESET }, 99 { .int_msk = BIT(1), .msg = "rx_stp_fifo_overflow", 100 .reset_level = HNAE3_GLOBAL_RESET }, 101 { .int_msk = BIT(2), .msg = "rx_stp_fifo_undeflow", 102 .reset_level = HNAE3_GLOBAL_RESET }, 103 { .int_msk = BIT(3), .msg = "tx_buf_overflow", 104 .reset_level = HNAE3_GLOBAL_RESET }, 105 { .int_msk = BIT(4), .msg = "tx_buf_underrun", 106 .reset_level = HNAE3_GLOBAL_RESET }, 107 { .int_msk = BIT(5), .msg = "rx_stp_buf_overflow", 108 .reset_level = HNAE3_GLOBAL_RESET }, 109 { /* sentinel */ } 110 }; 111 112 static const struct hclge_hw_error hclge_ncsi_err_int[] = { 113 { .int_msk = BIT(1), .msg = "ncsi_tx_ecc_mbit_err", 114 .reset_level = HNAE3_NONE_RESET }, 115 { /* sentinel */ } 116 }; 117 118 static const struct hclge_hw_error hclge_ppp_mpf_abnormal_int_st1[] = { 119 { .int_msk = BIT(0), .msg = "vf_vlan_ad_mem_ecc_mbit_err", 120 .reset_level = HNAE3_GLOBAL_RESET }, 121 { .int_msk = BIT(1), .msg = "umv_mcast_group_mem_ecc_mbit_err", 122 .reset_level = HNAE3_GLOBAL_RESET }, 123 { .int_msk = BIT(2), .msg = "umv_key_mem0_ecc_mbit_err", 124 .reset_level = HNAE3_GLOBAL_RESET }, 125 { .int_msk = BIT(3), .msg = "umv_key_mem1_ecc_mbit_err", 126 .reset_level = HNAE3_GLOBAL_RESET }, 127 { .int_msk = BIT(4), .msg = "umv_key_mem2_ecc_mbit_err", 128 .reset_level = HNAE3_GLOBAL_RESET }, 129 { .int_msk = BIT(5), .msg = "umv_key_mem3_ecc_mbit_err", 130 .reset_level = HNAE3_GLOBAL_RESET }, 131 { .int_msk = BIT(6), .msg = "umv_ad_mem_ecc_mbit_err", 132 .reset_level = HNAE3_GLOBAL_RESET }, 133 { .int_msk = BIT(7), .msg = "rss_tc_mode_mem_ecc_mbit_err", 134 .reset_level = HNAE3_GLOBAL_RESET }, 135 { .int_msk = BIT(8), .msg = "rss_idt_mem0_ecc_mbit_err", 136 .reset_level = HNAE3_GLOBAL_RESET }, 137 { .int_msk = BIT(9), .msg = "rss_idt_mem1_ecc_mbit_err", 138 .reset_level = HNAE3_GLOBAL_RESET }, 139 { .int_msk = BIT(10), .msg = "rss_idt_mem2_ecc_mbit_err", 140 .reset_level = HNAE3_GLOBAL_RESET }, 141 { .int_msk = BIT(11), .msg = "rss_idt_mem3_ecc_mbit_err", 142 .reset_level = HNAE3_GLOBAL_RESET }, 143 { .int_msk = BIT(12), .msg = "rss_idt_mem4_ecc_mbit_err", 144 .reset_level = HNAE3_GLOBAL_RESET }, 145 { .int_msk = BIT(13), .msg = "rss_idt_mem5_ecc_mbit_err", 146 .reset_level = HNAE3_GLOBAL_RESET }, 147 { .int_msk = BIT(14), .msg = "rss_idt_mem6_ecc_mbit_err", 148 .reset_level = HNAE3_GLOBAL_RESET }, 149 { .int_msk = BIT(15), .msg = "rss_idt_mem7_ecc_mbit_err", 150 .reset_level = HNAE3_GLOBAL_RESET }, 151 { .int_msk = BIT(16), .msg = "rss_idt_mem8_ecc_mbit_err", 152 .reset_level = HNAE3_GLOBAL_RESET }, 153 { .int_msk = BIT(17), .msg = "rss_idt_mem9_ecc_mbit_err", 154 .reset_level = HNAE3_GLOBAL_RESET }, 155 { .int_msk = BIT(18), .msg = "rss_idt_mem10_ecc_m1bit_err", 156 .reset_level = HNAE3_GLOBAL_RESET }, 157 { .int_msk = BIT(19), .msg = "rss_idt_mem11_ecc_mbit_err", 158 .reset_level = HNAE3_GLOBAL_RESET }, 159 { .int_msk = BIT(20), .msg = "rss_idt_mem12_ecc_mbit_err", 160 .reset_level = HNAE3_GLOBAL_RESET }, 161 { .int_msk = BIT(21), .msg = "rss_idt_mem13_ecc_mbit_err", 162 .reset_level = HNAE3_GLOBAL_RESET }, 163 { .int_msk = BIT(22), .msg = "rss_idt_mem14_ecc_mbit_err", 164 .reset_level = HNAE3_GLOBAL_RESET }, 165 { .int_msk = BIT(23), .msg = "rss_idt_mem15_ecc_mbit_err", 166 .reset_level = HNAE3_GLOBAL_RESET }, 167 { .int_msk = BIT(24), .msg = "port_vlan_mem_ecc_mbit_err", 168 .reset_level = HNAE3_GLOBAL_RESET }, 169 { .int_msk = BIT(25), .msg = "mcast_linear_table_mem_ecc_mbit_err", 170 .reset_level = HNAE3_GLOBAL_RESET }, 171 { .int_msk = BIT(26), .msg = "mcast_result_mem_ecc_mbit_err", 172 .reset_level = HNAE3_GLOBAL_RESET }, 173 { .int_msk = BIT(27), .msg = "flow_director_ad_mem0_ecc_mbit_err", 174 .reset_level = HNAE3_GLOBAL_RESET }, 175 { .int_msk = BIT(28), .msg = "flow_director_ad_mem1_ecc_mbit_err", 176 .reset_level = HNAE3_GLOBAL_RESET }, 177 { .int_msk = BIT(29), .msg = "rx_vlan_tag_memory_ecc_mbit_err", 178 .reset_level = HNAE3_GLOBAL_RESET }, 179 { .int_msk = BIT(30), .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err", 180 .reset_level = HNAE3_GLOBAL_RESET }, 181 { /* sentinel */ } 182 }; 183 184 static const struct hclge_hw_error hclge_ppp_pf_abnormal_int[] = { 185 { .int_msk = BIT(0), .msg = "tx_vlan_tag_err", 186 .reset_level = HNAE3_NONE_RESET }, 187 { .int_msk = BIT(1), .msg = "rss_list_tc_unassigned_queue_err", 188 .reset_level = HNAE3_NONE_RESET }, 189 { /* sentinel */ } 190 }; 191 192 static const struct hclge_hw_error hclge_ppp_mpf_abnormal_int_st3[] = { 193 { .int_msk = BIT(0), .msg = "hfs_fifo_mem_ecc_mbit_err", 194 .reset_level = HNAE3_GLOBAL_RESET }, 195 { .int_msk = BIT(1), .msg = "rslt_descr_fifo_mem_ecc_mbit_err", 196 .reset_level = HNAE3_GLOBAL_RESET }, 197 { .int_msk = BIT(2), .msg = "tx_vlan_tag_mem_ecc_mbit_err", 198 .reset_level = HNAE3_GLOBAL_RESET }, 199 { .int_msk = BIT(3), .msg = "FD_CN0_memory_ecc_mbit_err", 200 .reset_level = HNAE3_GLOBAL_RESET }, 201 { .int_msk = BIT(4), .msg = "FD_CN1_memory_ecc_mbit_err", 202 .reset_level = HNAE3_GLOBAL_RESET }, 203 { .int_msk = BIT(5), .msg = "GRO_AD_memory_ecc_mbit_err", 204 .reset_level = HNAE3_GLOBAL_RESET }, 205 { /* sentinel */ } 206 }; 207 208 static const struct hclge_hw_error hclge_tm_sch_rint[] = { 209 { .int_msk = BIT(1), .msg = "tm_sch_ecc_mbit_err", 210 .reset_level = HNAE3_GLOBAL_RESET }, 211 { .int_msk = BIT(2), .msg = "tm_sch_port_shap_sub_fifo_wr_err", 212 .reset_level = HNAE3_GLOBAL_RESET }, 213 { .int_msk = BIT(3), .msg = "tm_sch_port_shap_sub_fifo_rd_err", 214 .reset_level = HNAE3_GLOBAL_RESET }, 215 { .int_msk = BIT(4), .msg = "tm_sch_pg_pshap_sub_fifo_wr_err", 216 .reset_level = HNAE3_GLOBAL_RESET }, 217 { .int_msk = BIT(5), .msg = "tm_sch_pg_pshap_sub_fifo_rd_err", 218 .reset_level = HNAE3_GLOBAL_RESET }, 219 { .int_msk = BIT(6), .msg = "tm_sch_pg_cshap_sub_fifo_wr_err", 220 .reset_level = HNAE3_GLOBAL_RESET }, 221 { .int_msk = BIT(7), .msg = "tm_sch_pg_cshap_sub_fifo_rd_err", 222 .reset_level = HNAE3_GLOBAL_RESET }, 223 { .int_msk = BIT(8), .msg = "tm_sch_pri_pshap_sub_fifo_wr_err", 224 .reset_level = HNAE3_GLOBAL_RESET }, 225 { .int_msk = BIT(9), .msg = "tm_sch_pri_pshap_sub_fifo_rd_err", 226 .reset_level = HNAE3_GLOBAL_RESET }, 227 { .int_msk = BIT(10), .msg = "tm_sch_pri_cshap_sub_fifo_wr_err", 228 .reset_level = HNAE3_GLOBAL_RESET }, 229 { .int_msk = BIT(11), .msg = "tm_sch_pri_cshap_sub_fifo_rd_err", 230 .reset_level = HNAE3_GLOBAL_RESET }, 231 { .int_msk = BIT(12), .msg = "tm_sch_port_shap_offset_fifo_wr_err", 232 .reset_level = HNAE3_GLOBAL_RESET }, 233 { .int_msk = BIT(13), .msg = "tm_sch_port_shap_offset_fifo_rd_err", 234 .reset_level = HNAE3_GLOBAL_RESET }, 235 { .int_msk = BIT(14), .msg = "tm_sch_pg_pshap_offset_fifo_wr_err", 236 .reset_level = HNAE3_GLOBAL_RESET }, 237 { .int_msk = BIT(15), .msg = "tm_sch_pg_pshap_offset_fifo_rd_err", 238 .reset_level = HNAE3_GLOBAL_RESET }, 239 { .int_msk = BIT(16), .msg = "tm_sch_pg_cshap_offset_fifo_wr_err", 240 .reset_level = HNAE3_GLOBAL_RESET }, 241 { .int_msk = BIT(17), .msg = "tm_sch_pg_cshap_offset_fifo_rd_err", 242 .reset_level = HNAE3_GLOBAL_RESET }, 243 { .int_msk = BIT(18), .msg = "tm_sch_pri_pshap_offset_fifo_wr_err", 244 .reset_level = HNAE3_GLOBAL_RESET }, 245 { .int_msk = BIT(19), .msg = "tm_sch_pri_pshap_offset_fifo_rd_err", 246 .reset_level = HNAE3_GLOBAL_RESET }, 247 { .int_msk = BIT(20), .msg = "tm_sch_pri_cshap_offset_fifo_wr_err", 248 .reset_level = HNAE3_GLOBAL_RESET }, 249 { .int_msk = BIT(21), .msg = "tm_sch_pri_cshap_offset_fifo_rd_err", 250 .reset_level = HNAE3_GLOBAL_RESET }, 251 { .int_msk = BIT(22), .msg = "tm_sch_rq_fifo_wr_err", 252 .reset_level = HNAE3_GLOBAL_RESET }, 253 { .int_msk = BIT(23), .msg = "tm_sch_rq_fifo_rd_err", 254 .reset_level = HNAE3_GLOBAL_RESET }, 255 { .int_msk = BIT(24), .msg = "tm_sch_nq_fifo_wr_err", 256 .reset_level = HNAE3_GLOBAL_RESET }, 257 { .int_msk = BIT(25), .msg = "tm_sch_nq_fifo_rd_err", 258 .reset_level = HNAE3_GLOBAL_RESET }, 259 { .int_msk = BIT(26), .msg = "tm_sch_roce_up_fifo_wr_err", 260 .reset_level = HNAE3_GLOBAL_RESET }, 261 { .int_msk = BIT(27), .msg = "tm_sch_roce_up_fifo_rd_err", 262 .reset_level = HNAE3_GLOBAL_RESET }, 263 { .int_msk = BIT(28), .msg = "tm_sch_rcb_byte_fifo_wr_err", 264 .reset_level = HNAE3_GLOBAL_RESET }, 265 { .int_msk = BIT(29), .msg = "tm_sch_rcb_byte_fifo_rd_err", 266 .reset_level = HNAE3_GLOBAL_RESET }, 267 { .int_msk = BIT(30), .msg = "tm_sch_ssu_byte_fifo_wr_err", 268 .reset_level = HNAE3_GLOBAL_RESET }, 269 { .int_msk = BIT(31), .msg = "tm_sch_ssu_byte_fifo_rd_err", 270 .reset_level = HNAE3_GLOBAL_RESET }, 271 { /* sentinel */ } 272 }; 273 274 static const struct hclge_hw_error hclge_qcn_fifo_rint[] = { 275 { .int_msk = BIT(0), .msg = "qcn_shap_gp0_sch_fifo_rd_err", 276 .reset_level = HNAE3_GLOBAL_RESET }, 277 { .int_msk = BIT(1), .msg = "qcn_shap_gp0_sch_fifo_wr_err", 278 .reset_level = HNAE3_GLOBAL_RESET }, 279 { .int_msk = BIT(2), .msg = "qcn_shap_gp1_sch_fifo_rd_err", 280 .reset_level = HNAE3_GLOBAL_RESET }, 281 { .int_msk = BIT(3), .msg = "qcn_shap_gp1_sch_fifo_wr_err", 282 .reset_level = HNAE3_GLOBAL_RESET }, 283 { .int_msk = BIT(4), .msg = "qcn_shap_gp2_sch_fifo_rd_err", 284 .reset_level = HNAE3_GLOBAL_RESET }, 285 { .int_msk = BIT(5), .msg = "qcn_shap_gp2_sch_fifo_wr_err", 286 .reset_level = HNAE3_GLOBAL_RESET }, 287 { .int_msk = BIT(6), .msg = "qcn_shap_gp3_sch_fifo_rd_err", 288 .reset_level = HNAE3_GLOBAL_RESET }, 289 { .int_msk = BIT(7), .msg = "qcn_shap_gp3_sch_fifo_wr_err", 290 .reset_level = HNAE3_GLOBAL_RESET }, 291 { .int_msk = BIT(8), .msg = "qcn_shap_gp0_offset_fifo_rd_err", 292 .reset_level = HNAE3_GLOBAL_RESET }, 293 { .int_msk = BIT(9), .msg = "qcn_shap_gp0_offset_fifo_wr_err", 294 .reset_level = HNAE3_GLOBAL_RESET }, 295 { .int_msk = BIT(10), .msg = "qcn_shap_gp1_offset_fifo_rd_err", 296 .reset_level = HNAE3_GLOBAL_RESET }, 297 { .int_msk = BIT(11), .msg = "qcn_shap_gp1_offset_fifo_wr_err", 298 .reset_level = HNAE3_GLOBAL_RESET }, 299 { .int_msk = BIT(12), .msg = "qcn_shap_gp2_offset_fifo_rd_err", 300 .reset_level = HNAE3_GLOBAL_RESET }, 301 { .int_msk = BIT(13), .msg = "qcn_shap_gp2_offset_fifo_wr_err", 302 .reset_level = HNAE3_GLOBAL_RESET }, 303 { .int_msk = BIT(14), .msg = "qcn_shap_gp3_offset_fifo_rd_err", 304 .reset_level = HNAE3_GLOBAL_RESET }, 305 { .int_msk = BIT(15), .msg = "qcn_shap_gp3_offset_fifo_wr_err", 306 .reset_level = HNAE3_GLOBAL_RESET }, 307 { .int_msk = BIT(16), .msg = "qcn_byte_info_fifo_rd_err", 308 .reset_level = HNAE3_GLOBAL_RESET }, 309 { .int_msk = BIT(17), .msg = "qcn_byte_info_fifo_wr_err", 310 .reset_level = HNAE3_GLOBAL_RESET }, 311 { /* sentinel */ } 312 }; 313 314 static const struct hclge_hw_error hclge_qcn_ecc_rint[] = { 315 { .int_msk = BIT(1), .msg = "qcn_byte_mem_ecc_mbit_err", 316 .reset_level = HNAE3_GLOBAL_RESET }, 317 { .int_msk = BIT(3), .msg = "qcn_time_mem_ecc_mbit_err", 318 .reset_level = HNAE3_GLOBAL_RESET }, 319 { .int_msk = BIT(5), .msg = "qcn_fb_mem_ecc_mbit_err", 320 .reset_level = HNAE3_GLOBAL_RESET }, 321 { .int_msk = BIT(7), .msg = "qcn_link_mem_ecc_mbit_err", 322 .reset_level = HNAE3_GLOBAL_RESET }, 323 { .int_msk = BIT(9), .msg = "qcn_rate_mem_ecc_mbit_err", 324 .reset_level = HNAE3_GLOBAL_RESET }, 325 { .int_msk = BIT(11), .msg = "qcn_tmplt_mem_ecc_mbit_err", 326 .reset_level = HNAE3_GLOBAL_RESET }, 327 { .int_msk = BIT(13), .msg = "qcn_shap_cfg_mem_ecc_mbit_err", 328 .reset_level = HNAE3_GLOBAL_RESET }, 329 { .int_msk = BIT(15), .msg = "qcn_gp0_barrel_mem_ecc_mbit_err", 330 .reset_level = HNAE3_GLOBAL_RESET }, 331 { .int_msk = BIT(17), .msg = "qcn_gp1_barrel_mem_ecc_mbit_err", 332 .reset_level = HNAE3_GLOBAL_RESET }, 333 { .int_msk = BIT(19), .msg = "qcn_gp2_barrel_mem_ecc_mbit_err", 334 .reset_level = HNAE3_GLOBAL_RESET }, 335 { .int_msk = BIT(21), .msg = "qcn_gp3_barral_mem_ecc_mbit_err", 336 .reset_level = HNAE3_GLOBAL_RESET }, 337 { /* sentinel */ } 338 }; 339 340 static const struct hclge_hw_error hclge_mac_afifo_tnl_int[] = { 341 { .int_msk = BIT(0), .msg = "egu_cge_afifo_ecc_1bit_err", 342 .reset_level = HNAE3_NONE_RESET }, 343 { .int_msk = BIT(1), .msg = "egu_cge_afifo_ecc_mbit_err", 344 .reset_level = HNAE3_GLOBAL_RESET }, 345 { .int_msk = BIT(2), .msg = "egu_lge_afifo_ecc_1bit_err", 346 .reset_level = HNAE3_NONE_RESET }, 347 { .int_msk = BIT(3), .msg = "egu_lge_afifo_ecc_mbit_err", 348 .reset_level = HNAE3_GLOBAL_RESET }, 349 { .int_msk = BIT(4), .msg = "cge_igu_afifo_ecc_1bit_err", 350 .reset_level = HNAE3_NONE_RESET }, 351 { .int_msk = BIT(5), .msg = "cge_igu_afifo_ecc_mbit_err", 352 .reset_level = HNAE3_GLOBAL_RESET }, 353 { .int_msk = BIT(6), .msg = "lge_igu_afifo_ecc_1bit_err", 354 .reset_level = HNAE3_NONE_RESET }, 355 { .int_msk = BIT(7), .msg = "lge_igu_afifo_ecc_mbit_err", 356 .reset_level = HNAE3_GLOBAL_RESET }, 357 { .int_msk = BIT(8), .msg = "cge_igu_afifo_overflow_err", 358 .reset_level = HNAE3_GLOBAL_RESET }, 359 { .int_msk = BIT(9), .msg = "lge_igu_afifo_overflow_err", 360 .reset_level = HNAE3_GLOBAL_RESET }, 361 { .int_msk = BIT(10), .msg = "egu_cge_afifo_underrun_err", 362 .reset_level = HNAE3_GLOBAL_RESET }, 363 { .int_msk = BIT(11), .msg = "egu_lge_afifo_underrun_err", 364 .reset_level = HNAE3_GLOBAL_RESET }, 365 { .int_msk = BIT(12), .msg = "egu_ge_afifo_underrun_err", 366 .reset_level = HNAE3_GLOBAL_RESET }, 367 { .int_msk = BIT(13), .msg = "ge_igu_afifo_overflow_err", 368 .reset_level = HNAE3_GLOBAL_RESET }, 369 { /* sentinel */ } 370 }; 371 372 static const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st2[] = { 373 { .int_msk = BIT(13), .msg = "rpu_rx_pkt_bit32_ecc_mbit_err", 374 .reset_level = HNAE3_GLOBAL_RESET }, 375 { .int_msk = BIT(14), .msg = "rpu_rx_pkt_bit33_ecc_mbit_err", 376 .reset_level = HNAE3_GLOBAL_RESET }, 377 { .int_msk = BIT(15), .msg = "rpu_rx_pkt_bit34_ecc_mbit_err", 378 .reset_level = HNAE3_GLOBAL_RESET }, 379 { .int_msk = BIT(16), .msg = "rpu_rx_pkt_bit35_ecc_mbit_err", 380 .reset_level = HNAE3_GLOBAL_RESET }, 381 { .int_msk = BIT(17), .msg = "rcb_tx_ring_ecc_mbit_err", 382 .reset_level = HNAE3_GLOBAL_RESET }, 383 { .int_msk = BIT(18), .msg = "rcb_rx_ring_ecc_mbit_err", 384 .reset_level = HNAE3_GLOBAL_RESET }, 385 { .int_msk = BIT(19), .msg = "rcb_tx_fbd_ecc_mbit_err", 386 .reset_level = HNAE3_GLOBAL_RESET }, 387 { .int_msk = BIT(20), .msg = "rcb_rx_ebd_ecc_mbit_err", 388 .reset_level = HNAE3_GLOBAL_RESET }, 389 { .int_msk = BIT(21), .msg = "rcb_tso_info_ecc_mbit_err", 390 .reset_level = HNAE3_GLOBAL_RESET }, 391 { .int_msk = BIT(22), .msg = "rcb_tx_int_info_ecc_mbit_err", 392 .reset_level = HNAE3_GLOBAL_RESET }, 393 { .int_msk = BIT(23), .msg = "rcb_rx_int_info_ecc_mbit_err", 394 .reset_level = HNAE3_GLOBAL_RESET }, 395 { .int_msk = BIT(24), .msg = "tpu_tx_pkt_0_ecc_mbit_err", 396 .reset_level = HNAE3_GLOBAL_RESET }, 397 { .int_msk = BIT(25), .msg = "tpu_tx_pkt_1_ecc_mbit_err", 398 .reset_level = HNAE3_GLOBAL_RESET }, 399 { .int_msk = BIT(26), .msg = "rd_bus_err", 400 .reset_level = HNAE3_GLOBAL_RESET }, 401 { .int_msk = BIT(27), .msg = "wr_bus_err", 402 .reset_level = HNAE3_GLOBAL_RESET }, 403 { .int_msk = BIT(28), .msg = "reg_search_miss", 404 .reset_level = HNAE3_GLOBAL_RESET }, 405 { .int_msk = BIT(29), .msg = "rx_q_search_miss", 406 .reset_level = HNAE3_NONE_RESET }, 407 { .int_msk = BIT(30), .msg = "ooo_ecc_err_detect", 408 .reset_level = HNAE3_NONE_RESET }, 409 { .int_msk = BIT(31), .msg = "ooo_ecc_err_multpl", 410 .reset_level = HNAE3_GLOBAL_RESET }, 411 { /* sentinel */ } 412 }; 413 414 static const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st3[] = { 415 { .int_msk = BIT(4), .msg = "gro_bd_ecc_mbit_err", 416 .reset_level = HNAE3_GLOBAL_RESET }, 417 { .int_msk = BIT(5), .msg = "gro_context_ecc_mbit_err", 418 .reset_level = HNAE3_GLOBAL_RESET }, 419 { .int_msk = BIT(6), .msg = "rx_stash_cfg_ecc_mbit_err", 420 .reset_level = HNAE3_GLOBAL_RESET }, 421 { .int_msk = BIT(7), .msg = "axi_rd_fbd_ecc_mbit_err", 422 .reset_level = HNAE3_GLOBAL_RESET }, 423 { /* sentinel */ } 424 }; 425 426 static const struct hclge_hw_error hclge_ppu_pf_abnormal_int[] = { 427 { .int_msk = BIT(0), .msg = "over_8bd_no_fe", 428 .reset_level = HNAE3_FUNC_RESET }, 429 { .int_msk = BIT(1), .msg = "tso_mss_cmp_min_err", 430 .reset_level = HNAE3_NONE_RESET }, 431 { .int_msk = BIT(2), .msg = "tso_mss_cmp_max_err", 432 .reset_level = HNAE3_NONE_RESET }, 433 { .int_msk = BIT(3), .msg = "tx_rd_fbd_poison", 434 .reset_level = HNAE3_FUNC_RESET }, 435 { .int_msk = BIT(4), .msg = "rx_rd_ebd_poison", 436 .reset_level = HNAE3_FUNC_RESET }, 437 { .int_msk = BIT(5), .msg = "buf_wait_timeout", 438 .reset_level = HNAE3_NONE_RESET }, 439 { /* sentinel */ } 440 }; 441 442 static const struct hclge_hw_error hclge_ssu_com_err_int[] = { 443 { .int_msk = BIT(0), .msg = "buf_sum_err", 444 .reset_level = HNAE3_NONE_RESET }, 445 { .int_msk = BIT(1), .msg = "ppp_mb_num_err", 446 .reset_level = HNAE3_NONE_RESET }, 447 { .int_msk = BIT(2), .msg = "ppp_mbid_err", 448 .reset_level = HNAE3_GLOBAL_RESET }, 449 { .int_msk = BIT(3), .msg = "ppp_rlt_mac_err", 450 .reset_level = HNAE3_GLOBAL_RESET }, 451 { .int_msk = BIT(4), .msg = "ppp_rlt_host_err", 452 .reset_level = HNAE3_GLOBAL_RESET }, 453 { .int_msk = BIT(5), .msg = "cks_edit_position_err", 454 .reset_level = HNAE3_GLOBAL_RESET }, 455 { .int_msk = BIT(6), .msg = "cks_edit_condition_err", 456 .reset_level = HNAE3_GLOBAL_RESET }, 457 { .int_msk = BIT(7), .msg = "vlan_edit_condition_err", 458 .reset_level = HNAE3_GLOBAL_RESET }, 459 { .int_msk = BIT(8), .msg = "vlan_num_ot_err", 460 .reset_level = HNAE3_GLOBAL_RESET }, 461 { .int_msk = BIT(9), .msg = "vlan_num_in_err", 462 .reset_level = HNAE3_GLOBAL_RESET }, 463 { /* sentinel */ } 464 }; 465 466 #define HCLGE_SSU_MEM_ECC_ERR(x) \ 467 { .int_msk = BIT(x), .msg = "ssu_mem" #x "_ecc_mbit_err", \ 468 .reset_level = HNAE3_GLOBAL_RESET } 469 470 static const struct hclge_hw_error hclge_ssu_mem_ecc_err_int[] = { 471 HCLGE_SSU_MEM_ECC_ERR(0), 472 HCLGE_SSU_MEM_ECC_ERR(1), 473 HCLGE_SSU_MEM_ECC_ERR(2), 474 HCLGE_SSU_MEM_ECC_ERR(3), 475 HCLGE_SSU_MEM_ECC_ERR(4), 476 HCLGE_SSU_MEM_ECC_ERR(5), 477 HCLGE_SSU_MEM_ECC_ERR(6), 478 HCLGE_SSU_MEM_ECC_ERR(7), 479 HCLGE_SSU_MEM_ECC_ERR(8), 480 HCLGE_SSU_MEM_ECC_ERR(9), 481 HCLGE_SSU_MEM_ECC_ERR(10), 482 HCLGE_SSU_MEM_ECC_ERR(11), 483 HCLGE_SSU_MEM_ECC_ERR(12), 484 HCLGE_SSU_MEM_ECC_ERR(13), 485 HCLGE_SSU_MEM_ECC_ERR(14), 486 HCLGE_SSU_MEM_ECC_ERR(15), 487 HCLGE_SSU_MEM_ECC_ERR(16), 488 HCLGE_SSU_MEM_ECC_ERR(17), 489 HCLGE_SSU_MEM_ECC_ERR(18), 490 HCLGE_SSU_MEM_ECC_ERR(19), 491 HCLGE_SSU_MEM_ECC_ERR(20), 492 HCLGE_SSU_MEM_ECC_ERR(21), 493 HCLGE_SSU_MEM_ECC_ERR(22), 494 HCLGE_SSU_MEM_ECC_ERR(23), 495 HCLGE_SSU_MEM_ECC_ERR(24), 496 HCLGE_SSU_MEM_ECC_ERR(25), 497 HCLGE_SSU_MEM_ECC_ERR(26), 498 HCLGE_SSU_MEM_ECC_ERR(27), 499 HCLGE_SSU_MEM_ECC_ERR(28), 500 HCLGE_SSU_MEM_ECC_ERR(29), 501 HCLGE_SSU_MEM_ECC_ERR(30), 502 HCLGE_SSU_MEM_ECC_ERR(31), 503 { /* sentinel */ } 504 }; 505 506 static const struct hclge_hw_error hclge_ssu_port_based_err_int[] = { 507 { .int_msk = BIT(0), .msg = "roc_pkt_without_key_port", 508 .reset_level = HNAE3_GLOBAL_RESET }, 509 { .int_msk = BIT(1), .msg = "tpu_pkt_without_key_port", 510 .reset_level = HNAE3_GLOBAL_RESET }, 511 { .int_msk = BIT(2), .msg = "igu_pkt_without_key_port", 512 .reset_level = HNAE3_GLOBAL_RESET }, 513 { .int_msk = BIT(3), .msg = "roc_eof_mis_match_port", 514 .reset_level = HNAE3_GLOBAL_RESET }, 515 { .int_msk = BIT(4), .msg = "tpu_eof_mis_match_port", 516 .reset_level = HNAE3_GLOBAL_RESET }, 517 { .int_msk = BIT(5), .msg = "igu_eof_mis_match_port", 518 .reset_level = HNAE3_GLOBAL_RESET }, 519 { .int_msk = BIT(6), .msg = "roc_sof_mis_match_port", 520 .reset_level = HNAE3_GLOBAL_RESET }, 521 { .int_msk = BIT(7), .msg = "tpu_sof_mis_match_port", 522 .reset_level = HNAE3_GLOBAL_RESET }, 523 { .int_msk = BIT(8), .msg = "igu_sof_mis_match_port", 524 .reset_level = HNAE3_GLOBAL_RESET }, 525 { .int_msk = BIT(11), .msg = "ets_rd_int_rx_port", 526 .reset_level = HNAE3_GLOBAL_RESET }, 527 { .int_msk = BIT(12), .msg = "ets_wr_int_rx_port", 528 .reset_level = HNAE3_GLOBAL_RESET }, 529 { .int_msk = BIT(13), .msg = "ets_rd_int_tx_port", 530 .reset_level = HNAE3_GLOBAL_RESET }, 531 { .int_msk = BIT(14), .msg = "ets_wr_int_tx_port", 532 .reset_level = HNAE3_GLOBAL_RESET }, 533 { /* sentinel */ } 534 }; 535 536 static const struct hclge_hw_error hclge_ssu_fifo_overflow_int[] = { 537 { .int_msk = BIT(0), .msg = "ig_mac_inf_int", 538 .reset_level = HNAE3_GLOBAL_RESET }, 539 { .int_msk = BIT(1), .msg = "ig_host_inf_int", 540 .reset_level = HNAE3_GLOBAL_RESET }, 541 { .int_msk = BIT(2), .msg = "ig_roc_buf_int", 542 .reset_level = HNAE3_GLOBAL_RESET }, 543 { .int_msk = BIT(3), .msg = "ig_host_data_fifo_int", 544 .reset_level = HNAE3_GLOBAL_RESET }, 545 { .int_msk = BIT(4), .msg = "ig_host_key_fifo_int", 546 .reset_level = HNAE3_GLOBAL_RESET }, 547 { .int_msk = BIT(5), .msg = "tx_qcn_fifo_int", 548 .reset_level = HNAE3_GLOBAL_RESET }, 549 { .int_msk = BIT(6), .msg = "rx_qcn_fifo_int", 550 .reset_level = HNAE3_GLOBAL_RESET }, 551 { .int_msk = BIT(7), .msg = "tx_pf_rd_fifo_int", 552 .reset_level = HNAE3_GLOBAL_RESET }, 553 { .int_msk = BIT(8), .msg = "rx_pf_rd_fifo_int", 554 .reset_level = HNAE3_GLOBAL_RESET }, 555 { .int_msk = BIT(9), .msg = "qm_eof_fifo_int", 556 .reset_level = HNAE3_GLOBAL_RESET }, 557 { .int_msk = BIT(10), .msg = "mb_rlt_fifo_int", 558 .reset_level = HNAE3_GLOBAL_RESET }, 559 { .int_msk = BIT(11), .msg = "dup_uncopy_fifo_int", 560 .reset_level = HNAE3_GLOBAL_RESET }, 561 { .int_msk = BIT(12), .msg = "dup_cnt_rd_fifo_int", 562 .reset_level = HNAE3_GLOBAL_RESET }, 563 { .int_msk = BIT(13), .msg = "dup_cnt_drop_fifo_int", 564 .reset_level = HNAE3_GLOBAL_RESET }, 565 { .int_msk = BIT(14), .msg = "dup_cnt_wrb_fifo_int", 566 .reset_level = HNAE3_GLOBAL_RESET }, 567 { .int_msk = BIT(15), .msg = "host_cmd_fifo_int", 568 .reset_level = HNAE3_GLOBAL_RESET }, 569 { .int_msk = BIT(16), .msg = "mac_cmd_fifo_int", 570 .reset_level = HNAE3_GLOBAL_RESET }, 571 { .int_msk = BIT(17), .msg = "host_cmd_bitmap_empty_int", 572 .reset_level = HNAE3_GLOBAL_RESET }, 573 { .int_msk = BIT(18), .msg = "mac_cmd_bitmap_empty_int", 574 .reset_level = HNAE3_GLOBAL_RESET }, 575 { .int_msk = BIT(19), .msg = "dup_bitmap_empty_int", 576 .reset_level = HNAE3_GLOBAL_RESET }, 577 { .int_msk = BIT(20), .msg = "out_queue_bitmap_empty_int", 578 .reset_level = HNAE3_GLOBAL_RESET }, 579 { .int_msk = BIT(21), .msg = "bank2_bitmap_empty_int", 580 .reset_level = HNAE3_GLOBAL_RESET }, 581 { .int_msk = BIT(22), .msg = "bank1_bitmap_empty_int", 582 .reset_level = HNAE3_GLOBAL_RESET }, 583 { .int_msk = BIT(23), .msg = "bank0_bitmap_empty_int", 584 .reset_level = HNAE3_GLOBAL_RESET }, 585 { /* sentinel */ } 586 }; 587 588 static const struct hclge_hw_error hclge_ssu_ets_tcg_int[] = { 589 { .int_msk = BIT(0), .msg = "ets_rd_int_rx_tcg", 590 .reset_level = HNAE3_GLOBAL_RESET }, 591 { .int_msk = BIT(1), .msg = "ets_wr_int_rx_tcg", 592 .reset_level = HNAE3_GLOBAL_RESET }, 593 { .int_msk = BIT(2), .msg = "ets_rd_int_tx_tcg", 594 .reset_level = HNAE3_GLOBAL_RESET }, 595 { .int_msk = BIT(3), .msg = "ets_wr_int_tx_tcg", 596 .reset_level = HNAE3_GLOBAL_RESET }, 597 { /* sentinel */ } 598 }; 599 600 static const struct hclge_hw_error hclge_ssu_port_based_pf_int[] = { 601 { .int_msk = BIT(0), .msg = "roc_pkt_without_key_port", 602 .reset_level = HNAE3_GLOBAL_RESET }, 603 { .int_msk = BIT(9), .msg = "low_water_line_err_port", 604 .reset_level = HNAE3_NONE_RESET }, 605 { .int_msk = BIT(10), .msg = "hi_water_line_err_port", 606 .reset_level = HNAE3_GLOBAL_RESET }, 607 { /* sentinel */ } 608 }; 609 610 static const struct hclge_hw_error hclge_rocee_qmm_ovf_err_int[] = { 611 { .int_msk = 0, .msg = "rocee qmm ovf: sgid invalid err" }, 612 { .int_msk = 0x4, .msg = "rocee qmm ovf: sgid ovf err" }, 613 { .int_msk = 0x8, .msg = "rocee qmm ovf: smac invalid err" }, 614 { .int_msk = 0xC, .msg = "rocee qmm ovf: smac ovf err" }, 615 { .int_msk = 0x10, .msg = "rocee qmm ovf: cqc invalid err" }, 616 { .int_msk = 0x11, .msg = "rocee qmm ovf: cqc ovf err" }, 617 { .int_msk = 0x12, .msg = "rocee qmm ovf: cqc hopnum err" }, 618 { .int_msk = 0x13, .msg = "rocee qmm ovf: cqc ba0 err" }, 619 { .int_msk = 0x14, .msg = "rocee qmm ovf: srqc invalid err" }, 620 { .int_msk = 0x15, .msg = "rocee qmm ovf: srqc ovf err" }, 621 { .int_msk = 0x16, .msg = "rocee qmm ovf: srqc hopnum err" }, 622 { .int_msk = 0x17, .msg = "rocee qmm ovf: srqc ba0 err" }, 623 { .int_msk = 0x18, .msg = "rocee qmm ovf: mpt invalid err" }, 624 { .int_msk = 0x19, .msg = "rocee qmm ovf: mpt ovf err" }, 625 { .int_msk = 0x1A, .msg = "rocee qmm ovf: mpt hopnum err" }, 626 { .int_msk = 0x1B, .msg = "rocee qmm ovf: mpt ba0 err" }, 627 { .int_msk = 0x1C, .msg = "rocee qmm ovf: qpc invalid err" }, 628 { .int_msk = 0x1D, .msg = "rocee qmm ovf: qpc ovf err" }, 629 { .int_msk = 0x1E, .msg = "rocee qmm ovf: qpc hopnum err" }, 630 { .int_msk = 0x1F, .msg = "rocee qmm ovf: qpc ba0 err" }, 631 { /* sentinel */ } 632 }; 633 634 static void hclge_log_error(struct device *dev, char *reg, 635 const struct hclge_hw_error *err, 636 u32 err_sts, unsigned long *reset_requests) 637 { 638 while (err->msg) { 639 if (err->int_msk & err_sts) { 640 dev_warn(dev, "%s %s found [error status=0x%x]\n", 641 reg, err->msg, err_sts); 642 if (err->reset_level && 643 err->reset_level != HNAE3_NONE_RESET) 644 set_bit(err->reset_level, reset_requests); 645 } 646 err++; 647 } 648 } 649 650 /* hclge_cmd_query_error: read the error information 651 * @hdev: pointer to struct hclge_dev 652 * @desc: descriptor for describing the command 653 * @cmd: command opcode 654 * @flag: flag for extended command structure 655 * @w_num: offset for setting the read interrupt type. 656 * @int_type: select which type of the interrupt for which the error 657 * info will be read(RAS-CE/RAS-NFE/RAS-FE etc). 658 * 659 * This function query the error info from hw register/s using command 660 */ 661 static int hclge_cmd_query_error(struct hclge_dev *hdev, 662 struct hclge_desc *desc, u32 cmd, 663 u16 flag, u8 w_num, 664 enum hclge_err_int_type int_type) 665 { 666 struct device *dev = &hdev->pdev->dev; 667 int desc_num = 1; 668 int ret; 669 670 hclge_cmd_setup_basic_desc(&desc[0], cmd, true); 671 if (flag) { 672 desc[0].flag |= cpu_to_le16(flag); 673 hclge_cmd_setup_basic_desc(&desc[1], cmd, true); 674 desc_num = 2; 675 } 676 if (w_num) 677 desc[0].data[w_num] = cpu_to_le32(int_type); 678 679 ret = hclge_cmd_send(&hdev->hw, &desc[0], desc_num); 680 if (ret) 681 dev_err(dev, "query error cmd failed (%d)\n", ret); 682 683 return ret; 684 } 685 686 static int hclge_clear_mac_tnl_int(struct hclge_dev *hdev) 687 { 688 struct hclge_desc desc; 689 690 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_MAC_TNL_INT, false); 691 desc.data[0] = cpu_to_le32(HCLGE_MAC_TNL_INT_CLR); 692 693 return hclge_cmd_send(&hdev->hw, &desc, 1); 694 } 695 696 static int hclge_config_common_hw_err_int(struct hclge_dev *hdev, bool en) 697 { 698 struct device *dev = &hdev->pdev->dev; 699 struct hclge_desc desc[2]; 700 int ret; 701 702 /* configure common error interrupts */ 703 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_COMMON_ECC_INT_CFG, false); 704 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 705 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_COMMON_ECC_INT_CFG, false); 706 707 if (en) { 708 desc[0].data[0] = cpu_to_le32(HCLGE_IMP_TCM_ECC_ERR_INT_EN); 709 desc[0].data[2] = cpu_to_le32(HCLGE_CMDQ_NIC_ECC_ERR_INT_EN | 710 HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN); 711 desc[0].data[3] = cpu_to_le32(HCLGE_IMP_RD_POISON_ERR_INT_EN); 712 desc[0].data[4] = cpu_to_le32(HCLGE_TQP_ECC_ERR_INT_EN | 713 HCLGE_MSIX_SRAM_ECC_ERR_INT_EN); 714 desc[0].data[5] = cpu_to_le32(HCLGE_IMP_ITCM4_ECC_ERR_INT_EN); 715 } 716 717 desc[1].data[0] = cpu_to_le32(HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK); 718 desc[1].data[2] = cpu_to_le32(HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK | 719 HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK); 720 desc[1].data[3] = cpu_to_le32(HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK); 721 desc[1].data[4] = cpu_to_le32(HCLGE_TQP_ECC_ERR_INT_EN_MASK | 722 HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK); 723 desc[1].data[5] = cpu_to_le32(HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK); 724 725 ret = hclge_cmd_send(&hdev->hw, &desc[0], 2); 726 if (ret) 727 dev_err(dev, 728 "fail(%d) to configure common err interrupts\n", ret); 729 730 return ret; 731 } 732 733 static int hclge_config_ncsi_hw_err_int(struct hclge_dev *hdev, bool en) 734 { 735 struct device *dev = &hdev->pdev->dev; 736 struct hclge_desc desc; 737 int ret; 738 739 if (hdev->pdev->revision < 0x21) 740 return 0; 741 742 /* configure NCSI error interrupts */ 743 hclge_cmd_setup_basic_desc(&desc, HCLGE_NCSI_INT_EN, false); 744 if (en) 745 desc.data[0] = cpu_to_le32(HCLGE_NCSI_ERR_INT_EN); 746 747 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 748 if (ret) 749 dev_err(dev, 750 "fail(%d) to configure NCSI error interrupts\n", ret); 751 752 return ret; 753 } 754 755 static int hclge_config_igu_egu_hw_err_int(struct hclge_dev *hdev, bool en) 756 { 757 struct device *dev = &hdev->pdev->dev; 758 struct hclge_desc desc; 759 int ret; 760 761 /* configure IGU,EGU error interrupts */ 762 hclge_cmd_setup_basic_desc(&desc, HCLGE_IGU_COMMON_INT_EN, false); 763 if (en) 764 desc.data[0] = cpu_to_le32(HCLGE_IGU_ERR_INT_EN); 765 766 desc.data[1] = cpu_to_le32(HCLGE_IGU_ERR_INT_EN_MASK); 767 768 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 769 if (ret) { 770 dev_err(dev, 771 "fail(%d) to configure IGU common interrupts\n", ret); 772 return ret; 773 } 774 775 hclge_cmd_setup_basic_desc(&desc, HCLGE_IGU_EGU_TNL_INT_EN, false); 776 if (en) 777 desc.data[0] = cpu_to_le32(HCLGE_IGU_TNL_ERR_INT_EN); 778 779 desc.data[1] = cpu_to_le32(HCLGE_IGU_TNL_ERR_INT_EN_MASK); 780 781 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 782 if (ret) { 783 dev_err(dev, 784 "fail(%d) to configure IGU-EGU TNL interrupts\n", ret); 785 return ret; 786 } 787 788 ret = hclge_config_ncsi_hw_err_int(hdev, en); 789 790 return ret; 791 } 792 793 static int hclge_config_ppp_error_interrupt(struct hclge_dev *hdev, u32 cmd, 794 bool en) 795 { 796 struct device *dev = &hdev->pdev->dev; 797 struct hclge_desc desc[2]; 798 int ret; 799 800 /* configure PPP error interrupts */ 801 hclge_cmd_setup_basic_desc(&desc[0], cmd, false); 802 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 803 hclge_cmd_setup_basic_desc(&desc[1], cmd, false); 804 805 if (cmd == HCLGE_PPP_CMD0_INT_CMD) { 806 if (en) { 807 desc[0].data[0] = 808 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT0_EN); 809 desc[0].data[1] = 810 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT1_EN); 811 desc[0].data[4] = cpu_to_le32(HCLGE_PPP_PF_ERR_INT_EN); 812 } 813 814 desc[1].data[0] = 815 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK); 816 desc[1].data[1] = 817 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK); 818 if (hdev->pdev->revision >= 0x21) 819 desc[1].data[2] = 820 cpu_to_le32(HCLGE_PPP_PF_ERR_INT_EN_MASK); 821 } else if (cmd == HCLGE_PPP_CMD1_INT_CMD) { 822 if (en) { 823 desc[0].data[0] = 824 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT2_EN); 825 desc[0].data[1] = 826 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT3_EN); 827 } 828 829 desc[1].data[0] = 830 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK); 831 desc[1].data[1] = 832 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK); 833 } 834 835 ret = hclge_cmd_send(&hdev->hw, &desc[0], 2); 836 if (ret) 837 dev_err(dev, "fail(%d) to configure PPP error intr\n", ret); 838 839 return ret; 840 } 841 842 static int hclge_config_ppp_hw_err_int(struct hclge_dev *hdev, bool en) 843 { 844 int ret; 845 846 ret = hclge_config_ppp_error_interrupt(hdev, HCLGE_PPP_CMD0_INT_CMD, 847 en); 848 if (ret) 849 return ret; 850 851 ret = hclge_config_ppp_error_interrupt(hdev, HCLGE_PPP_CMD1_INT_CMD, 852 en); 853 854 return ret; 855 } 856 857 static int hclge_config_tm_hw_err_int(struct hclge_dev *hdev, bool en) 858 { 859 struct device *dev = &hdev->pdev->dev; 860 struct hclge_desc desc; 861 int ret; 862 863 /* configure TM SCH hw errors */ 864 hclge_cmd_setup_basic_desc(&desc, HCLGE_TM_SCH_ECC_INT_EN, false); 865 if (en) 866 desc.data[0] = cpu_to_le32(HCLGE_TM_SCH_ECC_ERR_INT_EN); 867 868 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 869 if (ret) { 870 dev_err(dev, "fail(%d) to configure TM SCH errors\n", ret); 871 return ret; 872 } 873 874 /* configure TM QCN hw errors */ 875 ret = hclge_cmd_query_error(hdev, &desc, HCLGE_TM_QCN_MEM_INT_CFG, 876 0, 0, 0); 877 if (ret) { 878 dev_err(dev, "fail(%d) to read TM QCN CFG status\n", ret); 879 return ret; 880 } 881 882 hclge_cmd_reuse_desc(&desc, false); 883 if (en) 884 desc.data[1] = cpu_to_le32(HCLGE_TM_QCN_MEM_ERR_INT_EN); 885 886 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 887 if (ret) 888 dev_err(dev, 889 "fail(%d) to configure TM QCN mem errors\n", ret); 890 891 return ret; 892 } 893 894 static int hclge_config_mac_err_int(struct hclge_dev *hdev, bool en) 895 { 896 struct device *dev = &hdev->pdev->dev; 897 struct hclge_desc desc; 898 int ret; 899 900 /* configure MAC common error interrupts */ 901 hclge_cmd_setup_basic_desc(&desc, HCLGE_MAC_COMMON_INT_EN, false); 902 if (en) 903 desc.data[0] = cpu_to_le32(HCLGE_MAC_COMMON_ERR_INT_EN); 904 905 desc.data[1] = cpu_to_le32(HCLGE_MAC_COMMON_ERR_INT_EN_MASK); 906 907 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 908 if (ret) 909 dev_err(dev, 910 "fail(%d) to configure MAC COMMON error intr\n", ret); 911 912 return ret; 913 } 914 915 int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en) 916 { 917 struct hclge_desc desc; 918 919 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_TNL_INT_EN, false); 920 if (en) 921 desc.data[0] = cpu_to_le32(HCLGE_MAC_TNL_INT_EN); 922 else 923 desc.data[0] = 0; 924 925 desc.data[1] = cpu_to_le32(HCLGE_MAC_TNL_INT_EN_MASK); 926 927 return hclge_cmd_send(&hdev->hw, &desc, 1); 928 } 929 930 static int hclge_config_ppu_error_interrupts(struct hclge_dev *hdev, u32 cmd, 931 bool en) 932 { 933 struct device *dev = &hdev->pdev->dev; 934 struct hclge_desc desc[2]; 935 int desc_num = 1; 936 int ret; 937 938 /* configure PPU error interrupts */ 939 if (cmd == HCLGE_PPU_MPF_ECC_INT_CMD) { 940 hclge_cmd_setup_basic_desc(&desc[0], cmd, false); 941 desc[0].flag |= HCLGE_CMD_FLAG_NEXT; 942 hclge_cmd_setup_basic_desc(&desc[1], cmd, false); 943 if (en) { 944 desc[0].data[0] = HCLGE_PPU_MPF_ABNORMAL_INT0_EN; 945 desc[0].data[1] = HCLGE_PPU_MPF_ABNORMAL_INT1_EN; 946 desc[1].data[3] = HCLGE_PPU_MPF_ABNORMAL_INT3_EN; 947 desc[1].data[4] = HCLGE_PPU_MPF_ABNORMAL_INT2_EN; 948 } 949 950 desc[1].data[0] = HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK; 951 desc[1].data[1] = HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK; 952 desc[1].data[2] = HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK; 953 desc[1].data[3] |= HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK; 954 desc_num = 2; 955 } else if (cmd == HCLGE_PPU_MPF_OTHER_INT_CMD) { 956 hclge_cmd_setup_basic_desc(&desc[0], cmd, false); 957 if (en) 958 desc[0].data[0] = HCLGE_PPU_MPF_ABNORMAL_INT2_EN2; 959 960 desc[0].data[2] = HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK; 961 } else if (cmd == HCLGE_PPU_PF_OTHER_INT_CMD) { 962 hclge_cmd_setup_basic_desc(&desc[0], cmd, false); 963 if (en) 964 desc[0].data[0] = HCLGE_PPU_PF_ABNORMAL_INT_EN; 965 966 desc[0].data[2] = HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK; 967 } else { 968 dev_err(dev, "Invalid cmd to configure PPU error interrupts\n"); 969 return -EINVAL; 970 } 971 972 ret = hclge_cmd_send(&hdev->hw, &desc[0], desc_num); 973 974 return ret; 975 } 976 977 static int hclge_config_ppu_hw_err_int(struct hclge_dev *hdev, bool en) 978 { 979 struct device *dev = &hdev->pdev->dev; 980 int ret; 981 982 ret = hclge_config_ppu_error_interrupts(hdev, HCLGE_PPU_MPF_ECC_INT_CMD, 983 en); 984 if (ret) { 985 dev_err(dev, "fail(%d) to configure PPU MPF ECC error intr\n", 986 ret); 987 return ret; 988 } 989 990 ret = hclge_config_ppu_error_interrupts(hdev, 991 HCLGE_PPU_MPF_OTHER_INT_CMD, 992 en); 993 if (ret) { 994 dev_err(dev, "fail(%d) to configure PPU MPF other intr\n", ret); 995 return ret; 996 } 997 998 ret = hclge_config_ppu_error_interrupts(hdev, 999 HCLGE_PPU_PF_OTHER_INT_CMD, en); 1000 if (ret) 1001 dev_err(dev, "fail(%d) to configure PPU PF error interrupts\n", 1002 ret); 1003 return ret; 1004 } 1005 1006 static int hclge_config_ssu_hw_err_int(struct hclge_dev *hdev, bool en) 1007 { 1008 struct device *dev = &hdev->pdev->dev; 1009 struct hclge_desc desc[2]; 1010 int ret; 1011 1012 /* configure SSU ecc error interrupts */ 1013 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_SSU_ECC_INT_CMD, false); 1014 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1015 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_SSU_ECC_INT_CMD, false); 1016 if (en) { 1017 desc[0].data[0] = cpu_to_le32(HCLGE_SSU_1BIT_ECC_ERR_INT_EN); 1018 desc[0].data[1] = 1019 cpu_to_le32(HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN); 1020 desc[0].data[4] = cpu_to_le32(HCLGE_SSU_BIT32_ECC_ERR_INT_EN); 1021 } 1022 1023 desc[1].data[0] = cpu_to_le32(HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK); 1024 desc[1].data[1] = cpu_to_le32(HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK); 1025 desc[1].data[2] = cpu_to_le32(HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK); 1026 1027 ret = hclge_cmd_send(&hdev->hw, &desc[0], 2); 1028 if (ret) { 1029 dev_err(dev, 1030 "fail(%d) to configure SSU ECC error interrupt\n", ret); 1031 return ret; 1032 } 1033 1034 /* configure SSU common error interrupts */ 1035 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_SSU_COMMON_INT_CMD, false); 1036 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1037 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_SSU_COMMON_INT_CMD, false); 1038 1039 if (en) { 1040 if (hdev->pdev->revision >= 0x21) 1041 desc[0].data[0] = 1042 cpu_to_le32(HCLGE_SSU_COMMON_INT_EN); 1043 else 1044 desc[0].data[0] = 1045 cpu_to_le32(HCLGE_SSU_COMMON_INT_EN & ~BIT(5)); 1046 desc[0].data[1] = cpu_to_le32(HCLGE_SSU_PORT_BASED_ERR_INT_EN); 1047 desc[0].data[2] = 1048 cpu_to_le32(HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN); 1049 } 1050 1051 desc[1].data[0] = cpu_to_le32(HCLGE_SSU_COMMON_INT_EN_MASK | 1052 HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK); 1053 desc[1].data[1] = cpu_to_le32(HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK); 1054 1055 ret = hclge_cmd_send(&hdev->hw, &desc[0], 2); 1056 if (ret) 1057 dev_err(dev, 1058 "fail(%d) to configure SSU COMMON error intr\n", ret); 1059 1060 return ret; 1061 } 1062 1063 /* hclge_query_bd_num: query number of buffer descriptors 1064 * @hdev: pointer to struct hclge_dev 1065 * @is_ras: true for ras, false for msix 1066 * @mpf_bd_num: number of main PF interrupt buffer descriptors 1067 * @pf_bd_num: number of not main PF interrupt buffer descriptors 1068 * 1069 * This function querys number of mpf and pf buffer descriptors. 1070 */ 1071 static int hclge_query_bd_num(struct hclge_dev *hdev, bool is_ras, 1072 int *mpf_bd_num, int *pf_bd_num) 1073 { 1074 struct device *dev = &hdev->pdev->dev; 1075 u32 mpf_min_bd_num, pf_min_bd_num; 1076 enum hclge_opcode_type opcode; 1077 struct hclge_desc desc_bd; 1078 int ret; 1079 1080 if (is_ras) { 1081 opcode = HCLGE_QUERY_RAS_INT_STS_BD_NUM; 1082 mpf_min_bd_num = HCLGE_MPF_RAS_INT_MIN_BD_NUM; 1083 pf_min_bd_num = HCLGE_PF_RAS_INT_MIN_BD_NUM; 1084 } else { 1085 opcode = HCLGE_QUERY_MSIX_INT_STS_BD_NUM; 1086 mpf_min_bd_num = HCLGE_MPF_MSIX_INT_MIN_BD_NUM; 1087 pf_min_bd_num = HCLGE_PF_MSIX_INT_MIN_BD_NUM; 1088 } 1089 1090 hclge_cmd_setup_basic_desc(&desc_bd, opcode, true); 1091 ret = hclge_cmd_send(&hdev->hw, &desc_bd, 1); 1092 if (ret) { 1093 dev_err(dev, "fail(%d) to query msix int status bd num\n", 1094 ret); 1095 return ret; 1096 } 1097 1098 *mpf_bd_num = le32_to_cpu(desc_bd.data[0]); 1099 *pf_bd_num = le32_to_cpu(desc_bd.data[1]); 1100 if (*mpf_bd_num < mpf_min_bd_num || *pf_bd_num < pf_min_bd_num) { 1101 dev_err(dev, "Invalid bd num: mpf(%d), pf(%d)\n", 1102 *mpf_bd_num, *pf_bd_num); 1103 return -EINVAL; 1104 } 1105 1106 return 0; 1107 } 1108 1109 /* hclge_handle_mpf_ras_error: handle all main PF RAS errors 1110 * @hdev: pointer to struct hclge_dev 1111 * @desc: descriptor for describing the command 1112 * @num: number of extended command structures 1113 * 1114 * This function handles all the main PF RAS errors in the 1115 * hw register/s using command. 1116 */ 1117 static int hclge_handle_mpf_ras_error(struct hclge_dev *hdev, 1118 struct hclge_desc *desc, 1119 int num) 1120 { 1121 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 1122 struct device *dev = &hdev->pdev->dev; 1123 __le32 *desc_data; 1124 u32 status; 1125 int ret; 1126 1127 /* query all main PF RAS errors */ 1128 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_MPF_RAS_INT, 1129 true); 1130 ret = hclge_cmd_send(&hdev->hw, &desc[0], num); 1131 if (ret) { 1132 dev_err(dev, "query all mpf ras int cmd failed (%d)\n", ret); 1133 return ret; 1134 } 1135 1136 /* log HNS common errors */ 1137 status = le32_to_cpu(desc[0].data[0]); 1138 if (status) 1139 hclge_log_error(dev, "IMP_TCM_ECC_INT_STS", 1140 &hclge_imp_tcm_ecc_int[0], status, 1141 &ae_dev->hw_err_reset_req); 1142 1143 status = le32_to_cpu(desc[0].data[1]); 1144 if (status) 1145 hclge_log_error(dev, "CMDQ_MEM_ECC_INT_STS", 1146 &hclge_cmdq_nic_mem_ecc_int[0], status, 1147 &ae_dev->hw_err_reset_req); 1148 1149 if ((le32_to_cpu(desc[0].data[2])) & BIT(0)) 1150 dev_warn(dev, "imp_rd_data_poison_err found\n"); 1151 1152 status = le32_to_cpu(desc[0].data[3]); 1153 if (status) 1154 hclge_log_error(dev, "TQP_INT_ECC_INT_STS", 1155 &hclge_tqp_int_ecc_int[0], status, 1156 &ae_dev->hw_err_reset_req); 1157 1158 status = le32_to_cpu(desc[0].data[4]); 1159 if (status) 1160 hclge_log_error(dev, "MSIX_ECC_INT_STS", 1161 &hclge_msix_sram_ecc_int[0], status, 1162 &ae_dev->hw_err_reset_req); 1163 1164 /* log SSU(Storage Switch Unit) errors */ 1165 desc_data = (__le32 *)&desc[2]; 1166 status = le32_to_cpu(*(desc_data + 2)); 1167 if (status) 1168 hclge_log_error(dev, "SSU_ECC_MULTI_BIT_INT_0", 1169 &hclge_ssu_mem_ecc_err_int[0], status, 1170 &ae_dev->hw_err_reset_req); 1171 1172 status = le32_to_cpu(*(desc_data + 3)) & BIT(0); 1173 if (status) { 1174 dev_warn(dev, "SSU_ECC_MULTI_BIT_INT_1 ssu_mem32_ecc_mbit_err found [error status=0x%x]\n", 1175 status); 1176 set_bit(HNAE3_GLOBAL_RESET, &ae_dev->hw_err_reset_req); 1177 } 1178 1179 status = le32_to_cpu(*(desc_data + 4)) & HCLGE_SSU_COMMON_ERR_INT_MASK; 1180 if (status) 1181 hclge_log_error(dev, "SSU_COMMON_ERR_INT", 1182 &hclge_ssu_com_err_int[0], status, 1183 &ae_dev->hw_err_reset_req); 1184 1185 /* log IGU(Ingress Unit) errors */ 1186 desc_data = (__le32 *)&desc[3]; 1187 status = le32_to_cpu(*desc_data) & HCLGE_IGU_INT_MASK; 1188 if (status) 1189 hclge_log_error(dev, "IGU_INT_STS", 1190 &hclge_igu_int[0], status, 1191 &ae_dev->hw_err_reset_req); 1192 1193 /* log PPP(Programmable Packet Process) errors */ 1194 desc_data = (__le32 *)&desc[4]; 1195 status = le32_to_cpu(*(desc_data + 1)); 1196 if (status) 1197 hclge_log_error(dev, "PPP_MPF_ABNORMAL_INT_ST1", 1198 &hclge_ppp_mpf_abnormal_int_st1[0], status, 1199 &ae_dev->hw_err_reset_req); 1200 1201 status = le32_to_cpu(*(desc_data + 3)) & HCLGE_PPP_MPF_INT_ST3_MASK; 1202 if (status) 1203 hclge_log_error(dev, "PPP_MPF_ABNORMAL_INT_ST3", 1204 &hclge_ppp_mpf_abnormal_int_st3[0], status, 1205 &ae_dev->hw_err_reset_req); 1206 1207 /* log PPU(RCB) errors */ 1208 desc_data = (__le32 *)&desc[5]; 1209 status = le32_to_cpu(*(desc_data + 1)); 1210 if (status) { 1211 dev_warn(dev, "PPU_MPF_ABNORMAL_INT_ST1 %s found\n", 1212 "rpu_rx_pkt_ecc_mbit_err"); 1213 set_bit(HNAE3_GLOBAL_RESET, &ae_dev->hw_err_reset_req); 1214 } 1215 1216 status = le32_to_cpu(*(desc_data + 2)); 1217 if (status) 1218 hclge_log_error(dev, "PPU_MPF_ABNORMAL_INT_ST2", 1219 &hclge_ppu_mpf_abnormal_int_st2[0], status, 1220 &ae_dev->hw_err_reset_req); 1221 1222 status = le32_to_cpu(*(desc_data + 3)) & HCLGE_PPU_MPF_INT_ST3_MASK; 1223 if (status) 1224 hclge_log_error(dev, "PPU_MPF_ABNORMAL_INT_ST3", 1225 &hclge_ppu_mpf_abnormal_int_st3[0], status, 1226 &ae_dev->hw_err_reset_req); 1227 1228 /* log TM(Traffic Manager) errors */ 1229 desc_data = (__le32 *)&desc[6]; 1230 status = le32_to_cpu(*desc_data); 1231 if (status) 1232 hclge_log_error(dev, "TM_SCH_RINT", 1233 &hclge_tm_sch_rint[0], status, 1234 &ae_dev->hw_err_reset_req); 1235 1236 /* log QCN(Quantized Congestion Control) errors */ 1237 desc_data = (__le32 *)&desc[7]; 1238 status = le32_to_cpu(*desc_data) & HCLGE_QCN_FIFO_INT_MASK; 1239 if (status) 1240 hclge_log_error(dev, "QCN_FIFO_RINT", 1241 &hclge_qcn_fifo_rint[0], status, 1242 &ae_dev->hw_err_reset_req); 1243 1244 status = le32_to_cpu(*(desc_data + 1)) & HCLGE_QCN_ECC_INT_MASK; 1245 if (status) 1246 hclge_log_error(dev, "QCN_ECC_RINT", 1247 &hclge_qcn_ecc_rint[0], status, 1248 &ae_dev->hw_err_reset_req); 1249 1250 /* log NCSI errors */ 1251 desc_data = (__le32 *)&desc[9]; 1252 status = le32_to_cpu(*desc_data) & HCLGE_NCSI_ECC_INT_MASK; 1253 if (status) 1254 hclge_log_error(dev, "NCSI_ECC_INT_RPT", 1255 &hclge_ncsi_err_int[0], status, 1256 &ae_dev->hw_err_reset_req); 1257 1258 /* clear all main PF RAS errors */ 1259 hclge_cmd_reuse_desc(&desc[0], false); 1260 ret = hclge_cmd_send(&hdev->hw, &desc[0], num); 1261 if (ret) 1262 dev_err(dev, "clear all mpf ras int cmd failed (%d)\n", ret); 1263 1264 return ret; 1265 } 1266 1267 /* hclge_handle_pf_ras_error: handle all PF RAS errors 1268 * @hdev: pointer to struct hclge_dev 1269 * @desc: descriptor for describing the command 1270 * @num: number of extended command structures 1271 * 1272 * This function handles all the PF RAS errors in the 1273 * hw register/s using command. 1274 */ 1275 static int hclge_handle_pf_ras_error(struct hclge_dev *hdev, 1276 struct hclge_desc *desc, 1277 int num) 1278 { 1279 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 1280 struct device *dev = &hdev->pdev->dev; 1281 __le32 *desc_data; 1282 u32 status; 1283 int ret; 1284 1285 /* query all PF RAS errors */ 1286 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_PF_RAS_INT, 1287 true); 1288 ret = hclge_cmd_send(&hdev->hw, &desc[0], num); 1289 if (ret) { 1290 dev_err(dev, "query all pf ras int cmd failed (%d)\n", ret); 1291 return ret; 1292 } 1293 1294 /* log SSU(Storage Switch Unit) errors */ 1295 status = le32_to_cpu(desc[0].data[0]); 1296 if (status) 1297 hclge_log_error(dev, "SSU_PORT_BASED_ERR_INT", 1298 &hclge_ssu_port_based_err_int[0], status, 1299 &ae_dev->hw_err_reset_req); 1300 1301 status = le32_to_cpu(desc[0].data[1]); 1302 if (status) 1303 hclge_log_error(dev, "SSU_FIFO_OVERFLOW_INT", 1304 &hclge_ssu_fifo_overflow_int[0], status, 1305 &ae_dev->hw_err_reset_req); 1306 1307 status = le32_to_cpu(desc[0].data[2]); 1308 if (status) 1309 hclge_log_error(dev, "SSU_ETS_TCG_INT", 1310 &hclge_ssu_ets_tcg_int[0], status, 1311 &ae_dev->hw_err_reset_req); 1312 1313 /* log IGU(Ingress Unit) EGU(Egress Unit) TNL errors */ 1314 desc_data = (__le32 *)&desc[1]; 1315 status = le32_to_cpu(*desc_data) & HCLGE_IGU_EGU_TNL_INT_MASK; 1316 if (status) 1317 hclge_log_error(dev, "IGU_EGU_TNL_INT_STS", 1318 &hclge_igu_egu_tnl_int[0], status, 1319 &ae_dev->hw_err_reset_req); 1320 1321 /* log PPU(RCB) errors */ 1322 desc_data = (__le32 *)&desc[3]; 1323 status = le32_to_cpu(*desc_data) & HCLGE_PPU_PF_INT_RAS_MASK; 1324 if (status) 1325 hclge_log_error(dev, "PPU_PF_ABNORMAL_INT_ST0", 1326 &hclge_ppu_pf_abnormal_int[0], status, 1327 &ae_dev->hw_err_reset_req); 1328 1329 /* clear all PF RAS errors */ 1330 hclge_cmd_reuse_desc(&desc[0], false); 1331 ret = hclge_cmd_send(&hdev->hw, &desc[0], num); 1332 if (ret) 1333 dev_err(dev, "clear all pf ras int cmd failed (%d)\n", ret); 1334 1335 return ret; 1336 } 1337 1338 static int hclge_handle_all_ras_errors(struct hclge_dev *hdev) 1339 { 1340 u32 mpf_bd_num, pf_bd_num, bd_num; 1341 struct hclge_desc *desc; 1342 int ret; 1343 1344 /* query the number of registers in the RAS int status */ 1345 ret = hclge_query_bd_num(hdev, true, &mpf_bd_num, &pf_bd_num); 1346 if (ret) 1347 return ret; 1348 1349 bd_num = max_t(u32, mpf_bd_num, pf_bd_num); 1350 desc = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL); 1351 if (!desc) 1352 return -ENOMEM; 1353 1354 /* handle all main PF RAS errors */ 1355 ret = hclge_handle_mpf_ras_error(hdev, desc, mpf_bd_num); 1356 if (ret) { 1357 kfree(desc); 1358 return ret; 1359 } 1360 memset(desc, 0, bd_num * sizeof(struct hclge_desc)); 1361 1362 /* handle all PF RAS errors */ 1363 ret = hclge_handle_pf_ras_error(hdev, desc, pf_bd_num); 1364 kfree(desc); 1365 1366 return ret; 1367 } 1368 1369 static int hclge_log_rocee_axi_error(struct hclge_dev *hdev) 1370 { 1371 struct device *dev = &hdev->pdev->dev; 1372 struct hclge_desc desc[3]; 1373 int ret; 1374 1375 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD, 1376 true); 1377 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD, 1378 true); 1379 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD, 1380 true); 1381 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1382 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1383 1384 ret = hclge_cmd_send(&hdev->hw, &desc[0], 3); 1385 if (ret) { 1386 dev_err(dev, "failed(%d) to query ROCEE AXI error sts\n", ret); 1387 return ret; 1388 } 1389 1390 dev_info(dev, "AXI1: %08X %08X %08X %08X %08X %08X\n", 1391 le32_to_cpu(desc[0].data[0]), le32_to_cpu(desc[0].data[1]), 1392 le32_to_cpu(desc[0].data[2]), le32_to_cpu(desc[0].data[3]), 1393 le32_to_cpu(desc[0].data[4]), le32_to_cpu(desc[0].data[5])); 1394 dev_info(dev, "AXI2: %08X %08X %08X %08X %08X %08X\n", 1395 le32_to_cpu(desc[1].data[0]), le32_to_cpu(desc[1].data[1]), 1396 le32_to_cpu(desc[1].data[2]), le32_to_cpu(desc[1].data[3]), 1397 le32_to_cpu(desc[1].data[4]), le32_to_cpu(desc[1].data[5])); 1398 dev_info(dev, "AXI3: %08X %08X %08X %08X\n", 1399 le32_to_cpu(desc[2].data[0]), le32_to_cpu(desc[2].data[1]), 1400 le32_to_cpu(desc[2].data[2]), le32_to_cpu(desc[2].data[3])); 1401 1402 return 0; 1403 } 1404 1405 static int hclge_log_rocee_ecc_error(struct hclge_dev *hdev) 1406 { 1407 struct device *dev = &hdev->pdev->dev; 1408 struct hclge_desc desc[2]; 1409 int ret; 1410 1411 ret = hclge_cmd_query_error(hdev, &desc[0], 1412 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD, 1413 HCLGE_CMD_FLAG_NEXT, 0, 0); 1414 if (ret) { 1415 dev_err(dev, "failed(%d) to query ROCEE ECC error sts\n", ret); 1416 return ret; 1417 } 1418 1419 dev_info(dev, "ECC1: %08X %08X %08X %08X %08X %08X\n", 1420 le32_to_cpu(desc[0].data[0]), le32_to_cpu(desc[0].data[1]), 1421 le32_to_cpu(desc[0].data[2]), le32_to_cpu(desc[0].data[3]), 1422 le32_to_cpu(desc[0].data[4]), le32_to_cpu(desc[0].data[5])); 1423 dev_info(dev, "ECC2: %08X %08X %08X\n", le32_to_cpu(desc[1].data[0]), 1424 le32_to_cpu(desc[1].data[1]), le32_to_cpu(desc[1].data[2])); 1425 1426 return 0; 1427 } 1428 1429 static int hclge_log_rocee_ovf_error(struct hclge_dev *hdev) 1430 { 1431 struct device *dev = &hdev->pdev->dev; 1432 struct hclge_desc desc[2]; 1433 int ret; 1434 1435 /* read overflow error status */ 1436 ret = hclge_cmd_query_error(hdev, &desc[0], HCLGE_ROCEE_PF_RAS_INT_CMD, 1437 0, 0, 0); 1438 if (ret) { 1439 dev_err(dev, "failed(%d) to query ROCEE OVF error sts\n", ret); 1440 return ret; 1441 } 1442 1443 /* log overflow error */ 1444 if (le32_to_cpu(desc[0].data[0]) & HCLGE_ROCEE_OVF_ERR_INT_MASK) { 1445 const struct hclge_hw_error *err; 1446 u32 err_sts; 1447 1448 err = &hclge_rocee_qmm_ovf_err_int[0]; 1449 err_sts = HCLGE_ROCEE_OVF_ERR_TYPE_MASK & 1450 le32_to_cpu(desc[0].data[0]); 1451 while (err->msg) { 1452 if (err->int_msk == err_sts) { 1453 dev_warn(dev, "%s [error status=0x%x] found\n", 1454 err->msg, 1455 le32_to_cpu(desc[0].data[0])); 1456 break; 1457 } 1458 err++; 1459 } 1460 } 1461 1462 if (le32_to_cpu(desc[0].data[1]) & HCLGE_ROCEE_OVF_ERR_INT_MASK) { 1463 dev_warn(dev, "ROCEE TSP OVF [error status=0x%x] found\n", 1464 le32_to_cpu(desc[0].data[1])); 1465 } 1466 1467 if (le32_to_cpu(desc[0].data[2]) & HCLGE_ROCEE_OVF_ERR_INT_MASK) { 1468 dev_warn(dev, "ROCEE SCC OVF [error status=0x%x] found\n", 1469 le32_to_cpu(desc[0].data[2])); 1470 } 1471 1472 return 0; 1473 } 1474 1475 static enum hnae3_reset_type 1476 hclge_log_and_clear_rocee_ras_error(struct hclge_dev *hdev) 1477 { 1478 enum hnae3_reset_type reset_type = HNAE3_NONE_RESET; 1479 struct device *dev = &hdev->pdev->dev; 1480 struct hclge_desc desc[2]; 1481 unsigned int status; 1482 int ret; 1483 1484 /* read RAS error interrupt status */ 1485 ret = hclge_cmd_query_error(hdev, &desc[0], 1486 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT, 1487 0, 0, 0); 1488 if (ret) { 1489 dev_err(dev, "failed(%d) to query ROCEE RAS INT SRC\n", ret); 1490 /* reset everything for now */ 1491 return HNAE3_GLOBAL_RESET; 1492 } 1493 1494 status = le32_to_cpu(desc[0].data[0]); 1495 1496 if (status & HCLGE_ROCEE_AXI_ERR_INT_MASK) { 1497 if (status & HCLGE_ROCEE_RERR_INT_MASK) 1498 dev_warn(dev, "ROCEE RAS AXI rresp error\n"); 1499 1500 if (status & HCLGE_ROCEE_BERR_INT_MASK) 1501 dev_warn(dev, "ROCEE RAS AXI bresp error\n"); 1502 1503 reset_type = HNAE3_FUNC_RESET; 1504 1505 ret = hclge_log_rocee_axi_error(hdev); 1506 if (ret) 1507 return HNAE3_GLOBAL_RESET; 1508 } 1509 1510 if (status & HCLGE_ROCEE_ECC_INT_MASK) { 1511 dev_warn(dev, "ROCEE RAS 2bit ECC error\n"); 1512 reset_type = HNAE3_GLOBAL_RESET; 1513 1514 ret = hclge_log_rocee_ecc_error(hdev); 1515 if (ret) 1516 return HNAE3_GLOBAL_RESET; 1517 } 1518 1519 if (status & HCLGE_ROCEE_OVF_INT_MASK) { 1520 ret = hclge_log_rocee_ovf_error(hdev); 1521 if (ret) { 1522 dev_err(dev, "failed(%d) to process ovf error\n", ret); 1523 /* reset everything for now */ 1524 return HNAE3_GLOBAL_RESET; 1525 } 1526 } 1527 1528 /* clear error status */ 1529 hclge_cmd_reuse_desc(&desc[0], false); 1530 ret = hclge_cmd_send(&hdev->hw, &desc[0], 1); 1531 if (ret) { 1532 dev_err(dev, "failed(%d) to clear ROCEE RAS error\n", ret); 1533 /* reset everything for now */ 1534 return HNAE3_GLOBAL_RESET; 1535 } 1536 1537 return reset_type; 1538 } 1539 1540 int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en) 1541 { 1542 struct device *dev = &hdev->pdev->dev; 1543 struct hclge_desc desc; 1544 int ret; 1545 1546 if (hdev->pdev->revision < 0x21 || !hnae3_dev_roce_supported(hdev)) 1547 return 0; 1548 1549 hclge_cmd_setup_basic_desc(&desc, HCLGE_CONFIG_ROCEE_RAS_INT_EN, false); 1550 if (en) { 1551 /* enable ROCEE hw error interrupts */ 1552 desc.data[0] = cpu_to_le32(HCLGE_ROCEE_RAS_NFE_INT_EN); 1553 desc.data[1] = cpu_to_le32(HCLGE_ROCEE_RAS_CE_INT_EN); 1554 1555 hclge_log_and_clear_rocee_ras_error(hdev); 1556 } 1557 desc.data[2] = cpu_to_le32(HCLGE_ROCEE_RAS_NFE_INT_EN_MASK); 1558 desc.data[3] = cpu_to_le32(HCLGE_ROCEE_RAS_CE_INT_EN_MASK); 1559 1560 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1561 if (ret) 1562 dev_err(dev, "failed(%d) to config ROCEE RAS interrupt\n", ret); 1563 1564 return ret; 1565 } 1566 1567 static void hclge_handle_rocee_ras_error(struct hnae3_ae_dev *ae_dev) 1568 { 1569 enum hnae3_reset_type reset_type = HNAE3_NONE_RESET; 1570 struct hclge_dev *hdev = ae_dev->priv; 1571 1572 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 1573 hdev->pdev->revision < 0x21) 1574 return; 1575 1576 reset_type = hclge_log_and_clear_rocee_ras_error(hdev); 1577 if (reset_type != HNAE3_NONE_RESET) 1578 set_bit(reset_type, &ae_dev->hw_err_reset_req); 1579 } 1580 1581 static const struct hclge_hw_blk hw_blk[] = { 1582 { 1583 .msk = BIT(0), .name = "IGU_EGU", 1584 .config_err_int = hclge_config_igu_egu_hw_err_int, 1585 }, 1586 { 1587 .msk = BIT(1), .name = "PPP", 1588 .config_err_int = hclge_config_ppp_hw_err_int, 1589 }, 1590 { 1591 .msk = BIT(2), .name = "SSU", 1592 .config_err_int = hclge_config_ssu_hw_err_int, 1593 }, 1594 { 1595 .msk = BIT(3), .name = "PPU", 1596 .config_err_int = hclge_config_ppu_hw_err_int, 1597 }, 1598 { 1599 .msk = BIT(4), .name = "TM", 1600 .config_err_int = hclge_config_tm_hw_err_int, 1601 }, 1602 { 1603 .msk = BIT(5), .name = "COMMON", 1604 .config_err_int = hclge_config_common_hw_err_int, 1605 }, 1606 { 1607 .msk = BIT(8), .name = "MAC", 1608 .config_err_int = hclge_config_mac_err_int, 1609 }, 1610 { /* sentinel */ } 1611 }; 1612 1613 int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state) 1614 { 1615 const struct hclge_hw_blk *module = hw_blk; 1616 int ret = 0; 1617 1618 while (module->name) { 1619 if (module->config_err_int) { 1620 ret = module->config_err_int(hdev, state); 1621 if (ret) 1622 return ret; 1623 } 1624 module++; 1625 } 1626 1627 return ret; 1628 } 1629 1630 pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev) 1631 { 1632 struct hclge_dev *hdev = ae_dev->priv; 1633 struct device *dev = &hdev->pdev->dev; 1634 u32 status; 1635 1636 if (!test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state)) { 1637 dev_err(dev, 1638 "Can't recover - RAS error reported during dev init\n"); 1639 return PCI_ERS_RESULT_NONE; 1640 } 1641 1642 status = hclge_read_dev(&hdev->hw, HCLGE_RAS_PF_OTHER_INT_STS_REG); 1643 1644 if (status & HCLGE_RAS_REG_NFE_MASK || 1645 status & HCLGE_RAS_REG_ROCEE_ERR_MASK) 1646 ae_dev->hw_err_reset_req = 0; 1647 else 1648 goto out; 1649 1650 /* Handling Non-fatal HNS RAS errors */ 1651 if (status & HCLGE_RAS_REG_NFE_MASK) { 1652 dev_warn(dev, 1653 "HNS Non-Fatal RAS error(status=0x%x) identified\n", 1654 status); 1655 hclge_handle_all_ras_errors(hdev); 1656 } 1657 1658 /* Handling Non-fatal Rocee RAS errors */ 1659 if (hdev->pdev->revision >= 0x21 && 1660 status & HCLGE_RAS_REG_ROCEE_ERR_MASK) { 1661 dev_warn(dev, "ROCEE Non-Fatal RAS error identified\n"); 1662 hclge_handle_rocee_ras_error(ae_dev); 1663 } 1664 1665 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 1666 goto out; 1667 1668 if (ae_dev->hw_err_reset_req) 1669 return PCI_ERS_RESULT_NEED_RESET; 1670 1671 out: 1672 return PCI_ERS_RESULT_RECOVERED; 1673 } 1674 1675 static int hclge_clear_hw_msix_error(struct hclge_dev *hdev, 1676 struct hclge_desc *desc, bool is_mpf, 1677 u32 bd_num) 1678 { 1679 if (is_mpf) 1680 desc[0].opcode = 1681 cpu_to_le16(HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT); 1682 else 1683 desc[0].opcode = cpu_to_le16(HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT); 1684 1685 desc[0].flag = cpu_to_le16(HCLGE_CMD_FLAG_NO_INTR | HCLGE_CMD_FLAG_IN); 1686 1687 return hclge_cmd_send(&hdev->hw, &desc[0], bd_num); 1688 } 1689 1690 /* hclge_query_8bd_info: query information about over_8bd_nfe_err 1691 * @hdev: pointer to struct hclge_dev 1692 * @vf_id: Index of the virtual function with error 1693 * @q_id: Physical index of the queue with error 1694 * 1695 * This function get specific index of queue and function which causes 1696 * over_8bd_nfe_err by using command. If vf_id is 0, it means error is 1697 * caused by PF instead of VF. 1698 */ 1699 static int hclge_query_over_8bd_err_info(struct hclge_dev *hdev, u16 *vf_id, 1700 u16 *q_id) 1701 { 1702 struct hclge_query_ppu_pf_other_int_dfx_cmd *req; 1703 struct hclge_desc desc; 1704 int ret; 1705 1706 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PPU_PF_OTHER_INT_DFX, true); 1707 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1708 if (ret) 1709 return ret; 1710 1711 req = (struct hclge_query_ppu_pf_other_int_dfx_cmd *)desc.data; 1712 *vf_id = le16_to_cpu(req->over_8bd_no_fe_vf_id); 1713 *q_id = le16_to_cpu(req->over_8bd_no_fe_qid); 1714 1715 return 0; 1716 } 1717 1718 /* hclge_handle_over_8bd_err: handle MSI-X error named over_8bd_nfe_err 1719 * @hdev: pointer to struct hclge_dev 1720 * @reset_requests: reset level that we need to trigger later 1721 * 1722 * over_8bd_nfe_err is a special MSI-X because it may caused by a VF, in 1723 * that case, we need to trigger VF reset. Otherwise, a PF reset is needed. 1724 */ 1725 static void hclge_handle_over_8bd_err(struct hclge_dev *hdev, 1726 unsigned long *reset_requests) 1727 { 1728 struct device *dev = &hdev->pdev->dev; 1729 u16 vf_id; 1730 u16 q_id; 1731 int ret; 1732 1733 ret = hclge_query_over_8bd_err_info(hdev, &vf_id, &q_id); 1734 if (ret) { 1735 dev_err(dev, "fail(%d) to query over_8bd_no_fe info\n", 1736 ret); 1737 return; 1738 } 1739 1740 dev_warn(dev, "PPU_PF_ABNORMAL_INT_ST over_8bd_no_fe found, vf_id(%d), queue_id(%d)\n", 1741 vf_id, q_id); 1742 1743 if (vf_id) { 1744 if (vf_id >= hdev->num_alloc_vport) { 1745 dev_err(dev, "invalid vf id(%d)\n", vf_id); 1746 return; 1747 } 1748 1749 /* If we need to trigger other reset whose level is higher 1750 * than HNAE3_VF_FUNC_RESET, no need to trigger a VF reset 1751 * here. 1752 */ 1753 if (*reset_requests != 0) 1754 return; 1755 1756 ret = hclge_inform_reset_assert_to_vf(&hdev->vport[vf_id]); 1757 if (ret) 1758 dev_warn(dev, "inform reset to vf(%d) failed %d!\n", 1759 hdev->vport->vport_id, ret); 1760 } else { 1761 set_bit(HNAE3_FUNC_RESET, reset_requests); 1762 } 1763 } 1764 1765 /* hclge_handle_mpf_msix_error: handle all main PF MSI-X errors 1766 * @hdev: pointer to struct hclge_dev 1767 * @desc: descriptor for describing the command 1768 * @mpf_bd_num: number of extended command structures 1769 * @reset_requests: record of the reset level that we need 1770 * 1771 * This function handles all the main PF MSI-X errors in the hw register/s 1772 * using command. 1773 */ 1774 static int hclge_handle_mpf_msix_error(struct hclge_dev *hdev, 1775 struct hclge_desc *desc, 1776 int mpf_bd_num, 1777 unsigned long *reset_requests) 1778 { 1779 struct device *dev = &hdev->pdev->dev; 1780 __le32 *desc_data; 1781 u32 status; 1782 int ret; 1783 /* query all main PF MSIx errors */ 1784 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT, 1785 true); 1786 ret = hclge_cmd_send(&hdev->hw, &desc[0], mpf_bd_num); 1787 if (ret) { 1788 dev_err(dev, "query all mpf msix int cmd failed (%d)\n", ret); 1789 return ret; 1790 } 1791 1792 /* log MAC errors */ 1793 desc_data = (__le32 *)&desc[1]; 1794 status = le32_to_cpu(*desc_data); 1795 if (status) 1796 hclge_log_error(dev, "MAC_AFIFO_TNL_INT_R", 1797 &hclge_mac_afifo_tnl_int[0], status, 1798 reset_requests); 1799 1800 /* log PPU(RCB) MPF errors */ 1801 desc_data = (__le32 *)&desc[5]; 1802 status = le32_to_cpu(*(desc_data + 2)) & 1803 HCLGE_PPU_MPF_INT_ST2_MSIX_MASK; 1804 if (status) 1805 dev_warn(dev, "PPU_MPF_ABNORMAL_INT_ST2 rx_q_search_miss found [dfx status=0x%x\n]", 1806 status); 1807 1808 /* clear all main PF MSIx errors */ 1809 ret = hclge_clear_hw_msix_error(hdev, desc, true, mpf_bd_num); 1810 if (ret) 1811 dev_err(dev, "clear all mpf msix int cmd failed (%d)\n", ret); 1812 1813 return ret; 1814 } 1815 1816 /* hclge_handle_pf_msix_error: handle all PF MSI-X errors 1817 * @hdev: pointer to struct hclge_dev 1818 * @desc: descriptor for describing the command 1819 * @mpf_bd_num: number of extended command structures 1820 * @reset_requests: record of the reset level that we need 1821 * 1822 * This function handles all the PF MSI-X errors in the hw register/s using 1823 * command. 1824 */ 1825 static int hclge_handle_pf_msix_error(struct hclge_dev *hdev, 1826 struct hclge_desc *desc, 1827 int pf_bd_num, 1828 unsigned long *reset_requests) 1829 { 1830 struct device *dev = &hdev->pdev->dev; 1831 __le32 *desc_data; 1832 u32 status; 1833 int ret; 1834 1835 /* query all PF MSIx errors */ 1836 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT, 1837 true); 1838 ret = hclge_cmd_send(&hdev->hw, &desc[0], pf_bd_num); 1839 if (ret) { 1840 dev_err(dev, "query all pf msix int cmd failed (%d)\n", ret); 1841 return ret; 1842 } 1843 1844 /* log SSU PF errors */ 1845 status = le32_to_cpu(desc[0].data[0]) & HCLGE_SSU_PORT_INT_MSIX_MASK; 1846 if (status) 1847 hclge_log_error(dev, "SSU_PORT_BASED_ERR_INT", 1848 &hclge_ssu_port_based_pf_int[0], 1849 status, reset_requests); 1850 1851 /* read and log PPP PF errors */ 1852 desc_data = (__le32 *)&desc[2]; 1853 status = le32_to_cpu(*desc_data); 1854 if (status) 1855 hclge_log_error(dev, "PPP_PF_ABNORMAL_INT_ST0", 1856 &hclge_ppp_pf_abnormal_int[0], 1857 status, reset_requests); 1858 1859 /* log PPU(RCB) PF errors */ 1860 desc_data = (__le32 *)&desc[3]; 1861 status = le32_to_cpu(*desc_data) & HCLGE_PPU_PF_INT_MSIX_MASK; 1862 if (status) 1863 hclge_log_error(dev, "PPU_PF_ABNORMAL_INT_ST", 1864 &hclge_ppu_pf_abnormal_int[0], 1865 status, reset_requests); 1866 1867 status = le32_to_cpu(*desc_data) & HCLGE_PPU_PF_OVER_8BD_ERR_MASK; 1868 if (status) 1869 hclge_handle_over_8bd_err(hdev, reset_requests); 1870 1871 /* clear all PF MSIx errors */ 1872 ret = hclge_clear_hw_msix_error(hdev, desc, false, pf_bd_num); 1873 if (ret) 1874 dev_err(dev, "clear all pf msix int cmd failed (%d)\n", ret); 1875 1876 return ret; 1877 } 1878 1879 static int hclge_handle_all_hw_msix_error(struct hclge_dev *hdev, 1880 unsigned long *reset_requests) 1881 { 1882 struct hclge_mac_tnl_stats mac_tnl_stats; 1883 struct device *dev = &hdev->pdev->dev; 1884 u32 mpf_bd_num, pf_bd_num, bd_num; 1885 struct hclge_desc *desc; 1886 u32 status; 1887 int ret; 1888 1889 /* query the number of bds for the MSIx int status */ 1890 ret = hclge_query_bd_num(hdev, false, &mpf_bd_num, &pf_bd_num); 1891 if (ret) 1892 goto out; 1893 1894 bd_num = max_t(u32, mpf_bd_num, pf_bd_num); 1895 desc = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL); 1896 if (!desc) { 1897 ret = -ENOMEM; 1898 goto out; 1899 } 1900 1901 ret = hclge_handle_mpf_msix_error(hdev, desc, mpf_bd_num, 1902 reset_requests); 1903 if (ret) 1904 goto msi_error; 1905 1906 memset(desc, 0, bd_num * sizeof(struct hclge_desc)); 1907 ret = hclge_handle_pf_msix_error(hdev, desc, pf_bd_num, reset_requests); 1908 if (ret) 1909 goto msi_error; 1910 1911 /* query and clear mac tnl interruptions */ 1912 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_MAC_TNL_INT, 1913 true); 1914 ret = hclge_cmd_send(&hdev->hw, &desc[0], 1); 1915 if (ret) { 1916 dev_err(dev, "query mac tnl int cmd failed (%d)\n", ret); 1917 goto msi_error; 1918 } 1919 1920 status = le32_to_cpu(desc->data[0]); 1921 if (status) { 1922 /* When mac tnl interrupt occurs, we record current time and 1923 * register status here in a fifo, then clear the status. So 1924 * that if link status changes suddenly at some time, we can 1925 * query them by debugfs. 1926 */ 1927 mac_tnl_stats.time = local_clock(); 1928 mac_tnl_stats.status = status; 1929 kfifo_put(&hdev->mac_tnl_log, mac_tnl_stats); 1930 ret = hclge_clear_mac_tnl_int(hdev); 1931 if (ret) 1932 dev_err(dev, "clear mac tnl int failed (%d)\n", ret); 1933 } 1934 1935 msi_error: 1936 kfree(desc); 1937 out: 1938 return ret; 1939 } 1940 1941 int hclge_handle_hw_msix_error(struct hclge_dev *hdev, 1942 unsigned long *reset_requests) 1943 { 1944 struct device *dev = &hdev->pdev->dev; 1945 1946 if (!test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state)) { 1947 dev_err(dev, 1948 "Can't handle - MSIx error reported during dev init\n"); 1949 return 0; 1950 } 1951 1952 return hclge_handle_all_hw_msix_error(hdev, reset_requests); 1953 } 1954 1955 void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev) 1956 { 1957 #define HCLGE_DESC_NO_DATA_LEN 8 1958 1959 struct hclge_dev *hdev = ae_dev->priv; 1960 struct device *dev = &hdev->pdev->dev; 1961 u32 mpf_bd_num, pf_bd_num, bd_num; 1962 struct hclge_desc *desc; 1963 u32 status; 1964 int ret; 1965 1966 ae_dev->hw_err_reset_req = 0; 1967 status = hclge_read_dev(&hdev->hw, HCLGE_RAS_PF_OTHER_INT_STS_REG); 1968 1969 /* query the number of bds for the MSIx int status */ 1970 ret = hclge_query_bd_num(hdev, false, &mpf_bd_num, &pf_bd_num); 1971 if (ret) 1972 return; 1973 1974 bd_num = max_t(u32, mpf_bd_num, pf_bd_num); 1975 desc = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL); 1976 if (!desc) 1977 return; 1978 1979 /* Clear HNS hw errors reported through msix */ 1980 memset(&desc[0].data[0], 0xFF, mpf_bd_num * sizeof(struct hclge_desc) - 1981 HCLGE_DESC_NO_DATA_LEN); 1982 ret = hclge_clear_hw_msix_error(hdev, desc, true, mpf_bd_num); 1983 if (ret) { 1984 dev_err(dev, "fail(%d) to clear mpf msix int during init\n", 1985 ret); 1986 goto msi_error; 1987 } 1988 1989 memset(&desc[0].data[0], 0xFF, pf_bd_num * sizeof(struct hclge_desc) - 1990 HCLGE_DESC_NO_DATA_LEN); 1991 ret = hclge_clear_hw_msix_error(hdev, desc, false, pf_bd_num); 1992 if (ret) { 1993 dev_err(dev, "fail(%d) to clear pf msix int during init\n", 1994 ret); 1995 goto msi_error; 1996 } 1997 1998 /* Handle Non-fatal HNS RAS errors */ 1999 if (status & HCLGE_RAS_REG_NFE_MASK) { 2000 dev_warn(dev, "HNS hw error(RAS) identified during init\n"); 2001 hclge_handle_all_ras_errors(hdev); 2002 } 2003 2004 msi_error: 2005 kfree(desc); 2006 } 2007