1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) 2018-2019 Hisilicon Limited. */ 3 4 #ifndef __HCLGE_DEBUGFS_H 5 #define __HCLGE_DEBUGFS_H 6 7 #define HCLGE_DBG_BUF_LEN 256 8 #define HCLGE_DBG_MNG_TBL_MAX 64 9 10 #define HCLGE_DBG_MNG_VLAN_MASK_B BIT(0) 11 #define HCLGE_DBG_MNG_MAC_MASK_B BIT(1) 12 #define HCLGE_DBG_MNG_ETHER_MASK_B BIT(2) 13 #define HCLGE_DBG_MNG_E_TYPE_B BIT(11) 14 #define HCLGE_DBG_MNG_DROP_B BIT(13) 15 #define HCLGE_DBG_MNG_VLAN_TAG 0x0FFF 16 #define HCLGE_DBG_MNG_PF_ID 0x0007 17 #define HCLGE_DBG_MNG_VF_ID 0x00FF 18 19 /* Get DFX BD number offset */ 20 #define HCLGE_DBG_DFX_BIOS_OFFSET 1 21 #define HCLGE_DBG_DFX_SSU_0_OFFSET 2 22 #define HCLGE_DBG_DFX_SSU_1_OFFSET 3 23 #define HCLGE_DBG_DFX_IGU_OFFSET 4 24 #define HCLGE_DBG_DFX_RPU_0_OFFSET 5 25 26 #define HCLGE_DBG_DFX_RPU_1_OFFSET 6 27 #define HCLGE_DBG_DFX_NCSI_OFFSET 7 28 #define HCLGE_DBG_DFX_RTC_OFFSET 8 29 #define HCLGE_DBG_DFX_PPP_OFFSET 9 30 #define HCLGE_DBG_DFX_RCB_OFFSET 10 31 #define HCLGE_DBG_DFX_TQP_OFFSET 11 32 33 #define HCLGE_DBG_DFX_SSU_2_OFFSET 12 34 35 #pragma pack(1) 36 37 struct hclge_qos_pri_map_cmd { 38 u8 pri0_tc : 4, 39 pri1_tc : 4; 40 u8 pri2_tc : 4, 41 pri3_tc : 4; 42 u8 pri4_tc : 4, 43 pri5_tc : 4; 44 u8 pri6_tc : 4, 45 pri7_tc : 4; 46 u8 vlan_pri : 4, 47 rev : 4; 48 }; 49 50 struct hclge_dbg_bitmap_cmd { 51 union { 52 u8 bitmap; 53 struct { 54 u8 bit0 : 1, 55 bit1 : 1, 56 bit2 : 1, 57 bit3 : 1, 58 bit4 : 1, 59 bit5 : 1, 60 bit6 : 1, 61 bit7 : 1; 62 }; 63 }; 64 }; 65 66 struct hclge_dbg_dfx_message { 67 int flag; 68 char message[60]; 69 }; 70 71 #pragma pack() 72 73 static struct hclge_dbg_dfx_message hclge_dbg_bios_common_reg[] = { 74 {false, "Reserved"}, 75 {true, "BP_CPU_STATE"}, 76 {true, "DFX_MSIX_INFO_NIC_0"}, 77 {true, "DFX_MSIX_INFO_NIC_1"}, 78 {true, "DFX_MSIX_INFO_NIC_2"}, 79 {true, "DFX_MSIX_INFO_NIC_3"}, 80 81 {true, "DFX_MSIX_INFO_ROC_0"}, 82 {true, "DFX_MSIX_INFO_ROC_1"}, 83 {true, "DFX_MSIX_INFO_ROC_2"}, 84 {true, "DFX_MSIX_INFO_ROC_3"}, 85 {false, "Reserved"}, 86 {false, "Reserved"}, 87 }; 88 89 static struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_0[] = { 90 {false, "Reserved"}, 91 {true, "SSU_ETS_PORT_STATUS"}, 92 {true, "SSU_ETS_TCG_STATUS"}, 93 {false, "Reserved"}, 94 {false, "Reserved"}, 95 {true, "SSU_BP_STATUS_0"}, 96 97 {true, "SSU_BP_STATUS_1"}, 98 {true, "SSU_BP_STATUS_2"}, 99 {true, "SSU_BP_STATUS_3"}, 100 {true, "SSU_BP_STATUS_4"}, 101 {true, "SSU_BP_STATUS_5"}, 102 {true, "SSU_MAC_TX_PFC_IND"}, 103 104 {true, "MAC_SSU_RX_PFC_IND"}, 105 {true, "BTMP_AGEING_ST_B0"}, 106 {true, "BTMP_AGEING_ST_B1"}, 107 {true, "BTMP_AGEING_ST_B2"}, 108 {false, "Reserved"}, 109 {false, "Reserved"}, 110 111 {true, "FULL_DROP_NUM"}, 112 {true, "PART_DROP_NUM"}, 113 {true, "PPP_KEY_DROP_NUM"}, 114 {true, "PPP_RLT_DROP_NUM"}, 115 {true, "LO_PRI_UNICAST_RLT_DROP_NUM"}, 116 {true, "HI_PRI_MULTICAST_RLT_DROP_NUM"}, 117 118 {true, "LO_PRI_MULTICAST_RLT_DROP_NUM"}, 119 {true, "NCSI_PACKET_CURR_BUFFER_CNT"}, 120 {true, "BTMP_AGEING_RLS_CNT_BANK0"}, 121 {true, "BTMP_AGEING_RLS_CNT_BANK1"}, 122 {true, "BTMP_AGEING_RLS_CNT_BANK2"}, 123 {true, "SSU_MB_RD_RLT_DROP_CNT"}, 124 125 {true, "SSU_PPP_MAC_KEY_NUM_L"}, 126 {true, "SSU_PPP_MAC_KEY_NUM_H"}, 127 {true, "SSU_PPP_HOST_KEY_NUM_L"}, 128 {true, "SSU_PPP_HOST_KEY_NUM_H"}, 129 {true, "PPP_SSU_MAC_RLT_NUM_L"}, 130 {true, "PPP_SSU_MAC_RLT_NUM_H"}, 131 132 {true, "PPP_SSU_HOST_RLT_NUM_L"}, 133 {true, "PPP_SSU_HOST_RLT_NUM_H"}, 134 {true, "NCSI_RX_PACKET_IN_CNT_L"}, 135 {true, "NCSI_RX_PACKET_IN_CNT_H"}, 136 {true, "NCSI_TX_PACKET_OUT_CNT_L"}, 137 {true, "NCSI_TX_PACKET_OUT_CNT_H"}, 138 139 {true, "SSU_KEY_DROP_NUM"}, 140 {true, "MB_UNCOPY_NUM"}, 141 {true, "RX_OQ_DROP_PKT_CNT"}, 142 {true, "TX_OQ_DROP_PKT_CNT"}, 143 {true, "BANK_UNBALANCE_DROP_CNT"}, 144 {true, "BANK_UNBALANCE_RX_DROP_CNT"}, 145 146 {true, "NIC_L2_ERR_DROP_PKT_CNT"}, 147 {true, "ROC_L2_ERR_DROP_PKT_CNT"}, 148 {true, "NIC_L2_ERR_DROP_PKT_CNT_RX"}, 149 {true, "ROC_L2_ERR_DROP_PKT_CNT_RX"}, 150 {true, "RX_OQ_GLB_DROP_PKT_CNT"}, 151 {false, "Reserved"}, 152 153 {true, "LO_PRI_UNICAST_CUR_CNT"}, 154 {true, "HI_PRI_MULTICAST_CUR_CNT"}, 155 {true, "LO_PRI_MULTICAST_CUR_CNT"}, 156 {false, "Reserved"}, 157 {false, "Reserved"}, 158 {false, "Reserved"}, 159 }; 160 161 static struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_1[] = { 162 {true, "prt_id"}, 163 {true, "PACKET_TC_CURR_BUFFER_CNT_0"}, 164 {true, "PACKET_TC_CURR_BUFFER_CNT_1"}, 165 {true, "PACKET_TC_CURR_BUFFER_CNT_2"}, 166 {true, "PACKET_TC_CURR_BUFFER_CNT_3"}, 167 {true, "PACKET_TC_CURR_BUFFER_CNT_4"}, 168 169 {true, "PACKET_TC_CURR_BUFFER_CNT_5"}, 170 {true, "PACKET_TC_CURR_BUFFER_CNT_6"}, 171 {true, "PACKET_TC_CURR_BUFFER_CNT_7"}, 172 {true, "PACKET_CURR_BUFFER_CNT"}, 173 {false, "Reserved"}, 174 {false, "Reserved"}, 175 176 {true, "RX_PACKET_IN_CNT_L"}, 177 {true, "RX_PACKET_IN_CNT_H"}, 178 {true, "RX_PACKET_OUT_CNT_L"}, 179 {true, "RX_PACKET_OUT_CNT_H"}, 180 {true, "TX_PACKET_IN_CNT_L"}, 181 {true, "TX_PACKET_IN_CNT_H"}, 182 183 {true, "TX_PACKET_OUT_CNT_L"}, 184 {true, "TX_PACKET_OUT_CNT_H"}, 185 {true, "ROC_RX_PACKET_IN_CNT_L"}, 186 {true, "ROC_RX_PACKET_IN_CNT_H"}, 187 {true, "ROC_TX_PACKET_OUT_CNT_L"}, 188 {true, "ROC_TX_PACKET_OUT_CNT_H"}, 189 190 {true, "RX_PACKET_TC_IN_CNT_0_L"}, 191 {true, "RX_PACKET_TC_IN_CNT_0_H"}, 192 {true, "RX_PACKET_TC_IN_CNT_1_L"}, 193 {true, "RX_PACKET_TC_IN_CNT_1_H"}, 194 {true, "RX_PACKET_TC_IN_CNT_2_L"}, 195 {true, "RX_PACKET_TC_IN_CNT_2_H"}, 196 197 {true, "RX_PACKET_TC_IN_CNT_3_L"}, 198 {true, "RX_PACKET_TC_IN_CNT_3_H"}, 199 {true, "RX_PACKET_TC_IN_CNT_4_L"}, 200 {true, "RX_PACKET_TC_IN_CNT_4_H"}, 201 {true, "RX_PACKET_TC_IN_CNT_5_L"}, 202 {true, "RX_PACKET_TC_IN_CNT_5_H"}, 203 204 {true, "RX_PACKET_TC_IN_CNT_6_L"}, 205 {true, "RX_PACKET_TC_IN_CNT_6_H"}, 206 {true, "RX_PACKET_TC_IN_CNT_7_L"}, 207 {true, "RX_PACKET_TC_IN_CNT_7_H"}, 208 {true, "RX_PACKET_TC_OUT_CNT_0_L"}, 209 {true, "RX_PACKET_TC_OUT_CNT_0_H"}, 210 211 {true, "RX_PACKET_TC_OUT_CNT_1_L"}, 212 {true, "RX_PACKET_TC_OUT_CNT_1_H"}, 213 {true, "RX_PACKET_TC_OUT_CNT_2_L"}, 214 {true, "RX_PACKET_TC_OUT_CNT_2_H"}, 215 {true, "RX_PACKET_TC_OUT_CNT_3_L"}, 216 {true, "RX_PACKET_TC_OUT_CNT_3_H"}, 217 218 {true, "RX_PACKET_TC_OUT_CNT_4_L"}, 219 {true, "RX_PACKET_TC_OUT_CNT_4_H"}, 220 {true, "RX_PACKET_TC_OUT_CNT_5_L"}, 221 {true, "RX_PACKET_TC_OUT_CNT_5_H"}, 222 {true, "RX_PACKET_TC_OUT_CNT_6_L"}, 223 {true, "RX_PACKET_TC_OUT_CNT_6_H"}, 224 225 {true, "RX_PACKET_TC_OUT_CNT_7_L"}, 226 {true, "RX_PACKET_TC_OUT_CNT_7_H"}, 227 {true, "TX_PACKET_TC_IN_CNT_0_L"}, 228 {true, "TX_PACKET_TC_IN_CNT_0_H"}, 229 {true, "TX_PACKET_TC_IN_CNT_1_L"}, 230 {true, "TX_PACKET_TC_IN_CNT_1_H"}, 231 232 {true, "TX_PACKET_TC_IN_CNT_2_L"}, 233 {true, "TX_PACKET_TC_IN_CNT_2_H"}, 234 {true, "TX_PACKET_TC_IN_CNT_3_L"}, 235 {true, "TX_PACKET_TC_IN_CNT_3_H"}, 236 {true, "TX_PACKET_TC_IN_CNT_4_L"}, 237 {true, "TX_PACKET_TC_IN_CNT_4_H"}, 238 239 {true, "TX_PACKET_TC_IN_CNT_5_L"}, 240 {true, "TX_PACKET_TC_IN_CNT_5_H"}, 241 {true, "TX_PACKET_TC_IN_CNT_6_L"}, 242 {true, "TX_PACKET_TC_IN_CNT_6_H"}, 243 {true, "TX_PACKET_TC_IN_CNT_7_L"}, 244 {true, "TX_PACKET_TC_IN_CNT_7_H"}, 245 246 {true, "TX_PACKET_TC_OUT_CNT_0_L"}, 247 {true, "TX_PACKET_TC_OUT_CNT_0_H"}, 248 {true, "TX_PACKET_TC_OUT_CNT_1_L"}, 249 {true, "TX_PACKET_TC_OUT_CNT_1_H"}, 250 {true, "TX_PACKET_TC_OUT_CNT_2_L"}, 251 {true, "TX_PACKET_TC_OUT_CNT_2_H"}, 252 253 {true, "TX_PACKET_TC_OUT_CNT_3_L"}, 254 {true, "TX_PACKET_TC_OUT_CNT_3_H"}, 255 {true, "TX_PACKET_TC_OUT_CNT_4_L"}, 256 {true, "TX_PACKET_TC_OUT_CNT_4_H"}, 257 {true, "TX_PACKET_TC_OUT_CNT_5_L"}, 258 {true, "TX_PACKET_TC_OUT_CNT_5_H"}, 259 260 {true, "TX_PACKET_TC_OUT_CNT_6_L"}, 261 {true, "TX_PACKET_TC_OUT_CNT_6_H"}, 262 {true, "TX_PACKET_TC_OUT_CNT_7_L"}, 263 {true, "TX_PACKET_TC_OUT_CNT_7_H"}, 264 {false, "Reserved"}, 265 {false, "Reserved"}, 266 }; 267 268 static struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_2[] = { 269 {true, "OQ_INDEX"}, 270 {true, "QUEUE_CNT"}, 271 {false, "Reserved"}, 272 {false, "Reserved"}, 273 {false, "Reserved"}, 274 {false, "Reserved"}, 275 }; 276 277 static struct hclge_dbg_dfx_message hclge_dbg_igu_egu_reg[] = { 278 {true, "prt_id"}, 279 {true, "IGU_RX_ERR_PKT"}, 280 {true, "IGU_RX_NO_SOF_PKT"}, 281 {true, "EGU_TX_1588_SHORT_PKT"}, 282 {true, "EGU_TX_1588_PKT"}, 283 {true, "EGU_TX_ERR_PKT"}, 284 285 {true, "IGU_RX_OUT_L2_PKT"}, 286 {true, "IGU_RX_OUT_L3_PKT"}, 287 {true, "IGU_RX_OUT_L4_PKT"}, 288 {true, "IGU_RX_IN_L2_PKT"}, 289 {true, "IGU_RX_IN_L3_PKT"}, 290 {true, "IGU_RX_IN_L4_PKT"}, 291 292 {true, "IGU_RX_EL3E_PKT"}, 293 {true, "IGU_RX_EL4E_PKT"}, 294 {true, "IGU_RX_L3E_PKT"}, 295 {true, "IGU_RX_L4E_PKT"}, 296 {true, "IGU_RX_ROCEE_PKT"}, 297 {true, "IGU_RX_OUT_UDP0_PKT"}, 298 299 {true, "IGU_RX_IN_UDP0_PKT"}, 300 {false, "Reserved"}, 301 {false, "Reserved"}, 302 {false, "Reserved"}, 303 {false, "Reserved"}, 304 {false, "Reserved"}, 305 306 {true, "IGU_RX_OVERSIZE_PKT_L"}, 307 {true, "IGU_RX_OVERSIZE_PKT_H"}, 308 {true, "IGU_RX_UNDERSIZE_PKT_L"}, 309 {true, "IGU_RX_UNDERSIZE_PKT_H"}, 310 {true, "IGU_RX_OUT_ALL_PKT_L"}, 311 {true, "IGU_RX_OUT_ALL_PKT_H"}, 312 313 {true, "IGU_TX_OUT_ALL_PKT_L"}, 314 {true, "IGU_TX_OUT_ALL_PKT_H"}, 315 {true, "IGU_RX_UNI_PKT_L"}, 316 {true, "IGU_RX_UNI_PKT_H"}, 317 {true, "IGU_RX_MULTI_PKT_L"}, 318 {true, "IGU_RX_MULTI_PKT_H"}, 319 320 {true, "IGU_RX_BROAD_PKT_L"}, 321 {true, "IGU_RX_BROAD_PKT_H"}, 322 {true, "EGU_TX_OUT_ALL_PKT_L"}, 323 {true, "EGU_TX_OUT_ALL_PKT_H"}, 324 {true, "EGU_TX_UNI_PKT_L"}, 325 {true, "EGU_TX_UNI_PKT_H"}, 326 327 {true, "EGU_TX_MULTI_PKT_L"}, 328 {true, "EGU_TX_MULTI_PKT_H"}, 329 {true, "EGU_TX_BROAD_PKT_L"}, 330 {true, "EGU_TX_BROAD_PKT_H"}, 331 {true, "IGU_TX_KEY_NUM_L"}, 332 {true, "IGU_TX_KEY_NUM_H"}, 333 334 {true, "IGU_RX_NON_TUN_PKT_L"}, 335 {true, "IGU_RX_NON_TUN_PKT_H"}, 336 {true, "IGU_RX_TUN_PKT_L"}, 337 {true, "IGU_RX_TUN_PKT_H"}, 338 {false, "Reserved"}, 339 {false, "Reserved"}, 340 }; 341 342 static struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_0[] = { 343 {true, "tc_queue_num"}, 344 {true, "FSM_DFX_ST0"}, 345 {true, "FSM_DFX_ST1"}, 346 {true, "RPU_RX_PKT_DROP_CNT"}, 347 {true, "BUF_WAIT_TIMEOUT"}, 348 {true, "BUF_WAIT_TIMEOUT_QID"}, 349 }; 350 351 static struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_1[] = { 352 {false, "Reserved"}, 353 {true, "FIFO_DFX_ST0"}, 354 {true, "FIFO_DFX_ST1"}, 355 {true, "FIFO_DFX_ST2"}, 356 {true, "FIFO_DFX_ST3"}, 357 {true, "FIFO_DFX_ST4"}, 358 359 {true, "FIFO_DFX_ST5"}, 360 {false, "Reserved"}, 361 {false, "Reserved"}, 362 {false, "Reserved"}, 363 {false, "Reserved"}, 364 {false, "Reserved"}, 365 }; 366 367 static struct hclge_dbg_dfx_message hclge_dbg_ncsi_reg[] = { 368 {false, "Reserved"}, 369 {true, "NCSI_EGU_TX_FIFO_STS"}, 370 {true, "NCSI_PAUSE_STATUS"}, 371 {true, "NCSI_RX_CTRL_DMAC_ERR_CNT"}, 372 {true, "NCSI_RX_CTRL_SMAC_ERR_CNT"}, 373 {true, "NCSI_RX_CTRL_CKS_ERR_CNT"}, 374 375 {true, "NCSI_RX_CTRL_PKT_CNT"}, 376 {true, "NCSI_RX_PT_DMAC_ERR_CNT"}, 377 {true, "NCSI_RX_PT_SMAC_ERR_CNT"}, 378 {true, "NCSI_RX_PT_PKT_CNT"}, 379 {true, "NCSI_RX_FCS_ERR_CNT"}, 380 {true, "NCSI_TX_CTRL_DMAC_ERR_CNT"}, 381 382 {true, "NCSI_TX_CTRL_SMAC_ERR_CNT"}, 383 {true, "NCSI_TX_CTRL_PKT_CNT"}, 384 {true, "NCSI_TX_PT_DMAC_ERR_CNT"}, 385 {true, "NCSI_TX_PT_SMAC_ERR_CNT"}, 386 {true, "NCSI_TX_PT_PKT_CNT"}, 387 {true, "NCSI_TX_PT_PKT_TRUNC_CNT"}, 388 389 {true, "NCSI_TX_PT_PKT_ERR_CNT"}, 390 {true, "NCSI_TX_CTRL_PKT_ERR_CNT"}, 391 {true, "NCSI_RX_CTRL_PKT_TRUNC_CNT"}, 392 {true, "NCSI_RX_CTRL_PKT_CFLIT_CNT"}, 393 {false, "Reserved"}, 394 {false, "Reserved"}, 395 396 {true, "NCSI_MAC_RX_OCTETS_OK"}, 397 {true, "NCSI_MAC_RX_OCTETS_BAD"}, 398 {true, "NCSI_MAC_RX_UC_PKTS"}, 399 {true, "NCSI_MAC_RX_MC_PKTS"}, 400 {true, "NCSI_MAC_RX_BC_PKTS"}, 401 {true, "NCSI_MAC_RX_PKTS_64OCTETS"}, 402 403 {true, "NCSI_MAC_RX_PKTS_65TO127OCTETS"}, 404 {true, "NCSI_MAC_RX_PKTS_128TO255OCTETS"}, 405 {true, "NCSI_MAC_RX_PKTS_255TO511OCTETS"}, 406 {true, "NCSI_MAC_RX_PKTS_512TO1023OCTETS"}, 407 {true, "NCSI_MAC_RX_PKTS_1024TO1518OCTETS"}, 408 {true, "NCSI_MAC_RX_PKTS_1519TOMAXOCTETS"}, 409 410 {true, "NCSI_MAC_RX_FCS_ERRORS"}, 411 {true, "NCSI_MAC_RX_LONG_ERRORS"}, 412 {true, "NCSI_MAC_RX_JABBER_ERRORS"}, 413 {true, "NCSI_MAC_RX_RUNT_ERR_CNT"}, 414 {true, "NCSI_MAC_RX_SHORT_ERR_CNT"}, 415 {true, "NCSI_MAC_RX_FILT_PKT_CNT"}, 416 417 {true, "NCSI_MAC_RX_OCTETS_TOTAL_FILT"}, 418 {true, "NCSI_MAC_TX_OCTETS_OK"}, 419 {true, "NCSI_MAC_TX_OCTETS_BAD"}, 420 {true, "NCSI_MAC_TX_UC_PKTS"}, 421 {true, "NCSI_MAC_TX_MC_PKTS"}, 422 {true, "NCSI_MAC_TX_BC_PKTS"}, 423 424 {true, "NCSI_MAC_TX_PKTS_64OCTETS"}, 425 {true, "NCSI_MAC_TX_PKTS_65TO127OCTETS"}, 426 {true, "NCSI_MAC_TX_PKTS_128TO255OCTETS"}, 427 {true, "NCSI_MAC_TX_PKTS_256TO511OCTETS"}, 428 {true, "NCSI_MAC_TX_PKTS_512TO1023OCTETS"}, 429 {true, "NCSI_MAC_TX_PKTS_1024TO1518OCTETS"}, 430 431 {true, "NCSI_MAC_TX_PKTS_1519TOMAXOCTETS"}, 432 {true, "NCSI_MAC_TX_UNDERRUN"}, 433 {true, "NCSI_MAC_TX_CRC_ERROR"}, 434 {true, "NCSI_MAC_TX_PAUSE_FRAMES"}, 435 {true, "NCSI_MAC_RX_PAD_PKTS"}, 436 {true, "NCSI_MAC_RX_PAUSE_FRAMES"}, 437 }; 438 439 static struct hclge_dbg_dfx_message hclge_dbg_rtc_reg[] = { 440 {false, "Reserved"}, 441 {true, "LGE_IGU_AFIFO_DFX_0"}, 442 {true, "LGE_IGU_AFIFO_DFX_1"}, 443 {true, "LGE_IGU_AFIFO_DFX_2"}, 444 {true, "LGE_IGU_AFIFO_DFX_3"}, 445 {true, "LGE_IGU_AFIFO_DFX_4"}, 446 447 {true, "LGE_IGU_AFIFO_DFX_5"}, 448 {true, "LGE_IGU_AFIFO_DFX_6"}, 449 {true, "LGE_IGU_AFIFO_DFX_7"}, 450 {true, "LGE_EGU_AFIFO_DFX_0"}, 451 {true, "LGE_EGU_AFIFO_DFX_1"}, 452 {true, "LGE_EGU_AFIFO_DFX_2"}, 453 454 {true, "LGE_EGU_AFIFO_DFX_3"}, 455 {true, "LGE_EGU_AFIFO_DFX_4"}, 456 {true, "LGE_EGU_AFIFO_DFX_5"}, 457 {true, "LGE_EGU_AFIFO_DFX_6"}, 458 {true, "LGE_EGU_AFIFO_DFX_7"}, 459 {true, "CGE_IGU_AFIFO_DFX_0"}, 460 461 {true, "CGE_IGU_AFIFO_DFX_1"}, 462 {true, "CGE_EGU_AFIFO_DFX_0"}, 463 {true, "CGE_EGU_AFIFO_DFX_1"}, 464 {false, "Reserved"}, 465 {false, "Reserved"}, 466 {false, "Reserved"}, 467 }; 468 469 static struct hclge_dbg_dfx_message hclge_dbg_ppp_reg[] = { 470 {false, "Reserved"}, 471 {true, "DROP_FROM_PRT_PKT_CNT"}, 472 {true, "DROP_FROM_HOST_PKT_CNT"}, 473 {true, "DROP_TX_VLAN_PROC_CNT"}, 474 {true, "DROP_MNG_CNT"}, 475 {true, "DROP_FD_CNT"}, 476 477 {true, "DROP_NO_DST_CNT"}, 478 {true, "DROP_MC_MBID_FULL_CNT"}, 479 {true, "DROP_SC_FILTERED"}, 480 {true, "PPP_MC_DROP_PKT_CNT"}, 481 {true, "DROP_PT_CNT"}, 482 {true, "DROP_MAC_ANTI_SPOOF_CNT"}, 483 484 {true, "DROP_IG_VFV_CNT"}, 485 {true, "DROP_IG_PRTV_CNT"}, 486 {true, "DROP_CNM_PFC_PAUSE_CNT"}, 487 {true, "DROP_TORUS_TC_CNT"}, 488 {true, "DROP_TORUS_LPBK_CNT"}, 489 {true, "PPP_HFS_STS"}, 490 491 {true, "PPP_MC_RSLT_STS"}, 492 {true, "PPP_P3U_STS"}, 493 {true, "PPP_RSLT_DESCR_STS"}, 494 {true, "PPP_UMV_STS_0"}, 495 {true, "PPP_UMV_STS_1"}, 496 {true, "PPP_VFV_STS"}, 497 498 {true, "PPP_GRO_KEY_CNT"}, 499 {true, "PPP_GRO_INFO_CNT"}, 500 {true, "PPP_GRO_DROP_CNT"}, 501 {true, "PPP_GRO_OUT_CNT"}, 502 {true, "PPP_GRO_KEY_MATCH_DATA_CNT"}, 503 {true, "PPP_GRO_KEY_MATCH_TCAM_CNT"}, 504 505 {true, "PPP_GRO_INFO_MATCH_CNT"}, 506 {true, "PPP_GRO_FREE_ENTRY_CNT"}, 507 {true, "PPP_GRO_INNER_DFX_SIGNAL"}, 508 {false, "Reserved"}, 509 {false, "Reserved"}, 510 {false, "Reserved"}, 511 512 {true, "GET_RX_PKT_CNT_L"}, 513 {true, "GET_RX_PKT_CNT_H"}, 514 {true, "GET_TX_PKT_CNT_L"}, 515 {true, "GET_TX_PKT_CNT_H"}, 516 {true, "SEND_UC_PRT2HOST_PKT_CNT_L"}, 517 {true, "SEND_UC_PRT2HOST_PKT_CNT_H"}, 518 519 {true, "SEND_UC_PRT2PRT_PKT_CNT_L"}, 520 {true, "SEND_UC_PRT2PRT_PKT_CNT_H"}, 521 {true, "SEND_UC_HOST2HOST_PKT_CNT_L"}, 522 {true, "SEND_UC_HOST2HOST_PKT_CNT_H"}, 523 {true, "SEND_UC_HOST2PRT_PKT_CNT_L"}, 524 {true, "SEND_UC_HOST2PRT_PKT_CNT_H"}, 525 526 {true, "SEND_MC_FROM_PRT_CNT_L"}, 527 {true, "SEND_MC_FROM_PRT_CNT_H"}, 528 {true, "SEND_MC_FROM_HOST_CNT_L"}, 529 {true, "SEND_MC_FROM_HOST_CNT_H"}, 530 {true, "SSU_MC_RD_CNT_L"}, 531 {true, "SSU_MC_RD_CNT_H"}, 532 533 {true, "SSU_MC_DROP_CNT_L"}, 534 {true, "SSU_MC_DROP_CNT_H"}, 535 {true, "SSU_MC_RD_PKT_CNT_L"}, 536 {true, "SSU_MC_RD_PKT_CNT_H"}, 537 {true, "PPP_MC_2HOST_PKT_CNT_L"}, 538 {true, "PPP_MC_2HOST_PKT_CNT_H"}, 539 540 {true, "PPP_MC_2PRT_PKT_CNT_L"}, 541 {true, "PPP_MC_2PRT_PKT_CNT_H"}, 542 {true, "NTSNOS_PKT_CNT_L"}, 543 {true, "NTSNOS_PKT_CNT_H"}, 544 {true, "NTUP_PKT_CNT_L"}, 545 {true, "NTUP_PKT_CNT_H"}, 546 547 {true, "NTLCL_PKT_CNT_L"}, 548 {true, "NTLCL_PKT_CNT_H"}, 549 {true, "NTTGT_PKT_CNT_L"}, 550 {true, "NTTGT_PKT_CNT_H"}, 551 {true, "RTNS_PKT_CNT_L"}, 552 {true, "RTNS_PKT_CNT_H"}, 553 554 {true, "RTLPBK_PKT_CNT_L"}, 555 {true, "RTLPBK_PKT_CNT_H"}, 556 {true, "NR_PKT_CNT_L"}, 557 {true, "NR_PKT_CNT_H"}, 558 {true, "RR_PKT_CNT_L"}, 559 {true, "RR_PKT_CNT_H"}, 560 561 {true, "MNG_TBL_HIT_CNT_L"}, 562 {true, "MNG_TBL_HIT_CNT_H"}, 563 {true, "FD_TBL_HIT_CNT_L"}, 564 {true, "FD_TBL_HIT_CNT_H"}, 565 {true, "FD_LKUP_CNT_L"}, 566 {true, "FD_LKUP_CNT_H"}, 567 568 {true, "BC_HIT_CNT_L"}, 569 {true, "BC_HIT_CNT_H"}, 570 {true, "UM_TBL_UC_HIT_CNT_L"}, 571 {true, "UM_TBL_UC_HIT_CNT_H"}, 572 {true, "UM_TBL_MC_HIT_CNT_L"}, 573 {true, "UM_TBL_MC_HIT_CNT_H"}, 574 575 {true, "UM_TBL_VMDQ1_HIT_CNT_L"}, 576 {true, "UM_TBL_VMDQ1_HIT_CNT_H"}, 577 {true, "MTA_TBL_HIT_CNT_L"}, 578 {true, "MTA_TBL_HIT_CNT_H"}, 579 {true, "FWD_BONDING_HIT_CNT_L"}, 580 {true, "FWD_BONDING_HIT_CNT_H"}, 581 582 {true, "PROMIS_TBL_HIT_CNT_L"}, 583 {true, "PROMIS_TBL_HIT_CNT_H"}, 584 {true, "GET_TUNL_PKT_CNT_L"}, 585 {true, "GET_TUNL_PKT_CNT_H"}, 586 {true, "GET_BMC_PKT_CNT_L"}, 587 {true, "GET_BMC_PKT_CNT_H"}, 588 589 {true, "SEND_UC_PRT2BMC_PKT_CNT_L"}, 590 {true, "SEND_UC_PRT2BMC_PKT_CNT_H"}, 591 {true, "SEND_UC_HOST2BMC_PKT_CNT_L"}, 592 {true, "SEND_UC_HOST2BMC_PKT_CNT_H"}, 593 {true, "SEND_UC_BMC2HOST_PKT_CNT_L"}, 594 {true, "SEND_UC_BMC2HOST_PKT_CNT_H"}, 595 596 {true, "SEND_UC_BMC2PRT_PKT_CNT_L"}, 597 {true, "SEND_UC_BMC2PRT_PKT_CNT_H"}, 598 {true, "PPP_MC_2BMC_PKT_CNT_L"}, 599 {true, "PPP_MC_2BMC_PKT_CNT_H"}, 600 {true, "VLAN_MIRR_CNT_L"}, 601 {true, "VLAN_MIRR_CNT_H"}, 602 603 {true, "IG_MIRR_CNT_L"}, 604 {true, "IG_MIRR_CNT_H"}, 605 {true, "EG_MIRR_CNT_L"}, 606 {true, "EG_MIRR_CNT_H"}, 607 {true, "RX_DEFAULT_HOST_HIT_CNT_L"}, 608 {true, "RX_DEFAULT_HOST_HIT_CNT_H"}, 609 610 {true, "LAN_PAIR_CNT_L"}, 611 {true, "LAN_PAIR_CNT_H"}, 612 {true, "UM_TBL_MC_HIT_PKT_CNT_L"}, 613 {true, "UM_TBL_MC_HIT_PKT_CNT_H"}, 614 {true, "MTA_TBL_HIT_PKT_CNT_L"}, 615 {true, "MTA_TBL_HIT_PKT_CNT_H"}, 616 617 {true, "PROMIS_TBL_HIT_PKT_CNT_L"}, 618 {true, "PROMIS_TBL_HIT_PKT_CNT_H"}, 619 {false, "Reserved"}, 620 {false, "Reserved"}, 621 {false, "Reserved"}, 622 {false, "Reserved"}, 623 }; 624 625 static struct hclge_dbg_dfx_message hclge_dbg_rcb_reg[] = { 626 {false, "Reserved"}, 627 {true, "FSM_DFX_ST0"}, 628 {true, "FSM_DFX_ST1"}, 629 {true, "FSM_DFX_ST2"}, 630 {true, "FIFO_DFX_ST0"}, 631 {true, "FIFO_DFX_ST1"}, 632 633 {true, "FIFO_DFX_ST2"}, 634 {true, "FIFO_DFX_ST3"}, 635 {true, "FIFO_DFX_ST4"}, 636 {true, "FIFO_DFX_ST5"}, 637 {true, "FIFO_DFX_ST6"}, 638 {true, "FIFO_DFX_ST7"}, 639 640 {true, "FIFO_DFX_ST8"}, 641 {true, "FIFO_DFX_ST9"}, 642 {true, "FIFO_DFX_ST10"}, 643 {true, "FIFO_DFX_ST11"}, 644 {true, "Q_CREDIT_VLD_0"}, 645 {true, "Q_CREDIT_VLD_1"}, 646 647 {true, "Q_CREDIT_VLD_2"}, 648 {true, "Q_CREDIT_VLD_3"}, 649 {true, "Q_CREDIT_VLD_4"}, 650 {true, "Q_CREDIT_VLD_5"}, 651 {true, "Q_CREDIT_VLD_6"}, 652 {true, "Q_CREDIT_VLD_7"}, 653 654 {true, "Q_CREDIT_VLD_8"}, 655 {true, "Q_CREDIT_VLD_9"}, 656 {true, "Q_CREDIT_VLD_10"}, 657 {true, "Q_CREDIT_VLD_11"}, 658 {true, "Q_CREDIT_VLD_12"}, 659 {true, "Q_CREDIT_VLD_13"}, 660 661 {true, "Q_CREDIT_VLD_14"}, 662 {true, "Q_CREDIT_VLD_15"}, 663 {true, "Q_CREDIT_VLD_16"}, 664 {true, "Q_CREDIT_VLD_17"}, 665 {true, "Q_CREDIT_VLD_18"}, 666 {true, "Q_CREDIT_VLD_19"}, 667 668 {true, "Q_CREDIT_VLD_20"}, 669 {true, "Q_CREDIT_VLD_21"}, 670 {true, "Q_CREDIT_VLD_22"}, 671 {true, "Q_CREDIT_VLD_23"}, 672 {true, "Q_CREDIT_VLD_24"}, 673 {true, "Q_CREDIT_VLD_25"}, 674 675 {true, "Q_CREDIT_VLD_26"}, 676 {true, "Q_CREDIT_VLD_27"}, 677 {true, "Q_CREDIT_VLD_28"}, 678 {true, "Q_CREDIT_VLD_29"}, 679 {true, "Q_CREDIT_VLD_30"}, 680 {true, "Q_CREDIT_VLD_31"}, 681 682 {true, "GRO_BD_SERR_CNT"}, 683 {true, "GRO_CONTEXT_SERR_CNT"}, 684 {true, "RX_STASH_CFG_SERR_CNT"}, 685 {true, "AXI_RD_FBD_SERR_CNT"}, 686 {true, "GRO_BD_MERR_CNT"}, 687 {true, "GRO_CONTEXT_MERR_CNT"}, 688 689 {true, "RX_STASH_CFG_MERR_CNT"}, 690 {true, "AXI_RD_FBD_MERR_CNT"}, 691 {false, "Reserved"}, 692 {false, "Reserved"}, 693 {false, "Reserved"}, 694 {false, "Reserved"}, 695 }; 696 697 static struct hclge_dbg_dfx_message hclge_dbg_tqp_reg[] = { 698 {true, "q_num"}, 699 {true, "RCB_CFG_RX_RING_TAIL"}, 700 {true, "RCB_CFG_RX_RING_HEAD"}, 701 {true, "RCB_CFG_RX_RING_FBDNUM"}, 702 {true, "RCB_CFG_RX_RING_OFFSET"}, 703 {true, "RCB_CFG_RX_RING_FBDOFFSET"}, 704 705 {true, "RCB_CFG_RX_RING_PKTNUM_RECORD"}, 706 {true, "RCB_CFG_TX_RING_TAIL"}, 707 {true, "RCB_CFG_TX_RING_HEAD"}, 708 {true, "RCB_CFG_TX_RING_FBDNUM"}, 709 {true, "RCB_CFG_TX_RING_OFFSET"}, 710 {true, "RCB_CFG_TX_RING_EBDNUM"}, 711 }; 712 713 #endif 714