1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (c) 2018-2019 Hisilicon Limited. */ 3 4 #include <linux/device.h> 5 6 #include "hclge_debugfs.h" 7 #include "hclge_err.h" 8 #include "hclge_main.h" 9 #include "hclge_tm.h" 10 #include "hnae3.h" 11 12 static const char * const state_str[] = { "off", "on" }; 13 static const char * const hclge_mac_state_str[] = { 14 "TO_ADD", "TO_DEL", "ACTIVE" 15 }; 16 17 static const struct hclge_dbg_reg_type_info hclge_dbg_reg_info[] = { 18 { .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON, 19 .dfx_msg = &hclge_dbg_bios_common_reg[0], 20 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_bios_common_reg), 21 .offset = HCLGE_DBG_DFX_BIOS_OFFSET, 22 .cmd = HCLGE_OPC_DFX_BIOS_COMMON_REG } }, 23 { .cmd = HNAE3_DBG_CMD_REG_SSU, 24 .dfx_msg = &hclge_dbg_ssu_reg_0[0], 25 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ssu_reg_0), 26 .offset = HCLGE_DBG_DFX_SSU_0_OFFSET, 27 .cmd = HCLGE_OPC_DFX_SSU_REG_0 } }, 28 { .cmd = HNAE3_DBG_CMD_REG_SSU, 29 .dfx_msg = &hclge_dbg_ssu_reg_1[0], 30 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ssu_reg_1), 31 .offset = HCLGE_DBG_DFX_SSU_1_OFFSET, 32 .cmd = HCLGE_OPC_DFX_SSU_REG_1 } }, 33 { .cmd = HNAE3_DBG_CMD_REG_SSU, 34 .dfx_msg = &hclge_dbg_ssu_reg_2[0], 35 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ssu_reg_2), 36 .offset = HCLGE_DBG_DFX_SSU_2_OFFSET, 37 .cmd = HCLGE_OPC_DFX_SSU_REG_2 } }, 38 { .cmd = HNAE3_DBG_CMD_REG_IGU_EGU, 39 .dfx_msg = &hclge_dbg_igu_egu_reg[0], 40 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_igu_egu_reg), 41 .offset = HCLGE_DBG_DFX_IGU_OFFSET, 42 .cmd = HCLGE_OPC_DFX_IGU_EGU_REG } }, 43 { .cmd = HNAE3_DBG_CMD_REG_RPU, 44 .dfx_msg = &hclge_dbg_rpu_reg_0[0], 45 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rpu_reg_0), 46 .offset = HCLGE_DBG_DFX_RPU_0_OFFSET, 47 .cmd = HCLGE_OPC_DFX_RPU_REG_0 } }, 48 { .cmd = HNAE3_DBG_CMD_REG_RPU, 49 .dfx_msg = &hclge_dbg_rpu_reg_1[0], 50 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rpu_reg_1), 51 .offset = HCLGE_DBG_DFX_RPU_1_OFFSET, 52 .cmd = HCLGE_OPC_DFX_RPU_REG_1 } }, 53 { .cmd = HNAE3_DBG_CMD_REG_NCSI, 54 .dfx_msg = &hclge_dbg_ncsi_reg[0], 55 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ncsi_reg), 56 .offset = HCLGE_DBG_DFX_NCSI_OFFSET, 57 .cmd = HCLGE_OPC_DFX_NCSI_REG } }, 58 { .cmd = HNAE3_DBG_CMD_REG_RTC, 59 .dfx_msg = &hclge_dbg_rtc_reg[0], 60 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rtc_reg), 61 .offset = HCLGE_DBG_DFX_RTC_OFFSET, 62 .cmd = HCLGE_OPC_DFX_RTC_REG } }, 63 { .cmd = HNAE3_DBG_CMD_REG_PPP, 64 .dfx_msg = &hclge_dbg_ppp_reg[0], 65 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ppp_reg), 66 .offset = HCLGE_DBG_DFX_PPP_OFFSET, 67 .cmd = HCLGE_OPC_DFX_PPP_REG } }, 68 { .cmd = HNAE3_DBG_CMD_REG_RCB, 69 .dfx_msg = &hclge_dbg_rcb_reg[0], 70 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rcb_reg), 71 .offset = HCLGE_DBG_DFX_RCB_OFFSET, 72 .cmd = HCLGE_OPC_DFX_RCB_REG } }, 73 { .cmd = HNAE3_DBG_CMD_REG_TQP, 74 .dfx_msg = &hclge_dbg_tqp_reg[0], 75 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_tqp_reg), 76 .offset = HCLGE_DBG_DFX_TQP_OFFSET, 77 .cmd = HCLGE_OPC_DFX_TQP_REG } }, 78 }; 79 80 static void hclge_dbg_fill_content(char *content, u16 len, 81 const struct hclge_dbg_item *items, 82 const char **result, u16 size) 83 { 84 char *pos = content; 85 u16 i; 86 87 memset(content, ' ', len); 88 for (i = 0; i < size; i++) { 89 if (result) 90 strncpy(pos, result[i], strlen(result[i])); 91 else 92 strncpy(pos, items[i].name, strlen(items[i].name)); 93 pos += strlen(items[i].name) + items[i].interval; 94 } 95 *pos++ = '\n'; 96 *pos++ = '\0'; 97 } 98 99 static char *hclge_dbg_get_func_id_str(char *buf, u8 id) 100 { 101 if (id) 102 sprintf(buf, "vf%u", id - 1); 103 else 104 sprintf(buf, "pf"); 105 106 return buf; 107 } 108 109 static int hclge_dbg_get_dfx_bd_num(struct hclge_dev *hdev, int offset, 110 u32 *bd_num) 111 { 112 struct hclge_desc desc[HCLGE_GET_DFX_REG_TYPE_CNT]; 113 int entries_per_desc; 114 int index; 115 int ret; 116 117 ret = hclge_query_bd_num_cmd_send(hdev, desc); 118 if (ret) { 119 dev_err(&hdev->pdev->dev, 120 "failed to get dfx bd_num, offset = %d, ret = %d\n", 121 offset, ret); 122 return ret; 123 } 124 125 entries_per_desc = ARRAY_SIZE(desc[0].data); 126 index = offset % entries_per_desc; 127 128 *bd_num = le32_to_cpu(desc[offset / entries_per_desc].data[index]); 129 if (!(*bd_num)) { 130 dev_err(&hdev->pdev->dev, "The value of dfx bd_num is 0!\n"); 131 return -EINVAL; 132 } 133 134 return 0; 135 } 136 137 static int hclge_dbg_cmd_send(struct hclge_dev *hdev, 138 struct hclge_desc *desc_src, 139 int index, int bd_num, 140 enum hclge_opcode_type cmd) 141 { 142 struct hclge_desc *desc = desc_src; 143 int ret, i; 144 145 hclge_cmd_setup_basic_desc(desc, cmd, true); 146 desc->data[0] = cpu_to_le32(index); 147 148 for (i = 1; i < bd_num; i++) { 149 desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 150 desc++; 151 hclge_cmd_setup_basic_desc(desc, cmd, true); 152 } 153 154 ret = hclge_cmd_send(&hdev->hw, desc_src, bd_num); 155 if (ret) 156 dev_err(&hdev->pdev->dev, 157 "cmd(0x%x) send fail, ret = %d\n", cmd, ret); 158 return ret; 159 } 160 161 static int 162 hclge_dbg_dump_reg_tqp(struct hclge_dev *hdev, 163 const struct hclge_dbg_reg_type_info *reg_info, 164 char *buf, int len, int *pos) 165 { 166 const struct hclge_dbg_dfx_message *dfx_message = reg_info->dfx_msg; 167 const struct hclge_dbg_reg_common_msg *reg_msg = ®_info->reg_msg; 168 struct hclge_desc *desc_src; 169 u32 index, entry, i, cnt; 170 int bd_num, min_num, ret; 171 struct hclge_desc *desc; 172 173 ret = hclge_dbg_get_dfx_bd_num(hdev, reg_msg->offset, &bd_num); 174 if (ret) 175 return ret; 176 177 desc_src = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL); 178 if (!desc_src) 179 return -ENOMEM; 180 181 min_num = min_t(int, bd_num * HCLGE_DESC_DATA_LEN, reg_msg->msg_num); 182 183 for (i = 0, cnt = 0; i < min_num; i++, dfx_message++) 184 *pos += scnprintf(buf + *pos, len - *pos, "item%u = %s\n", 185 cnt++, dfx_message->message); 186 187 for (i = 0; i < cnt; i++) 188 *pos += scnprintf(buf + *pos, len - *pos, "item%u\t", i); 189 190 *pos += scnprintf(buf + *pos, len - *pos, "\n"); 191 192 for (index = 0; index < hdev->vport[0].alloc_tqps; index++) { 193 dfx_message = reg_info->dfx_msg; 194 desc = desc_src; 195 ret = hclge_dbg_cmd_send(hdev, desc, index, bd_num, 196 reg_msg->cmd); 197 if (ret) 198 break; 199 200 for (i = 0; i < min_num; i++, dfx_message++) { 201 entry = i % HCLGE_DESC_DATA_LEN; 202 if (i > 0 && !entry) 203 desc++; 204 205 *pos += scnprintf(buf + *pos, len - *pos, "%#x\t", 206 le32_to_cpu(desc->data[entry])); 207 } 208 *pos += scnprintf(buf + *pos, len - *pos, "\n"); 209 } 210 211 kfree(desc_src); 212 return ret; 213 } 214 215 static int 216 hclge_dbg_dump_reg_common(struct hclge_dev *hdev, 217 const struct hclge_dbg_reg_type_info *reg_info, 218 char *buf, int len, int *pos) 219 { 220 const struct hclge_dbg_reg_common_msg *reg_msg = ®_info->reg_msg; 221 const struct hclge_dbg_dfx_message *dfx_message = reg_info->dfx_msg; 222 struct hclge_desc *desc_src; 223 int bd_num, min_num, ret; 224 struct hclge_desc *desc; 225 u32 entry, i; 226 227 ret = hclge_dbg_get_dfx_bd_num(hdev, reg_msg->offset, &bd_num); 228 if (ret) 229 return ret; 230 231 desc_src = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL); 232 if (!desc_src) 233 return -ENOMEM; 234 235 desc = desc_src; 236 237 ret = hclge_dbg_cmd_send(hdev, desc, 0, bd_num, reg_msg->cmd); 238 if (ret) { 239 kfree(desc); 240 return ret; 241 } 242 243 min_num = min_t(int, bd_num * HCLGE_DESC_DATA_LEN, reg_msg->msg_num); 244 245 for (i = 0; i < min_num; i++, dfx_message++) { 246 entry = i % HCLGE_DESC_DATA_LEN; 247 if (i > 0 && !entry) 248 desc++; 249 if (!dfx_message->flag) 250 continue; 251 252 *pos += scnprintf(buf + *pos, len - *pos, "%s: %#x\n", 253 dfx_message->message, 254 le32_to_cpu(desc->data[entry])); 255 } 256 257 kfree(desc_src); 258 return 0; 259 } 260 261 static int hclge_dbg_dump_mac_enable_status(struct hclge_dev *hdev, char *buf, 262 int len, int *pos) 263 { 264 struct hclge_config_mac_mode_cmd *req; 265 struct hclge_desc desc; 266 u32 loop_en; 267 int ret; 268 269 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 270 271 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 272 if (ret) { 273 dev_err(&hdev->pdev->dev, 274 "failed to dump mac enable status, ret = %d\n", ret); 275 return ret; 276 } 277 278 req = (struct hclge_config_mac_mode_cmd *)desc.data; 279 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 280 281 *pos += scnprintf(buf + *pos, len - *pos, "mac_trans_en: %#x\n", 282 hnae3_get_bit(loop_en, HCLGE_MAC_TX_EN_B)); 283 *pos += scnprintf(buf + *pos, len - *pos, "mac_rcv_en: %#x\n", 284 hnae3_get_bit(loop_en, HCLGE_MAC_RX_EN_B)); 285 *pos += scnprintf(buf + *pos, len - *pos, "pad_trans_en: %#x\n", 286 hnae3_get_bit(loop_en, HCLGE_MAC_PAD_TX_B)); 287 *pos += scnprintf(buf + *pos, len - *pos, "pad_rcv_en: %#x\n", 288 hnae3_get_bit(loop_en, HCLGE_MAC_PAD_RX_B)); 289 *pos += scnprintf(buf + *pos, len - *pos, "1588_trans_en: %#x\n", 290 hnae3_get_bit(loop_en, HCLGE_MAC_1588_TX_B)); 291 *pos += scnprintf(buf + *pos, len - *pos, "1588_rcv_en: %#x\n", 292 hnae3_get_bit(loop_en, HCLGE_MAC_1588_RX_B)); 293 *pos += scnprintf(buf + *pos, len - *pos, "mac_app_loop_en: %#x\n", 294 hnae3_get_bit(loop_en, HCLGE_MAC_APP_LP_B)); 295 *pos += scnprintf(buf + *pos, len - *pos, "mac_line_loop_en: %#x\n", 296 hnae3_get_bit(loop_en, HCLGE_MAC_LINE_LP_B)); 297 *pos += scnprintf(buf + *pos, len - *pos, "mac_fcs_tx_en: %#x\n", 298 hnae3_get_bit(loop_en, HCLGE_MAC_FCS_TX_B)); 299 *pos += scnprintf(buf + *pos, len - *pos, 300 "mac_rx_oversize_truncate_en: %#x\n", 301 hnae3_get_bit(loop_en, 302 HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B)); 303 *pos += scnprintf(buf + *pos, len - *pos, "mac_rx_fcs_strip_en: %#x\n", 304 hnae3_get_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B)); 305 *pos += scnprintf(buf + *pos, len - *pos, "mac_rx_fcs_en: %#x\n", 306 hnae3_get_bit(loop_en, HCLGE_MAC_RX_FCS_B)); 307 *pos += scnprintf(buf + *pos, len - *pos, 308 "mac_tx_under_min_err_en: %#x\n", 309 hnae3_get_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B)); 310 *pos += scnprintf(buf + *pos, len - *pos, 311 "mac_tx_oversize_truncate_en: %#x\n", 312 hnae3_get_bit(loop_en, 313 HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B)); 314 315 return 0; 316 } 317 318 static int hclge_dbg_dump_mac_frame_size(struct hclge_dev *hdev, char *buf, 319 int len, int *pos) 320 { 321 struct hclge_config_max_frm_size_cmd *req; 322 struct hclge_desc desc; 323 int ret; 324 325 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, true); 326 327 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 328 if (ret) { 329 dev_err(&hdev->pdev->dev, 330 "failed to dump mac frame size, ret = %d\n", ret); 331 return ret; 332 } 333 334 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 335 336 *pos += scnprintf(buf + *pos, len - *pos, "max_frame_size: %u\n", 337 le16_to_cpu(req->max_frm_size)); 338 *pos += scnprintf(buf + *pos, len - *pos, "min_frame_size: %u\n", 339 req->min_frm_size); 340 341 return 0; 342 } 343 344 static int hclge_dbg_dump_mac_speed_duplex(struct hclge_dev *hdev, char *buf, 345 int len, int *pos) 346 { 347 #define HCLGE_MAC_SPEED_SHIFT 0 348 #define HCLGE_MAC_SPEED_MASK GENMASK(5, 0) 349 #define HCLGE_MAC_DUPLEX_SHIFT 7 350 351 struct hclge_config_mac_speed_dup_cmd *req; 352 struct hclge_desc desc; 353 int ret; 354 355 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, true); 356 357 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 358 if (ret) { 359 dev_err(&hdev->pdev->dev, 360 "failed to dump mac speed duplex, ret = %d\n", ret); 361 return ret; 362 } 363 364 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 365 366 *pos += scnprintf(buf + *pos, len - *pos, "speed: %#lx\n", 367 hnae3_get_field(req->speed_dup, HCLGE_MAC_SPEED_MASK, 368 HCLGE_MAC_SPEED_SHIFT)); 369 *pos += scnprintf(buf + *pos, len - *pos, "duplex: %#x\n", 370 hnae3_get_bit(req->speed_dup, 371 HCLGE_MAC_DUPLEX_SHIFT)); 372 return 0; 373 } 374 375 static int hclge_dbg_dump_mac(struct hclge_dev *hdev, char *buf, int len) 376 { 377 int pos = 0; 378 int ret; 379 380 ret = hclge_dbg_dump_mac_enable_status(hdev, buf, len, &pos); 381 if (ret) 382 return ret; 383 384 ret = hclge_dbg_dump_mac_frame_size(hdev, buf, len, &pos); 385 if (ret) 386 return ret; 387 388 return hclge_dbg_dump_mac_speed_duplex(hdev, buf, len, &pos); 389 } 390 391 static int hclge_dbg_dump_dcb_qset(struct hclge_dev *hdev, char *buf, int len, 392 int *pos) 393 { 394 struct hclge_dbg_bitmap_cmd *bitmap; 395 struct hclge_desc desc; 396 u16 qset_id, qset_num; 397 int ret; 398 399 ret = hclge_tm_get_qset_num(hdev, &qset_num); 400 if (ret) 401 return ret; 402 403 *pos += scnprintf(buf + *pos, len - *pos, 404 "qset_id roce_qset_mask nic_qset_mask qset_shaping_pass qset_bp_status\n"); 405 for (qset_id = 0; qset_id < qset_num; qset_id++) { 406 ret = hclge_dbg_cmd_send(hdev, &desc, qset_id, 1, 407 HCLGE_OPC_QSET_DFX_STS); 408 if (ret) 409 return ret; 410 411 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc.data[1]; 412 413 *pos += scnprintf(buf + *pos, len - *pos, 414 "%04u %#x %#x %#x %#x\n", 415 qset_id, bitmap->bit0, bitmap->bit1, 416 bitmap->bit2, bitmap->bit3); 417 } 418 419 return 0; 420 } 421 422 static int hclge_dbg_dump_dcb_pri(struct hclge_dev *hdev, char *buf, int len, 423 int *pos) 424 { 425 struct hclge_dbg_bitmap_cmd *bitmap; 426 struct hclge_desc desc; 427 u8 pri_id, pri_num; 428 int ret; 429 430 ret = hclge_tm_get_pri_num(hdev, &pri_num); 431 if (ret) 432 return ret; 433 434 *pos += scnprintf(buf + *pos, len - *pos, 435 "pri_id pri_mask pri_cshaping_pass pri_pshaping_pass\n"); 436 for (pri_id = 0; pri_id < pri_num; pri_id++) { 437 ret = hclge_dbg_cmd_send(hdev, &desc, pri_id, 1, 438 HCLGE_OPC_PRI_DFX_STS); 439 if (ret) 440 return ret; 441 442 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc.data[1]; 443 444 *pos += scnprintf(buf + *pos, len - *pos, 445 "%03u %#x %#x %#x\n", 446 pri_id, bitmap->bit0, bitmap->bit1, 447 bitmap->bit2); 448 } 449 450 return 0; 451 } 452 453 static int hclge_dbg_dump_dcb_pg(struct hclge_dev *hdev, char *buf, int len, 454 int *pos) 455 { 456 struct hclge_dbg_bitmap_cmd *bitmap; 457 struct hclge_desc desc; 458 u8 pg_id; 459 int ret; 460 461 *pos += scnprintf(buf + *pos, len - *pos, 462 "pg_id pg_mask pg_cshaping_pass pg_pshaping_pass\n"); 463 for (pg_id = 0; pg_id < hdev->tm_info.num_pg; pg_id++) { 464 ret = hclge_dbg_cmd_send(hdev, &desc, pg_id, 1, 465 HCLGE_OPC_PG_DFX_STS); 466 if (ret) 467 return ret; 468 469 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc.data[1]; 470 471 *pos += scnprintf(buf + *pos, len - *pos, 472 "%03u %#x %#x %#x\n", 473 pg_id, bitmap->bit0, bitmap->bit1, 474 bitmap->bit2); 475 } 476 477 return 0; 478 } 479 480 static int hclge_dbg_dump_dcb_queue(struct hclge_dev *hdev, char *buf, int len, 481 int *pos) 482 { 483 struct hclge_desc desc; 484 u16 nq_id; 485 int ret; 486 487 *pos += scnprintf(buf + *pos, len - *pos, 488 "nq_id sch_nic_queue_cnt sch_roce_queue_cnt\n"); 489 for (nq_id = 0; nq_id < hdev->num_tqps; nq_id++) { 490 ret = hclge_dbg_cmd_send(hdev, &desc, nq_id, 1, 491 HCLGE_OPC_SCH_NQ_CNT); 492 if (ret) 493 return ret; 494 495 *pos += scnprintf(buf + *pos, len - *pos, "%04u %#x", 496 nq_id, le32_to_cpu(desc.data[1])); 497 498 ret = hclge_dbg_cmd_send(hdev, &desc, nq_id, 1, 499 HCLGE_OPC_SCH_RQ_CNT); 500 if (ret) 501 return ret; 502 503 *pos += scnprintf(buf + *pos, len - *pos, 504 " %#x\n", 505 le32_to_cpu(desc.data[1])); 506 } 507 508 return 0; 509 } 510 511 static int hclge_dbg_dump_dcb_port(struct hclge_dev *hdev, char *buf, int len, 512 int *pos) 513 { 514 struct hclge_dbg_bitmap_cmd *bitmap; 515 struct hclge_desc desc; 516 u8 port_id = 0; 517 int ret; 518 519 ret = hclge_dbg_cmd_send(hdev, &desc, port_id, 1, 520 HCLGE_OPC_PORT_DFX_STS); 521 if (ret) 522 return ret; 523 524 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc.data[1]; 525 526 *pos += scnprintf(buf + *pos, len - *pos, "port_mask: %#x\n", 527 bitmap->bit0); 528 *pos += scnprintf(buf + *pos, len - *pos, "port_shaping_pass: %#x\n", 529 bitmap->bit1); 530 531 return 0; 532 } 533 534 static int hclge_dbg_dump_dcb_tm(struct hclge_dev *hdev, char *buf, int len, 535 int *pos) 536 { 537 struct hclge_desc desc[2]; 538 u8 port_id = 0; 539 int ret; 540 541 ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1, 542 HCLGE_OPC_TM_INTERNAL_CNT); 543 if (ret) 544 return ret; 545 546 *pos += scnprintf(buf + *pos, len - *pos, "SCH_NIC_NUM: %#x\n", 547 le32_to_cpu(desc[0].data[1])); 548 *pos += scnprintf(buf + *pos, len - *pos, "SCH_ROCE_NUM: %#x\n", 549 le32_to_cpu(desc[0].data[2])); 550 551 ret = hclge_dbg_cmd_send(hdev, desc, port_id, 2, 552 HCLGE_OPC_TM_INTERNAL_STS); 553 if (ret) 554 return ret; 555 556 *pos += scnprintf(buf + *pos, len - *pos, "pri_bp: %#x\n", 557 le32_to_cpu(desc[0].data[1])); 558 *pos += scnprintf(buf + *pos, len - *pos, "fifo_dfx_info: %#x\n", 559 le32_to_cpu(desc[0].data[2])); 560 *pos += scnprintf(buf + *pos, len - *pos, 561 "sch_roce_fifo_afull_gap: %#x\n", 562 le32_to_cpu(desc[0].data[3])); 563 *pos += scnprintf(buf + *pos, len - *pos, 564 "tx_private_waterline: %#x\n", 565 le32_to_cpu(desc[0].data[4])); 566 *pos += scnprintf(buf + *pos, len - *pos, "tm_bypass_en: %#x\n", 567 le32_to_cpu(desc[0].data[5])); 568 *pos += scnprintf(buf + *pos, len - *pos, "SSU_TM_BYPASS_EN: %#x\n", 569 le32_to_cpu(desc[1].data[0])); 570 *pos += scnprintf(buf + *pos, len - *pos, "SSU_RESERVE_CFG: %#x\n", 571 le32_to_cpu(desc[1].data[1])); 572 573 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) 574 return 0; 575 576 ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1, 577 HCLGE_OPC_TM_INTERNAL_STS_1); 578 if (ret) 579 return ret; 580 581 *pos += scnprintf(buf + *pos, len - *pos, "TC_MAP_SEL: %#x\n", 582 le32_to_cpu(desc[0].data[1])); 583 *pos += scnprintf(buf + *pos, len - *pos, "IGU_PFC_PRI_EN: %#x\n", 584 le32_to_cpu(desc[0].data[2])); 585 *pos += scnprintf(buf + *pos, len - *pos, "MAC_PFC_PRI_EN: %#x\n", 586 le32_to_cpu(desc[0].data[3])); 587 *pos += scnprintf(buf + *pos, len - *pos, "IGU_PRI_MAP_TC_CFG: %#x\n", 588 le32_to_cpu(desc[0].data[4])); 589 *pos += scnprintf(buf + *pos, len - *pos, 590 "IGU_TX_PRI_MAP_TC_CFG: %#x\n", 591 le32_to_cpu(desc[0].data[5])); 592 593 return 0; 594 } 595 596 static int hclge_dbg_dump_dcb(struct hclge_dev *hdev, char *buf, int len) 597 { 598 int pos = 0; 599 int ret; 600 601 ret = hclge_dbg_dump_dcb_qset(hdev, buf, len, &pos); 602 if (ret) 603 return ret; 604 605 ret = hclge_dbg_dump_dcb_pri(hdev, buf, len, &pos); 606 if (ret) 607 return ret; 608 609 ret = hclge_dbg_dump_dcb_pg(hdev, buf, len, &pos); 610 if (ret) 611 return ret; 612 613 ret = hclge_dbg_dump_dcb_queue(hdev, buf, len, &pos); 614 if (ret) 615 return ret; 616 617 ret = hclge_dbg_dump_dcb_port(hdev, buf, len, &pos); 618 if (ret) 619 return ret; 620 621 return hclge_dbg_dump_dcb_tm(hdev, buf, len, &pos); 622 } 623 624 static int hclge_dbg_dump_reg_cmd(struct hclge_dev *hdev, 625 enum hnae3_dbg_cmd cmd, char *buf, int len) 626 { 627 const struct hclge_dbg_reg_type_info *reg_info; 628 int pos = 0, ret = 0; 629 int i; 630 631 for (i = 0; i < ARRAY_SIZE(hclge_dbg_reg_info); i++) { 632 reg_info = &hclge_dbg_reg_info[i]; 633 if (cmd == reg_info->cmd) { 634 if (cmd == HNAE3_DBG_CMD_REG_TQP) 635 return hclge_dbg_dump_reg_tqp(hdev, reg_info, 636 buf, len, &pos); 637 638 ret = hclge_dbg_dump_reg_common(hdev, reg_info, buf, 639 len, &pos); 640 if (ret) 641 break; 642 } 643 } 644 645 return ret; 646 } 647 648 static int hclge_dbg_dump_tc(struct hclge_dev *hdev, char *buf, int len) 649 { 650 struct hclge_ets_tc_weight_cmd *ets_weight; 651 struct hclge_desc desc; 652 char *sch_mode_str; 653 int pos = 0; 654 int ret; 655 u8 i; 656 657 if (!hnae3_dev_dcb_supported(hdev)) { 658 dev_err(&hdev->pdev->dev, 659 "Only DCB-supported dev supports tc\n"); 660 return -EOPNOTSUPP; 661 } 662 663 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, true); 664 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 665 if (ret) { 666 dev_err(&hdev->pdev->dev, "failed to get tc weight, ret = %d\n", 667 ret); 668 return ret; 669 } 670 671 ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data; 672 673 pos += scnprintf(buf + pos, len - pos, "enabled tc number: %u\n", 674 hdev->tm_info.num_tc); 675 pos += scnprintf(buf + pos, len - pos, "weight_offset: %u\n", 676 ets_weight->weight_offset); 677 678 pos += scnprintf(buf + pos, len - pos, "TC MODE WEIGHT\n"); 679 for (i = 0; i < HNAE3_MAX_TC; i++) { 680 sch_mode_str = ets_weight->tc_weight[i] ? "dwrr" : "sp"; 681 pos += scnprintf(buf + pos, len - pos, "%u %4s %3u\n", 682 i, sch_mode_str, 683 hdev->tm_info.pg_info[0].tc_dwrr[i]); 684 } 685 686 return 0; 687 } 688 689 static const struct hclge_dbg_item tm_pg_items[] = { 690 { "ID", 2 }, 691 { "PRI_MAP", 2 }, 692 { "MODE", 2 }, 693 { "DWRR", 2 }, 694 { "C_IR_B", 2 }, 695 { "C_IR_U", 2 }, 696 { "C_IR_S", 2 }, 697 { "C_BS_B", 2 }, 698 { "C_BS_S", 2 }, 699 { "C_FLAG", 2 }, 700 { "C_RATE(Mbps)", 2 }, 701 { "P_IR_B", 2 }, 702 { "P_IR_U", 2 }, 703 { "P_IR_S", 2 }, 704 { "P_BS_B", 2 }, 705 { "P_BS_S", 2 }, 706 { "P_FLAG", 2 }, 707 { "P_RATE(Mbps)", 0 } 708 }; 709 710 static void hclge_dbg_fill_shaper_content(struct hclge_tm_shaper_para *para, 711 char **result, u8 *index) 712 { 713 sprintf(result[(*index)++], "%3u", para->ir_b); 714 sprintf(result[(*index)++], "%3u", para->ir_u); 715 sprintf(result[(*index)++], "%3u", para->ir_s); 716 sprintf(result[(*index)++], "%3u", para->bs_b); 717 sprintf(result[(*index)++], "%3u", para->bs_s); 718 sprintf(result[(*index)++], "%3u", para->flag); 719 sprintf(result[(*index)++], "%6u", para->rate); 720 } 721 722 static int __hclge_dbg_dump_tm_pg(struct hclge_dev *hdev, char *data_str, 723 char *buf, int len) 724 { 725 struct hclge_tm_shaper_para c_shaper_para, p_shaper_para; 726 char *result[ARRAY_SIZE(tm_pg_items)], *sch_mode_str; 727 u8 pg_id, sch_mode, weight, pri_bit_map, i, j; 728 char content[HCLGE_DBG_TM_INFO_LEN]; 729 int pos = 0; 730 int ret; 731 732 for (i = 0; i < ARRAY_SIZE(tm_pg_items); i++) { 733 result[i] = data_str; 734 data_str += HCLGE_DBG_DATA_STR_LEN; 735 } 736 737 hclge_dbg_fill_content(content, sizeof(content), tm_pg_items, 738 NULL, ARRAY_SIZE(tm_pg_items)); 739 pos += scnprintf(buf + pos, len - pos, "%s", content); 740 741 for (pg_id = 0; pg_id < hdev->tm_info.num_pg; pg_id++) { 742 ret = hclge_tm_get_pg_to_pri_map(hdev, pg_id, &pri_bit_map); 743 if (ret) 744 return ret; 745 746 ret = hclge_tm_get_pg_sch_mode(hdev, pg_id, &sch_mode); 747 if (ret) 748 return ret; 749 750 ret = hclge_tm_get_pg_weight(hdev, pg_id, &weight); 751 if (ret) 752 return ret; 753 754 ret = hclge_tm_get_pg_shaper(hdev, pg_id, 755 HCLGE_OPC_TM_PG_C_SHAPPING, 756 &c_shaper_para); 757 if (ret) 758 return ret; 759 760 ret = hclge_tm_get_pg_shaper(hdev, pg_id, 761 HCLGE_OPC_TM_PG_P_SHAPPING, 762 &p_shaper_para); 763 if (ret) 764 return ret; 765 766 sch_mode_str = sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK ? "dwrr" : 767 "sp"; 768 769 j = 0; 770 sprintf(result[j++], "%02u", pg_id); 771 sprintf(result[j++], "0x%02x", pri_bit_map); 772 sprintf(result[j++], "%4s", sch_mode_str); 773 sprintf(result[j++], "%3u", weight); 774 hclge_dbg_fill_shaper_content(&c_shaper_para, result, &j); 775 hclge_dbg_fill_shaper_content(&p_shaper_para, result, &j); 776 777 hclge_dbg_fill_content(content, sizeof(content), tm_pg_items, 778 (const char **)result, 779 ARRAY_SIZE(tm_pg_items)); 780 pos += scnprintf(buf + pos, len - pos, "%s", content); 781 } 782 783 return 0; 784 } 785 786 static int hclge_dbg_dump_tm_pg(struct hclge_dev *hdev, char *buf, int len) 787 { 788 char *data_str; 789 int ret; 790 791 data_str = kcalloc(ARRAY_SIZE(tm_pg_items), 792 HCLGE_DBG_DATA_STR_LEN, GFP_KERNEL); 793 794 if (!data_str) 795 return -ENOMEM; 796 797 ret = __hclge_dbg_dump_tm_pg(hdev, data_str, buf, len); 798 799 kfree(data_str); 800 801 return ret; 802 } 803 804 static int hclge_dbg_dump_tm_port(struct hclge_dev *hdev, char *buf, int len) 805 { 806 struct hclge_tm_shaper_para shaper_para; 807 int pos = 0; 808 int ret; 809 810 ret = hclge_tm_get_port_shaper(hdev, &shaper_para); 811 if (ret) 812 return ret; 813 814 pos += scnprintf(buf + pos, len - pos, 815 "IR_B IR_U IR_S BS_B BS_S FLAG RATE(Mbps)\n"); 816 pos += scnprintf(buf + pos, len - pos, 817 "%3u %3u %3u %3u %3u %1u %6u\n", 818 shaper_para.ir_b, shaper_para.ir_u, shaper_para.ir_s, 819 shaper_para.bs_b, shaper_para.bs_s, shaper_para.flag, 820 shaper_para.rate); 821 822 return 0; 823 } 824 825 static int hclge_dbg_dump_tm_bp_qset_map(struct hclge_dev *hdev, u8 tc_id, 826 char *buf, int len) 827 { 828 u32 qset_mapping[HCLGE_BP_EXT_GRP_NUM]; 829 struct hclge_bp_to_qs_map_cmd *map; 830 struct hclge_desc desc; 831 int pos = 0; 832 u8 group_id; 833 u8 grp_num; 834 u16 i = 0; 835 int ret; 836 837 grp_num = hdev->num_tqps <= HCLGE_TQP_MAX_SIZE_DEV_V2 ? 838 HCLGE_BP_GRP_NUM : HCLGE_BP_EXT_GRP_NUM; 839 map = (struct hclge_bp_to_qs_map_cmd *)desc.data; 840 for (group_id = 0; group_id < grp_num; group_id++) { 841 hclge_cmd_setup_basic_desc(&desc, 842 HCLGE_OPC_TM_BP_TO_QSET_MAPPING, 843 true); 844 map->tc_id = tc_id; 845 map->qs_group_id = group_id; 846 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 847 if (ret) { 848 dev_err(&hdev->pdev->dev, 849 "failed to get bp to qset map, ret = %d\n", 850 ret); 851 return ret; 852 } 853 854 qset_mapping[group_id] = le32_to_cpu(map->qs_bit_map); 855 } 856 857 pos += scnprintf(buf + pos, len - pos, "INDEX | TM BP QSET MAPPING:\n"); 858 for (group_id = 0; group_id < grp_num / 8; group_id++) { 859 pos += scnprintf(buf + pos, len - pos, 860 "%04d | %08x:%08x:%08x:%08x:%08x:%08x:%08x:%08x\n", 861 group_id * 256, qset_mapping[i + 7], 862 qset_mapping[i + 6], qset_mapping[i + 5], 863 qset_mapping[i + 4], qset_mapping[i + 3], 864 qset_mapping[i + 2], qset_mapping[i + 1], 865 qset_mapping[i]); 866 i += 8; 867 } 868 869 return pos; 870 } 871 872 static int hclge_dbg_dump_tm_map(struct hclge_dev *hdev, char *buf, int len) 873 { 874 u16 queue_id; 875 u16 qset_id; 876 u8 link_vld; 877 int pos = 0; 878 u8 pri_id; 879 u8 tc_id; 880 int ret; 881 882 for (queue_id = 0; queue_id < hdev->num_tqps; queue_id++) { 883 ret = hclge_tm_get_q_to_qs_map(hdev, queue_id, &qset_id); 884 if (ret) 885 return ret; 886 887 ret = hclge_tm_get_qset_map_pri(hdev, qset_id, &pri_id, 888 &link_vld); 889 if (ret) 890 return ret; 891 892 ret = hclge_tm_get_q_to_tc(hdev, queue_id, &tc_id); 893 if (ret) 894 return ret; 895 896 pos += scnprintf(buf + pos, len - pos, 897 "QUEUE_ID QSET_ID PRI_ID TC_ID\n"); 898 pos += scnprintf(buf + pos, len - pos, 899 "%04u %4u %3u %2u\n", 900 queue_id, qset_id, pri_id, tc_id); 901 902 if (!hnae3_dev_dcb_supported(hdev)) 903 continue; 904 905 ret = hclge_dbg_dump_tm_bp_qset_map(hdev, tc_id, buf + pos, 906 len - pos); 907 if (ret < 0) 908 return ret; 909 pos += ret; 910 911 pos += scnprintf(buf + pos, len - pos, "\n"); 912 } 913 914 return 0; 915 } 916 917 static int hclge_dbg_dump_tm_nodes(struct hclge_dev *hdev, char *buf, int len) 918 { 919 struct hclge_tm_nodes_cmd *nodes; 920 struct hclge_desc desc; 921 int pos = 0; 922 int ret; 923 924 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NODES, true); 925 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 926 if (ret) { 927 dev_err(&hdev->pdev->dev, 928 "failed to dump tm nodes, ret = %d\n", ret); 929 return ret; 930 } 931 932 nodes = (struct hclge_tm_nodes_cmd *)desc.data; 933 934 pos += scnprintf(buf + pos, len - pos, " BASE_ID MAX_NUM\n"); 935 pos += scnprintf(buf + pos, len - pos, "PG %4u %4u\n", 936 nodes->pg_base_id, nodes->pg_num); 937 pos += scnprintf(buf + pos, len - pos, "PRI %4u %4u\n", 938 nodes->pri_base_id, nodes->pri_num); 939 pos += scnprintf(buf + pos, len - pos, "QSET %4u %4u\n", 940 le16_to_cpu(nodes->qset_base_id), 941 le16_to_cpu(nodes->qset_num)); 942 pos += scnprintf(buf + pos, len - pos, "QUEUE %4u %4u\n", 943 le16_to_cpu(nodes->queue_base_id), 944 le16_to_cpu(nodes->queue_num)); 945 946 return 0; 947 } 948 949 static const struct hclge_dbg_item tm_pri_items[] = { 950 { "ID", 4 }, 951 { "MODE", 2 }, 952 { "DWRR", 2 }, 953 { "C_IR_B", 2 }, 954 { "C_IR_U", 2 }, 955 { "C_IR_S", 2 }, 956 { "C_BS_B", 2 }, 957 { "C_BS_S", 2 }, 958 { "C_FLAG", 2 }, 959 { "C_RATE(Mbps)", 2 }, 960 { "P_IR_B", 2 }, 961 { "P_IR_U", 2 }, 962 { "P_IR_S", 2 }, 963 { "P_BS_B", 2 }, 964 { "P_BS_S", 2 }, 965 { "P_FLAG", 2 }, 966 { "P_RATE(Mbps)", 0 } 967 }; 968 969 static int hclge_dbg_dump_tm_pri(struct hclge_dev *hdev, char *buf, int len) 970 { 971 char data_str[ARRAY_SIZE(tm_pri_items)][HCLGE_DBG_DATA_STR_LEN]; 972 struct hclge_tm_shaper_para c_shaper_para, p_shaper_para; 973 char *result[ARRAY_SIZE(tm_pri_items)], *sch_mode_str; 974 char content[HCLGE_DBG_TM_INFO_LEN]; 975 u8 pri_num, sch_mode, weight, i, j; 976 int pos, ret; 977 978 ret = hclge_tm_get_pri_num(hdev, &pri_num); 979 if (ret) 980 return ret; 981 982 for (i = 0; i < ARRAY_SIZE(tm_pri_items); i++) 983 result[i] = &data_str[i][0]; 984 985 hclge_dbg_fill_content(content, sizeof(content), tm_pri_items, 986 NULL, ARRAY_SIZE(tm_pri_items)); 987 pos = scnprintf(buf, len, "%s", content); 988 989 for (i = 0; i < pri_num; i++) { 990 ret = hclge_tm_get_pri_sch_mode(hdev, i, &sch_mode); 991 if (ret) 992 return ret; 993 994 ret = hclge_tm_get_pri_weight(hdev, i, &weight); 995 if (ret) 996 return ret; 997 998 ret = hclge_tm_get_pri_shaper(hdev, i, 999 HCLGE_OPC_TM_PRI_C_SHAPPING, 1000 &c_shaper_para); 1001 if (ret) 1002 return ret; 1003 1004 ret = hclge_tm_get_pri_shaper(hdev, i, 1005 HCLGE_OPC_TM_PRI_P_SHAPPING, 1006 &p_shaper_para); 1007 if (ret) 1008 return ret; 1009 1010 sch_mode_str = sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK ? "dwrr" : 1011 "sp"; 1012 1013 j = 0; 1014 sprintf(result[j++], "%04u", i); 1015 sprintf(result[j++], "%4s", sch_mode_str); 1016 sprintf(result[j++], "%3u", weight); 1017 hclge_dbg_fill_shaper_content(&c_shaper_para, result, &j); 1018 hclge_dbg_fill_shaper_content(&p_shaper_para, result, &j); 1019 hclge_dbg_fill_content(content, sizeof(content), tm_pri_items, 1020 (const char **)result, 1021 ARRAY_SIZE(tm_pri_items)); 1022 pos += scnprintf(buf + pos, len - pos, "%s", content); 1023 } 1024 1025 return 0; 1026 } 1027 1028 static const struct hclge_dbg_item tm_qset_items[] = { 1029 { "ID", 4 }, 1030 { "MAP_PRI", 2 }, 1031 { "LINK_VLD", 2 }, 1032 { "MODE", 2 }, 1033 { "DWRR", 2 }, 1034 { "IR_B", 2 }, 1035 { "IR_U", 2 }, 1036 { "IR_S", 2 }, 1037 { "BS_B", 2 }, 1038 { "BS_S", 2 }, 1039 { "FLAG", 2 }, 1040 { "RATE(Mbps)", 0 } 1041 }; 1042 1043 static int hclge_dbg_dump_tm_qset(struct hclge_dev *hdev, char *buf, int len) 1044 { 1045 char data_str[ARRAY_SIZE(tm_qset_items)][HCLGE_DBG_DATA_STR_LEN]; 1046 char *result[ARRAY_SIZE(tm_qset_items)], *sch_mode_str; 1047 u8 priority, link_vld, sch_mode, weight; 1048 struct hclge_tm_shaper_para shaper_para; 1049 char content[HCLGE_DBG_TM_INFO_LEN]; 1050 u16 qset_num, i; 1051 int ret, pos; 1052 u8 j; 1053 1054 ret = hclge_tm_get_qset_num(hdev, &qset_num); 1055 if (ret) 1056 return ret; 1057 1058 for (i = 0; i < ARRAY_SIZE(tm_qset_items); i++) 1059 result[i] = &data_str[i][0]; 1060 1061 hclge_dbg_fill_content(content, sizeof(content), tm_qset_items, 1062 NULL, ARRAY_SIZE(tm_qset_items)); 1063 pos = scnprintf(buf, len, "%s", content); 1064 1065 for (i = 0; i < qset_num; i++) { 1066 ret = hclge_tm_get_qset_map_pri(hdev, i, &priority, &link_vld); 1067 if (ret) 1068 return ret; 1069 1070 ret = hclge_tm_get_qset_sch_mode(hdev, i, &sch_mode); 1071 if (ret) 1072 return ret; 1073 1074 ret = hclge_tm_get_qset_weight(hdev, i, &weight); 1075 if (ret) 1076 return ret; 1077 1078 ret = hclge_tm_get_qset_shaper(hdev, i, &shaper_para); 1079 if (ret) 1080 return ret; 1081 1082 sch_mode_str = sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK ? "dwrr" : 1083 "sp"; 1084 1085 j = 0; 1086 sprintf(result[j++], "%04u", i); 1087 sprintf(result[j++], "%4u", priority); 1088 sprintf(result[j++], "%4u", link_vld); 1089 sprintf(result[j++], "%4s", sch_mode_str); 1090 sprintf(result[j++], "%3u", weight); 1091 hclge_dbg_fill_shaper_content(&shaper_para, result, &j); 1092 1093 hclge_dbg_fill_content(content, sizeof(content), tm_qset_items, 1094 (const char **)result, 1095 ARRAY_SIZE(tm_qset_items)); 1096 pos += scnprintf(buf + pos, len - pos, "%s", content); 1097 } 1098 1099 return 0; 1100 } 1101 1102 static int hclge_dbg_dump_qos_pause_cfg(struct hclge_dev *hdev, char *buf, 1103 int len) 1104 { 1105 struct hclge_cfg_pause_param_cmd *pause_param; 1106 struct hclge_desc desc; 1107 int pos = 0; 1108 int ret; 1109 1110 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true); 1111 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1112 if (ret) { 1113 dev_err(&hdev->pdev->dev, 1114 "failed to dump qos pause, ret = %d\n", ret); 1115 return ret; 1116 } 1117 1118 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data; 1119 1120 pos += scnprintf(buf + pos, len - pos, "pause_trans_gap: 0x%x\n", 1121 pause_param->pause_trans_gap); 1122 pos += scnprintf(buf + pos, len - pos, "pause_trans_time: 0x%x\n", 1123 le16_to_cpu(pause_param->pause_trans_time)); 1124 return 0; 1125 } 1126 1127 static int hclge_dbg_dump_qos_pri_map(struct hclge_dev *hdev, char *buf, 1128 int len) 1129 { 1130 #define HCLGE_DBG_TC_MASK 0x0F 1131 #define HCLGE_DBG_TC_BIT_WIDTH 4 1132 1133 struct hclge_qos_pri_map_cmd *pri_map; 1134 struct hclge_desc desc; 1135 int pos = 0; 1136 u8 *pri_tc; 1137 u8 tc, i; 1138 int ret; 1139 1140 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, true); 1141 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1142 if (ret) { 1143 dev_err(&hdev->pdev->dev, 1144 "failed to dump qos pri map, ret = %d\n", ret); 1145 return ret; 1146 } 1147 1148 pri_map = (struct hclge_qos_pri_map_cmd *)desc.data; 1149 1150 pos += scnprintf(buf + pos, len - pos, "vlan_to_pri: 0x%x\n", 1151 pri_map->vlan_pri); 1152 pos += scnprintf(buf + pos, len - pos, "PRI TC\n"); 1153 1154 pri_tc = (u8 *)pri_map; 1155 for (i = 0; i < HNAE3_MAX_TC; i++) { 1156 tc = pri_tc[i >> 1] >> ((i & 1) * HCLGE_DBG_TC_BIT_WIDTH); 1157 tc &= HCLGE_DBG_TC_MASK; 1158 pos += scnprintf(buf + pos, len - pos, "%u %u\n", i, tc); 1159 } 1160 1161 return 0; 1162 } 1163 1164 static int hclge_dbg_dump_tx_buf_cfg(struct hclge_dev *hdev, char *buf, int len) 1165 { 1166 struct hclge_tx_buff_alloc_cmd *tx_buf_cmd; 1167 struct hclge_desc desc; 1168 int pos = 0; 1169 int i, ret; 1170 1171 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, true); 1172 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1173 if (ret) { 1174 dev_err(&hdev->pdev->dev, 1175 "failed to dump tx buf, ret = %d\n", ret); 1176 return ret; 1177 } 1178 1179 tx_buf_cmd = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1180 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1181 pos += scnprintf(buf + pos, len - pos, 1182 "tx_packet_buf_tc_%d: 0x%x\n", i, 1183 le16_to_cpu(tx_buf_cmd->tx_pkt_buff[i])); 1184 1185 return pos; 1186 } 1187 1188 static int hclge_dbg_dump_rx_priv_buf_cfg(struct hclge_dev *hdev, char *buf, 1189 int len) 1190 { 1191 struct hclge_rx_priv_buff_cmd *rx_buf_cmd; 1192 struct hclge_desc desc; 1193 int pos = 0; 1194 int i, ret; 1195 1196 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, true); 1197 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1198 if (ret) { 1199 dev_err(&hdev->pdev->dev, 1200 "failed to dump rx priv buf, ret = %d\n", ret); 1201 return ret; 1202 } 1203 1204 pos += scnprintf(buf + pos, len - pos, "\n"); 1205 1206 rx_buf_cmd = (struct hclge_rx_priv_buff_cmd *)desc.data; 1207 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1208 pos += scnprintf(buf + pos, len - pos, 1209 "rx_packet_buf_tc_%d: 0x%x\n", i, 1210 le16_to_cpu(rx_buf_cmd->buf_num[i])); 1211 1212 pos += scnprintf(buf + pos, len - pos, "rx_share_buf: 0x%x\n", 1213 le16_to_cpu(rx_buf_cmd->shared_buf)); 1214 1215 return pos; 1216 } 1217 1218 static int hclge_dbg_dump_rx_common_wl_cfg(struct hclge_dev *hdev, char *buf, 1219 int len) 1220 { 1221 struct hclge_rx_com_wl *rx_com_wl; 1222 struct hclge_desc desc; 1223 int pos = 0; 1224 int ret; 1225 1226 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, true); 1227 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1228 if (ret) { 1229 dev_err(&hdev->pdev->dev, 1230 "failed to dump rx common wl, ret = %d\n", ret); 1231 return ret; 1232 } 1233 1234 rx_com_wl = (struct hclge_rx_com_wl *)desc.data; 1235 pos += scnprintf(buf + pos, len - pos, "\n"); 1236 pos += scnprintf(buf + pos, len - pos, 1237 "rx_com_wl: high: 0x%x, low: 0x%x\n", 1238 le16_to_cpu(rx_com_wl->com_wl.high), 1239 le16_to_cpu(rx_com_wl->com_wl.low)); 1240 1241 return pos; 1242 } 1243 1244 static int hclge_dbg_dump_rx_global_pkt_cnt(struct hclge_dev *hdev, char *buf, 1245 int len) 1246 { 1247 struct hclge_rx_com_wl *rx_packet_cnt; 1248 struct hclge_desc desc; 1249 int pos = 0; 1250 int ret; 1251 1252 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_GBL_PKT_CNT, true); 1253 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1254 if (ret) { 1255 dev_err(&hdev->pdev->dev, 1256 "failed to dump rx global pkt cnt, ret = %d\n", ret); 1257 return ret; 1258 } 1259 1260 rx_packet_cnt = (struct hclge_rx_com_wl *)desc.data; 1261 pos += scnprintf(buf + pos, len - pos, 1262 "rx_global_packet_cnt: high: 0x%x, low: 0x%x\n", 1263 le16_to_cpu(rx_packet_cnt->com_wl.high), 1264 le16_to_cpu(rx_packet_cnt->com_wl.low)); 1265 1266 return pos; 1267 } 1268 1269 static int hclge_dbg_dump_rx_priv_wl_buf_cfg(struct hclge_dev *hdev, char *buf, 1270 int len) 1271 { 1272 struct hclge_rx_priv_wl_buf *rx_priv_wl; 1273 struct hclge_desc desc[2]; 1274 int pos = 0; 1275 int i, ret; 1276 1277 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_RX_PRIV_WL_ALLOC, true); 1278 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1279 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_RX_PRIV_WL_ALLOC, true); 1280 ret = hclge_cmd_send(&hdev->hw, desc, 2); 1281 if (ret) { 1282 dev_err(&hdev->pdev->dev, 1283 "failed to dump rx priv wl buf, ret = %d\n", ret); 1284 return ret; 1285 } 1286 1287 rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[0].data; 1288 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 1289 pos += scnprintf(buf + pos, len - pos, 1290 "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n", i, 1291 le16_to_cpu(rx_priv_wl->tc_wl[i].high), 1292 le16_to_cpu(rx_priv_wl->tc_wl[i].low)); 1293 1294 rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[1].data; 1295 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 1296 pos += scnprintf(buf + pos, len - pos, 1297 "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n", 1298 i + HCLGE_TC_NUM_ONE_DESC, 1299 le16_to_cpu(rx_priv_wl->tc_wl[i].high), 1300 le16_to_cpu(rx_priv_wl->tc_wl[i].low)); 1301 1302 return pos; 1303 } 1304 1305 static int hclge_dbg_dump_rx_common_threshold_cfg(struct hclge_dev *hdev, 1306 char *buf, int len) 1307 { 1308 struct hclge_rx_com_thrd *rx_com_thrd; 1309 struct hclge_desc desc[2]; 1310 int pos = 0; 1311 int i, ret; 1312 1313 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_RX_COM_THRD_ALLOC, true); 1314 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1315 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_RX_COM_THRD_ALLOC, true); 1316 ret = hclge_cmd_send(&hdev->hw, desc, 2); 1317 if (ret) { 1318 dev_err(&hdev->pdev->dev, 1319 "failed to dump rx common threshold, ret = %d\n", ret); 1320 return ret; 1321 } 1322 1323 pos += scnprintf(buf + pos, len - pos, "\n"); 1324 rx_com_thrd = (struct hclge_rx_com_thrd *)desc[0].data; 1325 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 1326 pos += scnprintf(buf + pos, len - pos, 1327 "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n", i, 1328 le16_to_cpu(rx_com_thrd->com_thrd[i].high), 1329 le16_to_cpu(rx_com_thrd->com_thrd[i].low)); 1330 1331 rx_com_thrd = (struct hclge_rx_com_thrd *)desc[1].data; 1332 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 1333 pos += scnprintf(buf + pos, len - pos, 1334 "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n", 1335 i + HCLGE_TC_NUM_ONE_DESC, 1336 le16_to_cpu(rx_com_thrd->com_thrd[i].high), 1337 le16_to_cpu(rx_com_thrd->com_thrd[i].low)); 1338 1339 return pos; 1340 } 1341 1342 static int hclge_dbg_dump_qos_buf_cfg(struct hclge_dev *hdev, char *buf, 1343 int len) 1344 { 1345 int pos = 0; 1346 int ret; 1347 1348 ret = hclge_dbg_dump_tx_buf_cfg(hdev, buf + pos, len - pos); 1349 if (ret < 0) 1350 return ret; 1351 pos += ret; 1352 1353 ret = hclge_dbg_dump_rx_priv_buf_cfg(hdev, buf + pos, len - pos); 1354 if (ret < 0) 1355 return ret; 1356 pos += ret; 1357 1358 ret = hclge_dbg_dump_rx_common_wl_cfg(hdev, buf + pos, len - pos); 1359 if (ret < 0) 1360 return ret; 1361 pos += ret; 1362 1363 ret = hclge_dbg_dump_rx_global_pkt_cnt(hdev, buf + pos, len - pos); 1364 if (ret < 0) 1365 return ret; 1366 pos += ret; 1367 1368 pos += scnprintf(buf + pos, len - pos, "\n"); 1369 if (!hnae3_dev_dcb_supported(hdev)) 1370 return 0; 1371 1372 ret = hclge_dbg_dump_rx_priv_wl_buf_cfg(hdev, buf + pos, len - pos); 1373 if (ret < 0) 1374 return ret; 1375 pos += ret; 1376 1377 ret = hclge_dbg_dump_rx_common_threshold_cfg(hdev, buf + pos, 1378 len - pos); 1379 if (ret < 0) 1380 return ret; 1381 1382 return 0; 1383 } 1384 1385 static int hclge_dbg_dump_mng_table(struct hclge_dev *hdev, char *buf, int len) 1386 { 1387 struct hclge_mac_ethertype_idx_rd_cmd *req0; 1388 struct hclge_desc desc; 1389 u32 msg_egress_port; 1390 int pos = 0; 1391 int ret, i; 1392 1393 pos += scnprintf(buf + pos, len - pos, 1394 "entry mac_addr mask ether "); 1395 pos += scnprintf(buf + pos, len - pos, 1396 "mask vlan mask i_map i_dir e_type "); 1397 pos += scnprintf(buf + pos, len - pos, "pf_id vf_id q_id drop\n"); 1398 1399 for (i = 0; i < HCLGE_DBG_MNG_TBL_MAX; i++) { 1400 hclge_cmd_setup_basic_desc(&desc, HCLGE_MAC_ETHERTYPE_IDX_RD, 1401 true); 1402 req0 = (struct hclge_mac_ethertype_idx_rd_cmd *)&desc.data; 1403 req0->index = cpu_to_le16(i); 1404 1405 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1406 if (ret) { 1407 dev_err(&hdev->pdev->dev, 1408 "failed to dump manage table, ret = %d\n", ret); 1409 return ret; 1410 } 1411 1412 if (!req0->resp_code) 1413 continue; 1414 1415 pos += scnprintf(buf + pos, len - pos, "%02u %pM ", 1416 le16_to_cpu(req0->index), req0->mac_addr); 1417 1418 pos += scnprintf(buf + pos, len - pos, 1419 "%x %04x %x %04x ", 1420 !!(req0->flags & HCLGE_DBG_MNG_MAC_MASK_B), 1421 le16_to_cpu(req0->ethter_type), 1422 !!(req0->flags & HCLGE_DBG_MNG_ETHER_MASK_B), 1423 le16_to_cpu(req0->vlan_tag) & 1424 HCLGE_DBG_MNG_VLAN_TAG); 1425 1426 pos += scnprintf(buf + pos, len - pos, 1427 "%x %02x %02x ", 1428 !!(req0->flags & HCLGE_DBG_MNG_VLAN_MASK_B), 1429 req0->i_port_bitmap, req0->i_port_direction); 1430 1431 msg_egress_port = le16_to_cpu(req0->egress_port); 1432 pos += scnprintf(buf + pos, len - pos, 1433 "%x %x %02x %04x %x\n", 1434 !!(msg_egress_port & HCLGE_DBG_MNG_E_TYPE_B), 1435 msg_egress_port & HCLGE_DBG_MNG_PF_ID, 1436 (msg_egress_port >> 3) & HCLGE_DBG_MNG_VF_ID, 1437 le16_to_cpu(req0->egress_queue), 1438 !!(msg_egress_port & HCLGE_DBG_MNG_DROP_B)); 1439 } 1440 1441 return 0; 1442 } 1443 1444 #define HCLGE_DBG_TCAM_BUF_SIZE 256 1445 1446 static int hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, bool sel_x, 1447 char *tcam_buf, 1448 struct hclge_dbg_tcam_msg tcam_msg) 1449 { 1450 struct hclge_fd_tcam_config_1_cmd *req1; 1451 struct hclge_fd_tcam_config_2_cmd *req2; 1452 struct hclge_fd_tcam_config_3_cmd *req3; 1453 struct hclge_desc desc[3]; 1454 int pos = 0; 1455 int ret, i; 1456 u32 *req; 1457 1458 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, true); 1459 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1460 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, true); 1461 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1462 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, true); 1463 1464 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 1465 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 1466 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 1467 1468 req1->stage = tcam_msg.stage; 1469 req1->xy_sel = sel_x ? 1 : 0; 1470 req1->index = cpu_to_le32(tcam_msg.loc); 1471 1472 ret = hclge_cmd_send(&hdev->hw, desc, 3); 1473 if (ret) 1474 return ret; 1475 1476 pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos, 1477 "read result tcam key %s(%u):\n", sel_x ? "x" : "y", 1478 tcam_msg.loc); 1479 1480 /* tcam_data0 ~ tcam_data1 */ 1481 req = (u32 *)req1->tcam_data; 1482 for (i = 0; i < 2; i++) 1483 pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos, 1484 "%08x\n", *req++); 1485 1486 /* tcam_data2 ~ tcam_data7 */ 1487 req = (u32 *)req2->tcam_data; 1488 for (i = 0; i < 6; i++) 1489 pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos, 1490 "%08x\n", *req++); 1491 1492 /* tcam_data8 ~ tcam_data12 */ 1493 req = (u32 *)req3->tcam_data; 1494 for (i = 0; i < 5; i++) 1495 pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos, 1496 "%08x\n", *req++); 1497 1498 return ret; 1499 } 1500 1501 static int hclge_dbg_get_rules_location(struct hclge_dev *hdev, u16 *rule_locs) 1502 { 1503 struct hclge_fd_rule *rule; 1504 struct hlist_node *node; 1505 int cnt = 0; 1506 1507 spin_lock_bh(&hdev->fd_rule_lock); 1508 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 1509 rule_locs[cnt] = rule->location; 1510 cnt++; 1511 } 1512 spin_unlock_bh(&hdev->fd_rule_lock); 1513 1514 if (cnt != hdev->hclge_fd_rule_num || cnt == 0) 1515 return -EINVAL; 1516 1517 return cnt; 1518 } 1519 1520 static int hclge_dbg_dump_fd_tcam(struct hclge_dev *hdev, char *buf, int len) 1521 { 1522 u32 rule_num = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 1523 struct hclge_dbg_tcam_msg tcam_msg; 1524 int i, ret, rule_cnt; 1525 u16 *rule_locs; 1526 char *tcam_buf; 1527 int pos = 0; 1528 1529 if (!hnae3_dev_fd_supported(hdev)) { 1530 dev_err(&hdev->pdev->dev, 1531 "Only FD-supported dev supports dump fd tcam\n"); 1532 return -EOPNOTSUPP; 1533 } 1534 1535 if (!hdev->hclge_fd_rule_num || !rule_num) 1536 return 0; 1537 1538 rule_locs = kcalloc(rule_num, sizeof(u16), GFP_KERNEL); 1539 if (!rule_locs) 1540 return -ENOMEM; 1541 1542 tcam_buf = kzalloc(HCLGE_DBG_TCAM_BUF_SIZE, GFP_KERNEL); 1543 if (!tcam_buf) { 1544 kfree(rule_locs); 1545 return -ENOMEM; 1546 } 1547 1548 rule_cnt = hclge_dbg_get_rules_location(hdev, rule_locs); 1549 if (rule_cnt < 0) { 1550 ret = rule_cnt; 1551 dev_err(&hdev->pdev->dev, 1552 "failed to get rule number, ret = %d\n", ret); 1553 goto out; 1554 } 1555 1556 ret = 0; 1557 for (i = 0; i < rule_cnt; i++) { 1558 tcam_msg.stage = HCLGE_FD_STAGE_1; 1559 tcam_msg.loc = rule_locs[i]; 1560 1561 ret = hclge_dbg_fd_tcam_read(hdev, true, tcam_buf, tcam_msg); 1562 if (ret) { 1563 dev_err(&hdev->pdev->dev, 1564 "failed to get fd tcam key x, ret = %d\n", ret); 1565 goto out; 1566 } 1567 1568 pos += scnprintf(buf + pos, len - pos, "%s", tcam_buf); 1569 1570 ret = hclge_dbg_fd_tcam_read(hdev, false, tcam_buf, tcam_msg); 1571 if (ret) { 1572 dev_err(&hdev->pdev->dev, 1573 "failed to get fd tcam key y, ret = %d\n", ret); 1574 goto out; 1575 } 1576 1577 pos += scnprintf(buf + pos, len - pos, "%s", tcam_buf); 1578 } 1579 1580 out: 1581 kfree(tcam_buf); 1582 kfree(rule_locs); 1583 return ret; 1584 } 1585 1586 static int hclge_dbg_dump_fd_counter(struct hclge_dev *hdev, char *buf, int len) 1587 { 1588 u8 func_num = pci_num_vf(hdev->pdev) + 1; /* pf and enabled vf num */ 1589 struct hclge_fd_ad_cnt_read_cmd *req; 1590 char str_id[HCLGE_DBG_ID_LEN]; 1591 struct hclge_desc desc; 1592 int pos = 0; 1593 int ret; 1594 u64 cnt; 1595 u8 i; 1596 1597 pos += scnprintf(buf + pos, len - pos, 1598 "func_id\thit_times\n"); 1599 1600 for (i = 0; i < func_num; i++) { 1601 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_CNT_OP, true); 1602 req = (struct hclge_fd_ad_cnt_read_cmd *)desc.data; 1603 req->index = cpu_to_le16(i); 1604 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1605 if (ret) { 1606 dev_err(&hdev->pdev->dev, "failed to get fd counter, ret = %d\n", 1607 ret); 1608 return ret; 1609 } 1610 cnt = le64_to_cpu(req->cnt); 1611 hclge_dbg_get_func_id_str(str_id, i); 1612 pos += scnprintf(buf + pos, len - pos, 1613 "%s\t%llu\n", str_id, cnt); 1614 } 1615 1616 return 0; 1617 } 1618 1619 int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len) 1620 { 1621 int pos = 0; 1622 1623 pos += scnprintf(buf + pos, len - pos, "PF reset count: %u\n", 1624 hdev->rst_stats.pf_rst_cnt); 1625 pos += scnprintf(buf + pos, len - pos, "FLR reset count: %u\n", 1626 hdev->rst_stats.flr_rst_cnt); 1627 pos += scnprintf(buf + pos, len - pos, "GLOBAL reset count: %u\n", 1628 hdev->rst_stats.global_rst_cnt); 1629 pos += scnprintf(buf + pos, len - pos, "IMP reset count: %u\n", 1630 hdev->rst_stats.imp_rst_cnt); 1631 pos += scnprintf(buf + pos, len - pos, "reset done count: %u\n", 1632 hdev->rst_stats.reset_done_cnt); 1633 pos += scnprintf(buf + pos, len - pos, "HW reset done count: %u\n", 1634 hdev->rst_stats.hw_reset_done_cnt); 1635 pos += scnprintf(buf + pos, len - pos, "reset count: %u\n", 1636 hdev->rst_stats.reset_cnt); 1637 pos += scnprintf(buf + pos, len - pos, "reset fail count: %u\n", 1638 hdev->rst_stats.reset_fail_cnt); 1639 pos += scnprintf(buf + pos, len - pos, 1640 "vector0 interrupt enable status: 0x%x\n", 1641 hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_REG_BASE)); 1642 pos += scnprintf(buf + pos, len - pos, "reset interrupt source: 0x%x\n", 1643 hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG)); 1644 pos += scnprintf(buf + pos, len - pos, "reset interrupt status: 0x%x\n", 1645 hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS)); 1646 pos += scnprintf(buf + pos, len - pos, "RAS interrupt status: 0x%x\n", 1647 hclge_read_dev(&hdev->hw, 1648 HCLGE_RAS_PF_OTHER_INT_STS_REG)); 1649 pos += scnprintf(buf + pos, len - pos, "hardware reset status: 0x%x\n", 1650 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 1651 pos += scnprintf(buf + pos, len - pos, "handshake status: 0x%x\n", 1652 hclge_read_dev(&hdev->hw, HCLGE_NIC_CSQ_DEPTH_REG)); 1653 pos += scnprintf(buf + pos, len - pos, "function reset status: 0x%x\n", 1654 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING)); 1655 pos += scnprintf(buf + pos, len - pos, "hdev state: 0x%lx\n", 1656 hdev->state); 1657 1658 return 0; 1659 } 1660 1661 static int hclge_dbg_dump_serv_info(struct hclge_dev *hdev, char *buf, int len) 1662 { 1663 unsigned long rem_nsec; 1664 int pos = 0; 1665 u64 lc; 1666 1667 lc = local_clock(); 1668 rem_nsec = do_div(lc, HCLGE_BILLION_NANO_SECONDS); 1669 1670 pos += scnprintf(buf + pos, len - pos, "local_clock: [%5lu.%06lu]\n", 1671 (unsigned long)lc, rem_nsec / 1000); 1672 pos += scnprintf(buf + pos, len - pos, "delta: %u(ms)\n", 1673 jiffies_to_msecs(jiffies - hdev->last_serv_processed)); 1674 pos += scnprintf(buf + pos, len - pos, 1675 "last_service_task_processed: %lu(jiffies)\n", 1676 hdev->last_serv_processed); 1677 pos += scnprintf(buf + pos, len - pos, "last_service_task_cnt: %lu\n", 1678 hdev->serv_processed_cnt); 1679 1680 return 0; 1681 } 1682 1683 static int hclge_dbg_dump_interrupt(struct hclge_dev *hdev, char *buf, int len) 1684 { 1685 int pos = 0; 1686 1687 pos += scnprintf(buf + pos, len - pos, "num_nic_msi: %u\n", 1688 hdev->num_nic_msi); 1689 pos += scnprintf(buf + pos, len - pos, "num_roce_msi: %u\n", 1690 hdev->num_roce_msi); 1691 pos += scnprintf(buf + pos, len - pos, "num_msi_used: %u\n", 1692 hdev->num_msi_used); 1693 pos += scnprintf(buf + pos, len - pos, "num_msi_left: %u\n", 1694 hdev->num_msi_left); 1695 1696 return 0; 1697 } 1698 1699 static void hclge_dbg_imp_info_data_print(struct hclge_desc *desc_src, 1700 char *buf, int len, u32 bd_num) 1701 { 1702 #define HCLGE_DBG_IMP_INFO_PRINT_OFFSET 0x2 1703 1704 struct hclge_desc *desc_index = desc_src; 1705 u32 offset = 0; 1706 int pos = 0; 1707 u32 i, j; 1708 1709 pos += scnprintf(buf + pos, len - pos, "offset | data\n"); 1710 1711 for (i = 0; i < bd_num; i++) { 1712 j = 0; 1713 while (j < HCLGE_DESC_DATA_LEN - 1) { 1714 pos += scnprintf(buf + pos, len - pos, "0x%04x | ", 1715 offset); 1716 pos += scnprintf(buf + pos, len - pos, "0x%08x ", 1717 le32_to_cpu(desc_index->data[j++])); 1718 pos += scnprintf(buf + pos, len - pos, "0x%08x\n", 1719 le32_to_cpu(desc_index->data[j++])); 1720 offset += sizeof(u32) * HCLGE_DBG_IMP_INFO_PRINT_OFFSET; 1721 } 1722 desc_index++; 1723 } 1724 } 1725 1726 static int 1727 hclge_dbg_get_imp_stats_info(struct hclge_dev *hdev, char *buf, int len) 1728 { 1729 struct hclge_get_imp_bd_cmd *req; 1730 struct hclge_desc *desc_src; 1731 struct hclge_desc desc; 1732 u32 bd_num; 1733 int ret; 1734 1735 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_IMP_STATS_BD, true); 1736 1737 req = (struct hclge_get_imp_bd_cmd *)desc.data; 1738 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1739 if (ret) { 1740 dev_err(&hdev->pdev->dev, 1741 "failed to get imp statistics bd number, ret = %d\n", 1742 ret); 1743 return ret; 1744 } 1745 1746 bd_num = le32_to_cpu(req->bd_num); 1747 if (!bd_num) { 1748 dev_err(&hdev->pdev->dev, "imp statistics bd number is 0!\n"); 1749 return -EINVAL; 1750 } 1751 1752 desc_src = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL); 1753 if (!desc_src) 1754 return -ENOMEM; 1755 1756 ret = hclge_dbg_cmd_send(hdev, desc_src, 0, bd_num, 1757 HCLGE_OPC_IMP_STATS_INFO); 1758 if (ret) { 1759 kfree(desc_src); 1760 dev_err(&hdev->pdev->dev, 1761 "failed to get imp statistics, ret = %d\n", ret); 1762 return ret; 1763 } 1764 1765 hclge_dbg_imp_info_data_print(desc_src, buf, len, bd_num); 1766 1767 kfree(desc_src); 1768 1769 return 0; 1770 } 1771 1772 #define HCLGE_CMD_NCL_CONFIG_BD_NUM 5 1773 #define HCLGE_MAX_NCL_CONFIG_LENGTH 16384 1774 1775 static void hclge_ncl_config_data_print(struct hclge_desc *desc, int *index, 1776 char *buf, int *len, int *pos) 1777 { 1778 #define HCLGE_CMD_DATA_NUM 6 1779 1780 int offset = HCLGE_MAX_NCL_CONFIG_LENGTH - *index; 1781 int i, j; 1782 1783 for (i = 0; i < HCLGE_CMD_NCL_CONFIG_BD_NUM; i++) { 1784 for (j = 0; j < HCLGE_CMD_DATA_NUM; j++) { 1785 if (i == 0 && j == 0) 1786 continue; 1787 1788 *pos += scnprintf(buf + *pos, *len - *pos, 1789 "0x%04x | 0x%08x\n", offset, 1790 le32_to_cpu(desc[i].data[j])); 1791 1792 offset += sizeof(u32); 1793 *index -= sizeof(u32); 1794 1795 if (*index <= 0) 1796 return; 1797 } 1798 } 1799 } 1800 1801 static int 1802 hclge_dbg_dump_ncl_config(struct hclge_dev *hdev, char *buf, int len) 1803 { 1804 #define HCLGE_NCL_CONFIG_LENGTH_IN_EACH_CMD (20 + 24 * 4) 1805 1806 struct hclge_desc desc[HCLGE_CMD_NCL_CONFIG_BD_NUM]; 1807 int bd_num = HCLGE_CMD_NCL_CONFIG_BD_NUM; 1808 int index = HCLGE_MAX_NCL_CONFIG_LENGTH; 1809 int pos = 0; 1810 u32 data0; 1811 int ret; 1812 1813 pos += scnprintf(buf + pos, len - pos, "offset | data\n"); 1814 1815 while (index > 0) { 1816 data0 = HCLGE_MAX_NCL_CONFIG_LENGTH - index; 1817 if (index >= HCLGE_NCL_CONFIG_LENGTH_IN_EACH_CMD) 1818 data0 |= HCLGE_NCL_CONFIG_LENGTH_IN_EACH_CMD << 16; 1819 else 1820 data0 |= (u32)index << 16; 1821 ret = hclge_dbg_cmd_send(hdev, desc, data0, bd_num, 1822 HCLGE_OPC_QUERY_NCL_CONFIG); 1823 if (ret) 1824 return ret; 1825 1826 hclge_ncl_config_data_print(desc, &index, buf, &len, &pos); 1827 } 1828 1829 return 0; 1830 } 1831 1832 static int hclge_dbg_dump_loopback(struct hclge_dev *hdev, char *buf, int len) 1833 { 1834 struct phy_device *phydev = hdev->hw.mac.phydev; 1835 struct hclge_config_mac_mode_cmd *req_app; 1836 struct hclge_common_lb_cmd *req_common; 1837 struct hclge_desc desc; 1838 u8 loopback_en; 1839 int pos = 0; 1840 int ret; 1841 1842 req_app = (struct hclge_config_mac_mode_cmd *)desc.data; 1843 req_common = (struct hclge_common_lb_cmd *)desc.data; 1844 1845 pos += scnprintf(buf + pos, len - pos, "mac id: %u\n", 1846 hdev->hw.mac.mac_id); 1847 1848 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 1849 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1850 if (ret) { 1851 dev_err(&hdev->pdev->dev, 1852 "failed to dump app loopback status, ret = %d\n", ret); 1853 return ret; 1854 } 1855 1856 loopback_en = hnae3_get_bit(le32_to_cpu(req_app->txrx_pad_fcs_loop_en), 1857 HCLGE_MAC_APP_LP_B); 1858 pos += scnprintf(buf + pos, len - pos, "app loopback: %s\n", 1859 state_str[loopback_en]); 1860 1861 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, true); 1862 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1863 if (ret) { 1864 dev_err(&hdev->pdev->dev, 1865 "failed to dump common loopback status, ret = %d\n", 1866 ret); 1867 return ret; 1868 } 1869 1870 loopback_en = req_common->enable & HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 1871 pos += scnprintf(buf + pos, len - pos, "serdes serial loopback: %s\n", 1872 state_str[loopback_en]); 1873 1874 loopback_en = req_common->enable & 1875 HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B ? 1 : 0; 1876 pos += scnprintf(buf + pos, len - pos, "serdes parallel loopback: %s\n", 1877 state_str[loopback_en]); 1878 1879 if (phydev) { 1880 loopback_en = phydev->loopback_enabled; 1881 pos += scnprintf(buf + pos, len - pos, "phy loopback: %s\n", 1882 state_str[loopback_en]); 1883 } else if (hnae3_dev_phy_imp_supported(hdev)) { 1884 loopback_en = req_common->enable & 1885 HCLGE_CMD_GE_PHY_INNER_LOOP_B; 1886 pos += scnprintf(buf + pos, len - pos, "phy loopback: %s\n", 1887 state_str[loopback_en]); 1888 } 1889 1890 return 0; 1891 } 1892 1893 /* hclge_dbg_dump_mac_tnl_status: print message about mac tnl interrupt 1894 * @hdev: pointer to struct hclge_dev 1895 */ 1896 static int 1897 hclge_dbg_dump_mac_tnl_status(struct hclge_dev *hdev, char *buf, int len) 1898 { 1899 struct hclge_mac_tnl_stats stats; 1900 unsigned long rem_nsec; 1901 int pos = 0; 1902 1903 pos += scnprintf(buf + pos, len - pos, 1904 "Recently generated mac tnl interruption:\n"); 1905 1906 while (kfifo_get(&hdev->mac_tnl_log, &stats)) { 1907 rem_nsec = do_div(stats.time, HCLGE_BILLION_NANO_SECONDS); 1908 1909 pos += scnprintf(buf + pos, len - pos, 1910 "[%07lu.%03lu] status = 0x%x\n", 1911 (unsigned long)stats.time, rem_nsec / 1000, 1912 stats.status); 1913 } 1914 1915 return 0; 1916 } 1917 1918 1919 static const struct hclge_dbg_item mac_list_items[] = { 1920 { "FUNC_ID", 2 }, 1921 { "MAC_ADDR", 12 }, 1922 { "STATE", 2 }, 1923 }; 1924 1925 static void hclge_dbg_dump_mac_list(struct hclge_dev *hdev, char *buf, int len, 1926 bool is_unicast) 1927 { 1928 char data_str[ARRAY_SIZE(mac_list_items)][HCLGE_DBG_DATA_STR_LEN]; 1929 char content[HCLGE_DBG_INFO_LEN], str_id[HCLGE_DBG_ID_LEN]; 1930 char *result[ARRAY_SIZE(mac_list_items)]; 1931 struct hclge_mac_node *mac_node, *tmp; 1932 struct hclge_vport *vport; 1933 struct list_head *list; 1934 u32 func_id; 1935 int pos = 0; 1936 int i; 1937 1938 for (i = 0; i < ARRAY_SIZE(mac_list_items); i++) 1939 result[i] = &data_str[i][0]; 1940 1941 pos += scnprintf(buf + pos, len - pos, "%s MAC_LIST:\n", 1942 is_unicast ? "UC" : "MC"); 1943 hclge_dbg_fill_content(content, sizeof(content), mac_list_items, 1944 NULL, ARRAY_SIZE(mac_list_items)); 1945 pos += scnprintf(buf + pos, len - pos, "%s", content); 1946 1947 for (func_id = 0; func_id < hdev->num_alloc_vport; func_id++) { 1948 vport = &hdev->vport[func_id]; 1949 list = is_unicast ? &vport->uc_mac_list : &vport->mc_mac_list; 1950 spin_lock_bh(&vport->mac_list_lock); 1951 list_for_each_entry_safe(mac_node, tmp, list, node) { 1952 i = 0; 1953 result[i++] = hclge_dbg_get_func_id_str(str_id, 1954 func_id); 1955 sprintf(result[i++], "%pM", mac_node->mac_addr); 1956 sprintf(result[i++], "%5s", 1957 hclge_mac_state_str[mac_node->state]); 1958 hclge_dbg_fill_content(content, sizeof(content), 1959 mac_list_items, 1960 (const char **)result, 1961 ARRAY_SIZE(mac_list_items)); 1962 pos += scnprintf(buf + pos, len - pos, "%s", content); 1963 } 1964 spin_unlock_bh(&vport->mac_list_lock); 1965 } 1966 } 1967 1968 static int hclge_dbg_dump_umv_info(struct hclge_dev *hdev, char *buf, int len) 1969 { 1970 u8 func_num = pci_num_vf(hdev->pdev) + 1; 1971 struct hclge_vport *vport; 1972 int pos = 0; 1973 u8 i; 1974 1975 pos += scnprintf(buf, len, "num_alloc_vport : %u\n", 1976 hdev->num_alloc_vport); 1977 pos += scnprintf(buf + pos, len - pos, "max_umv_size : %u\n", 1978 hdev->max_umv_size); 1979 pos += scnprintf(buf + pos, len - pos, "wanted_umv_size : %u\n", 1980 hdev->wanted_umv_size); 1981 pos += scnprintf(buf + pos, len - pos, "priv_umv_size : %u\n", 1982 hdev->priv_umv_size); 1983 1984 mutex_lock(&hdev->vport_lock); 1985 pos += scnprintf(buf + pos, len - pos, "share_umv_size : %u\n", 1986 hdev->share_umv_size); 1987 for (i = 0; i < func_num; i++) { 1988 vport = &hdev->vport[i]; 1989 pos += scnprintf(buf + pos, len - pos, 1990 "vport(%u) used_umv_num : %u\n", 1991 i, vport->used_umv_num); 1992 } 1993 mutex_unlock(&hdev->vport_lock); 1994 1995 return 0; 1996 } 1997 1998 static int hclge_get_vlan_rx_offload_cfg(struct hclge_dev *hdev, u8 vf_id, 1999 struct hclge_dbg_vlan_cfg *vlan_cfg) 2000 { 2001 struct hclge_vport_vtag_rx_cfg_cmd *req; 2002 struct hclge_desc desc; 2003 u16 bmap_index; 2004 u8 rx_cfg; 2005 int ret; 2006 2007 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, true); 2008 2009 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 2010 req->vf_offset = vf_id / HCLGE_VF_NUM_PER_CMD; 2011 bmap_index = vf_id % HCLGE_VF_NUM_PER_CMD / HCLGE_VF_NUM_PER_BYTE; 2012 req->vf_bitmap[bmap_index] = 1U << (vf_id % HCLGE_VF_NUM_PER_BYTE); 2013 2014 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2015 if (ret) { 2016 dev_err(&hdev->pdev->dev, 2017 "failed to get vport%u rxvlan cfg, ret = %d\n", 2018 vf_id, ret); 2019 return ret; 2020 } 2021 2022 rx_cfg = req->vport_vlan_cfg; 2023 vlan_cfg->strip_tag1 = hnae3_get_bit(rx_cfg, HCLGE_REM_TAG1_EN_B); 2024 vlan_cfg->strip_tag2 = hnae3_get_bit(rx_cfg, HCLGE_REM_TAG2_EN_B); 2025 vlan_cfg->drop_tag1 = hnae3_get_bit(rx_cfg, HCLGE_DISCARD_TAG1_EN_B); 2026 vlan_cfg->drop_tag2 = hnae3_get_bit(rx_cfg, HCLGE_DISCARD_TAG2_EN_B); 2027 vlan_cfg->pri_only1 = hnae3_get_bit(rx_cfg, HCLGE_SHOW_TAG1_EN_B); 2028 vlan_cfg->pri_only2 = hnae3_get_bit(rx_cfg, HCLGE_SHOW_TAG2_EN_B); 2029 2030 return 0; 2031 } 2032 2033 static int hclge_get_vlan_tx_offload_cfg(struct hclge_dev *hdev, u8 vf_id, 2034 struct hclge_dbg_vlan_cfg *vlan_cfg) 2035 { 2036 struct hclge_vport_vtag_tx_cfg_cmd *req; 2037 struct hclge_desc desc; 2038 u16 bmap_index; 2039 u8 tx_cfg; 2040 int ret; 2041 2042 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, true); 2043 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 2044 req->vf_offset = vf_id / HCLGE_VF_NUM_PER_CMD; 2045 bmap_index = vf_id % HCLGE_VF_NUM_PER_CMD / HCLGE_VF_NUM_PER_BYTE; 2046 req->vf_bitmap[bmap_index] = 1U << (vf_id % HCLGE_VF_NUM_PER_BYTE); 2047 2048 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2049 if (ret) { 2050 dev_err(&hdev->pdev->dev, 2051 "failed to get vport%u txvlan cfg, ret = %d\n", 2052 vf_id, ret); 2053 return ret; 2054 } 2055 2056 tx_cfg = req->vport_vlan_cfg; 2057 vlan_cfg->pvid = le16_to_cpu(req->def_vlan_tag1); 2058 2059 vlan_cfg->accept_tag1 = hnae3_get_bit(tx_cfg, HCLGE_ACCEPT_TAG1_B); 2060 vlan_cfg->accept_tag2 = hnae3_get_bit(tx_cfg, HCLGE_ACCEPT_TAG2_B); 2061 vlan_cfg->accept_untag1 = hnae3_get_bit(tx_cfg, HCLGE_ACCEPT_UNTAG1_B); 2062 vlan_cfg->accept_untag2 = hnae3_get_bit(tx_cfg, HCLGE_ACCEPT_UNTAG2_B); 2063 vlan_cfg->insert_tag1 = hnae3_get_bit(tx_cfg, HCLGE_PORT_INS_TAG1_EN_B); 2064 vlan_cfg->insert_tag2 = hnae3_get_bit(tx_cfg, HCLGE_PORT_INS_TAG2_EN_B); 2065 vlan_cfg->shift_tag = hnae3_get_bit(tx_cfg, HCLGE_TAG_SHIFT_MODE_EN_B); 2066 2067 return 0; 2068 } 2069 2070 static int hclge_get_vlan_filter_config_cmd(struct hclge_dev *hdev, 2071 u8 vlan_type, u8 vf_id, 2072 struct hclge_desc *desc) 2073 { 2074 struct hclge_vlan_filter_ctrl_cmd *req; 2075 int ret; 2076 2077 hclge_cmd_setup_basic_desc(desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 2078 req = (struct hclge_vlan_filter_ctrl_cmd *)desc->data; 2079 req->vlan_type = vlan_type; 2080 req->vf_id = vf_id; 2081 2082 ret = hclge_cmd_send(&hdev->hw, desc, 1); 2083 if (ret) 2084 dev_err(&hdev->pdev->dev, 2085 "failed to get vport%u vlan filter config, ret = %d.\n", 2086 vf_id, ret); 2087 2088 return ret; 2089 } 2090 2091 static int hclge_get_vlan_filter_state(struct hclge_dev *hdev, u8 vlan_type, 2092 u8 vf_id, u8 *vlan_fe) 2093 { 2094 struct hclge_vlan_filter_ctrl_cmd *req; 2095 struct hclge_desc desc; 2096 int ret; 2097 2098 ret = hclge_get_vlan_filter_config_cmd(hdev, vlan_type, vf_id, &desc); 2099 if (ret) 2100 return ret; 2101 2102 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 2103 *vlan_fe = req->vlan_fe; 2104 2105 return 0; 2106 } 2107 2108 static int hclge_get_port_vlan_filter_bypass_state(struct hclge_dev *hdev, 2109 u8 vf_id, u8 *bypass_en) 2110 { 2111 struct hclge_port_vlan_filter_bypass_cmd *req; 2112 struct hclge_desc desc; 2113 int ret; 2114 2115 if (!test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, hdev->ae_dev->caps)) 2116 return 0; 2117 2118 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, true); 2119 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 2120 req->vf_id = vf_id; 2121 2122 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2123 if (ret) { 2124 dev_err(&hdev->pdev->dev, 2125 "failed to get vport%u port vlan filter bypass state, ret = %d.\n", 2126 vf_id, ret); 2127 return ret; 2128 } 2129 2130 *bypass_en = hnae3_get_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B); 2131 2132 return 0; 2133 } 2134 2135 static const struct hclge_dbg_item vlan_filter_items[] = { 2136 { "FUNC_ID", 2 }, 2137 { "I_VF_VLAN_FILTER", 2 }, 2138 { "E_VF_VLAN_FILTER", 2 }, 2139 { "PORT_VLAN_FILTER_BYPASS", 0 } 2140 }; 2141 2142 static const struct hclge_dbg_item vlan_offload_items[] = { 2143 { "FUNC_ID", 2 }, 2144 { "PVID", 4 }, 2145 { "ACCEPT_TAG1", 2 }, 2146 { "ACCEPT_TAG2", 2 }, 2147 { "ACCEPT_UNTAG1", 2 }, 2148 { "ACCEPT_UNTAG2", 2 }, 2149 { "INSERT_TAG1", 2 }, 2150 { "INSERT_TAG2", 2 }, 2151 { "SHIFT_TAG", 2 }, 2152 { "STRIP_TAG1", 2 }, 2153 { "STRIP_TAG2", 2 }, 2154 { "DROP_TAG1", 2 }, 2155 { "DROP_TAG2", 2 }, 2156 { "PRI_ONLY_TAG1", 2 }, 2157 { "PRI_ONLY_TAG2", 0 } 2158 }; 2159 2160 static int hclge_dbg_dump_vlan_filter_config(struct hclge_dev *hdev, char *buf, 2161 int len, int *pos) 2162 { 2163 char content[HCLGE_DBG_VLAN_FLTR_INFO_LEN], str_id[HCLGE_DBG_ID_LEN]; 2164 const char *result[ARRAY_SIZE(vlan_filter_items)]; 2165 u8 i, j, vlan_fe, bypass, ingress, egress; 2166 u8 func_num = pci_num_vf(hdev->pdev) + 1; /* pf and enabled vf num */ 2167 int ret; 2168 2169 ret = hclge_get_vlan_filter_state(hdev, HCLGE_FILTER_TYPE_PORT, 0, 2170 &vlan_fe); 2171 if (ret) 2172 return ret; 2173 ingress = vlan_fe & HCLGE_FILTER_FE_NIC_INGRESS_B; 2174 egress = vlan_fe & HCLGE_FILTER_FE_NIC_EGRESS_B ? 1 : 0; 2175 2176 *pos += scnprintf(buf, len, "I_PORT_VLAN_FILTER: %s\n", 2177 state_str[ingress]); 2178 *pos += scnprintf(buf + *pos, len - *pos, "E_PORT_VLAN_FILTER: %s\n", 2179 state_str[egress]); 2180 2181 hclge_dbg_fill_content(content, sizeof(content), vlan_filter_items, 2182 NULL, ARRAY_SIZE(vlan_filter_items)); 2183 *pos += scnprintf(buf + *pos, len - *pos, "%s", content); 2184 2185 for (i = 0; i < func_num; i++) { 2186 ret = hclge_get_vlan_filter_state(hdev, HCLGE_FILTER_TYPE_VF, i, 2187 &vlan_fe); 2188 if (ret) 2189 return ret; 2190 2191 ingress = vlan_fe & HCLGE_FILTER_FE_NIC_INGRESS_B; 2192 egress = vlan_fe & HCLGE_FILTER_FE_NIC_EGRESS_B ? 1 : 0; 2193 ret = hclge_get_port_vlan_filter_bypass_state(hdev, i, &bypass); 2194 if (ret) 2195 return ret; 2196 j = 0; 2197 result[j++] = hclge_dbg_get_func_id_str(str_id, i); 2198 result[j++] = state_str[ingress]; 2199 result[j++] = state_str[egress]; 2200 result[j++] = 2201 test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, 2202 hdev->ae_dev->caps) ? state_str[bypass] : "NA"; 2203 hclge_dbg_fill_content(content, sizeof(content), 2204 vlan_filter_items, result, 2205 ARRAY_SIZE(vlan_filter_items)); 2206 *pos += scnprintf(buf + *pos, len - *pos, "%s", content); 2207 } 2208 *pos += scnprintf(buf + *pos, len - *pos, "\n"); 2209 2210 return 0; 2211 } 2212 2213 static int hclge_dbg_dump_vlan_offload_config(struct hclge_dev *hdev, char *buf, 2214 int len, int *pos) 2215 { 2216 char str_id[HCLGE_DBG_ID_LEN], str_pvid[HCLGE_DBG_ID_LEN]; 2217 const char *result[ARRAY_SIZE(vlan_offload_items)]; 2218 char content[HCLGE_DBG_VLAN_OFFLOAD_INFO_LEN]; 2219 u8 func_num = pci_num_vf(hdev->pdev) + 1; /* pf and enabled vf num */ 2220 struct hclge_dbg_vlan_cfg vlan_cfg; 2221 int ret; 2222 u8 i, j; 2223 2224 hclge_dbg_fill_content(content, sizeof(content), vlan_offload_items, 2225 NULL, ARRAY_SIZE(vlan_offload_items)); 2226 *pos += scnprintf(buf + *pos, len - *pos, "%s", content); 2227 2228 for (i = 0; i < func_num; i++) { 2229 ret = hclge_get_vlan_tx_offload_cfg(hdev, i, &vlan_cfg); 2230 if (ret) 2231 return ret; 2232 2233 ret = hclge_get_vlan_rx_offload_cfg(hdev, i, &vlan_cfg); 2234 if (ret) 2235 return ret; 2236 2237 sprintf(str_pvid, "%u", vlan_cfg.pvid); 2238 j = 0; 2239 result[j++] = hclge_dbg_get_func_id_str(str_id, i); 2240 result[j++] = str_pvid; 2241 result[j++] = state_str[vlan_cfg.accept_tag1]; 2242 result[j++] = state_str[vlan_cfg.accept_tag2]; 2243 result[j++] = state_str[vlan_cfg.accept_untag1]; 2244 result[j++] = state_str[vlan_cfg.accept_untag2]; 2245 result[j++] = state_str[vlan_cfg.insert_tag1]; 2246 result[j++] = state_str[vlan_cfg.insert_tag2]; 2247 result[j++] = state_str[vlan_cfg.shift_tag]; 2248 result[j++] = state_str[vlan_cfg.strip_tag1]; 2249 result[j++] = state_str[vlan_cfg.strip_tag2]; 2250 result[j++] = state_str[vlan_cfg.drop_tag1]; 2251 result[j++] = state_str[vlan_cfg.drop_tag2]; 2252 result[j++] = state_str[vlan_cfg.pri_only1]; 2253 result[j++] = state_str[vlan_cfg.pri_only2]; 2254 2255 hclge_dbg_fill_content(content, sizeof(content), 2256 vlan_offload_items, result, 2257 ARRAY_SIZE(vlan_offload_items)); 2258 *pos += scnprintf(buf + *pos, len - *pos, "%s", content); 2259 } 2260 2261 return 0; 2262 } 2263 2264 static int hclge_dbg_dump_vlan_config(struct hclge_dev *hdev, char *buf, 2265 int len) 2266 { 2267 int pos = 0; 2268 int ret; 2269 2270 ret = hclge_dbg_dump_vlan_filter_config(hdev, buf, len, &pos); 2271 if (ret) 2272 return ret; 2273 2274 return hclge_dbg_dump_vlan_offload_config(hdev, buf, len, &pos); 2275 } 2276 2277 static int hclge_dbg_dump_ptp_info(struct hclge_dev *hdev, char *buf, int len) 2278 { 2279 struct hclge_ptp *ptp = hdev->ptp; 2280 u32 sw_cfg = ptp->ptp_cfg; 2281 unsigned int tx_start; 2282 unsigned int last_rx; 2283 int pos = 0; 2284 u32 hw_cfg; 2285 int ret; 2286 2287 pos += scnprintf(buf + pos, len - pos, "phc %s's debug info:\n", 2288 ptp->info.name); 2289 pos += scnprintf(buf + pos, len - pos, "ptp enable: %s\n", 2290 test_bit(HCLGE_PTP_FLAG_EN, &ptp->flags) ? 2291 "yes" : "no"); 2292 pos += scnprintf(buf + pos, len - pos, "ptp tx enable: %s\n", 2293 test_bit(HCLGE_PTP_FLAG_TX_EN, &ptp->flags) ? 2294 "yes" : "no"); 2295 pos += scnprintf(buf + pos, len - pos, "ptp rx enable: %s\n", 2296 test_bit(HCLGE_PTP_FLAG_RX_EN, &ptp->flags) ? 2297 "yes" : "no"); 2298 2299 last_rx = jiffies_to_msecs(ptp->last_rx); 2300 pos += scnprintf(buf + pos, len - pos, "last rx time: %lu.%lu\n", 2301 last_rx / MSEC_PER_SEC, last_rx % MSEC_PER_SEC); 2302 pos += scnprintf(buf + pos, len - pos, "rx count: %lu\n", ptp->rx_cnt); 2303 2304 tx_start = jiffies_to_msecs(ptp->tx_start); 2305 pos += scnprintf(buf + pos, len - pos, "last tx start time: %lu.%lu\n", 2306 tx_start / MSEC_PER_SEC, tx_start % MSEC_PER_SEC); 2307 pos += scnprintf(buf + pos, len - pos, "tx count: %lu\n", ptp->tx_cnt); 2308 pos += scnprintf(buf + pos, len - pos, "tx skipped count: %lu\n", 2309 ptp->tx_skipped); 2310 pos += scnprintf(buf + pos, len - pos, "tx timeout count: %lu\n", 2311 ptp->tx_timeout); 2312 pos += scnprintf(buf + pos, len - pos, "last tx seqid: %u\n", 2313 ptp->last_tx_seqid); 2314 2315 ret = hclge_ptp_cfg_qry(hdev, &hw_cfg); 2316 if (ret) 2317 return ret; 2318 2319 pos += scnprintf(buf + pos, len - pos, "sw_cfg: %#x, hw_cfg: %#x\n", 2320 sw_cfg, hw_cfg); 2321 2322 pos += scnprintf(buf + pos, len - pos, "tx type: %d, rx filter: %d\n", 2323 ptp->ts_cfg.tx_type, ptp->ts_cfg.rx_filter); 2324 2325 return 0; 2326 } 2327 2328 static int hclge_dbg_dump_mac_uc(struct hclge_dev *hdev, char *buf, int len) 2329 { 2330 hclge_dbg_dump_mac_list(hdev, buf, len, true); 2331 2332 return 0; 2333 } 2334 2335 static int hclge_dbg_dump_mac_mc(struct hclge_dev *hdev, char *buf, int len) 2336 { 2337 hclge_dbg_dump_mac_list(hdev, buf, len, false); 2338 2339 return 0; 2340 } 2341 2342 static const struct hclge_dbg_func hclge_dbg_cmd_func[] = { 2343 { 2344 .cmd = HNAE3_DBG_CMD_TM_NODES, 2345 .dbg_dump = hclge_dbg_dump_tm_nodes, 2346 }, 2347 { 2348 .cmd = HNAE3_DBG_CMD_TM_PRI, 2349 .dbg_dump = hclge_dbg_dump_tm_pri, 2350 }, 2351 { 2352 .cmd = HNAE3_DBG_CMD_TM_QSET, 2353 .dbg_dump = hclge_dbg_dump_tm_qset, 2354 }, 2355 { 2356 .cmd = HNAE3_DBG_CMD_TM_MAP, 2357 .dbg_dump = hclge_dbg_dump_tm_map, 2358 }, 2359 { 2360 .cmd = HNAE3_DBG_CMD_TM_PG, 2361 .dbg_dump = hclge_dbg_dump_tm_pg, 2362 }, 2363 { 2364 .cmd = HNAE3_DBG_CMD_TM_PORT, 2365 .dbg_dump = hclge_dbg_dump_tm_port, 2366 }, 2367 { 2368 .cmd = HNAE3_DBG_CMD_TC_SCH_INFO, 2369 .dbg_dump = hclge_dbg_dump_tc, 2370 }, 2371 { 2372 .cmd = HNAE3_DBG_CMD_QOS_PAUSE_CFG, 2373 .dbg_dump = hclge_dbg_dump_qos_pause_cfg, 2374 }, 2375 { 2376 .cmd = HNAE3_DBG_CMD_QOS_PRI_MAP, 2377 .dbg_dump = hclge_dbg_dump_qos_pri_map, 2378 }, 2379 { 2380 .cmd = HNAE3_DBG_CMD_QOS_BUF_CFG, 2381 .dbg_dump = hclge_dbg_dump_qos_buf_cfg, 2382 }, 2383 { 2384 .cmd = HNAE3_DBG_CMD_MAC_UC, 2385 .dbg_dump = hclge_dbg_dump_mac_uc, 2386 }, 2387 { 2388 .cmd = HNAE3_DBG_CMD_MAC_MC, 2389 .dbg_dump = hclge_dbg_dump_mac_mc, 2390 }, 2391 { 2392 .cmd = HNAE3_DBG_CMD_MNG_TBL, 2393 .dbg_dump = hclge_dbg_dump_mng_table, 2394 }, 2395 { 2396 .cmd = HNAE3_DBG_CMD_LOOPBACK, 2397 .dbg_dump = hclge_dbg_dump_loopback, 2398 }, 2399 { 2400 .cmd = HNAE3_DBG_CMD_PTP_INFO, 2401 .dbg_dump = hclge_dbg_dump_ptp_info, 2402 }, 2403 { 2404 .cmd = HNAE3_DBG_CMD_INTERRUPT_INFO, 2405 .dbg_dump = hclge_dbg_dump_interrupt, 2406 }, 2407 { 2408 .cmd = HNAE3_DBG_CMD_RESET_INFO, 2409 .dbg_dump = hclge_dbg_dump_rst_info, 2410 }, 2411 { 2412 .cmd = HNAE3_DBG_CMD_IMP_INFO, 2413 .dbg_dump = hclge_dbg_get_imp_stats_info, 2414 }, 2415 { 2416 .cmd = HNAE3_DBG_CMD_NCL_CONFIG, 2417 .dbg_dump = hclge_dbg_dump_ncl_config, 2418 }, 2419 { 2420 .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON, 2421 .dbg_dump_reg = hclge_dbg_dump_reg_cmd, 2422 }, 2423 { 2424 .cmd = HNAE3_DBG_CMD_REG_SSU, 2425 .dbg_dump_reg = hclge_dbg_dump_reg_cmd, 2426 }, 2427 { 2428 .cmd = HNAE3_DBG_CMD_REG_IGU_EGU, 2429 .dbg_dump_reg = hclge_dbg_dump_reg_cmd, 2430 }, 2431 { 2432 .cmd = HNAE3_DBG_CMD_REG_RPU, 2433 .dbg_dump_reg = hclge_dbg_dump_reg_cmd, 2434 }, 2435 { 2436 .cmd = HNAE3_DBG_CMD_REG_NCSI, 2437 .dbg_dump_reg = hclge_dbg_dump_reg_cmd, 2438 }, 2439 { 2440 .cmd = HNAE3_DBG_CMD_REG_RTC, 2441 .dbg_dump_reg = hclge_dbg_dump_reg_cmd, 2442 }, 2443 { 2444 .cmd = HNAE3_DBG_CMD_REG_PPP, 2445 .dbg_dump_reg = hclge_dbg_dump_reg_cmd, 2446 }, 2447 { 2448 .cmd = HNAE3_DBG_CMD_REG_RCB, 2449 .dbg_dump_reg = hclge_dbg_dump_reg_cmd, 2450 }, 2451 { 2452 .cmd = HNAE3_DBG_CMD_REG_TQP, 2453 .dbg_dump_reg = hclge_dbg_dump_reg_cmd, 2454 }, 2455 { 2456 .cmd = HNAE3_DBG_CMD_REG_MAC, 2457 .dbg_dump = hclge_dbg_dump_mac, 2458 }, 2459 { 2460 .cmd = HNAE3_DBG_CMD_REG_DCB, 2461 .dbg_dump = hclge_dbg_dump_dcb, 2462 }, 2463 { 2464 .cmd = HNAE3_DBG_CMD_FD_TCAM, 2465 .dbg_dump = hclge_dbg_dump_fd_tcam, 2466 }, 2467 { 2468 .cmd = HNAE3_DBG_CMD_MAC_TNL_STATUS, 2469 .dbg_dump = hclge_dbg_dump_mac_tnl_status, 2470 }, 2471 { 2472 .cmd = HNAE3_DBG_CMD_SERV_INFO, 2473 .dbg_dump = hclge_dbg_dump_serv_info, 2474 }, 2475 { 2476 .cmd = HNAE3_DBG_CMD_VLAN_CONFIG, 2477 .dbg_dump = hclge_dbg_dump_vlan_config, 2478 }, 2479 { 2480 .cmd = HNAE3_DBG_CMD_FD_COUNTER, 2481 .dbg_dump = hclge_dbg_dump_fd_counter, 2482 }, 2483 { 2484 .cmd = HNAE3_DBG_CMD_UMV_INFO, 2485 .dbg_dump = hclge_dbg_dump_umv_info, 2486 }, 2487 }; 2488 2489 int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, 2490 char *buf, int len) 2491 { 2492 struct hclge_vport *vport = hclge_get_vport(handle); 2493 const struct hclge_dbg_func *cmd_func; 2494 struct hclge_dev *hdev = vport->back; 2495 u32 i; 2496 2497 for (i = 0; i < ARRAY_SIZE(hclge_dbg_cmd_func); i++) { 2498 if (cmd == hclge_dbg_cmd_func[i].cmd) { 2499 cmd_func = &hclge_dbg_cmd_func[i]; 2500 if (cmd_func->dbg_dump) 2501 return cmd_func->dbg_dump(hdev, buf, len); 2502 else 2503 return cmd_func->dbg_dump_reg(hdev, cmd, buf, 2504 len); 2505 } 2506 } 2507 2508 dev_err(&hdev->pdev->dev, "invalid command(%d)\n", cmd); 2509 return -EINVAL; 2510 } 2511