1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (c) 2018-2019 Hisilicon Limited. */ 3 4 #include <linux/device.h> 5 6 #include "hclge_debugfs.h" 7 #include "hclge_cmd.h" 8 #include "hclge_main.h" 9 #include "hclge_tm.h" 10 #include "hnae3.h" 11 12 static int hclge_dbg_get_dfx_bd_num(struct hclge_dev *hdev, int offset) 13 { 14 struct hclge_desc desc[4]; 15 int ret; 16 17 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_DFX_BD_NUM, true); 18 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 19 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_DFX_BD_NUM, true); 20 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 21 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_DFX_BD_NUM, true); 22 desc[2].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 23 hclge_cmd_setup_basic_desc(&desc[3], HCLGE_OPC_DFX_BD_NUM, true); 24 25 ret = hclge_cmd_send(&hdev->hw, desc, 4); 26 if (ret != HCLGE_CMD_EXEC_SUCCESS) { 27 dev_err(&hdev->pdev->dev, 28 "get dfx bdnum fail, status is %d.\n", ret); 29 return ret; 30 } 31 32 return (int)desc[offset / 6].data[offset % 6]; 33 } 34 35 static int hclge_dbg_cmd_send(struct hclge_dev *hdev, 36 struct hclge_desc *desc_src, 37 int index, int bd_num, 38 enum hclge_opcode_type cmd) 39 { 40 struct hclge_desc *desc = desc_src; 41 int ret, i; 42 43 hclge_cmd_setup_basic_desc(desc, cmd, true); 44 desc->data[0] = cpu_to_le32(index); 45 46 for (i = 1; i < bd_num; i++) { 47 desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 48 desc++; 49 hclge_cmd_setup_basic_desc(desc, cmd, true); 50 } 51 52 ret = hclge_cmd_send(&hdev->hw, desc_src, bd_num); 53 if (ret) { 54 dev_err(&hdev->pdev->dev, 55 "read reg cmd send fail, status is %d.\n", ret); 56 return ret; 57 } 58 59 return ret; 60 } 61 62 static void hclge_dbg_dump_reg_common(struct hclge_dev *hdev, 63 struct hclge_dbg_dfx_message *dfx_message, 64 const char *cmd_buf, int msg_num, 65 int offset, enum hclge_opcode_type cmd) 66 { 67 #define BD_DATA_NUM 6 68 69 struct hclge_desc *desc_src; 70 struct hclge_desc *desc; 71 int bd_num, buf_len; 72 int ret, i; 73 int index; 74 int max; 75 76 ret = kstrtouint(cmd_buf, 10, &index); 77 index = (ret != 0) ? 0 : index; 78 79 bd_num = hclge_dbg_get_dfx_bd_num(hdev, offset); 80 if (bd_num <= 0) 81 return; 82 83 buf_len = sizeof(struct hclge_desc) * bd_num; 84 desc_src = kzalloc(buf_len, GFP_KERNEL); 85 if (!desc_src) { 86 dev_err(&hdev->pdev->dev, "call kzalloc failed\n"); 87 return; 88 } 89 90 desc = desc_src; 91 ret = hclge_dbg_cmd_send(hdev, desc, index, bd_num, cmd); 92 if (ret != HCLGE_CMD_EXEC_SUCCESS) { 93 kfree(desc_src); 94 return; 95 } 96 97 max = (bd_num * BD_DATA_NUM) <= msg_num ? 98 (bd_num * BD_DATA_NUM) : msg_num; 99 100 desc = desc_src; 101 for (i = 0; i < max; i++) { 102 ((i > 0) && ((i % BD_DATA_NUM) == 0)) ? desc++ : desc; 103 if (dfx_message->flag) 104 dev_info(&hdev->pdev->dev, "%s: 0x%x\n", 105 dfx_message->message, 106 desc->data[i % BD_DATA_NUM]); 107 108 dfx_message++; 109 } 110 111 kfree(desc_src); 112 } 113 114 static void hclge_dbg_dump_dcb(struct hclge_dev *hdev, const char *cmd_buf) 115 { 116 struct device *dev = &hdev->pdev->dev; 117 struct hclge_dbg_bitmap_cmd *bitmap; 118 int rq_id, pri_id, qset_id; 119 int port_id, nq_id, pg_id; 120 struct hclge_desc desc[2]; 121 122 int cnt, ret; 123 124 cnt = sscanf(cmd_buf, "%i %i %i %i %i %i", 125 &port_id, &pri_id, &pg_id, &rq_id, &nq_id, &qset_id); 126 if (cnt != 6) { 127 dev_err(&hdev->pdev->dev, 128 "dump dcb: bad command parameter, cnt=%d\n", cnt); 129 return; 130 } 131 132 ret = hclge_dbg_cmd_send(hdev, desc, qset_id, 1, 133 HCLGE_OPC_QSET_DFX_STS); 134 if (ret) 135 return; 136 137 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1]; 138 dev_info(dev, "roce_qset_mask: 0x%x\n", bitmap->bit0); 139 dev_info(dev, "nic_qs_mask: 0x%x\n", bitmap->bit1); 140 dev_info(dev, "qs_shaping_pass: 0x%x\n", bitmap->bit2); 141 dev_info(dev, "qs_bp_sts: 0x%x\n", bitmap->bit3); 142 143 ret = hclge_dbg_cmd_send(hdev, desc, pri_id, 1, HCLGE_OPC_PRI_DFX_STS); 144 if (ret) 145 return; 146 147 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1]; 148 dev_info(dev, "pri_mask: 0x%x\n", bitmap->bit0); 149 dev_info(dev, "pri_cshaping_pass: 0x%x\n", bitmap->bit1); 150 dev_info(dev, "pri_pshaping_pass: 0x%x\n", bitmap->bit2); 151 152 ret = hclge_dbg_cmd_send(hdev, desc, pg_id, 1, HCLGE_OPC_PG_DFX_STS); 153 if (ret) 154 return; 155 156 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1]; 157 dev_info(dev, "pg_mask: 0x%x\n", bitmap->bit0); 158 dev_info(dev, "pg_cshaping_pass: 0x%x\n", bitmap->bit1); 159 dev_info(dev, "pg_pshaping_pass: 0x%x\n", bitmap->bit2); 160 161 ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1, 162 HCLGE_OPC_PORT_DFX_STS); 163 if (ret) 164 return; 165 166 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1]; 167 dev_info(dev, "port_mask: 0x%x\n", bitmap->bit0); 168 dev_info(dev, "port_shaping_pass: 0x%x\n", bitmap->bit1); 169 170 ret = hclge_dbg_cmd_send(hdev, desc, nq_id, 1, HCLGE_OPC_SCH_NQ_CNT); 171 if (ret) 172 return; 173 174 dev_info(dev, "sch_nq_cnt: 0x%x\n", desc[0].data[1]); 175 176 ret = hclge_dbg_cmd_send(hdev, desc, nq_id, 1, HCLGE_OPC_SCH_RQ_CNT); 177 if (ret) 178 return; 179 180 dev_info(dev, "sch_rq_cnt: 0x%x\n", desc[0].data[1]); 181 182 ret = hclge_dbg_cmd_send(hdev, desc, 0, 2, HCLGE_OPC_TM_INTERNAL_STS); 183 if (ret) 184 return; 185 186 dev_info(dev, "pri_bp: 0x%x\n", desc[0].data[1]); 187 dev_info(dev, "fifo_dfx_info: 0x%x\n", desc[0].data[2]); 188 dev_info(dev, "sch_roce_fifo_afull_gap: 0x%x\n", desc[0].data[3]); 189 dev_info(dev, "tx_private_waterline: 0x%x\n", desc[0].data[4]); 190 dev_info(dev, "tm_bypass_en: 0x%x\n", desc[0].data[5]); 191 dev_info(dev, "SSU_TM_BYPASS_EN: 0x%x\n", desc[1].data[0]); 192 dev_info(dev, "SSU_RESERVE_CFG: 0x%x\n", desc[1].data[1]); 193 194 ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1, 195 HCLGE_OPC_TM_INTERNAL_CNT); 196 if (ret) 197 return; 198 199 dev_info(dev, "SCH_NIC_NUM: 0x%x\n", desc[0].data[1]); 200 dev_info(dev, "SCH_ROCE_NUM: 0x%x\n", desc[0].data[2]); 201 202 ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1, 203 HCLGE_OPC_TM_INTERNAL_STS_1); 204 if (ret) 205 return; 206 207 dev_info(dev, "TC_MAP_SEL: 0x%x\n", desc[0].data[1]); 208 dev_info(dev, "IGU_PFC_PRI_EN: 0x%x\n", desc[0].data[2]); 209 dev_info(dev, "MAC_PFC_PRI_EN: 0x%x\n", desc[0].data[3]); 210 dev_info(dev, "IGU_PRI_MAP_TC_CFG: 0x%x\n", desc[0].data[4]); 211 dev_info(dev, "IGU_TX_PRI_MAP_TC_CFG: 0x%x\n", desc[0].data[5]); 212 } 213 214 static void hclge_dbg_dump_reg_cmd(struct hclge_dev *hdev, const char *cmd_buf) 215 { 216 int msg_num; 217 218 if (strncmp(&cmd_buf[9], "bios common", 11) == 0) { 219 msg_num = sizeof(hclge_dbg_bios_common_reg) / 220 sizeof(struct hclge_dbg_dfx_message); 221 hclge_dbg_dump_reg_common(hdev, hclge_dbg_bios_common_reg, 222 &cmd_buf[21], msg_num, 223 HCLGE_DBG_DFX_BIOS_OFFSET, 224 HCLGE_OPC_DFX_BIOS_COMMON_REG); 225 } else if (strncmp(&cmd_buf[9], "ssu", 3) == 0) { 226 msg_num = sizeof(hclge_dbg_ssu_reg_0) / 227 sizeof(struct hclge_dbg_dfx_message); 228 hclge_dbg_dump_reg_common(hdev, hclge_dbg_ssu_reg_0, 229 &cmd_buf[13], msg_num, 230 HCLGE_DBG_DFX_SSU_0_OFFSET, 231 HCLGE_OPC_DFX_SSU_REG_0); 232 233 msg_num = sizeof(hclge_dbg_ssu_reg_1) / 234 sizeof(struct hclge_dbg_dfx_message); 235 hclge_dbg_dump_reg_common(hdev, hclge_dbg_ssu_reg_1, 236 &cmd_buf[13], msg_num, 237 HCLGE_DBG_DFX_SSU_1_OFFSET, 238 HCLGE_OPC_DFX_SSU_REG_1); 239 240 msg_num = sizeof(hclge_dbg_ssu_reg_2) / 241 sizeof(struct hclge_dbg_dfx_message); 242 hclge_dbg_dump_reg_common(hdev, hclge_dbg_ssu_reg_2, 243 &cmd_buf[13], msg_num, 244 HCLGE_DBG_DFX_SSU_2_OFFSET, 245 HCLGE_OPC_DFX_SSU_REG_2); 246 } else if (strncmp(&cmd_buf[9], "igu egu", 7) == 0) { 247 msg_num = sizeof(hclge_dbg_igu_egu_reg) / 248 sizeof(struct hclge_dbg_dfx_message); 249 hclge_dbg_dump_reg_common(hdev, hclge_dbg_igu_egu_reg, 250 &cmd_buf[17], msg_num, 251 HCLGE_DBG_DFX_IGU_OFFSET, 252 HCLGE_OPC_DFX_IGU_EGU_REG); 253 } else if (strncmp(&cmd_buf[9], "rpu", 3) == 0) { 254 msg_num = sizeof(hclge_dbg_rpu_reg_0) / 255 sizeof(struct hclge_dbg_dfx_message); 256 hclge_dbg_dump_reg_common(hdev, hclge_dbg_rpu_reg_0, 257 &cmd_buf[13], msg_num, 258 HCLGE_DBG_DFX_RPU_0_OFFSET, 259 HCLGE_OPC_DFX_RPU_REG_0); 260 261 msg_num = sizeof(hclge_dbg_rpu_reg_1) / 262 sizeof(struct hclge_dbg_dfx_message); 263 hclge_dbg_dump_reg_common(hdev, hclge_dbg_rpu_reg_1, 264 &cmd_buf[13], msg_num, 265 HCLGE_DBG_DFX_RPU_1_OFFSET, 266 HCLGE_OPC_DFX_RPU_REG_1); 267 } else if (strncmp(&cmd_buf[9], "ncsi", 4) == 0) { 268 msg_num = sizeof(hclge_dbg_ncsi_reg) / 269 sizeof(struct hclge_dbg_dfx_message); 270 hclge_dbg_dump_reg_common(hdev, hclge_dbg_ncsi_reg, 271 &cmd_buf[14], msg_num, 272 HCLGE_DBG_DFX_NCSI_OFFSET, 273 HCLGE_OPC_DFX_NCSI_REG); 274 } else if (strncmp(&cmd_buf[9], "rtc", 3) == 0) { 275 msg_num = sizeof(hclge_dbg_rtc_reg) / 276 sizeof(struct hclge_dbg_dfx_message); 277 hclge_dbg_dump_reg_common(hdev, hclge_dbg_rtc_reg, 278 &cmd_buf[13], msg_num, 279 HCLGE_DBG_DFX_RTC_OFFSET, 280 HCLGE_OPC_DFX_RTC_REG); 281 } else if (strncmp(&cmd_buf[9], "ppp", 3) == 0) { 282 msg_num = sizeof(hclge_dbg_ppp_reg) / 283 sizeof(struct hclge_dbg_dfx_message); 284 hclge_dbg_dump_reg_common(hdev, hclge_dbg_ppp_reg, 285 &cmd_buf[13], msg_num, 286 HCLGE_DBG_DFX_PPP_OFFSET, 287 HCLGE_OPC_DFX_PPP_REG); 288 } else if (strncmp(&cmd_buf[9], "rcb", 3) == 0) { 289 msg_num = sizeof(hclge_dbg_rcb_reg) / 290 sizeof(struct hclge_dbg_dfx_message); 291 hclge_dbg_dump_reg_common(hdev, hclge_dbg_rcb_reg, 292 &cmd_buf[13], msg_num, 293 HCLGE_DBG_DFX_RCB_OFFSET, 294 HCLGE_OPC_DFX_RCB_REG); 295 } else if (strncmp(&cmd_buf[9], "tqp", 3) == 0) { 296 msg_num = sizeof(hclge_dbg_tqp_reg) / 297 sizeof(struct hclge_dbg_dfx_message); 298 hclge_dbg_dump_reg_common(hdev, hclge_dbg_tqp_reg, 299 &cmd_buf[13], msg_num, 300 HCLGE_DBG_DFX_TQP_OFFSET, 301 HCLGE_OPC_DFX_TQP_REG); 302 } else if (strncmp(&cmd_buf[9], "dcb", 3) == 0) { 303 hclge_dbg_dump_dcb(hdev, &cmd_buf[13]); 304 } else { 305 dev_info(&hdev->pdev->dev, "unknown command\n"); 306 return; 307 } 308 } 309 310 static void hclge_title_idx_print(struct hclge_dev *hdev, bool flag, int index, 311 char *title_buf, char *true_buf, 312 char *false_buf) 313 { 314 if (flag) 315 dev_info(&hdev->pdev->dev, "%s(%d): %s\n", title_buf, index, 316 true_buf); 317 else 318 dev_info(&hdev->pdev->dev, "%s(%d): %s\n", title_buf, index, 319 false_buf); 320 } 321 322 static void hclge_dbg_dump_tc(struct hclge_dev *hdev) 323 { 324 struct hclge_ets_tc_weight_cmd *ets_weight; 325 struct hclge_desc desc; 326 int i, ret; 327 328 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, true); 329 330 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 331 if (ret) { 332 dev_err(&hdev->pdev->dev, "dump tc fail, status is %d.\n", ret); 333 return; 334 } 335 336 ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data; 337 338 dev_info(&hdev->pdev->dev, "dump tc\n"); 339 dev_info(&hdev->pdev->dev, "weight_offset: %u\n", 340 ets_weight->weight_offset); 341 342 for (i = 0; i < HNAE3_MAX_TC; i++) 343 hclge_title_idx_print(hdev, ets_weight->tc_weight[i], i, 344 "tc", "no sp mode", "sp mode"); 345 } 346 347 static void hclge_dbg_dump_tm_pg(struct hclge_dev *hdev) 348 { 349 struct hclge_port_shapping_cmd *port_shap_cfg_cmd; 350 struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd; 351 struct hclge_pg_shapping_cmd *pg_shap_cfg_cmd; 352 enum hclge_opcode_type cmd; 353 struct hclge_desc desc; 354 int ret; 355 356 cmd = HCLGE_OPC_TM_PG_C_SHAPPING; 357 hclge_cmd_setup_basic_desc(&desc, cmd, true); 358 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 359 if (ret) 360 goto err_tm_pg_cmd_send; 361 362 pg_shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data; 363 dev_info(&hdev->pdev->dev, "PG_C pg_id: %u\n", pg_shap_cfg_cmd->pg_id); 364 dev_info(&hdev->pdev->dev, "PG_C pg_shapping: 0x%x\n", 365 pg_shap_cfg_cmd->pg_shapping_para); 366 367 cmd = HCLGE_OPC_TM_PG_P_SHAPPING; 368 hclge_cmd_setup_basic_desc(&desc, cmd, true); 369 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 370 if (ret) 371 goto err_tm_pg_cmd_send; 372 373 pg_shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data; 374 dev_info(&hdev->pdev->dev, "PG_P pg_id: %u\n", pg_shap_cfg_cmd->pg_id); 375 dev_info(&hdev->pdev->dev, "PG_P pg_shapping: 0x%x\n", 376 pg_shap_cfg_cmd->pg_shapping_para); 377 378 cmd = HCLGE_OPC_TM_PORT_SHAPPING; 379 hclge_cmd_setup_basic_desc(&desc, cmd, true); 380 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 381 if (ret) 382 goto err_tm_pg_cmd_send; 383 384 port_shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data; 385 dev_info(&hdev->pdev->dev, "PORT port_shapping: 0x%x\n", 386 port_shap_cfg_cmd->port_shapping_para); 387 388 cmd = HCLGE_OPC_TM_PG_SCH_MODE_CFG; 389 hclge_cmd_setup_basic_desc(&desc, cmd, true); 390 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 391 if (ret) 392 goto err_tm_pg_cmd_send; 393 394 dev_info(&hdev->pdev->dev, "PG_SCH pg_id: %u\n", desc.data[0]); 395 396 cmd = HCLGE_OPC_TM_PRI_SCH_MODE_CFG; 397 hclge_cmd_setup_basic_desc(&desc, cmd, true); 398 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 399 if (ret) 400 goto err_tm_pg_cmd_send; 401 402 dev_info(&hdev->pdev->dev, "PRI_SCH pri_id: %u\n", desc.data[0]); 403 404 cmd = HCLGE_OPC_TM_QS_SCH_MODE_CFG; 405 hclge_cmd_setup_basic_desc(&desc, cmd, true); 406 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 407 if (ret) 408 goto err_tm_pg_cmd_send; 409 410 dev_info(&hdev->pdev->dev, "QS_SCH qs_id: %u\n", desc.data[0]); 411 412 cmd = HCLGE_OPC_TM_BP_TO_QSET_MAPPING; 413 hclge_cmd_setup_basic_desc(&desc, cmd, true); 414 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 415 if (ret) 416 goto err_tm_pg_cmd_send; 417 418 bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data; 419 dev_info(&hdev->pdev->dev, "BP_TO_QSET tc_id: %u\n", 420 bp_to_qs_map_cmd->tc_id); 421 dev_info(&hdev->pdev->dev, "BP_TO_QSET qs_group_id: 0x%x\n", 422 bp_to_qs_map_cmd->qs_group_id); 423 dev_info(&hdev->pdev->dev, "BP_TO_QSET qs_bit_map: 0x%x\n", 424 bp_to_qs_map_cmd->qs_bit_map); 425 return; 426 427 err_tm_pg_cmd_send: 428 dev_err(&hdev->pdev->dev, "dump tm_pg fail(0x%x), status is %d\n", 429 cmd, ret); 430 } 431 432 static void hclge_dbg_dump_tm(struct hclge_dev *hdev) 433 { 434 struct hclge_priority_weight_cmd *priority_weight; 435 struct hclge_pg_to_pri_link_cmd *pg_to_pri_map; 436 struct hclge_qs_to_pri_link_cmd *qs_to_pri_map; 437 struct hclge_nq_to_qs_link_cmd *nq_to_qs_map; 438 struct hclge_pri_shapping_cmd *shap_cfg_cmd; 439 struct hclge_pg_weight_cmd *pg_weight; 440 struct hclge_qs_weight_cmd *qs_weight; 441 enum hclge_opcode_type cmd; 442 struct hclge_desc desc; 443 int ret; 444 445 cmd = HCLGE_OPC_TM_PG_TO_PRI_LINK; 446 hclge_cmd_setup_basic_desc(&desc, cmd, true); 447 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 448 if (ret) 449 goto err_tm_cmd_send; 450 451 pg_to_pri_map = (struct hclge_pg_to_pri_link_cmd *)desc.data; 452 dev_info(&hdev->pdev->dev, "dump tm\n"); 453 dev_info(&hdev->pdev->dev, "PG_TO_PRI gp_id: %u\n", 454 pg_to_pri_map->pg_id); 455 dev_info(&hdev->pdev->dev, "PG_TO_PRI map: 0x%x\n", 456 pg_to_pri_map->pri_bit_map); 457 458 cmd = HCLGE_OPC_TM_QS_TO_PRI_LINK; 459 hclge_cmd_setup_basic_desc(&desc, cmd, true); 460 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 461 if (ret) 462 goto err_tm_cmd_send; 463 464 qs_to_pri_map = (struct hclge_qs_to_pri_link_cmd *)desc.data; 465 dev_info(&hdev->pdev->dev, "QS_TO_PRI qs_id: %u\n", 466 qs_to_pri_map->qs_id); 467 dev_info(&hdev->pdev->dev, "QS_TO_PRI priority: %u\n", 468 qs_to_pri_map->priority); 469 dev_info(&hdev->pdev->dev, "QS_TO_PRI link_vld: %u\n", 470 qs_to_pri_map->link_vld); 471 472 cmd = HCLGE_OPC_TM_NQ_TO_QS_LINK; 473 hclge_cmd_setup_basic_desc(&desc, cmd, true); 474 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 475 if (ret) 476 goto err_tm_cmd_send; 477 478 nq_to_qs_map = (struct hclge_nq_to_qs_link_cmd *)desc.data; 479 dev_info(&hdev->pdev->dev, "NQ_TO_QS nq_id: %u\n", nq_to_qs_map->nq_id); 480 dev_info(&hdev->pdev->dev, "NQ_TO_QS qset_id: 0x%x\n", 481 nq_to_qs_map->qset_id); 482 483 cmd = HCLGE_OPC_TM_PG_WEIGHT; 484 hclge_cmd_setup_basic_desc(&desc, cmd, true); 485 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 486 if (ret) 487 goto err_tm_cmd_send; 488 489 pg_weight = (struct hclge_pg_weight_cmd *)desc.data; 490 dev_info(&hdev->pdev->dev, "PG pg_id: %u\n", pg_weight->pg_id); 491 dev_info(&hdev->pdev->dev, "PG dwrr: %u\n", pg_weight->dwrr); 492 493 cmd = HCLGE_OPC_TM_QS_WEIGHT; 494 hclge_cmd_setup_basic_desc(&desc, cmd, true); 495 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 496 if (ret) 497 goto err_tm_cmd_send; 498 499 qs_weight = (struct hclge_qs_weight_cmd *)desc.data; 500 dev_info(&hdev->pdev->dev, "QS qs_id: %u\n", qs_weight->qs_id); 501 dev_info(&hdev->pdev->dev, "QS dwrr: %u\n", qs_weight->dwrr); 502 503 cmd = HCLGE_OPC_TM_PRI_WEIGHT; 504 hclge_cmd_setup_basic_desc(&desc, cmd, true); 505 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 506 if (ret) 507 goto err_tm_cmd_send; 508 509 priority_weight = (struct hclge_priority_weight_cmd *)desc.data; 510 dev_info(&hdev->pdev->dev, "PRI pri_id: %u\n", priority_weight->pri_id); 511 dev_info(&hdev->pdev->dev, "PRI dwrr: %u\n", priority_weight->dwrr); 512 513 cmd = HCLGE_OPC_TM_PRI_C_SHAPPING; 514 hclge_cmd_setup_basic_desc(&desc, cmd, true); 515 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 516 if (ret) 517 goto err_tm_cmd_send; 518 519 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data; 520 dev_info(&hdev->pdev->dev, "PRI_C pri_id: %u\n", shap_cfg_cmd->pri_id); 521 dev_info(&hdev->pdev->dev, "PRI_C pri_shapping: 0x%x\n", 522 shap_cfg_cmd->pri_shapping_para); 523 524 cmd = HCLGE_OPC_TM_PRI_P_SHAPPING; 525 hclge_cmd_setup_basic_desc(&desc, cmd, true); 526 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 527 if (ret) 528 goto err_tm_cmd_send; 529 530 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data; 531 dev_info(&hdev->pdev->dev, "PRI_P pri_id: %u\n", shap_cfg_cmd->pri_id); 532 dev_info(&hdev->pdev->dev, "PRI_P pri_shapping: 0x%x\n", 533 shap_cfg_cmd->pri_shapping_para); 534 535 hclge_dbg_dump_tm_pg(hdev); 536 537 return; 538 539 err_tm_cmd_send: 540 dev_err(&hdev->pdev->dev, "dump tm fail(0x%x), status is %d\n", 541 cmd, ret); 542 } 543 544 static void hclge_dbg_dump_tm_map(struct hclge_dev *hdev, 545 const char *cmd_buf) 546 { 547 struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd; 548 struct hclge_nq_to_qs_link_cmd *nq_to_qs_map; 549 struct hclge_qs_to_pri_link_cmd *map; 550 struct hclge_tqp_tx_queue_tc_cmd *tc; 551 enum hclge_opcode_type cmd; 552 struct hclge_desc desc; 553 int queue_id, group_id; 554 u32 qset_maping[32]; 555 int tc_id, qset_id; 556 int pri_id, ret; 557 u32 i; 558 559 ret = kstrtouint(&cmd_buf[12], 10, &queue_id); 560 queue_id = (ret != 0) ? 0 : queue_id; 561 562 cmd = HCLGE_OPC_TM_NQ_TO_QS_LINK; 563 nq_to_qs_map = (struct hclge_nq_to_qs_link_cmd *)desc.data; 564 hclge_cmd_setup_basic_desc(&desc, cmd, true); 565 nq_to_qs_map->nq_id = cpu_to_le16(queue_id); 566 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 567 if (ret) 568 goto err_tm_map_cmd_send; 569 qset_id = nq_to_qs_map->qset_id & 0x3FF; 570 571 cmd = HCLGE_OPC_TM_QS_TO_PRI_LINK; 572 map = (struct hclge_qs_to_pri_link_cmd *)desc.data; 573 hclge_cmd_setup_basic_desc(&desc, cmd, true); 574 map->qs_id = cpu_to_le16(qset_id); 575 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 576 if (ret) 577 goto err_tm_map_cmd_send; 578 pri_id = map->priority; 579 580 cmd = HCLGE_OPC_TQP_TX_QUEUE_TC; 581 tc = (struct hclge_tqp_tx_queue_tc_cmd *)desc.data; 582 hclge_cmd_setup_basic_desc(&desc, cmd, true); 583 tc->queue_id = cpu_to_le16(queue_id); 584 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 585 if (ret) 586 goto err_tm_map_cmd_send; 587 tc_id = tc->tc_id & 0x7; 588 589 dev_info(&hdev->pdev->dev, "queue_id | qset_id | pri_id | tc_id\n"); 590 dev_info(&hdev->pdev->dev, "%04d | %04d | %02d | %02d\n", 591 queue_id, qset_id, pri_id, tc_id); 592 593 cmd = HCLGE_OPC_TM_BP_TO_QSET_MAPPING; 594 bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data; 595 for (group_id = 0; group_id < 32; group_id++) { 596 hclge_cmd_setup_basic_desc(&desc, cmd, true); 597 bp_to_qs_map_cmd->tc_id = tc_id; 598 bp_to_qs_map_cmd->qs_group_id = group_id; 599 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 600 if (ret) 601 goto err_tm_map_cmd_send; 602 603 qset_maping[group_id] = bp_to_qs_map_cmd->qs_bit_map; 604 } 605 606 dev_info(&hdev->pdev->dev, "index | tm bp qset maping:\n"); 607 608 i = 0; 609 for (group_id = 0; group_id < 4; group_id++) { 610 dev_info(&hdev->pdev->dev, 611 "%04d | %08x:%08x:%08x:%08x:%08x:%08x:%08x:%08x\n", 612 group_id * 256, qset_maping[(u32)(i + 7)], 613 qset_maping[(u32)(i + 6)], qset_maping[(u32)(i + 5)], 614 qset_maping[(u32)(i + 4)], qset_maping[(u32)(i + 3)], 615 qset_maping[(u32)(i + 2)], qset_maping[(u32)(i + 1)], 616 qset_maping[i]); 617 i += 8; 618 } 619 620 return; 621 622 err_tm_map_cmd_send: 623 dev_err(&hdev->pdev->dev, "dump tqp map fail(0x%x), status is %d\n", 624 cmd, ret); 625 } 626 627 static void hclge_dbg_dump_qos_pause_cfg(struct hclge_dev *hdev) 628 { 629 struct hclge_cfg_pause_param_cmd *pause_param; 630 struct hclge_desc desc; 631 int ret; 632 633 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true); 634 635 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 636 if (ret) { 637 dev_err(&hdev->pdev->dev, "dump checksum fail, status is %d.\n", 638 ret); 639 return; 640 } 641 642 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data; 643 dev_info(&hdev->pdev->dev, "dump qos pause cfg\n"); 644 dev_info(&hdev->pdev->dev, "pause_trans_gap: 0x%x\n", 645 pause_param->pause_trans_gap); 646 dev_info(&hdev->pdev->dev, "pause_trans_time: 0x%x\n", 647 pause_param->pause_trans_time); 648 } 649 650 static void hclge_dbg_dump_qos_pri_map(struct hclge_dev *hdev) 651 { 652 struct hclge_qos_pri_map_cmd *pri_map; 653 struct hclge_desc desc; 654 int ret; 655 656 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, true); 657 658 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 659 if (ret) { 660 dev_err(&hdev->pdev->dev, 661 "dump qos pri map fail, status is %d.\n", ret); 662 return; 663 } 664 665 pri_map = (struct hclge_qos_pri_map_cmd *)desc.data; 666 dev_info(&hdev->pdev->dev, "dump qos pri map\n"); 667 dev_info(&hdev->pdev->dev, "vlan_to_pri: 0x%x\n", pri_map->vlan_pri); 668 dev_info(&hdev->pdev->dev, "pri_0_to_tc: 0x%x\n", pri_map->pri0_tc); 669 dev_info(&hdev->pdev->dev, "pri_1_to_tc: 0x%x\n", pri_map->pri1_tc); 670 dev_info(&hdev->pdev->dev, "pri_2_to_tc: 0x%x\n", pri_map->pri2_tc); 671 dev_info(&hdev->pdev->dev, "pri_3_to_tc: 0x%x\n", pri_map->pri3_tc); 672 dev_info(&hdev->pdev->dev, "pri_4_to_tc: 0x%x\n", pri_map->pri4_tc); 673 dev_info(&hdev->pdev->dev, "pri_5_to_tc: 0x%x\n", pri_map->pri5_tc); 674 dev_info(&hdev->pdev->dev, "pri_6_to_tc: 0x%x\n", pri_map->pri6_tc); 675 dev_info(&hdev->pdev->dev, "pri_7_to_tc: 0x%x\n", pri_map->pri7_tc); 676 } 677 678 static void hclge_dbg_dump_qos_buf_cfg(struct hclge_dev *hdev) 679 { 680 struct hclge_tx_buff_alloc_cmd *tx_buf_cmd; 681 struct hclge_rx_priv_buff_cmd *rx_buf_cmd; 682 struct hclge_rx_priv_wl_buf *rx_priv_wl; 683 struct hclge_rx_com_wl *rx_packet_cnt; 684 struct hclge_rx_com_thrd *rx_com_thrd; 685 struct hclge_rx_com_wl *rx_com_wl; 686 enum hclge_opcode_type cmd; 687 struct hclge_desc desc[2]; 688 int i, ret; 689 690 cmd = HCLGE_OPC_TX_BUFF_ALLOC; 691 hclge_cmd_setup_basic_desc(desc, cmd, true); 692 ret = hclge_cmd_send(&hdev->hw, desc, 1); 693 if (ret) 694 goto err_qos_cmd_send; 695 696 dev_info(&hdev->pdev->dev, "dump qos buf cfg\n"); 697 698 tx_buf_cmd = (struct hclge_tx_buff_alloc_cmd *)desc[0].data; 699 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 700 dev_info(&hdev->pdev->dev, "tx_packet_buf_tc_%d: 0x%x\n", i, 701 tx_buf_cmd->tx_pkt_buff[i]); 702 703 cmd = HCLGE_OPC_RX_PRIV_BUFF_ALLOC; 704 hclge_cmd_setup_basic_desc(desc, cmd, true); 705 ret = hclge_cmd_send(&hdev->hw, desc, 1); 706 if (ret) 707 goto err_qos_cmd_send; 708 709 dev_info(&hdev->pdev->dev, "\n"); 710 rx_buf_cmd = (struct hclge_rx_priv_buff_cmd *)desc[0].data; 711 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 712 dev_info(&hdev->pdev->dev, "rx_packet_buf_tc_%d: 0x%x\n", i, 713 rx_buf_cmd->buf_num[i]); 714 715 dev_info(&hdev->pdev->dev, "rx_share_buf: 0x%x\n", 716 rx_buf_cmd->shared_buf); 717 718 cmd = HCLGE_OPC_RX_PRIV_WL_ALLOC; 719 hclge_cmd_setup_basic_desc(&desc[0], cmd, true); 720 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 721 hclge_cmd_setup_basic_desc(&desc[1], cmd, true); 722 ret = hclge_cmd_send(&hdev->hw, desc, 2); 723 if (ret) 724 goto err_qos_cmd_send; 725 726 dev_info(&hdev->pdev->dev, "\n"); 727 rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[0].data; 728 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 729 dev_info(&hdev->pdev->dev, 730 "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n", i, 731 rx_priv_wl->tc_wl[i].high, rx_priv_wl->tc_wl[i].low); 732 733 rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[1].data; 734 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 735 dev_info(&hdev->pdev->dev, 736 "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n", i + 4, 737 rx_priv_wl->tc_wl[i].high, rx_priv_wl->tc_wl[i].low); 738 739 cmd = HCLGE_OPC_RX_COM_THRD_ALLOC; 740 hclge_cmd_setup_basic_desc(&desc[0], cmd, true); 741 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 742 hclge_cmd_setup_basic_desc(&desc[1], cmd, true); 743 ret = hclge_cmd_send(&hdev->hw, desc, 2); 744 if (ret) 745 goto err_qos_cmd_send; 746 747 dev_info(&hdev->pdev->dev, "\n"); 748 rx_com_thrd = (struct hclge_rx_com_thrd *)desc[0].data; 749 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 750 dev_info(&hdev->pdev->dev, 751 "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n", i, 752 rx_com_thrd->com_thrd[i].high, 753 rx_com_thrd->com_thrd[i].low); 754 755 rx_com_thrd = (struct hclge_rx_com_thrd *)desc[1].data; 756 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 757 dev_info(&hdev->pdev->dev, 758 "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n", i + 4, 759 rx_com_thrd->com_thrd[i].high, 760 rx_com_thrd->com_thrd[i].low); 761 762 cmd = HCLGE_OPC_RX_COM_WL_ALLOC; 763 hclge_cmd_setup_basic_desc(desc, cmd, true); 764 ret = hclge_cmd_send(&hdev->hw, desc, 1); 765 if (ret) 766 goto err_qos_cmd_send; 767 768 rx_com_wl = (struct hclge_rx_com_wl *)desc[0].data; 769 dev_info(&hdev->pdev->dev, "\n"); 770 dev_info(&hdev->pdev->dev, "rx_com_wl: high: 0x%x, low: 0x%x\n", 771 rx_com_wl->com_wl.high, rx_com_wl->com_wl.low); 772 773 cmd = HCLGE_OPC_RX_GBL_PKT_CNT; 774 hclge_cmd_setup_basic_desc(desc, cmd, true); 775 ret = hclge_cmd_send(&hdev->hw, desc, 1); 776 if (ret) 777 goto err_qos_cmd_send; 778 779 rx_packet_cnt = (struct hclge_rx_com_wl *)desc[0].data; 780 dev_info(&hdev->pdev->dev, 781 "rx_global_packet_cnt: high: 0x%x, low: 0x%x\n", 782 rx_packet_cnt->com_wl.high, rx_packet_cnt->com_wl.low); 783 784 return; 785 786 err_qos_cmd_send: 787 dev_err(&hdev->pdev->dev, 788 "dump qos buf cfg fail(0x%x), status is %d\n", cmd, ret); 789 } 790 791 static void hclge_dbg_dump_mng_table(struct hclge_dev *hdev) 792 { 793 struct hclge_mac_ethertype_idx_rd_cmd *req0; 794 char printf_buf[HCLGE_DBG_BUF_LEN]; 795 struct hclge_desc desc; 796 int ret, i; 797 798 dev_info(&hdev->pdev->dev, "mng tab:\n"); 799 memset(printf_buf, 0, HCLGE_DBG_BUF_LEN); 800 strncat(printf_buf, 801 "entry|mac_addr |mask|ether|mask|vlan|mask", 802 HCLGE_DBG_BUF_LEN - 1); 803 strncat(printf_buf + strlen(printf_buf), 804 "|i_map|i_dir|e_type|pf_id|vf_id|q_id|drop\n", 805 HCLGE_DBG_BUF_LEN - strlen(printf_buf) - 1); 806 807 dev_info(&hdev->pdev->dev, "%s", printf_buf); 808 809 for (i = 0; i < HCLGE_DBG_MNG_TBL_MAX; i++) { 810 hclge_cmd_setup_basic_desc(&desc, HCLGE_MAC_ETHERTYPE_IDX_RD, 811 true); 812 req0 = (struct hclge_mac_ethertype_idx_rd_cmd *)&desc.data; 813 req0->index = cpu_to_le16(i); 814 815 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 816 if (ret) { 817 dev_err(&hdev->pdev->dev, 818 "call hclge_cmd_send fail, ret = %d\n", ret); 819 return; 820 } 821 822 if (!req0->resp_code) 823 continue; 824 825 memset(printf_buf, 0, HCLGE_DBG_BUF_LEN); 826 snprintf(printf_buf, HCLGE_DBG_BUF_LEN, 827 "%02u |%02x:%02x:%02x:%02x:%02x:%02x|", 828 req0->index, req0->mac_add[0], req0->mac_add[1], 829 req0->mac_add[2], req0->mac_add[3], req0->mac_add[4], 830 req0->mac_add[5]); 831 832 snprintf(printf_buf + strlen(printf_buf), 833 HCLGE_DBG_BUF_LEN - strlen(printf_buf), 834 "%x |%04x |%x |%04x|%x |%02x |%02x |", 835 !!(req0->flags & HCLGE_DBG_MNG_MAC_MASK_B), 836 req0->ethter_type, 837 !!(req0->flags & HCLGE_DBG_MNG_ETHER_MASK_B), 838 req0->vlan_tag & HCLGE_DBG_MNG_VLAN_TAG, 839 !!(req0->flags & HCLGE_DBG_MNG_VLAN_MASK_B), 840 req0->i_port_bitmap, req0->i_port_direction); 841 842 snprintf(printf_buf + strlen(printf_buf), 843 HCLGE_DBG_BUF_LEN - strlen(printf_buf), 844 "%d |%d |%02d |%04d|%x\n", 845 !!(req0->egress_port & HCLGE_DBG_MNG_E_TYPE_B), 846 req0->egress_port & HCLGE_DBG_MNG_PF_ID, 847 (req0->egress_port >> 3) & HCLGE_DBG_MNG_VF_ID, 848 req0->egress_queue, 849 !!(req0->egress_port & HCLGE_DBG_MNG_DROP_B)); 850 851 dev_info(&hdev->pdev->dev, "%s", printf_buf); 852 } 853 } 854 855 static void hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, u8 stage, 856 bool sel_x, u32 loc) 857 { 858 struct hclge_fd_tcam_config_1_cmd *req1; 859 struct hclge_fd_tcam_config_2_cmd *req2; 860 struct hclge_fd_tcam_config_3_cmd *req3; 861 struct hclge_desc desc[3]; 862 int ret, i; 863 u32 *req; 864 865 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, true); 866 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 867 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, true); 868 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 869 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, true); 870 871 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 872 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 873 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 874 875 req1->stage = stage; 876 req1->xy_sel = sel_x ? 1 : 0; 877 req1->index = cpu_to_le32(loc); 878 879 ret = hclge_cmd_send(&hdev->hw, desc, 3); 880 if (ret) 881 return; 882 883 dev_info(&hdev->pdev->dev, " read result tcam key %s(%u):\n", 884 sel_x ? "x" : "y", loc); 885 886 req = (u32 *)req1->tcam_data; 887 for (i = 0; i < 2; i++) 888 dev_info(&hdev->pdev->dev, "%08x\n", *req++); 889 890 req = (u32 *)req2->tcam_data; 891 for (i = 0; i < 6; i++) 892 dev_info(&hdev->pdev->dev, "%08x\n", *req++); 893 894 req = (u32 *)req3->tcam_data; 895 for (i = 0; i < 5; i++) 896 dev_info(&hdev->pdev->dev, "%08x\n", *req++); 897 } 898 899 static void hclge_dbg_fd_tcam(struct hclge_dev *hdev) 900 { 901 u32 i; 902 903 for (i = 0; i < hdev->fd_cfg.rule_num[0]; i++) { 904 hclge_dbg_fd_tcam_read(hdev, 0, true, i); 905 hclge_dbg_fd_tcam_read(hdev, 0, false, i); 906 } 907 } 908 909 static void hclge_dbg_dump_rst_info(struct hclge_dev *hdev) 910 { 911 dev_info(&hdev->pdev->dev, "PF reset count: %d\n", 912 hdev->rst_stats.pf_rst_cnt); 913 dev_info(&hdev->pdev->dev, "FLR reset count: %d\n", 914 hdev->rst_stats.flr_rst_cnt); 915 dev_info(&hdev->pdev->dev, "CORE reset count: %d\n", 916 hdev->rst_stats.core_rst_cnt); 917 dev_info(&hdev->pdev->dev, "GLOBAL reset count: %d\n", 918 hdev->rst_stats.global_rst_cnt); 919 dev_info(&hdev->pdev->dev, "IMP reset count: %d\n", 920 hdev->rst_stats.imp_rst_cnt); 921 dev_info(&hdev->pdev->dev, "reset done count: %d\n", 922 hdev->rst_stats.reset_done_cnt); 923 dev_info(&hdev->pdev->dev, "HW reset done count: %d\n", 924 hdev->rst_stats.hw_reset_done_cnt); 925 dev_info(&hdev->pdev->dev, "reset count: %d\n", 926 hdev->rst_stats.reset_cnt); 927 } 928 929 void hclge_dbg_get_m7_stats_info(struct hclge_dev *hdev) 930 { 931 struct hclge_desc *desc_src, *desc_tmp; 932 struct hclge_get_m7_bd_cmd *req; 933 struct hclge_desc desc; 934 u32 bd_num, buf_len; 935 int ret, i; 936 937 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_M7_STATS_BD, true); 938 939 req = (struct hclge_get_m7_bd_cmd *)desc.data; 940 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 941 if (ret) { 942 dev_err(&hdev->pdev->dev, 943 "get firmware statistics bd number failed, ret=%d\n", 944 ret); 945 return; 946 } 947 948 bd_num = le32_to_cpu(req->bd_num); 949 950 buf_len = sizeof(struct hclge_desc) * bd_num; 951 desc_src = kzalloc(buf_len, GFP_KERNEL); 952 if (!desc_src) { 953 dev_err(&hdev->pdev->dev, 954 "allocate desc for get_m7_stats failed\n"); 955 return; 956 } 957 958 desc_tmp = desc_src; 959 ret = hclge_dbg_cmd_send(hdev, desc_tmp, 0, bd_num, 960 HCLGE_OPC_M7_STATS_INFO); 961 if (ret) { 962 kfree(desc_src); 963 dev_err(&hdev->pdev->dev, 964 "get firmware statistics failed, ret=%d\n", ret); 965 return; 966 } 967 968 for (i = 0; i < bd_num; i++) { 969 dev_info(&hdev->pdev->dev, "0x%08x 0x%08x 0x%08x\n", 970 le32_to_cpu(desc_tmp->data[0]), 971 le32_to_cpu(desc_tmp->data[1]), 972 le32_to_cpu(desc_tmp->data[2])); 973 dev_info(&hdev->pdev->dev, "0x%08x 0x%08x 0x%08x\n", 974 le32_to_cpu(desc_tmp->data[3]), 975 le32_to_cpu(desc_tmp->data[4]), 976 le32_to_cpu(desc_tmp->data[5])); 977 978 desc_tmp++; 979 } 980 981 kfree(desc_src); 982 } 983 984 /* hclge_dbg_dump_ncl_config: print specified range of NCL_CONFIG file 985 * @hdev: pointer to struct hclge_dev 986 * @cmd_buf: string that contains offset and length 987 */ 988 static void hclge_dbg_dump_ncl_config(struct hclge_dev *hdev, 989 const char *cmd_buf) 990 { 991 #define HCLGE_MAX_NCL_CONFIG_OFFSET 4096 992 #define HCLGE_MAX_NCL_CONFIG_LENGTH (20 + 24 * 4) 993 #define HCLGE_CMD_DATA_NUM 6 994 995 struct hclge_desc desc[5]; 996 u32 byte_offset; 997 int bd_num = 5; 998 int offset; 999 int length; 1000 int data0; 1001 int ret; 1002 int i; 1003 int j; 1004 1005 ret = sscanf(cmd_buf, "%x %x", &offset, &length); 1006 if (ret != 2 || offset >= HCLGE_MAX_NCL_CONFIG_OFFSET || 1007 length > HCLGE_MAX_NCL_CONFIG_OFFSET - offset) { 1008 dev_err(&hdev->pdev->dev, "Invalid offset or length.\n"); 1009 return; 1010 } 1011 if (offset < 0 || length <= 0) { 1012 dev_err(&hdev->pdev->dev, "Non-positive offset or length.\n"); 1013 return; 1014 } 1015 1016 dev_info(&hdev->pdev->dev, "offset | data\n"); 1017 1018 while (length > 0) { 1019 data0 = offset; 1020 if (length >= HCLGE_MAX_NCL_CONFIG_LENGTH) 1021 data0 |= HCLGE_MAX_NCL_CONFIG_LENGTH << 16; 1022 else 1023 data0 |= length << 16; 1024 ret = hclge_dbg_cmd_send(hdev, desc, data0, bd_num, 1025 HCLGE_OPC_QUERY_NCL_CONFIG); 1026 if (ret) 1027 return; 1028 1029 byte_offset = offset; 1030 for (i = 0; i < bd_num; i++) { 1031 for (j = 0; j < HCLGE_CMD_DATA_NUM; j++) { 1032 if (i == 0 && j == 0) 1033 continue; 1034 1035 dev_info(&hdev->pdev->dev, "0x%04x | 0x%08x\n", 1036 byte_offset, 1037 le32_to_cpu(desc[i].data[j])); 1038 byte_offset += sizeof(u32); 1039 length -= sizeof(u32); 1040 if (length <= 0) 1041 return; 1042 } 1043 } 1044 offset += HCLGE_MAX_NCL_CONFIG_LENGTH; 1045 } 1046 } 1047 1048 /* hclge_dbg_dump_mac_tnl_status: print message about mac tnl interrupt 1049 * @hdev: pointer to struct hclge_dev 1050 */ 1051 static void hclge_dbg_dump_mac_tnl_status(struct hclge_dev *hdev) 1052 { 1053 #define HCLGE_BILLION_NANO_SECONDS 1000000000 1054 1055 struct hclge_mac_tnl_stats stats; 1056 unsigned long rem_nsec; 1057 1058 dev_info(&hdev->pdev->dev, "Recently generated mac tnl interruption:\n"); 1059 1060 while (kfifo_get(&hdev->mac_tnl_log, &stats)) { 1061 rem_nsec = do_div(stats.time, HCLGE_BILLION_NANO_SECONDS); 1062 dev_info(&hdev->pdev->dev, "[%07lu.%03lu] status = 0x%x\n", 1063 (unsigned long)stats.time, rem_nsec / 1000, 1064 stats.status); 1065 } 1066 } 1067 1068 int hclge_dbg_run_cmd(struct hnae3_handle *handle, const char *cmd_buf) 1069 { 1070 struct hclge_vport *vport = hclge_get_vport(handle); 1071 struct hclge_dev *hdev = vport->back; 1072 1073 if (strncmp(cmd_buf, "dump fd tcam", 12) == 0) { 1074 hclge_dbg_fd_tcam(hdev); 1075 } else if (strncmp(cmd_buf, "dump tc", 7) == 0) { 1076 hclge_dbg_dump_tc(hdev); 1077 } else if (strncmp(cmd_buf, "dump tm map", 11) == 0) { 1078 hclge_dbg_dump_tm_map(hdev, cmd_buf); 1079 } else if (strncmp(cmd_buf, "dump tm", 7) == 0) { 1080 hclge_dbg_dump_tm(hdev); 1081 } else if (strncmp(cmd_buf, "dump qos pause cfg", 18) == 0) { 1082 hclge_dbg_dump_qos_pause_cfg(hdev); 1083 } else if (strncmp(cmd_buf, "dump qos pri map", 16) == 0) { 1084 hclge_dbg_dump_qos_pri_map(hdev); 1085 } else if (strncmp(cmd_buf, "dump qos buf cfg", 16) == 0) { 1086 hclge_dbg_dump_qos_buf_cfg(hdev); 1087 } else if (strncmp(cmd_buf, "dump mng tbl", 12) == 0) { 1088 hclge_dbg_dump_mng_table(hdev); 1089 } else if (strncmp(cmd_buf, "dump reg", 8) == 0) { 1090 hclge_dbg_dump_reg_cmd(hdev, cmd_buf); 1091 } else if (strncmp(cmd_buf, "dump reset info", 15) == 0) { 1092 hclge_dbg_dump_rst_info(hdev); 1093 } else if (strncmp(cmd_buf, "dump m7 info", 12) == 0) { 1094 hclge_dbg_get_m7_stats_info(hdev); 1095 } else if (strncmp(cmd_buf, "dump ncl_config", 15) == 0) { 1096 hclge_dbg_dump_ncl_config(hdev, 1097 &cmd_buf[sizeof("dump ncl_config")]); 1098 } else if (strncmp(cmd_buf, "dump mac tnl status", 19) == 0) { 1099 hclge_dbg_dump_mac_tnl_status(hdev); 1100 } else { 1101 dev_info(&hdev->pdev->dev, "unknown command\n"); 1102 return -EINVAL; 1103 } 1104 1105 return 0; 1106 } 1107