1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3 
4 #include "hclge_main.h"
5 #include "hclge_dcb.h"
6 #include "hclge_tm.h"
7 #include "hclge_dcb.h"
8 #include "hnae3.h"
9 
10 #define BW_PERCENT	100
11 
12 static int hclge_ieee_ets_to_tm_info(struct hclge_dev *hdev,
13 				     struct ieee_ets *ets)
14 {
15 	u8 i;
16 
17 	for (i = 0; i < HNAE3_MAX_TC; i++) {
18 		switch (ets->tc_tsa[i]) {
19 		case IEEE_8021QAZ_TSA_STRICT:
20 			hdev->tm_info.tc_info[i].tc_sch_mode =
21 				HCLGE_SCH_MODE_SP;
22 			hdev->tm_info.pg_info[0].tc_dwrr[i] = 0;
23 			break;
24 		case IEEE_8021QAZ_TSA_ETS:
25 			hdev->tm_info.tc_info[i].tc_sch_mode =
26 				HCLGE_SCH_MODE_DWRR;
27 			hdev->tm_info.pg_info[0].tc_dwrr[i] =
28 				ets->tc_tx_bw[i];
29 			break;
30 		default:
31 			/* Hardware only supports SP (strict priority)
32 			 * or ETS (enhanced transmission selection)
33 			 * algorithms, if we receive some other value
34 			 * from dcbnl, then throw an error.
35 			 */
36 			return -EINVAL;
37 		}
38 	}
39 
40 	hclge_tm_prio_tc_info_update(hdev, ets->prio_tc);
41 
42 	return 0;
43 }
44 
45 static void hclge_tm_info_to_ieee_ets(struct hclge_dev *hdev,
46 				      struct ieee_ets *ets)
47 {
48 	u32 i;
49 
50 	memset(ets, 0, sizeof(*ets));
51 	ets->willing = 1;
52 	ets->ets_cap = hdev->tc_max;
53 
54 	for (i = 0; i < HNAE3_MAX_TC; i++) {
55 		ets->prio_tc[i] = hdev->tm_info.prio_tc[i];
56 		ets->tc_tx_bw[i] = hdev->tm_info.pg_info[0].tc_dwrr[i];
57 
58 		if (hdev->tm_info.tc_info[i].tc_sch_mode ==
59 		    HCLGE_SCH_MODE_SP)
60 			ets->tc_tsa[i] = IEEE_8021QAZ_TSA_STRICT;
61 		else
62 			ets->tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
63 	}
64 }
65 
66 /* IEEE std */
67 static int hclge_ieee_getets(struct hnae3_handle *h, struct ieee_ets *ets)
68 {
69 	struct hclge_vport *vport = hclge_get_vport(h);
70 	struct hclge_dev *hdev = vport->back;
71 
72 	hclge_tm_info_to_ieee_ets(hdev, ets);
73 
74 	return 0;
75 }
76 
77 static int hclge_dcb_common_validate(struct hclge_dev *hdev, u8 num_tc,
78 				     u8 *prio_tc)
79 {
80 	int i;
81 
82 	if (num_tc > hdev->tc_max) {
83 		dev_err(&hdev->pdev->dev,
84 			"tc num checking failed, %u > tc_max(%u)\n",
85 			num_tc, hdev->tc_max);
86 		return -EINVAL;
87 	}
88 
89 	for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
90 		if (prio_tc[i] >= num_tc) {
91 			dev_err(&hdev->pdev->dev,
92 				"prio_tc[%d] checking failed, %u >= num_tc(%u)\n",
93 				i, prio_tc[i], num_tc);
94 			return -EINVAL;
95 		}
96 	}
97 
98 	if (num_tc > hdev->vport[0].alloc_tqps) {
99 		dev_err(&hdev->pdev->dev,
100 			"allocated tqp checking failed, %u > tqp(%u)\n",
101 			num_tc, hdev->vport[0].alloc_tqps);
102 		return -EINVAL;
103 	}
104 
105 	return 0;
106 }
107 
108 static int hclge_ets_validate(struct hclge_dev *hdev, struct ieee_ets *ets,
109 			      u8 *tc, bool *changed)
110 {
111 	bool has_ets_tc = false;
112 	u32 total_ets_bw = 0;
113 	u8 max_tc = 0;
114 	int ret;
115 	u8 i;
116 
117 	for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
118 		if (ets->prio_tc[i] != hdev->tm_info.prio_tc[i])
119 			*changed = true;
120 
121 		if (ets->prio_tc[i] > max_tc)
122 			max_tc = ets->prio_tc[i];
123 	}
124 
125 	ret = hclge_dcb_common_validate(hdev, max_tc + 1, ets->prio_tc);
126 	if (ret)
127 		return ret;
128 
129 	for (i = 0; i < hdev->tc_max; i++) {
130 		switch (ets->tc_tsa[i]) {
131 		case IEEE_8021QAZ_TSA_STRICT:
132 			if (hdev->tm_info.tc_info[i].tc_sch_mode !=
133 				HCLGE_SCH_MODE_SP)
134 				*changed = true;
135 			break;
136 		case IEEE_8021QAZ_TSA_ETS:
137 			if (hdev->tm_info.tc_info[i].tc_sch_mode !=
138 				HCLGE_SCH_MODE_DWRR)
139 				*changed = true;
140 
141 			total_ets_bw += ets->tc_tx_bw[i];
142 			has_ets_tc = true;
143 			break;
144 		default:
145 			return -EINVAL;
146 		}
147 	}
148 
149 	if (has_ets_tc && total_ets_bw != BW_PERCENT)
150 		return -EINVAL;
151 
152 	*tc = max_tc + 1;
153 	if (*tc != hdev->tm_info.num_tc)
154 		*changed = true;
155 
156 	return 0;
157 }
158 
159 static int hclge_map_update(struct hclge_dev *hdev)
160 {
161 	int ret;
162 
163 	ret = hclge_tm_schd_setup_hw(hdev);
164 	if (ret)
165 		return ret;
166 
167 	ret = hclge_pause_setup_hw(hdev, false);
168 	if (ret)
169 		return ret;
170 
171 	ret = hclge_buffer_alloc(hdev);
172 	if (ret)
173 		return ret;
174 
175 	hclge_rss_indir_init_cfg(hdev);
176 
177 	return hclge_rss_init_hw(hdev);
178 }
179 
180 static int hclge_client_setup_tc(struct hclge_dev *hdev)
181 {
182 	struct hclge_vport *vport = hdev->vport;
183 	struct hnae3_client *client;
184 	struct hnae3_handle *handle;
185 	int ret;
186 	u32 i;
187 
188 	for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
189 		handle = &vport[i].nic;
190 		client = handle->client;
191 
192 		if (!client || !client->ops || !client->ops->setup_tc)
193 			continue;
194 
195 		ret = client->ops->setup_tc(handle, hdev->tm_info.num_tc);
196 		if (ret)
197 			return ret;
198 	}
199 
200 	return 0;
201 }
202 
203 static int hclge_notify_down_uinit(struct hclge_dev *hdev)
204 {
205 	int ret;
206 
207 	ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
208 	if (ret)
209 		return ret;
210 
211 	return hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
212 }
213 
214 static int hclge_notify_init_up(struct hclge_dev *hdev)
215 {
216 	int ret;
217 
218 	ret = hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
219 	if (ret)
220 		return ret;
221 
222 	return hclge_notify_client(hdev, HNAE3_UP_CLIENT);
223 }
224 
225 static int hclge_ieee_setets(struct hnae3_handle *h, struct ieee_ets *ets)
226 {
227 	struct hclge_vport *vport = hclge_get_vport(h);
228 	struct net_device *netdev = h->kinfo.netdev;
229 	struct hclge_dev *hdev = vport->back;
230 	bool map_changed = false;
231 	u8 num_tc = 0;
232 	int ret;
233 
234 	if (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||
235 	    hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE)
236 		return -EINVAL;
237 
238 	ret = hclge_ets_validate(hdev, ets, &num_tc, &map_changed);
239 	if (ret)
240 		return ret;
241 
242 	if (map_changed) {
243 		netif_dbg(h, drv, netdev, "set ets\n");
244 
245 		ret = hclge_notify_down_uinit(hdev);
246 		if (ret)
247 			return ret;
248 	}
249 
250 	hclge_tm_schd_info_update(hdev, num_tc);
251 
252 	ret = hclge_ieee_ets_to_tm_info(hdev, ets);
253 	if (ret)
254 		goto err_out;
255 
256 	if (map_changed) {
257 		ret = hclge_map_update(hdev);
258 		if (ret)
259 			goto err_out;
260 
261 		ret = hclge_client_setup_tc(hdev);
262 		if (ret)
263 			goto err_out;
264 
265 		ret = hclge_notify_init_up(hdev);
266 		if (ret)
267 			return ret;
268 	}
269 
270 	return hclge_tm_dwrr_cfg(hdev);
271 
272 err_out:
273 	if (!map_changed)
274 		return ret;
275 
276 	hclge_notify_init_up(hdev);
277 
278 	return ret;
279 }
280 
281 static int hclge_ieee_getpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
282 {
283 	u64 requests[HNAE3_MAX_TC], indications[HNAE3_MAX_TC];
284 	struct hclge_vport *vport = hclge_get_vport(h);
285 	struct hclge_dev *hdev = vport->back;
286 	u8 i, j, pfc_map, *prio_tc;
287 	int ret;
288 
289 	memset(pfc, 0, sizeof(*pfc));
290 	pfc->pfc_cap = hdev->pfc_max;
291 	prio_tc = hdev->tm_info.prio_tc;
292 	pfc_map = hdev->tm_info.hw_pfc_map;
293 
294 	/* Pfc setting is based on TC */
295 	for (i = 0; i < hdev->tm_info.num_tc; i++) {
296 		for (j = 0; j < HNAE3_MAX_USER_PRIO; j++) {
297 			if ((prio_tc[j] == i) && (pfc_map & BIT(i)))
298 				pfc->pfc_en |= BIT(j);
299 		}
300 	}
301 
302 	ret = hclge_pfc_tx_stats_get(hdev, requests);
303 	if (ret)
304 		return ret;
305 
306 	ret = hclge_pfc_rx_stats_get(hdev, indications);
307 	if (ret)
308 		return ret;
309 
310 	for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
311 		pfc->requests[i] = requests[i];
312 		pfc->indications[i] = indications[i];
313 	}
314 	return 0;
315 }
316 
317 static int hclge_ieee_setpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
318 {
319 	struct hclge_vport *vport = hclge_get_vport(h);
320 	struct net_device *netdev = h->kinfo.netdev;
321 	struct hclge_dev *hdev = vport->back;
322 	u8 i, j, pfc_map, *prio_tc;
323 	int ret;
324 
325 	if (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) ||
326 	    hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE)
327 		return -EINVAL;
328 
329 	if (pfc->pfc_en == hdev->tm_info.pfc_en)
330 		return 0;
331 
332 	prio_tc = hdev->tm_info.prio_tc;
333 	pfc_map = 0;
334 
335 	for (i = 0; i < hdev->tm_info.num_tc; i++) {
336 		for (j = 0; j < HNAE3_MAX_USER_PRIO; j++) {
337 			if ((prio_tc[j] == i) && (pfc->pfc_en & BIT(j))) {
338 				pfc_map |= BIT(i);
339 				break;
340 			}
341 		}
342 	}
343 
344 	hdev->tm_info.hw_pfc_map = pfc_map;
345 	hdev->tm_info.pfc_en = pfc->pfc_en;
346 
347 	netif_dbg(h, drv, netdev,
348 		  "set pfc: pfc_en=%x, pfc_map=%x, num_tc=%u\n",
349 		  pfc->pfc_en, pfc_map, hdev->tm_info.num_tc);
350 
351 	hclge_tm_pfc_info_update(hdev);
352 
353 	ret = hclge_pause_setup_hw(hdev, false);
354 	if (ret)
355 		return ret;
356 
357 	ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
358 	if (ret)
359 		return ret;
360 
361 	ret = hclge_buffer_alloc(hdev);
362 	if (ret) {
363 		hclge_notify_client(hdev, HNAE3_UP_CLIENT);
364 		return ret;
365 	}
366 
367 	return hclge_notify_client(hdev, HNAE3_UP_CLIENT);
368 }
369 
370 /* DCBX configuration */
371 static u8 hclge_getdcbx(struct hnae3_handle *h)
372 {
373 	struct hclge_vport *vport = hclge_get_vport(h);
374 	struct hclge_dev *hdev = vport->back;
375 
376 	if (hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE)
377 		return 0;
378 
379 	return hdev->dcbx_cap;
380 }
381 
382 static u8 hclge_setdcbx(struct hnae3_handle *h, u8 mode)
383 {
384 	struct hclge_vport *vport = hclge_get_vport(h);
385 	struct net_device *netdev = h->kinfo.netdev;
386 	struct hclge_dev *hdev = vport->back;
387 
388 	netif_dbg(h, drv, netdev, "set dcbx: mode=%u\n", mode);
389 
390 	/* No support for LLD_MANAGED modes or CEE */
391 	if ((mode & DCB_CAP_DCBX_LLD_MANAGED) ||
392 	    (mode & DCB_CAP_DCBX_VER_CEE) ||
393 	    !(mode & DCB_CAP_DCBX_HOST))
394 		return 1;
395 
396 	hdev->dcbx_cap = mode;
397 
398 	return 0;
399 }
400 
401 /* Set up TC for hardware offloaded mqprio in channel mode */
402 static int hclge_setup_tc(struct hnae3_handle *h, u8 tc, u8 *prio_tc)
403 {
404 	struct hclge_vport *vport = hclge_get_vport(h);
405 	struct hclge_dev *hdev = vport->back;
406 	int ret;
407 
408 	if (hdev->flag & HCLGE_FLAG_DCB_ENABLE)
409 		return -EINVAL;
410 
411 	ret = hclge_dcb_common_validate(hdev, tc, prio_tc);
412 	if (ret)
413 		return -EINVAL;
414 
415 	ret = hclge_notify_down_uinit(hdev);
416 	if (ret)
417 		return ret;
418 
419 	hclge_tm_schd_info_update(hdev, tc);
420 	hclge_tm_prio_tc_info_update(hdev, prio_tc);
421 
422 	ret = hclge_tm_init_hw(hdev, false);
423 	if (ret)
424 		goto err_out;
425 
426 	ret = hclge_client_setup_tc(hdev);
427 	if (ret)
428 		goto err_out;
429 
430 	hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE;
431 
432 	if (tc > 1)
433 		hdev->flag |= HCLGE_FLAG_MQPRIO_ENABLE;
434 	else
435 		hdev->flag &= ~HCLGE_FLAG_MQPRIO_ENABLE;
436 
437 	return hclge_notify_init_up(hdev);
438 
439 err_out:
440 	hclge_notify_init_up(hdev);
441 
442 	return ret;
443 }
444 
445 static const struct hnae3_dcb_ops hns3_dcb_ops = {
446 	.ieee_getets	= hclge_ieee_getets,
447 	.ieee_setets	= hclge_ieee_setets,
448 	.ieee_getpfc	= hclge_ieee_getpfc,
449 	.ieee_setpfc	= hclge_ieee_setpfc,
450 	.getdcbx	= hclge_getdcbx,
451 	.setdcbx	= hclge_setdcbx,
452 	.setup_tc	= hclge_setup_tc,
453 };
454 
455 void hclge_dcb_ops_set(struct hclge_dev *hdev)
456 {
457 	struct hclge_vport *vport = hdev->vport;
458 	struct hnae3_knic_private_info *kinfo;
459 
460 	/* Hdev does not support DCB or vport is
461 	 * not a pf, then dcb_ops is not set.
462 	 */
463 	if (!hnae3_dev_dcb_supported(hdev) ||
464 	    vport->vport_id != 0)
465 		return;
466 
467 	kinfo = &vport->nic.kinfo;
468 	kinfo->dcb_ops = &hns3_dcb_ops;
469 	hdev->dcbx_cap = DCB_CAP_DCBX_VER_IEEE | DCB_CAP_DCBX_HOST;
470 }
471