1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_CMD_H 5 #define __HCLGE_CMD_H 6 #include <linux/types.h> 7 #include <linux/io.h> 8 #include <linux/etherdevice.h> 9 #include "hnae3.h" 10 11 #define HCLGE_CMDQ_TX_TIMEOUT 30000 12 #define HCLGE_DESC_DATA_LEN 6 13 14 struct hclge_dev; 15 struct hclge_desc { 16 __le16 opcode; 17 18 #define HCLGE_CMDQ_RX_INVLD_B 0 19 #define HCLGE_CMDQ_RX_OUTVLD_B 1 20 21 __le16 flag; 22 __le16 retval; 23 __le16 rsv; 24 __le32 data[HCLGE_DESC_DATA_LEN]; 25 }; 26 27 struct hclge_cmq_ring { 28 dma_addr_t desc_dma_addr; 29 struct hclge_desc *desc; 30 struct hclge_dev *dev; 31 u32 head; 32 u32 tail; 33 34 u16 buf_size; 35 u16 desc_num; 36 int next_to_use; 37 int next_to_clean; 38 u8 ring_type; /* cmq ring type */ 39 spinlock_t lock; /* Command queue lock */ 40 }; 41 42 enum hclge_cmd_return_status { 43 HCLGE_CMD_EXEC_SUCCESS = 0, 44 HCLGE_CMD_NO_AUTH = 1, 45 HCLGE_CMD_NOT_SUPPORTED = 2, 46 HCLGE_CMD_QUEUE_FULL = 3, 47 HCLGE_CMD_NEXT_ERR = 4, 48 HCLGE_CMD_UNEXE_ERR = 5, 49 HCLGE_CMD_PARA_ERR = 6, 50 HCLGE_CMD_RESULT_ERR = 7, 51 HCLGE_CMD_TIMEOUT = 8, 52 HCLGE_CMD_HILINK_ERR = 9, 53 HCLGE_CMD_QUEUE_ILLEGAL = 10, 54 HCLGE_CMD_INVALID = 11, 55 }; 56 57 enum hclge_cmd_status { 58 HCLGE_STATUS_SUCCESS = 0, 59 HCLGE_ERR_CSQ_FULL = -1, 60 HCLGE_ERR_CSQ_TIMEOUT = -2, 61 HCLGE_ERR_CSQ_ERROR = -3, 62 }; 63 64 struct hclge_misc_vector { 65 u8 __iomem *addr; 66 int vector_irq; 67 char name[HNAE3_INT_NAME_LEN]; 68 }; 69 70 struct hclge_cmq { 71 struct hclge_cmq_ring csq; 72 struct hclge_cmq_ring crq; 73 u16 tx_timeout; 74 enum hclge_cmd_status last_status; 75 }; 76 77 #define HCLGE_CMD_FLAG_IN BIT(0) 78 #define HCLGE_CMD_FLAG_OUT BIT(1) 79 #define HCLGE_CMD_FLAG_NEXT BIT(2) 80 #define HCLGE_CMD_FLAG_WR BIT(3) 81 #define HCLGE_CMD_FLAG_NO_INTR BIT(4) 82 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5) 83 84 enum hclge_opcode_type { 85 /* Generic commands */ 86 HCLGE_OPC_QUERY_FW_VER = 0x0001, 87 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, 88 HCLGE_OPC_GBL_RST_STATUS = 0x0021, 89 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, 90 HCLGE_OPC_QUERY_PF_RSRC = 0x0023, 91 HCLGE_OPC_QUERY_VF_RSRC = 0x0024, 92 HCLGE_OPC_GET_CFG_PARAM = 0x0025, 93 HCLGE_OPC_PF_RST_DONE = 0x0026, 94 HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027, 95 96 HCLGE_OPC_STATS_64_BIT = 0x0030, 97 HCLGE_OPC_STATS_32_BIT = 0x0031, 98 HCLGE_OPC_STATS_MAC = 0x0032, 99 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033, 100 HCLGE_OPC_STATS_MAC_ALL = 0x0034, 101 102 HCLGE_OPC_QUERY_REG_NUM = 0x0040, 103 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, 104 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, 105 HCLGE_OPC_DFX_BD_NUM = 0x0043, 106 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044, 107 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045, 108 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046, 109 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047, 110 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048, 111 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049, 112 HCLGE_OPC_DFX_NCSI_REG = 0x004A, 113 HCLGE_OPC_DFX_RTC_REG = 0x004B, 114 HCLGE_OPC_DFX_PPP_REG = 0x004C, 115 HCLGE_OPC_DFX_RCB_REG = 0x004D, 116 HCLGE_OPC_DFX_TQP_REG = 0x004E, 117 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F, 118 119 HCLGE_OPC_QUERY_DEV_SPECS = 0x0050, 120 121 /* MAC command */ 122 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, 123 HCLGE_OPC_CONFIG_AN_MODE = 0x0304, 124 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, 125 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, 126 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, 127 HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310, 128 HCLGE_OPC_MAC_TNL_INT_EN = 0x0311, 129 HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312, 130 HCLGE_OPC_COMMON_LOOPBACK = 0x0315, 131 HCLGE_OPC_CONFIG_FEC_MODE = 0x031A, 132 133 /* PTP commands */ 134 HCLGE_OPC_PTP_INT_EN = 0x0501, 135 HCLGE_OPC_PTP_MODE_CFG = 0x0507, 136 137 /* PFC/Pause commands */ 138 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, 139 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, 140 HCLGE_OPC_CFG_MAC_PARA = 0x0703, 141 HCLGE_OPC_CFG_PFC_PARA = 0x0704, 142 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, 143 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, 144 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, 145 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, 146 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, 147 HCLGE_OPC_QOS_MAP = 0x070A, 148 149 /* ETS/scheduler commands */ 150 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, 151 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, 152 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, 153 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, 154 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, 155 HCLGE_OPC_TM_PG_WEIGHT = 0x0809, 156 HCLGE_OPC_TM_QS_WEIGHT = 0x080A, 157 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, 158 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, 159 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, 160 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, 161 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, 162 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, 163 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, 164 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, 165 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, 166 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, 167 HCLGE_OPC_TM_NODES = 0x0816, 168 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843, 169 HCLGE_OPC_QSET_DFX_STS = 0x0844, 170 HCLGE_OPC_PRI_DFX_STS = 0x0845, 171 HCLGE_OPC_PG_DFX_STS = 0x0846, 172 HCLGE_OPC_PORT_DFX_STS = 0x0847, 173 HCLGE_OPC_SCH_NQ_CNT = 0x0848, 174 HCLGE_OPC_SCH_RQ_CNT = 0x0849, 175 HCLGE_OPC_TM_INTERNAL_STS = 0x0850, 176 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851, 177 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852, 178 179 /* Packet buffer allocate commands */ 180 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, 181 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, 182 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, 183 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, 184 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, 185 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, 186 187 /* TQP management command */ 188 HCLGE_OPC_SET_TQP_MAP = 0x0A01, 189 190 /* TQP commands */ 191 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, 192 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, 193 HCLGE_OPC_QUERY_TX_STATS = 0x0B03, 194 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04, 195 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, 196 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, 197 HCLGE_OPC_QUERY_RX_STATS = 0x0B13, 198 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, 199 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, 200 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 201 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, 202 203 /* PPU commands */ 204 HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A, 205 206 /* TSO command */ 207 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, 208 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10, 209 210 /* RSS commands */ 211 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, 212 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, 213 HCLGE_OPC_RSS_TC_MODE = 0x0D08, 214 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, 215 216 /* Promisuous mode command */ 217 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, 218 219 /* Vlan offload commands */ 220 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, 221 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, 222 223 /* Interrupts commands */ 224 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, 225 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, 226 227 /* MAC commands */ 228 HCLGE_OPC_MAC_VLAN_ADD = 0x1000, 229 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, 230 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, 231 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, 232 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004, 233 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, 234 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, 235 236 /* MAC VLAN commands */ 237 HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033, 238 239 /* VLAN commands */ 240 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, 241 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, 242 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, 243 HCLGE_OPC_PORT_VLAN_BYPASS = 0x1103, 244 245 /* Flow Director commands */ 246 HCLGE_OPC_FD_MODE_CTRL = 0x1200, 247 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201, 248 HCLGE_OPC_FD_KEY_CONFIG = 0x1202, 249 HCLGE_OPC_FD_TCAM_OP = 0x1203, 250 HCLGE_OPC_FD_AD_OP = 0x1204, 251 HCLGE_OPC_FD_CNT_OP = 0x1205, 252 HCLGE_OPC_FD_USER_DEF_OP = 0x1207, 253 254 /* MDIO command */ 255 HCLGE_OPC_MDIO_CONFIG = 0x1900, 256 257 /* QCN commands */ 258 HCLGE_OPC_QCN_MOD_CFG = 0x1A01, 259 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, 260 HCLGE_OPC_QCN_SHAPPING_CFG = 0x1A03, 261 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, 262 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, 263 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, 264 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, 265 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, 266 267 /* Mailbox command */ 268 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, 269 270 /* Led command */ 271 HCLGE_OPC_LED_STATUS_CFG = 0xB000, 272 273 /* NCL config command */ 274 HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011, 275 276 /* IMP stats command */ 277 HCLGE_OPC_IMP_STATS_BD = 0x7012, 278 HCLGE_OPC_IMP_STATS_INFO = 0x7013, 279 HCLGE_OPC_IMP_COMPAT_CFG = 0x701A, 280 281 /* SFP command */ 282 HCLGE_OPC_GET_SFP_EEPROM = 0x7100, 283 HCLGE_OPC_GET_SFP_EXIST = 0x7101, 284 HCLGE_OPC_GET_SFP_INFO = 0x7104, 285 286 /* Error INT commands */ 287 HCLGE_MAC_COMMON_INT_EN = 0x030E, 288 HCLGE_TM_SCH_ECC_INT_EN = 0x0829, 289 HCLGE_SSU_ECC_INT_CMD = 0x0989, 290 HCLGE_SSU_COMMON_INT_CMD = 0x098C, 291 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40, 292 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41, 293 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42, 294 HCLGE_COMMON_ECC_INT_CFG = 0x1505, 295 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510, 296 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511, 297 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512, 298 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513, 299 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514, 300 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515, 301 HCLGE_QUERY_ALL_ERR_BD_NUM = 0x1516, 302 HCLGE_QUERY_ALL_ERR_INFO = 0x1517, 303 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580, 304 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581, 305 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584, 306 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585, 307 HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586, 308 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803, 309 HCLGE_IGU_COMMON_INT_EN = 0x1806, 310 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14, 311 HCLGE_PPP_CMD0_INT_CMD = 0x2100, 312 HCLGE_PPP_CMD1_INT_CMD = 0x2101, 313 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105, 314 HCLGE_NCSI_INT_EN = 0x2401, 315 316 /* PHY command */ 317 HCLGE_OPC_PHY_LINK_KSETTING = 0x7025, 318 HCLGE_OPC_PHY_REG = 0x7026, 319 320 /* Query link diagnosis info command */ 321 HCLGE_OPC_QUERY_LINK_DIAGNOSIS = 0x702A, 322 }; 323 324 #define HCLGE_TQP_REG_OFFSET 0x80000 325 #define HCLGE_TQP_REG_SIZE 0x200 326 327 #define HCLGE_TQP_MAX_SIZE_DEV_V2 1024 328 #define HCLGE_TQP_EXT_REG_OFFSET 0x100 329 330 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 331 #define HCLGE_RCB_INIT_FLAG_EN_B 0 332 #define HCLGE_RCB_INIT_FLAG_FINI_B 8 333 struct hclge_config_rcb_init_cmd { 334 __le16 rcb_init_flag; 335 u8 rsv[22]; 336 }; 337 338 struct hclge_tqp_map_cmd { 339 __le16 tqp_id; /* Absolute tqp id for in this pf */ 340 u8 tqp_vf; /* VF id */ 341 #define HCLGE_TQP_MAP_TYPE_PF 0 342 #define HCLGE_TQP_MAP_TYPE_VF 1 343 #define HCLGE_TQP_MAP_TYPE_B 0 344 #define HCLGE_TQP_MAP_EN_B 1 345 u8 tqp_flag; /* Indicate it's pf or vf tqp */ 346 __le16 tqp_vid; /* Virtual id in this pf/vf */ 347 u8 rsv[18]; 348 }; 349 350 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 351 352 enum hclge_int_type { 353 HCLGE_INT_TX, 354 HCLGE_INT_RX, 355 HCLGE_INT_EVENT, 356 }; 357 358 struct hclge_ctrl_vector_chain_cmd { 359 #define HCLGE_VECTOR_ID_L_S 0 360 #define HCLGE_VECTOR_ID_L_M GENMASK(7, 0) 361 u8 int_vector_id_l; 362 u8 int_cause_num; 363 #define HCLGE_INT_TYPE_S 0 364 #define HCLGE_INT_TYPE_M GENMASK(1, 0) 365 #define HCLGE_TQP_ID_S 2 366 #define HCLGE_TQP_ID_M GENMASK(12, 2) 367 #define HCLGE_INT_GL_IDX_S 13 368 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) 369 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; 370 u8 vfid; 371 #define HCLGE_VECTOR_ID_H_S 8 372 #define HCLGE_VECTOR_ID_H_M GENMASK(15, 8) 373 u8 int_vector_id_h; 374 }; 375 376 #define HCLGE_MAX_TC_NUM 8 377 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ 378 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ 379 struct hclge_tx_buff_alloc_cmd { 380 __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM]; 381 u8 tx_buff_rsv[8]; 382 }; 383 384 struct hclge_rx_priv_buff_cmd { 385 __le16 buf_num[HCLGE_MAX_TC_NUM]; 386 __le16 shared_buf; 387 u8 rsv[6]; 388 }; 389 390 enum HCLGE_CAP_BITS { 391 HCLGE_CAP_UDP_GSO_B, 392 HCLGE_CAP_QB_B, 393 HCLGE_CAP_FD_FORWARD_TC_B, 394 HCLGE_CAP_PTP_B, 395 HCLGE_CAP_INT_QL_B, 396 HCLGE_CAP_HW_TX_CSUM_B, 397 HCLGE_CAP_TX_PUSH_B, 398 HCLGE_CAP_PHY_IMP_B, 399 HCLGE_CAP_TQP_TXRX_INDEP_B, 400 HCLGE_CAP_HW_PAD_B, 401 HCLGE_CAP_STASH_B, 402 HCLGE_CAP_UDP_TUNNEL_CSUM_B, 403 HCLGE_CAP_RAS_IMP_B = 12, 404 HCLGE_CAP_FEC_B = 13, 405 HCLGE_CAP_PAUSE_B = 14, 406 HCLGE_CAP_RXD_ADV_LAYOUT_B = 15, 407 HCLGE_CAP_PORT_VLAN_BYPASS_B = 17, 408 }; 409 410 enum HCLGE_API_CAP_BITS { 411 HCLGE_API_CAP_FLEX_RSS_TBL_B, 412 }; 413 414 #define HCLGE_QUERY_CAP_LENGTH 3 415 struct hclge_query_version_cmd { 416 __le32 firmware; 417 __le32 hardware; 418 __le32 api_caps; 419 __le32 caps[HCLGE_QUERY_CAP_LENGTH]; /* capabilities of device */ 420 }; 421 422 #define HCLGE_RX_PRIV_EN_B 15 423 #define HCLGE_TC_NUM_ONE_DESC 4 424 struct hclge_priv_wl { 425 __le16 high; 426 __le16 low; 427 }; 428 429 struct hclge_rx_priv_wl_buf { 430 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; 431 }; 432 433 struct hclge_rx_com_thrd { 434 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; 435 }; 436 437 struct hclge_rx_com_wl { 438 struct hclge_priv_wl com_wl; 439 }; 440 441 struct hclge_waterline { 442 u32 low; 443 u32 high; 444 }; 445 446 struct hclge_tc_thrd { 447 u32 low; 448 u32 high; 449 }; 450 451 struct hclge_priv_buf { 452 struct hclge_waterline wl; /* Waterline for low and high*/ 453 u32 buf_size; /* TC private buffer size */ 454 u32 tx_buf_size; 455 u32 enable; /* Enable TC private buffer or not */ 456 }; 457 458 struct hclge_shared_buf { 459 struct hclge_waterline self; 460 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; 461 u32 buf_size; 462 }; 463 464 struct hclge_pkt_buf_alloc { 465 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; 466 struct hclge_shared_buf s_buf; 467 }; 468 469 #define HCLGE_RX_COM_WL_EN_B 15 470 struct hclge_rx_com_wl_buf_cmd { 471 __le16 high_wl; 472 __le16 low_wl; 473 u8 rsv[20]; 474 }; 475 476 #define HCLGE_RX_PKT_EN_B 15 477 struct hclge_rx_pkt_buf_cmd { 478 __le16 high_pkt; 479 __le16 low_pkt; 480 u8 rsv[20]; 481 }; 482 483 #define HCLGE_PF_STATE_DONE_B 0 484 #define HCLGE_PF_STATE_MAIN_B 1 485 #define HCLGE_PF_STATE_BOND_B 2 486 #define HCLGE_PF_STATE_MAC_N_B 6 487 #define HCLGE_PF_MAC_NUM_MASK 0x3 488 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) 489 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) 490 #define HCLGE_VF_RST_STATUS_CMD 4 491 492 struct hclge_func_status_cmd { 493 __le32 vf_rst_state[HCLGE_VF_RST_STATUS_CMD]; 494 u8 pf_state; 495 u8 mac_id; 496 u8 rsv1; 497 u8 pf_cnt_in_mac; 498 u8 pf_num; 499 u8 vf_num; 500 u8 rsv[2]; 501 }; 502 503 struct hclge_pf_res_cmd { 504 __le16 tqp_num; 505 __le16 buf_size; 506 __le16 msixcap_localid_ba_nic; 507 __le16 msixcap_localid_number_nic; 508 __le16 pf_intr_vector_number_roce; 509 __le16 pf_own_fun_number; 510 __le16 tx_buf_size; 511 __le16 dv_buf_size; 512 __le16 ext_tqp_num; 513 u8 rsv[6]; 514 }; 515 516 #define HCLGE_CFG_OFFSET_S 0 517 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) 518 #define HCLGE_CFG_RD_LEN_S 24 519 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) 520 #define HCLGE_CFG_RD_LEN_BYTES 16 521 #define HCLGE_CFG_RD_LEN_UNIT 4 522 523 #define HCLGE_CFG_TC_NUM_S 8 524 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) 525 #define HCLGE_CFG_TQP_DESC_N_S 16 526 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) 527 #define HCLGE_CFG_PHY_ADDR_S 0 528 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) 529 #define HCLGE_CFG_MEDIA_TP_S 8 530 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) 531 #define HCLGE_CFG_RX_BUF_LEN_S 16 532 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) 533 #define HCLGE_CFG_MAC_ADDR_H_S 0 534 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) 535 #define HCLGE_CFG_DEFAULT_SPEED_S 16 536 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) 537 #define HCLGE_CFG_RSS_SIZE_S 24 538 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) 539 #define HCLGE_CFG_SPEED_ABILITY_S 0 540 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) 541 #define HCLGE_CFG_SPEED_ABILITY_EXT_S 10 542 #define HCLGE_CFG_SPEED_ABILITY_EXT_M GENMASK(15, 10) 543 #define HCLGE_CFG_VLAN_FLTR_CAP_S 8 544 #define HCLGE_CFG_VLAN_FLTR_CAP_M GENMASK(9, 8) 545 #define HCLGE_CFG_UMV_TBL_SPACE_S 16 546 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) 547 #define HCLGE_CFG_PF_RSS_SIZE_S 0 548 #define HCLGE_CFG_PF_RSS_SIZE_M GENMASK(3, 0) 549 #define HCLGE_CFG_TX_SPARE_BUF_SIZE_S 4 550 #define HCLGE_CFG_TX_SPARE_BUF_SIZE_M GENMASK(15, 4) 551 552 #define HCLGE_CFG_CMD_CNT 4 553 554 struct hclge_cfg_param_cmd { 555 __le32 offset; 556 __le32 rsv; 557 __le32 param[HCLGE_CFG_CMD_CNT]; 558 }; 559 560 #define HCLGE_MAC_MODE 0x0 561 #define HCLGE_DESC_NUM 0x40 562 563 #define HCLGE_ALLOC_VALID_B 0 564 struct hclge_vf_num_cmd { 565 u8 alloc_valid; 566 u8 rsv[23]; 567 }; 568 569 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 570 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 571 #define HCLGE_RSS_HASH_KEY_NUM 16 572 struct hclge_rss_config_cmd { 573 u8 hash_config; 574 u8 rsv[7]; 575 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; 576 }; 577 578 struct hclge_rss_input_tuple_cmd { 579 u8 ipv4_tcp_en; 580 u8 ipv4_udp_en; 581 u8 ipv4_sctp_en; 582 u8 ipv4_fragment_en; 583 u8 ipv6_tcp_en; 584 u8 ipv6_udp_en; 585 u8 ipv6_sctp_en; 586 u8 ipv6_fragment_en; 587 u8 rsv[16]; 588 }; 589 590 #define HCLGE_RSS_CFG_TBL_SIZE 16 591 #define HCLGE_RSS_CFG_TBL_SIZE_H 4 592 #define HCLGE_RSS_CFG_TBL_BW_H 2U 593 #define HCLGE_RSS_CFG_TBL_BW_L 8U 594 595 struct hclge_rss_indirection_table_cmd { 596 __le16 start_table_index; 597 __le16 rss_set_bitmap; 598 u8 rss_qid_h[HCLGE_RSS_CFG_TBL_SIZE_H]; 599 u8 rss_qid_l[HCLGE_RSS_CFG_TBL_SIZE]; 600 }; 601 602 #define HCLGE_RSS_TC_OFFSET_S 0 603 #define HCLGE_RSS_TC_OFFSET_M GENMASK(10, 0) 604 #define HCLGE_RSS_TC_SIZE_MSB_B 11 605 #define HCLGE_RSS_TC_SIZE_S 12 606 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) 607 #define HCLGE_RSS_TC_SIZE_MSB_OFFSET 3 608 #define HCLGE_RSS_TC_VALID_B 15 609 struct hclge_rss_tc_mode_cmd { 610 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; 611 u8 rsv[8]; 612 }; 613 614 #define HCLGE_LINK_STATUS_UP_B 0 615 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B) 616 struct hclge_link_status_cmd { 617 u8 status; 618 u8 rsv[23]; 619 }; 620 621 /* for DEVICE_VERSION_V1/2, reference to promisc cmd byte8 */ 622 #define HCLGE_PROMISC_EN_UC 1 623 #define HCLGE_PROMISC_EN_MC 2 624 #define HCLGE_PROMISC_EN_BC 3 625 #define HCLGE_PROMISC_TX_EN 4 626 #define HCLGE_PROMISC_RX_EN 5 627 628 /* for DEVICE_VERSION_V3, reference to promisc cmd byte10 */ 629 #define HCLGE_PROMISC_UC_RX_EN 2 630 #define HCLGE_PROMISC_MC_RX_EN 3 631 #define HCLGE_PROMISC_BC_RX_EN 4 632 #define HCLGE_PROMISC_UC_TX_EN 5 633 #define HCLGE_PROMISC_MC_TX_EN 6 634 #define HCLGE_PROMISC_BC_TX_EN 7 635 636 struct hclge_promisc_cfg_cmd { 637 u8 promisc; 638 u8 vf_id; 639 u8 extend_promisc; 640 u8 rsv0[21]; 641 }; 642 643 enum hclge_promisc_type { 644 HCLGE_UNICAST = 1, 645 HCLGE_MULTICAST = 2, 646 HCLGE_BROADCAST = 3, 647 }; 648 649 #define HCLGE_MAC_TX_EN_B 6 650 #define HCLGE_MAC_RX_EN_B 7 651 #define HCLGE_MAC_PAD_TX_B 11 652 #define HCLGE_MAC_PAD_RX_B 12 653 #define HCLGE_MAC_1588_TX_B 13 654 #define HCLGE_MAC_1588_RX_B 14 655 #define HCLGE_MAC_APP_LP_B 15 656 #define HCLGE_MAC_LINE_LP_B 16 657 #define HCLGE_MAC_FCS_TX_B 17 658 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 659 #define HCLGE_MAC_RX_FCS_STRIP_B 19 660 #define HCLGE_MAC_RX_FCS_B 20 661 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 662 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 663 664 struct hclge_config_mac_mode_cmd { 665 __le32 txrx_pad_fcs_loop_en; 666 u8 rsv[20]; 667 }; 668 669 struct hclge_pf_rst_sync_cmd { 670 #define HCLGE_PF_RST_ALL_VF_RDY_B 0 671 u8 all_vf_ready; 672 u8 rsv[23]; 673 }; 674 675 #define HCLGE_CFG_SPEED_S 0 676 #define HCLGE_CFG_SPEED_M GENMASK(5, 0) 677 678 #define HCLGE_CFG_DUPLEX_B 7 679 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) 680 681 struct hclge_config_mac_speed_dup_cmd { 682 u8 speed_dup; 683 684 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 685 u8 mac_change_fec_en; 686 u8 rsv[22]; 687 }; 688 689 #define HCLGE_TQP_ENABLE_B 0 690 691 #define HCLGE_MAC_CFG_AN_EN_B 0 692 #define HCLGE_MAC_CFG_AN_INT_EN_B 1 693 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 694 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 695 #define HCLGE_MAC_CFG_AN_RST_B 4 696 697 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) 698 699 struct hclge_config_auto_neg_cmd { 700 __le32 cfg_an_cmd_flag; 701 u8 rsv[20]; 702 }; 703 704 struct hclge_sfp_info_cmd { 705 __le32 speed; 706 u8 query_type; /* 0: sfp speed, 1: active speed */ 707 u8 active_fec; 708 u8 autoneg; /* autoneg state */ 709 u8 autoneg_ability; /* whether support autoneg */ 710 __le32 speed_ability; /* speed ability for current media */ 711 __le32 module_type; 712 u8 rsv[8]; 713 }; 714 715 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0 716 #define HCLGE_MAC_CFG_FEC_MODE_S 1 717 #define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1) 718 #define HCLGE_MAC_CFG_FEC_SET_DEF_B 0 719 #define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1 720 721 #define HCLGE_MAC_FEC_OFF 0 722 #define HCLGE_MAC_FEC_BASER 1 723 #define HCLGE_MAC_FEC_RS 2 724 struct hclge_config_fec_cmd { 725 u8 fec_mode; 726 u8 default_config; 727 u8 rsv[22]; 728 }; 729 730 #define HCLGE_MAC_UPLINK_PORT 0x100 731 732 struct hclge_config_max_frm_size_cmd { 733 __le16 max_frm_size; 734 u8 min_frm_size; 735 u8 rsv[21]; 736 }; 737 738 enum hclge_mac_vlan_tbl_opcode { 739 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ 740 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ 741 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ 742 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ 743 }; 744 745 enum hclge_mac_vlan_add_resp_code { 746 HCLGE_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */ 747 HCLGE_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */ 748 }; 749 750 #define HCLGE_MAC_VLAN_BIT0_EN_B 0 751 #define HCLGE_MAC_VLAN_BIT1_EN_B 1 752 #define HCLGE_MAC_EPORT_SW_EN_B 12 753 #define HCLGE_MAC_EPORT_TYPE_B 11 754 #define HCLGE_MAC_EPORT_VFID_S 3 755 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) 756 #define HCLGE_MAC_EPORT_PFID_S 0 757 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) 758 struct hclge_mac_vlan_tbl_entry_cmd { 759 u8 flags; 760 u8 resp_code; 761 __le16 vlan_tag; 762 __le32 mac_addr_hi32; 763 __le16 mac_addr_lo16; 764 __le16 rsv1; 765 u8 entry_type; 766 u8 mc_mac_en; 767 __le16 egress_port; 768 __le16 egress_queue; 769 u8 rsv2[6]; 770 }; 771 772 #define HCLGE_UMV_SPC_ALC_B 0 773 struct hclge_umv_spc_alc_cmd { 774 u8 allocate; 775 u8 rsv1[3]; 776 __le32 space_size; 777 u8 rsv2[16]; 778 }; 779 780 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) 781 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) 782 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) 783 784 struct hclge_mac_mgr_tbl_entry_cmd { 785 u8 flags; 786 u8 resp_code; 787 __le16 vlan_tag; 788 u8 mac_addr[ETH_ALEN]; 789 __le16 rsv1; 790 __le16 ethter_type; 791 __le16 egress_port; 792 __le16 egress_queue; 793 u8 sw_port_id_aware; 794 u8 rsv2; 795 u8 i_port_bitmap; 796 u8 i_port_direction; 797 u8 rsv3[2]; 798 }; 799 800 struct hclge_vlan_filter_ctrl_cmd { 801 u8 vlan_type; 802 u8 vlan_fe; 803 u8 rsv1[2]; 804 u8 vf_id; 805 u8 rsv2[19]; 806 }; 807 808 #define HCLGE_VLAN_ID_OFFSET_STEP 160 809 #define HCLGE_VLAN_BYTE_SIZE 8 810 #define HCLGE_VLAN_OFFSET_BITMAP \ 811 (HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE) 812 813 struct hclge_vlan_filter_pf_cfg_cmd { 814 u8 vlan_offset; 815 u8 vlan_cfg; 816 u8 rsv[2]; 817 u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP]; 818 }; 819 820 #define HCLGE_MAX_VF_BYTES 16 821 822 struct hclge_vlan_filter_vf_cfg_cmd { 823 __le16 vlan_id; 824 u8 resp_code; 825 u8 rsv; 826 u8 vlan_cfg; 827 u8 rsv1[3]; 828 u8 vf_bitmap[HCLGE_MAX_VF_BYTES]; 829 }; 830 831 #define HCLGE_INGRESS_BYPASS_B 0 832 struct hclge_port_vlan_filter_bypass_cmd { 833 u8 bypass_state; 834 u8 rsv1[3]; 835 u8 vf_id; 836 u8 rsv2[19]; 837 }; 838 839 #define HCLGE_SWITCH_ANTI_SPOOF_B 0U 840 #define HCLGE_SWITCH_ALW_LPBK_B 1U 841 #define HCLGE_SWITCH_ALW_LCL_LPBK_B 2U 842 #define HCLGE_SWITCH_ALW_DST_OVRD_B 3U 843 #define HCLGE_SWITCH_NO_MASK 0x0 844 #define HCLGE_SWITCH_ANTI_SPOOF_MASK 0xFE 845 #define HCLGE_SWITCH_ALW_LPBK_MASK 0xFD 846 #define HCLGE_SWITCH_ALW_LCL_LPBK_MASK 0xFB 847 #define HCLGE_SWITCH_LW_DST_OVRD_MASK 0xF7 848 849 struct hclge_mac_vlan_switch_cmd { 850 u8 roce_sel; 851 u8 rsv1[3]; 852 __le32 func_id; 853 u8 switch_param; 854 u8 rsv2[3]; 855 u8 param_mask; 856 u8 rsv3[11]; 857 }; 858 859 enum hclge_mac_vlan_cfg_sel { 860 HCLGE_MAC_VLAN_NIC_SEL = 0, 861 HCLGE_MAC_VLAN_ROCE_SEL, 862 }; 863 864 #define HCLGE_ACCEPT_TAG1_B 0 865 #define HCLGE_ACCEPT_UNTAG1_B 1 866 #define HCLGE_PORT_INS_TAG1_EN_B 2 867 #define HCLGE_PORT_INS_TAG2_EN_B 3 868 #define HCLGE_CFG_NIC_ROCE_SEL_B 4 869 #define HCLGE_ACCEPT_TAG2_B 5 870 #define HCLGE_ACCEPT_UNTAG2_B 6 871 #define HCLGE_TAG_SHIFT_MODE_EN_B 7 872 #define HCLGE_VF_NUM_PER_BYTE 8 873 874 struct hclge_vport_vtag_tx_cfg_cmd { 875 u8 vport_vlan_cfg; 876 u8 vf_offset; 877 u8 rsv1[2]; 878 __le16 def_vlan_tag1; 879 __le16 def_vlan_tag2; 880 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE]; 881 u8 rsv2[8]; 882 }; 883 884 #define HCLGE_REM_TAG1_EN_B 0 885 #define HCLGE_REM_TAG2_EN_B 1 886 #define HCLGE_SHOW_TAG1_EN_B 2 887 #define HCLGE_SHOW_TAG2_EN_B 3 888 #define HCLGE_DISCARD_TAG1_EN_B 5 889 #define HCLGE_DISCARD_TAG2_EN_B 6 890 struct hclge_vport_vtag_rx_cfg_cmd { 891 u8 vport_vlan_cfg; 892 u8 vf_offset; 893 u8 rsv1[6]; 894 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE]; 895 u8 rsv2[8]; 896 }; 897 898 struct hclge_tx_vlan_type_cfg_cmd { 899 __le16 ot_vlan_type; 900 __le16 in_vlan_type; 901 u8 rsv[20]; 902 }; 903 904 struct hclge_rx_vlan_type_cfg_cmd { 905 __le16 ot_fst_vlan_type; 906 __le16 ot_sec_vlan_type; 907 __le16 in_fst_vlan_type; 908 __le16 in_sec_vlan_type; 909 u8 rsv[16]; 910 }; 911 912 struct hclge_cfg_com_tqp_queue_cmd { 913 __le16 tqp_id; 914 __le16 stream_id; 915 u8 enable; 916 u8 rsv[19]; 917 }; 918 919 struct hclge_cfg_tx_queue_pointer_cmd { 920 __le16 tqp_id; 921 __le16 tx_tail; 922 __le16 tx_head; 923 __le16 fbd_num; 924 __le16 ring_offset; 925 u8 rsv[14]; 926 }; 927 928 #pragma pack(1) 929 struct hclge_mac_ethertype_idx_rd_cmd { 930 u8 flags; 931 u8 resp_code; 932 __le16 vlan_tag; 933 u8 mac_addr[ETH_ALEN]; 934 __le16 index; 935 __le16 ethter_type; 936 __le16 egress_port; 937 __le16 egress_queue; 938 __le16 rev0; 939 u8 i_port_bitmap; 940 u8 i_port_direction; 941 u8 rev1[2]; 942 }; 943 944 #pragma pack() 945 946 #define HCLGE_TSO_MSS_MIN_S 0 947 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) 948 949 #define HCLGE_TSO_MSS_MAX_S 16 950 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) 951 952 struct hclge_cfg_tso_status_cmd { 953 __le16 tso_mss_min; 954 __le16 tso_mss_max; 955 u8 rsv[20]; 956 }; 957 958 #define HCLGE_GRO_EN_B 0 959 struct hclge_cfg_gro_status_cmd { 960 u8 gro_en; 961 u8 rsv[23]; 962 }; 963 964 #define HCLGE_TSO_MSS_MIN 256 965 #define HCLGE_TSO_MSS_MAX 9668 966 967 #define HCLGE_TQP_RESET_B 0 968 struct hclge_reset_tqp_queue_cmd { 969 __le16 tqp_id; 970 u8 reset_req; 971 u8 ready_to_reset; 972 u8 rsv[20]; 973 }; 974 975 #define HCLGE_CFG_RESET_MAC_B 3 976 #define HCLGE_CFG_RESET_FUNC_B 7 977 #define HCLGE_CFG_RESET_RCB_B 1 978 struct hclge_reset_cmd { 979 u8 mac_func_reset; 980 u8 fun_reset_vfid; 981 u8 fun_reset_rcb; 982 u8 rsv; 983 __le16 fun_reset_rcb_vqid_start; 984 __le16 fun_reset_rcb_vqid_num; 985 u8 fun_reset_rcb_return_status; 986 u8 rsv1[15]; 987 }; 988 989 #define HCLGE_PF_RESET_DONE_BIT BIT(0) 990 991 struct hclge_pf_rst_done_cmd { 992 u8 pf_rst_done; 993 u8 rsv[23]; 994 }; 995 996 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0) 997 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2) 998 #define HCLGE_CMD_GE_PHY_INNER_LOOP_B BIT(3) 999 #define HCLGE_CMD_COMMON_LB_DONE_B BIT(0) 1000 #define HCLGE_CMD_COMMON_LB_SUCCESS_B BIT(1) 1001 struct hclge_common_lb_cmd { 1002 u8 mask; 1003 u8 enable; 1004 u8 result; 1005 u8 rsv[21]; 1006 }; 1007 1008 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ 1009 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ 1010 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ 1011 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ 1012 #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */ 1013 1014 #define HCLGE_TYPE_CRQ 0 1015 #define HCLGE_TYPE_CSQ 1 1016 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 1017 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 1018 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 1019 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 1020 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 1021 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 1022 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c 1023 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 1024 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 1025 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 1026 1027 /* this bit indicates that the driver is ready for hardware reset */ 1028 #define HCLGE_NIC_SW_RST_RDY_B 16 1029 #define HCLGE_NIC_SW_RST_RDY BIT(HCLGE_NIC_SW_RST_RDY_B) 1030 1031 #define HCLGE_NIC_CMQ_DESC_NUM 1024 1032 #define HCLGE_NIC_CMQ_DESC_NUM_S 3 1033 1034 #define HCLGE_LED_LOCATE_STATE_S 0 1035 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) 1036 1037 struct hclge_set_led_state_cmd { 1038 u8 rsv1[3]; 1039 u8 locate_led_config; 1040 u8 rsv2[20]; 1041 }; 1042 1043 struct hclge_get_fd_mode_cmd { 1044 u8 mode; 1045 u8 enable; 1046 u8 rsv[22]; 1047 }; 1048 1049 struct hclge_get_fd_allocation_cmd { 1050 __le32 stage1_entry_num; 1051 __le32 stage2_entry_num; 1052 __le16 stage1_counter_num; 1053 __le16 stage2_counter_num; 1054 u8 rsv[12]; 1055 }; 1056 1057 struct hclge_set_fd_key_config_cmd { 1058 u8 stage; 1059 u8 key_select; 1060 u8 inner_sipv6_word_en; 1061 u8 inner_dipv6_word_en; 1062 u8 outer_sipv6_word_en; 1063 u8 outer_dipv6_word_en; 1064 u8 rsv1[2]; 1065 __le32 tuple_mask; 1066 __le32 meta_data_mask; 1067 u8 rsv2[8]; 1068 }; 1069 1070 #define HCLGE_FD_EPORT_SW_EN_B 0 1071 struct hclge_fd_tcam_config_1_cmd { 1072 u8 stage; 1073 u8 xy_sel; 1074 u8 port_info; 1075 u8 rsv1[1]; 1076 __le32 index; 1077 u8 entry_vld; 1078 u8 rsv2[7]; 1079 u8 tcam_data[8]; 1080 }; 1081 1082 struct hclge_fd_tcam_config_2_cmd { 1083 u8 tcam_data[24]; 1084 }; 1085 1086 struct hclge_fd_tcam_config_3_cmd { 1087 u8 tcam_data[20]; 1088 u8 rsv[4]; 1089 }; 1090 1091 #define HCLGE_FD_AD_DROP_B 0 1092 #define HCLGE_FD_AD_DIRECT_QID_B 1 1093 #define HCLGE_FD_AD_QID_S 2 1094 #define HCLGE_FD_AD_QID_M GENMASK(11, 2) 1095 #define HCLGE_FD_AD_USE_COUNTER_B 12 1096 #define HCLGE_FD_AD_COUNTER_NUM_S 13 1097 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13) 1098 #define HCLGE_FD_AD_NXT_STEP_B 20 1099 #define HCLGE_FD_AD_NXT_KEY_S 21 1100 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(25, 21) 1101 #define HCLGE_FD_AD_WR_RULE_ID_B 0 1102 #define HCLGE_FD_AD_RULE_ID_S 1 1103 #define HCLGE_FD_AD_RULE_ID_M GENMASK(12, 1) 1104 #define HCLGE_FD_AD_TC_OVRD_B 16 1105 #define HCLGE_FD_AD_TC_SIZE_S 17 1106 #define HCLGE_FD_AD_TC_SIZE_M GENMASK(20, 17) 1107 1108 struct hclge_fd_ad_config_cmd { 1109 u8 stage; 1110 u8 rsv1[3]; 1111 __le32 index; 1112 __le64 ad_data; 1113 u8 rsv2[8]; 1114 }; 1115 1116 struct hclge_fd_ad_cnt_read_cmd { 1117 u8 rsv0[4]; 1118 __le16 index; 1119 u8 rsv1[2]; 1120 __le64 cnt; 1121 u8 rsv2[8]; 1122 }; 1123 1124 #define HCLGE_FD_USER_DEF_OFT_S 0 1125 #define HCLGE_FD_USER_DEF_OFT_M GENMASK(14, 0) 1126 #define HCLGE_FD_USER_DEF_EN_B 15 1127 struct hclge_fd_user_def_cfg_cmd { 1128 __le16 ol2_cfg; 1129 __le16 l2_cfg; 1130 __le16 ol3_cfg; 1131 __le16 l3_cfg; 1132 __le16 ol4_cfg; 1133 __le16 l4_cfg; 1134 u8 rsv[12]; 1135 }; 1136 1137 struct hclge_get_imp_bd_cmd { 1138 __le32 bd_num; 1139 u8 rsv[20]; 1140 }; 1141 1142 struct hclge_query_ppu_pf_other_int_dfx_cmd { 1143 __le16 over_8bd_no_fe_qid; 1144 __le16 over_8bd_no_fe_vf_id; 1145 __le16 tso_mss_cmp_min_err_qid; 1146 __le16 tso_mss_cmp_min_err_vf_id; 1147 __le16 tso_mss_cmp_max_err_qid; 1148 __le16 tso_mss_cmp_max_err_vf_id; 1149 __le16 tx_rd_fbd_poison_qid; 1150 __le16 tx_rd_fbd_poison_vf_id; 1151 __le16 rx_rd_fbd_poison_qid; 1152 __le16 rx_rd_fbd_poison_vf_id; 1153 u8 rsv[4]; 1154 }; 1155 1156 #define HCLGE_LINK_EVENT_REPORT_EN_B 0 1157 #define HCLGE_NCSI_ERROR_REPORT_EN_B 1 1158 #define HCLGE_PHY_IMP_EN_B 2 1159 struct hclge_firmware_compat_cmd { 1160 __le32 compat; 1161 u8 rsv[20]; 1162 }; 1163 1164 #define HCLGE_SFP_INFO_CMD_NUM 6 1165 #define HCLGE_SFP_INFO_BD0_LEN 20 1166 #define HCLGE_SFP_INFO_BDX_LEN 24 1167 #define HCLGE_SFP_INFO_MAX_LEN \ 1168 (HCLGE_SFP_INFO_BD0_LEN + \ 1169 (HCLGE_SFP_INFO_CMD_NUM - 1) * HCLGE_SFP_INFO_BDX_LEN) 1170 1171 struct hclge_sfp_info_bd0_cmd { 1172 __le16 offset; 1173 __le16 read_len; 1174 u8 data[HCLGE_SFP_INFO_BD0_LEN]; 1175 }; 1176 1177 #define HCLGE_QUERY_DEV_SPECS_BD_NUM 4 1178 1179 struct hclge_dev_specs_0_cmd { 1180 __le32 rsv0; 1181 __le32 mac_entry_num; 1182 __le32 mng_entry_num; 1183 __le16 rss_ind_tbl_size; 1184 __le16 rss_key_size; 1185 __le16 int_ql_max; 1186 u8 max_non_tso_bd_num; 1187 u8 rsv1; 1188 __le32 max_tm_rate; 1189 }; 1190 1191 #define HCLGE_DEF_MAX_INT_GL 0x1FE0U 1192 1193 struct hclge_dev_specs_1_cmd { 1194 __le16 max_frm_size; 1195 __le16 max_qset_num; 1196 __le16 max_int_gl; 1197 u8 rsv1[18]; 1198 }; 1199 1200 #define HCLGE_PHY_LINK_SETTING_BD_NUM 2 1201 1202 struct hclge_phy_link_ksetting_0_cmd { 1203 __le32 speed; 1204 u8 duplex; 1205 u8 autoneg; 1206 u8 eth_tp_mdix; 1207 u8 eth_tp_mdix_ctrl; 1208 u8 port; 1209 u8 transceiver; 1210 u8 phy_address; 1211 u8 rsv; 1212 __le32 supported; 1213 __le32 advertising; 1214 __le32 lp_advertising; 1215 }; 1216 1217 struct hclge_phy_link_ksetting_1_cmd { 1218 u8 master_slave_cfg; 1219 u8 master_slave_state; 1220 u8 rsv[22]; 1221 }; 1222 1223 struct hclge_phy_reg_cmd { 1224 __le16 reg_addr; 1225 u8 rsv0[2]; 1226 __le16 reg_val; 1227 u8 rsv1[18]; 1228 }; 1229 1230 int hclge_cmd_init(struct hclge_dev *hdev); 1231 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) 1232 { 1233 writel(value, base + reg); 1234 } 1235 1236 #define hclge_write_dev(a, reg, value) \ 1237 hclge_write_reg((a)->io_base, reg, value) 1238 #define hclge_read_dev(a, reg) \ 1239 hclge_read_reg((a)->io_base, reg) 1240 1241 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) 1242 { 1243 u8 __iomem *reg_addr = READ_ONCE(base); 1244 1245 return readl(reg_addr + reg); 1246 } 1247 1248 #define HCLGE_SEND_SYNC(flag) \ 1249 ((flag) & HCLGE_CMD_FLAG_NO_INTR) 1250 1251 struct hclge_hw; 1252 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); 1253 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, 1254 enum hclge_opcode_type opcode, bool is_read); 1255 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); 1256 1257 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, 1258 struct hclge_desc *desc); 1259 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, 1260 struct hclge_desc *desc); 1261 1262 void hclge_cmd_uninit(struct hclge_dev *hdev); 1263 int hclge_cmd_queue_init(struct hclge_dev *hdev); 1264 #endif 1265