1 /* 2 * Copyright (c) 2016~2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #ifndef __HCLGE_CMD_H 11 #define __HCLGE_CMD_H 12 #include <linux/types.h> 13 #include <linux/io.h> 14 15 #define HCLGE_CMDQ_TX_TIMEOUT 30000 16 17 struct hclge_dev; 18 struct hclge_desc { 19 __le16 opcode; 20 21 #define HCLGE_CMDQ_RX_INVLD_B 0 22 #define HCLGE_CMDQ_RX_OUTVLD_B 1 23 24 __le16 flag; 25 __le16 retval; 26 __le16 rsv; 27 __le32 data[6]; 28 }; 29 30 struct hclge_desc_cb { 31 dma_addr_t dma; 32 void *va; 33 u32 length; 34 }; 35 36 struct hclge_cmq_ring { 37 dma_addr_t desc_dma_addr; 38 struct hclge_desc *desc; 39 struct hclge_desc_cb *desc_cb; 40 struct hclge_dev *dev; 41 u32 head; 42 u32 tail; 43 44 u16 buf_size; 45 u16 desc_num; 46 int next_to_use; 47 int next_to_clean; 48 u8 flag; 49 spinlock_t lock; /* Command queue lock */ 50 }; 51 52 enum hclge_cmd_return_status { 53 HCLGE_CMD_EXEC_SUCCESS = 0, 54 HCLGE_CMD_NO_AUTH = 1, 55 HCLGE_CMD_NOT_EXEC = 2, 56 HCLGE_CMD_QUEUE_FULL = 3, 57 }; 58 59 enum hclge_cmd_status { 60 HCLGE_STATUS_SUCCESS = 0, 61 HCLGE_ERR_CSQ_FULL = -1, 62 HCLGE_ERR_CSQ_TIMEOUT = -2, 63 HCLGE_ERR_CSQ_ERROR = -3, 64 }; 65 66 struct hclge_misc_vector { 67 u8 __iomem *addr; 68 int vector_irq; 69 }; 70 71 struct hclge_cmq { 72 struct hclge_cmq_ring csq; 73 struct hclge_cmq_ring crq; 74 u16 tx_timeout; /* Tx timeout */ 75 enum hclge_cmd_status last_status; 76 }; 77 78 #define HCLGE_CMD_FLAG_IN_VALID_SHIFT 0 79 #define HCLGE_CMD_FLAG_OUT_VALID_SHIFT 1 80 #define HCLGE_CMD_FLAG_NEXT_SHIFT 2 81 #define HCLGE_CMD_FLAG_WR_OR_RD_SHIFT 3 82 #define HCLGE_CMD_FLAG_NO_INTR_SHIFT 4 83 #define HCLGE_CMD_FLAG_ERR_INTR_SHIFT 5 84 85 #define HCLGE_CMD_FLAG_IN BIT(HCLGE_CMD_FLAG_IN_VALID_SHIFT) 86 #define HCLGE_CMD_FLAG_OUT BIT(HCLGE_CMD_FLAG_OUT_VALID_SHIFT) 87 #define HCLGE_CMD_FLAG_NEXT BIT(HCLGE_CMD_FLAG_NEXT_SHIFT) 88 #define HCLGE_CMD_FLAG_WR BIT(HCLGE_CMD_FLAG_WR_OR_RD_SHIFT) 89 #define HCLGE_CMD_FLAG_NO_INTR BIT(HCLGE_CMD_FLAG_NO_INTR_SHIFT) 90 #define HCLGE_CMD_FLAG_ERR_INTR BIT(HCLGE_CMD_FLAG_ERR_INTR_SHIFT) 91 92 enum hclge_opcode_type { 93 /* Generic command */ 94 HCLGE_OPC_QUERY_FW_VER = 0x0001, 95 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, 96 HCLGE_OPC_GBL_RST_STATUS = 0x0021, 97 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, 98 HCLGE_OPC_QUERY_PF_RSRC = 0x0023, 99 HCLGE_OPC_QUERY_VF_RSRC = 0x0024, 100 HCLGE_OPC_GET_CFG_PARAM = 0x0025, 101 102 HCLGE_OPC_STATS_64_BIT = 0x0030, 103 HCLGE_OPC_STATS_32_BIT = 0x0031, 104 HCLGE_OPC_STATS_MAC = 0x0032, 105 106 HCLGE_OPC_QUERY_REG_NUM = 0x0040, 107 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, 108 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, 109 /* Device management command */ 110 111 /* MAC commond */ 112 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, 113 HCLGE_OPC_CONFIG_AN_MODE = 0x0304, 114 HCLGE_OPC_QUERY_AN_RESULT = 0x0306, 115 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, 116 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, 117 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, 118 /* MACSEC command */ 119 120 /* PFC/Pause CMD*/ 121 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, 122 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, 123 HCLGE_OPC_CFG_MAC_PARA = 0x0703, 124 HCLGE_OPC_CFG_PFC_PARA = 0x0704, 125 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, 126 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, 127 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, 128 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, 129 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, 130 HCLGE_OPC_QOS_MAP = 0x070A, 131 132 /* ETS/scheduler commands */ 133 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, 134 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, 135 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, 136 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, 137 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, 138 HCLGE_OPC_TM_PG_WEIGHT = 0x0809, 139 HCLGE_OPC_TM_QS_WEIGHT = 0x080A, 140 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, 141 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, 142 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, 143 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, 144 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, 145 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, 146 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, 147 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, 148 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, 149 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, 150 151 /* Packet buffer allocate command */ 152 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, 153 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, 154 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, 155 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, 156 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, 157 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, 158 159 /* PTP command */ 160 /* TQP management command */ 161 HCLGE_OPC_SET_TQP_MAP = 0x0A01, 162 163 /* TQP command */ 164 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, 165 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, 166 HCLGE_OPC_QUERY_TX_STATUS = 0x0B03, 167 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, 168 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, 169 HCLGE_OPC_QUERY_RX_STATUS = 0x0B13, 170 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, 171 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, 172 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 173 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, 174 175 /* TSO cmd */ 176 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, 177 178 /* RSS cmd */ 179 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, 180 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, 181 HCLGE_OPC_RSS_TC_MODE = 0x0D08, 182 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, 183 184 /* Promisuous mode command */ 185 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, 186 187 /* Vlan offload command */ 188 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, 189 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, 190 191 /* Interrupts cmd */ 192 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, 193 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, 194 195 /* MAC command */ 196 HCLGE_OPC_MAC_VLAN_ADD = 0x1000, 197 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, 198 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, 199 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, 200 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, 201 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, 202 HCLGE_OPC_MAC_VLAN_MASK_SET = 0x1012, 203 204 /* Multicast linear table cmd */ 205 HCLGE_OPC_MTA_MAC_MODE_CFG = 0x1020, 206 HCLGE_OPC_MTA_MAC_FUNC_CFG = 0x1021, 207 HCLGE_OPC_MTA_TBL_ITEM_CFG = 0x1022, 208 HCLGE_OPC_MTA_TBL_ITEM_QUERY = 0x1023, 209 210 /* VLAN command */ 211 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, 212 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, 213 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, 214 215 /* MDIO command */ 216 HCLGE_OPC_MDIO_CONFIG = 0x1900, 217 218 /* QCN command */ 219 HCLGE_OPC_QCN_MOD_CFG = 0x1A01, 220 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, 221 HCLGE_OPC_QCN_SHAPPING_IR_CFG = 0x1A03, 222 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, 223 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, 224 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, 225 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, 226 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, 227 228 /* Mailbox cmd */ 229 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, 230 231 /* Led command */ 232 HCLGE_OPC_LED_STATUS_CFG = 0xB000, 233 }; 234 235 #define HCLGE_TQP_REG_OFFSET 0x80000 236 #define HCLGE_TQP_REG_SIZE 0x200 237 238 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 239 #define HCLGE_RCB_INIT_FLAG_EN_B 0 240 #define HCLGE_RCB_INIT_FLAG_FINI_B 8 241 struct hclge_config_rcb_init_cmd { 242 __le16 rcb_init_flag; 243 u8 rsv[22]; 244 }; 245 246 struct hclge_tqp_map_cmd { 247 __le16 tqp_id; /* Absolute tqp id for in this pf */ 248 u8 tqp_vf; /* VF id */ 249 #define HCLGE_TQP_MAP_TYPE_PF 0 250 #define HCLGE_TQP_MAP_TYPE_VF 1 251 #define HCLGE_TQP_MAP_TYPE_B 0 252 #define HCLGE_TQP_MAP_EN_B 1 253 u8 tqp_flag; /* Indicate it's pf or vf tqp */ 254 __le16 tqp_vid; /* Virtual id in this pf/vf */ 255 u8 rsv[18]; 256 }; 257 258 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 259 260 enum hclge_int_type { 261 HCLGE_INT_TX, 262 HCLGE_INT_RX, 263 HCLGE_INT_EVENT, 264 }; 265 266 struct hclge_ctrl_vector_chain_cmd { 267 u8 int_vector_id; 268 u8 int_cause_num; 269 #define HCLGE_INT_TYPE_S 0 270 #define HCLGE_INT_TYPE_M GENMASK(1, 0) 271 #define HCLGE_TQP_ID_S 2 272 #define HCLGE_TQP_ID_M GENMASK(12, 2) 273 #define HCLGE_INT_GL_IDX_S 13 274 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) 275 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; 276 u8 vfid; 277 u8 rsv; 278 }; 279 280 #define HCLGE_TC_NUM 8 281 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ 282 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ 283 struct hclge_tx_buff_alloc_cmd { 284 __le16 tx_pkt_buff[HCLGE_TC_NUM]; 285 u8 tx_buff_rsv[8]; 286 }; 287 288 struct hclge_rx_priv_buff_cmd { 289 __le16 buf_num[HCLGE_TC_NUM]; 290 __le16 shared_buf; 291 u8 rsv[6]; 292 }; 293 294 struct hclge_query_version_cmd { 295 __le32 firmware; 296 __le32 firmware_rsv[5]; 297 }; 298 299 #define HCLGE_RX_PRIV_EN_B 15 300 #define HCLGE_TC_NUM_ONE_DESC 4 301 struct hclge_priv_wl { 302 __le16 high; 303 __le16 low; 304 }; 305 306 struct hclge_rx_priv_wl_buf { 307 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; 308 }; 309 310 struct hclge_rx_com_thrd { 311 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; 312 }; 313 314 struct hclge_rx_com_wl { 315 struct hclge_priv_wl com_wl; 316 }; 317 318 struct hclge_waterline { 319 u32 low; 320 u32 high; 321 }; 322 323 struct hclge_tc_thrd { 324 u32 low; 325 u32 high; 326 }; 327 328 struct hclge_priv_buf { 329 struct hclge_waterline wl; /* Waterline for low and high*/ 330 u32 buf_size; /* TC private buffer size */ 331 u32 tx_buf_size; 332 u32 enable; /* Enable TC private buffer or not */ 333 }; 334 335 #define HCLGE_MAX_TC_NUM 8 336 struct hclge_shared_buf { 337 struct hclge_waterline self; 338 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; 339 u32 buf_size; 340 }; 341 342 struct hclge_pkt_buf_alloc { 343 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; 344 struct hclge_shared_buf s_buf; 345 }; 346 347 #define HCLGE_RX_COM_WL_EN_B 15 348 struct hclge_rx_com_wl_buf_cmd { 349 __le16 high_wl; 350 __le16 low_wl; 351 u8 rsv[20]; 352 }; 353 354 #define HCLGE_RX_PKT_EN_B 15 355 struct hclge_rx_pkt_buf_cmd { 356 __le16 high_pkt; 357 __le16 low_pkt; 358 u8 rsv[20]; 359 }; 360 361 #define HCLGE_PF_STATE_DONE_B 0 362 #define HCLGE_PF_STATE_MAIN_B 1 363 #define HCLGE_PF_STATE_BOND_B 2 364 #define HCLGE_PF_STATE_MAC_N_B 6 365 #define HCLGE_PF_MAC_NUM_MASK 0x3 366 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) 367 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) 368 struct hclge_func_status_cmd { 369 __le32 vf_rst_state[4]; 370 u8 pf_state; 371 u8 mac_id; 372 u8 rsv1; 373 u8 pf_cnt_in_mac; 374 u8 pf_num; 375 u8 vf_num; 376 u8 rsv[2]; 377 }; 378 379 struct hclge_pf_res_cmd { 380 __le16 tqp_num; 381 __le16 buf_size; 382 __le16 msixcap_localid_ba_nic; 383 __le16 msixcap_localid_ba_rocee; 384 #define HCLGE_PF_VEC_NUM_S 0 385 #define HCLGE_PF_VEC_NUM_M (0xff << HCLGE_PF_VEC_NUM_S) 386 __le16 pf_intr_vector_number; 387 __le16 pf_own_fun_number; 388 __le32 rsv[3]; 389 }; 390 391 #define HCLGE_CFG_OFFSET_S 0 392 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) 393 #define HCLGE_CFG_RD_LEN_S 24 394 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) 395 #define HCLGE_CFG_RD_LEN_BYTES 16 396 #define HCLGE_CFG_RD_LEN_UNIT 4 397 398 #define HCLGE_CFG_VMDQ_S 0 399 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0) 400 #define HCLGE_CFG_TC_NUM_S 8 401 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) 402 #define HCLGE_CFG_TQP_DESC_N_S 16 403 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) 404 #define HCLGE_CFG_PHY_ADDR_S 0 405 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) 406 #define HCLGE_CFG_MEDIA_TP_S 8 407 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) 408 #define HCLGE_CFG_RX_BUF_LEN_S 16 409 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) 410 #define HCLGE_CFG_MAC_ADDR_H_S 0 411 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) 412 #define HCLGE_CFG_DEFAULT_SPEED_S 16 413 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) 414 #define HCLGE_CFG_RSS_SIZE_S 24 415 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) 416 #define HCLGE_CFG_SPEED_ABILITY_S 0 417 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) 418 419 struct hclge_cfg_param_cmd { 420 __le32 offset; 421 __le32 rsv; 422 __le32 param[4]; 423 }; 424 425 #define HCLGE_MAC_MODE 0x0 426 #define HCLGE_DESC_NUM 0x40 427 428 #define HCLGE_ALLOC_VALID_B 0 429 struct hclge_vf_num_cmd { 430 u8 alloc_valid; 431 u8 rsv[23]; 432 }; 433 434 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 435 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 436 #define HCLGE_RSS_HASH_KEY_NUM 16 437 struct hclge_rss_config_cmd { 438 u8 hash_config; 439 u8 rsv[7]; 440 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; 441 }; 442 443 struct hclge_rss_input_tuple_cmd { 444 u8 ipv4_tcp_en; 445 u8 ipv4_udp_en; 446 u8 ipv4_sctp_en; 447 u8 ipv4_fragment_en; 448 u8 ipv6_tcp_en; 449 u8 ipv6_udp_en; 450 u8 ipv6_sctp_en; 451 u8 ipv6_fragment_en; 452 u8 rsv[16]; 453 }; 454 455 #define HCLGE_RSS_CFG_TBL_SIZE 16 456 457 struct hclge_rss_indirection_table_cmd { 458 __le16 start_table_index; 459 __le16 rss_set_bitmap; 460 u8 rsv[4]; 461 u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE]; 462 }; 463 464 #define HCLGE_RSS_TC_OFFSET_S 0 465 #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0) 466 #define HCLGE_RSS_TC_SIZE_S 12 467 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) 468 #define HCLGE_RSS_TC_VALID_B 15 469 struct hclge_rss_tc_mode_cmd { 470 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; 471 u8 rsv[8]; 472 }; 473 474 #define HCLGE_LINK_STS_B 0 475 #define HCLGE_LINK_STATUS BIT(HCLGE_LINK_STS_B) 476 struct hclge_link_status_cmd { 477 u8 status; 478 u8 rsv[23]; 479 }; 480 481 struct hclge_promisc_param { 482 u8 vf_id; 483 u8 enable; 484 }; 485 486 #define HCLGE_PROMISC_TX_EN_B BIT(4) 487 #define HCLGE_PROMISC_RX_EN_B BIT(5) 488 #define HCLGE_PROMISC_EN_B 1 489 #define HCLGE_PROMISC_EN_ALL 0x7 490 #define HCLGE_PROMISC_EN_UC 0x1 491 #define HCLGE_PROMISC_EN_MC 0x2 492 #define HCLGE_PROMISC_EN_BC 0x4 493 struct hclge_promisc_cfg_cmd { 494 u8 flag; 495 u8 vf_id; 496 __le16 rsv0; 497 u8 rsv1[20]; 498 }; 499 500 enum hclge_promisc_type { 501 HCLGE_UNICAST = 1, 502 HCLGE_MULTICAST = 2, 503 HCLGE_BROADCAST = 3, 504 }; 505 506 #define HCLGE_MAC_TX_EN_B 6 507 #define HCLGE_MAC_RX_EN_B 7 508 #define HCLGE_MAC_PAD_TX_B 11 509 #define HCLGE_MAC_PAD_RX_B 12 510 #define HCLGE_MAC_1588_TX_B 13 511 #define HCLGE_MAC_1588_RX_B 14 512 #define HCLGE_MAC_APP_LP_B 15 513 #define HCLGE_MAC_LINE_LP_B 16 514 #define HCLGE_MAC_FCS_TX_B 17 515 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 516 #define HCLGE_MAC_RX_FCS_STRIP_B 19 517 #define HCLGE_MAC_RX_FCS_B 20 518 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 519 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 520 521 struct hclge_config_mac_mode_cmd { 522 __le32 txrx_pad_fcs_loop_en; 523 u8 rsv[20]; 524 }; 525 526 #define HCLGE_CFG_SPEED_S 0 527 #define HCLGE_CFG_SPEED_M GENMASK(5, 0) 528 529 #define HCLGE_CFG_DUPLEX_B 7 530 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) 531 532 struct hclge_config_mac_speed_dup_cmd { 533 u8 speed_dup; 534 535 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 536 u8 mac_change_fec_en; 537 u8 rsv[22]; 538 }; 539 540 #define HCLGE_QUERY_SPEED_S 3 541 #define HCLGE_QUERY_AN_B 0 542 #define HCLGE_QUERY_DUPLEX_B 2 543 544 #define HCLGE_QUERY_SPEED_M GENMASK(4, 0) 545 #define HCLGE_QUERY_AN_M BIT(HCLGE_QUERY_AN_B) 546 #define HCLGE_QUERY_DUPLEX_M BIT(HCLGE_QUERY_DUPLEX_B) 547 548 struct hclge_query_an_speed_dup_cmd { 549 u8 an_syn_dup_speed; 550 u8 pause; 551 u8 rsv[23]; 552 }; 553 554 #define HCLGE_RING_ID_MASK GENMASK(9, 0) 555 #define HCLGE_TQP_ENABLE_B 0 556 557 #define HCLGE_MAC_CFG_AN_EN_B 0 558 #define HCLGE_MAC_CFG_AN_INT_EN_B 1 559 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 560 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 561 #define HCLGE_MAC_CFG_AN_RST_B 4 562 563 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) 564 565 struct hclge_config_auto_neg_cmd { 566 __le32 cfg_an_cmd_flag; 567 u8 rsv[20]; 568 }; 569 570 #define HCLGE_MAC_UPLINK_PORT 0x100 571 572 struct hclge_config_max_frm_size_cmd { 573 __le16 max_frm_size; 574 u8 rsv[22]; 575 }; 576 577 enum hclge_mac_vlan_tbl_opcode { 578 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ 579 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ 580 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ 581 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ 582 }; 583 584 #define HCLGE_MAC_VLAN_BIT0_EN_B 0x0 585 #define HCLGE_MAC_VLAN_BIT1_EN_B 0x1 586 #define HCLGE_MAC_EPORT_SW_EN_B 0xc 587 #define HCLGE_MAC_EPORT_TYPE_B 0xb 588 #define HCLGE_MAC_EPORT_VFID_S 0x3 589 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) 590 #define HCLGE_MAC_EPORT_PFID_S 0x0 591 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) 592 struct hclge_mac_vlan_tbl_entry_cmd { 593 u8 flags; 594 u8 resp_code; 595 __le16 vlan_tag; 596 __le32 mac_addr_hi32; 597 __le16 mac_addr_lo16; 598 __le16 rsv1; 599 u8 entry_type; 600 u8 mc_mac_en; 601 __le16 egress_port; 602 __le16 egress_queue; 603 u8 rsv2[6]; 604 }; 605 606 #define HCLGE_VLAN_MASK_EN_B 0x0 607 struct hclge_mac_vlan_mask_entry_cmd { 608 u8 rsv0[2]; 609 u8 vlan_mask; 610 u8 rsv1; 611 u8 mac_mask[6]; 612 u8 rsv2[14]; 613 }; 614 615 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) 616 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) 617 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) 618 #define HCLGE_MAC_ETHERTYPE_LLDP 0x88cc 619 620 struct hclge_mac_mgr_tbl_entry_cmd { 621 u8 flags; 622 u8 resp_code; 623 __le16 vlan_tag; 624 __le32 mac_addr_hi32; 625 __le16 mac_addr_lo16; 626 __le16 rsv1; 627 __le16 ethter_type; 628 __le16 egress_port; 629 __le16 egress_queue; 630 u8 sw_port_id_aware; 631 u8 rsv2; 632 u8 i_port_bitmap; 633 u8 i_port_direction; 634 u8 rsv3[2]; 635 }; 636 637 #define HCLGE_CFG_MTA_MAC_SEL_S 0x0 638 #define HCLGE_CFG_MTA_MAC_SEL_M GENMASK(1, 0) 639 #define HCLGE_CFG_MTA_MAC_EN_B 0x7 640 struct hclge_mta_filter_mode_cmd { 641 u8 dmac_sel_en; /* Use lowest 2 bit as sel_mode, bit 7 as enable */ 642 u8 rsv[23]; 643 }; 644 645 #define HCLGE_CFG_FUNC_MTA_ACCEPT_B 0x0 646 struct hclge_cfg_func_mta_filter_cmd { 647 u8 accept; /* Only used lowest 1 bit */ 648 u8 function_id; 649 u8 rsv[22]; 650 }; 651 652 #define HCLGE_CFG_MTA_ITEM_ACCEPT_B 0x0 653 #define HCLGE_CFG_MTA_ITEM_IDX_S 0x0 654 #define HCLGE_CFG_MTA_ITEM_IDX_M GENMASK(11, 0) 655 struct hclge_cfg_func_mta_item_cmd { 656 __le16 item_idx; /* Only used lowest 12 bit */ 657 u8 accept; /* Only used lowest 1 bit */ 658 u8 rsv[21]; 659 }; 660 661 struct hclge_mac_vlan_add_cmd { 662 __le16 flags; 663 __le16 mac_addr_hi16; 664 __le32 mac_addr_lo32; 665 __le32 mac_addr_msk_hi32; 666 __le16 mac_addr_msk_lo16; 667 __le16 vlan_tag; 668 __le16 ingress_port; 669 __le16 egress_port; 670 u8 rsv[4]; 671 }; 672 673 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0 674 struct hclge_mac_vlan_remove_cmd { 675 __le16 flags; 676 __le16 mac_addr_hi16; 677 __le32 mac_addr_lo32; 678 __le32 mac_addr_msk_hi32; 679 __le16 mac_addr_msk_lo16; 680 __le16 vlan_tag; 681 __le16 ingress_port; 682 __le16 egress_port; 683 u8 rsv[4]; 684 }; 685 686 struct hclge_vlan_filter_ctrl_cmd { 687 u8 vlan_type; 688 u8 vlan_fe; 689 u8 rsv[22]; 690 }; 691 692 struct hclge_vlan_filter_pf_cfg_cmd { 693 u8 vlan_offset; 694 u8 vlan_cfg; 695 u8 rsv[2]; 696 u8 vlan_offset_bitmap[20]; 697 }; 698 699 struct hclge_vlan_filter_vf_cfg_cmd { 700 __le16 vlan_id; 701 u8 resp_code; 702 u8 rsv; 703 u8 vlan_cfg; 704 u8 rsv1[3]; 705 u8 vf_bitmap[16]; 706 }; 707 708 #define HCLGE_ACCEPT_TAG1_B 0 709 #define HCLGE_ACCEPT_UNTAG1_B 1 710 #define HCLGE_PORT_INS_TAG1_EN_B 2 711 #define HCLGE_PORT_INS_TAG2_EN_B 3 712 #define HCLGE_CFG_NIC_ROCE_SEL_B 4 713 #define HCLGE_ACCEPT_TAG2_B 5 714 #define HCLGE_ACCEPT_UNTAG2_B 6 715 716 struct hclge_vport_vtag_tx_cfg_cmd { 717 u8 vport_vlan_cfg; 718 u8 vf_offset; 719 u8 rsv1[2]; 720 __le16 def_vlan_tag1; 721 __le16 def_vlan_tag2; 722 u8 vf_bitmap[8]; 723 u8 rsv2[8]; 724 }; 725 726 #define HCLGE_REM_TAG1_EN_B 0 727 #define HCLGE_REM_TAG2_EN_B 1 728 #define HCLGE_SHOW_TAG1_EN_B 2 729 #define HCLGE_SHOW_TAG2_EN_B 3 730 struct hclge_vport_vtag_rx_cfg_cmd { 731 u8 vport_vlan_cfg; 732 u8 vf_offset; 733 u8 rsv1[6]; 734 u8 vf_bitmap[8]; 735 u8 rsv2[8]; 736 }; 737 738 struct hclge_tx_vlan_type_cfg_cmd { 739 __le16 ot_vlan_type; 740 __le16 in_vlan_type; 741 u8 rsv[20]; 742 }; 743 744 struct hclge_rx_vlan_type_cfg_cmd { 745 __le16 ot_fst_vlan_type; 746 __le16 ot_sec_vlan_type; 747 __le16 in_fst_vlan_type; 748 __le16 in_sec_vlan_type; 749 u8 rsv[16]; 750 }; 751 752 struct hclge_cfg_com_tqp_queue_cmd { 753 __le16 tqp_id; 754 __le16 stream_id; 755 u8 enable; 756 u8 rsv[19]; 757 }; 758 759 struct hclge_cfg_tx_queue_pointer_cmd { 760 __le16 tqp_id; 761 __le16 tx_tail; 762 __le16 tx_head; 763 __le16 fbd_num; 764 __le16 ring_offset; 765 u8 rsv[14]; 766 }; 767 768 #define HCLGE_TSO_MSS_MIN_S 0 769 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) 770 771 #define HCLGE_TSO_MSS_MAX_S 16 772 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) 773 774 struct hclge_cfg_tso_status_cmd { 775 __le16 tso_mss_min; 776 __le16 tso_mss_max; 777 u8 rsv[20]; 778 }; 779 780 #define HCLGE_TSO_MSS_MIN 256 781 #define HCLGE_TSO_MSS_MAX 9668 782 783 #define HCLGE_TQP_RESET_B 0 784 struct hclge_reset_tqp_queue_cmd { 785 __le16 tqp_id; 786 u8 reset_req; 787 u8 ready_to_reset; 788 u8 rsv[20]; 789 }; 790 791 #define HCLGE_CFG_RESET_MAC_B 3 792 #define HCLGE_CFG_RESET_FUNC_B 7 793 struct hclge_reset_cmd { 794 u8 mac_func_reset; 795 u8 fun_reset_vfid; 796 u8 rsv[22]; 797 }; 798 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ 799 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ 800 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ 801 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ 802 803 #define HCLGE_TYPE_CRQ 0 804 #define HCLGE_TYPE_CSQ 1 805 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 806 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 807 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 808 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 809 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 810 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 811 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c 812 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 813 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 814 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 815 #define HCLGE_NIC_CMQ_EN_B 16 816 #define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B) 817 #define HCLGE_NIC_CMQ_DESC_NUM 1024 818 #define HCLGE_NIC_CMQ_DESC_NUM_S 3 819 820 #define HCLGE_LED_LOCATE_STATE_S 0 821 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) 822 823 struct hclge_set_led_state_cmd { 824 u8 rsv1[3]; 825 u8 locate_led_config; 826 u8 rsv2[20]; 827 }; 828 829 int hclge_cmd_init(struct hclge_dev *hdev); 830 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) 831 { 832 writel(value, base + reg); 833 } 834 835 #define hclge_write_dev(a, reg, value) \ 836 hclge_write_reg((a)->io_base, (reg), (value)) 837 #define hclge_read_dev(a, reg) \ 838 hclge_read_reg((a)->io_base, (reg)) 839 840 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) 841 { 842 u8 __iomem *reg_addr = READ_ONCE(base); 843 844 return readl(reg_addr + reg); 845 } 846 847 #define HCLGE_SEND_SYNC(flag) \ 848 ((flag) & HCLGE_CMD_FLAG_NO_INTR) 849 850 struct hclge_hw; 851 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); 852 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, 853 enum hclge_opcode_type opcode, bool is_read); 854 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); 855 856 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, 857 struct hclge_promisc_param *param); 858 859 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, 860 struct hclge_desc *desc); 861 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, 862 struct hclge_desc *desc); 863 864 void hclge_destroy_cmd_queue(struct hclge_hw *hw); 865 int hclge_cmd_queue_init(struct hclge_dev *hdev); 866 #endif 867