1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_CMD_H 5 #define __HCLGE_CMD_H 6 #include <linux/types.h> 7 #include <linux/io.h> 8 #include <linux/etherdevice.h> 9 #include "hnae3.h" 10 11 #define HCLGE_CMDQ_TX_TIMEOUT 30000 12 #define HCLGE_DESC_DATA_LEN 6 13 14 struct hclge_dev; 15 struct hclge_desc { 16 __le16 opcode; 17 18 #define HCLGE_CMDQ_RX_INVLD_B 0 19 #define HCLGE_CMDQ_RX_OUTVLD_B 1 20 21 __le16 flag; 22 __le16 retval; 23 __le16 rsv; 24 __le32 data[HCLGE_DESC_DATA_LEN]; 25 }; 26 27 struct hclge_cmq_ring { 28 dma_addr_t desc_dma_addr; 29 struct hclge_desc *desc; 30 struct hclge_dev *dev; 31 u32 head; 32 u32 tail; 33 34 u16 buf_size; 35 u16 desc_num; 36 int next_to_use; 37 int next_to_clean; 38 u8 ring_type; /* cmq ring type */ 39 spinlock_t lock; /* Command queue lock */ 40 }; 41 42 enum hclge_cmd_return_status { 43 HCLGE_CMD_EXEC_SUCCESS = 0, 44 HCLGE_CMD_NO_AUTH = 1, 45 HCLGE_CMD_NOT_SUPPORTED = 2, 46 HCLGE_CMD_QUEUE_FULL = 3, 47 HCLGE_CMD_NEXT_ERR = 4, 48 HCLGE_CMD_UNEXE_ERR = 5, 49 HCLGE_CMD_PARA_ERR = 6, 50 HCLGE_CMD_RESULT_ERR = 7, 51 HCLGE_CMD_TIMEOUT = 8, 52 HCLGE_CMD_HILINK_ERR = 9, 53 HCLGE_CMD_QUEUE_ILLEGAL = 10, 54 HCLGE_CMD_INVALID = 11, 55 }; 56 57 enum hclge_cmd_status { 58 HCLGE_STATUS_SUCCESS = 0, 59 HCLGE_ERR_CSQ_FULL = -1, 60 HCLGE_ERR_CSQ_TIMEOUT = -2, 61 HCLGE_ERR_CSQ_ERROR = -3, 62 }; 63 64 struct hclge_misc_vector { 65 u8 __iomem *addr; 66 int vector_irq; 67 char name[HNAE3_INT_NAME_LEN]; 68 }; 69 70 struct hclge_cmq { 71 struct hclge_cmq_ring csq; 72 struct hclge_cmq_ring crq; 73 u16 tx_timeout; 74 enum hclge_cmd_status last_status; 75 }; 76 77 #define HCLGE_CMD_FLAG_IN BIT(0) 78 #define HCLGE_CMD_FLAG_OUT BIT(1) 79 #define HCLGE_CMD_FLAG_NEXT BIT(2) 80 #define HCLGE_CMD_FLAG_WR BIT(3) 81 #define HCLGE_CMD_FLAG_NO_INTR BIT(4) 82 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5) 83 84 enum hclge_opcode_type { 85 /* Generic commands */ 86 HCLGE_OPC_QUERY_FW_VER = 0x0001, 87 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, 88 HCLGE_OPC_GBL_RST_STATUS = 0x0021, 89 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, 90 HCLGE_OPC_QUERY_PF_RSRC = 0x0023, 91 HCLGE_OPC_QUERY_VF_RSRC = 0x0024, 92 HCLGE_OPC_GET_CFG_PARAM = 0x0025, 93 HCLGE_OPC_PF_RST_DONE = 0x0026, 94 HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027, 95 96 HCLGE_OPC_STATS_64_BIT = 0x0030, 97 HCLGE_OPC_STATS_32_BIT = 0x0031, 98 HCLGE_OPC_STATS_MAC = 0x0032, 99 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033, 100 HCLGE_OPC_STATS_MAC_ALL = 0x0034, 101 102 HCLGE_OPC_QUERY_REG_NUM = 0x0040, 103 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, 104 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, 105 HCLGE_OPC_DFX_BD_NUM = 0x0043, 106 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044, 107 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045, 108 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046, 109 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047, 110 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048, 111 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049, 112 HCLGE_OPC_DFX_NCSI_REG = 0x004A, 113 HCLGE_OPC_DFX_RTC_REG = 0x004B, 114 HCLGE_OPC_DFX_PPP_REG = 0x004C, 115 HCLGE_OPC_DFX_RCB_REG = 0x004D, 116 HCLGE_OPC_DFX_TQP_REG = 0x004E, 117 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F, 118 HCLGE_OPC_DFX_QUERY_CHIP_CAP = 0x0050, 119 120 /* MAC command */ 121 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, 122 HCLGE_OPC_CONFIG_AN_MODE = 0x0304, 123 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, 124 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, 125 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, 126 HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310, 127 HCLGE_OPC_MAC_TNL_INT_EN = 0x0311, 128 HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312, 129 HCLGE_OPC_SERDES_LOOPBACK = 0x0315, 130 HCLGE_OPC_CONFIG_FEC_MODE = 0x031A, 131 132 /* PFC/Pause commands */ 133 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, 134 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, 135 HCLGE_OPC_CFG_MAC_PARA = 0x0703, 136 HCLGE_OPC_CFG_PFC_PARA = 0x0704, 137 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, 138 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, 139 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, 140 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, 141 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, 142 HCLGE_OPC_QOS_MAP = 0x070A, 143 144 /* ETS/scheduler commands */ 145 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, 146 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, 147 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, 148 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, 149 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, 150 HCLGE_OPC_TM_PG_WEIGHT = 0x0809, 151 HCLGE_OPC_TM_QS_WEIGHT = 0x080A, 152 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, 153 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, 154 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, 155 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, 156 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, 157 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, 158 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, 159 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, 160 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, 161 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, 162 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843, 163 HCLGE_OPC_QSET_DFX_STS = 0x0844, 164 HCLGE_OPC_PRI_DFX_STS = 0x0845, 165 HCLGE_OPC_PG_DFX_STS = 0x0846, 166 HCLGE_OPC_PORT_DFX_STS = 0x0847, 167 HCLGE_OPC_SCH_NQ_CNT = 0x0848, 168 HCLGE_OPC_SCH_RQ_CNT = 0x0849, 169 HCLGE_OPC_TM_INTERNAL_STS = 0x0850, 170 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851, 171 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852, 172 173 /* Packet buffer allocate commands */ 174 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, 175 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, 176 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, 177 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, 178 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, 179 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, 180 181 /* TQP management command */ 182 HCLGE_OPC_SET_TQP_MAP = 0x0A01, 183 184 /* TQP commands */ 185 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, 186 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, 187 HCLGE_OPC_QUERY_TX_STATS = 0x0B03, 188 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04, 189 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, 190 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, 191 HCLGE_OPC_QUERY_RX_STATS = 0x0B13, 192 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, 193 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, 194 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 195 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, 196 197 /* PPU commands */ 198 HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A, 199 200 /* TSO command */ 201 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, 202 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10, 203 204 /* RSS commands */ 205 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, 206 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, 207 HCLGE_OPC_RSS_TC_MODE = 0x0D08, 208 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, 209 210 /* Promisuous mode command */ 211 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, 212 213 /* Vlan offload commands */ 214 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, 215 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, 216 217 /* Interrupts commands */ 218 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, 219 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, 220 221 /* MAC commands */ 222 HCLGE_OPC_MAC_VLAN_ADD = 0x1000, 223 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, 224 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, 225 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, 226 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004, 227 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, 228 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, 229 230 /* MAC VLAN commands */ 231 HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033, 232 233 /* VLAN commands */ 234 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, 235 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, 236 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, 237 238 /* Flow Director commands */ 239 HCLGE_OPC_FD_MODE_CTRL = 0x1200, 240 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201, 241 HCLGE_OPC_FD_KEY_CONFIG = 0x1202, 242 HCLGE_OPC_FD_TCAM_OP = 0x1203, 243 HCLGE_OPC_FD_AD_OP = 0x1204, 244 245 /* MDIO command */ 246 HCLGE_OPC_MDIO_CONFIG = 0x1900, 247 248 /* QCN commands */ 249 HCLGE_OPC_QCN_MOD_CFG = 0x1A01, 250 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, 251 HCLGE_OPC_QCN_SHAPPING_CFG = 0x1A03, 252 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, 253 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, 254 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, 255 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, 256 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, 257 258 /* Mailbox command */ 259 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, 260 261 /* Led command */ 262 HCLGE_OPC_LED_STATUS_CFG = 0xB000, 263 264 /* NCL config command */ 265 HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011, 266 267 /* M7 stats command */ 268 HCLGE_OPC_M7_STATS_BD = 0x7012, 269 HCLGE_OPC_M7_STATS_INFO = 0x7013, 270 HCLGE_OPC_M7_COMPAT_CFG = 0x701A, 271 272 /* SFP command */ 273 HCLGE_OPC_GET_SFP_EEPROM = 0x7100, 274 HCLGE_OPC_GET_SFP_EXIST = 0x7101, 275 HCLGE_OPC_GET_SFP_INFO = 0x7104, 276 277 /* Error INT commands */ 278 HCLGE_MAC_COMMON_INT_EN = 0x030E, 279 HCLGE_TM_SCH_ECC_INT_EN = 0x0829, 280 HCLGE_SSU_ECC_INT_CMD = 0x0989, 281 HCLGE_SSU_COMMON_INT_CMD = 0x098C, 282 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40, 283 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41, 284 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42, 285 HCLGE_COMMON_ECC_INT_CFG = 0x1505, 286 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510, 287 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511, 288 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512, 289 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513, 290 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514, 291 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515, 292 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580, 293 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581, 294 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584, 295 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585, 296 HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586, 297 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803, 298 HCLGE_IGU_COMMON_INT_EN = 0x1806, 299 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14, 300 HCLGE_PPP_CMD0_INT_CMD = 0x2100, 301 HCLGE_PPP_CMD1_INT_CMD = 0x2101, 302 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105, 303 HCLGE_NCSI_INT_EN = 0x2401, 304 }; 305 306 #define HCLGE_TQP_REG_OFFSET 0x80000 307 #define HCLGE_TQP_REG_SIZE 0x200 308 309 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 310 #define HCLGE_RCB_INIT_FLAG_EN_B 0 311 #define HCLGE_RCB_INIT_FLAG_FINI_B 8 312 struct hclge_config_rcb_init_cmd { 313 __le16 rcb_init_flag; 314 u8 rsv[22]; 315 }; 316 317 struct hclge_tqp_map_cmd { 318 __le16 tqp_id; /* Absolute tqp id for in this pf */ 319 u8 tqp_vf; /* VF id */ 320 #define HCLGE_TQP_MAP_TYPE_PF 0 321 #define HCLGE_TQP_MAP_TYPE_VF 1 322 #define HCLGE_TQP_MAP_TYPE_B 0 323 #define HCLGE_TQP_MAP_EN_B 1 324 u8 tqp_flag; /* Indicate it's pf or vf tqp */ 325 __le16 tqp_vid; /* Virtual id in this pf/vf */ 326 u8 rsv[18]; 327 }; 328 329 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 330 331 enum hclge_int_type { 332 HCLGE_INT_TX, 333 HCLGE_INT_RX, 334 HCLGE_INT_EVENT, 335 }; 336 337 struct hclge_ctrl_vector_chain_cmd { 338 u8 int_vector_id; 339 u8 int_cause_num; 340 #define HCLGE_INT_TYPE_S 0 341 #define HCLGE_INT_TYPE_M GENMASK(1, 0) 342 #define HCLGE_TQP_ID_S 2 343 #define HCLGE_TQP_ID_M GENMASK(12, 2) 344 #define HCLGE_INT_GL_IDX_S 13 345 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) 346 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; 347 u8 vfid; 348 u8 rsv; 349 }; 350 351 #define HCLGE_MAX_TC_NUM 8 352 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ 353 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ 354 struct hclge_tx_buff_alloc_cmd { 355 __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM]; 356 u8 tx_buff_rsv[8]; 357 }; 358 359 struct hclge_rx_priv_buff_cmd { 360 __le16 buf_num[HCLGE_MAX_TC_NUM]; 361 __le16 shared_buf; 362 u8 rsv[6]; 363 }; 364 365 struct hclge_query_version_cmd { 366 __le32 firmware; 367 __le32 firmware_rsv[5]; 368 }; 369 370 #define HCLGE_RX_PRIV_EN_B 15 371 #define HCLGE_TC_NUM_ONE_DESC 4 372 struct hclge_priv_wl { 373 __le16 high; 374 __le16 low; 375 }; 376 377 struct hclge_rx_priv_wl_buf { 378 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; 379 }; 380 381 struct hclge_rx_com_thrd { 382 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; 383 }; 384 385 struct hclge_rx_com_wl { 386 struct hclge_priv_wl com_wl; 387 }; 388 389 struct hclge_waterline { 390 u32 low; 391 u32 high; 392 }; 393 394 struct hclge_tc_thrd { 395 u32 low; 396 u32 high; 397 }; 398 399 struct hclge_priv_buf { 400 struct hclge_waterline wl; /* Waterline for low and high*/ 401 u32 buf_size; /* TC private buffer size */ 402 u32 tx_buf_size; 403 u32 enable; /* Enable TC private buffer or not */ 404 }; 405 406 struct hclge_shared_buf { 407 struct hclge_waterline self; 408 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; 409 u32 buf_size; 410 }; 411 412 struct hclge_pkt_buf_alloc { 413 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; 414 struct hclge_shared_buf s_buf; 415 }; 416 417 #define HCLGE_RX_COM_WL_EN_B 15 418 struct hclge_rx_com_wl_buf_cmd { 419 __le16 high_wl; 420 __le16 low_wl; 421 u8 rsv[20]; 422 }; 423 424 #define HCLGE_RX_PKT_EN_B 15 425 struct hclge_rx_pkt_buf_cmd { 426 __le16 high_pkt; 427 __le16 low_pkt; 428 u8 rsv[20]; 429 }; 430 431 #define HCLGE_PF_STATE_DONE_B 0 432 #define HCLGE_PF_STATE_MAIN_B 1 433 #define HCLGE_PF_STATE_BOND_B 2 434 #define HCLGE_PF_STATE_MAC_N_B 6 435 #define HCLGE_PF_MAC_NUM_MASK 0x3 436 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) 437 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) 438 #define HCLGE_VF_RST_STATUS_CMD 4 439 440 struct hclge_func_status_cmd { 441 __le32 vf_rst_state[HCLGE_VF_RST_STATUS_CMD]; 442 u8 pf_state; 443 u8 mac_id; 444 u8 rsv1; 445 u8 pf_cnt_in_mac; 446 u8 pf_num; 447 u8 vf_num; 448 u8 rsv[2]; 449 }; 450 451 struct hclge_pf_res_cmd { 452 __le16 tqp_num; 453 __le16 buf_size; 454 __le16 msixcap_localid_ba_nic; 455 __le16 msixcap_localid_ba_rocee; 456 #define HCLGE_MSIX_OFT_ROCEE_S 0 457 #define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0) 458 #define HCLGE_PF_VEC_NUM_S 0 459 #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0) 460 __le16 pf_intr_vector_number; 461 __le16 pf_own_fun_number; 462 __le16 tx_buf_size; 463 __le16 dv_buf_size; 464 __le32 rsv[2]; 465 }; 466 467 #define HCLGE_CFG_OFFSET_S 0 468 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) 469 #define HCLGE_CFG_RD_LEN_S 24 470 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) 471 #define HCLGE_CFG_RD_LEN_BYTES 16 472 #define HCLGE_CFG_RD_LEN_UNIT 4 473 474 #define HCLGE_CFG_VMDQ_S 0 475 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0) 476 #define HCLGE_CFG_TC_NUM_S 8 477 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) 478 #define HCLGE_CFG_TQP_DESC_N_S 16 479 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) 480 #define HCLGE_CFG_PHY_ADDR_S 0 481 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) 482 #define HCLGE_CFG_MEDIA_TP_S 8 483 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) 484 #define HCLGE_CFG_RX_BUF_LEN_S 16 485 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) 486 #define HCLGE_CFG_MAC_ADDR_H_S 0 487 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) 488 #define HCLGE_CFG_DEFAULT_SPEED_S 16 489 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) 490 #define HCLGE_CFG_RSS_SIZE_S 24 491 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) 492 #define HCLGE_CFG_SPEED_ABILITY_S 0 493 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) 494 #define HCLGE_CFG_UMV_TBL_SPACE_S 16 495 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) 496 497 #define HCLGE_CFG_CMD_CNT 4 498 499 struct hclge_cfg_param_cmd { 500 __le32 offset; 501 __le32 rsv; 502 __le32 param[HCLGE_CFG_CMD_CNT]; 503 }; 504 505 #define HCLGE_MAC_MODE 0x0 506 #define HCLGE_DESC_NUM 0x40 507 508 #define HCLGE_ALLOC_VALID_B 0 509 struct hclge_vf_num_cmd { 510 u8 alloc_valid; 511 u8 rsv[23]; 512 }; 513 514 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 515 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 516 #define HCLGE_RSS_HASH_KEY_NUM 16 517 struct hclge_rss_config_cmd { 518 u8 hash_config; 519 u8 rsv[7]; 520 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; 521 }; 522 523 struct hclge_rss_input_tuple_cmd { 524 u8 ipv4_tcp_en; 525 u8 ipv4_udp_en; 526 u8 ipv4_sctp_en; 527 u8 ipv4_fragment_en; 528 u8 ipv6_tcp_en; 529 u8 ipv6_udp_en; 530 u8 ipv6_sctp_en; 531 u8 ipv6_fragment_en; 532 u8 rsv[16]; 533 }; 534 535 #define HCLGE_RSS_CFG_TBL_SIZE 16 536 537 struct hclge_rss_indirection_table_cmd { 538 __le16 start_table_index; 539 __le16 rss_set_bitmap; 540 u8 rsv[4]; 541 u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE]; 542 }; 543 544 #define HCLGE_RSS_TC_OFFSET_S 0 545 #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0) 546 #define HCLGE_RSS_TC_SIZE_S 12 547 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) 548 #define HCLGE_RSS_TC_VALID_B 15 549 struct hclge_rss_tc_mode_cmd { 550 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; 551 u8 rsv[8]; 552 }; 553 554 #define HCLGE_LINK_STATUS_UP_B 0 555 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B) 556 struct hclge_link_status_cmd { 557 u8 status; 558 u8 rsv[23]; 559 }; 560 561 struct hclge_promisc_param { 562 u8 vf_id; 563 u8 enable; 564 }; 565 566 #define HCLGE_PROMISC_TX_EN_B BIT(4) 567 #define HCLGE_PROMISC_RX_EN_B BIT(5) 568 #define HCLGE_PROMISC_EN_B 1 569 #define HCLGE_PROMISC_EN_ALL 0x7 570 #define HCLGE_PROMISC_EN_UC 0x1 571 #define HCLGE_PROMISC_EN_MC 0x2 572 #define HCLGE_PROMISC_EN_BC 0x4 573 struct hclge_promisc_cfg_cmd { 574 u8 flag; 575 u8 vf_id; 576 __le16 rsv0; 577 u8 rsv1[20]; 578 }; 579 580 enum hclge_promisc_type { 581 HCLGE_UNICAST = 1, 582 HCLGE_MULTICAST = 2, 583 HCLGE_BROADCAST = 3, 584 }; 585 586 #define HCLGE_MAC_TX_EN_B 6 587 #define HCLGE_MAC_RX_EN_B 7 588 #define HCLGE_MAC_PAD_TX_B 11 589 #define HCLGE_MAC_PAD_RX_B 12 590 #define HCLGE_MAC_1588_TX_B 13 591 #define HCLGE_MAC_1588_RX_B 14 592 #define HCLGE_MAC_APP_LP_B 15 593 #define HCLGE_MAC_LINE_LP_B 16 594 #define HCLGE_MAC_FCS_TX_B 17 595 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 596 #define HCLGE_MAC_RX_FCS_STRIP_B 19 597 #define HCLGE_MAC_RX_FCS_B 20 598 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 599 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 600 601 struct hclge_config_mac_mode_cmd { 602 __le32 txrx_pad_fcs_loop_en; 603 u8 rsv[20]; 604 }; 605 606 struct hclge_pf_rst_sync_cmd { 607 #define HCLGE_PF_RST_ALL_VF_RDY_B 0 608 u8 all_vf_ready; 609 u8 rsv[23]; 610 }; 611 612 #define HCLGE_CFG_SPEED_S 0 613 #define HCLGE_CFG_SPEED_M GENMASK(5, 0) 614 615 #define HCLGE_CFG_DUPLEX_B 7 616 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) 617 618 struct hclge_config_mac_speed_dup_cmd { 619 u8 speed_dup; 620 621 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 622 u8 mac_change_fec_en; 623 u8 rsv[22]; 624 }; 625 626 #define HCLGE_RING_ID_MASK GENMASK(9, 0) 627 #define HCLGE_TQP_ENABLE_B 0 628 629 #define HCLGE_MAC_CFG_AN_EN_B 0 630 #define HCLGE_MAC_CFG_AN_INT_EN_B 1 631 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 632 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 633 #define HCLGE_MAC_CFG_AN_RST_B 4 634 635 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) 636 637 struct hclge_config_auto_neg_cmd { 638 __le32 cfg_an_cmd_flag; 639 u8 rsv[20]; 640 }; 641 642 struct hclge_sfp_info_cmd { 643 __le32 speed; 644 u8 query_type; /* 0: sfp speed, 1: active speed */ 645 u8 active_fec; 646 u8 autoneg; /* autoneg state */ 647 u8 autoneg_ability; /* whether support autoneg */ 648 __le32 speed_ability; /* speed ability for current media */ 649 __le32 module_type; 650 u8 rsv[8]; 651 }; 652 653 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0 654 #define HCLGE_MAC_CFG_FEC_MODE_S 1 655 #define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1) 656 #define HCLGE_MAC_CFG_FEC_SET_DEF_B 0 657 #define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1 658 659 #define HCLGE_MAC_FEC_OFF 0 660 #define HCLGE_MAC_FEC_BASER 1 661 #define HCLGE_MAC_FEC_RS 2 662 struct hclge_config_fec_cmd { 663 u8 fec_mode; 664 u8 default_config; 665 u8 rsv[22]; 666 }; 667 668 #define HCLGE_MAC_UPLINK_PORT 0x100 669 670 struct hclge_config_max_frm_size_cmd { 671 __le16 max_frm_size; 672 u8 min_frm_size; 673 u8 rsv[21]; 674 }; 675 676 enum hclge_mac_vlan_tbl_opcode { 677 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ 678 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ 679 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ 680 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ 681 }; 682 683 enum hclge_mac_vlan_add_resp_code { 684 HCLGE_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */ 685 HCLGE_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */ 686 }; 687 688 #define HCLGE_MAC_VLAN_BIT0_EN_B 0 689 #define HCLGE_MAC_VLAN_BIT1_EN_B 1 690 #define HCLGE_MAC_EPORT_SW_EN_B 12 691 #define HCLGE_MAC_EPORT_TYPE_B 11 692 #define HCLGE_MAC_EPORT_VFID_S 3 693 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) 694 #define HCLGE_MAC_EPORT_PFID_S 0 695 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) 696 struct hclge_mac_vlan_tbl_entry_cmd { 697 u8 flags; 698 u8 resp_code; 699 __le16 vlan_tag; 700 __le32 mac_addr_hi32; 701 __le16 mac_addr_lo16; 702 __le16 rsv1; 703 u8 entry_type; 704 u8 mc_mac_en; 705 __le16 egress_port; 706 __le16 egress_queue; 707 u8 rsv2[6]; 708 }; 709 710 #define HCLGE_UMV_SPC_ALC_B 0 711 struct hclge_umv_spc_alc_cmd { 712 u8 allocate; 713 u8 rsv1[3]; 714 __le32 space_size; 715 u8 rsv2[16]; 716 }; 717 718 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) 719 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) 720 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) 721 722 struct hclge_mac_mgr_tbl_entry_cmd { 723 u8 flags; 724 u8 resp_code; 725 __le16 vlan_tag; 726 u8 mac_addr[ETH_ALEN]; 727 __le16 rsv1; 728 __le16 ethter_type; 729 __le16 egress_port; 730 __le16 egress_queue; 731 u8 sw_port_id_aware; 732 u8 rsv2; 733 u8 i_port_bitmap; 734 u8 i_port_direction; 735 u8 rsv3[2]; 736 }; 737 738 struct hclge_vlan_filter_ctrl_cmd { 739 u8 vlan_type; 740 u8 vlan_fe; 741 u8 rsv1[2]; 742 u8 vf_id; 743 u8 rsv2[19]; 744 }; 745 746 #define HCLGE_VLAN_ID_OFFSET_STEP 160 747 #define HCLGE_VLAN_BYTE_SIZE 8 748 #define HCLGE_VLAN_OFFSET_BITMAP \ 749 (HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE) 750 751 struct hclge_vlan_filter_pf_cfg_cmd { 752 u8 vlan_offset; 753 u8 vlan_cfg; 754 u8 rsv[2]; 755 u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP]; 756 }; 757 758 #define HCLGE_MAX_VF_BYTES 16 759 760 struct hclge_vlan_filter_vf_cfg_cmd { 761 __le16 vlan_id; 762 u8 resp_code; 763 u8 rsv; 764 u8 vlan_cfg; 765 u8 rsv1[3]; 766 u8 vf_bitmap[HCLGE_MAX_VF_BYTES]; 767 }; 768 769 #define HCLGE_SWITCH_ANTI_SPOOF_B 0U 770 #define HCLGE_SWITCH_ALW_LPBK_B 1U 771 #define HCLGE_SWITCH_ALW_LCL_LPBK_B 2U 772 #define HCLGE_SWITCH_ALW_DST_OVRD_B 3U 773 #define HCLGE_SWITCH_NO_MASK 0x0 774 #define HCLGE_SWITCH_ANTI_SPOOF_MASK 0xFE 775 #define HCLGE_SWITCH_ALW_LPBK_MASK 0xFD 776 #define HCLGE_SWITCH_ALW_LCL_LPBK_MASK 0xFB 777 #define HCLGE_SWITCH_LW_DST_OVRD_MASK 0xF7 778 779 struct hclge_mac_vlan_switch_cmd { 780 u8 roce_sel; 781 u8 rsv1[3]; 782 __le32 func_id; 783 u8 switch_param; 784 u8 rsv2[3]; 785 u8 param_mask; 786 u8 rsv3[11]; 787 }; 788 789 enum hclge_mac_vlan_cfg_sel { 790 HCLGE_MAC_VLAN_NIC_SEL = 0, 791 HCLGE_MAC_VLAN_ROCE_SEL, 792 }; 793 794 #define HCLGE_ACCEPT_TAG1_B 0 795 #define HCLGE_ACCEPT_UNTAG1_B 1 796 #define HCLGE_PORT_INS_TAG1_EN_B 2 797 #define HCLGE_PORT_INS_TAG2_EN_B 3 798 #define HCLGE_CFG_NIC_ROCE_SEL_B 4 799 #define HCLGE_ACCEPT_TAG2_B 5 800 #define HCLGE_ACCEPT_UNTAG2_B 6 801 #define HCLGE_VF_NUM_PER_BYTE 8 802 803 struct hclge_vport_vtag_tx_cfg_cmd { 804 u8 vport_vlan_cfg; 805 u8 vf_offset; 806 u8 rsv1[2]; 807 __le16 def_vlan_tag1; 808 __le16 def_vlan_tag2; 809 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE]; 810 u8 rsv2[8]; 811 }; 812 813 #define HCLGE_REM_TAG1_EN_B 0 814 #define HCLGE_REM_TAG2_EN_B 1 815 #define HCLGE_SHOW_TAG1_EN_B 2 816 #define HCLGE_SHOW_TAG2_EN_B 3 817 struct hclge_vport_vtag_rx_cfg_cmd { 818 u8 vport_vlan_cfg; 819 u8 vf_offset; 820 u8 rsv1[6]; 821 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE]; 822 u8 rsv2[8]; 823 }; 824 825 struct hclge_tx_vlan_type_cfg_cmd { 826 __le16 ot_vlan_type; 827 __le16 in_vlan_type; 828 u8 rsv[20]; 829 }; 830 831 struct hclge_rx_vlan_type_cfg_cmd { 832 __le16 ot_fst_vlan_type; 833 __le16 ot_sec_vlan_type; 834 __le16 in_fst_vlan_type; 835 __le16 in_sec_vlan_type; 836 u8 rsv[16]; 837 }; 838 839 struct hclge_cfg_com_tqp_queue_cmd { 840 __le16 tqp_id; 841 __le16 stream_id; 842 u8 enable; 843 u8 rsv[19]; 844 }; 845 846 struct hclge_cfg_tx_queue_pointer_cmd { 847 __le16 tqp_id; 848 __le16 tx_tail; 849 __le16 tx_head; 850 __le16 fbd_num; 851 __le16 ring_offset; 852 u8 rsv[14]; 853 }; 854 855 #pragma pack(1) 856 struct hclge_mac_ethertype_idx_rd_cmd { 857 u8 flags; 858 u8 resp_code; 859 __le16 vlan_tag; 860 u8 mac_addr[ETH_ALEN]; 861 __le16 index; 862 __le16 ethter_type; 863 __le16 egress_port; 864 __le16 egress_queue; 865 __le16 rev0; 866 u8 i_port_bitmap; 867 u8 i_port_direction; 868 u8 rev1[2]; 869 }; 870 871 #pragma pack() 872 873 #define HCLGE_TSO_MSS_MIN_S 0 874 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) 875 876 #define HCLGE_TSO_MSS_MAX_S 16 877 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) 878 879 struct hclge_cfg_tso_status_cmd { 880 __le16 tso_mss_min; 881 __le16 tso_mss_max; 882 u8 rsv[20]; 883 }; 884 885 #define HCLGE_GRO_EN_B 0 886 struct hclge_cfg_gro_status_cmd { 887 u8 gro_en; 888 u8 rsv[23]; 889 }; 890 891 #define HCLGE_TSO_MSS_MIN 256 892 #define HCLGE_TSO_MSS_MAX 9668 893 894 #define HCLGE_TQP_RESET_B 0 895 struct hclge_reset_tqp_queue_cmd { 896 __le16 tqp_id; 897 u8 reset_req; 898 u8 ready_to_reset; 899 u8 rsv[20]; 900 }; 901 902 #define HCLGE_CFG_RESET_MAC_B 3 903 #define HCLGE_CFG_RESET_FUNC_B 7 904 struct hclge_reset_cmd { 905 u8 mac_func_reset; 906 u8 fun_reset_vfid; 907 u8 rsv[22]; 908 }; 909 910 #define HCLGE_PF_RESET_DONE_BIT BIT(0) 911 912 struct hclge_pf_rst_done_cmd { 913 u8 pf_rst_done; 914 u8 rsv[23]; 915 }; 916 917 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0) 918 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2) 919 #define HCLGE_CMD_SERDES_DONE_B BIT(0) 920 #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1) 921 struct hclge_serdes_lb_cmd { 922 u8 mask; 923 u8 enable; 924 u8 result; 925 u8 rsv[21]; 926 }; 927 928 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ 929 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ 930 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ 931 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ 932 #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */ 933 934 #define HCLGE_TYPE_CRQ 0 935 #define HCLGE_TYPE_CSQ 1 936 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 937 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 938 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 939 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 940 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 941 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 942 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c 943 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 944 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 945 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 946 947 /* this bit indicates that the driver is ready for hardware reset */ 948 #define HCLGE_NIC_SW_RST_RDY_B 16 949 #define HCLGE_NIC_SW_RST_RDY BIT(HCLGE_NIC_SW_RST_RDY_B) 950 951 #define HCLGE_NIC_CMQ_DESC_NUM 1024 952 #define HCLGE_NIC_CMQ_DESC_NUM_S 3 953 954 #define HCLGE_LED_LOCATE_STATE_S 0 955 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) 956 957 struct hclge_set_led_state_cmd { 958 u8 rsv1[3]; 959 u8 locate_led_config; 960 u8 rsv2[20]; 961 }; 962 963 struct hclge_get_fd_mode_cmd { 964 u8 mode; 965 u8 enable; 966 u8 rsv[22]; 967 }; 968 969 struct hclge_get_fd_allocation_cmd { 970 __le32 stage1_entry_num; 971 __le32 stage2_entry_num; 972 __le16 stage1_counter_num; 973 __le16 stage2_counter_num; 974 u8 rsv[12]; 975 }; 976 977 struct hclge_set_fd_key_config_cmd { 978 u8 stage; 979 u8 key_select; 980 u8 inner_sipv6_word_en; 981 u8 inner_dipv6_word_en; 982 u8 outer_sipv6_word_en; 983 u8 outer_dipv6_word_en; 984 u8 rsv1[2]; 985 __le32 tuple_mask; 986 __le32 meta_data_mask; 987 u8 rsv2[8]; 988 }; 989 990 #define HCLGE_FD_EPORT_SW_EN_B 0 991 struct hclge_fd_tcam_config_1_cmd { 992 u8 stage; 993 u8 xy_sel; 994 u8 port_info; 995 u8 rsv1[1]; 996 __le32 index; 997 u8 entry_vld; 998 u8 rsv2[7]; 999 u8 tcam_data[8]; 1000 }; 1001 1002 struct hclge_fd_tcam_config_2_cmd { 1003 u8 tcam_data[24]; 1004 }; 1005 1006 struct hclge_fd_tcam_config_3_cmd { 1007 u8 tcam_data[20]; 1008 u8 rsv[4]; 1009 }; 1010 1011 #define HCLGE_FD_AD_DROP_B 0 1012 #define HCLGE_FD_AD_DIRECT_QID_B 1 1013 #define HCLGE_FD_AD_QID_S 2 1014 #define HCLGE_FD_AD_QID_M GENMASK(12, 2) 1015 #define HCLGE_FD_AD_USE_COUNTER_B 12 1016 #define HCLGE_FD_AD_COUNTER_NUM_S 13 1017 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13) 1018 #define HCLGE_FD_AD_NXT_STEP_B 20 1019 #define HCLGE_FD_AD_NXT_KEY_S 21 1020 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21) 1021 #define HCLGE_FD_AD_WR_RULE_ID_B 0 1022 #define HCLGE_FD_AD_RULE_ID_S 1 1023 #define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1) 1024 1025 struct hclge_fd_ad_config_cmd { 1026 u8 stage; 1027 u8 rsv1[3]; 1028 __le32 index; 1029 __le64 ad_data; 1030 u8 rsv2[8]; 1031 }; 1032 1033 struct hclge_get_m7_bd_cmd { 1034 __le32 bd_num; 1035 u8 rsv[20]; 1036 }; 1037 1038 struct hclge_query_ppu_pf_other_int_dfx_cmd { 1039 __le16 over_8bd_no_fe_qid; 1040 __le16 over_8bd_no_fe_vf_id; 1041 __le16 tso_mss_cmp_min_err_qid; 1042 __le16 tso_mss_cmp_min_err_vf_id; 1043 __le16 tso_mss_cmp_max_err_qid; 1044 __le16 tso_mss_cmp_max_err_vf_id; 1045 __le16 tx_rd_fbd_poison_qid; 1046 __le16 tx_rd_fbd_poison_vf_id; 1047 __le16 rx_rd_fbd_poison_qid; 1048 __le16 rx_rd_fbd_poison_vf_id; 1049 u8 rsv[4]; 1050 }; 1051 1052 #define HCLGE_LINK_EVENT_REPORT_EN_B 0 1053 #define HCLGE_NCSI_ERROR_REPORT_EN_B 1 1054 struct hclge_firmware_compat_cmd { 1055 __le32 compat; 1056 u8 rsv[20]; 1057 }; 1058 1059 #define HCLGE_SFP_INFO_CMD_NUM 6 1060 #define HCLGE_SFP_INFO_BD0_LEN 20 1061 #define HCLGE_SFP_INFO_BDX_LEN 24 1062 #define HCLGE_SFP_INFO_MAX_LEN \ 1063 (HCLGE_SFP_INFO_BD0_LEN + \ 1064 (HCLGE_SFP_INFO_CMD_NUM - 1) * HCLGE_SFP_INFO_BDX_LEN) 1065 1066 struct hclge_sfp_info_bd0_cmd { 1067 __le16 offset; 1068 __le16 read_len; 1069 u8 data[HCLGE_SFP_INFO_BD0_LEN]; 1070 }; 1071 1072 int hclge_cmd_init(struct hclge_dev *hdev); 1073 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) 1074 { 1075 writel(value, base + reg); 1076 } 1077 1078 #define hclge_write_dev(a, reg, value) \ 1079 hclge_write_reg((a)->io_base, (reg), (value)) 1080 #define hclge_read_dev(a, reg) \ 1081 hclge_read_reg((a)->io_base, (reg)) 1082 1083 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) 1084 { 1085 u8 __iomem *reg_addr = READ_ONCE(base); 1086 1087 return readl(reg_addr + reg); 1088 } 1089 1090 #define HCLGE_SEND_SYNC(flag) \ 1091 ((flag) & HCLGE_CMD_FLAG_NO_INTR) 1092 1093 struct hclge_hw; 1094 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); 1095 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, 1096 enum hclge_opcode_type opcode, bool is_read); 1097 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); 1098 1099 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, 1100 struct hclge_desc *desc); 1101 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, 1102 struct hclge_desc *desc); 1103 1104 void hclge_cmd_uninit(struct hclge_dev *hdev); 1105 int hclge_cmd_queue_init(struct hclge_dev *hdev); 1106 #endif 1107