1 /* 2 * Copyright (c) 2016~2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #ifndef __HCLGE_CMD_H 11 #define __HCLGE_CMD_H 12 #include <linux/types.h> 13 #include <linux/io.h> 14 15 #define HCLGE_CMDQ_TX_TIMEOUT 1000 16 17 struct hclge_dev; 18 struct hclge_desc { 19 __le16 opcode; 20 21 #define HCLGE_CMDQ_RX_INVLD_B 0 22 #define HCLGE_CMDQ_RX_OUTVLD_B 1 23 24 __le16 flag; 25 __le16 retval; 26 __le16 rsv; 27 __le32 data[6]; 28 }; 29 30 struct hclge_desc_cb { 31 dma_addr_t dma; 32 void *va; 33 u32 length; 34 }; 35 36 struct hclge_cmq_ring { 37 dma_addr_t desc_dma_addr; 38 struct hclge_desc *desc; 39 struct hclge_desc_cb *desc_cb; 40 struct hclge_dev *dev; 41 u32 head; 42 u32 tail; 43 44 u16 buf_size; 45 u16 desc_num; 46 int next_to_use; 47 int next_to_clean; 48 u8 flag; 49 spinlock_t lock; /* Command queue lock */ 50 }; 51 52 enum hclge_cmd_return_status { 53 HCLGE_CMD_EXEC_SUCCESS = 0, 54 HCLGE_CMD_NO_AUTH = 1, 55 HCLGE_CMD_NOT_EXEC = 2, 56 HCLGE_CMD_QUEUE_FULL = 3, 57 }; 58 59 enum hclge_cmd_status { 60 HCLGE_STATUS_SUCCESS = 0, 61 HCLGE_ERR_CSQ_FULL = -1, 62 HCLGE_ERR_CSQ_TIMEOUT = -2, 63 HCLGE_ERR_CSQ_ERROR = -3, 64 }; 65 66 struct hclge_cmq { 67 struct hclge_cmq_ring csq; 68 struct hclge_cmq_ring crq; 69 u16 tx_timeout; /* Tx timeout */ 70 enum hclge_cmd_status last_status; 71 }; 72 73 #define HCLGE_CMD_FLAG_IN_VALID_SHIFT 0 74 #define HCLGE_CMD_FLAG_OUT_VALID_SHIFT 1 75 #define HCLGE_CMD_FLAG_NEXT_SHIFT 2 76 #define HCLGE_CMD_FLAG_WR_OR_RD_SHIFT 3 77 #define HCLGE_CMD_FLAG_NO_INTR_SHIFT 4 78 #define HCLGE_CMD_FLAG_ERR_INTR_SHIFT 5 79 80 #define HCLGE_CMD_FLAG_IN BIT(HCLGE_CMD_FLAG_IN_VALID_SHIFT) 81 #define HCLGE_CMD_FLAG_OUT BIT(HCLGE_CMD_FLAG_OUT_VALID_SHIFT) 82 #define HCLGE_CMD_FLAG_NEXT BIT(HCLGE_CMD_FLAG_NEXT_SHIFT) 83 #define HCLGE_CMD_FLAG_WR BIT(HCLGE_CMD_FLAG_WR_OR_RD_SHIFT) 84 #define HCLGE_CMD_FLAG_NO_INTR BIT(HCLGE_CMD_FLAG_NO_INTR_SHIFT) 85 #define HCLGE_CMD_FLAG_ERR_INTR BIT(HCLGE_CMD_FLAG_ERR_INTR_SHIFT) 86 87 enum hclge_opcode_type { 88 /* Generic command */ 89 HCLGE_OPC_QUERY_FW_VER = 0x0001, 90 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, 91 HCLGE_OPC_GBL_RST_STATUS = 0x0021, 92 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, 93 HCLGE_OPC_QUERY_PF_RSRC = 0x0023, 94 HCLGE_OPC_QUERY_VF_RSRC = 0x0024, 95 HCLGE_OPC_GET_CFG_PARAM = 0x0025, 96 97 HCLGE_OPC_STATS_64_BIT = 0x0030, 98 HCLGE_OPC_STATS_32_BIT = 0x0031, 99 HCLGE_OPC_STATS_MAC = 0x0032, 100 /* Device management command */ 101 102 /* MAC commond */ 103 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, 104 HCLGE_OPC_CONFIG_AN_MODE = 0x0304, 105 HCLGE_OPC_QUERY_AN_RESULT = 0x0306, 106 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, 107 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, 108 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, 109 /* MACSEC command */ 110 111 /* PFC/Pause CMD*/ 112 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, 113 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, 114 HCLGE_OPC_CFG_MAC_PARA = 0x0703, 115 HCLGE_OPC_CFG_PFC_PARA = 0x0704, 116 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, 117 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, 118 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, 119 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, 120 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, 121 HCLGE_OPC_QOS_MAP = 0x070A, 122 123 /* ETS/scheduler commands */ 124 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, 125 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, 126 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, 127 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, 128 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, 129 HCLGE_OPC_TM_PG_WEIGHT = 0x0809, 130 HCLGE_OPC_TM_QS_WEIGHT = 0x080A, 131 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, 132 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, 133 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, 134 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, 135 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, 136 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, 137 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, 138 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, 139 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, 140 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, 141 142 /* Packet buffer allocate command */ 143 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, 144 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, 145 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, 146 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, 147 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, 148 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, 149 150 /* PTP command */ 151 /* TQP management command */ 152 HCLGE_OPC_SET_TQP_MAP = 0x0A01, 153 154 /* TQP command */ 155 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, 156 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, 157 HCLGE_OPC_QUERY_TX_STATUS = 0x0B03, 158 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, 159 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, 160 HCLGE_OPC_QUERY_RX_STATUS = 0x0B13, 161 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, 162 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, 163 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 164 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, 165 166 /* TSO cmd */ 167 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, 168 169 /* RSS cmd */ 170 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, 171 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, 172 HCLGE_OPC_RSS_TC_MODE = 0x0D08, 173 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, 174 175 /* Promisuous mode command */ 176 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, 177 178 /* Interrupts cmd */ 179 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, 180 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, 181 182 /* MAC command */ 183 HCLGE_OPC_MAC_VLAN_ADD = 0x1000, 184 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, 185 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, 186 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, 187 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, 188 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, 189 190 /* Multicast linear table cmd */ 191 HCLGE_OPC_MTA_MAC_MODE_CFG = 0x1020, 192 HCLGE_OPC_MTA_MAC_FUNC_CFG = 0x1021, 193 HCLGE_OPC_MTA_TBL_ITEM_CFG = 0x1022, 194 HCLGE_OPC_MTA_TBL_ITEM_QUERY = 0x1023, 195 196 /* VLAN command */ 197 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, 198 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, 199 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, 200 201 /* MDIO command */ 202 HCLGE_OPC_MDIO_CONFIG = 0x1900, 203 204 /* QCN command */ 205 HCLGE_OPC_QCN_MOD_CFG = 0x1A01, 206 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, 207 HCLGE_OPC_QCN_SHAPPING_IR_CFG = 0x1A03, 208 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, 209 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, 210 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, 211 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, 212 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, 213 214 /* Mailbox cmd */ 215 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, 216 }; 217 218 #define HCLGE_TQP_REG_OFFSET 0x80000 219 #define HCLGE_TQP_REG_SIZE 0x200 220 221 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 222 #define HCLGE_RCB_INIT_FLAG_EN_B 0 223 #define HCLGE_RCB_INIT_FLAG_FINI_B 8 224 struct hclge_config_rcb_init { 225 __le16 rcb_init_flag; 226 u8 rsv[22]; 227 }; 228 229 struct hclge_tqp_map { 230 __le16 tqp_id; /* Absolute tqp id for in this pf */ 231 u8 tqp_vf; /* VF id */ 232 #define HCLGE_TQP_MAP_TYPE_PF 0 233 #define HCLGE_TQP_MAP_TYPE_VF 1 234 #define HCLGE_TQP_MAP_TYPE_B 0 235 #define HCLGE_TQP_MAP_EN_B 1 236 u8 tqp_flag; /* Indicate it's pf or vf tqp */ 237 __le16 tqp_vid; /* Virtual id in this pf/vf */ 238 u8 rsv[18]; 239 }; 240 241 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 242 243 enum hclge_int_type { 244 HCLGE_INT_TX, 245 HCLGE_INT_RX, 246 HCLGE_INT_EVENT, 247 }; 248 249 struct hclge_ctrl_vector_chain { 250 u8 int_vector_id; 251 u8 int_cause_num; 252 #define HCLGE_INT_TYPE_S 0 253 #define HCLGE_INT_TYPE_M 0x3 254 #define HCLGE_TQP_ID_S 2 255 #define HCLGE_TQP_ID_M (0x7ff << HCLGE_TQP_ID_S) 256 #define HCLGE_INT_GL_IDX_S 13 257 #define HCLGE_INT_GL_IDX_M (0x3 << HCLGE_INT_GL_IDX_S) 258 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; 259 u8 vfid; 260 u8 rsv; 261 }; 262 263 #define HCLGE_TC_NUM 8 264 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ 265 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ 266 struct hclge_tx_buff_alloc { 267 __le16 tx_pkt_buff[HCLGE_TC_NUM]; 268 u8 tx_buff_rsv[8]; 269 }; 270 271 struct hclge_rx_priv_buff { 272 __le16 buf_num[HCLGE_TC_NUM]; 273 __le16 shared_buf; 274 u8 rsv[6]; 275 }; 276 277 struct hclge_query_version { 278 __le32 firmware; 279 __le32 firmware_rsv[5]; 280 }; 281 282 #define HCLGE_RX_PRIV_EN_B 15 283 #define HCLGE_TC_NUM_ONE_DESC 4 284 struct hclge_priv_wl { 285 __le16 high; 286 __le16 low; 287 }; 288 289 struct hclge_rx_priv_wl_buf { 290 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; 291 }; 292 293 struct hclge_rx_com_thrd { 294 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; 295 }; 296 297 struct hclge_rx_com_wl { 298 struct hclge_priv_wl com_wl; 299 }; 300 301 struct hclge_waterline { 302 u32 low; 303 u32 high; 304 }; 305 306 struct hclge_tc_thrd { 307 u32 low; 308 u32 high; 309 }; 310 311 struct hclge_priv_buf { 312 struct hclge_waterline wl; /* Waterline for low and high*/ 313 u32 buf_size; /* TC private buffer size */ 314 u32 enable; /* Enable TC private buffer or not */ 315 }; 316 317 #define HCLGE_MAX_TC_NUM 8 318 struct hclge_shared_buf { 319 struct hclge_waterline self; 320 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; 321 u32 buf_size; 322 }; 323 324 #define HCLGE_RX_COM_WL_EN_B 15 325 struct hclge_rx_com_wl_buf { 326 __le16 high_wl; 327 __le16 low_wl; 328 u8 rsv[20]; 329 }; 330 331 #define HCLGE_RX_PKT_EN_B 15 332 struct hclge_rx_pkt_buf { 333 __le16 high_pkt; 334 __le16 low_pkt; 335 u8 rsv[20]; 336 }; 337 338 #define HCLGE_PF_STATE_DONE_B 0 339 #define HCLGE_PF_STATE_MAIN_B 1 340 #define HCLGE_PF_STATE_BOND_B 2 341 #define HCLGE_PF_STATE_MAC_N_B 6 342 #define HCLGE_PF_MAC_NUM_MASK 0x3 343 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) 344 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) 345 struct hclge_func_status { 346 __le32 vf_rst_state[4]; 347 u8 pf_state; 348 u8 mac_id; 349 u8 rsv1; 350 u8 pf_cnt_in_mac; 351 u8 pf_num; 352 u8 vf_num; 353 u8 rsv[2]; 354 }; 355 356 struct hclge_pf_res { 357 __le16 tqp_num; 358 __le16 buf_size; 359 __le16 msixcap_localid_ba_nic; 360 __le16 msixcap_localid_ba_rocee; 361 #define HCLGE_PF_VEC_NUM_S 0 362 #define HCLGE_PF_VEC_NUM_M (0xff << HCLGE_PF_VEC_NUM_S) 363 __le16 pf_intr_vector_number; 364 __le16 pf_own_fun_number; 365 __le32 rsv[3]; 366 }; 367 368 #define HCLGE_CFG_OFFSET_S 0 369 #define HCLGE_CFG_OFFSET_M 0xfffff /* Byte (8-10.3) */ 370 #define HCLGE_CFG_RD_LEN_S 24 371 #define HCLGE_CFG_RD_LEN_M (0xf << HCLGE_CFG_RD_LEN_S) 372 #define HCLGE_CFG_RD_LEN_BYTES 16 373 #define HCLGE_CFG_RD_LEN_UNIT 4 374 375 #define HCLGE_CFG_VMDQ_S 0 376 #define HCLGE_CFG_VMDQ_M (0xff << HCLGE_CFG_VMDQ_S) 377 #define HCLGE_CFG_TC_NUM_S 8 378 #define HCLGE_CFG_TC_NUM_M (0xff << HCLGE_CFG_TC_NUM_S) 379 #define HCLGE_CFG_TQP_DESC_N_S 16 380 #define HCLGE_CFG_TQP_DESC_N_M (0xffff << HCLGE_CFG_TQP_DESC_N_S) 381 #define HCLGE_CFG_PHY_ADDR_S 0 382 #define HCLGE_CFG_PHY_ADDR_M (0x1f << HCLGE_CFG_PHY_ADDR_S) 383 #define HCLGE_CFG_MEDIA_TP_S 8 384 #define HCLGE_CFG_MEDIA_TP_M (0xff << HCLGE_CFG_MEDIA_TP_S) 385 #define HCLGE_CFG_RX_BUF_LEN_S 16 386 #define HCLGE_CFG_RX_BUF_LEN_M (0xffff << HCLGE_CFG_RX_BUF_LEN_S) 387 #define HCLGE_CFG_MAC_ADDR_H_S 0 388 #define HCLGE_CFG_MAC_ADDR_H_M (0xffff << HCLGE_CFG_MAC_ADDR_H_S) 389 #define HCLGE_CFG_DEFAULT_SPEED_S 16 390 #define HCLGE_CFG_DEFAULT_SPEED_M (0xff << HCLGE_CFG_DEFAULT_SPEED_S) 391 392 struct hclge_cfg_param { 393 __le32 offset; 394 __le32 rsv; 395 __le32 param[4]; 396 }; 397 398 #define HCLGE_MAC_MODE 0x0 399 #define HCLGE_DESC_NUM 0x40 400 401 #define HCLGE_ALLOC_VALID_B 0 402 struct hclge_vf_num { 403 u8 alloc_valid; 404 u8 rsv[23]; 405 }; 406 407 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 408 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 409 #define HCLGE_RSS_HASH_KEY_NUM 16 410 struct hclge_rss_config { 411 u8 hash_config; 412 u8 rsv[7]; 413 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; 414 }; 415 416 struct hclge_rss_input_tuple { 417 u8 ipv4_tcp_en; 418 u8 ipv4_udp_en; 419 u8 ipv4_sctp_en; 420 u8 ipv4_fragment_en; 421 u8 ipv6_tcp_en; 422 u8 ipv6_udp_en; 423 u8 ipv6_sctp_en; 424 u8 ipv6_fragment_en; 425 u8 rsv[16]; 426 }; 427 428 #define HCLGE_RSS_CFG_TBL_SIZE 16 429 430 struct hclge_rss_indirection_table { 431 u16 start_table_index; 432 u16 rss_set_bitmap; 433 u8 rsv[4]; 434 u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE]; 435 }; 436 437 #define HCLGE_RSS_TC_OFFSET_S 0 438 #define HCLGE_RSS_TC_OFFSET_M (0x3ff << HCLGE_RSS_TC_OFFSET_S) 439 #define HCLGE_RSS_TC_SIZE_S 12 440 #define HCLGE_RSS_TC_SIZE_M (0x7 << HCLGE_RSS_TC_SIZE_S) 441 #define HCLGE_RSS_TC_VALID_B 15 442 struct hclge_rss_tc_mode { 443 u16 rss_tc_mode[HCLGE_MAX_TC_NUM]; 444 u8 rsv[8]; 445 }; 446 447 #define HCLGE_LINK_STS_B 0 448 #define HCLGE_LINK_STATUS BIT(HCLGE_LINK_STS_B) 449 struct hclge_link_status { 450 u8 status; 451 u8 rsv[23]; 452 }; 453 454 struct hclge_promisc_param { 455 u8 vf_id; 456 u8 enable; 457 }; 458 459 #define HCLGE_PROMISC_EN_B 1 460 #define HCLGE_PROMISC_EN_ALL 0x7 461 #define HCLGE_PROMISC_EN_UC 0x1 462 #define HCLGE_PROMISC_EN_MC 0x2 463 #define HCLGE_PROMISC_EN_BC 0x4 464 struct hclge_promisc_cfg { 465 u8 flag; 466 u8 vf_id; 467 __le16 rsv0; 468 u8 rsv1[20]; 469 }; 470 471 enum hclge_promisc_type { 472 HCLGE_UNICAST = 1, 473 HCLGE_MULTICAST = 2, 474 HCLGE_BROADCAST = 3, 475 }; 476 477 #define HCLGE_MAC_TX_EN_B 6 478 #define HCLGE_MAC_RX_EN_B 7 479 #define HCLGE_MAC_PAD_TX_B 11 480 #define HCLGE_MAC_PAD_RX_B 12 481 #define HCLGE_MAC_1588_TX_B 13 482 #define HCLGE_MAC_1588_RX_B 14 483 #define HCLGE_MAC_APP_LP_B 15 484 #define HCLGE_MAC_LINE_LP_B 16 485 #define HCLGE_MAC_FCS_TX_B 17 486 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 487 #define HCLGE_MAC_RX_FCS_STRIP_B 19 488 #define HCLGE_MAC_RX_FCS_B 20 489 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 490 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 491 492 struct hclge_config_mac_mode { 493 __le32 txrx_pad_fcs_loop_en; 494 u8 rsv[20]; 495 }; 496 497 #define HCLGE_CFG_SPEED_S 0 498 #define HCLGE_CFG_SPEED_M (0x3f << HCLGE_CFG_SPEED_S) 499 500 #define HCLGE_CFG_DUPLEX_B 7 501 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) 502 503 struct hclge_config_mac_speed_dup { 504 u8 speed_dup; 505 506 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 507 u8 mac_change_fec_en; 508 u8 rsv[22]; 509 }; 510 511 #define HCLGE_QUERY_SPEED_S 3 512 #define HCLGE_QUERY_AN_B 0 513 #define HCLGE_QUERY_DUPLEX_B 2 514 515 #define HCLGE_QUERY_SPEED_M (0x1f << HCLGE_QUERY_SPEED_S) 516 #define HCLGE_QUERY_AN_M BIT(HCLGE_QUERY_AN_B) 517 #define HCLGE_QUERY_DUPLEX_M BIT(HCLGE_QUERY_DUPLEX_B) 518 519 struct hclge_query_an_speed_dup { 520 u8 an_syn_dup_speed; 521 u8 pause; 522 u8 rsv[23]; 523 }; 524 525 #define HCLGE_RING_ID_MASK 0x3ff 526 #define HCLGE_TQP_ENABLE_B 0 527 528 #define HCLGE_MAC_CFG_AN_EN_B 0 529 #define HCLGE_MAC_CFG_AN_INT_EN_B 1 530 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 531 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 532 #define HCLGE_MAC_CFG_AN_RST_B 4 533 534 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) 535 536 struct hclge_config_auto_neg { 537 __le32 cfg_an_cmd_flag; 538 u8 rsv[20]; 539 }; 540 541 #define HCLGE_MAC_MIN_MTU 64 542 #define HCLGE_MAC_MAX_MTU 9728 543 #define HCLGE_MAC_UPLINK_PORT 0x100 544 545 struct hclge_config_max_frm_size { 546 __le16 max_frm_size; 547 u8 rsv[22]; 548 }; 549 550 enum hclge_mac_vlan_tbl_opcode { 551 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ 552 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ 553 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ 554 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ 555 }; 556 557 #define HCLGE_MAC_VLAN_BIT0_EN_B 0x0 558 #define HCLGE_MAC_VLAN_BIT1_EN_B 0x1 559 #define HCLGE_MAC_EPORT_SW_EN_B 0xc 560 #define HCLGE_MAC_EPORT_TYPE_B 0xb 561 #define HCLGE_MAC_EPORT_VFID_S 0x3 562 #define HCLGE_MAC_EPORT_VFID_M (0xff << HCLGE_MAC_EPORT_VFID_S) 563 #define HCLGE_MAC_EPORT_PFID_S 0x0 564 #define HCLGE_MAC_EPORT_PFID_M (0x7 << HCLGE_MAC_EPORT_PFID_S) 565 struct hclge_mac_vlan_tbl_entry { 566 u8 flags; 567 u8 resp_code; 568 __le16 vlan_tag; 569 __le32 mac_addr_hi32; 570 __le16 mac_addr_lo16; 571 __le16 rsv1; 572 u8 entry_type; 573 u8 mc_mac_en; 574 __le16 egress_port; 575 __le16 egress_queue; 576 u8 rsv2[6]; 577 }; 578 579 #define HCLGE_CFG_MTA_MAC_SEL_S 0x0 580 #define HCLGE_CFG_MTA_MAC_SEL_M (0x3 << HCLGE_CFG_MTA_MAC_SEL_S) 581 #define HCLGE_CFG_MTA_MAC_EN_B 0x7 582 struct hclge_mta_filter_mode { 583 u8 dmac_sel_en; /* Use lowest 2 bit as sel_mode, bit 7 as enable */ 584 u8 rsv[23]; 585 }; 586 587 #define HCLGE_CFG_FUNC_MTA_ACCEPT_B 0x0 588 struct hclge_cfg_func_mta_filter { 589 u8 accept; /* Only used lowest 1 bit */ 590 u8 function_id; 591 u8 rsv[22]; 592 }; 593 594 #define HCLGE_CFG_MTA_ITEM_ACCEPT_B 0x0 595 #define HCLGE_CFG_MTA_ITEM_IDX_S 0x0 596 #define HCLGE_CFG_MTA_ITEM_IDX_M (0xfff << HCLGE_CFG_MTA_ITEM_IDX_S) 597 struct hclge_cfg_func_mta_item { 598 u16 item_idx; /* Only used lowest 12 bit */ 599 u8 accept; /* Only used lowest 1 bit */ 600 u8 rsv[21]; 601 }; 602 603 struct hclge_mac_vlan_add { 604 __le16 flags; 605 __le16 mac_addr_hi16; 606 __le32 mac_addr_lo32; 607 __le32 mac_addr_msk_hi32; 608 __le16 mac_addr_msk_lo16; 609 __le16 vlan_tag; 610 __le16 ingress_port; 611 __le16 egress_port; 612 u8 rsv[4]; 613 }; 614 615 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0 616 struct hclge_mac_vlan_remove { 617 __le16 flags; 618 __le16 mac_addr_hi16; 619 __le32 mac_addr_lo32; 620 __le32 mac_addr_msk_hi32; 621 __le16 mac_addr_msk_lo16; 622 __le16 vlan_tag; 623 __le16 ingress_port; 624 __le16 egress_port; 625 u8 rsv[4]; 626 }; 627 628 struct hclge_vlan_filter_ctrl { 629 u8 vlan_type; 630 u8 vlan_fe; 631 u8 rsv[22]; 632 }; 633 634 struct hclge_vlan_filter_pf_cfg { 635 u8 vlan_offset; 636 u8 vlan_cfg; 637 u8 rsv[2]; 638 u8 vlan_offset_bitmap[20]; 639 }; 640 641 struct hclge_vlan_filter_vf_cfg { 642 u16 vlan_id; 643 u8 resp_code; 644 u8 rsv; 645 u8 vlan_cfg; 646 u8 rsv1[3]; 647 u8 vf_bitmap[16]; 648 }; 649 650 struct hclge_cfg_com_tqp_queue { 651 __le16 tqp_id; 652 __le16 stream_id; 653 u8 enable; 654 u8 rsv[19]; 655 }; 656 657 struct hclge_cfg_tx_queue_pointer { 658 __le16 tqp_id; 659 __le16 tx_tail; 660 __le16 tx_head; 661 __le16 fbd_num; 662 __le16 ring_offset; 663 u8 rsv[14]; 664 }; 665 666 #define HCLGE_TSO_MSS_MIN_S 0 667 #define HCLGE_TSO_MSS_MIN_M (0x3FFF << HCLGE_TSO_MSS_MIN_S) 668 669 #define HCLGE_TSO_MSS_MAX_S 16 670 #define HCLGE_TSO_MSS_MAX_M (0x3FFF << HCLGE_TSO_MSS_MAX_S) 671 672 struct hclge_cfg_tso_status { 673 __le16 tso_mss_min; 674 __le16 tso_mss_max; 675 u8 rsv[20]; 676 }; 677 678 #define HCLGE_TSO_MSS_MIN 256 679 #define HCLGE_TSO_MSS_MAX 9668 680 681 #define HCLGE_TQP_RESET_B 0 682 struct hclge_reset_tqp_queue { 683 __le16 tqp_id; 684 u8 reset_req; 685 u8 ready_to_reset; 686 u8 rsv[20]; 687 }; 688 689 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ 690 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ 691 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ 692 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ 693 694 #define HCLGE_TYPE_CRQ 0 695 #define HCLGE_TYPE_CSQ 1 696 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 697 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 698 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 699 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 700 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 701 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 702 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c 703 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 704 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 705 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 706 #define HCLGE_NIC_CMQ_EN_B 16 707 #define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B) 708 #define HCLGE_NIC_CMQ_DESC_NUM 1024 709 #define HCLGE_NIC_CMQ_DESC_NUM_S 3 710 711 int hclge_cmd_init(struct hclge_dev *hdev); 712 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) 713 { 714 writel(value, base + reg); 715 } 716 717 #define hclge_write_dev(a, reg, value) \ 718 hclge_write_reg((a)->io_base, (reg), (value)) 719 #define hclge_read_dev(a, reg) \ 720 hclge_read_reg((a)->io_base, (reg)) 721 722 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) 723 { 724 u8 __iomem *reg_addr = READ_ONCE(base); 725 726 return readl(reg_addr + reg); 727 } 728 729 #define HCLGE_SEND_SYNC(flag) \ 730 ((flag) & HCLGE_CMD_FLAG_NO_INTR) 731 732 struct hclge_hw; 733 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); 734 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, 735 enum hclge_opcode_type opcode, bool is_read); 736 737 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, 738 struct hclge_promisc_param *param); 739 740 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, 741 struct hclge_desc *desc); 742 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, 743 struct hclge_desc *desc); 744 745 void hclge_destroy_cmd_queue(struct hclge_hw *hw); 746 #endif 747