1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_CMD_H 5 #define __HCLGE_CMD_H 6 #include <linux/types.h> 7 #include <linux/io.h> 8 #include <linux/etherdevice.h> 9 #include "hnae3.h" 10 11 #define HCLGE_CMDQ_TX_TIMEOUT 30000 12 #define HCLGE_DESC_DATA_LEN 6 13 14 struct hclge_dev; 15 struct hclge_desc { 16 __le16 opcode; 17 18 #define HCLGE_CMDQ_RX_INVLD_B 0 19 #define HCLGE_CMDQ_RX_OUTVLD_B 1 20 21 __le16 flag; 22 __le16 retval; 23 __le16 rsv; 24 __le32 data[HCLGE_DESC_DATA_LEN]; 25 }; 26 27 struct hclge_cmq_ring { 28 dma_addr_t desc_dma_addr; 29 struct hclge_desc *desc; 30 struct hclge_dev *dev; 31 u32 head; 32 u32 tail; 33 34 u16 buf_size; 35 u16 desc_num; 36 int next_to_use; 37 int next_to_clean; 38 u8 ring_type; /* cmq ring type */ 39 spinlock_t lock; /* Command queue lock */ 40 }; 41 42 enum hclge_cmd_return_status { 43 HCLGE_CMD_EXEC_SUCCESS = 0, 44 HCLGE_CMD_NO_AUTH = 1, 45 HCLGE_CMD_NOT_SUPPORTED = 2, 46 HCLGE_CMD_QUEUE_FULL = 3, 47 HCLGE_CMD_NEXT_ERR = 4, 48 HCLGE_CMD_UNEXE_ERR = 5, 49 HCLGE_CMD_PARA_ERR = 6, 50 HCLGE_CMD_RESULT_ERR = 7, 51 HCLGE_CMD_TIMEOUT = 8, 52 HCLGE_CMD_HILINK_ERR = 9, 53 HCLGE_CMD_QUEUE_ILLEGAL = 10, 54 HCLGE_CMD_INVALID = 11, 55 }; 56 57 enum hclge_cmd_status { 58 HCLGE_STATUS_SUCCESS = 0, 59 HCLGE_ERR_CSQ_FULL = -1, 60 HCLGE_ERR_CSQ_TIMEOUT = -2, 61 HCLGE_ERR_CSQ_ERROR = -3, 62 }; 63 64 struct hclge_misc_vector { 65 u8 __iomem *addr; 66 int vector_irq; 67 char name[HNAE3_INT_NAME_LEN]; 68 }; 69 70 struct hclge_cmq { 71 struct hclge_cmq_ring csq; 72 struct hclge_cmq_ring crq; 73 u16 tx_timeout; 74 enum hclge_cmd_status last_status; 75 }; 76 77 #define HCLGE_CMD_FLAG_IN BIT(0) 78 #define HCLGE_CMD_FLAG_OUT BIT(1) 79 #define HCLGE_CMD_FLAG_NEXT BIT(2) 80 #define HCLGE_CMD_FLAG_WR BIT(3) 81 #define HCLGE_CMD_FLAG_NO_INTR BIT(4) 82 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5) 83 84 enum hclge_opcode_type { 85 /* Generic commands */ 86 HCLGE_OPC_QUERY_FW_VER = 0x0001, 87 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, 88 HCLGE_OPC_GBL_RST_STATUS = 0x0021, 89 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, 90 HCLGE_OPC_QUERY_PF_RSRC = 0x0023, 91 HCLGE_OPC_QUERY_VF_RSRC = 0x0024, 92 HCLGE_OPC_GET_CFG_PARAM = 0x0025, 93 HCLGE_OPC_PF_RST_DONE = 0x0026, 94 HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027, 95 96 HCLGE_OPC_STATS_64_BIT = 0x0030, 97 HCLGE_OPC_STATS_32_BIT = 0x0031, 98 HCLGE_OPC_STATS_MAC = 0x0032, 99 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033, 100 HCLGE_OPC_STATS_MAC_ALL = 0x0034, 101 102 HCLGE_OPC_QUERY_REG_NUM = 0x0040, 103 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, 104 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, 105 HCLGE_OPC_DFX_BD_NUM = 0x0043, 106 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044, 107 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045, 108 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046, 109 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047, 110 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048, 111 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049, 112 HCLGE_OPC_DFX_NCSI_REG = 0x004A, 113 HCLGE_OPC_DFX_RTC_REG = 0x004B, 114 HCLGE_OPC_DFX_PPP_REG = 0x004C, 115 HCLGE_OPC_DFX_RCB_REG = 0x004D, 116 HCLGE_OPC_DFX_TQP_REG = 0x004E, 117 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F, 118 119 HCLGE_OPC_QUERY_DEV_SPECS = 0x0050, 120 121 /* MAC command */ 122 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, 123 HCLGE_OPC_CONFIG_AN_MODE = 0x0304, 124 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, 125 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, 126 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, 127 HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310, 128 HCLGE_OPC_MAC_TNL_INT_EN = 0x0311, 129 HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312, 130 HCLGE_OPC_COMMON_LOOPBACK = 0x0315, 131 HCLGE_OPC_CONFIG_FEC_MODE = 0x031A, 132 133 /* PFC/Pause commands */ 134 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, 135 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, 136 HCLGE_OPC_CFG_MAC_PARA = 0x0703, 137 HCLGE_OPC_CFG_PFC_PARA = 0x0704, 138 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, 139 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, 140 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, 141 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, 142 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, 143 HCLGE_OPC_QOS_MAP = 0x070A, 144 145 /* ETS/scheduler commands */ 146 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, 147 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, 148 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, 149 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, 150 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, 151 HCLGE_OPC_TM_PG_WEIGHT = 0x0809, 152 HCLGE_OPC_TM_QS_WEIGHT = 0x080A, 153 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, 154 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, 155 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, 156 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, 157 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, 158 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, 159 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, 160 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, 161 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, 162 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, 163 HCLGE_OPC_TM_NODES = 0x0816, 164 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843, 165 HCLGE_OPC_QSET_DFX_STS = 0x0844, 166 HCLGE_OPC_PRI_DFX_STS = 0x0845, 167 HCLGE_OPC_PG_DFX_STS = 0x0846, 168 HCLGE_OPC_PORT_DFX_STS = 0x0847, 169 HCLGE_OPC_SCH_NQ_CNT = 0x0848, 170 HCLGE_OPC_SCH_RQ_CNT = 0x0849, 171 HCLGE_OPC_TM_INTERNAL_STS = 0x0850, 172 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851, 173 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852, 174 175 /* Packet buffer allocate commands */ 176 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, 177 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, 178 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, 179 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, 180 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, 181 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, 182 183 /* TQP management command */ 184 HCLGE_OPC_SET_TQP_MAP = 0x0A01, 185 186 /* TQP commands */ 187 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, 188 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, 189 HCLGE_OPC_QUERY_TX_STATS = 0x0B03, 190 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04, 191 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, 192 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, 193 HCLGE_OPC_QUERY_RX_STATS = 0x0B13, 194 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, 195 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, 196 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 197 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, 198 199 /* PPU commands */ 200 HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A, 201 202 /* TSO command */ 203 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, 204 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10, 205 206 /* RSS commands */ 207 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, 208 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, 209 HCLGE_OPC_RSS_TC_MODE = 0x0D08, 210 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, 211 212 /* Promisuous mode command */ 213 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, 214 215 /* Vlan offload commands */ 216 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, 217 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, 218 219 /* Interrupts commands */ 220 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, 221 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, 222 223 /* MAC commands */ 224 HCLGE_OPC_MAC_VLAN_ADD = 0x1000, 225 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, 226 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, 227 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, 228 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004, 229 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, 230 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, 231 232 /* MAC VLAN commands */ 233 HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033, 234 235 /* VLAN commands */ 236 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, 237 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, 238 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, 239 HCLGE_OPC_PORT_VLAN_BYPASS = 0x1103, 240 241 /* Flow Director commands */ 242 HCLGE_OPC_FD_MODE_CTRL = 0x1200, 243 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201, 244 HCLGE_OPC_FD_KEY_CONFIG = 0x1202, 245 HCLGE_OPC_FD_TCAM_OP = 0x1203, 246 HCLGE_OPC_FD_AD_OP = 0x1204, 247 HCLGE_OPC_FD_USER_DEF_OP = 0x1207, 248 249 /* MDIO command */ 250 HCLGE_OPC_MDIO_CONFIG = 0x1900, 251 252 /* QCN commands */ 253 HCLGE_OPC_QCN_MOD_CFG = 0x1A01, 254 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, 255 HCLGE_OPC_QCN_SHAPPING_CFG = 0x1A03, 256 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, 257 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, 258 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, 259 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, 260 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, 261 262 /* Mailbox command */ 263 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, 264 265 /* Led command */ 266 HCLGE_OPC_LED_STATUS_CFG = 0xB000, 267 268 /* NCL config command */ 269 HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011, 270 271 /* IMP stats command */ 272 HCLGE_OPC_IMP_STATS_BD = 0x7012, 273 HCLGE_OPC_IMP_STATS_INFO = 0x7013, 274 HCLGE_OPC_IMP_COMPAT_CFG = 0x701A, 275 276 /* SFP command */ 277 HCLGE_OPC_GET_SFP_EEPROM = 0x7100, 278 HCLGE_OPC_GET_SFP_EXIST = 0x7101, 279 HCLGE_OPC_GET_SFP_INFO = 0x7104, 280 281 /* Error INT commands */ 282 HCLGE_MAC_COMMON_INT_EN = 0x030E, 283 HCLGE_TM_SCH_ECC_INT_EN = 0x0829, 284 HCLGE_SSU_ECC_INT_CMD = 0x0989, 285 HCLGE_SSU_COMMON_INT_CMD = 0x098C, 286 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40, 287 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41, 288 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42, 289 HCLGE_COMMON_ECC_INT_CFG = 0x1505, 290 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510, 291 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511, 292 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512, 293 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513, 294 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514, 295 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515, 296 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580, 297 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581, 298 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584, 299 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585, 300 HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586, 301 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803, 302 HCLGE_IGU_COMMON_INT_EN = 0x1806, 303 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14, 304 HCLGE_PPP_CMD0_INT_CMD = 0x2100, 305 HCLGE_PPP_CMD1_INT_CMD = 0x2101, 306 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105, 307 HCLGE_NCSI_INT_EN = 0x2401, 308 309 /* PHY command */ 310 HCLGE_OPC_PHY_LINK_KSETTING = 0x7025, 311 HCLGE_OPC_PHY_REG = 0x7026, 312 }; 313 314 #define HCLGE_TQP_REG_OFFSET 0x80000 315 #define HCLGE_TQP_REG_SIZE 0x200 316 317 #define HCLGE_TQP_MAX_SIZE_DEV_V2 1024 318 #define HCLGE_TQP_EXT_REG_OFFSET 0x100 319 320 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 321 #define HCLGE_RCB_INIT_FLAG_EN_B 0 322 #define HCLGE_RCB_INIT_FLAG_FINI_B 8 323 struct hclge_config_rcb_init_cmd { 324 __le16 rcb_init_flag; 325 u8 rsv[22]; 326 }; 327 328 struct hclge_tqp_map_cmd { 329 __le16 tqp_id; /* Absolute tqp id for in this pf */ 330 u8 tqp_vf; /* VF id */ 331 #define HCLGE_TQP_MAP_TYPE_PF 0 332 #define HCLGE_TQP_MAP_TYPE_VF 1 333 #define HCLGE_TQP_MAP_TYPE_B 0 334 #define HCLGE_TQP_MAP_EN_B 1 335 u8 tqp_flag; /* Indicate it's pf or vf tqp */ 336 __le16 tqp_vid; /* Virtual id in this pf/vf */ 337 u8 rsv[18]; 338 }; 339 340 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 341 342 enum hclge_int_type { 343 HCLGE_INT_TX, 344 HCLGE_INT_RX, 345 HCLGE_INT_EVENT, 346 }; 347 348 struct hclge_ctrl_vector_chain_cmd { 349 #define HCLGE_VECTOR_ID_L_S 0 350 #define HCLGE_VECTOR_ID_L_M GENMASK(7, 0) 351 u8 int_vector_id_l; 352 u8 int_cause_num; 353 #define HCLGE_INT_TYPE_S 0 354 #define HCLGE_INT_TYPE_M GENMASK(1, 0) 355 #define HCLGE_TQP_ID_S 2 356 #define HCLGE_TQP_ID_M GENMASK(12, 2) 357 #define HCLGE_INT_GL_IDX_S 13 358 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) 359 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; 360 u8 vfid; 361 #define HCLGE_VECTOR_ID_H_S 8 362 #define HCLGE_VECTOR_ID_H_M GENMASK(15, 8) 363 u8 int_vector_id_h; 364 }; 365 366 #define HCLGE_MAX_TC_NUM 8 367 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ 368 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ 369 struct hclge_tx_buff_alloc_cmd { 370 __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM]; 371 u8 tx_buff_rsv[8]; 372 }; 373 374 struct hclge_rx_priv_buff_cmd { 375 __le16 buf_num[HCLGE_MAX_TC_NUM]; 376 __le16 shared_buf; 377 u8 rsv[6]; 378 }; 379 380 enum HCLGE_CAP_BITS { 381 HCLGE_CAP_UDP_GSO_B, 382 HCLGE_CAP_QB_B, 383 HCLGE_CAP_FD_FORWARD_TC_B, 384 HCLGE_CAP_PTP_B, 385 HCLGE_CAP_INT_QL_B, 386 HCLGE_CAP_HW_TX_CSUM_B, 387 HCLGE_CAP_TX_PUSH_B, 388 HCLGE_CAP_PHY_IMP_B, 389 HCLGE_CAP_TQP_TXRX_INDEP_B, 390 HCLGE_CAP_HW_PAD_B, 391 HCLGE_CAP_STASH_B, 392 HCLGE_CAP_UDP_TUNNEL_CSUM_B, 393 HCLGE_CAP_FEC_B = 13, 394 HCLGE_CAP_PAUSE_B = 14, 395 HCLGE_CAP_RXD_ADV_LAYOUT_B = 15, 396 HCLGE_CAP_PORT_VLAN_BYPASS_B = 17, 397 }; 398 399 enum HCLGE_API_CAP_BITS { 400 HCLGE_API_CAP_FLEX_RSS_TBL_B, 401 }; 402 403 #define HCLGE_QUERY_CAP_LENGTH 3 404 struct hclge_query_version_cmd { 405 __le32 firmware; 406 __le32 hardware; 407 __le32 api_caps; 408 __le32 caps[HCLGE_QUERY_CAP_LENGTH]; /* capabilities of device */ 409 }; 410 411 #define HCLGE_RX_PRIV_EN_B 15 412 #define HCLGE_TC_NUM_ONE_DESC 4 413 struct hclge_priv_wl { 414 __le16 high; 415 __le16 low; 416 }; 417 418 struct hclge_rx_priv_wl_buf { 419 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; 420 }; 421 422 struct hclge_rx_com_thrd { 423 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; 424 }; 425 426 struct hclge_rx_com_wl { 427 struct hclge_priv_wl com_wl; 428 }; 429 430 struct hclge_waterline { 431 u32 low; 432 u32 high; 433 }; 434 435 struct hclge_tc_thrd { 436 u32 low; 437 u32 high; 438 }; 439 440 struct hclge_priv_buf { 441 struct hclge_waterline wl; /* Waterline for low and high*/ 442 u32 buf_size; /* TC private buffer size */ 443 u32 tx_buf_size; 444 u32 enable; /* Enable TC private buffer or not */ 445 }; 446 447 struct hclge_shared_buf { 448 struct hclge_waterline self; 449 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; 450 u32 buf_size; 451 }; 452 453 struct hclge_pkt_buf_alloc { 454 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; 455 struct hclge_shared_buf s_buf; 456 }; 457 458 #define HCLGE_RX_COM_WL_EN_B 15 459 struct hclge_rx_com_wl_buf_cmd { 460 __le16 high_wl; 461 __le16 low_wl; 462 u8 rsv[20]; 463 }; 464 465 #define HCLGE_RX_PKT_EN_B 15 466 struct hclge_rx_pkt_buf_cmd { 467 __le16 high_pkt; 468 __le16 low_pkt; 469 u8 rsv[20]; 470 }; 471 472 #define HCLGE_PF_STATE_DONE_B 0 473 #define HCLGE_PF_STATE_MAIN_B 1 474 #define HCLGE_PF_STATE_BOND_B 2 475 #define HCLGE_PF_STATE_MAC_N_B 6 476 #define HCLGE_PF_MAC_NUM_MASK 0x3 477 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) 478 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) 479 #define HCLGE_VF_RST_STATUS_CMD 4 480 481 struct hclge_func_status_cmd { 482 __le32 vf_rst_state[HCLGE_VF_RST_STATUS_CMD]; 483 u8 pf_state; 484 u8 mac_id; 485 u8 rsv1; 486 u8 pf_cnt_in_mac; 487 u8 pf_num; 488 u8 vf_num; 489 u8 rsv[2]; 490 }; 491 492 struct hclge_pf_res_cmd { 493 __le16 tqp_num; 494 __le16 buf_size; 495 __le16 msixcap_localid_ba_nic; 496 __le16 msixcap_localid_number_nic; 497 __le16 pf_intr_vector_number_roce; 498 __le16 pf_own_fun_number; 499 __le16 tx_buf_size; 500 __le16 dv_buf_size; 501 __le16 ext_tqp_num; 502 u8 rsv[6]; 503 }; 504 505 #define HCLGE_CFG_OFFSET_S 0 506 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) 507 #define HCLGE_CFG_RD_LEN_S 24 508 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) 509 #define HCLGE_CFG_RD_LEN_BYTES 16 510 #define HCLGE_CFG_RD_LEN_UNIT 4 511 512 #define HCLGE_CFG_TC_NUM_S 8 513 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) 514 #define HCLGE_CFG_TQP_DESC_N_S 16 515 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) 516 #define HCLGE_CFG_PHY_ADDR_S 0 517 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) 518 #define HCLGE_CFG_MEDIA_TP_S 8 519 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) 520 #define HCLGE_CFG_RX_BUF_LEN_S 16 521 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) 522 #define HCLGE_CFG_MAC_ADDR_H_S 0 523 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) 524 #define HCLGE_CFG_DEFAULT_SPEED_S 16 525 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) 526 #define HCLGE_CFG_RSS_SIZE_S 24 527 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) 528 #define HCLGE_CFG_SPEED_ABILITY_S 0 529 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) 530 #define HCLGE_CFG_SPEED_ABILITY_EXT_S 10 531 #define HCLGE_CFG_SPEED_ABILITY_EXT_M GENMASK(15, 10) 532 #define HCLGE_CFG_VLAN_FLTR_CAP_S 8 533 #define HCLGE_CFG_VLAN_FLTR_CAP_M GENMASK(9, 8) 534 #define HCLGE_CFG_UMV_TBL_SPACE_S 16 535 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) 536 #define HCLGE_CFG_PF_RSS_SIZE_S 0 537 #define HCLGE_CFG_PF_RSS_SIZE_M GENMASK(3, 0) 538 539 #define HCLGE_CFG_CMD_CNT 4 540 541 struct hclge_cfg_param_cmd { 542 __le32 offset; 543 __le32 rsv; 544 __le32 param[HCLGE_CFG_CMD_CNT]; 545 }; 546 547 #define HCLGE_MAC_MODE 0x0 548 #define HCLGE_DESC_NUM 0x40 549 550 #define HCLGE_ALLOC_VALID_B 0 551 struct hclge_vf_num_cmd { 552 u8 alloc_valid; 553 u8 rsv[23]; 554 }; 555 556 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 557 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 558 #define HCLGE_RSS_HASH_KEY_NUM 16 559 struct hclge_rss_config_cmd { 560 u8 hash_config; 561 u8 rsv[7]; 562 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; 563 }; 564 565 struct hclge_rss_input_tuple_cmd { 566 u8 ipv4_tcp_en; 567 u8 ipv4_udp_en; 568 u8 ipv4_sctp_en; 569 u8 ipv4_fragment_en; 570 u8 ipv6_tcp_en; 571 u8 ipv6_udp_en; 572 u8 ipv6_sctp_en; 573 u8 ipv6_fragment_en; 574 u8 rsv[16]; 575 }; 576 577 #define HCLGE_RSS_CFG_TBL_SIZE 16 578 #define HCLGE_RSS_CFG_TBL_SIZE_H 4 579 #define HCLGE_RSS_CFG_TBL_BW_H 2U 580 #define HCLGE_RSS_CFG_TBL_BW_L 8U 581 582 struct hclge_rss_indirection_table_cmd { 583 __le16 start_table_index; 584 __le16 rss_set_bitmap; 585 u8 rss_qid_h[HCLGE_RSS_CFG_TBL_SIZE_H]; 586 u8 rss_qid_l[HCLGE_RSS_CFG_TBL_SIZE]; 587 }; 588 589 #define HCLGE_RSS_TC_OFFSET_S 0 590 #define HCLGE_RSS_TC_OFFSET_M GENMASK(10, 0) 591 #define HCLGE_RSS_TC_SIZE_MSB_B 11 592 #define HCLGE_RSS_TC_SIZE_S 12 593 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) 594 #define HCLGE_RSS_TC_SIZE_MSB_OFFSET 3 595 #define HCLGE_RSS_TC_VALID_B 15 596 struct hclge_rss_tc_mode_cmd { 597 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; 598 u8 rsv[8]; 599 }; 600 601 #define HCLGE_LINK_STATUS_UP_B 0 602 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B) 603 struct hclge_link_status_cmd { 604 u8 status; 605 u8 rsv[23]; 606 }; 607 608 /* for DEVICE_VERSION_V1/2, reference to promisc cmd byte8 */ 609 #define HCLGE_PROMISC_EN_UC 1 610 #define HCLGE_PROMISC_EN_MC 2 611 #define HCLGE_PROMISC_EN_BC 3 612 #define HCLGE_PROMISC_TX_EN 4 613 #define HCLGE_PROMISC_RX_EN 5 614 615 /* for DEVICE_VERSION_V3, reference to promisc cmd byte10 */ 616 #define HCLGE_PROMISC_UC_RX_EN 2 617 #define HCLGE_PROMISC_MC_RX_EN 3 618 #define HCLGE_PROMISC_BC_RX_EN 4 619 #define HCLGE_PROMISC_UC_TX_EN 5 620 #define HCLGE_PROMISC_MC_TX_EN 6 621 #define HCLGE_PROMISC_BC_TX_EN 7 622 623 struct hclge_promisc_cfg_cmd { 624 u8 promisc; 625 u8 vf_id; 626 u8 extend_promisc; 627 u8 rsv0[21]; 628 }; 629 630 enum hclge_promisc_type { 631 HCLGE_UNICAST = 1, 632 HCLGE_MULTICAST = 2, 633 HCLGE_BROADCAST = 3, 634 }; 635 636 #define HCLGE_MAC_TX_EN_B 6 637 #define HCLGE_MAC_RX_EN_B 7 638 #define HCLGE_MAC_PAD_TX_B 11 639 #define HCLGE_MAC_PAD_RX_B 12 640 #define HCLGE_MAC_1588_TX_B 13 641 #define HCLGE_MAC_1588_RX_B 14 642 #define HCLGE_MAC_APP_LP_B 15 643 #define HCLGE_MAC_LINE_LP_B 16 644 #define HCLGE_MAC_FCS_TX_B 17 645 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 646 #define HCLGE_MAC_RX_FCS_STRIP_B 19 647 #define HCLGE_MAC_RX_FCS_B 20 648 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 649 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 650 651 struct hclge_config_mac_mode_cmd { 652 __le32 txrx_pad_fcs_loop_en; 653 u8 rsv[20]; 654 }; 655 656 struct hclge_pf_rst_sync_cmd { 657 #define HCLGE_PF_RST_ALL_VF_RDY_B 0 658 u8 all_vf_ready; 659 u8 rsv[23]; 660 }; 661 662 #define HCLGE_CFG_SPEED_S 0 663 #define HCLGE_CFG_SPEED_M GENMASK(5, 0) 664 665 #define HCLGE_CFG_DUPLEX_B 7 666 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) 667 668 struct hclge_config_mac_speed_dup_cmd { 669 u8 speed_dup; 670 671 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 672 u8 mac_change_fec_en; 673 u8 rsv[22]; 674 }; 675 676 #define HCLGE_TQP_ENABLE_B 0 677 678 #define HCLGE_MAC_CFG_AN_EN_B 0 679 #define HCLGE_MAC_CFG_AN_INT_EN_B 1 680 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 681 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 682 #define HCLGE_MAC_CFG_AN_RST_B 4 683 684 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) 685 686 struct hclge_config_auto_neg_cmd { 687 __le32 cfg_an_cmd_flag; 688 u8 rsv[20]; 689 }; 690 691 struct hclge_sfp_info_cmd { 692 __le32 speed; 693 u8 query_type; /* 0: sfp speed, 1: active speed */ 694 u8 active_fec; 695 u8 autoneg; /* autoneg state */ 696 u8 autoneg_ability; /* whether support autoneg */ 697 __le32 speed_ability; /* speed ability for current media */ 698 __le32 module_type; 699 u8 rsv[8]; 700 }; 701 702 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0 703 #define HCLGE_MAC_CFG_FEC_MODE_S 1 704 #define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1) 705 #define HCLGE_MAC_CFG_FEC_SET_DEF_B 0 706 #define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1 707 708 #define HCLGE_MAC_FEC_OFF 0 709 #define HCLGE_MAC_FEC_BASER 1 710 #define HCLGE_MAC_FEC_RS 2 711 struct hclge_config_fec_cmd { 712 u8 fec_mode; 713 u8 default_config; 714 u8 rsv[22]; 715 }; 716 717 #define HCLGE_MAC_UPLINK_PORT 0x100 718 719 struct hclge_config_max_frm_size_cmd { 720 __le16 max_frm_size; 721 u8 min_frm_size; 722 u8 rsv[21]; 723 }; 724 725 enum hclge_mac_vlan_tbl_opcode { 726 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ 727 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ 728 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ 729 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ 730 }; 731 732 enum hclge_mac_vlan_add_resp_code { 733 HCLGE_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */ 734 HCLGE_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */ 735 }; 736 737 #define HCLGE_MAC_VLAN_BIT0_EN_B 0 738 #define HCLGE_MAC_VLAN_BIT1_EN_B 1 739 #define HCLGE_MAC_EPORT_SW_EN_B 12 740 #define HCLGE_MAC_EPORT_TYPE_B 11 741 #define HCLGE_MAC_EPORT_VFID_S 3 742 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) 743 #define HCLGE_MAC_EPORT_PFID_S 0 744 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) 745 struct hclge_mac_vlan_tbl_entry_cmd { 746 u8 flags; 747 u8 resp_code; 748 __le16 vlan_tag; 749 __le32 mac_addr_hi32; 750 __le16 mac_addr_lo16; 751 __le16 rsv1; 752 u8 entry_type; 753 u8 mc_mac_en; 754 __le16 egress_port; 755 __le16 egress_queue; 756 u8 rsv2[6]; 757 }; 758 759 #define HCLGE_UMV_SPC_ALC_B 0 760 struct hclge_umv_spc_alc_cmd { 761 u8 allocate; 762 u8 rsv1[3]; 763 __le32 space_size; 764 u8 rsv2[16]; 765 }; 766 767 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) 768 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) 769 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) 770 771 struct hclge_mac_mgr_tbl_entry_cmd { 772 u8 flags; 773 u8 resp_code; 774 __le16 vlan_tag; 775 u8 mac_addr[ETH_ALEN]; 776 __le16 rsv1; 777 __le16 ethter_type; 778 __le16 egress_port; 779 __le16 egress_queue; 780 u8 sw_port_id_aware; 781 u8 rsv2; 782 u8 i_port_bitmap; 783 u8 i_port_direction; 784 u8 rsv3[2]; 785 }; 786 787 struct hclge_vlan_filter_ctrl_cmd { 788 u8 vlan_type; 789 u8 vlan_fe; 790 u8 rsv1[2]; 791 u8 vf_id; 792 u8 rsv2[19]; 793 }; 794 795 #define HCLGE_VLAN_ID_OFFSET_STEP 160 796 #define HCLGE_VLAN_BYTE_SIZE 8 797 #define HCLGE_VLAN_OFFSET_BITMAP \ 798 (HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE) 799 800 struct hclge_vlan_filter_pf_cfg_cmd { 801 u8 vlan_offset; 802 u8 vlan_cfg; 803 u8 rsv[2]; 804 u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP]; 805 }; 806 807 #define HCLGE_MAX_VF_BYTES 16 808 809 struct hclge_vlan_filter_vf_cfg_cmd { 810 __le16 vlan_id; 811 u8 resp_code; 812 u8 rsv; 813 u8 vlan_cfg; 814 u8 rsv1[3]; 815 u8 vf_bitmap[HCLGE_MAX_VF_BYTES]; 816 }; 817 818 #define HCLGE_INGRESS_BYPASS_B 0 819 struct hclge_port_vlan_filter_bypass_cmd { 820 u8 bypass_state; 821 u8 rsv1[3]; 822 u8 vf_id; 823 u8 rsv2[19]; 824 }; 825 826 #define HCLGE_SWITCH_ANTI_SPOOF_B 0U 827 #define HCLGE_SWITCH_ALW_LPBK_B 1U 828 #define HCLGE_SWITCH_ALW_LCL_LPBK_B 2U 829 #define HCLGE_SWITCH_ALW_DST_OVRD_B 3U 830 #define HCLGE_SWITCH_NO_MASK 0x0 831 #define HCLGE_SWITCH_ANTI_SPOOF_MASK 0xFE 832 #define HCLGE_SWITCH_ALW_LPBK_MASK 0xFD 833 #define HCLGE_SWITCH_ALW_LCL_LPBK_MASK 0xFB 834 #define HCLGE_SWITCH_LW_DST_OVRD_MASK 0xF7 835 836 struct hclge_mac_vlan_switch_cmd { 837 u8 roce_sel; 838 u8 rsv1[3]; 839 __le32 func_id; 840 u8 switch_param; 841 u8 rsv2[3]; 842 u8 param_mask; 843 u8 rsv3[11]; 844 }; 845 846 enum hclge_mac_vlan_cfg_sel { 847 HCLGE_MAC_VLAN_NIC_SEL = 0, 848 HCLGE_MAC_VLAN_ROCE_SEL, 849 }; 850 851 #define HCLGE_ACCEPT_TAG1_B 0 852 #define HCLGE_ACCEPT_UNTAG1_B 1 853 #define HCLGE_PORT_INS_TAG1_EN_B 2 854 #define HCLGE_PORT_INS_TAG2_EN_B 3 855 #define HCLGE_CFG_NIC_ROCE_SEL_B 4 856 #define HCLGE_ACCEPT_TAG2_B 5 857 #define HCLGE_ACCEPT_UNTAG2_B 6 858 #define HCLGE_TAG_SHIFT_MODE_EN_B 7 859 #define HCLGE_VF_NUM_PER_BYTE 8 860 861 struct hclge_vport_vtag_tx_cfg_cmd { 862 u8 vport_vlan_cfg; 863 u8 vf_offset; 864 u8 rsv1[2]; 865 __le16 def_vlan_tag1; 866 __le16 def_vlan_tag2; 867 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE]; 868 u8 rsv2[8]; 869 }; 870 871 #define HCLGE_REM_TAG1_EN_B 0 872 #define HCLGE_REM_TAG2_EN_B 1 873 #define HCLGE_SHOW_TAG1_EN_B 2 874 #define HCLGE_SHOW_TAG2_EN_B 3 875 #define HCLGE_DISCARD_TAG1_EN_B 5 876 #define HCLGE_DISCARD_TAG2_EN_B 6 877 struct hclge_vport_vtag_rx_cfg_cmd { 878 u8 vport_vlan_cfg; 879 u8 vf_offset; 880 u8 rsv1[6]; 881 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE]; 882 u8 rsv2[8]; 883 }; 884 885 struct hclge_tx_vlan_type_cfg_cmd { 886 __le16 ot_vlan_type; 887 __le16 in_vlan_type; 888 u8 rsv[20]; 889 }; 890 891 struct hclge_rx_vlan_type_cfg_cmd { 892 __le16 ot_fst_vlan_type; 893 __le16 ot_sec_vlan_type; 894 __le16 in_fst_vlan_type; 895 __le16 in_sec_vlan_type; 896 u8 rsv[16]; 897 }; 898 899 struct hclge_cfg_com_tqp_queue_cmd { 900 __le16 tqp_id; 901 __le16 stream_id; 902 u8 enable; 903 u8 rsv[19]; 904 }; 905 906 struct hclge_cfg_tx_queue_pointer_cmd { 907 __le16 tqp_id; 908 __le16 tx_tail; 909 __le16 tx_head; 910 __le16 fbd_num; 911 __le16 ring_offset; 912 u8 rsv[14]; 913 }; 914 915 #pragma pack(1) 916 struct hclge_mac_ethertype_idx_rd_cmd { 917 u8 flags; 918 u8 resp_code; 919 __le16 vlan_tag; 920 u8 mac_addr[ETH_ALEN]; 921 __le16 index; 922 __le16 ethter_type; 923 __le16 egress_port; 924 __le16 egress_queue; 925 __le16 rev0; 926 u8 i_port_bitmap; 927 u8 i_port_direction; 928 u8 rev1[2]; 929 }; 930 931 #pragma pack() 932 933 #define HCLGE_TSO_MSS_MIN_S 0 934 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) 935 936 #define HCLGE_TSO_MSS_MAX_S 16 937 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) 938 939 struct hclge_cfg_tso_status_cmd { 940 __le16 tso_mss_min; 941 __le16 tso_mss_max; 942 u8 rsv[20]; 943 }; 944 945 #define HCLGE_GRO_EN_B 0 946 struct hclge_cfg_gro_status_cmd { 947 u8 gro_en; 948 u8 rsv[23]; 949 }; 950 951 #define HCLGE_TSO_MSS_MIN 256 952 #define HCLGE_TSO_MSS_MAX 9668 953 954 #define HCLGE_TQP_RESET_B 0 955 struct hclge_reset_tqp_queue_cmd { 956 __le16 tqp_id; 957 u8 reset_req; 958 u8 ready_to_reset; 959 u8 rsv[20]; 960 }; 961 962 #define HCLGE_CFG_RESET_MAC_B 3 963 #define HCLGE_CFG_RESET_FUNC_B 7 964 #define HCLGE_CFG_RESET_RCB_B 1 965 struct hclge_reset_cmd { 966 u8 mac_func_reset; 967 u8 fun_reset_vfid; 968 u8 fun_reset_rcb; 969 u8 rsv; 970 __le16 fun_reset_rcb_vqid_start; 971 __le16 fun_reset_rcb_vqid_num; 972 u8 fun_reset_rcb_return_status; 973 u8 rsv1[15]; 974 }; 975 976 #define HCLGE_PF_RESET_DONE_BIT BIT(0) 977 978 struct hclge_pf_rst_done_cmd { 979 u8 pf_rst_done; 980 u8 rsv[23]; 981 }; 982 983 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0) 984 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2) 985 #define HCLGE_CMD_GE_PHY_INNER_LOOP_B BIT(3) 986 #define HCLGE_CMD_COMMON_LB_DONE_B BIT(0) 987 #define HCLGE_CMD_COMMON_LB_SUCCESS_B BIT(1) 988 struct hclge_common_lb_cmd { 989 u8 mask; 990 u8 enable; 991 u8 result; 992 u8 rsv[21]; 993 }; 994 995 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ 996 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ 997 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ 998 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ 999 #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */ 1000 1001 #define HCLGE_TYPE_CRQ 0 1002 #define HCLGE_TYPE_CSQ 1 1003 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 1004 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 1005 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 1006 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 1007 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 1008 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 1009 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c 1010 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 1011 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 1012 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 1013 1014 /* this bit indicates that the driver is ready for hardware reset */ 1015 #define HCLGE_NIC_SW_RST_RDY_B 16 1016 #define HCLGE_NIC_SW_RST_RDY BIT(HCLGE_NIC_SW_RST_RDY_B) 1017 1018 #define HCLGE_NIC_CMQ_DESC_NUM 1024 1019 #define HCLGE_NIC_CMQ_DESC_NUM_S 3 1020 1021 #define HCLGE_LED_LOCATE_STATE_S 0 1022 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) 1023 1024 struct hclge_set_led_state_cmd { 1025 u8 rsv1[3]; 1026 u8 locate_led_config; 1027 u8 rsv2[20]; 1028 }; 1029 1030 struct hclge_get_fd_mode_cmd { 1031 u8 mode; 1032 u8 enable; 1033 u8 rsv[22]; 1034 }; 1035 1036 struct hclge_get_fd_allocation_cmd { 1037 __le32 stage1_entry_num; 1038 __le32 stage2_entry_num; 1039 __le16 stage1_counter_num; 1040 __le16 stage2_counter_num; 1041 u8 rsv[12]; 1042 }; 1043 1044 struct hclge_set_fd_key_config_cmd { 1045 u8 stage; 1046 u8 key_select; 1047 u8 inner_sipv6_word_en; 1048 u8 inner_dipv6_word_en; 1049 u8 outer_sipv6_word_en; 1050 u8 outer_dipv6_word_en; 1051 u8 rsv1[2]; 1052 __le32 tuple_mask; 1053 __le32 meta_data_mask; 1054 u8 rsv2[8]; 1055 }; 1056 1057 #define HCLGE_FD_EPORT_SW_EN_B 0 1058 struct hclge_fd_tcam_config_1_cmd { 1059 u8 stage; 1060 u8 xy_sel; 1061 u8 port_info; 1062 u8 rsv1[1]; 1063 __le32 index; 1064 u8 entry_vld; 1065 u8 rsv2[7]; 1066 u8 tcam_data[8]; 1067 }; 1068 1069 struct hclge_fd_tcam_config_2_cmd { 1070 u8 tcam_data[24]; 1071 }; 1072 1073 struct hclge_fd_tcam_config_3_cmd { 1074 u8 tcam_data[20]; 1075 u8 rsv[4]; 1076 }; 1077 1078 #define HCLGE_FD_AD_DROP_B 0 1079 #define HCLGE_FD_AD_DIRECT_QID_B 1 1080 #define HCLGE_FD_AD_QID_S 2 1081 #define HCLGE_FD_AD_QID_M GENMASK(11, 2) 1082 #define HCLGE_FD_AD_USE_COUNTER_B 12 1083 #define HCLGE_FD_AD_COUNTER_NUM_S 13 1084 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13) 1085 #define HCLGE_FD_AD_NXT_STEP_B 20 1086 #define HCLGE_FD_AD_NXT_KEY_S 21 1087 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(25, 21) 1088 #define HCLGE_FD_AD_WR_RULE_ID_B 0 1089 #define HCLGE_FD_AD_RULE_ID_S 1 1090 #define HCLGE_FD_AD_RULE_ID_M GENMASK(12, 1) 1091 #define HCLGE_FD_AD_TC_OVRD_B 16 1092 #define HCLGE_FD_AD_TC_SIZE_S 17 1093 #define HCLGE_FD_AD_TC_SIZE_M GENMASK(20, 17) 1094 1095 struct hclge_fd_ad_config_cmd { 1096 u8 stage; 1097 u8 rsv1[3]; 1098 __le32 index; 1099 __le64 ad_data; 1100 u8 rsv2[8]; 1101 }; 1102 1103 #define HCLGE_FD_USER_DEF_OFT_S 0 1104 #define HCLGE_FD_USER_DEF_OFT_M GENMASK(14, 0) 1105 #define HCLGE_FD_USER_DEF_EN_B 15 1106 struct hclge_fd_user_def_cfg_cmd { 1107 __le16 ol2_cfg; 1108 __le16 l2_cfg; 1109 __le16 ol3_cfg; 1110 __le16 l3_cfg; 1111 __le16 ol4_cfg; 1112 __le16 l4_cfg; 1113 u8 rsv[12]; 1114 }; 1115 1116 struct hclge_get_imp_bd_cmd { 1117 __le32 bd_num; 1118 u8 rsv[20]; 1119 }; 1120 1121 struct hclge_query_ppu_pf_other_int_dfx_cmd { 1122 __le16 over_8bd_no_fe_qid; 1123 __le16 over_8bd_no_fe_vf_id; 1124 __le16 tso_mss_cmp_min_err_qid; 1125 __le16 tso_mss_cmp_min_err_vf_id; 1126 __le16 tso_mss_cmp_max_err_qid; 1127 __le16 tso_mss_cmp_max_err_vf_id; 1128 __le16 tx_rd_fbd_poison_qid; 1129 __le16 tx_rd_fbd_poison_vf_id; 1130 __le16 rx_rd_fbd_poison_qid; 1131 __le16 rx_rd_fbd_poison_vf_id; 1132 u8 rsv[4]; 1133 }; 1134 1135 #define HCLGE_LINK_EVENT_REPORT_EN_B 0 1136 #define HCLGE_NCSI_ERROR_REPORT_EN_B 1 1137 #define HCLGE_PHY_IMP_EN_B 2 1138 struct hclge_firmware_compat_cmd { 1139 __le32 compat; 1140 u8 rsv[20]; 1141 }; 1142 1143 #define HCLGE_SFP_INFO_CMD_NUM 6 1144 #define HCLGE_SFP_INFO_BD0_LEN 20 1145 #define HCLGE_SFP_INFO_BDX_LEN 24 1146 #define HCLGE_SFP_INFO_MAX_LEN \ 1147 (HCLGE_SFP_INFO_BD0_LEN + \ 1148 (HCLGE_SFP_INFO_CMD_NUM - 1) * HCLGE_SFP_INFO_BDX_LEN) 1149 1150 struct hclge_sfp_info_bd0_cmd { 1151 __le16 offset; 1152 __le16 read_len; 1153 u8 data[HCLGE_SFP_INFO_BD0_LEN]; 1154 }; 1155 1156 #define HCLGE_QUERY_DEV_SPECS_BD_NUM 4 1157 1158 struct hclge_dev_specs_0_cmd { 1159 __le32 rsv0; 1160 __le32 mac_entry_num; 1161 __le32 mng_entry_num; 1162 __le16 rss_ind_tbl_size; 1163 __le16 rss_key_size; 1164 __le16 int_ql_max; 1165 u8 max_non_tso_bd_num; 1166 u8 rsv1; 1167 __le32 max_tm_rate; 1168 }; 1169 1170 #define HCLGE_DEF_MAX_INT_GL 0x1FE0U 1171 1172 struct hclge_dev_specs_1_cmd { 1173 __le16 max_frm_size; 1174 __le16 max_qset_num; 1175 __le16 max_int_gl; 1176 u8 rsv1[18]; 1177 }; 1178 1179 #define HCLGE_PHY_LINK_SETTING_BD_NUM 2 1180 1181 struct hclge_phy_link_ksetting_0_cmd { 1182 __le32 speed; 1183 u8 duplex; 1184 u8 autoneg; 1185 u8 eth_tp_mdix; 1186 u8 eth_tp_mdix_ctrl; 1187 u8 port; 1188 u8 transceiver; 1189 u8 phy_address; 1190 u8 rsv; 1191 __le32 supported; 1192 __le32 advertising; 1193 __le32 lp_advertising; 1194 }; 1195 1196 struct hclge_phy_link_ksetting_1_cmd { 1197 u8 master_slave_cfg; 1198 u8 master_slave_state; 1199 u8 rsv[22]; 1200 }; 1201 1202 struct hclge_phy_reg_cmd { 1203 __le16 reg_addr; 1204 u8 rsv0[2]; 1205 __le16 reg_val; 1206 u8 rsv1[18]; 1207 }; 1208 1209 int hclge_cmd_init(struct hclge_dev *hdev); 1210 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) 1211 { 1212 writel(value, base + reg); 1213 } 1214 1215 #define hclge_write_dev(a, reg, value) \ 1216 hclge_write_reg((a)->io_base, reg, value) 1217 #define hclge_read_dev(a, reg) \ 1218 hclge_read_reg((a)->io_base, reg) 1219 1220 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) 1221 { 1222 u8 __iomem *reg_addr = READ_ONCE(base); 1223 1224 return readl(reg_addr + reg); 1225 } 1226 1227 #define HCLGE_SEND_SYNC(flag) \ 1228 ((flag) & HCLGE_CMD_FLAG_NO_INTR) 1229 1230 struct hclge_hw; 1231 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); 1232 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, 1233 enum hclge_opcode_type opcode, bool is_read); 1234 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); 1235 1236 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, 1237 struct hclge_desc *desc); 1238 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, 1239 struct hclge_desc *desc); 1240 1241 void hclge_cmd_uninit(struct hclge_dev *hdev); 1242 int hclge_cmd_queue_init(struct hclge_dev *hdev); 1243 #endif 1244