1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_CMD_H 5 #define __HCLGE_CMD_H 6 #include <linux/types.h> 7 #include <linux/io.h> 8 9 #define HCLGE_CMDQ_TX_TIMEOUT 30000 10 11 struct hclge_dev; 12 struct hclge_desc { 13 __le16 opcode; 14 15 #define HCLGE_CMDQ_RX_INVLD_B 0 16 #define HCLGE_CMDQ_RX_OUTVLD_B 1 17 18 __le16 flag; 19 __le16 retval; 20 __le16 rsv; 21 __le32 data[6]; 22 }; 23 24 struct hclge_cmq_ring { 25 dma_addr_t desc_dma_addr; 26 struct hclge_desc *desc; 27 struct hclge_dev *dev; 28 u32 head; 29 u32 tail; 30 31 u16 buf_size; 32 u16 desc_num; 33 int next_to_use; 34 int next_to_clean; 35 u8 ring_type; /* cmq ring type */ 36 spinlock_t lock; /* Command queue lock */ 37 }; 38 39 enum hclge_cmd_return_status { 40 HCLGE_CMD_EXEC_SUCCESS = 0, 41 HCLGE_CMD_NO_AUTH = 1, 42 HCLGE_CMD_NOT_EXEC = 2, 43 HCLGE_CMD_QUEUE_FULL = 3, 44 }; 45 46 enum hclge_cmd_status { 47 HCLGE_STATUS_SUCCESS = 0, 48 HCLGE_ERR_CSQ_FULL = -1, 49 HCLGE_ERR_CSQ_TIMEOUT = -2, 50 HCLGE_ERR_CSQ_ERROR = -3, 51 }; 52 53 struct hclge_misc_vector { 54 u8 __iomem *addr; 55 int vector_irq; 56 }; 57 58 struct hclge_cmq { 59 struct hclge_cmq_ring csq; 60 struct hclge_cmq_ring crq; 61 u16 tx_timeout; 62 enum hclge_cmd_status last_status; 63 }; 64 65 #define HCLGE_CMD_FLAG_IN BIT(0) 66 #define HCLGE_CMD_FLAG_OUT BIT(1) 67 #define HCLGE_CMD_FLAG_NEXT BIT(2) 68 #define HCLGE_CMD_FLAG_WR BIT(3) 69 #define HCLGE_CMD_FLAG_NO_INTR BIT(4) 70 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5) 71 72 enum hclge_opcode_type { 73 /* Generic commands */ 74 HCLGE_OPC_QUERY_FW_VER = 0x0001, 75 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, 76 HCLGE_OPC_GBL_RST_STATUS = 0x0021, 77 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, 78 HCLGE_OPC_QUERY_PF_RSRC = 0x0023, 79 HCLGE_OPC_QUERY_VF_RSRC = 0x0024, 80 HCLGE_OPC_GET_CFG_PARAM = 0x0025, 81 82 HCLGE_OPC_STATS_64_BIT = 0x0030, 83 HCLGE_OPC_STATS_32_BIT = 0x0031, 84 HCLGE_OPC_STATS_MAC = 0x0032, 85 86 HCLGE_OPC_QUERY_REG_NUM = 0x0040, 87 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, 88 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, 89 90 /* MAC command */ 91 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, 92 HCLGE_OPC_CONFIG_AN_MODE = 0x0304, 93 HCLGE_OPC_QUERY_AN_RESULT = 0x0306, 94 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, 95 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, 96 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, 97 HCLGE_OPC_SERDES_LOOPBACK = 0x0315, 98 99 /* PFC/Pause commands */ 100 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, 101 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, 102 HCLGE_OPC_CFG_MAC_PARA = 0x0703, 103 HCLGE_OPC_CFG_PFC_PARA = 0x0704, 104 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, 105 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, 106 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, 107 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, 108 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, 109 HCLGE_OPC_QOS_MAP = 0x070A, 110 111 /* ETS/scheduler commands */ 112 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, 113 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, 114 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, 115 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, 116 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, 117 HCLGE_OPC_TM_PG_WEIGHT = 0x0809, 118 HCLGE_OPC_TM_QS_WEIGHT = 0x080A, 119 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, 120 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, 121 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, 122 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, 123 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, 124 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, 125 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, 126 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, 127 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, 128 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, 129 130 /* Packet buffer allocate commands */ 131 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, 132 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, 133 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, 134 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, 135 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, 136 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, 137 138 /* TQP management command */ 139 HCLGE_OPC_SET_TQP_MAP = 0x0A01, 140 141 /* TQP commands */ 142 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, 143 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, 144 HCLGE_OPC_QUERY_TX_STATUS = 0x0B03, 145 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, 146 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, 147 HCLGE_OPC_QUERY_RX_STATUS = 0x0B13, 148 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, 149 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, 150 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 151 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, 152 153 /* TSO command */ 154 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, 155 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10, 156 157 /* RSS commands */ 158 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, 159 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, 160 HCLGE_OPC_RSS_TC_MODE = 0x0D08, 161 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, 162 163 /* Promisuous mode command */ 164 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, 165 166 /* Vlan offload commands */ 167 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, 168 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, 169 170 /* Interrupts commands */ 171 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, 172 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, 173 174 /* MAC commands */ 175 HCLGE_OPC_MAC_VLAN_ADD = 0x1000, 176 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, 177 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, 178 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, 179 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004, 180 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, 181 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, 182 183 /* VLAN commands */ 184 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, 185 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, 186 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, 187 188 /* Flow Director commands */ 189 HCLGE_OPC_FD_MODE_CTRL = 0x1200, 190 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201, 191 HCLGE_OPC_FD_KEY_CONFIG = 0x1202, 192 HCLGE_OPC_FD_TCAM_OP = 0x1203, 193 HCLGE_OPC_FD_AD_OP = 0x1204, 194 195 /* MDIO command */ 196 HCLGE_OPC_MDIO_CONFIG = 0x1900, 197 198 /* QCN commands */ 199 HCLGE_OPC_QCN_MOD_CFG = 0x1A01, 200 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, 201 HCLGE_OPC_QCN_SHAPPING_IR_CFG = 0x1A03, 202 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, 203 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, 204 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, 205 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, 206 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, 207 208 /* Mailbox command */ 209 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, 210 211 /* Led command */ 212 HCLGE_OPC_LED_STATUS_CFG = 0xB000, 213 214 /* Error INT commands */ 215 HCLGE_TM_SCH_ECC_INT_EN = 0x0829, 216 HCLGE_TM_SCH_ECC_ERR_RINT_CMD = 0x082d, 217 HCLGE_TM_SCH_ECC_ERR_RINT_CE = 0x082f, 218 HCLGE_TM_SCH_ECC_ERR_RINT_NFE = 0x0830, 219 HCLGE_TM_SCH_ECC_ERR_RINT_FE = 0x0831, 220 HCLGE_TM_SCH_MBIT_ECC_INFO_CMD = 0x0833, 221 HCLGE_COMMON_ECC_INT_CFG = 0x1505, 222 HCLGE_IGU_EGU_TNL_INT_QUERY = 0x1802, 223 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803, 224 HCLGE_IGU_EGU_TNL_INT_CLR = 0x1804, 225 HCLGE_IGU_COMMON_INT_QUERY = 0x1805, 226 HCLGE_IGU_COMMON_INT_EN = 0x1806, 227 HCLGE_IGU_COMMON_INT_CLR = 0x1807, 228 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14, 229 HCLGE_TM_QCN_MEM_INT_INFO_CMD = 0x1A17, 230 HCLGE_PPP_CMD0_INT_CMD = 0x2100, 231 HCLGE_PPP_CMD1_INT_CMD = 0x2101, 232 HCLGE_NCSI_INT_QUERY = 0x2400, 233 HCLGE_NCSI_INT_EN = 0x2401, 234 HCLGE_NCSI_INT_CLR = 0x2402, 235 }; 236 237 #define HCLGE_TQP_REG_OFFSET 0x80000 238 #define HCLGE_TQP_REG_SIZE 0x200 239 240 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 241 #define HCLGE_RCB_INIT_FLAG_EN_B 0 242 #define HCLGE_RCB_INIT_FLAG_FINI_B 8 243 struct hclge_config_rcb_init_cmd { 244 __le16 rcb_init_flag; 245 u8 rsv[22]; 246 }; 247 248 struct hclge_tqp_map_cmd { 249 __le16 tqp_id; /* Absolute tqp id for in this pf */ 250 u8 tqp_vf; /* VF id */ 251 #define HCLGE_TQP_MAP_TYPE_PF 0 252 #define HCLGE_TQP_MAP_TYPE_VF 1 253 #define HCLGE_TQP_MAP_TYPE_B 0 254 #define HCLGE_TQP_MAP_EN_B 1 255 u8 tqp_flag; /* Indicate it's pf or vf tqp */ 256 __le16 tqp_vid; /* Virtual id in this pf/vf */ 257 u8 rsv[18]; 258 }; 259 260 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 261 262 enum hclge_int_type { 263 HCLGE_INT_TX, 264 HCLGE_INT_RX, 265 HCLGE_INT_EVENT, 266 }; 267 268 struct hclge_ctrl_vector_chain_cmd { 269 u8 int_vector_id; 270 u8 int_cause_num; 271 #define HCLGE_INT_TYPE_S 0 272 #define HCLGE_INT_TYPE_M GENMASK(1, 0) 273 #define HCLGE_TQP_ID_S 2 274 #define HCLGE_TQP_ID_M GENMASK(12, 2) 275 #define HCLGE_INT_GL_IDX_S 13 276 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) 277 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; 278 u8 vfid; 279 u8 rsv; 280 }; 281 282 #define HCLGE_TC_NUM 8 283 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ 284 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ 285 struct hclge_tx_buff_alloc_cmd { 286 __le16 tx_pkt_buff[HCLGE_TC_NUM]; 287 u8 tx_buff_rsv[8]; 288 }; 289 290 struct hclge_rx_priv_buff_cmd { 291 __le16 buf_num[HCLGE_TC_NUM]; 292 __le16 shared_buf; 293 u8 rsv[6]; 294 }; 295 296 struct hclge_query_version_cmd { 297 __le32 firmware; 298 __le32 firmware_rsv[5]; 299 }; 300 301 #define HCLGE_RX_PRIV_EN_B 15 302 #define HCLGE_TC_NUM_ONE_DESC 4 303 struct hclge_priv_wl { 304 __le16 high; 305 __le16 low; 306 }; 307 308 struct hclge_rx_priv_wl_buf { 309 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; 310 }; 311 312 struct hclge_rx_com_thrd { 313 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; 314 }; 315 316 struct hclge_rx_com_wl { 317 struct hclge_priv_wl com_wl; 318 }; 319 320 struct hclge_waterline { 321 u32 low; 322 u32 high; 323 }; 324 325 struct hclge_tc_thrd { 326 u32 low; 327 u32 high; 328 }; 329 330 struct hclge_priv_buf { 331 struct hclge_waterline wl; /* Waterline for low and high*/ 332 u32 buf_size; /* TC private buffer size */ 333 u32 tx_buf_size; 334 u32 enable; /* Enable TC private buffer or not */ 335 }; 336 337 #define HCLGE_MAX_TC_NUM 8 338 struct hclge_shared_buf { 339 struct hclge_waterline self; 340 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; 341 u32 buf_size; 342 }; 343 344 struct hclge_pkt_buf_alloc { 345 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; 346 struct hclge_shared_buf s_buf; 347 }; 348 349 #define HCLGE_RX_COM_WL_EN_B 15 350 struct hclge_rx_com_wl_buf_cmd { 351 __le16 high_wl; 352 __le16 low_wl; 353 u8 rsv[20]; 354 }; 355 356 #define HCLGE_RX_PKT_EN_B 15 357 struct hclge_rx_pkt_buf_cmd { 358 __le16 high_pkt; 359 __le16 low_pkt; 360 u8 rsv[20]; 361 }; 362 363 #define HCLGE_PF_STATE_DONE_B 0 364 #define HCLGE_PF_STATE_MAIN_B 1 365 #define HCLGE_PF_STATE_BOND_B 2 366 #define HCLGE_PF_STATE_MAC_N_B 6 367 #define HCLGE_PF_MAC_NUM_MASK 0x3 368 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) 369 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) 370 struct hclge_func_status_cmd { 371 __le32 vf_rst_state[4]; 372 u8 pf_state; 373 u8 mac_id; 374 u8 rsv1; 375 u8 pf_cnt_in_mac; 376 u8 pf_num; 377 u8 vf_num; 378 u8 rsv[2]; 379 }; 380 381 struct hclge_pf_res_cmd { 382 __le16 tqp_num; 383 __le16 buf_size; 384 __le16 msixcap_localid_ba_nic; 385 __le16 msixcap_localid_ba_rocee; 386 #define HCLGE_MSIX_OFT_ROCEE_S 0 387 #define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0) 388 #define HCLGE_PF_VEC_NUM_S 0 389 #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0) 390 __le16 pf_intr_vector_number; 391 __le16 pf_own_fun_number; 392 __le32 rsv[3]; 393 }; 394 395 #define HCLGE_CFG_OFFSET_S 0 396 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) 397 #define HCLGE_CFG_RD_LEN_S 24 398 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) 399 #define HCLGE_CFG_RD_LEN_BYTES 16 400 #define HCLGE_CFG_RD_LEN_UNIT 4 401 402 #define HCLGE_CFG_VMDQ_S 0 403 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0) 404 #define HCLGE_CFG_TC_NUM_S 8 405 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) 406 #define HCLGE_CFG_TQP_DESC_N_S 16 407 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) 408 #define HCLGE_CFG_PHY_ADDR_S 0 409 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) 410 #define HCLGE_CFG_MEDIA_TP_S 8 411 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) 412 #define HCLGE_CFG_RX_BUF_LEN_S 16 413 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) 414 #define HCLGE_CFG_MAC_ADDR_H_S 0 415 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) 416 #define HCLGE_CFG_DEFAULT_SPEED_S 16 417 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) 418 #define HCLGE_CFG_RSS_SIZE_S 24 419 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) 420 #define HCLGE_CFG_SPEED_ABILITY_S 0 421 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) 422 #define HCLGE_CFG_UMV_TBL_SPACE_S 16 423 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) 424 425 struct hclge_cfg_param_cmd { 426 __le32 offset; 427 __le32 rsv; 428 __le32 param[4]; 429 }; 430 431 #define HCLGE_MAC_MODE 0x0 432 #define HCLGE_DESC_NUM 0x40 433 434 #define HCLGE_ALLOC_VALID_B 0 435 struct hclge_vf_num_cmd { 436 u8 alloc_valid; 437 u8 rsv[23]; 438 }; 439 440 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 441 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 442 #define HCLGE_RSS_HASH_KEY_NUM 16 443 struct hclge_rss_config_cmd { 444 u8 hash_config; 445 u8 rsv[7]; 446 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; 447 }; 448 449 struct hclge_rss_input_tuple_cmd { 450 u8 ipv4_tcp_en; 451 u8 ipv4_udp_en; 452 u8 ipv4_sctp_en; 453 u8 ipv4_fragment_en; 454 u8 ipv6_tcp_en; 455 u8 ipv6_udp_en; 456 u8 ipv6_sctp_en; 457 u8 ipv6_fragment_en; 458 u8 rsv[16]; 459 }; 460 461 #define HCLGE_RSS_CFG_TBL_SIZE 16 462 463 struct hclge_rss_indirection_table_cmd { 464 __le16 start_table_index; 465 __le16 rss_set_bitmap; 466 u8 rsv[4]; 467 u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE]; 468 }; 469 470 #define HCLGE_RSS_TC_OFFSET_S 0 471 #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0) 472 #define HCLGE_RSS_TC_SIZE_S 12 473 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) 474 #define HCLGE_RSS_TC_VALID_B 15 475 struct hclge_rss_tc_mode_cmd { 476 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; 477 u8 rsv[8]; 478 }; 479 480 #define HCLGE_LINK_STATUS_UP_B 0 481 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B) 482 struct hclge_link_status_cmd { 483 u8 status; 484 u8 rsv[23]; 485 }; 486 487 struct hclge_promisc_param { 488 u8 vf_id; 489 u8 enable; 490 }; 491 492 #define HCLGE_PROMISC_TX_EN_B BIT(4) 493 #define HCLGE_PROMISC_RX_EN_B BIT(5) 494 #define HCLGE_PROMISC_EN_B 1 495 #define HCLGE_PROMISC_EN_ALL 0x7 496 #define HCLGE_PROMISC_EN_UC 0x1 497 #define HCLGE_PROMISC_EN_MC 0x2 498 #define HCLGE_PROMISC_EN_BC 0x4 499 struct hclge_promisc_cfg_cmd { 500 u8 flag; 501 u8 vf_id; 502 __le16 rsv0; 503 u8 rsv1[20]; 504 }; 505 506 enum hclge_promisc_type { 507 HCLGE_UNICAST = 1, 508 HCLGE_MULTICAST = 2, 509 HCLGE_BROADCAST = 3, 510 }; 511 512 #define HCLGE_MAC_TX_EN_B 6 513 #define HCLGE_MAC_RX_EN_B 7 514 #define HCLGE_MAC_PAD_TX_B 11 515 #define HCLGE_MAC_PAD_RX_B 12 516 #define HCLGE_MAC_1588_TX_B 13 517 #define HCLGE_MAC_1588_RX_B 14 518 #define HCLGE_MAC_APP_LP_B 15 519 #define HCLGE_MAC_LINE_LP_B 16 520 #define HCLGE_MAC_FCS_TX_B 17 521 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 522 #define HCLGE_MAC_RX_FCS_STRIP_B 19 523 #define HCLGE_MAC_RX_FCS_B 20 524 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 525 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 526 527 struct hclge_config_mac_mode_cmd { 528 __le32 txrx_pad_fcs_loop_en; 529 u8 rsv[20]; 530 }; 531 532 #define HCLGE_CFG_SPEED_S 0 533 #define HCLGE_CFG_SPEED_M GENMASK(5, 0) 534 535 #define HCLGE_CFG_DUPLEX_B 7 536 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) 537 538 struct hclge_config_mac_speed_dup_cmd { 539 u8 speed_dup; 540 541 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 542 u8 mac_change_fec_en; 543 u8 rsv[22]; 544 }; 545 546 #define HCLGE_QUERY_SPEED_S 3 547 #define HCLGE_QUERY_AN_B 0 548 #define HCLGE_QUERY_DUPLEX_B 2 549 550 #define HCLGE_QUERY_SPEED_M GENMASK(4, 0) 551 #define HCLGE_QUERY_AN_M BIT(HCLGE_QUERY_AN_B) 552 #define HCLGE_QUERY_DUPLEX_M BIT(HCLGE_QUERY_DUPLEX_B) 553 554 struct hclge_query_an_speed_dup_cmd { 555 u8 an_syn_dup_speed; 556 u8 pause; 557 u8 rsv[23]; 558 }; 559 560 #define HCLGE_RING_ID_MASK GENMASK(9, 0) 561 #define HCLGE_TQP_ENABLE_B 0 562 563 #define HCLGE_MAC_CFG_AN_EN_B 0 564 #define HCLGE_MAC_CFG_AN_INT_EN_B 1 565 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 566 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 567 #define HCLGE_MAC_CFG_AN_RST_B 4 568 569 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) 570 571 struct hclge_config_auto_neg_cmd { 572 __le32 cfg_an_cmd_flag; 573 u8 rsv[20]; 574 }; 575 576 #define HCLGE_MAC_UPLINK_PORT 0x100 577 578 struct hclge_config_max_frm_size_cmd { 579 __le16 max_frm_size; 580 u8 min_frm_size; 581 u8 rsv[21]; 582 }; 583 584 enum hclge_mac_vlan_tbl_opcode { 585 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ 586 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ 587 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ 588 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ 589 }; 590 591 #define HCLGE_MAC_VLAN_BIT0_EN_B 0 592 #define HCLGE_MAC_VLAN_BIT1_EN_B 1 593 #define HCLGE_MAC_EPORT_SW_EN_B 12 594 #define HCLGE_MAC_EPORT_TYPE_B 11 595 #define HCLGE_MAC_EPORT_VFID_S 3 596 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) 597 #define HCLGE_MAC_EPORT_PFID_S 0 598 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) 599 struct hclge_mac_vlan_tbl_entry_cmd { 600 u8 flags; 601 u8 resp_code; 602 __le16 vlan_tag; 603 __le32 mac_addr_hi32; 604 __le16 mac_addr_lo16; 605 __le16 rsv1; 606 u8 entry_type; 607 u8 mc_mac_en; 608 __le16 egress_port; 609 __le16 egress_queue; 610 u8 rsv2[6]; 611 }; 612 613 #define HCLGE_UMV_SPC_ALC_B 0 614 struct hclge_umv_spc_alc_cmd { 615 u8 allocate; 616 u8 rsv1[3]; 617 __le32 space_size; 618 u8 rsv2[16]; 619 }; 620 621 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) 622 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) 623 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) 624 #define HCLGE_MAC_ETHERTYPE_LLDP 0x88cc 625 626 struct hclge_mac_mgr_tbl_entry_cmd { 627 u8 flags; 628 u8 resp_code; 629 __le16 vlan_tag; 630 __le32 mac_addr_hi32; 631 __le16 mac_addr_lo16; 632 __le16 rsv1; 633 __le16 ethter_type; 634 __le16 egress_port; 635 __le16 egress_queue; 636 u8 sw_port_id_aware; 637 u8 rsv2; 638 u8 i_port_bitmap; 639 u8 i_port_direction; 640 u8 rsv3[2]; 641 }; 642 643 struct hclge_mac_vlan_add_cmd { 644 __le16 flags; 645 __le16 mac_addr_hi16; 646 __le32 mac_addr_lo32; 647 __le32 mac_addr_msk_hi32; 648 __le16 mac_addr_msk_lo16; 649 __le16 vlan_tag; 650 __le16 ingress_port; 651 __le16 egress_port; 652 u8 rsv[4]; 653 }; 654 655 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0 656 struct hclge_mac_vlan_remove_cmd { 657 __le16 flags; 658 __le16 mac_addr_hi16; 659 __le32 mac_addr_lo32; 660 __le32 mac_addr_msk_hi32; 661 __le16 mac_addr_msk_lo16; 662 __le16 vlan_tag; 663 __le16 ingress_port; 664 __le16 egress_port; 665 u8 rsv[4]; 666 }; 667 668 struct hclge_vlan_filter_ctrl_cmd { 669 u8 vlan_type; 670 u8 vlan_fe; 671 u8 rsv[22]; 672 }; 673 674 struct hclge_vlan_filter_pf_cfg_cmd { 675 u8 vlan_offset; 676 u8 vlan_cfg; 677 u8 rsv[2]; 678 u8 vlan_offset_bitmap[20]; 679 }; 680 681 struct hclge_vlan_filter_vf_cfg_cmd { 682 __le16 vlan_id; 683 u8 resp_code; 684 u8 rsv; 685 u8 vlan_cfg; 686 u8 rsv1[3]; 687 u8 vf_bitmap[16]; 688 }; 689 690 #define HCLGE_ACCEPT_TAG1_B 0 691 #define HCLGE_ACCEPT_UNTAG1_B 1 692 #define HCLGE_PORT_INS_TAG1_EN_B 2 693 #define HCLGE_PORT_INS_TAG2_EN_B 3 694 #define HCLGE_CFG_NIC_ROCE_SEL_B 4 695 #define HCLGE_ACCEPT_TAG2_B 5 696 #define HCLGE_ACCEPT_UNTAG2_B 6 697 698 struct hclge_vport_vtag_tx_cfg_cmd { 699 u8 vport_vlan_cfg; 700 u8 vf_offset; 701 u8 rsv1[2]; 702 __le16 def_vlan_tag1; 703 __le16 def_vlan_tag2; 704 u8 vf_bitmap[8]; 705 u8 rsv2[8]; 706 }; 707 708 #define HCLGE_REM_TAG1_EN_B 0 709 #define HCLGE_REM_TAG2_EN_B 1 710 #define HCLGE_SHOW_TAG1_EN_B 2 711 #define HCLGE_SHOW_TAG2_EN_B 3 712 struct hclge_vport_vtag_rx_cfg_cmd { 713 u8 vport_vlan_cfg; 714 u8 vf_offset; 715 u8 rsv1[6]; 716 u8 vf_bitmap[8]; 717 u8 rsv2[8]; 718 }; 719 720 struct hclge_tx_vlan_type_cfg_cmd { 721 __le16 ot_vlan_type; 722 __le16 in_vlan_type; 723 u8 rsv[20]; 724 }; 725 726 struct hclge_rx_vlan_type_cfg_cmd { 727 __le16 ot_fst_vlan_type; 728 __le16 ot_sec_vlan_type; 729 __le16 in_fst_vlan_type; 730 __le16 in_sec_vlan_type; 731 u8 rsv[16]; 732 }; 733 734 struct hclge_cfg_com_tqp_queue_cmd { 735 __le16 tqp_id; 736 __le16 stream_id; 737 u8 enable; 738 u8 rsv[19]; 739 }; 740 741 struct hclge_cfg_tx_queue_pointer_cmd { 742 __le16 tqp_id; 743 __le16 tx_tail; 744 __le16 tx_head; 745 __le16 fbd_num; 746 __le16 ring_offset; 747 u8 rsv[14]; 748 }; 749 750 #define HCLGE_TSO_MSS_MIN_S 0 751 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) 752 753 #define HCLGE_TSO_MSS_MAX_S 16 754 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) 755 756 struct hclge_cfg_tso_status_cmd { 757 __le16 tso_mss_min; 758 __le16 tso_mss_max; 759 u8 rsv[20]; 760 }; 761 762 #define HCLGE_GRO_EN_B 0 763 struct hclge_cfg_gro_status_cmd { 764 __le16 gro_en; 765 u8 rsv[22]; 766 }; 767 768 #define HCLGE_TSO_MSS_MIN 256 769 #define HCLGE_TSO_MSS_MAX 9668 770 771 #define HCLGE_TQP_RESET_B 0 772 struct hclge_reset_tqp_queue_cmd { 773 __le16 tqp_id; 774 u8 reset_req; 775 u8 ready_to_reset; 776 u8 rsv[20]; 777 }; 778 779 #define HCLGE_CFG_RESET_MAC_B 3 780 #define HCLGE_CFG_RESET_FUNC_B 7 781 struct hclge_reset_cmd { 782 u8 mac_func_reset; 783 u8 fun_reset_vfid; 784 u8 rsv[22]; 785 }; 786 787 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0) 788 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2) 789 #define HCLGE_CMD_SERDES_DONE_B BIT(0) 790 #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1) 791 struct hclge_serdes_lb_cmd { 792 u8 mask; 793 u8 enable; 794 u8 result; 795 u8 rsv[21]; 796 }; 797 798 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ 799 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ 800 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ 801 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ 802 803 #define HCLGE_TYPE_CRQ 0 804 #define HCLGE_TYPE_CSQ 1 805 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 806 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 807 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 808 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 809 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 810 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 811 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c 812 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 813 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 814 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 815 #define HCLGE_NIC_CMQ_EN_B 16 816 #define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B) 817 #define HCLGE_NIC_CMQ_DESC_NUM 1024 818 #define HCLGE_NIC_CMQ_DESC_NUM_S 3 819 820 #define HCLGE_LED_LOCATE_STATE_S 0 821 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) 822 823 struct hclge_set_led_state_cmd { 824 u8 rsv1[3]; 825 u8 locate_led_config; 826 u8 rsv2[20]; 827 }; 828 829 struct hclge_get_fd_mode_cmd { 830 u8 mode; 831 u8 enable; 832 u8 rsv[22]; 833 }; 834 835 struct hclge_get_fd_allocation_cmd { 836 __le32 stage1_entry_num; 837 __le32 stage2_entry_num; 838 __le16 stage1_counter_num; 839 __le16 stage2_counter_num; 840 u8 rsv[12]; 841 }; 842 843 struct hclge_set_fd_key_config_cmd { 844 u8 stage; 845 u8 key_select; 846 u8 inner_sipv6_word_en; 847 u8 inner_dipv6_word_en; 848 u8 outer_sipv6_word_en; 849 u8 outer_dipv6_word_en; 850 u8 rsv1[2]; 851 __le32 tuple_mask; 852 __le32 meta_data_mask; 853 u8 rsv2[8]; 854 }; 855 856 #define HCLGE_FD_EPORT_SW_EN_B 0 857 struct hclge_fd_tcam_config_1_cmd { 858 u8 stage; 859 u8 xy_sel; 860 u8 port_info; 861 u8 rsv1[1]; 862 __le32 index; 863 u8 entry_vld; 864 u8 rsv2[7]; 865 u8 tcam_data[8]; 866 }; 867 868 struct hclge_fd_tcam_config_2_cmd { 869 u8 tcam_data[24]; 870 }; 871 872 struct hclge_fd_tcam_config_3_cmd { 873 u8 tcam_data[20]; 874 u8 rsv[4]; 875 }; 876 877 #define HCLGE_FD_AD_DROP_B 0 878 #define HCLGE_FD_AD_DIRECT_QID_B 1 879 #define HCLGE_FD_AD_QID_S 2 880 #define HCLGE_FD_AD_QID_M GENMASK(12, 2) 881 #define HCLGE_FD_AD_USE_COUNTER_B 12 882 #define HCLGE_FD_AD_COUNTER_NUM_S 13 883 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13) 884 #define HCLGE_FD_AD_NXT_STEP_B 20 885 #define HCLGE_FD_AD_NXT_KEY_S 21 886 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21) 887 #define HCLGE_FD_AD_WR_RULE_ID_B 0 888 #define HCLGE_FD_AD_RULE_ID_S 1 889 #define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1) 890 891 struct hclge_fd_ad_config_cmd { 892 u8 stage; 893 u8 rsv1[3]; 894 __le32 index; 895 __le64 ad_data; 896 u8 rsv2[8]; 897 }; 898 899 int hclge_cmd_init(struct hclge_dev *hdev); 900 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) 901 { 902 writel(value, base + reg); 903 } 904 905 #define hclge_write_dev(a, reg, value) \ 906 hclge_write_reg((a)->io_base, (reg), (value)) 907 #define hclge_read_dev(a, reg) \ 908 hclge_read_reg((a)->io_base, (reg)) 909 910 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) 911 { 912 u8 __iomem *reg_addr = READ_ONCE(base); 913 914 return readl(reg_addr + reg); 915 } 916 917 #define HCLGE_SEND_SYNC(flag) \ 918 ((flag) & HCLGE_CMD_FLAG_NO_INTR) 919 920 struct hclge_hw; 921 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); 922 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, 923 enum hclge_opcode_type opcode, bool is_read); 924 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); 925 926 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, 927 struct hclge_promisc_param *param); 928 929 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, 930 struct hclge_desc *desc); 931 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, 932 struct hclge_desc *desc); 933 934 void hclge_destroy_cmd_queue(struct hclge_hw *hw); 935 int hclge_cmd_queue_init(struct hclge_dev *hdev); 936 #endif 937