1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_CMD_H 5 #define __HCLGE_CMD_H 6 #include <linux/types.h> 7 #include <linux/io.h> 8 9 #define HCLGE_CMDQ_TX_TIMEOUT 30000 10 11 struct hclge_dev; 12 struct hclge_desc { 13 __le16 opcode; 14 15 #define HCLGE_CMDQ_RX_INVLD_B 0 16 #define HCLGE_CMDQ_RX_OUTVLD_B 1 17 18 __le16 flag; 19 __le16 retval; 20 __le16 rsv; 21 __le32 data[6]; 22 }; 23 24 struct hclge_cmq_ring { 25 dma_addr_t desc_dma_addr; 26 struct hclge_desc *desc; 27 struct hclge_dev *dev; 28 u32 head; 29 u32 tail; 30 31 u16 buf_size; 32 u16 desc_num; 33 int next_to_use; 34 int next_to_clean; 35 u8 ring_type; /* cmq ring type */ 36 spinlock_t lock; /* Command queue lock */ 37 }; 38 39 enum hclge_cmd_return_status { 40 HCLGE_CMD_EXEC_SUCCESS = 0, 41 HCLGE_CMD_NO_AUTH = 1, 42 HCLGE_CMD_NOT_SUPPORTED = 2, 43 HCLGE_CMD_QUEUE_FULL = 3, 44 }; 45 46 enum hclge_cmd_status { 47 HCLGE_STATUS_SUCCESS = 0, 48 HCLGE_ERR_CSQ_FULL = -1, 49 HCLGE_ERR_CSQ_TIMEOUT = -2, 50 HCLGE_ERR_CSQ_ERROR = -3, 51 }; 52 53 struct hclge_misc_vector { 54 u8 __iomem *addr; 55 int vector_irq; 56 }; 57 58 struct hclge_cmq { 59 struct hclge_cmq_ring csq; 60 struct hclge_cmq_ring crq; 61 u16 tx_timeout; 62 enum hclge_cmd_status last_status; 63 }; 64 65 #define HCLGE_CMD_FLAG_IN BIT(0) 66 #define HCLGE_CMD_FLAG_OUT BIT(1) 67 #define HCLGE_CMD_FLAG_NEXT BIT(2) 68 #define HCLGE_CMD_FLAG_WR BIT(3) 69 #define HCLGE_CMD_FLAG_NO_INTR BIT(4) 70 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5) 71 72 enum hclge_opcode_type { 73 /* Generic commands */ 74 HCLGE_OPC_QUERY_FW_VER = 0x0001, 75 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, 76 HCLGE_OPC_GBL_RST_STATUS = 0x0021, 77 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, 78 HCLGE_OPC_QUERY_PF_RSRC = 0x0023, 79 HCLGE_OPC_QUERY_VF_RSRC = 0x0024, 80 HCLGE_OPC_GET_CFG_PARAM = 0x0025, 81 82 HCLGE_OPC_STATS_64_BIT = 0x0030, 83 HCLGE_OPC_STATS_32_BIT = 0x0031, 84 HCLGE_OPC_STATS_MAC = 0x0032, 85 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033, 86 HCLGE_OPC_STATS_MAC_ALL = 0x0034, 87 88 HCLGE_OPC_QUERY_REG_NUM = 0x0040, 89 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, 90 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, 91 HCLGE_OPC_DFX_BD_NUM = 0x0043, 92 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044, 93 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045, 94 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046, 95 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047, 96 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048, 97 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049, 98 HCLGE_OPC_DFX_NCSI_REG = 0x004A, 99 HCLGE_OPC_DFX_RTC_REG = 0x004B, 100 HCLGE_OPC_DFX_PPP_REG = 0x004C, 101 HCLGE_OPC_DFX_RCB_REG = 0x004D, 102 HCLGE_OPC_DFX_TQP_REG = 0x004E, 103 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F, 104 HCLGE_OPC_DFX_QUERY_CHIP_CAP = 0x0050, 105 106 /* MAC command */ 107 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, 108 HCLGE_OPC_CONFIG_AN_MODE = 0x0304, 109 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, 110 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, 111 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, 112 HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310, 113 HCLGE_OPC_MAC_TNL_INT_EN = 0x0311, 114 HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312, 115 HCLGE_OPC_SERDES_LOOPBACK = 0x0315, 116 117 /* PFC/Pause commands */ 118 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, 119 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, 120 HCLGE_OPC_CFG_MAC_PARA = 0x0703, 121 HCLGE_OPC_CFG_PFC_PARA = 0x0704, 122 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, 123 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, 124 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, 125 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, 126 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, 127 HCLGE_OPC_QOS_MAP = 0x070A, 128 129 /* ETS/scheduler commands */ 130 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, 131 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, 132 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, 133 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, 134 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, 135 HCLGE_OPC_TM_PG_WEIGHT = 0x0809, 136 HCLGE_OPC_TM_QS_WEIGHT = 0x080A, 137 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, 138 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, 139 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, 140 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, 141 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, 142 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, 143 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, 144 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, 145 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, 146 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, 147 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843, 148 HCLGE_OPC_QSET_DFX_STS = 0x0844, 149 HCLGE_OPC_PRI_DFX_STS = 0x0845, 150 HCLGE_OPC_PG_DFX_STS = 0x0846, 151 HCLGE_OPC_PORT_DFX_STS = 0x0847, 152 HCLGE_OPC_SCH_NQ_CNT = 0x0848, 153 HCLGE_OPC_SCH_RQ_CNT = 0x0849, 154 HCLGE_OPC_TM_INTERNAL_STS = 0x0850, 155 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851, 156 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852, 157 158 /* Packet buffer allocate commands */ 159 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, 160 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, 161 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, 162 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, 163 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, 164 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, 165 166 /* TQP management command */ 167 HCLGE_OPC_SET_TQP_MAP = 0x0A01, 168 169 /* TQP commands */ 170 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, 171 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, 172 HCLGE_OPC_QUERY_TX_STATUS = 0x0B03, 173 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04, 174 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, 175 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, 176 HCLGE_OPC_QUERY_RX_STATUS = 0x0B13, 177 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, 178 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, 179 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 180 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, 181 182 /* TSO command */ 183 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, 184 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10, 185 186 /* RSS commands */ 187 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, 188 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, 189 HCLGE_OPC_RSS_TC_MODE = 0x0D08, 190 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, 191 192 /* Promisuous mode command */ 193 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, 194 195 /* Vlan offload commands */ 196 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, 197 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, 198 199 /* Interrupts commands */ 200 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, 201 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, 202 203 /* MAC commands */ 204 HCLGE_OPC_MAC_VLAN_ADD = 0x1000, 205 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, 206 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, 207 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, 208 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004, 209 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, 210 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, 211 212 /* VLAN commands */ 213 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, 214 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, 215 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, 216 217 /* Flow Director commands */ 218 HCLGE_OPC_FD_MODE_CTRL = 0x1200, 219 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201, 220 HCLGE_OPC_FD_KEY_CONFIG = 0x1202, 221 HCLGE_OPC_FD_TCAM_OP = 0x1203, 222 HCLGE_OPC_FD_AD_OP = 0x1204, 223 224 /* MDIO command */ 225 HCLGE_OPC_MDIO_CONFIG = 0x1900, 226 227 /* QCN commands */ 228 HCLGE_OPC_QCN_MOD_CFG = 0x1A01, 229 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, 230 HCLGE_OPC_QCN_SHAPPING_IR_CFG = 0x1A03, 231 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, 232 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, 233 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, 234 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, 235 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, 236 237 /* Mailbox command */ 238 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, 239 240 /* Led command */ 241 HCLGE_OPC_LED_STATUS_CFG = 0xB000, 242 243 /* NCL config command */ 244 HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011, 245 246 /* SFP command */ 247 HCLGE_OPC_SFP_GET_SPEED = 0x7104, 248 249 /* Error INT commands */ 250 HCLGE_MAC_COMMON_INT_EN = 0x030E, 251 HCLGE_TM_SCH_ECC_INT_EN = 0x0829, 252 HCLGE_SSU_ECC_INT_CMD = 0x0989, 253 HCLGE_SSU_COMMON_INT_CMD = 0x098C, 254 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40, 255 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41, 256 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42, 257 HCLGE_COMMON_ECC_INT_CFG = 0x1505, 258 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510, 259 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511, 260 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512, 261 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513, 262 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514, 263 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515, 264 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580, 265 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581, 266 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584, 267 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803, 268 HCLGE_IGU_COMMON_INT_EN = 0x1806, 269 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14, 270 HCLGE_PPP_CMD0_INT_CMD = 0x2100, 271 HCLGE_PPP_CMD1_INT_CMD = 0x2101, 272 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105, 273 HCLGE_NCSI_INT_EN = 0x2401, 274 }; 275 276 #define HCLGE_TQP_REG_OFFSET 0x80000 277 #define HCLGE_TQP_REG_SIZE 0x200 278 279 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 280 #define HCLGE_RCB_INIT_FLAG_EN_B 0 281 #define HCLGE_RCB_INIT_FLAG_FINI_B 8 282 struct hclge_config_rcb_init_cmd { 283 __le16 rcb_init_flag; 284 u8 rsv[22]; 285 }; 286 287 struct hclge_tqp_map_cmd { 288 __le16 tqp_id; /* Absolute tqp id for in this pf */ 289 u8 tqp_vf; /* VF id */ 290 #define HCLGE_TQP_MAP_TYPE_PF 0 291 #define HCLGE_TQP_MAP_TYPE_VF 1 292 #define HCLGE_TQP_MAP_TYPE_B 0 293 #define HCLGE_TQP_MAP_EN_B 1 294 u8 tqp_flag; /* Indicate it's pf or vf tqp */ 295 __le16 tqp_vid; /* Virtual id in this pf/vf */ 296 u8 rsv[18]; 297 }; 298 299 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 300 301 enum hclge_int_type { 302 HCLGE_INT_TX, 303 HCLGE_INT_RX, 304 HCLGE_INT_EVENT, 305 }; 306 307 struct hclge_ctrl_vector_chain_cmd { 308 u8 int_vector_id; 309 u8 int_cause_num; 310 #define HCLGE_INT_TYPE_S 0 311 #define HCLGE_INT_TYPE_M GENMASK(1, 0) 312 #define HCLGE_TQP_ID_S 2 313 #define HCLGE_TQP_ID_M GENMASK(12, 2) 314 #define HCLGE_INT_GL_IDX_S 13 315 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) 316 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; 317 u8 vfid; 318 u8 rsv; 319 }; 320 321 #define HCLGE_MAX_TC_NUM 8 322 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ 323 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ 324 struct hclge_tx_buff_alloc_cmd { 325 __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM]; 326 u8 tx_buff_rsv[8]; 327 }; 328 329 struct hclge_rx_priv_buff_cmd { 330 __le16 buf_num[HCLGE_MAX_TC_NUM]; 331 __le16 shared_buf; 332 u8 rsv[6]; 333 }; 334 335 struct hclge_query_version_cmd { 336 __le32 firmware; 337 __le32 firmware_rsv[5]; 338 }; 339 340 #define HCLGE_RX_PRIV_EN_B 15 341 #define HCLGE_TC_NUM_ONE_DESC 4 342 struct hclge_priv_wl { 343 __le16 high; 344 __le16 low; 345 }; 346 347 struct hclge_rx_priv_wl_buf { 348 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; 349 }; 350 351 struct hclge_rx_com_thrd { 352 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; 353 }; 354 355 struct hclge_rx_com_wl { 356 struct hclge_priv_wl com_wl; 357 }; 358 359 struct hclge_waterline { 360 u32 low; 361 u32 high; 362 }; 363 364 struct hclge_tc_thrd { 365 u32 low; 366 u32 high; 367 }; 368 369 struct hclge_priv_buf { 370 struct hclge_waterline wl; /* Waterline for low and high*/ 371 u32 buf_size; /* TC private buffer size */ 372 u32 tx_buf_size; 373 u32 enable; /* Enable TC private buffer or not */ 374 }; 375 376 struct hclge_shared_buf { 377 struct hclge_waterline self; 378 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; 379 u32 buf_size; 380 }; 381 382 struct hclge_pkt_buf_alloc { 383 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; 384 struct hclge_shared_buf s_buf; 385 }; 386 387 #define HCLGE_RX_COM_WL_EN_B 15 388 struct hclge_rx_com_wl_buf_cmd { 389 __le16 high_wl; 390 __le16 low_wl; 391 u8 rsv[20]; 392 }; 393 394 #define HCLGE_RX_PKT_EN_B 15 395 struct hclge_rx_pkt_buf_cmd { 396 __le16 high_pkt; 397 __le16 low_pkt; 398 u8 rsv[20]; 399 }; 400 401 #define HCLGE_PF_STATE_DONE_B 0 402 #define HCLGE_PF_STATE_MAIN_B 1 403 #define HCLGE_PF_STATE_BOND_B 2 404 #define HCLGE_PF_STATE_MAC_N_B 6 405 #define HCLGE_PF_MAC_NUM_MASK 0x3 406 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) 407 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) 408 struct hclge_func_status_cmd { 409 __le32 vf_rst_state[4]; 410 u8 pf_state; 411 u8 mac_id; 412 u8 rsv1; 413 u8 pf_cnt_in_mac; 414 u8 pf_num; 415 u8 vf_num; 416 u8 rsv[2]; 417 }; 418 419 struct hclge_pf_res_cmd { 420 __le16 tqp_num; 421 __le16 buf_size; 422 __le16 msixcap_localid_ba_nic; 423 __le16 msixcap_localid_ba_rocee; 424 #define HCLGE_MSIX_OFT_ROCEE_S 0 425 #define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0) 426 #define HCLGE_PF_VEC_NUM_S 0 427 #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0) 428 __le16 pf_intr_vector_number; 429 __le16 pf_own_fun_number; 430 __le16 tx_buf_size; 431 __le16 dv_buf_size; 432 __le32 rsv[2]; 433 }; 434 435 #define HCLGE_CFG_OFFSET_S 0 436 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) 437 #define HCLGE_CFG_RD_LEN_S 24 438 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) 439 #define HCLGE_CFG_RD_LEN_BYTES 16 440 #define HCLGE_CFG_RD_LEN_UNIT 4 441 442 #define HCLGE_CFG_VMDQ_S 0 443 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0) 444 #define HCLGE_CFG_TC_NUM_S 8 445 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) 446 #define HCLGE_CFG_TQP_DESC_N_S 16 447 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) 448 #define HCLGE_CFG_PHY_ADDR_S 0 449 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) 450 #define HCLGE_CFG_MEDIA_TP_S 8 451 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) 452 #define HCLGE_CFG_RX_BUF_LEN_S 16 453 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) 454 #define HCLGE_CFG_MAC_ADDR_H_S 0 455 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) 456 #define HCLGE_CFG_DEFAULT_SPEED_S 16 457 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) 458 #define HCLGE_CFG_RSS_SIZE_S 24 459 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) 460 #define HCLGE_CFG_SPEED_ABILITY_S 0 461 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) 462 #define HCLGE_CFG_UMV_TBL_SPACE_S 16 463 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) 464 465 struct hclge_cfg_param_cmd { 466 __le32 offset; 467 __le32 rsv; 468 __le32 param[4]; 469 }; 470 471 #define HCLGE_MAC_MODE 0x0 472 #define HCLGE_DESC_NUM 0x40 473 474 #define HCLGE_ALLOC_VALID_B 0 475 struct hclge_vf_num_cmd { 476 u8 alloc_valid; 477 u8 rsv[23]; 478 }; 479 480 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 481 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 482 #define HCLGE_RSS_HASH_KEY_NUM 16 483 struct hclge_rss_config_cmd { 484 u8 hash_config; 485 u8 rsv[7]; 486 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; 487 }; 488 489 struct hclge_rss_input_tuple_cmd { 490 u8 ipv4_tcp_en; 491 u8 ipv4_udp_en; 492 u8 ipv4_sctp_en; 493 u8 ipv4_fragment_en; 494 u8 ipv6_tcp_en; 495 u8 ipv6_udp_en; 496 u8 ipv6_sctp_en; 497 u8 ipv6_fragment_en; 498 u8 rsv[16]; 499 }; 500 501 #define HCLGE_RSS_CFG_TBL_SIZE 16 502 503 struct hclge_rss_indirection_table_cmd { 504 __le16 start_table_index; 505 __le16 rss_set_bitmap; 506 u8 rsv[4]; 507 u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE]; 508 }; 509 510 #define HCLGE_RSS_TC_OFFSET_S 0 511 #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0) 512 #define HCLGE_RSS_TC_SIZE_S 12 513 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) 514 #define HCLGE_RSS_TC_VALID_B 15 515 struct hclge_rss_tc_mode_cmd { 516 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; 517 u8 rsv[8]; 518 }; 519 520 #define HCLGE_LINK_STATUS_UP_B 0 521 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B) 522 struct hclge_link_status_cmd { 523 u8 status; 524 u8 rsv[23]; 525 }; 526 527 struct hclge_promisc_param { 528 u8 vf_id; 529 u8 enable; 530 }; 531 532 #define HCLGE_PROMISC_TX_EN_B BIT(4) 533 #define HCLGE_PROMISC_RX_EN_B BIT(5) 534 #define HCLGE_PROMISC_EN_B 1 535 #define HCLGE_PROMISC_EN_ALL 0x7 536 #define HCLGE_PROMISC_EN_UC 0x1 537 #define HCLGE_PROMISC_EN_MC 0x2 538 #define HCLGE_PROMISC_EN_BC 0x4 539 struct hclge_promisc_cfg_cmd { 540 u8 flag; 541 u8 vf_id; 542 __le16 rsv0; 543 u8 rsv1[20]; 544 }; 545 546 enum hclge_promisc_type { 547 HCLGE_UNICAST = 1, 548 HCLGE_MULTICAST = 2, 549 HCLGE_BROADCAST = 3, 550 }; 551 552 #define HCLGE_MAC_TX_EN_B 6 553 #define HCLGE_MAC_RX_EN_B 7 554 #define HCLGE_MAC_PAD_TX_B 11 555 #define HCLGE_MAC_PAD_RX_B 12 556 #define HCLGE_MAC_1588_TX_B 13 557 #define HCLGE_MAC_1588_RX_B 14 558 #define HCLGE_MAC_APP_LP_B 15 559 #define HCLGE_MAC_LINE_LP_B 16 560 #define HCLGE_MAC_FCS_TX_B 17 561 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 562 #define HCLGE_MAC_RX_FCS_STRIP_B 19 563 #define HCLGE_MAC_RX_FCS_B 20 564 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 565 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 566 567 struct hclge_config_mac_mode_cmd { 568 __le32 txrx_pad_fcs_loop_en; 569 u8 rsv[20]; 570 }; 571 572 #define HCLGE_CFG_SPEED_S 0 573 #define HCLGE_CFG_SPEED_M GENMASK(5, 0) 574 575 #define HCLGE_CFG_DUPLEX_B 7 576 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) 577 578 struct hclge_config_mac_speed_dup_cmd { 579 u8 speed_dup; 580 581 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 582 u8 mac_change_fec_en; 583 u8 rsv[22]; 584 }; 585 586 #define HCLGE_RING_ID_MASK GENMASK(9, 0) 587 #define HCLGE_TQP_ENABLE_B 0 588 589 #define HCLGE_MAC_CFG_AN_EN_B 0 590 #define HCLGE_MAC_CFG_AN_INT_EN_B 1 591 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 592 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 593 #define HCLGE_MAC_CFG_AN_RST_B 4 594 595 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) 596 597 struct hclge_config_auto_neg_cmd { 598 __le32 cfg_an_cmd_flag; 599 u8 rsv[20]; 600 }; 601 602 struct hclge_sfp_speed_cmd { 603 __le32 sfp_speed; 604 u32 rsv[5]; 605 }; 606 607 #define HCLGE_MAC_UPLINK_PORT 0x100 608 609 struct hclge_config_max_frm_size_cmd { 610 __le16 max_frm_size; 611 u8 min_frm_size; 612 u8 rsv[21]; 613 }; 614 615 enum hclge_mac_vlan_tbl_opcode { 616 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ 617 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ 618 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ 619 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ 620 }; 621 622 #define HCLGE_MAC_VLAN_BIT0_EN_B 0 623 #define HCLGE_MAC_VLAN_BIT1_EN_B 1 624 #define HCLGE_MAC_EPORT_SW_EN_B 12 625 #define HCLGE_MAC_EPORT_TYPE_B 11 626 #define HCLGE_MAC_EPORT_VFID_S 3 627 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) 628 #define HCLGE_MAC_EPORT_PFID_S 0 629 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) 630 struct hclge_mac_vlan_tbl_entry_cmd { 631 u8 flags; 632 u8 resp_code; 633 __le16 vlan_tag; 634 __le32 mac_addr_hi32; 635 __le16 mac_addr_lo16; 636 __le16 rsv1; 637 u8 entry_type; 638 u8 mc_mac_en; 639 __le16 egress_port; 640 __le16 egress_queue; 641 u8 rsv2[6]; 642 }; 643 644 #define HCLGE_UMV_SPC_ALC_B 0 645 struct hclge_umv_spc_alc_cmd { 646 u8 allocate; 647 u8 rsv1[3]; 648 __le32 space_size; 649 u8 rsv2[16]; 650 }; 651 652 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) 653 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) 654 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) 655 #define HCLGE_MAC_ETHERTYPE_LLDP 0x88cc 656 657 struct hclge_mac_mgr_tbl_entry_cmd { 658 u8 flags; 659 u8 resp_code; 660 __le16 vlan_tag; 661 __le32 mac_addr_hi32; 662 __le16 mac_addr_lo16; 663 __le16 rsv1; 664 __le16 ethter_type; 665 __le16 egress_port; 666 __le16 egress_queue; 667 u8 sw_port_id_aware; 668 u8 rsv2; 669 u8 i_port_bitmap; 670 u8 i_port_direction; 671 u8 rsv3[2]; 672 }; 673 674 struct hclge_mac_vlan_add_cmd { 675 __le16 flags; 676 __le16 mac_addr_hi16; 677 __le32 mac_addr_lo32; 678 __le32 mac_addr_msk_hi32; 679 __le16 mac_addr_msk_lo16; 680 __le16 vlan_tag; 681 __le16 ingress_port; 682 __le16 egress_port; 683 u8 rsv[4]; 684 }; 685 686 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0 687 struct hclge_mac_vlan_remove_cmd { 688 __le16 flags; 689 __le16 mac_addr_hi16; 690 __le32 mac_addr_lo32; 691 __le32 mac_addr_msk_hi32; 692 __le16 mac_addr_msk_lo16; 693 __le16 vlan_tag; 694 __le16 ingress_port; 695 __le16 egress_port; 696 u8 rsv[4]; 697 }; 698 699 struct hclge_vlan_filter_ctrl_cmd { 700 u8 vlan_type; 701 u8 vlan_fe; 702 u8 rsv1[2]; 703 u8 vf_id; 704 u8 rsv2[19]; 705 }; 706 707 struct hclge_vlan_filter_pf_cfg_cmd { 708 u8 vlan_offset; 709 u8 vlan_cfg; 710 u8 rsv[2]; 711 u8 vlan_offset_bitmap[20]; 712 }; 713 714 struct hclge_vlan_filter_vf_cfg_cmd { 715 __le16 vlan_id; 716 u8 resp_code; 717 u8 rsv; 718 u8 vlan_cfg; 719 u8 rsv1[3]; 720 u8 vf_bitmap[16]; 721 }; 722 723 #define HCLGE_ACCEPT_TAG1_B 0 724 #define HCLGE_ACCEPT_UNTAG1_B 1 725 #define HCLGE_PORT_INS_TAG1_EN_B 2 726 #define HCLGE_PORT_INS_TAG2_EN_B 3 727 #define HCLGE_CFG_NIC_ROCE_SEL_B 4 728 #define HCLGE_ACCEPT_TAG2_B 5 729 #define HCLGE_ACCEPT_UNTAG2_B 6 730 731 struct hclge_vport_vtag_tx_cfg_cmd { 732 u8 vport_vlan_cfg; 733 u8 vf_offset; 734 u8 rsv1[2]; 735 __le16 def_vlan_tag1; 736 __le16 def_vlan_tag2; 737 u8 vf_bitmap[8]; 738 u8 rsv2[8]; 739 }; 740 741 #define HCLGE_REM_TAG1_EN_B 0 742 #define HCLGE_REM_TAG2_EN_B 1 743 #define HCLGE_SHOW_TAG1_EN_B 2 744 #define HCLGE_SHOW_TAG2_EN_B 3 745 struct hclge_vport_vtag_rx_cfg_cmd { 746 u8 vport_vlan_cfg; 747 u8 vf_offset; 748 u8 rsv1[6]; 749 u8 vf_bitmap[8]; 750 u8 rsv2[8]; 751 }; 752 753 struct hclge_tx_vlan_type_cfg_cmd { 754 __le16 ot_vlan_type; 755 __le16 in_vlan_type; 756 u8 rsv[20]; 757 }; 758 759 struct hclge_rx_vlan_type_cfg_cmd { 760 __le16 ot_fst_vlan_type; 761 __le16 ot_sec_vlan_type; 762 __le16 in_fst_vlan_type; 763 __le16 in_sec_vlan_type; 764 u8 rsv[16]; 765 }; 766 767 struct hclge_cfg_com_tqp_queue_cmd { 768 __le16 tqp_id; 769 __le16 stream_id; 770 u8 enable; 771 u8 rsv[19]; 772 }; 773 774 struct hclge_cfg_tx_queue_pointer_cmd { 775 __le16 tqp_id; 776 __le16 tx_tail; 777 __le16 tx_head; 778 __le16 fbd_num; 779 __le16 ring_offset; 780 u8 rsv[14]; 781 }; 782 783 #pragma pack(1) 784 struct hclge_mac_ethertype_idx_rd_cmd { 785 u8 flags; 786 u8 resp_code; 787 __le16 vlan_tag; 788 u8 mac_add[6]; 789 __le16 index; 790 __le16 ethter_type; 791 __le16 egress_port; 792 __le16 egress_queue; 793 __le16 rev0; 794 u8 i_port_bitmap; 795 u8 i_port_direction; 796 u8 rev1[2]; 797 }; 798 799 #pragma pack() 800 801 #define HCLGE_TSO_MSS_MIN_S 0 802 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) 803 804 #define HCLGE_TSO_MSS_MAX_S 16 805 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) 806 807 struct hclge_cfg_tso_status_cmd { 808 __le16 tso_mss_min; 809 __le16 tso_mss_max; 810 u8 rsv[20]; 811 }; 812 813 #define HCLGE_GRO_EN_B 0 814 struct hclge_cfg_gro_status_cmd { 815 __le16 gro_en; 816 u8 rsv[22]; 817 }; 818 819 #define HCLGE_TSO_MSS_MIN 256 820 #define HCLGE_TSO_MSS_MAX 9668 821 822 #define HCLGE_TQP_RESET_B 0 823 struct hclge_reset_tqp_queue_cmd { 824 __le16 tqp_id; 825 u8 reset_req; 826 u8 ready_to_reset; 827 u8 rsv[20]; 828 }; 829 830 #define HCLGE_CFG_RESET_MAC_B 3 831 #define HCLGE_CFG_RESET_FUNC_B 7 832 struct hclge_reset_cmd { 833 u8 mac_func_reset; 834 u8 fun_reset_vfid; 835 u8 rsv[22]; 836 }; 837 838 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0) 839 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2) 840 #define HCLGE_CMD_SERDES_DONE_B BIT(0) 841 #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1) 842 struct hclge_serdes_lb_cmd { 843 u8 mask; 844 u8 enable; 845 u8 result; 846 u8 rsv[21]; 847 }; 848 849 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ 850 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ 851 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ 852 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ 853 #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x200 /* 512 byte */ 854 855 #define HCLGE_TYPE_CRQ 0 856 #define HCLGE_TYPE_CSQ 1 857 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 858 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 859 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 860 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 861 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 862 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 863 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c 864 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 865 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 866 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 867 #define HCLGE_NIC_CMQ_EN_B 16 868 #define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B) 869 #define HCLGE_NIC_CMQ_DESC_NUM 1024 870 #define HCLGE_NIC_CMQ_DESC_NUM_S 3 871 872 #define HCLGE_LED_LOCATE_STATE_S 0 873 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) 874 875 struct hclge_set_led_state_cmd { 876 u8 rsv1[3]; 877 u8 locate_led_config; 878 u8 rsv2[20]; 879 }; 880 881 struct hclge_get_fd_mode_cmd { 882 u8 mode; 883 u8 enable; 884 u8 rsv[22]; 885 }; 886 887 struct hclge_get_fd_allocation_cmd { 888 __le32 stage1_entry_num; 889 __le32 stage2_entry_num; 890 __le16 stage1_counter_num; 891 __le16 stage2_counter_num; 892 u8 rsv[12]; 893 }; 894 895 struct hclge_set_fd_key_config_cmd { 896 u8 stage; 897 u8 key_select; 898 u8 inner_sipv6_word_en; 899 u8 inner_dipv6_word_en; 900 u8 outer_sipv6_word_en; 901 u8 outer_dipv6_word_en; 902 u8 rsv1[2]; 903 __le32 tuple_mask; 904 __le32 meta_data_mask; 905 u8 rsv2[8]; 906 }; 907 908 #define HCLGE_FD_EPORT_SW_EN_B 0 909 struct hclge_fd_tcam_config_1_cmd { 910 u8 stage; 911 u8 xy_sel; 912 u8 port_info; 913 u8 rsv1[1]; 914 __le32 index; 915 u8 entry_vld; 916 u8 rsv2[7]; 917 u8 tcam_data[8]; 918 }; 919 920 struct hclge_fd_tcam_config_2_cmd { 921 u8 tcam_data[24]; 922 }; 923 924 struct hclge_fd_tcam_config_3_cmd { 925 u8 tcam_data[20]; 926 u8 rsv[4]; 927 }; 928 929 #define HCLGE_FD_AD_DROP_B 0 930 #define HCLGE_FD_AD_DIRECT_QID_B 1 931 #define HCLGE_FD_AD_QID_S 2 932 #define HCLGE_FD_AD_QID_M GENMASK(12, 2) 933 #define HCLGE_FD_AD_USE_COUNTER_B 12 934 #define HCLGE_FD_AD_COUNTER_NUM_S 13 935 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13) 936 #define HCLGE_FD_AD_NXT_STEP_B 20 937 #define HCLGE_FD_AD_NXT_KEY_S 21 938 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21) 939 #define HCLGE_FD_AD_WR_RULE_ID_B 0 940 #define HCLGE_FD_AD_RULE_ID_S 1 941 #define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1) 942 943 struct hclge_fd_ad_config_cmd { 944 u8 stage; 945 u8 rsv1[3]; 946 __le32 index; 947 __le64 ad_data; 948 u8 rsv2[8]; 949 }; 950 951 int hclge_cmd_init(struct hclge_dev *hdev); 952 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) 953 { 954 writel(value, base + reg); 955 } 956 957 #define hclge_write_dev(a, reg, value) \ 958 hclge_write_reg((a)->io_base, (reg), (value)) 959 #define hclge_read_dev(a, reg) \ 960 hclge_read_reg((a)->io_base, (reg)) 961 962 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) 963 { 964 u8 __iomem *reg_addr = READ_ONCE(base); 965 966 return readl(reg_addr + reg); 967 } 968 969 #define HCLGE_SEND_SYNC(flag) \ 970 ((flag) & HCLGE_CMD_FLAG_NO_INTR) 971 972 struct hclge_hw; 973 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); 974 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, 975 enum hclge_opcode_type opcode, bool is_read); 976 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); 977 978 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, 979 struct hclge_promisc_param *param); 980 981 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, 982 struct hclge_desc *desc); 983 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, 984 struct hclge_desc *desc); 985 986 void hclge_cmd_uninit(struct hclge_dev *hdev); 987 int hclge_cmd_queue_init(struct hclge_dev *hdev); 988 #endif 989