1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_CMD_H 5 #define __HCLGE_CMD_H 6 #include <linux/types.h> 7 #include <linux/io.h> 8 #include <linux/etherdevice.h> 9 #include "hnae3.h" 10 11 #define HCLGE_CMDQ_TX_TIMEOUT 30000 12 #define HCLGE_DESC_DATA_LEN 6 13 14 struct hclge_dev; 15 struct hclge_desc { 16 __le16 opcode; 17 18 #define HCLGE_CMDQ_RX_INVLD_B 0 19 #define HCLGE_CMDQ_RX_OUTVLD_B 1 20 21 __le16 flag; 22 __le16 retval; 23 __le16 rsv; 24 __le32 data[HCLGE_DESC_DATA_LEN]; 25 }; 26 27 struct hclge_cmq_ring { 28 dma_addr_t desc_dma_addr; 29 struct hclge_desc *desc; 30 struct hclge_dev *dev; 31 u32 head; 32 u32 tail; 33 34 u16 buf_size; 35 u16 desc_num; 36 int next_to_use; 37 int next_to_clean; 38 u8 ring_type; /* cmq ring type */ 39 spinlock_t lock; /* Command queue lock */ 40 }; 41 42 enum hclge_cmd_return_status { 43 HCLGE_CMD_EXEC_SUCCESS = 0, 44 HCLGE_CMD_NO_AUTH = 1, 45 HCLGE_CMD_NOT_SUPPORTED = 2, 46 HCLGE_CMD_QUEUE_FULL = 3, 47 HCLGE_CMD_NEXT_ERR = 4, 48 HCLGE_CMD_UNEXE_ERR = 5, 49 HCLGE_CMD_PARA_ERR = 6, 50 HCLGE_CMD_RESULT_ERR = 7, 51 HCLGE_CMD_TIMEOUT = 8, 52 HCLGE_CMD_HILINK_ERR = 9, 53 HCLGE_CMD_QUEUE_ILLEGAL = 10, 54 HCLGE_CMD_INVALID = 11, 55 }; 56 57 enum hclge_cmd_status { 58 HCLGE_STATUS_SUCCESS = 0, 59 HCLGE_ERR_CSQ_FULL = -1, 60 HCLGE_ERR_CSQ_TIMEOUT = -2, 61 HCLGE_ERR_CSQ_ERROR = -3, 62 }; 63 64 struct hclge_misc_vector { 65 u8 __iomem *addr; 66 int vector_irq; 67 char name[HNAE3_INT_NAME_LEN]; 68 }; 69 70 struct hclge_cmq { 71 struct hclge_cmq_ring csq; 72 struct hclge_cmq_ring crq; 73 u16 tx_timeout; 74 enum hclge_cmd_status last_status; 75 }; 76 77 #define HCLGE_CMD_FLAG_IN BIT(0) 78 #define HCLGE_CMD_FLAG_OUT BIT(1) 79 #define HCLGE_CMD_FLAG_NEXT BIT(2) 80 #define HCLGE_CMD_FLAG_WR BIT(3) 81 #define HCLGE_CMD_FLAG_NO_INTR BIT(4) 82 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5) 83 84 enum hclge_opcode_type { 85 /* Generic commands */ 86 HCLGE_OPC_QUERY_FW_VER = 0x0001, 87 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, 88 HCLGE_OPC_GBL_RST_STATUS = 0x0021, 89 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, 90 HCLGE_OPC_QUERY_PF_RSRC = 0x0023, 91 HCLGE_OPC_QUERY_VF_RSRC = 0x0024, 92 HCLGE_OPC_GET_CFG_PARAM = 0x0025, 93 HCLGE_OPC_PF_RST_DONE = 0x0026, 94 HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027, 95 96 HCLGE_OPC_STATS_64_BIT = 0x0030, 97 HCLGE_OPC_STATS_32_BIT = 0x0031, 98 HCLGE_OPC_STATS_MAC = 0x0032, 99 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033, 100 HCLGE_OPC_STATS_MAC_ALL = 0x0034, 101 102 HCLGE_OPC_QUERY_REG_NUM = 0x0040, 103 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, 104 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, 105 HCLGE_OPC_DFX_BD_NUM = 0x0043, 106 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044, 107 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045, 108 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046, 109 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047, 110 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048, 111 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049, 112 HCLGE_OPC_DFX_NCSI_REG = 0x004A, 113 HCLGE_OPC_DFX_RTC_REG = 0x004B, 114 HCLGE_OPC_DFX_PPP_REG = 0x004C, 115 HCLGE_OPC_DFX_RCB_REG = 0x004D, 116 HCLGE_OPC_DFX_TQP_REG = 0x004E, 117 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F, 118 119 HCLGE_OPC_QUERY_DEV_SPECS = 0x0050, 120 121 /* MAC command */ 122 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, 123 HCLGE_OPC_CONFIG_AN_MODE = 0x0304, 124 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, 125 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, 126 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, 127 HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310, 128 HCLGE_OPC_MAC_TNL_INT_EN = 0x0311, 129 HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312, 130 HCLGE_OPC_SERDES_LOOPBACK = 0x0315, 131 HCLGE_OPC_CONFIG_FEC_MODE = 0x031A, 132 133 /* PFC/Pause commands */ 134 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, 135 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, 136 HCLGE_OPC_CFG_MAC_PARA = 0x0703, 137 HCLGE_OPC_CFG_PFC_PARA = 0x0704, 138 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, 139 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, 140 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, 141 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, 142 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, 143 HCLGE_OPC_QOS_MAP = 0x070A, 144 145 /* ETS/scheduler commands */ 146 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, 147 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, 148 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, 149 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, 150 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, 151 HCLGE_OPC_TM_PG_WEIGHT = 0x0809, 152 HCLGE_OPC_TM_QS_WEIGHT = 0x080A, 153 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, 154 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, 155 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, 156 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, 157 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, 158 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, 159 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, 160 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, 161 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, 162 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, 163 HCLGE_OPC_TM_NODES = 0x0816, 164 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843, 165 HCLGE_OPC_QSET_DFX_STS = 0x0844, 166 HCLGE_OPC_PRI_DFX_STS = 0x0845, 167 HCLGE_OPC_PG_DFX_STS = 0x0846, 168 HCLGE_OPC_PORT_DFX_STS = 0x0847, 169 HCLGE_OPC_SCH_NQ_CNT = 0x0848, 170 HCLGE_OPC_SCH_RQ_CNT = 0x0849, 171 HCLGE_OPC_TM_INTERNAL_STS = 0x0850, 172 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851, 173 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852, 174 175 /* Packet buffer allocate commands */ 176 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, 177 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, 178 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, 179 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, 180 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, 181 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, 182 183 /* TQP management command */ 184 HCLGE_OPC_SET_TQP_MAP = 0x0A01, 185 186 /* TQP commands */ 187 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, 188 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, 189 HCLGE_OPC_QUERY_TX_STATS = 0x0B03, 190 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04, 191 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, 192 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, 193 HCLGE_OPC_QUERY_RX_STATS = 0x0B13, 194 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, 195 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, 196 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 197 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, 198 199 /* PPU commands */ 200 HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A, 201 202 /* TSO command */ 203 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, 204 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10, 205 206 /* RSS commands */ 207 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, 208 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, 209 HCLGE_OPC_RSS_TC_MODE = 0x0D08, 210 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, 211 212 /* Promisuous mode command */ 213 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, 214 215 /* Vlan offload commands */ 216 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, 217 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, 218 219 /* Interrupts commands */ 220 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, 221 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, 222 223 /* MAC commands */ 224 HCLGE_OPC_MAC_VLAN_ADD = 0x1000, 225 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, 226 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, 227 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, 228 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004, 229 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, 230 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, 231 232 /* MAC VLAN commands */ 233 HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033, 234 235 /* VLAN commands */ 236 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, 237 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, 238 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, 239 240 /* Flow Director commands */ 241 HCLGE_OPC_FD_MODE_CTRL = 0x1200, 242 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201, 243 HCLGE_OPC_FD_KEY_CONFIG = 0x1202, 244 HCLGE_OPC_FD_TCAM_OP = 0x1203, 245 HCLGE_OPC_FD_AD_OP = 0x1204, 246 247 /* MDIO command */ 248 HCLGE_OPC_MDIO_CONFIG = 0x1900, 249 250 /* QCN commands */ 251 HCLGE_OPC_QCN_MOD_CFG = 0x1A01, 252 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, 253 HCLGE_OPC_QCN_SHAPPING_CFG = 0x1A03, 254 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, 255 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, 256 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, 257 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, 258 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, 259 260 /* Mailbox command */ 261 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, 262 263 /* Led command */ 264 HCLGE_OPC_LED_STATUS_CFG = 0xB000, 265 266 /* NCL config command */ 267 HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011, 268 269 /* M7 stats command */ 270 HCLGE_OPC_M7_STATS_BD = 0x7012, 271 HCLGE_OPC_M7_STATS_INFO = 0x7013, 272 HCLGE_OPC_M7_COMPAT_CFG = 0x701A, 273 274 /* SFP command */ 275 HCLGE_OPC_GET_SFP_EEPROM = 0x7100, 276 HCLGE_OPC_GET_SFP_EXIST = 0x7101, 277 HCLGE_OPC_GET_SFP_INFO = 0x7104, 278 279 /* Error INT commands */ 280 HCLGE_MAC_COMMON_INT_EN = 0x030E, 281 HCLGE_TM_SCH_ECC_INT_EN = 0x0829, 282 HCLGE_SSU_ECC_INT_CMD = 0x0989, 283 HCLGE_SSU_COMMON_INT_CMD = 0x098C, 284 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40, 285 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41, 286 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42, 287 HCLGE_COMMON_ECC_INT_CFG = 0x1505, 288 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510, 289 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511, 290 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512, 291 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513, 292 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514, 293 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515, 294 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580, 295 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581, 296 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584, 297 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585, 298 HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586, 299 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803, 300 HCLGE_IGU_COMMON_INT_EN = 0x1806, 301 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14, 302 HCLGE_PPP_CMD0_INT_CMD = 0x2100, 303 HCLGE_PPP_CMD1_INT_CMD = 0x2101, 304 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105, 305 HCLGE_NCSI_INT_EN = 0x2401, 306 }; 307 308 #define HCLGE_TQP_REG_OFFSET 0x80000 309 #define HCLGE_TQP_REG_SIZE 0x200 310 311 #define HCLGE_TQP_MAX_SIZE_DEV_V2 1024 312 #define HCLGE_TQP_EXT_REG_OFFSET 0x100 313 314 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 315 #define HCLGE_RCB_INIT_FLAG_EN_B 0 316 #define HCLGE_RCB_INIT_FLAG_FINI_B 8 317 struct hclge_config_rcb_init_cmd { 318 __le16 rcb_init_flag; 319 u8 rsv[22]; 320 }; 321 322 struct hclge_tqp_map_cmd { 323 __le16 tqp_id; /* Absolute tqp id for in this pf */ 324 u8 tqp_vf; /* VF id */ 325 #define HCLGE_TQP_MAP_TYPE_PF 0 326 #define HCLGE_TQP_MAP_TYPE_VF 1 327 #define HCLGE_TQP_MAP_TYPE_B 0 328 #define HCLGE_TQP_MAP_EN_B 1 329 u8 tqp_flag; /* Indicate it's pf or vf tqp */ 330 __le16 tqp_vid; /* Virtual id in this pf/vf */ 331 u8 rsv[18]; 332 }; 333 334 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 335 336 enum hclge_int_type { 337 HCLGE_INT_TX, 338 HCLGE_INT_RX, 339 HCLGE_INT_EVENT, 340 }; 341 342 struct hclge_ctrl_vector_chain_cmd { 343 #define HCLGE_VECTOR_ID_L_S 0 344 #define HCLGE_VECTOR_ID_L_M GENMASK(7, 0) 345 u8 int_vector_id_l; 346 u8 int_cause_num; 347 #define HCLGE_INT_TYPE_S 0 348 #define HCLGE_INT_TYPE_M GENMASK(1, 0) 349 #define HCLGE_TQP_ID_S 2 350 #define HCLGE_TQP_ID_M GENMASK(12, 2) 351 #define HCLGE_INT_GL_IDX_S 13 352 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) 353 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; 354 u8 vfid; 355 #define HCLGE_VECTOR_ID_H_S 8 356 #define HCLGE_VECTOR_ID_H_M GENMASK(15, 8) 357 u8 int_vector_id_h; 358 }; 359 360 #define HCLGE_MAX_TC_NUM 8 361 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ 362 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ 363 struct hclge_tx_buff_alloc_cmd { 364 __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM]; 365 u8 tx_buff_rsv[8]; 366 }; 367 368 struct hclge_rx_priv_buff_cmd { 369 __le16 buf_num[HCLGE_MAX_TC_NUM]; 370 __le16 shared_buf; 371 u8 rsv[6]; 372 }; 373 374 enum HCLGE_CAP_BITS { 375 HCLGE_CAP_UDP_GSO_B, 376 HCLGE_CAP_QB_B, 377 HCLGE_CAP_FD_FORWARD_TC_B, 378 HCLGE_CAP_PTP_B, 379 HCLGE_CAP_INT_QL_B, 380 HCLGE_CAP_HW_TX_CSUM_B, 381 HCLGE_CAP_TX_PUSH_B, 382 HCLGE_CAP_PHY_IMP_B, 383 HCLGE_CAP_TQP_TXRX_INDEP_B, 384 HCLGE_CAP_HW_PAD_B, 385 HCLGE_CAP_STASH_B, 386 HCLGE_CAP_UDP_TUNNEL_CSUM_B, 387 }; 388 389 enum HCLGE_API_CAP_BITS { 390 HCLGE_API_CAP_FLEX_RSS_TBL_B, 391 }; 392 393 #define HCLGE_QUERY_CAP_LENGTH 3 394 struct hclge_query_version_cmd { 395 __le32 firmware; 396 __le32 hardware; 397 __le32 api_caps; 398 __le32 caps[HCLGE_QUERY_CAP_LENGTH]; /* capabilities of device */ 399 }; 400 401 #define HCLGE_RX_PRIV_EN_B 15 402 #define HCLGE_TC_NUM_ONE_DESC 4 403 struct hclge_priv_wl { 404 __le16 high; 405 __le16 low; 406 }; 407 408 struct hclge_rx_priv_wl_buf { 409 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; 410 }; 411 412 struct hclge_rx_com_thrd { 413 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; 414 }; 415 416 struct hclge_rx_com_wl { 417 struct hclge_priv_wl com_wl; 418 }; 419 420 struct hclge_waterline { 421 u32 low; 422 u32 high; 423 }; 424 425 struct hclge_tc_thrd { 426 u32 low; 427 u32 high; 428 }; 429 430 struct hclge_priv_buf { 431 struct hclge_waterline wl; /* Waterline for low and high*/ 432 u32 buf_size; /* TC private buffer size */ 433 u32 tx_buf_size; 434 u32 enable; /* Enable TC private buffer or not */ 435 }; 436 437 struct hclge_shared_buf { 438 struct hclge_waterline self; 439 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; 440 u32 buf_size; 441 }; 442 443 struct hclge_pkt_buf_alloc { 444 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; 445 struct hclge_shared_buf s_buf; 446 }; 447 448 #define HCLGE_RX_COM_WL_EN_B 15 449 struct hclge_rx_com_wl_buf_cmd { 450 __le16 high_wl; 451 __le16 low_wl; 452 u8 rsv[20]; 453 }; 454 455 #define HCLGE_RX_PKT_EN_B 15 456 struct hclge_rx_pkt_buf_cmd { 457 __le16 high_pkt; 458 __le16 low_pkt; 459 u8 rsv[20]; 460 }; 461 462 #define HCLGE_PF_STATE_DONE_B 0 463 #define HCLGE_PF_STATE_MAIN_B 1 464 #define HCLGE_PF_STATE_BOND_B 2 465 #define HCLGE_PF_STATE_MAC_N_B 6 466 #define HCLGE_PF_MAC_NUM_MASK 0x3 467 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) 468 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) 469 #define HCLGE_VF_RST_STATUS_CMD 4 470 471 struct hclge_func_status_cmd { 472 __le32 vf_rst_state[HCLGE_VF_RST_STATUS_CMD]; 473 u8 pf_state; 474 u8 mac_id; 475 u8 rsv1; 476 u8 pf_cnt_in_mac; 477 u8 pf_num; 478 u8 vf_num; 479 u8 rsv[2]; 480 }; 481 482 struct hclge_pf_res_cmd { 483 __le16 tqp_num; 484 __le16 buf_size; 485 __le16 msixcap_localid_ba_nic; 486 __le16 msixcap_localid_number_nic; 487 __le16 pf_intr_vector_number_roce; 488 __le16 pf_own_fun_number; 489 __le16 tx_buf_size; 490 __le16 dv_buf_size; 491 __le16 ext_tqp_num; 492 u8 rsv[6]; 493 }; 494 495 #define HCLGE_CFG_OFFSET_S 0 496 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) 497 #define HCLGE_CFG_RD_LEN_S 24 498 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) 499 #define HCLGE_CFG_RD_LEN_BYTES 16 500 #define HCLGE_CFG_RD_LEN_UNIT 4 501 502 #define HCLGE_CFG_VMDQ_S 0 503 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0) 504 #define HCLGE_CFG_TC_NUM_S 8 505 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) 506 #define HCLGE_CFG_TQP_DESC_N_S 16 507 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) 508 #define HCLGE_CFG_PHY_ADDR_S 0 509 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) 510 #define HCLGE_CFG_MEDIA_TP_S 8 511 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) 512 #define HCLGE_CFG_RX_BUF_LEN_S 16 513 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) 514 #define HCLGE_CFG_MAC_ADDR_H_S 0 515 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) 516 #define HCLGE_CFG_DEFAULT_SPEED_S 16 517 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) 518 #define HCLGE_CFG_RSS_SIZE_S 24 519 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) 520 #define HCLGE_CFG_SPEED_ABILITY_S 0 521 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) 522 #define HCLGE_CFG_SPEED_ABILITY_EXT_S 10 523 #define HCLGE_CFG_SPEED_ABILITY_EXT_M GENMASK(15, 10) 524 #define HCLGE_CFG_UMV_TBL_SPACE_S 16 525 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) 526 #define HCLGE_CFG_PF_RSS_SIZE_S 0 527 #define HCLGE_CFG_PF_RSS_SIZE_M GENMASK(3, 0) 528 529 #define HCLGE_CFG_CMD_CNT 4 530 531 struct hclge_cfg_param_cmd { 532 __le32 offset; 533 __le32 rsv; 534 __le32 param[HCLGE_CFG_CMD_CNT]; 535 }; 536 537 #define HCLGE_MAC_MODE 0x0 538 #define HCLGE_DESC_NUM 0x40 539 540 #define HCLGE_ALLOC_VALID_B 0 541 struct hclge_vf_num_cmd { 542 u8 alloc_valid; 543 u8 rsv[23]; 544 }; 545 546 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 547 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 548 #define HCLGE_RSS_HASH_KEY_NUM 16 549 struct hclge_rss_config_cmd { 550 u8 hash_config; 551 u8 rsv[7]; 552 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; 553 }; 554 555 struct hclge_rss_input_tuple_cmd { 556 u8 ipv4_tcp_en; 557 u8 ipv4_udp_en; 558 u8 ipv4_sctp_en; 559 u8 ipv4_fragment_en; 560 u8 ipv6_tcp_en; 561 u8 ipv6_udp_en; 562 u8 ipv6_sctp_en; 563 u8 ipv6_fragment_en; 564 u8 rsv[16]; 565 }; 566 567 #define HCLGE_RSS_CFG_TBL_SIZE 16 568 #define HCLGE_RSS_CFG_TBL_SIZE_H 4 569 #define HCLGE_RSS_CFG_TBL_BW_H 2U 570 #define HCLGE_RSS_CFG_TBL_BW_L 8U 571 572 struct hclge_rss_indirection_table_cmd { 573 __le16 start_table_index; 574 __le16 rss_set_bitmap; 575 u8 rss_qid_h[HCLGE_RSS_CFG_TBL_SIZE_H]; 576 u8 rss_qid_l[HCLGE_RSS_CFG_TBL_SIZE]; 577 }; 578 579 #define HCLGE_RSS_TC_OFFSET_S 0 580 #define HCLGE_RSS_TC_OFFSET_M GENMASK(10, 0) 581 #define HCLGE_RSS_TC_SIZE_MSB_B 11 582 #define HCLGE_RSS_TC_SIZE_S 12 583 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) 584 #define HCLGE_RSS_TC_SIZE_MSB_OFFSET 3 585 #define HCLGE_RSS_TC_VALID_B 15 586 struct hclge_rss_tc_mode_cmd { 587 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; 588 u8 rsv[8]; 589 }; 590 591 #define HCLGE_LINK_STATUS_UP_B 0 592 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B) 593 struct hclge_link_status_cmd { 594 u8 status; 595 u8 rsv[23]; 596 }; 597 598 /* for DEVICE_VERSION_V1/2, reference to promisc cmd byte8 */ 599 #define HCLGE_PROMISC_EN_UC 1 600 #define HCLGE_PROMISC_EN_MC 2 601 #define HCLGE_PROMISC_EN_BC 3 602 #define HCLGE_PROMISC_TX_EN 4 603 #define HCLGE_PROMISC_RX_EN 5 604 605 /* for DEVICE_VERSION_V3, reference to promisc cmd byte10 */ 606 #define HCLGE_PROMISC_UC_RX_EN 2 607 #define HCLGE_PROMISC_MC_RX_EN 3 608 #define HCLGE_PROMISC_BC_RX_EN 4 609 #define HCLGE_PROMISC_UC_TX_EN 5 610 #define HCLGE_PROMISC_MC_TX_EN 6 611 #define HCLGE_PROMISC_BC_TX_EN 7 612 613 struct hclge_promisc_cfg_cmd { 614 u8 promisc; 615 u8 vf_id; 616 u8 extend_promisc; 617 u8 rsv0[21]; 618 }; 619 620 enum hclge_promisc_type { 621 HCLGE_UNICAST = 1, 622 HCLGE_MULTICAST = 2, 623 HCLGE_BROADCAST = 3, 624 }; 625 626 #define HCLGE_MAC_TX_EN_B 6 627 #define HCLGE_MAC_RX_EN_B 7 628 #define HCLGE_MAC_PAD_TX_B 11 629 #define HCLGE_MAC_PAD_RX_B 12 630 #define HCLGE_MAC_1588_TX_B 13 631 #define HCLGE_MAC_1588_RX_B 14 632 #define HCLGE_MAC_APP_LP_B 15 633 #define HCLGE_MAC_LINE_LP_B 16 634 #define HCLGE_MAC_FCS_TX_B 17 635 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 636 #define HCLGE_MAC_RX_FCS_STRIP_B 19 637 #define HCLGE_MAC_RX_FCS_B 20 638 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 639 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 640 641 struct hclge_config_mac_mode_cmd { 642 __le32 txrx_pad_fcs_loop_en; 643 u8 rsv[20]; 644 }; 645 646 struct hclge_pf_rst_sync_cmd { 647 #define HCLGE_PF_RST_ALL_VF_RDY_B 0 648 u8 all_vf_ready; 649 u8 rsv[23]; 650 }; 651 652 #define HCLGE_CFG_SPEED_S 0 653 #define HCLGE_CFG_SPEED_M GENMASK(5, 0) 654 655 #define HCLGE_CFG_DUPLEX_B 7 656 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) 657 658 struct hclge_config_mac_speed_dup_cmd { 659 u8 speed_dup; 660 661 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 662 u8 mac_change_fec_en; 663 u8 rsv[22]; 664 }; 665 666 #define HCLGE_TQP_ENABLE_B 0 667 668 #define HCLGE_MAC_CFG_AN_EN_B 0 669 #define HCLGE_MAC_CFG_AN_INT_EN_B 1 670 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 671 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 672 #define HCLGE_MAC_CFG_AN_RST_B 4 673 674 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) 675 676 struct hclge_config_auto_neg_cmd { 677 __le32 cfg_an_cmd_flag; 678 u8 rsv[20]; 679 }; 680 681 struct hclge_sfp_info_cmd { 682 __le32 speed; 683 u8 query_type; /* 0: sfp speed, 1: active speed */ 684 u8 active_fec; 685 u8 autoneg; /* autoneg state */ 686 u8 autoneg_ability; /* whether support autoneg */ 687 __le32 speed_ability; /* speed ability for current media */ 688 __le32 module_type; 689 u8 rsv[8]; 690 }; 691 692 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0 693 #define HCLGE_MAC_CFG_FEC_MODE_S 1 694 #define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1) 695 #define HCLGE_MAC_CFG_FEC_SET_DEF_B 0 696 #define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1 697 698 #define HCLGE_MAC_FEC_OFF 0 699 #define HCLGE_MAC_FEC_BASER 1 700 #define HCLGE_MAC_FEC_RS 2 701 struct hclge_config_fec_cmd { 702 u8 fec_mode; 703 u8 default_config; 704 u8 rsv[22]; 705 }; 706 707 #define HCLGE_MAC_UPLINK_PORT 0x100 708 709 struct hclge_config_max_frm_size_cmd { 710 __le16 max_frm_size; 711 u8 min_frm_size; 712 u8 rsv[21]; 713 }; 714 715 enum hclge_mac_vlan_tbl_opcode { 716 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ 717 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ 718 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ 719 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ 720 }; 721 722 enum hclge_mac_vlan_add_resp_code { 723 HCLGE_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */ 724 HCLGE_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */ 725 }; 726 727 #define HCLGE_MAC_VLAN_BIT0_EN_B 0 728 #define HCLGE_MAC_VLAN_BIT1_EN_B 1 729 #define HCLGE_MAC_EPORT_SW_EN_B 12 730 #define HCLGE_MAC_EPORT_TYPE_B 11 731 #define HCLGE_MAC_EPORT_VFID_S 3 732 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) 733 #define HCLGE_MAC_EPORT_PFID_S 0 734 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) 735 struct hclge_mac_vlan_tbl_entry_cmd { 736 u8 flags; 737 u8 resp_code; 738 __le16 vlan_tag; 739 __le32 mac_addr_hi32; 740 __le16 mac_addr_lo16; 741 __le16 rsv1; 742 u8 entry_type; 743 u8 mc_mac_en; 744 __le16 egress_port; 745 __le16 egress_queue; 746 u8 rsv2[6]; 747 }; 748 749 #define HCLGE_UMV_SPC_ALC_B 0 750 struct hclge_umv_spc_alc_cmd { 751 u8 allocate; 752 u8 rsv1[3]; 753 __le32 space_size; 754 u8 rsv2[16]; 755 }; 756 757 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) 758 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) 759 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) 760 761 struct hclge_mac_mgr_tbl_entry_cmd { 762 u8 flags; 763 u8 resp_code; 764 __le16 vlan_tag; 765 u8 mac_addr[ETH_ALEN]; 766 __le16 rsv1; 767 __le16 ethter_type; 768 __le16 egress_port; 769 __le16 egress_queue; 770 u8 sw_port_id_aware; 771 u8 rsv2; 772 u8 i_port_bitmap; 773 u8 i_port_direction; 774 u8 rsv3[2]; 775 }; 776 777 struct hclge_vlan_filter_ctrl_cmd { 778 u8 vlan_type; 779 u8 vlan_fe; 780 u8 rsv1[2]; 781 u8 vf_id; 782 u8 rsv2[19]; 783 }; 784 785 #define HCLGE_VLAN_ID_OFFSET_STEP 160 786 #define HCLGE_VLAN_BYTE_SIZE 8 787 #define HCLGE_VLAN_OFFSET_BITMAP \ 788 (HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE) 789 790 struct hclge_vlan_filter_pf_cfg_cmd { 791 u8 vlan_offset; 792 u8 vlan_cfg; 793 u8 rsv[2]; 794 u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP]; 795 }; 796 797 #define HCLGE_MAX_VF_BYTES 16 798 799 struct hclge_vlan_filter_vf_cfg_cmd { 800 __le16 vlan_id; 801 u8 resp_code; 802 u8 rsv; 803 u8 vlan_cfg; 804 u8 rsv1[3]; 805 u8 vf_bitmap[HCLGE_MAX_VF_BYTES]; 806 }; 807 808 #define HCLGE_SWITCH_ANTI_SPOOF_B 0U 809 #define HCLGE_SWITCH_ALW_LPBK_B 1U 810 #define HCLGE_SWITCH_ALW_LCL_LPBK_B 2U 811 #define HCLGE_SWITCH_ALW_DST_OVRD_B 3U 812 #define HCLGE_SWITCH_NO_MASK 0x0 813 #define HCLGE_SWITCH_ANTI_SPOOF_MASK 0xFE 814 #define HCLGE_SWITCH_ALW_LPBK_MASK 0xFD 815 #define HCLGE_SWITCH_ALW_LCL_LPBK_MASK 0xFB 816 #define HCLGE_SWITCH_LW_DST_OVRD_MASK 0xF7 817 818 struct hclge_mac_vlan_switch_cmd { 819 u8 roce_sel; 820 u8 rsv1[3]; 821 __le32 func_id; 822 u8 switch_param; 823 u8 rsv2[3]; 824 u8 param_mask; 825 u8 rsv3[11]; 826 }; 827 828 enum hclge_mac_vlan_cfg_sel { 829 HCLGE_MAC_VLAN_NIC_SEL = 0, 830 HCLGE_MAC_VLAN_ROCE_SEL, 831 }; 832 833 #define HCLGE_ACCEPT_TAG1_B 0 834 #define HCLGE_ACCEPT_UNTAG1_B 1 835 #define HCLGE_PORT_INS_TAG1_EN_B 2 836 #define HCLGE_PORT_INS_TAG2_EN_B 3 837 #define HCLGE_CFG_NIC_ROCE_SEL_B 4 838 #define HCLGE_ACCEPT_TAG2_B 5 839 #define HCLGE_ACCEPT_UNTAG2_B 6 840 #define HCLGE_TAG_SHIFT_MODE_EN_B 7 841 #define HCLGE_VF_NUM_PER_BYTE 8 842 843 struct hclge_vport_vtag_tx_cfg_cmd { 844 u8 vport_vlan_cfg; 845 u8 vf_offset; 846 u8 rsv1[2]; 847 __le16 def_vlan_tag1; 848 __le16 def_vlan_tag2; 849 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE]; 850 u8 rsv2[8]; 851 }; 852 853 #define HCLGE_REM_TAG1_EN_B 0 854 #define HCLGE_REM_TAG2_EN_B 1 855 #define HCLGE_SHOW_TAG1_EN_B 2 856 #define HCLGE_SHOW_TAG2_EN_B 3 857 #define HCLGE_DISCARD_TAG1_EN_B 5 858 #define HCLGE_DISCARD_TAG2_EN_B 6 859 struct hclge_vport_vtag_rx_cfg_cmd { 860 u8 vport_vlan_cfg; 861 u8 vf_offset; 862 u8 rsv1[6]; 863 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE]; 864 u8 rsv2[8]; 865 }; 866 867 struct hclge_tx_vlan_type_cfg_cmd { 868 __le16 ot_vlan_type; 869 __le16 in_vlan_type; 870 u8 rsv[20]; 871 }; 872 873 struct hclge_rx_vlan_type_cfg_cmd { 874 __le16 ot_fst_vlan_type; 875 __le16 ot_sec_vlan_type; 876 __le16 in_fst_vlan_type; 877 __le16 in_sec_vlan_type; 878 u8 rsv[16]; 879 }; 880 881 struct hclge_cfg_com_tqp_queue_cmd { 882 __le16 tqp_id; 883 __le16 stream_id; 884 u8 enable; 885 u8 rsv[19]; 886 }; 887 888 struct hclge_cfg_tx_queue_pointer_cmd { 889 __le16 tqp_id; 890 __le16 tx_tail; 891 __le16 tx_head; 892 __le16 fbd_num; 893 __le16 ring_offset; 894 u8 rsv[14]; 895 }; 896 897 #pragma pack(1) 898 struct hclge_mac_ethertype_idx_rd_cmd { 899 u8 flags; 900 u8 resp_code; 901 __le16 vlan_tag; 902 u8 mac_addr[ETH_ALEN]; 903 __le16 index; 904 __le16 ethter_type; 905 __le16 egress_port; 906 __le16 egress_queue; 907 __le16 rev0; 908 u8 i_port_bitmap; 909 u8 i_port_direction; 910 u8 rev1[2]; 911 }; 912 913 #pragma pack() 914 915 #define HCLGE_TSO_MSS_MIN_S 0 916 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) 917 918 #define HCLGE_TSO_MSS_MAX_S 16 919 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) 920 921 struct hclge_cfg_tso_status_cmd { 922 __le16 tso_mss_min; 923 __le16 tso_mss_max; 924 u8 rsv[20]; 925 }; 926 927 #define HCLGE_GRO_EN_B 0 928 struct hclge_cfg_gro_status_cmd { 929 u8 gro_en; 930 u8 rsv[23]; 931 }; 932 933 #define HCLGE_TSO_MSS_MIN 256 934 #define HCLGE_TSO_MSS_MAX 9668 935 936 #define HCLGE_TQP_RESET_B 0 937 struct hclge_reset_tqp_queue_cmd { 938 __le16 tqp_id; 939 u8 reset_req; 940 u8 ready_to_reset; 941 u8 rsv[20]; 942 }; 943 944 #define HCLGE_CFG_RESET_MAC_B 3 945 #define HCLGE_CFG_RESET_FUNC_B 7 946 struct hclge_reset_cmd { 947 u8 mac_func_reset; 948 u8 fun_reset_vfid; 949 u8 rsv[22]; 950 }; 951 952 #define HCLGE_PF_RESET_DONE_BIT BIT(0) 953 954 struct hclge_pf_rst_done_cmd { 955 u8 pf_rst_done; 956 u8 rsv[23]; 957 }; 958 959 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0) 960 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2) 961 #define HCLGE_CMD_SERDES_DONE_B BIT(0) 962 #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1) 963 struct hclge_serdes_lb_cmd { 964 u8 mask; 965 u8 enable; 966 u8 result; 967 u8 rsv[21]; 968 }; 969 970 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ 971 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ 972 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ 973 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ 974 #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */ 975 976 #define HCLGE_TYPE_CRQ 0 977 #define HCLGE_TYPE_CSQ 1 978 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 979 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 980 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 981 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 982 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 983 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 984 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c 985 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 986 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 987 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 988 989 /* this bit indicates that the driver is ready for hardware reset */ 990 #define HCLGE_NIC_SW_RST_RDY_B 16 991 #define HCLGE_NIC_SW_RST_RDY BIT(HCLGE_NIC_SW_RST_RDY_B) 992 993 #define HCLGE_NIC_CMQ_DESC_NUM 1024 994 #define HCLGE_NIC_CMQ_DESC_NUM_S 3 995 996 #define HCLGE_LED_LOCATE_STATE_S 0 997 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) 998 999 struct hclge_set_led_state_cmd { 1000 u8 rsv1[3]; 1001 u8 locate_led_config; 1002 u8 rsv2[20]; 1003 }; 1004 1005 struct hclge_get_fd_mode_cmd { 1006 u8 mode; 1007 u8 enable; 1008 u8 rsv[22]; 1009 }; 1010 1011 struct hclge_get_fd_allocation_cmd { 1012 __le32 stage1_entry_num; 1013 __le32 stage2_entry_num; 1014 __le16 stage1_counter_num; 1015 __le16 stage2_counter_num; 1016 u8 rsv[12]; 1017 }; 1018 1019 struct hclge_set_fd_key_config_cmd { 1020 u8 stage; 1021 u8 key_select; 1022 u8 inner_sipv6_word_en; 1023 u8 inner_dipv6_word_en; 1024 u8 outer_sipv6_word_en; 1025 u8 outer_dipv6_word_en; 1026 u8 rsv1[2]; 1027 __le32 tuple_mask; 1028 __le32 meta_data_mask; 1029 u8 rsv2[8]; 1030 }; 1031 1032 #define HCLGE_FD_EPORT_SW_EN_B 0 1033 struct hclge_fd_tcam_config_1_cmd { 1034 u8 stage; 1035 u8 xy_sel; 1036 u8 port_info; 1037 u8 rsv1[1]; 1038 __le32 index; 1039 u8 entry_vld; 1040 u8 rsv2[7]; 1041 u8 tcam_data[8]; 1042 }; 1043 1044 struct hclge_fd_tcam_config_2_cmd { 1045 u8 tcam_data[24]; 1046 }; 1047 1048 struct hclge_fd_tcam_config_3_cmd { 1049 u8 tcam_data[20]; 1050 u8 rsv[4]; 1051 }; 1052 1053 #define HCLGE_FD_AD_DROP_B 0 1054 #define HCLGE_FD_AD_DIRECT_QID_B 1 1055 #define HCLGE_FD_AD_QID_S 2 1056 #define HCLGE_FD_AD_QID_M GENMASK(12, 2) 1057 #define HCLGE_FD_AD_USE_COUNTER_B 12 1058 #define HCLGE_FD_AD_COUNTER_NUM_S 13 1059 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13) 1060 #define HCLGE_FD_AD_NXT_STEP_B 20 1061 #define HCLGE_FD_AD_NXT_KEY_S 21 1062 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21) 1063 #define HCLGE_FD_AD_WR_RULE_ID_B 0 1064 #define HCLGE_FD_AD_RULE_ID_S 1 1065 #define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1) 1066 #define HCLGE_FD_AD_TC_OVRD_B 16 1067 #define HCLGE_FD_AD_TC_SIZE_S 17 1068 #define HCLGE_FD_AD_TC_SIZE_M GENMASK(20, 17) 1069 1070 struct hclge_fd_ad_config_cmd { 1071 u8 stage; 1072 u8 rsv1[3]; 1073 __le32 index; 1074 __le64 ad_data; 1075 u8 rsv2[8]; 1076 }; 1077 1078 struct hclge_get_m7_bd_cmd { 1079 __le32 bd_num; 1080 u8 rsv[20]; 1081 }; 1082 1083 struct hclge_query_ppu_pf_other_int_dfx_cmd { 1084 __le16 over_8bd_no_fe_qid; 1085 __le16 over_8bd_no_fe_vf_id; 1086 __le16 tso_mss_cmp_min_err_qid; 1087 __le16 tso_mss_cmp_min_err_vf_id; 1088 __le16 tso_mss_cmp_max_err_qid; 1089 __le16 tso_mss_cmp_max_err_vf_id; 1090 __le16 tx_rd_fbd_poison_qid; 1091 __le16 tx_rd_fbd_poison_vf_id; 1092 __le16 rx_rd_fbd_poison_qid; 1093 __le16 rx_rd_fbd_poison_vf_id; 1094 u8 rsv[4]; 1095 }; 1096 1097 #define HCLGE_LINK_EVENT_REPORT_EN_B 0 1098 #define HCLGE_NCSI_ERROR_REPORT_EN_B 1 1099 struct hclge_firmware_compat_cmd { 1100 __le32 compat; 1101 u8 rsv[20]; 1102 }; 1103 1104 #define HCLGE_SFP_INFO_CMD_NUM 6 1105 #define HCLGE_SFP_INFO_BD0_LEN 20 1106 #define HCLGE_SFP_INFO_BDX_LEN 24 1107 #define HCLGE_SFP_INFO_MAX_LEN \ 1108 (HCLGE_SFP_INFO_BD0_LEN + \ 1109 (HCLGE_SFP_INFO_CMD_NUM - 1) * HCLGE_SFP_INFO_BDX_LEN) 1110 1111 struct hclge_sfp_info_bd0_cmd { 1112 __le16 offset; 1113 __le16 read_len; 1114 u8 data[HCLGE_SFP_INFO_BD0_LEN]; 1115 }; 1116 1117 #define HCLGE_QUERY_DEV_SPECS_BD_NUM 4 1118 1119 struct hclge_dev_specs_0_cmd { 1120 __le32 rsv0; 1121 __le32 mac_entry_num; 1122 __le32 mng_entry_num; 1123 __le16 rss_ind_tbl_size; 1124 __le16 rss_key_size; 1125 __le16 int_ql_max; 1126 u8 max_non_tso_bd_num; 1127 u8 rsv1; 1128 __le32 max_tm_rate; 1129 }; 1130 1131 #define HCLGE_DEF_MAX_INT_GL 0x1FE0U 1132 1133 struct hclge_dev_specs_1_cmd { 1134 __le16 max_frm_size; 1135 __le16 max_qset_num; 1136 __le16 max_int_gl; 1137 u8 rsv1[18]; 1138 }; 1139 1140 int hclge_cmd_init(struct hclge_dev *hdev); 1141 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) 1142 { 1143 writel(value, base + reg); 1144 } 1145 1146 #define hclge_write_dev(a, reg, value) \ 1147 hclge_write_reg((a)->io_base, reg, value) 1148 #define hclge_read_dev(a, reg) \ 1149 hclge_read_reg((a)->io_base, reg) 1150 1151 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) 1152 { 1153 u8 __iomem *reg_addr = READ_ONCE(base); 1154 1155 return readl(reg_addr + reg); 1156 } 1157 1158 #define HCLGE_SEND_SYNC(flag) \ 1159 ((flag) & HCLGE_CMD_FLAG_NO_INTR) 1160 1161 struct hclge_hw; 1162 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); 1163 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, 1164 enum hclge_opcode_type opcode, bool is_read); 1165 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); 1166 1167 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, 1168 struct hclge_desc *desc); 1169 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, 1170 struct hclge_desc *desc); 1171 1172 void hclge_cmd_uninit(struct hclge_dev *hdev); 1173 int hclge_cmd_queue_init(struct hclge_dev *hdev); 1174 #endif 1175