1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HCLGE_CMD_H 5 #define __HCLGE_CMD_H 6 #include <linux/types.h> 7 #include <linux/io.h> 8 9 #define HCLGE_CMDQ_TX_TIMEOUT 30000 10 11 struct hclge_dev; 12 struct hclge_desc { 13 __le16 opcode; 14 15 #define HCLGE_CMDQ_RX_INVLD_B 0 16 #define HCLGE_CMDQ_RX_OUTVLD_B 1 17 18 __le16 flag; 19 __le16 retval; 20 __le16 rsv; 21 __le32 data[6]; 22 }; 23 24 struct hclge_cmq_ring { 25 dma_addr_t desc_dma_addr; 26 struct hclge_desc *desc; 27 struct hclge_dev *dev; 28 u32 head; 29 u32 tail; 30 31 u16 buf_size; 32 u16 desc_num; 33 int next_to_use; 34 int next_to_clean; 35 u8 ring_type; /* cmq ring type */ 36 spinlock_t lock; /* Command queue lock */ 37 }; 38 39 enum hclge_cmd_return_status { 40 HCLGE_CMD_EXEC_SUCCESS = 0, 41 HCLGE_CMD_NO_AUTH = 1, 42 HCLGE_CMD_NOT_EXEC = 2, 43 HCLGE_CMD_QUEUE_FULL = 3, 44 }; 45 46 enum hclge_cmd_status { 47 HCLGE_STATUS_SUCCESS = 0, 48 HCLGE_ERR_CSQ_FULL = -1, 49 HCLGE_ERR_CSQ_TIMEOUT = -2, 50 HCLGE_ERR_CSQ_ERROR = -3, 51 }; 52 53 struct hclge_misc_vector { 54 u8 __iomem *addr; 55 int vector_irq; 56 }; 57 58 struct hclge_cmq { 59 struct hclge_cmq_ring csq; 60 struct hclge_cmq_ring crq; 61 u16 tx_timeout; 62 enum hclge_cmd_status last_status; 63 }; 64 65 #define HCLGE_CMD_FLAG_IN BIT(0) 66 #define HCLGE_CMD_FLAG_OUT BIT(1) 67 #define HCLGE_CMD_FLAG_NEXT BIT(2) 68 #define HCLGE_CMD_FLAG_WR BIT(3) 69 #define HCLGE_CMD_FLAG_NO_INTR BIT(4) 70 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5) 71 72 enum hclge_opcode_type { 73 /* Generic commands */ 74 HCLGE_OPC_QUERY_FW_VER = 0x0001, 75 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020, 76 HCLGE_OPC_GBL_RST_STATUS = 0x0021, 77 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022, 78 HCLGE_OPC_QUERY_PF_RSRC = 0x0023, 79 HCLGE_OPC_QUERY_VF_RSRC = 0x0024, 80 HCLGE_OPC_GET_CFG_PARAM = 0x0025, 81 82 HCLGE_OPC_STATS_64_BIT = 0x0030, 83 HCLGE_OPC_STATS_32_BIT = 0x0031, 84 HCLGE_OPC_STATS_MAC = 0x0032, 85 86 HCLGE_OPC_QUERY_REG_NUM = 0x0040, 87 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041, 88 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042, 89 90 /* MAC command */ 91 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301, 92 HCLGE_OPC_CONFIG_AN_MODE = 0x0304, 93 HCLGE_OPC_QUERY_AN_RESULT = 0x0306, 94 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307, 95 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, 96 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309, 97 HCLGE_OPC_SERDES_LOOPBACK = 0x0315, 98 99 /* PFC/Pause commands */ 100 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701, 101 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702, 102 HCLGE_OPC_CFG_MAC_PARA = 0x0703, 103 HCLGE_OPC_CFG_PFC_PARA = 0x0704, 104 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, 105 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, 106 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, 107 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, 108 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709, 109 HCLGE_OPC_QOS_MAP = 0x070A, 110 111 /* ETS/scheduler commands */ 112 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804, 113 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805, 114 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806, 115 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807, 116 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808, 117 HCLGE_OPC_TM_PG_WEIGHT = 0x0809, 118 HCLGE_OPC_TM_QS_WEIGHT = 0x080A, 119 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B, 120 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C, 121 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D, 122 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E, 123 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F, 124 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810, 125 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812, 126 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, 127 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814, 128 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, 129 130 /* Packet buffer allocate commands */ 131 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901, 132 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, 133 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903, 134 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904, 135 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905, 136 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906, 137 138 /* TQP management command */ 139 HCLGE_OPC_SET_TQP_MAP = 0x0A01, 140 141 /* TQP commands */ 142 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01, 143 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02, 144 HCLGE_OPC_QUERY_TX_STATUS = 0x0B03, 145 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11, 146 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12, 147 HCLGE_OPC_QUERY_RX_STATUS = 0x0B13, 148 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16, 149 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17, 150 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 151 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22, 152 153 /* TSO command */ 154 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01, 155 156 /* RSS commands */ 157 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01, 158 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07, 159 HCLGE_OPC_RSS_TC_MODE = 0x0D08, 160 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02, 161 162 /* Promisuous mode command */ 163 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01, 164 165 /* Vlan offload commands */ 166 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01, 167 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02, 168 169 /* Interrupts commands */ 170 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503, 171 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504, 172 173 /* MAC commands */ 174 HCLGE_OPC_MAC_VLAN_ADD = 0x1000, 175 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001, 176 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002, 177 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003, 178 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004, 179 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010, 180 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011, 181 182 /* VLAN commands */ 183 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100, 184 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101, 185 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102, 186 187 /* Flow Director commands */ 188 HCLGE_OPC_FD_MODE_CTRL = 0x1200, 189 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201, 190 HCLGE_OPC_FD_KEY_CONFIG = 0x1202, 191 HCLGE_OPC_FD_TCAM_OP = 0x1203, 192 HCLGE_OPC_FD_AD_OP = 0x1204, 193 194 /* MDIO command */ 195 HCLGE_OPC_MDIO_CONFIG = 0x1900, 196 197 /* QCN commands */ 198 HCLGE_OPC_QCN_MOD_CFG = 0x1A01, 199 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02, 200 HCLGE_OPC_QCN_SHAPPING_IR_CFG = 0x1A03, 201 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04, 202 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05, 203 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06, 204 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07, 205 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08, 206 207 /* Mailbox command */ 208 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000, 209 210 /* Led command */ 211 HCLGE_OPC_LED_STATUS_CFG = 0xB000, 212 213 /* Error INT commands */ 214 HCLGE_TM_SCH_ECC_INT_EN = 0x0829, 215 HCLGE_TM_SCH_ECC_ERR_RINT_CMD = 0x082d, 216 HCLGE_TM_SCH_ECC_ERR_RINT_CE = 0x082f, 217 HCLGE_TM_SCH_ECC_ERR_RINT_NFE = 0x0830, 218 HCLGE_TM_SCH_ECC_ERR_RINT_FE = 0x0831, 219 HCLGE_TM_SCH_MBIT_ECC_INFO_CMD = 0x0833, 220 HCLGE_COMMON_ECC_INT_CFG = 0x1505, 221 HCLGE_IGU_EGU_TNL_INT_QUERY = 0x1802, 222 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803, 223 HCLGE_IGU_EGU_TNL_INT_CLR = 0x1804, 224 HCLGE_IGU_COMMON_INT_QUERY = 0x1805, 225 HCLGE_IGU_COMMON_INT_EN = 0x1806, 226 HCLGE_IGU_COMMON_INT_CLR = 0x1807, 227 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14, 228 HCLGE_TM_QCN_MEM_INT_INFO_CMD = 0x1A17, 229 HCLGE_PPP_CMD0_INT_CMD = 0x2100, 230 HCLGE_PPP_CMD1_INT_CMD = 0x2101, 231 HCLGE_NCSI_INT_QUERY = 0x2400, 232 HCLGE_NCSI_INT_EN = 0x2401, 233 HCLGE_NCSI_INT_CLR = 0x2402, 234 }; 235 236 #define HCLGE_TQP_REG_OFFSET 0x80000 237 #define HCLGE_TQP_REG_SIZE 0x200 238 239 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10 240 #define HCLGE_RCB_INIT_FLAG_EN_B 0 241 #define HCLGE_RCB_INIT_FLAG_FINI_B 8 242 struct hclge_config_rcb_init_cmd { 243 __le16 rcb_init_flag; 244 u8 rsv[22]; 245 }; 246 247 struct hclge_tqp_map_cmd { 248 __le16 tqp_id; /* Absolute tqp id for in this pf */ 249 u8 tqp_vf; /* VF id */ 250 #define HCLGE_TQP_MAP_TYPE_PF 0 251 #define HCLGE_TQP_MAP_TYPE_VF 1 252 #define HCLGE_TQP_MAP_TYPE_B 0 253 #define HCLGE_TQP_MAP_EN_B 1 254 u8 tqp_flag; /* Indicate it's pf or vf tqp */ 255 __le16 tqp_vid; /* Virtual id in this pf/vf */ 256 u8 rsv[18]; 257 }; 258 259 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10 260 261 enum hclge_int_type { 262 HCLGE_INT_TX, 263 HCLGE_INT_RX, 264 HCLGE_INT_EVENT, 265 }; 266 267 struct hclge_ctrl_vector_chain_cmd { 268 u8 int_vector_id; 269 u8 int_cause_num; 270 #define HCLGE_INT_TYPE_S 0 271 #define HCLGE_INT_TYPE_M GENMASK(1, 0) 272 #define HCLGE_TQP_ID_S 2 273 #define HCLGE_TQP_ID_M GENMASK(12, 2) 274 #define HCLGE_INT_GL_IDX_S 13 275 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13) 276 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD]; 277 u8 vfid; 278 u8 rsv; 279 }; 280 281 #define HCLGE_TC_NUM 8 282 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ 283 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ 284 struct hclge_tx_buff_alloc_cmd { 285 __le16 tx_pkt_buff[HCLGE_TC_NUM]; 286 u8 tx_buff_rsv[8]; 287 }; 288 289 struct hclge_rx_priv_buff_cmd { 290 __le16 buf_num[HCLGE_TC_NUM]; 291 __le16 shared_buf; 292 u8 rsv[6]; 293 }; 294 295 struct hclge_query_version_cmd { 296 __le32 firmware; 297 __le32 firmware_rsv[5]; 298 }; 299 300 #define HCLGE_RX_PRIV_EN_B 15 301 #define HCLGE_TC_NUM_ONE_DESC 4 302 struct hclge_priv_wl { 303 __le16 high; 304 __le16 low; 305 }; 306 307 struct hclge_rx_priv_wl_buf { 308 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC]; 309 }; 310 311 struct hclge_rx_com_thrd { 312 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC]; 313 }; 314 315 struct hclge_rx_com_wl { 316 struct hclge_priv_wl com_wl; 317 }; 318 319 struct hclge_waterline { 320 u32 low; 321 u32 high; 322 }; 323 324 struct hclge_tc_thrd { 325 u32 low; 326 u32 high; 327 }; 328 329 struct hclge_priv_buf { 330 struct hclge_waterline wl; /* Waterline for low and high*/ 331 u32 buf_size; /* TC private buffer size */ 332 u32 tx_buf_size; 333 u32 enable; /* Enable TC private buffer or not */ 334 }; 335 336 #define HCLGE_MAX_TC_NUM 8 337 struct hclge_shared_buf { 338 struct hclge_waterline self; 339 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM]; 340 u32 buf_size; 341 }; 342 343 struct hclge_pkt_buf_alloc { 344 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM]; 345 struct hclge_shared_buf s_buf; 346 }; 347 348 #define HCLGE_RX_COM_WL_EN_B 15 349 struct hclge_rx_com_wl_buf_cmd { 350 __le16 high_wl; 351 __le16 low_wl; 352 u8 rsv[20]; 353 }; 354 355 #define HCLGE_RX_PKT_EN_B 15 356 struct hclge_rx_pkt_buf_cmd { 357 __le16 high_pkt; 358 __le16 low_pkt; 359 u8 rsv[20]; 360 }; 361 362 #define HCLGE_PF_STATE_DONE_B 0 363 #define HCLGE_PF_STATE_MAIN_B 1 364 #define HCLGE_PF_STATE_BOND_B 2 365 #define HCLGE_PF_STATE_MAC_N_B 6 366 #define HCLGE_PF_MAC_NUM_MASK 0x3 367 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) 368 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) 369 struct hclge_func_status_cmd { 370 __le32 vf_rst_state[4]; 371 u8 pf_state; 372 u8 mac_id; 373 u8 rsv1; 374 u8 pf_cnt_in_mac; 375 u8 pf_num; 376 u8 vf_num; 377 u8 rsv[2]; 378 }; 379 380 struct hclge_pf_res_cmd { 381 __le16 tqp_num; 382 __le16 buf_size; 383 __le16 msixcap_localid_ba_nic; 384 __le16 msixcap_localid_ba_rocee; 385 #define HCLGE_MSIX_OFT_ROCEE_S 0 386 #define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0) 387 #define HCLGE_PF_VEC_NUM_S 0 388 #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0) 389 __le16 pf_intr_vector_number; 390 __le16 pf_own_fun_number; 391 __le32 rsv[3]; 392 }; 393 394 #define HCLGE_CFG_OFFSET_S 0 395 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0) 396 #define HCLGE_CFG_RD_LEN_S 24 397 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24) 398 #define HCLGE_CFG_RD_LEN_BYTES 16 399 #define HCLGE_CFG_RD_LEN_UNIT 4 400 401 #define HCLGE_CFG_VMDQ_S 0 402 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0) 403 #define HCLGE_CFG_TC_NUM_S 8 404 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8) 405 #define HCLGE_CFG_TQP_DESC_N_S 16 406 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16) 407 #define HCLGE_CFG_PHY_ADDR_S 0 408 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0) 409 #define HCLGE_CFG_MEDIA_TP_S 8 410 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8) 411 #define HCLGE_CFG_RX_BUF_LEN_S 16 412 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16) 413 #define HCLGE_CFG_MAC_ADDR_H_S 0 414 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0) 415 #define HCLGE_CFG_DEFAULT_SPEED_S 16 416 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16) 417 #define HCLGE_CFG_RSS_SIZE_S 24 418 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24) 419 #define HCLGE_CFG_SPEED_ABILITY_S 0 420 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0) 421 #define HCLGE_CFG_UMV_TBL_SPACE_S 16 422 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) 423 424 struct hclge_cfg_param_cmd { 425 __le32 offset; 426 __le32 rsv; 427 __le32 param[4]; 428 }; 429 430 #define HCLGE_MAC_MODE 0x0 431 #define HCLGE_DESC_NUM 0x40 432 433 #define HCLGE_ALLOC_VALID_B 0 434 struct hclge_vf_num_cmd { 435 u8 alloc_valid; 436 u8 rsv[23]; 437 }; 438 439 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4 440 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4 441 #define HCLGE_RSS_HASH_KEY_NUM 16 442 struct hclge_rss_config_cmd { 443 u8 hash_config; 444 u8 rsv[7]; 445 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM]; 446 }; 447 448 struct hclge_rss_input_tuple_cmd { 449 u8 ipv4_tcp_en; 450 u8 ipv4_udp_en; 451 u8 ipv4_sctp_en; 452 u8 ipv4_fragment_en; 453 u8 ipv6_tcp_en; 454 u8 ipv6_udp_en; 455 u8 ipv6_sctp_en; 456 u8 ipv6_fragment_en; 457 u8 rsv[16]; 458 }; 459 460 #define HCLGE_RSS_CFG_TBL_SIZE 16 461 462 struct hclge_rss_indirection_table_cmd { 463 __le16 start_table_index; 464 __le16 rss_set_bitmap; 465 u8 rsv[4]; 466 u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE]; 467 }; 468 469 #define HCLGE_RSS_TC_OFFSET_S 0 470 #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0) 471 #define HCLGE_RSS_TC_SIZE_S 12 472 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12) 473 #define HCLGE_RSS_TC_VALID_B 15 474 struct hclge_rss_tc_mode_cmd { 475 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM]; 476 u8 rsv[8]; 477 }; 478 479 #define HCLGE_LINK_STATUS_UP_B 0 480 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B) 481 struct hclge_link_status_cmd { 482 u8 status; 483 u8 rsv[23]; 484 }; 485 486 struct hclge_promisc_param { 487 u8 vf_id; 488 u8 enable; 489 }; 490 491 #define HCLGE_PROMISC_TX_EN_B BIT(4) 492 #define HCLGE_PROMISC_RX_EN_B BIT(5) 493 #define HCLGE_PROMISC_EN_B 1 494 #define HCLGE_PROMISC_EN_ALL 0x7 495 #define HCLGE_PROMISC_EN_UC 0x1 496 #define HCLGE_PROMISC_EN_MC 0x2 497 #define HCLGE_PROMISC_EN_BC 0x4 498 struct hclge_promisc_cfg_cmd { 499 u8 flag; 500 u8 vf_id; 501 __le16 rsv0; 502 u8 rsv1[20]; 503 }; 504 505 enum hclge_promisc_type { 506 HCLGE_UNICAST = 1, 507 HCLGE_MULTICAST = 2, 508 HCLGE_BROADCAST = 3, 509 }; 510 511 #define HCLGE_MAC_TX_EN_B 6 512 #define HCLGE_MAC_RX_EN_B 7 513 #define HCLGE_MAC_PAD_TX_B 11 514 #define HCLGE_MAC_PAD_RX_B 12 515 #define HCLGE_MAC_1588_TX_B 13 516 #define HCLGE_MAC_1588_RX_B 14 517 #define HCLGE_MAC_APP_LP_B 15 518 #define HCLGE_MAC_LINE_LP_B 16 519 #define HCLGE_MAC_FCS_TX_B 17 520 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18 521 #define HCLGE_MAC_RX_FCS_STRIP_B 19 522 #define HCLGE_MAC_RX_FCS_B 20 523 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21 524 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22 525 526 struct hclge_config_mac_mode_cmd { 527 __le32 txrx_pad_fcs_loop_en; 528 u8 rsv[20]; 529 }; 530 531 #define HCLGE_CFG_SPEED_S 0 532 #define HCLGE_CFG_SPEED_M GENMASK(5, 0) 533 534 #define HCLGE_CFG_DUPLEX_B 7 535 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B) 536 537 struct hclge_config_mac_speed_dup_cmd { 538 u8 speed_dup; 539 540 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0 541 u8 mac_change_fec_en; 542 u8 rsv[22]; 543 }; 544 545 #define HCLGE_QUERY_SPEED_S 3 546 #define HCLGE_QUERY_AN_B 0 547 #define HCLGE_QUERY_DUPLEX_B 2 548 549 #define HCLGE_QUERY_SPEED_M GENMASK(4, 0) 550 #define HCLGE_QUERY_AN_M BIT(HCLGE_QUERY_AN_B) 551 #define HCLGE_QUERY_DUPLEX_M BIT(HCLGE_QUERY_DUPLEX_B) 552 553 struct hclge_query_an_speed_dup_cmd { 554 u8 an_syn_dup_speed; 555 u8 pause; 556 u8 rsv[23]; 557 }; 558 559 #define HCLGE_RING_ID_MASK GENMASK(9, 0) 560 #define HCLGE_TQP_ENABLE_B 0 561 562 #define HCLGE_MAC_CFG_AN_EN_B 0 563 #define HCLGE_MAC_CFG_AN_INT_EN_B 1 564 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2 565 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3 566 #define HCLGE_MAC_CFG_AN_RST_B 4 567 568 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B) 569 570 struct hclge_config_auto_neg_cmd { 571 __le32 cfg_an_cmd_flag; 572 u8 rsv[20]; 573 }; 574 575 #define HCLGE_MAC_UPLINK_PORT 0x100 576 577 struct hclge_config_max_frm_size_cmd { 578 __le16 max_frm_size; 579 u8 min_frm_size; 580 u8 rsv[21]; 581 }; 582 583 enum hclge_mac_vlan_tbl_opcode { 584 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ 585 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */ 586 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ 587 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ 588 }; 589 590 #define HCLGE_MAC_VLAN_BIT0_EN_B 0 591 #define HCLGE_MAC_VLAN_BIT1_EN_B 1 592 #define HCLGE_MAC_EPORT_SW_EN_B 12 593 #define HCLGE_MAC_EPORT_TYPE_B 11 594 #define HCLGE_MAC_EPORT_VFID_S 3 595 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3) 596 #define HCLGE_MAC_EPORT_PFID_S 0 597 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0) 598 struct hclge_mac_vlan_tbl_entry_cmd { 599 u8 flags; 600 u8 resp_code; 601 __le16 vlan_tag; 602 __le32 mac_addr_hi32; 603 __le16 mac_addr_lo16; 604 __le16 rsv1; 605 u8 entry_type; 606 u8 mc_mac_en; 607 __le16 egress_port; 608 __le16 egress_queue; 609 u8 rsv2[6]; 610 }; 611 612 #define HCLGE_UMV_SPC_ALC_B 0 613 struct hclge_umv_spc_alc_cmd { 614 u8 allocate; 615 u8 rsv1[3]; 616 __le32 space_size; 617 u8 rsv2[16]; 618 }; 619 620 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0) 621 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1) 622 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2) 623 #define HCLGE_MAC_ETHERTYPE_LLDP 0x88cc 624 625 struct hclge_mac_mgr_tbl_entry_cmd { 626 u8 flags; 627 u8 resp_code; 628 __le16 vlan_tag; 629 __le32 mac_addr_hi32; 630 __le16 mac_addr_lo16; 631 __le16 rsv1; 632 __le16 ethter_type; 633 __le16 egress_port; 634 __le16 egress_queue; 635 u8 sw_port_id_aware; 636 u8 rsv2; 637 u8 i_port_bitmap; 638 u8 i_port_direction; 639 u8 rsv3[2]; 640 }; 641 642 struct hclge_mac_vlan_add_cmd { 643 __le16 flags; 644 __le16 mac_addr_hi16; 645 __le32 mac_addr_lo32; 646 __le32 mac_addr_msk_hi32; 647 __le16 mac_addr_msk_lo16; 648 __le16 vlan_tag; 649 __le16 ingress_port; 650 __le16 egress_port; 651 u8 rsv[4]; 652 }; 653 654 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0 655 struct hclge_mac_vlan_remove_cmd { 656 __le16 flags; 657 __le16 mac_addr_hi16; 658 __le32 mac_addr_lo32; 659 __le32 mac_addr_msk_hi32; 660 __le16 mac_addr_msk_lo16; 661 __le16 vlan_tag; 662 __le16 ingress_port; 663 __le16 egress_port; 664 u8 rsv[4]; 665 }; 666 667 struct hclge_vlan_filter_ctrl_cmd { 668 u8 vlan_type; 669 u8 vlan_fe; 670 u8 rsv[22]; 671 }; 672 673 struct hclge_vlan_filter_pf_cfg_cmd { 674 u8 vlan_offset; 675 u8 vlan_cfg; 676 u8 rsv[2]; 677 u8 vlan_offset_bitmap[20]; 678 }; 679 680 struct hclge_vlan_filter_vf_cfg_cmd { 681 __le16 vlan_id; 682 u8 resp_code; 683 u8 rsv; 684 u8 vlan_cfg; 685 u8 rsv1[3]; 686 u8 vf_bitmap[16]; 687 }; 688 689 #define HCLGE_ACCEPT_TAG1_B 0 690 #define HCLGE_ACCEPT_UNTAG1_B 1 691 #define HCLGE_PORT_INS_TAG1_EN_B 2 692 #define HCLGE_PORT_INS_TAG2_EN_B 3 693 #define HCLGE_CFG_NIC_ROCE_SEL_B 4 694 #define HCLGE_ACCEPT_TAG2_B 5 695 #define HCLGE_ACCEPT_UNTAG2_B 6 696 697 struct hclge_vport_vtag_tx_cfg_cmd { 698 u8 vport_vlan_cfg; 699 u8 vf_offset; 700 u8 rsv1[2]; 701 __le16 def_vlan_tag1; 702 __le16 def_vlan_tag2; 703 u8 vf_bitmap[8]; 704 u8 rsv2[8]; 705 }; 706 707 #define HCLGE_REM_TAG1_EN_B 0 708 #define HCLGE_REM_TAG2_EN_B 1 709 #define HCLGE_SHOW_TAG1_EN_B 2 710 #define HCLGE_SHOW_TAG2_EN_B 3 711 struct hclge_vport_vtag_rx_cfg_cmd { 712 u8 vport_vlan_cfg; 713 u8 vf_offset; 714 u8 rsv1[6]; 715 u8 vf_bitmap[8]; 716 u8 rsv2[8]; 717 }; 718 719 struct hclge_tx_vlan_type_cfg_cmd { 720 __le16 ot_vlan_type; 721 __le16 in_vlan_type; 722 u8 rsv[20]; 723 }; 724 725 struct hclge_rx_vlan_type_cfg_cmd { 726 __le16 ot_fst_vlan_type; 727 __le16 ot_sec_vlan_type; 728 __le16 in_fst_vlan_type; 729 __le16 in_sec_vlan_type; 730 u8 rsv[16]; 731 }; 732 733 struct hclge_cfg_com_tqp_queue_cmd { 734 __le16 tqp_id; 735 __le16 stream_id; 736 u8 enable; 737 u8 rsv[19]; 738 }; 739 740 struct hclge_cfg_tx_queue_pointer_cmd { 741 __le16 tqp_id; 742 __le16 tx_tail; 743 __le16 tx_head; 744 __le16 fbd_num; 745 __le16 ring_offset; 746 u8 rsv[14]; 747 }; 748 749 #define HCLGE_TSO_MSS_MIN_S 0 750 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0) 751 752 #define HCLGE_TSO_MSS_MAX_S 16 753 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16) 754 755 struct hclge_cfg_tso_status_cmd { 756 __le16 tso_mss_min; 757 __le16 tso_mss_max; 758 u8 rsv[20]; 759 }; 760 761 #define HCLGE_TSO_MSS_MIN 256 762 #define HCLGE_TSO_MSS_MAX 9668 763 764 #define HCLGE_TQP_RESET_B 0 765 struct hclge_reset_tqp_queue_cmd { 766 __le16 tqp_id; 767 u8 reset_req; 768 u8 ready_to_reset; 769 u8 rsv[20]; 770 }; 771 772 #define HCLGE_CFG_RESET_MAC_B 3 773 #define HCLGE_CFG_RESET_FUNC_B 7 774 struct hclge_reset_cmd { 775 u8 mac_func_reset; 776 u8 fun_reset_vfid; 777 u8 rsv[22]; 778 }; 779 780 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0) 781 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2) 782 #define HCLGE_CMD_SERDES_DONE_B BIT(0) 783 #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1) 784 struct hclge_serdes_lb_cmd { 785 u8 mask; 786 u8 enable; 787 u8 result; 788 u8 rsv[21]; 789 }; 790 791 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ 792 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ 793 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */ 794 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ 795 796 #define HCLGE_TYPE_CRQ 0 797 #define HCLGE_TYPE_CSQ 1 798 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000 799 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004 800 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008 801 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010 802 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014 803 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018 804 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c 805 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020 806 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024 807 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028 808 #define HCLGE_NIC_CMQ_EN_B 16 809 #define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B) 810 #define HCLGE_NIC_CMQ_DESC_NUM 1024 811 #define HCLGE_NIC_CMQ_DESC_NUM_S 3 812 813 #define HCLGE_LED_LOCATE_STATE_S 0 814 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0) 815 816 struct hclge_set_led_state_cmd { 817 u8 rsv1[3]; 818 u8 locate_led_config; 819 u8 rsv2[20]; 820 }; 821 822 struct hclge_get_fd_mode_cmd { 823 u8 mode; 824 u8 enable; 825 u8 rsv[22]; 826 }; 827 828 struct hclge_get_fd_allocation_cmd { 829 __le32 stage1_entry_num; 830 __le32 stage2_entry_num; 831 __le16 stage1_counter_num; 832 __le16 stage2_counter_num; 833 u8 rsv[12]; 834 }; 835 836 struct hclge_set_fd_key_config_cmd { 837 u8 stage; 838 u8 key_select; 839 u8 inner_sipv6_word_en; 840 u8 inner_dipv6_word_en; 841 u8 outer_sipv6_word_en; 842 u8 outer_dipv6_word_en; 843 u8 rsv1[2]; 844 __le32 tuple_mask; 845 __le32 meta_data_mask; 846 u8 rsv2[8]; 847 }; 848 849 #define HCLGE_FD_EPORT_SW_EN_B 0 850 struct hclge_fd_tcam_config_1_cmd { 851 u8 stage; 852 u8 xy_sel; 853 u8 port_info; 854 u8 rsv1[1]; 855 __le32 index; 856 u8 entry_vld; 857 u8 rsv2[7]; 858 u8 tcam_data[8]; 859 }; 860 861 struct hclge_fd_tcam_config_2_cmd { 862 u8 tcam_data[24]; 863 }; 864 865 struct hclge_fd_tcam_config_3_cmd { 866 u8 tcam_data[20]; 867 u8 rsv[4]; 868 }; 869 870 #define HCLGE_FD_AD_DROP_B 0 871 #define HCLGE_FD_AD_DIRECT_QID_B 1 872 #define HCLGE_FD_AD_QID_S 2 873 #define HCLGE_FD_AD_QID_M GENMASK(12, 2) 874 #define HCLGE_FD_AD_USE_COUNTER_B 12 875 #define HCLGE_FD_AD_COUNTER_NUM_S 13 876 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13) 877 #define HCLGE_FD_AD_NXT_STEP_B 20 878 #define HCLGE_FD_AD_NXT_KEY_S 21 879 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21) 880 #define HCLGE_FD_AD_WR_RULE_ID_B 0 881 #define HCLGE_FD_AD_RULE_ID_S 1 882 #define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1) 883 884 struct hclge_fd_ad_config_cmd { 885 u8 stage; 886 u8 rsv1[3]; 887 __le32 index; 888 __le64 ad_data; 889 u8 rsv2[8]; 890 }; 891 892 int hclge_cmd_init(struct hclge_dev *hdev); 893 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value) 894 { 895 writel(value, base + reg); 896 } 897 898 #define hclge_write_dev(a, reg, value) \ 899 hclge_write_reg((a)->io_base, (reg), (value)) 900 #define hclge_read_dev(a, reg) \ 901 hclge_read_reg((a)->io_base, (reg)) 902 903 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg) 904 { 905 u8 __iomem *reg_addr = READ_ONCE(base); 906 907 return readl(reg_addr + reg); 908 } 909 910 #define HCLGE_SEND_SYNC(flag) \ 911 ((flag) & HCLGE_CMD_FLAG_NO_INTR) 912 913 struct hclge_hw; 914 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num); 915 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc, 916 enum hclge_opcode_type opcode, bool is_read); 917 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); 918 919 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, 920 struct hclge_promisc_param *param); 921 922 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw, 923 struct hclge_desc *desc); 924 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw, 925 struct hclge_desc *desc); 926 927 void hclge_destroy_cmd_queue(struct hclge_hw *hw); 928 int hclge_cmd_queue_init(struct hclge_dev *hdev); 929 #endif 930