1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HNS3_ENET_H 5 #define __HNS3_ENET_H 6 7 #include <linux/if_vlan.h> 8 9 #include "hnae3.h" 10 11 enum hns3_nic_state { 12 HNS3_NIC_STATE_TESTING, 13 HNS3_NIC_STATE_RESETTING, 14 HNS3_NIC_STATE_INITED, 15 HNS3_NIC_STATE_DOWN, 16 HNS3_NIC_STATE_DISABLED, 17 HNS3_NIC_STATE_REMOVING, 18 HNS3_NIC_STATE_SERVICE_INITED, 19 HNS3_NIC_STATE_SERVICE_SCHED, 20 HNS3_NIC_STATE2_RESET_REQUESTED, 21 HNS3_NIC_STATE_MAX 22 }; 23 24 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000 25 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004 26 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008 27 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C 28 #define HNS3_RING_RX_RING_TAIL_REG 0x00018 29 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C 30 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020 31 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C 32 33 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040 34 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044 35 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048 36 #define HNS3_RING_TX_RING_TC_REG 0x00050 37 #define HNS3_RING_TX_RING_TAIL_REG 0x00058 38 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C 39 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060 40 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064 41 #define HNS3_RING_TX_RING_EBDNUM_REG 0x00068 42 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C 43 #define HNS3_RING_TX_RING_EBD_OFFSET_REG 0x00070 44 #define HNS3_RING_TX_RING_BD_ERR_REG 0x00074 45 #define HNS3_RING_EN_REG 0x00090 46 #define HNS3_RING_RX_EN_REG 0x00098 47 #define HNS3_RING_TX_EN_REG 0x000D4 48 49 #define HNS3_RX_HEAD_SIZE 256 50 51 #define HNS3_TX_TIMEOUT (5 * HZ) 52 #define HNS3_RING_NAME_LEN 16 53 #define HNS3_BUFFER_SIZE_2048 2048 54 #define HNS3_RING_MAX_PENDING 32760 55 #define HNS3_RING_MIN_PENDING 72 56 #define HNS3_RING_BD_MULTIPLE 8 57 /* max frame size of mac */ 58 #define HNS3_MAC_MAX_FRAME 9728 59 #define HNS3_MAX_MTU \ 60 (HNS3_MAC_MAX_FRAME - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN)) 61 62 #define HNS3_BD_SIZE_512_TYPE 0 63 #define HNS3_BD_SIZE_1024_TYPE 1 64 #define HNS3_BD_SIZE_2048_TYPE 2 65 #define HNS3_BD_SIZE_4096_TYPE 3 66 67 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1 68 #define HNS3_RX_FLAG_L3ID_IPV4 0x0 69 #define HNS3_RX_FLAG_L3ID_IPV6 0x1 70 #define HNS3_RX_FLAG_L4ID_UDP 0x0 71 #define HNS3_RX_FLAG_L4ID_TCP 0x1 72 73 #define HNS3_RXD_DMAC_S 0 74 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S) 75 #define HNS3_RXD_VLAN_S 2 76 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S) 77 #define HNS3_RXD_L3ID_S 4 78 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S) 79 #define HNS3_RXD_L4ID_S 8 80 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S) 81 #define HNS3_RXD_FRAG_B 12 82 #define HNS3_RXD_STRP_TAGP_S 13 83 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S) 84 85 #define HNS3_RXD_L2E_B 16 86 #define HNS3_RXD_L3E_B 17 87 #define HNS3_RXD_L4E_B 18 88 #define HNS3_RXD_TRUNCAT_B 19 89 #define HNS3_RXD_HOI_B 20 90 #define HNS3_RXD_DOI_B 21 91 #define HNS3_RXD_OL3E_B 22 92 #define HNS3_RXD_OL4E_B 23 93 #define HNS3_RXD_GRO_COUNT_S 24 94 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S) 95 #define HNS3_RXD_GRO_FIXID_B 30 96 #define HNS3_RXD_GRO_ECN_B 31 97 98 #define HNS3_RXD_ODMAC_S 0 99 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S) 100 #define HNS3_RXD_OVLAN_S 2 101 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S) 102 #define HNS3_RXD_OL3ID_S 4 103 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S) 104 #define HNS3_RXD_OL4ID_S 8 105 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S) 106 #define HNS3_RXD_FBHI_S 12 107 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S) 108 #define HNS3_RXD_FBLI_S 14 109 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S) 110 111 #define HNS3_RXD_BDTYPE_S 0 112 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S) 113 #define HNS3_RXD_VLD_B 4 114 #define HNS3_RXD_UDP0_B 5 115 #define HNS3_RXD_EXTEND_B 7 116 #define HNS3_RXD_FE_B 8 117 #define HNS3_RXD_LUM_B 9 118 #define HNS3_RXD_CRCP_B 10 119 #define HNS3_RXD_L3L4P_B 11 120 #define HNS3_RXD_TSIND_S 12 121 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S) 122 #define HNS3_RXD_LKBK_B 15 123 #define HNS3_RXD_GRO_SIZE_S 16 124 #define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S) 125 126 #define HNS3_TXD_L3T_S 0 127 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S) 128 #define HNS3_TXD_L4T_S 2 129 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S) 130 #define HNS3_TXD_L3CS_B 4 131 #define HNS3_TXD_L4CS_B 5 132 #define HNS3_TXD_VLAN_B 6 133 #define HNS3_TXD_TSO_B 7 134 135 #define HNS3_TXD_L2LEN_S 8 136 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S) 137 #define HNS3_TXD_L3LEN_S 16 138 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S) 139 #define HNS3_TXD_L4LEN_S 24 140 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S) 141 142 #define HNS3_TXD_OL3T_S 0 143 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S) 144 #define HNS3_TXD_OVLAN_B 2 145 #define HNS3_TXD_MACSEC_B 3 146 #define HNS3_TXD_TUNTYPE_S 4 147 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S) 148 149 #define HNS3_TXD_BDTYPE_S 0 150 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S) 151 #define HNS3_TXD_FE_B 4 152 #define HNS3_TXD_SC_S 5 153 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S) 154 #define HNS3_TXD_EXTEND_B 7 155 #define HNS3_TXD_VLD_B 8 156 #define HNS3_TXD_RI_B 9 157 #define HNS3_TXD_RA_B 10 158 #define HNS3_TXD_TSYN_B 11 159 #define HNS3_TXD_DECTTL_S 12 160 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S) 161 162 #define HNS3_TXD_MSS_S 0 163 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) 164 165 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0) 166 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1) 167 168 #define HNS3_VECTOR_NOT_INITED 0 169 #define HNS3_VECTOR_INITED 1 170 171 #define HNS3_MAX_BD_SIZE 65535 172 #define HNS3_MAX_TSO_BD_NUM 63U 173 #define HNS3_MAX_TSO_SIZE \ 174 (HNS3_MAX_BD_SIZE * HNS3_MAX_TSO_BD_NUM) 175 176 #define HNS3_MAX_NON_TSO_SIZE(max_non_tso_bd_num) \ 177 (HNS3_MAX_BD_SIZE * (max_non_tso_bd_num)) 178 179 #define HNS3_VECTOR_GL0_OFFSET 0x100 180 #define HNS3_VECTOR_GL1_OFFSET 0x200 181 #define HNS3_VECTOR_GL2_OFFSET 0x300 182 #define HNS3_VECTOR_RL_OFFSET 0x900 183 #define HNS3_VECTOR_RL_EN_B 6 184 185 #define HNS3_RING_EN_B 0 186 187 enum hns3_pkt_l2t_type { 188 HNS3_L2_TYPE_UNICAST, 189 HNS3_L2_TYPE_MULTICAST, 190 HNS3_L2_TYPE_BROADCAST, 191 HNS3_L2_TYPE_INVALID, 192 }; 193 194 enum hns3_pkt_l3t_type { 195 HNS3_L3T_NONE, 196 HNS3_L3T_IPV6, 197 HNS3_L3T_IPV4, 198 HNS3_L3T_RESERVED 199 }; 200 201 enum hns3_pkt_l4t_type { 202 HNS3_L4T_UNKNOWN, 203 HNS3_L4T_TCP, 204 HNS3_L4T_UDP, 205 HNS3_L4T_SCTP 206 }; 207 208 enum hns3_pkt_ol3t_type { 209 HNS3_OL3T_NONE, 210 HNS3_OL3T_IPV6, 211 HNS3_OL3T_IPV4_NO_CSUM, 212 HNS3_OL3T_IPV4_CSUM 213 }; 214 215 enum hns3_pkt_tun_type { 216 HNS3_TUN_NONE, 217 HNS3_TUN_MAC_IN_UDP, 218 HNS3_TUN_NVGRE, 219 HNS3_TUN_OTHER 220 }; 221 222 /* hardware spec ring buffer format */ 223 struct __packed hns3_desc { 224 __le64 addr; 225 union { 226 struct { 227 __le16 vlan_tag; 228 __le16 send_size; 229 union { 230 __le32 type_cs_vlan_tso_len; 231 struct { 232 __u8 type_cs_vlan_tso; 233 __u8 l2_len; 234 __u8 l3_len; 235 __u8 l4_len; 236 }; 237 }; 238 __le16 outer_vlan_tag; 239 __le16 tv; 240 241 union { 242 __le32 ol_type_vlan_len_msec; 243 struct { 244 __u8 ol_type_vlan_msec; 245 __u8 ol2_len; 246 __u8 ol3_len; 247 __u8 ol4_len; 248 }; 249 }; 250 251 __le32 paylen; 252 __le16 bdtp_fe_sc_vld_ra_ri; 253 __le16 mss; 254 } tx; 255 256 struct { 257 __le32 l234_info; 258 __le16 pkt_len; 259 __le16 size; 260 261 __le32 rss_hash; 262 __le16 fd_id; 263 __le16 vlan_tag; 264 265 union { 266 __le32 ol_info; 267 struct { 268 __le16 o_dm_vlan_id_fb; 269 __le16 ot_vlan_tag; 270 }; 271 }; 272 273 __le32 bd_base_info; 274 } rx; 275 }; 276 }; 277 278 struct hns3_desc_cb { 279 dma_addr_t dma; /* dma address of this desc */ 280 void *buf; /* cpu addr for a desc */ 281 282 /* priv data for the desc, e.g. skb when use with ip stack */ 283 void *priv; 284 u32 page_offset; 285 u32 length; /* length of the buffer */ 286 287 u16 reuse_flag; 288 289 /* desc type, used by the ring user to mark the type of the priv data */ 290 u16 type; 291 u16 pagecnt_bias; 292 }; 293 294 enum hns3_pkt_l3type { 295 HNS3_L3_TYPE_IPV4, 296 HNS3_L3_TYPE_IPV6, 297 HNS3_L3_TYPE_ARP, 298 HNS3_L3_TYPE_RARP, 299 HNS3_L3_TYPE_IPV4_OPT, 300 HNS3_L3_TYPE_IPV6_EXT, 301 HNS3_L3_TYPE_LLDP, 302 HNS3_L3_TYPE_BPDU, 303 HNS3_L3_TYPE_MAC_PAUSE, 304 HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/ 305 306 /* reserved for 0xA~0xB */ 307 308 HNS3_L3_TYPE_CNM = 0xc, 309 310 /* reserved for 0xD~0xE */ 311 312 HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */ 313 }; 314 315 enum hns3_pkt_l4type { 316 HNS3_L4_TYPE_UDP, 317 HNS3_L4_TYPE_TCP, 318 HNS3_L4_TYPE_GRE, 319 HNS3_L4_TYPE_SCTP, 320 HNS3_L4_TYPE_IGMP, 321 HNS3_L4_TYPE_ICMP, 322 323 /* reserved for 0x6~0xE */ 324 325 HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */ 326 }; 327 328 enum hns3_pkt_ol3type { 329 HNS3_OL3_TYPE_IPV4 = 0, 330 HNS3_OL3_TYPE_IPV6, 331 /* reserved for 0x2~0x3 */ 332 HNS3_OL3_TYPE_IPV4_OPT = 4, 333 HNS3_OL3_TYPE_IPV6_EXT, 334 335 /* reserved for 0x6~0xE */ 336 337 HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */ 338 }; 339 340 enum hns3_pkt_ol4type { 341 HNS3_OL4_TYPE_NO_TUN, 342 HNS3_OL4_TYPE_MAC_IN_UDP, 343 HNS3_OL4_TYPE_NVGRE, 344 HNS3_OL4_TYPE_UNKNOWN 345 }; 346 347 struct ring_stats { 348 u64 sw_err_cnt; 349 u64 seg_pkt_cnt; 350 union { 351 struct { 352 u64 tx_pkts; 353 u64 tx_bytes; 354 u64 tx_more; 355 u64 restart_queue; 356 u64 tx_busy; 357 u64 tx_copy; 358 u64 tx_vlan_err; 359 u64 tx_l4_proto_err; 360 u64 tx_l2l3l4_err; 361 u64 tx_tso_err; 362 }; 363 struct { 364 u64 rx_pkts; 365 u64 rx_bytes; 366 u64 rx_err_cnt; 367 u64 reuse_pg_cnt; 368 u64 err_pkt_len; 369 u64 err_bd_num; 370 u64 l2_err; 371 u64 l3l4_csum_err; 372 u64 rx_multicast; 373 u64 non_reuse_pg; 374 }; 375 }; 376 }; 377 378 struct hns3_enet_ring { 379 struct hns3_desc *desc; /* dma map address space */ 380 struct hns3_desc_cb *desc_cb; 381 struct hns3_enet_ring *next; 382 struct hns3_enet_tqp_vector *tqp_vector; 383 struct hnae3_queue *tqp; 384 int queue_index; 385 struct device *dev; /* will be used for DMA mapping of descriptors */ 386 387 /* statistic */ 388 struct ring_stats stats; 389 struct u64_stats_sync syncp; 390 391 dma_addr_t desc_dma_addr; 392 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 393 u16 desc_num; /* total number of desc */ 394 int next_to_use; /* idx of next spare desc */ 395 396 /* idx of lastest sent desc, the ring is empty when equal to 397 * next_to_use 398 */ 399 int next_to_clean; 400 union { 401 int last_to_use; /* last idx used by xmit */ 402 u32 pull_len; /* memcpy len for current rx packet */ 403 }; 404 u32 frag_num; 405 void *va; /* first buffer address for current packet */ 406 407 u32 flag; /* ring attribute */ 408 409 int pending_buf; 410 struct sk_buff *skb; 411 struct sk_buff *tail_skb; 412 } ____cacheline_internodealigned_in_smp; 413 414 enum hns3_flow_level_range { 415 HNS3_FLOW_LOW = 0, 416 HNS3_FLOW_MID = 1, 417 HNS3_FLOW_HIGH = 2, 418 HNS3_FLOW_ULTRA = 3, 419 }; 420 421 #define HNS3_INT_GL_MAX 0x1FE0 422 #define HNS3_INT_GL_50K 0x0014 423 #define HNS3_INT_GL_20K 0x0032 424 #define HNS3_INT_GL_18K 0x0036 425 #define HNS3_INT_GL_8K 0x007C 426 427 #define HNS3_INT_RL_MAX 0x00EC 428 #define HNS3_INT_RL_ENABLE_MASK 0x40 429 430 struct hns3_enet_coalesce { 431 u16 int_gl; 432 u8 gl_adapt_enable; 433 enum hns3_flow_level_range flow_level; 434 }; 435 436 struct hns3_enet_ring_group { 437 /* array of pointers to rings */ 438 struct hns3_enet_ring *ring; 439 u64 total_bytes; /* total bytes processed this group */ 440 u64 total_packets; /* total packets processed this group */ 441 u16 count; 442 struct hns3_enet_coalesce coal; 443 }; 444 445 struct hns3_enet_tqp_vector { 446 struct hnae3_handle *handle; 447 u8 __iomem *mask_addr; 448 int vector_irq; 449 int irq_init_flag; 450 451 u16 idx; /* index in the TQP vector array per handle. */ 452 453 struct napi_struct napi; 454 455 struct hns3_enet_ring_group rx_group; 456 struct hns3_enet_ring_group tx_group; 457 458 cpumask_t affinity_mask; 459 u16 num_tqps; /* total number of tqps in TQP vector */ 460 struct irq_affinity_notify affinity_notify; 461 462 char name[HNAE3_INT_NAME_LEN]; 463 464 unsigned long last_jiffies; 465 } ____cacheline_internodealigned_in_smp; 466 467 struct hns3_nic_priv { 468 struct hnae3_handle *ae_handle; 469 struct net_device *netdev; 470 struct device *dev; 471 472 /** 473 * the cb for nic to manage the ring buffer, the first half of the 474 * array is for tx_ring and vice versa for the second half 475 */ 476 struct hns3_enet_ring *ring; 477 struct hns3_enet_tqp_vector *tqp_vector; 478 u16 vector_num; 479 u8 max_non_tso_bd_num; 480 481 u64 tx_timeout_count; 482 483 unsigned long state; 484 485 struct hns3_enet_coalesce tx_coal; 486 struct hns3_enet_coalesce rx_coal; 487 }; 488 489 union l3_hdr_info { 490 struct iphdr *v4; 491 struct ipv6hdr *v6; 492 unsigned char *hdr; 493 }; 494 495 union l4_hdr_info { 496 struct tcphdr *tcp; 497 struct udphdr *udp; 498 struct gre_base_hdr *gre; 499 unsigned char *hdr; 500 }; 501 502 struct hns3_hw_error_info { 503 enum hnae3_hw_error_type type; 504 const char *msg; 505 }; 506 507 static inline int ring_space(struct hns3_enet_ring *ring) 508 { 509 /* This smp_load_acquire() pairs with smp_store_release() in 510 * hns3_nic_reclaim_one_desc called by hns3_clean_tx_ring. 511 */ 512 int begin = smp_load_acquire(&ring->next_to_clean); 513 int end = READ_ONCE(ring->next_to_use); 514 515 return ((end >= begin) ? (ring->desc_num - end + begin) : 516 (begin - end)) - 1; 517 } 518 519 static inline u32 hns3_read_reg(void __iomem *base, u32 reg) 520 { 521 return readl(base + reg); 522 } 523 524 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value) 525 { 526 u8 __iomem *reg_addr = READ_ONCE(base); 527 528 writel(value, reg_addr + reg); 529 } 530 531 #define hns3_read_dev(a, reg) \ 532 hns3_read_reg((a)->io_base, (reg)) 533 534 static inline bool hns3_nic_resetting(struct net_device *netdev) 535 { 536 struct hns3_nic_priv *priv = netdev_priv(netdev); 537 538 return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 539 } 540 541 #define hns3_write_dev(a, reg, value) \ 542 hns3_write_reg((a)->io_base, (reg), (value)) 543 544 #define ring_to_dev(ring) ((ring)->dev) 545 546 #define ring_to_netdev(ring) ((ring)->tqp_vector->napi.dev) 547 548 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \ 549 DMA_TO_DEVICE : DMA_FROM_DEVICE) 550 551 #define hns3_buf_size(_ring) ((_ring)->buf_size) 552 553 static inline unsigned int hns3_page_order(struct hns3_enet_ring *ring) 554 { 555 #if (PAGE_SIZE < 8192) 556 if (ring->buf_size > (PAGE_SIZE / 2)) 557 return 1; 558 #endif 559 return 0; 560 } 561 562 #define hns3_page_size(_ring) (PAGE_SIZE << hns3_page_order(_ring)) 563 564 /* iterator for handling rings in ring group */ 565 #define hns3_for_each_ring(pos, head) \ 566 for (pos = (head).ring; pos; pos = pos->next) 567 568 #define hns3_get_handle(ndev) \ 569 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle) 570 571 #define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1) 572 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2) 573 574 #define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2) 575 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4) 576 577 void hns3_ethtool_set_ops(struct net_device *netdev); 578 int hns3_set_channels(struct net_device *netdev, 579 struct ethtool_channels *ch); 580 581 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget); 582 int hns3_init_all_ring(struct hns3_nic_priv *priv); 583 int hns3_uninit_all_ring(struct hns3_nic_priv *priv); 584 int hns3_nic_reset_all_ring(struct hnae3_handle *h); 585 void hns3_fini_ring(struct hns3_enet_ring *ring); 586 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev); 587 bool hns3_is_phys_func(struct pci_dev *pdev); 588 int hns3_clean_rx_ring( 589 struct hns3_enet_ring *ring, int budget, 590 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)); 591 592 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 593 u32 gl_value); 594 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 595 u32 gl_value); 596 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 597 u32 rl_value); 598 599 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable); 600 void hns3_request_update_promisc_mode(struct hnae3_handle *handle); 601 602 #ifdef CONFIG_HNS3_DCB 603 void hns3_dcbnl_setup(struct hnae3_handle *handle); 604 #else 605 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {} 606 #endif 607 608 void hns3_dbg_init(struct hnae3_handle *handle); 609 void hns3_dbg_uninit(struct hnae3_handle *handle); 610 void hns3_dbg_register_debugfs(const char *debugfs_dir_name); 611 void hns3_dbg_unregister_debugfs(void); 612 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size); 613 #endif 614