1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #ifndef __HNS3_ENET_H 11 #define __HNS3_ENET_H 12 13 #include <linux/if_vlan.h> 14 15 #include "hnae3.h" 16 17 #define HNS3_MOD_VERSION "1.0" 18 19 extern const char hns3_driver_version[]; 20 21 enum hns3_nic_state { 22 HNS3_NIC_STATE_TESTING, 23 HNS3_NIC_STATE_RESETTING, 24 HNS3_NIC_STATE_REINITING, 25 HNS3_NIC_STATE_DOWN, 26 HNS3_NIC_STATE_DISABLED, 27 HNS3_NIC_STATE_REMOVING, 28 HNS3_NIC_STATE_SERVICE_INITED, 29 HNS3_NIC_STATE_SERVICE_SCHED, 30 HNS3_NIC_STATE2_RESET_REQUESTED, 31 HNS3_NIC_STATE_MAX 32 }; 33 34 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000 35 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004 36 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008 37 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C 38 #define HNS3_RING_RX_RING_TAIL_REG 0x00018 39 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C 40 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020 41 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C 42 43 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040 44 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044 45 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048 46 #define HNS3_RING_TX_RING_BD_LEN_REG 0x0004C 47 #define HNS3_RING_TX_RING_TAIL_REG 0x00058 48 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C 49 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060 50 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064 51 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C 52 53 #define HNS3_RING_PREFETCH_EN_REG 0x0007C 54 #define HNS3_RING_CFG_VF_NUM_REG 0x00080 55 #define HNS3_RING_ASID_REG 0x0008C 56 #define HNS3_RING_RX_VM_REG 0x00090 57 #define HNS3_RING_T0_BE_RST 0x00094 58 #define HNS3_RING_COULD_BE_RST 0x00098 59 #define HNS3_RING_WRR_WEIGHT_REG 0x0009c 60 61 #define HNS3_RING_INTMSK_RXWL_REG 0x000A0 62 #define HNS3_RING_INTSTS_RX_RING_REG 0x000A4 63 #define HNS3_RX_RING_INT_STS_REG 0x000A8 64 #define HNS3_RING_INTMSK_TXWL_REG 0x000AC 65 #define HNS3_RING_INTSTS_TX_RING_REG 0x000B0 66 #define HNS3_TX_RING_INT_STS_REG 0x000B4 67 #define HNS3_RING_INTMSK_RX_OVERTIME_REG 0x000B8 68 #define HNS3_RING_INTSTS_RX_OVERTIME_REG 0x000BC 69 #define HNS3_RING_INTMSK_TX_OVERTIME_REG 0x000C4 70 #define HNS3_RING_INTSTS_TX_OVERTIME_REG 0x000C8 71 72 #define HNS3_RING_MB_CTRL_REG 0x00100 73 #define HNS3_RING_MB_DATA_BASE_REG 0x00200 74 75 #define HNS3_TX_REG_OFFSET 0x40 76 77 #define HNS3_RX_HEAD_SIZE 256 78 79 #define HNS3_TX_TIMEOUT (5 * HZ) 80 #define HNS3_RING_NAME_LEN 16 81 #define HNS3_BUFFER_SIZE_2048 2048 82 #define HNS3_RING_MAX_PENDING 32768 83 #define HNS3_RING_MIN_PENDING 8 84 #define HNS3_RING_BD_MULTIPLE 8 85 #define HNS3_MAX_MTU 9728 86 87 #define HNS3_BD_SIZE_512_TYPE 0 88 #define HNS3_BD_SIZE_1024_TYPE 1 89 #define HNS3_BD_SIZE_2048_TYPE 2 90 #define HNS3_BD_SIZE_4096_TYPE 3 91 92 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1 93 #define HNS3_RX_FLAG_L3ID_IPV4 0x0 94 #define HNS3_RX_FLAG_L3ID_IPV6 0x1 95 #define HNS3_RX_FLAG_L4ID_UDP 0x0 96 #define HNS3_RX_FLAG_L4ID_TCP 0x1 97 98 #define HNS3_RXD_DMAC_S 0 99 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S) 100 #define HNS3_RXD_VLAN_S 2 101 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S) 102 #define HNS3_RXD_L3ID_S 4 103 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S) 104 #define HNS3_RXD_L4ID_S 8 105 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S) 106 #define HNS3_RXD_FRAG_B 12 107 #define HNS3_RXD_L2E_B 16 108 #define HNS3_RXD_L3E_B 17 109 #define HNS3_RXD_L4E_B 18 110 #define HNS3_RXD_TRUNCAT_B 19 111 #define HNS3_RXD_HOI_B 20 112 #define HNS3_RXD_DOI_B 21 113 #define HNS3_RXD_OL3E_B 22 114 #define HNS3_RXD_OL4E_B 23 115 116 #define HNS3_RXD_ODMAC_S 0 117 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S) 118 #define HNS3_RXD_OVLAN_S 2 119 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S) 120 #define HNS3_RXD_OL3ID_S 4 121 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S) 122 #define HNS3_RXD_OL4ID_S 8 123 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S) 124 #define HNS3_RXD_FBHI_S 12 125 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S) 126 #define HNS3_RXD_FBLI_S 14 127 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S) 128 129 #define HNS3_RXD_BDTYPE_S 0 130 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S) 131 #define HNS3_RXD_VLD_B 4 132 #define HNS3_RXD_UDP0_B 5 133 #define HNS3_RXD_EXTEND_B 7 134 #define HNS3_RXD_FE_B 8 135 #define HNS3_RXD_LUM_B 9 136 #define HNS3_RXD_CRCP_B 10 137 #define HNS3_RXD_L3L4P_B 11 138 #define HNS3_RXD_TSIND_S 12 139 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S) 140 #define HNS3_RXD_LKBK_B 15 141 #define HNS3_RXD_HDL_S 16 142 #define HNS3_RXD_HDL_M (0x7ff << HNS3_RXD_HDL_S) 143 #define HNS3_RXD_HSIND_B 31 144 145 #define HNS3_TXD_L3T_S 0 146 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S) 147 #define HNS3_TXD_L4T_S 2 148 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S) 149 #define HNS3_TXD_L3CS_B 4 150 #define HNS3_TXD_L4CS_B 5 151 #define HNS3_TXD_VLAN_B 6 152 #define HNS3_TXD_TSO_B 7 153 154 #define HNS3_TXD_L2LEN_S 8 155 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S) 156 #define HNS3_TXD_L3LEN_S 16 157 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S) 158 #define HNS3_TXD_L4LEN_S 24 159 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S) 160 161 #define HNS3_TXD_OL3T_S 0 162 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S) 163 #define HNS3_TXD_OVLAN_B 2 164 #define HNS3_TXD_MACSEC_B 3 165 #define HNS3_TXD_TUNTYPE_S 4 166 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S) 167 168 #define HNS3_TXD_BDTYPE_S 0 169 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S) 170 #define HNS3_TXD_FE_B 4 171 #define HNS3_TXD_SC_S 5 172 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S) 173 #define HNS3_TXD_EXTEND_B 7 174 #define HNS3_TXD_VLD_B 8 175 #define HNS3_TXD_RI_B 9 176 #define HNS3_TXD_RA_B 10 177 #define HNS3_TXD_TSYN_B 11 178 #define HNS3_TXD_DECTTL_S 12 179 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S) 180 181 #define HNS3_TXD_MSS_S 0 182 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) 183 184 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0) 185 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1) 186 187 #define HNS3_VECTOR_NOT_INITED 0 188 #define HNS3_VECTOR_INITED 1 189 190 #define HNS3_MAX_BD_SIZE 65535 191 #define HNS3_MAX_BD_PER_FRAG 8 192 #define HNS3_MAX_BD_PER_PKT MAX_SKB_FRAGS 193 194 #define HNS3_VECTOR_GL0_OFFSET 0x100 195 #define HNS3_VECTOR_GL1_OFFSET 0x200 196 #define HNS3_VECTOR_GL2_OFFSET 0x300 197 #define HNS3_VECTOR_RL_OFFSET 0x900 198 #define HNS3_VECTOR_RL_EN_B 6 199 200 enum hns3_pkt_l3t_type { 201 HNS3_L3T_NONE, 202 HNS3_L3T_IPV6, 203 HNS3_L3T_IPV4, 204 HNS3_L3T_RESERVED 205 }; 206 207 enum hns3_pkt_l4t_type { 208 HNS3_L4T_UNKNOWN, 209 HNS3_L4T_TCP, 210 HNS3_L4T_UDP, 211 HNS3_L4T_SCTP 212 }; 213 214 enum hns3_pkt_ol3t_type { 215 HNS3_OL3T_NONE, 216 HNS3_OL3T_IPV6, 217 HNS3_OL3T_IPV4_NO_CSUM, 218 HNS3_OL3T_IPV4_CSUM 219 }; 220 221 enum hns3_pkt_tun_type { 222 HNS3_TUN_NONE, 223 HNS3_TUN_MAC_IN_UDP, 224 HNS3_TUN_NVGRE, 225 HNS3_TUN_OTHER 226 }; 227 228 /* hardware spec ring buffer format */ 229 struct __packed hns3_desc { 230 __le64 addr; 231 union { 232 struct { 233 __le16 vlan_tag; 234 __le16 send_size; 235 union { 236 __le32 type_cs_vlan_tso_len; 237 struct { 238 __u8 type_cs_vlan_tso; 239 __u8 l2_len; 240 __u8 l3_len; 241 __u8 l4_len; 242 }; 243 }; 244 __le16 outer_vlan_tag; 245 __le16 tv; 246 247 union { 248 __le32 ol_type_vlan_len_msec; 249 struct { 250 __u8 ol_type_vlan_msec; 251 __u8 ol2_len; 252 __u8 ol3_len; 253 __u8 ol4_len; 254 }; 255 }; 256 257 __le32 paylen; 258 __le16 bdtp_fe_sc_vld_ra_ri; 259 __le16 mss; 260 } tx; 261 262 struct { 263 __le32 l234_info; 264 __le16 pkt_len; 265 __le16 size; 266 267 __le32 rss_hash; 268 __le16 fd_id; 269 __le16 vlan_tag; 270 271 union { 272 __le32 ol_info; 273 struct { 274 __le16 o_dm_vlan_id_fb; 275 __le16 ot_vlan_tag; 276 }; 277 }; 278 279 __le32 bd_base_info; 280 } rx; 281 }; 282 }; 283 284 struct hns3_desc_cb { 285 dma_addr_t dma; /* dma address of this desc */ 286 void *buf; /* cpu addr for a desc */ 287 288 /* priv data for the desc, e.g. skb when use with ip stack*/ 289 void *priv; 290 u16 page_offset; 291 u16 reuse_flag; 292 293 u32 length; /* length of the buffer */ 294 295 /* desc type, used by the ring user to mark the type of the priv data */ 296 u16 type; 297 }; 298 299 enum hns3_pkt_l3type { 300 HNS3_L3_TYPE_IPV4, 301 HNS3_L3_TYPE_IPV6, 302 HNS3_L3_TYPE_ARP, 303 HNS3_L3_TYPE_RARP, 304 HNS3_L3_TYPE_IPV4_OPT, 305 HNS3_L3_TYPE_IPV6_EXT, 306 HNS3_L3_TYPE_LLDP, 307 HNS3_L3_TYPE_BPDU, 308 HNS3_L3_TYPE_MAC_PAUSE, 309 HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/ 310 311 /* reserved for 0xA~0xB*/ 312 313 HNS3_L3_TYPE_CNM = 0xc, 314 315 /* reserved for 0xD~0xE*/ 316 317 HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */ 318 }; 319 320 enum hns3_pkt_l4type { 321 HNS3_L4_TYPE_UDP, 322 HNS3_L4_TYPE_TCP, 323 HNS3_L4_TYPE_GRE, 324 HNS3_L4_TYPE_SCTP, 325 HNS3_L4_TYPE_IGMP, 326 HNS3_L4_TYPE_ICMP, 327 328 /* reserved for 0x6~0xE */ 329 330 HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */ 331 }; 332 333 enum hns3_pkt_ol3type { 334 HNS3_OL3_TYPE_IPV4 = 0, 335 HNS3_OL3_TYPE_IPV6, 336 /* reserved for 0x2~0x3 */ 337 HNS3_OL3_TYPE_IPV4_OPT = 4, 338 HNS3_OL3_TYPE_IPV6_EXT, 339 340 /* reserved for 0x6~0xE*/ 341 342 HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */ 343 }; 344 345 enum hns3_pkt_ol4type { 346 HNS3_OL4_TYPE_NO_TUN, 347 HNS3_OL4_TYPE_MAC_IN_UDP, 348 HNS3_OL4_TYPE_NVGRE, 349 HNS3_OL4_TYPE_UNKNOWN 350 }; 351 352 struct ring_stats { 353 u64 io_err_cnt; 354 u64 sw_err_cnt; 355 u64 seg_pkt_cnt; 356 union { 357 struct { 358 u64 tx_pkts; 359 u64 tx_bytes; 360 u64 tx_err_cnt; 361 u64 restart_queue; 362 u64 tx_busy; 363 }; 364 struct { 365 u64 rx_pkts; 366 u64 rx_bytes; 367 u64 rx_err_cnt; 368 u64 reuse_pg_cnt; 369 u64 err_pkt_len; 370 u64 non_vld_descs; 371 u64 err_bd_num; 372 u64 l2_err; 373 u64 l3l4_csum_err; 374 }; 375 }; 376 }; 377 378 struct hns3_enet_ring { 379 u8 __iomem *io_base; /* base io address for the ring */ 380 struct hns3_desc *desc; /* dma map address space */ 381 struct hns3_desc_cb *desc_cb; 382 struct hns3_enet_ring *next; 383 struct hns3_enet_tqp_vector *tqp_vector; 384 struct hnae3_queue *tqp; 385 char ring_name[HNS3_RING_NAME_LEN]; 386 struct device *dev; /* will be used for DMA mapping of descriptors */ 387 388 /* statistic */ 389 struct ring_stats stats; 390 struct u64_stats_sync syncp; 391 392 dma_addr_t desc_dma_addr; 393 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 394 u16 desc_num; /* total number of desc */ 395 u16 max_desc_num_per_pkt; 396 u16 max_raw_data_sz_per_desc; 397 u16 max_pkt_size; 398 int next_to_use; /* idx of next spare desc */ 399 400 /* idx of lastest sent desc, the ring is empty when equal to 401 * next_to_use 402 */ 403 int next_to_clean; 404 405 u32 flag; /* ring attribute */ 406 int irq_init_flag; 407 408 int numa_node; 409 cpumask_t affinity_mask; 410 }; 411 412 struct hns_queue; 413 414 struct hns3_nic_ring_data { 415 struct hns3_enet_ring *ring; 416 struct napi_struct napi; 417 int queue_index; 418 int (*poll_one)(struct hns3_nic_ring_data *, int, void *); 419 void (*ex_process)(struct hns3_nic_ring_data *, struct sk_buff *); 420 void (*fini_process)(struct hns3_nic_ring_data *); 421 }; 422 423 struct hns3_nic_ops { 424 int (*fill_desc)(struct hns3_enet_ring *ring, void *priv, 425 int size, dma_addr_t dma, int frag_end, 426 enum hns_desc_type type); 427 int (*maybe_stop_tx)(struct sk_buff **out_skb, 428 int *bnum, struct hns3_enet_ring *ring); 429 void (*get_rxd_bnum)(u32 bnum_flag, int *out_bnum); 430 }; 431 432 enum hns3_flow_level_range { 433 HNS3_FLOW_LOW = 0, 434 HNS3_FLOW_MID = 1, 435 HNS3_FLOW_HIGH = 2, 436 HNS3_FLOW_ULTRA = 3, 437 }; 438 439 enum hns3_link_mode_bits { 440 HNS3_LM_FIBRE_BIT = BIT(0), 441 HNS3_LM_AUTONEG_BIT = BIT(1), 442 HNS3_LM_TP_BIT = BIT(2), 443 HNS3_LM_PAUSE_BIT = BIT(3), 444 HNS3_LM_BACKPLANE_BIT = BIT(4), 445 HNS3_LM_10BASET_HALF_BIT = BIT(5), 446 HNS3_LM_10BASET_FULL_BIT = BIT(6), 447 HNS3_LM_100BASET_HALF_BIT = BIT(7), 448 HNS3_LM_100BASET_FULL_BIT = BIT(8), 449 HNS3_LM_1000BASET_FULL_BIT = BIT(9), 450 HNS3_LM_10000BASEKR_FULL_BIT = BIT(10), 451 HNS3_LM_25000BASEKR_FULL_BIT = BIT(11), 452 HNS3_LM_40000BASELR4_FULL_BIT = BIT(12), 453 HNS3_LM_50000BASEKR2_FULL_BIT = BIT(13), 454 HNS3_LM_100000BASEKR4_FULL_BIT = BIT(14), 455 HNS3_LM_COUNT = 15 456 }; 457 458 #define HNS3_INT_GL_MAX 0x1FE0 459 #define HNS3_INT_GL_50K 0x0014 460 #define HNS3_INT_GL_20K 0x0032 461 #define HNS3_INT_GL_18K 0x0036 462 #define HNS3_INT_GL_8K 0x007C 463 464 #define HNS3_INT_RL_MAX 0x00EC 465 #define HNS3_INT_RL_ENABLE_MASK 0x40 466 467 #define HNS3_INT_ADAPT_DOWN_START 100 468 469 struct hns3_enet_coalesce { 470 u16 int_gl; 471 u8 gl_adapt_enable; 472 enum hns3_flow_level_range flow_level; 473 }; 474 475 struct hns3_enet_ring_group { 476 /* array of pointers to rings */ 477 struct hns3_enet_ring *ring; 478 u64 total_bytes; /* total bytes processed this group */ 479 u64 total_packets; /* total packets processed this group */ 480 u16 count; 481 struct hns3_enet_coalesce coal; 482 }; 483 484 struct hns3_enet_tqp_vector { 485 struct hnae3_handle *handle; 486 u8 __iomem *mask_addr; 487 int vector_irq; 488 int irq_init_flag; 489 490 u16 idx; /* index in the TQP vector array per handle. */ 491 492 struct napi_struct napi; 493 494 struct hns3_enet_ring_group rx_group; 495 struct hns3_enet_ring_group tx_group; 496 497 u16 num_tqps; /* total number of tqps in TQP vector */ 498 499 cpumask_t affinity_mask; 500 char name[HNAE3_INT_NAME_LEN]; 501 502 /* when 0 should adjust interrupt coalesce parameter */ 503 u8 int_adapt_down; 504 unsigned long last_jiffies; 505 } ____cacheline_internodealigned_in_smp; 506 507 enum hns3_udp_tnl_type { 508 HNS3_UDP_TNL_VXLAN, 509 HNS3_UDP_TNL_GENEVE, 510 HNS3_UDP_TNL_MAX, 511 }; 512 513 struct hns3_udp_tunnel { 514 u16 dst_port; 515 int used; 516 }; 517 518 struct hns3_nic_priv { 519 struct hnae3_handle *ae_handle; 520 u32 enet_ver; 521 u32 port_id; 522 struct net_device *netdev; 523 struct device *dev; 524 struct hns3_nic_ops ops; 525 526 /** 527 * the cb for nic to manage the ring buffer, the first half of the 528 * array is for tx_ring and vice versa for the second half 529 */ 530 struct hns3_nic_ring_data *ring_data; 531 struct hns3_enet_tqp_vector *tqp_vector; 532 u16 vector_num; 533 534 /* The most recently read link state */ 535 int link; 536 u64 tx_timeout_count; 537 538 unsigned long state; 539 540 struct timer_list service_timer; 541 542 struct work_struct service_task; 543 544 struct notifier_block notifier_block; 545 /* Vxlan/Geneve information */ 546 struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX]; 547 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 548 }; 549 550 union l3_hdr_info { 551 struct iphdr *v4; 552 struct ipv6hdr *v6; 553 unsigned char *hdr; 554 }; 555 556 union l4_hdr_info { 557 struct tcphdr *tcp; 558 struct udphdr *udp; 559 unsigned char *hdr; 560 }; 561 562 /* the distance between [begin, end) in a ring buffer 563 * note: there is a unuse slot between the begin and the end 564 */ 565 static inline int ring_dist(struct hns3_enet_ring *ring, int begin, int end) 566 { 567 return (end - begin + ring->desc_num) % ring->desc_num; 568 } 569 570 static inline int ring_space(struct hns3_enet_ring *ring) 571 { 572 return ring->desc_num - 573 ring_dist(ring, ring->next_to_clean, ring->next_to_use) - 1; 574 } 575 576 static inline int is_ring_empty(struct hns3_enet_ring *ring) 577 { 578 return ring->next_to_use == ring->next_to_clean; 579 } 580 581 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value) 582 { 583 u8 __iomem *reg_addr = READ_ONCE(base); 584 585 writel(value, reg_addr + reg); 586 } 587 588 #define hns3_write_dev(a, reg, value) \ 589 hns3_write_reg((a)->io_base, (reg), (value)) 590 591 #define hnae_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \ 592 (tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG) 593 594 #define ring_to_dev(ring) (&(ring)->tqp->handle->pdev->dev) 595 596 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \ 597 DMA_TO_DEVICE : DMA_FROM_DEVICE) 598 599 #define tx_ring_data(priv, idx) ((priv)->ring_data[idx]) 600 601 #define hnae_buf_size(_ring) ((_ring)->buf_size) 602 #define hnae_page_order(_ring) (get_order(hnae_buf_size(_ring))) 603 #define hnae_page_size(_ring) (PAGE_SIZE << hnae_page_order(_ring)) 604 605 /* iterator for handling rings in ring group */ 606 #define hns3_for_each_ring(pos, head) \ 607 for (pos = (head).ring; pos; pos = pos->next) 608 609 #define hns3_get_handle(ndev) \ 610 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle) 611 612 #define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1) 613 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2) 614 615 #define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2) 616 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4) 617 618 void hns3_ethtool_set_ops(struct net_device *netdev); 619 int hns3_set_channels(struct net_device *netdev, 620 struct ethtool_channels *ch); 621 622 bool hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget); 623 int hns3_init_all_ring(struct hns3_nic_priv *priv); 624 int hns3_uninit_all_ring(struct hns3_nic_priv *priv); 625 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev); 626 int hns3_clean_rx_ring( 627 struct hns3_enet_ring *ring, int budget, 628 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)); 629 630 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 631 u32 gl_value); 632 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 633 u32 gl_value); 634 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 635 u32 rl_value); 636 637 #ifdef CONFIG_HNS3_DCB 638 void hns3_dcbnl_setup(struct hnae3_handle *handle); 639 #else 640 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {} 641 #endif 642 643 #endif 644