1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #ifndef __HNS3_ENET_H 11 #define __HNS3_ENET_H 12 13 #include <linux/if_vlan.h> 14 15 #include "hnae3.h" 16 17 extern const char hns3_driver_version[]; 18 19 enum hns3_nic_state { 20 HNS3_NIC_STATE_TESTING, 21 HNS3_NIC_STATE_RESETTING, 22 HNS3_NIC_STATE_REINITING, 23 HNS3_NIC_STATE_DOWN, 24 HNS3_NIC_STATE_DISABLED, 25 HNS3_NIC_STATE_REMOVING, 26 HNS3_NIC_STATE_SERVICE_INITED, 27 HNS3_NIC_STATE_SERVICE_SCHED, 28 HNS3_NIC_STATE2_RESET_REQUESTED, 29 HNS3_NIC_STATE_MAX 30 }; 31 32 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000 33 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004 34 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008 35 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C 36 #define HNS3_RING_RX_RING_TAIL_REG 0x00018 37 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C 38 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020 39 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C 40 41 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040 42 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044 43 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048 44 #define HNS3_RING_TX_RING_BD_LEN_REG 0x0004C 45 #define HNS3_RING_TX_RING_TAIL_REG 0x00058 46 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C 47 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060 48 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064 49 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C 50 51 #define HNS3_RING_PREFETCH_EN_REG 0x0007C 52 #define HNS3_RING_CFG_VF_NUM_REG 0x00080 53 #define HNS3_RING_ASID_REG 0x0008C 54 #define HNS3_RING_RX_VM_REG 0x00090 55 #define HNS3_RING_T0_BE_RST 0x00094 56 #define HNS3_RING_COULD_BE_RST 0x00098 57 #define HNS3_RING_WRR_WEIGHT_REG 0x0009c 58 59 #define HNS3_RING_INTMSK_RXWL_REG 0x000A0 60 #define HNS3_RING_INTSTS_RX_RING_REG 0x000A4 61 #define HNS3_RX_RING_INT_STS_REG 0x000A8 62 #define HNS3_RING_INTMSK_TXWL_REG 0x000AC 63 #define HNS3_RING_INTSTS_TX_RING_REG 0x000B0 64 #define HNS3_TX_RING_INT_STS_REG 0x000B4 65 #define HNS3_RING_INTMSK_RX_OVERTIME_REG 0x000B8 66 #define HNS3_RING_INTSTS_RX_OVERTIME_REG 0x000BC 67 #define HNS3_RING_INTMSK_TX_OVERTIME_REG 0x000C4 68 #define HNS3_RING_INTSTS_TX_OVERTIME_REG 0x000C8 69 70 #define HNS3_RING_MB_CTRL_REG 0x00100 71 #define HNS3_RING_MB_DATA_BASE_REG 0x00200 72 73 #define HNS3_TX_REG_OFFSET 0x40 74 75 #define HNS3_RX_HEAD_SIZE 256 76 77 #define HNS3_TX_TIMEOUT (5 * HZ) 78 #define HNS3_RING_NAME_LEN 16 79 #define HNS3_BUFFER_SIZE_2048 2048 80 #define HNS3_RING_MAX_PENDING 32768 81 #define HNS3_RING_MIN_PENDING 8 82 #define HNS3_RING_BD_MULTIPLE 8 83 #define HNS3_MAX_MTU 9728 84 85 #define HNS3_BD_SIZE_512_TYPE 0 86 #define HNS3_BD_SIZE_1024_TYPE 1 87 #define HNS3_BD_SIZE_2048_TYPE 2 88 #define HNS3_BD_SIZE_4096_TYPE 3 89 90 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1 91 #define HNS3_RX_FLAG_L3ID_IPV4 0x0 92 #define HNS3_RX_FLAG_L3ID_IPV6 0x1 93 #define HNS3_RX_FLAG_L4ID_UDP 0x0 94 #define HNS3_RX_FLAG_L4ID_TCP 0x1 95 96 #define HNS3_RXD_DMAC_S 0 97 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S) 98 #define HNS3_RXD_VLAN_S 2 99 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S) 100 #define HNS3_RXD_L3ID_S 4 101 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S) 102 #define HNS3_RXD_L4ID_S 8 103 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S) 104 #define HNS3_RXD_FRAG_B 12 105 #define HNS3_RXD_L2E_B 16 106 #define HNS3_RXD_L3E_B 17 107 #define HNS3_RXD_L4E_B 18 108 #define HNS3_RXD_TRUNCAT_B 19 109 #define HNS3_RXD_HOI_B 20 110 #define HNS3_RXD_DOI_B 21 111 #define HNS3_RXD_OL3E_B 22 112 #define HNS3_RXD_OL4E_B 23 113 114 #define HNS3_RXD_ODMAC_S 0 115 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S) 116 #define HNS3_RXD_OVLAN_S 2 117 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S) 118 #define HNS3_RXD_OL3ID_S 4 119 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S) 120 #define HNS3_RXD_OL4ID_S 8 121 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S) 122 #define HNS3_RXD_FBHI_S 12 123 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S) 124 #define HNS3_RXD_FBLI_S 14 125 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S) 126 127 #define HNS3_RXD_BDTYPE_S 0 128 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S) 129 #define HNS3_RXD_VLD_B 4 130 #define HNS3_RXD_UDP0_B 5 131 #define HNS3_RXD_EXTEND_B 7 132 #define HNS3_RXD_FE_B 8 133 #define HNS3_RXD_LUM_B 9 134 #define HNS3_RXD_CRCP_B 10 135 #define HNS3_RXD_L3L4P_B 11 136 #define HNS3_RXD_TSIND_S 12 137 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S) 138 #define HNS3_RXD_LKBK_B 15 139 #define HNS3_RXD_HDL_S 16 140 #define HNS3_RXD_HDL_M (0x7ff << HNS3_RXD_HDL_S) 141 #define HNS3_RXD_HSIND_B 31 142 143 #define HNS3_TXD_L3T_S 0 144 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S) 145 #define HNS3_TXD_L4T_S 2 146 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S) 147 #define HNS3_TXD_L3CS_B 4 148 #define HNS3_TXD_L4CS_B 5 149 #define HNS3_TXD_VLAN_B 6 150 #define HNS3_TXD_TSO_B 7 151 152 #define HNS3_TXD_L2LEN_S 8 153 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S) 154 #define HNS3_TXD_L3LEN_S 16 155 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S) 156 #define HNS3_TXD_L4LEN_S 24 157 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S) 158 159 #define HNS3_TXD_OL3T_S 0 160 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S) 161 #define HNS3_TXD_OVLAN_B 2 162 #define HNS3_TXD_MACSEC_B 3 163 #define HNS3_TXD_TUNTYPE_S 4 164 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S) 165 166 #define HNS3_TXD_BDTYPE_S 0 167 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S) 168 #define HNS3_TXD_FE_B 4 169 #define HNS3_TXD_SC_S 5 170 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S) 171 #define HNS3_TXD_EXTEND_B 7 172 #define HNS3_TXD_VLD_B 8 173 #define HNS3_TXD_RI_B 9 174 #define HNS3_TXD_RA_B 10 175 #define HNS3_TXD_TSYN_B 11 176 #define HNS3_TXD_DECTTL_S 12 177 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S) 178 179 #define HNS3_TXD_MSS_S 0 180 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) 181 182 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0) 183 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1) 184 185 #define HNS3_VECTOR_NOT_INITED 0 186 #define HNS3_VECTOR_INITED 1 187 188 #define HNS3_MAX_BD_SIZE 65535 189 #define HNS3_MAX_BD_PER_FRAG 8 190 #define HNS3_MAX_BD_PER_PKT MAX_SKB_FRAGS 191 192 #define HNS3_VECTOR_GL0_OFFSET 0x100 193 #define HNS3_VECTOR_GL1_OFFSET 0x200 194 #define HNS3_VECTOR_GL2_OFFSET 0x300 195 #define HNS3_VECTOR_RL_OFFSET 0x900 196 #define HNS3_VECTOR_RL_EN_B 6 197 198 enum hns3_pkt_l3t_type { 199 HNS3_L3T_NONE, 200 HNS3_L3T_IPV6, 201 HNS3_L3T_IPV4, 202 HNS3_L3T_RESERVED 203 }; 204 205 enum hns3_pkt_l4t_type { 206 HNS3_L4T_UNKNOWN, 207 HNS3_L4T_TCP, 208 HNS3_L4T_UDP, 209 HNS3_L4T_SCTP 210 }; 211 212 enum hns3_pkt_ol3t_type { 213 HNS3_OL3T_NONE, 214 HNS3_OL3T_IPV6, 215 HNS3_OL3T_IPV4_NO_CSUM, 216 HNS3_OL3T_IPV4_CSUM 217 }; 218 219 enum hns3_pkt_tun_type { 220 HNS3_TUN_NONE, 221 HNS3_TUN_MAC_IN_UDP, 222 HNS3_TUN_NVGRE, 223 HNS3_TUN_OTHER 224 }; 225 226 /* hardware spec ring buffer format */ 227 struct __packed hns3_desc { 228 __le64 addr; 229 union { 230 struct { 231 __le16 vlan_tag; 232 __le16 send_size; 233 union { 234 __le32 type_cs_vlan_tso_len; 235 struct { 236 __u8 type_cs_vlan_tso; 237 __u8 l2_len; 238 __u8 l3_len; 239 __u8 l4_len; 240 }; 241 }; 242 __le16 outer_vlan_tag; 243 __le16 tv; 244 245 union { 246 __le32 ol_type_vlan_len_msec; 247 struct { 248 __u8 ol_type_vlan_msec; 249 __u8 ol2_len; 250 __u8 ol3_len; 251 __u8 ol4_len; 252 }; 253 }; 254 255 __le32 paylen; 256 __le16 bdtp_fe_sc_vld_ra_ri; 257 __le16 mss; 258 } tx; 259 260 struct { 261 __le32 l234_info; 262 __le16 pkt_len; 263 __le16 size; 264 265 __le32 rss_hash; 266 __le16 fd_id; 267 __le16 vlan_tag; 268 269 union { 270 __le32 ol_info; 271 struct { 272 __le16 o_dm_vlan_id_fb; 273 __le16 ot_vlan_tag; 274 }; 275 }; 276 277 __le32 bd_base_info; 278 } rx; 279 }; 280 }; 281 282 struct hns3_desc_cb { 283 dma_addr_t dma; /* dma address of this desc */ 284 void *buf; /* cpu addr for a desc */ 285 286 /* priv data for the desc, e.g. skb when use with ip stack*/ 287 void *priv; 288 u16 page_offset; 289 u16 reuse_flag; 290 291 u32 length; /* length of the buffer */ 292 293 /* desc type, used by the ring user to mark the type of the priv data */ 294 u16 type; 295 }; 296 297 enum hns3_pkt_l3type { 298 HNS3_L3_TYPE_IPV4, 299 HNS3_L3_TYPE_IPV6, 300 HNS3_L3_TYPE_ARP, 301 HNS3_L3_TYPE_RARP, 302 HNS3_L3_TYPE_IPV4_OPT, 303 HNS3_L3_TYPE_IPV6_EXT, 304 HNS3_L3_TYPE_LLDP, 305 HNS3_L3_TYPE_BPDU, 306 HNS3_L3_TYPE_MAC_PAUSE, 307 HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/ 308 309 /* reserved for 0xA~0xB*/ 310 311 HNS3_L3_TYPE_CNM = 0xc, 312 313 /* reserved for 0xD~0xE*/ 314 315 HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */ 316 }; 317 318 enum hns3_pkt_l4type { 319 HNS3_L4_TYPE_UDP, 320 HNS3_L4_TYPE_TCP, 321 HNS3_L4_TYPE_GRE, 322 HNS3_L4_TYPE_SCTP, 323 HNS3_L4_TYPE_IGMP, 324 HNS3_L4_TYPE_ICMP, 325 326 /* reserved for 0x6~0xE */ 327 328 HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */ 329 }; 330 331 enum hns3_pkt_ol3type { 332 HNS3_OL3_TYPE_IPV4 = 0, 333 HNS3_OL3_TYPE_IPV6, 334 /* reserved for 0x2~0x3 */ 335 HNS3_OL3_TYPE_IPV4_OPT = 4, 336 HNS3_OL3_TYPE_IPV6_EXT, 337 338 /* reserved for 0x6~0xE*/ 339 340 HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */ 341 }; 342 343 enum hns3_pkt_ol4type { 344 HNS3_OL4_TYPE_NO_TUN, 345 HNS3_OL4_TYPE_MAC_IN_UDP, 346 HNS3_OL4_TYPE_NVGRE, 347 HNS3_OL4_TYPE_UNKNOWN 348 }; 349 350 struct ring_stats { 351 u64 io_err_cnt; 352 u64 sw_err_cnt; 353 u64 seg_pkt_cnt; 354 union { 355 struct { 356 u64 tx_pkts; 357 u64 tx_bytes; 358 u64 tx_err_cnt; 359 u64 restart_queue; 360 u64 tx_busy; 361 }; 362 struct { 363 u64 rx_pkts; 364 u64 rx_bytes; 365 u64 rx_err_cnt; 366 u64 reuse_pg_cnt; 367 u64 err_pkt_len; 368 u64 non_vld_descs; 369 u64 err_bd_num; 370 u64 l2_err; 371 u64 l3l4_csum_err; 372 }; 373 }; 374 }; 375 376 struct hns3_enet_ring { 377 u8 __iomem *io_base; /* base io address for the ring */ 378 struct hns3_desc *desc; /* dma map address space */ 379 struct hns3_desc_cb *desc_cb; 380 struct hns3_enet_ring *next; 381 struct hns3_enet_tqp_vector *tqp_vector; 382 struct hnae3_queue *tqp; 383 char ring_name[HNS3_RING_NAME_LEN]; 384 struct device *dev; /* will be used for DMA mapping of descriptors */ 385 386 /* statistic */ 387 struct ring_stats stats; 388 struct u64_stats_sync syncp; 389 390 dma_addr_t desc_dma_addr; 391 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 392 u16 desc_num; /* total number of desc */ 393 u16 max_desc_num_per_pkt; 394 u16 max_raw_data_sz_per_desc; 395 u16 max_pkt_size; 396 int next_to_use; /* idx of next spare desc */ 397 398 /* idx of lastest sent desc, the ring is empty when equal to 399 * next_to_use 400 */ 401 int next_to_clean; 402 403 u32 flag; /* ring attribute */ 404 int irq_init_flag; 405 406 int numa_node; 407 cpumask_t affinity_mask; 408 }; 409 410 struct hns_queue; 411 412 struct hns3_nic_ring_data { 413 struct hns3_enet_ring *ring; 414 struct napi_struct napi; 415 int queue_index; 416 int (*poll_one)(struct hns3_nic_ring_data *, int, void *); 417 void (*ex_process)(struct hns3_nic_ring_data *, struct sk_buff *); 418 void (*fini_process)(struct hns3_nic_ring_data *); 419 }; 420 421 struct hns3_nic_ops { 422 int (*fill_desc)(struct hns3_enet_ring *ring, void *priv, 423 int size, dma_addr_t dma, int frag_end, 424 enum hns_desc_type type); 425 int (*maybe_stop_tx)(struct sk_buff **out_skb, 426 int *bnum, struct hns3_enet_ring *ring); 427 void (*get_rxd_bnum)(u32 bnum_flag, int *out_bnum); 428 }; 429 430 enum hns3_flow_level_range { 431 HNS3_FLOW_LOW = 0, 432 HNS3_FLOW_MID = 1, 433 HNS3_FLOW_HIGH = 2, 434 HNS3_FLOW_ULTRA = 3, 435 }; 436 437 enum hns3_link_mode_bits { 438 HNS3_LM_FIBRE_BIT = BIT(0), 439 HNS3_LM_AUTONEG_BIT = BIT(1), 440 HNS3_LM_TP_BIT = BIT(2), 441 HNS3_LM_PAUSE_BIT = BIT(3), 442 HNS3_LM_BACKPLANE_BIT = BIT(4), 443 HNS3_LM_10BASET_HALF_BIT = BIT(5), 444 HNS3_LM_10BASET_FULL_BIT = BIT(6), 445 HNS3_LM_100BASET_HALF_BIT = BIT(7), 446 HNS3_LM_100BASET_FULL_BIT = BIT(8), 447 HNS3_LM_1000BASET_FULL_BIT = BIT(9), 448 HNS3_LM_10000BASEKR_FULL_BIT = BIT(10), 449 HNS3_LM_25000BASEKR_FULL_BIT = BIT(11), 450 HNS3_LM_40000BASELR4_FULL_BIT = BIT(12), 451 HNS3_LM_50000BASEKR2_FULL_BIT = BIT(13), 452 HNS3_LM_100000BASEKR4_FULL_BIT = BIT(14), 453 HNS3_LM_COUNT = 15 454 }; 455 456 #define HNS3_INT_GL_MAX 0x1FE0 457 #define HNS3_INT_GL_50K 0x0014 458 #define HNS3_INT_GL_20K 0x0032 459 #define HNS3_INT_GL_18K 0x0036 460 #define HNS3_INT_GL_8K 0x007C 461 462 #define HNS3_INT_RL_MAX 0x00EC 463 #define HNS3_INT_RL_ENABLE_MASK 0x40 464 465 #define HNS3_INT_ADAPT_DOWN_START 100 466 467 struct hns3_enet_coalesce { 468 u16 int_gl; 469 u8 gl_adapt_enable; 470 enum hns3_flow_level_range flow_level; 471 }; 472 473 struct hns3_enet_ring_group { 474 /* array of pointers to rings */ 475 struct hns3_enet_ring *ring; 476 u64 total_bytes; /* total bytes processed this group */ 477 u64 total_packets; /* total packets processed this group */ 478 u16 count; 479 struct hns3_enet_coalesce coal; 480 }; 481 482 struct hns3_enet_tqp_vector { 483 struct hnae3_handle *handle; 484 u8 __iomem *mask_addr; 485 int vector_irq; 486 int irq_init_flag; 487 488 u16 idx; /* index in the TQP vector array per handle. */ 489 490 struct napi_struct napi; 491 492 struct hns3_enet_ring_group rx_group; 493 struct hns3_enet_ring_group tx_group; 494 495 u16 num_tqps; /* total number of tqps in TQP vector */ 496 497 cpumask_t affinity_mask; 498 char name[HNAE3_INT_NAME_LEN]; 499 500 /* when 0 should adjust interrupt coalesce parameter */ 501 u8 int_adapt_down; 502 unsigned long last_jiffies; 503 } ____cacheline_internodealigned_in_smp; 504 505 enum hns3_udp_tnl_type { 506 HNS3_UDP_TNL_VXLAN, 507 HNS3_UDP_TNL_GENEVE, 508 HNS3_UDP_TNL_MAX, 509 }; 510 511 struct hns3_udp_tunnel { 512 u16 dst_port; 513 int used; 514 }; 515 516 struct hns3_nic_priv { 517 struct hnae3_handle *ae_handle; 518 u32 enet_ver; 519 u32 port_id; 520 struct net_device *netdev; 521 struct device *dev; 522 struct hns3_nic_ops ops; 523 524 /** 525 * the cb for nic to manage the ring buffer, the first half of the 526 * array is for tx_ring and vice versa for the second half 527 */ 528 struct hns3_nic_ring_data *ring_data; 529 struct hns3_enet_tqp_vector *tqp_vector; 530 u16 vector_num; 531 532 /* The most recently read link state */ 533 int link; 534 u64 tx_timeout_count; 535 536 unsigned long state; 537 538 struct timer_list service_timer; 539 540 struct work_struct service_task; 541 542 struct notifier_block notifier_block; 543 /* Vxlan/Geneve information */ 544 struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX]; 545 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 546 }; 547 548 union l3_hdr_info { 549 struct iphdr *v4; 550 struct ipv6hdr *v6; 551 unsigned char *hdr; 552 }; 553 554 union l4_hdr_info { 555 struct tcphdr *tcp; 556 struct udphdr *udp; 557 unsigned char *hdr; 558 }; 559 560 /* the distance between [begin, end) in a ring buffer 561 * note: there is a unuse slot between the begin and the end 562 */ 563 static inline int ring_dist(struct hns3_enet_ring *ring, int begin, int end) 564 { 565 return (end - begin + ring->desc_num) % ring->desc_num; 566 } 567 568 static inline int ring_space(struct hns3_enet_ring *ring) 569 { 570 return ring->desc_num - 571 ring_dist(ring, ring->next_to_clean, ring->next_to_use) - 1; 572 } 573 574 static inline int is_ring_empty(struct hns3_enet_ring *ring) 575 { 576 return ring->next_to_use == ring->next_to_clean; 577 } 578 579 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value) 580 { 581 u8 __iomem *reg_addr = READ_ONCE(base); 582 583 writel(value, reg_addr + reg); 584 } 585 586 #define hns3_write_dev(a, reg, value) \ 587 hns3_write_reg((a)->io_base, (reg), (value)) 588 589 #define hnae_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \ 590 (tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG) 591 592 #define ring_to_dev(ring) (&(ring)->tqp->handle->pdev->dev) 593 594 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \ 595 DMA_TO_DEVICE : DMA_FROM_DEVICE) 596 597 #define tx_ring_data(priv, idx) ((priv)->ring_data[idx]) 598 599 #define hnae_buf_size(_ring) ((_ring)->buf_size) 600 #define hnae_page_order(_ring) (get_order(hnae_buf_size(_ring))) 601 #define hnae_page_size(_ring) (PAGE_SIZE << hnae_page_order(_ring)) 602 603 /* iterator for handling rings in ring group */ 604 #define hns3_for_each_ring(pos, head) \ 605 for (pos = (head).ring; pos; pos = pos->next) 606 607 #define hns3_get_handle(ndev) \ 608 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle) 609 610 #define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1) 611 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2) 612 613 #define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2) 614 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4) 615 616 void hns3_ethtool_set_ops(struct net_device *netdev); 617 int hns3_set_channels(struct net_device *netdev, 618 struct ethtool_channels *ch); 619 620 bool hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget); 621 int hns3_init_all_ring(struct hns3_nic_priv *priv); 622 int hns3_uninit_all_ring(struct hns3_nic_priv *priv); 623 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev); 624 int hns3_clean_rx_ring( 625 struct hns3_enet_ring *ring, int budget, 626 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)); 627 628 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 629 u32 gl_value); 630 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 631 u32 gl_value); 632 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 633 u32 rl_value); 634 635 #ifdef CONFIG_HNS3_DCB 636 void hns3_dcbnl_setup(struct hnae3_handle *handle); 637 #else 638 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {} 639 #endif 640 641 #endif 642