1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HNS3_ENET_H 5 #define __HNS3_ENET_H 6 7 #include <linux/if_vlan.h> 8 9 #include "hnae3.h" 10 11 #define HNS3_MOD_VERSION "1.0" 12 13 extern const char hns3_driver_version[]; 14 15 enum hns3_nic_state { 16 HNS3_NIC_STATE_TESTING, 17 HNS3_NIC_STATE_RESETTING, 18 HNS3_NIC_STATE_INITED, 19 HNS3_NIC_STATE_DOWN, 20 HNS3_NIC_STATE_DISABLED, 21 HNS3_NIC_STATE_REMOVING, 22 HNS3_NIC_STATE_SERVICE_INITED, 23 HNS3_NIC_STATE_SERVICE_SCHED, 24 HNS3_NIC_STATE2_RESET_REQUESTED, 25 HNS3_NIC_STATE_MAX 26 }; 27 28 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000 29 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004 30 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008 31 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C 32 #define HNS3_RING_RX_RING_TAIL_REG 0x00018 33 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C 34 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020 35 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C 36 37 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040 38 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044 39 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048 40 #define HNS3_RING_TX_RING_TC_REG 0x00050 41 #define HNS3_RING_TX_RING_TAIL_REG 0x00058 42 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C 43 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060 44 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064 45 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C 46 47 #define HNS3_RING_PREFETCH_EN_REG 0x0007C 48 #define HNS3_RING_CFG_VF_NUM_REG 0x00080 49 #define HNS3_RING_ASID_REG 0x0008C 50 #define HNS3_RING_EN_REG 0x00090 51 #define HNS3_RING_T0_BE_RST 0x00094 52 #define HNS3_RING_COULD_BE_RST 0x00098 53 #define HNS3_RING_WRR_WEIGHT_REG 0x0009c 54 55 #define HNS3_RING_INTMSK_RXWL_REG 0x000A0 56 #define HNS3_RING_INTSTS_RX_RING_REG 0x000A4 57 #define HNS3_RX_RING_INT_STS_REG 0x000A8 58 #define HNS3_RING_INTMSK_TXWL_REG 0x000AC 59 #define HNS3_RING_INTSTS_TX_RING_REG 0x000B0 60 #define HNS3_TX_RING_INT_STS_REG 0x000B4 61 #define HNS3_RING_INTMSK_RX_OVERTIME_REG 0x000B8 62 #define HNS3_RING_INTSTS_RX_OVERTIME_REG 0x000BC 63 #define HNS3_RING_INTMSK_TX_OVERTIME_REG 0x000C4 64 #define HNS3_RING_INTSTS_TX_OVERTIME_REG 0x000C8 65 66 #define HNS3_RING_MB_CTRL_REG 0x00100 67 #define HNS3_RING_MB_DATA_BASE_REG 0x00200 68 69 #define HNS3_TX_REG_OFFSET 0x40 70 71 #define HNS3_RX_HEAD_SIZE 256 72 73 #define HNS3_TX_TIMEOUT (5 * HZ) 74 #define HNS3_RING_NAME_LEN 16 75 #define HNS3_BUFFER_SIZE_2048 2048 76 #define HNS3_RING_MAX_PENDING 32768 77 #define HNS3_RING_MIN_PENDING 24 78 #define HNS3_RING_BD_MULTIPLE 8 79 /* max frame size of mac */ 80 #define HNS3_MAC_MAX_FRAME 9728 81 #define HNS3_MAX_MTU \ 82 (HNS3_MAC_MAX_FRAME - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN)) 83 84 #define HNS3_BD_SIZE_512_TYPE 0 85 #define HNS3_BD_SIZE_1024_TYPE 1 86 #define HNS3_BD_SIZE_2048_TYPE 2 87 #define HNS3_BD_SIZE_4096_TYPE 3 88 89 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1 90 #define HNS3_RX_FLAG_L3ID_IPV4 0x0 91 #define HNS3_RX_FLAG_L3ID_IPV6 0x1 92 #define HNS3_RX_FLAG_L4ID_UDP 0x0 93 #define HNS3_RX_FLAG_L4ID_TCP 0x1 94 95 #define HNS3_RXD_DMAC_S 0 96 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S) 97 #define HNS3_RXD_VLAN_S 2 98 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S) 99 #define HNS3_RXD_L3ID_S 4 100 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S) 101 #define HNS3_RXD_L4ID_S 8 102 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S) 103 #define HNS3_RXD_FRAG_B 12 104 #define HNS3_RXD_STRP_TAGP_S 13 105 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S) 106 107 #define HNS3_RXD_L2E_B 16 108 #define HNS3_RXD_L3E_B 17 109 #define HNS3_RXD_L4E_B 18 110 #define HNS3_RXD_TRUNCAT_B 19 111 #define HNS3_RXD_HOI_B 20 112 #define HNS3_RXD_DOI_B 21 113 #define HNS3_RXD_OL3E_B 22 114 #define HNS3_RXD_OL4E_B 23 115 #define HNS3_RXD_GRO_COUNT_S 24 116 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S) 117 #define HNS3_RXD_GRO_FIXID_B 30 118 #define HNS3_RXD_GRO_ECN_B 31 119 120 #define HNS3_RXD_ODMAC_S 0 121 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S) 122 #define HNS3_RXD_OVLAN_S 2 123 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S) 124 #define HNS3_RXD_OL3ID_S 4 125 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S) 126 #define HNS3_RXD_OL4ID_S 8 127 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S) 128 #define HNS3_RXD_FBHI_S 12 129 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S) 130 #define HNS3_RXD_FBLI_S 14 131 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S) 132 133 #define HNS3_RXD_BDTYPE_S 0 134 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S) 135 #define HNS3_RXD_VLD_B 4 136 #define HNS3_RXD_UDP0_B 5 137 #define HNS3_RXD_EXTEND_B 7 138 #define HNS3_RXD_FE_B 8 139 #define HNS3_RXD_LUM_B 9 140 #define HNS3_RXD_CRCP_B 10 141 #define HNS3_RXD_L3L4P_B 11 142 #define HNS3_RXD_TSIND_S 12 143 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S) 144 #define HNS3_RXD_LKBK_B 15 145 #define HNS3_RXD_GRO_SIZE_S 16 146 #define HNS3_RXD_GRO_SIZE_M (0x3ff << HNS3_RXD_GRO_SIZE_S) 147 148 #define HNS3_TXD_L3T_S 0 149 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S) 150 #define HNS3_TXD_L4T_S 2 151 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S) 152 #define HNS3_TXD_L3CS_B 4 153 #define HNS3_TXD_L4CS_B 5 154 #define HNS3_TXD_VLAN_B 6 155 #define HNS3_TXD_TSO_B 7 156 157 #define HNS3_TXD_L2LEN_S 8 158 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S) 159 #define HNS3_TXD_L3LEN_S 16 160 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S) 161 #define HNS3_TXD_L4LEN_S 24 162 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S) 163 164 #define HNS3_TXD_OL3T_S 0 165 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S) 166 #define HNS3_TXD_OVLAN_B 2 167 #define HNS3_TXD_MACSEC_B 3 168 #define HNS3_TXD_TUNTYPE_S 4 169 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S) 170 171 #define HNS3_TXD_BDTYPE_S 0 172 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S) 173 #define HNS3_TXD_FE_B 4 174 #define HNS3_TXD_SC_S 5 175 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S) 176 #define HNS3_TXD_EXTEND_B 7 177 #define HNS3_TXD_VLD_B 8 178 #define HNS3_TXD_RI_B 9 179 #define HNS3_TXD_RA_B 10 180 #define HNS3_TXD_TSYN_B 11 181 #define HNS3_TXD_DECTTL_S 12 182 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S) 183 184 #define HNS3_TXD_MSS_S 0 185 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) 186 187 #define HNS3_TX_LAST_SIZE_M 0xffff 188 189 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0) 190 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1) 191 192 #define HNS3_VECTOR_NOT_INITED 0 193 #define HNS3_VECTOR_INITED 1 194 195 #define HNS3_MAX_BD_SIZE 65535 196 #define HNS3_MAX_BD_PER_FRAG 8 197 #define HNS3_MAX_BD_PER_PKT MAX_SKB_FRAGS 198 199 #define HNS3_VECTOR_GL0_OFFSET 0x100 200 #define HNS3_VECTOR_GL1_OFFSET 0x200 201 #define HNS3_VECTOR_GL2_OFFSET 0x300 202 #define HNS3_VECTOR_RL_OFFSET 0x900 203 #define HNS3_VECTOR_RL_EN_B 6 204 205 #define HNS3_RING_EN_B 0 206 207 enum hns3_pkt_l2t_type { 208 HNS3_L2_TYPE_UNICAST, 209 HNS3_L2_TYPE_MULTICAST, 210 HNS3_L2_TYPE_BROADCAST, 211 HNS3_L2_TYPE_INVALID, 212 }; 213 214 enum hns3_pkt_l3t_type { 215 HNS3_L3T_NONE, 216 HNS3_L3T_IPV6, 217 HNS3_L3T_IPV4, 218 HNS3_L3T_RESERVED 219 }; 220 221 enum hns3_pkt_l4t_type { 222 HNS3_L4T_UNKNOWN, 223 HNS3_L4T_TCP, 224 HNS3_L4T_UDP, 225 HNS3_L4T_SCTP 226 }; 227 228 enum hns3_pkt_ol3t_type { 229 HNS3_OL3T_NONE, 230 HNS3_OL3T_IPV6, 231 HNS3_OL3T_IPV4_NO_CSUM, 232 HNS3_OL3T_IPV4_CSUM 233 }; 234 235 enum hns3_pkt_tun_type { 236 HNS3_TUN_NONE, 237 HNS3_TUN_MAC_IN_UDP, 238 HNS3_TUN_NVGRE, 239 HNS3_TUN_OTHER 240 }; 241 242 /* hardware spec ring buffer format */ 243 struct __packed hns3_desc { 244 __le64 addr; 245 union { 246 struct { 247 __le16 vlan_tag; 248 __le16 send_size; 249 union { 250 __le32 type_cs_vlan_tso_len; 251 struct { 252 __u8 type_cs_vlan_tso; 253 __u8 l2_len; 254 __u8 l3_len; 255 __u8 l4_len; 256 }; 257 }; 258 __le16 outer_vlan_tag; 259 __le16 tv; 260 261 union { 262 __le32 ol_type_vlan_len_msec; 263 struct { 264 __u8 ol_type_vlan_msec; 265 __u8 ol2_len; 266 __u8 ol3_len; 267 __u8 ol4_len; 268 }; 269 }; 270 271 __le32 paylen; 272 __le16 bdtp_fe_sc_vld_ra_ri; 273 __le16 mss; 274 } tx; 275 276 struct { 277 __le32 l234_info; 278 __le16 pkt_len; 279 __le16 size; 280 281 __le32 rss_hash; 282 __le16 fd_id; 283 __le16 vlan_tag; 284 285 union { 286 __le32 ol_info; 287 struct { 288 __le16 o_dm_vlan_id_fb; 289 __le16 ot_vlan_tag; 290 }; 291 }; 292 293 __le32 bd_base_info; 294 } rx; 295 }; 296 }; 297 298 struct hns3_desc_cb { 299 dma_addr_t dma; /* dma address of this desc */ 300 void *buf; /* cpu addr for a desc */ 301 302 /* priv data for the desc, e.g. skb when use with ip stack*/ 303 void *priv; 304 u32 page_offset; 305 u32 length; /* length of the buffer */ 306 307 u16 reuse_flag; 308 309 /* desc type, used by the ring user to mark the type of the priv data */ 310 u16 type; 311 }; 312 313 enum hns3_pkt_l3type { 314 HNS3_L3_TYPE_IPV4, 315 HNS3_L3_TYPE_IPV6, 316 HNS3_L3_TYPE_ARP, 317 HNS3_L3_TYPE_RARP, 318 HNS3_L3_TYPE_IPV4_OPT, 319 HNS3_L3_TYPE_IPV6_EXT, 320 HNS3_L3_TYPE_LLDP, 321 HNS3_L3_TYPE_BPDU, 322 HNS3_L3_TYPE_MAC_PAUSE, 323 HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/ 324 325 /* reserved for 0xA~0xB*/ 326 327 HNS3_L3_TYPE_CNM = 0xc, 328 329 /* reserved for 0xD~0xE*/ 330 331 HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */ 332 }; 333 334 enum hns3_pkt_l4type { 335 HNS3_L4_TYPE_UDP, 336 HNS3_L4_TYPE_TCP, 337 HNS3_L4_TYPE_GRE, 338 HNS3_L4_TYPE_SCTP, 339 HNS3_L4_TYPE_IGMP, 340 HNS3_L4_TYPE_ICMP, 341 342 /* reserved for 0x6~0xE */ 343 344 HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */ 345 }; 346 347 enum hns3_pkt_ol3type { 348 HNS3_OL3_TYPE_IPV4 = 0, 349 HNS3_OL3_TYPE_IPV6, 350 /* reserved for 0x2~0x3 */ 351 HNS3_OL3_TYPE_IPV4_OPT = 4, 352 HNS3_OL3_TYPE_IPV6_EXT, 353 354 /* reserved for 0x6~0xE*/ 355 356 HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */ 357 }; 358 359 enum hns3_pkt_ol4type { 360 HNS3_OL4_TYPE_NO_TUN, 361 HNS3_OL4_TYPE_MAC_IN_UDP, 362 HNS3_OL4_TYPE_NVGRE, 363 HNS3_OL4_TYPE_UNKNOWN 364 }; 365 366 struct ring_stats { 367 u64 io_err_cnt; 368 u64 sw_err_cnt; 369 u64 seg_pkt_cnt; 370 union { 371 struct { 372 u64 tx_pkts; 373 u64 tx_bytes; 374 u64 tx_err_cnt; 375 u64 restart_queue; 376 u64 tx_busy; 377 }; 378 struct { 379 u64 rx_pkts; 380 u64 rx_bytes; 381 u64 rx_err_cnt; 382 u64 reuse_pg_cnt; 383 u64 err_pkt_len; 384 u64 non_vld_descs; 385 u64 err_bd_num; 386 u64 l2_err; 387 u64 l3l4_csum_err; 388 u64 rx_multicast; 389 }; 390 }; 391 }; 392 393 struct hns3_enet_ring { 394 u8 __iomem *io_base; /* base io address for the ring */ 395 struct hns3_desc *desc; /* dma map address space */ 396 struct hns3_desc_cb *desc_cb; 397 struct hns3_enet_ring *next; 398 struct hns3_enet_tqp_vector *tqp_vector; 399 struct hnae3_queue *tqp; 400 char ring_name[HNS3_RING_NAME_LEN]; 401 struct device *dev; /* will be used for DMA mapping of descriptors */ 402 403 /* statistic */ 404 struct ring_stats stats; 405 struct u64_stats_sync syncp; 406 407 dma_addr_t desc_dma_addr; 408 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 409 u16 desc_num; /* total number of desc */ 410 u16 max_desc_num_per_pkt; 411 u16 max_raw_data_sz_per_desc; 412 u16 max_pkt_size; 413 int next_to_use; /* idx of next spare desc */ 414 415 /* idx of lastest sent desc, the ring is empty when equal to 416 * next_to_use 417 */ 418 int next_to_clean; 419 420 int pull_len; /* head length for current packet */ 421 u32 frag_num; 422 unsigned char *va; /* first buffer address for current packet */ 423 424 u32 flag; /* ring attribute */ 425 426 int numa_node; 427 cpumask_t affinity_mask; 428 429 int pending_buf; 430 struct sk_buff *skb; 431 struct sk_buff *tail_skb; 432 }; 433 434 struct hns_queue; 435 436 struct hns3_nic_ring_data { 437 struct hns3_enet_ring *ring; 438 struct napi_struct napi; 439 int queue_index; 440 int (*poll_one)(struct hns3_nic_ring_data *, int, void *); 441 void (*ex_process)(struct hns3_nic_ring_data *, struct sk_buff *); 442 void (*fini_process)(struct hns3_nic_ring_data *); 443 }; 444 445 struct hns3_nic_ops { 446 int (*maybe_stop_tx)(struct sk_buff **out_skb, 447 int *bnum, struct hns3_enet_ring *ring); 448 }; 449 450 enum hns3_flow_level_range { 451 HNS3_FLOW_LOW = 0, 452 HNS3_FLOW_MID = 1, 453 HNS3_FLOW_HIGH = 2, 454 HNS3_FLOW_ULTRA = 3, 455 }; 456 457 enum hns3_link_mode_bits { 458 HNS3_LM_FIBRE_BIT = BIT(0), 459 HNS3_LM_AUTONEG_BIT = BIT(1), 460 HNS3_LM_TP_BIT = BIT(2), 461 HNS3_LM_PAUSE_BIT = BIT(3), 462 HNS3_LM_BACKPLANE_BIT = BIT(4), 463 HNS3_LM_10BASET_HALF_BIT = BIT(5), 464 HNS3_LM_10BASET_FULL_BIT = BIT(6), 465 HNS3_LM_100BASET_HALF_BIT = BIT(7), 466 HNS3_LM_100BASET_FULL_BIT = BIT(8), 467 HNS3_LM_1000BASET_FULL_BIT = BIT(9), 468 HNS3_LM_10000BASEKR_FULL_BIT = BIT(10), 469 HNS3_LM_25000BASEKR_FULL_BIT = BIT(11), 470 HNS3_LM_40000BASELR4_FULL_BIT = BIT(12), 471 HNS3_LM_50000BASEKR2_FULL_BIT = BIT(13), 472 HNS3_LM_100000BASEKR4_FULL_BIT = BIT(14), 473 HNS3_LM_COUNT = 15 474 }; 475 476 #define HNS3_INT_GL_MAX 0x1FE0 477 #define HNS3_INT_GL_50K 0x0014 478 #define HNS3_INT_GL_20K 0x0032 479 #define HNS3_INT_GL_18K 0x0036 480 #define HNS3_INT_GL_8K 0x007C 481 482 #define HNS3_INT_RL_MAX 0x00EC 483 #define HNS3_INT_RL_ENABLE_MASK 0x40 484 485 struct hns3_enet_coalesce { 486 u16 int_gl; 487 u8 gl_adapt_enable; 488 enum hns3_flow_level_range flow_level; 489 }; 490 491 struct hns3_enet_ring_group { 492 /* array of pointers to rings */ 493 struct hns3_enet_ring *ring; 494 u64 total_bytes; /* total bytes processed this group */ 495 u64 total_packets; /* total packets processed this group */ 496 u16 count; 497 struct hns3_enet_coalesce coal; 498 }; 499 500 struct hns3_enet_tqp_vector { 501 struct hnae3_handle *handle; 502 u8 __iomem *mask_addr; 503 int vector_irq; 504 int irq_init_flag; 505 506 u16 idx; /* index in the TQP vector array per handle. */ 507 508 struct napi_struct napi; 509 510 struct hns3_enet_ring_group rx_group; 511 struct hns3_enet_ring_group tx_group; 512 513 cpumask_t affinity_mask; 514 u16 num_tqps; /* total number of tqps in TQP vector */ 515 struct irq_affinity_notify affinity_notify; 516 517 char name[HNAE3_INT_NAME_LEN]; 518 519 unsigned long last_jiffies; 520 } ____cacheline_internodealigned_in_smp; 521 522 enum hns3_udp_tnl_type { 523 HNS3_UDP_TNL_VXLAN, 524 HNS3_UDP_TNL_GENEVE, 525 HNS3_UDP_TNL_MAX, 526 }; 527 528 struct hns3_udp_tunnel { 529 u16 dst_port; 530 int used; 531 }; 532 533 struct hns3_nic_priv { 534 struct hnae3_handle *ae_handle; 535 u32 enet_ver; 536 u32 port_id; 537 struct net_device *netdev; 538 struct device *dev; 539 struct hns3_nic_ops ops; 540 541 /** 542 * the cb for nic to manage the ring buffer, the first half of the 543 * array is for tx_ring and vice versa for the second half 544 */ 545 struct hns3_nic_ring_data *ring_data; 546 struct hns3_enet_tqp_vector *tqp_vector; 547 u16 vector_num; 548 549 /* The most recently read link state */ 550 int link; 551 u64 tx_timeout_count; 552 553 unsigned long state; 554 555 struct timer_list service_timer; 556 557 struct work_struct service_task; 558 559 struct notifier_block notifier_block; 560 /* Vxlan/Geneve information */ 561 struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX]; 562 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 563 struct hns3_enet_coalesce tx_coal; 564 struct hns3_enet_coalesce rx_coal; 565 }; 566 567 union l3_hdr_info { 568 struct iphdr *v4; 569 struct ipv6hdr *v6; 570 unsigned char *hdr; 571 }; 572 573 union l4_hdr_info { 574 struct tcphdr *tcp; 575 struct udphdr *udp; 576 struct gre_base_hdr *gre; 577 unsigned char *hdr; 578 }; 579 580 /* the distance between [begin, end) in a ring buffer 581 * note: there is a unuse slot between the begin and the end 582 */ 583 static inline int ring_dist(struct hns3_enet_ring *ring, int begin, int end) 584 { 585 return (end - begin + ring->desc_num) % ring->desc_num; 586 } 587 588 static inline int ring_space(struct hns3_enet_ring *ring) 589 { 590 return ring->desc_num - 591 ring_dist(ring, ring->next_to_clean, ring->next_to_use) - 1; 592 } 593 594 static inline int is_ring_empty(struct hns3_enet_ring *ring) 595 { 596 return ring->next_to_use == ring->next_to_clean; 597 } 598 599 static inline u32 hns3_read_reg(void __iomem *base, u32 reg) 600 { 601 return readl(base + reg); 602 } 603 604 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value) 605 { 606 u8 __iomem *reg_addr = READ_ONCE(base); 607 608 writel(value, reg_addr + reg); 609 } 610 611 static inline bool hns3_dev_ongoing_func_reset(struct hnae3_ae_dev *ae_dev) 612 { 613 return (ae_dev && (ae_dev->reset_type == HNAE3_FUNC_RESET || 614 ae_dev->reset_type == HNAE3_FLR_RESET || 615 ae_dev->reset_type == HNAE3_VF_FUNC_RESET || 616 ae_dev->reset_type == HNAE3_VF_FULL_RESET || 617 ae_dev->reset_type == HNAE3_VF_PF_FUNC_RESET)); 618 } 619 620 #define hns3_read_dev(a, reg) \ 621 hns3_read_reg((a)->io_base, (reg)) 622 623 static inline bool hns3_nic_resetting(struct net_device *netdev) 624 { 625 struct hns3_nic_priv *priv = netdev_priv(netdev); 626 627 return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 628 } 629 630 #define hns3_write_dev(a, reg, value) \ 631 hns3_write_reg((a)->io_base, (reg), (value)) 632 633 #define hnae3_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \ 634 (tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG) 635 636 #define ring_to_dev(ring) (&(ring)->tqp->handle->pdev->dev) 637 638 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \ 639 DMA_TO_DEVICE : DMA_FROM_DEVICE) 640 641 #define tx_ring_data(priv, idx) ((priv)->ring_data[idx]) 642 643 #define hnae3_buf_size(_ring) ((_ring)->buf_size) 644 #define hnae3_page_order(_ring) (get_order(hnae3_buf_size(_ring))) 645 #define hnae3_page_size(_ring) (PAGE_SIZE << hnae3_page_order(_ring)) 646 647 /* iterator for handling rings in ring group */ 648 #define hns3_for_each_ring(pos, head) \ 649 for (pos = (head).ring; pos; pos = pos->next) 650 651 #define hns3_get_handle(ndev) \ 652 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle) 653 654 #define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1) 655 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2) 656 657 #define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2) 658 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4) 659 660 void hns3_ethtool_set_ops(struct net_device *netdev); 661 int hns3_set_channels(struct net_device *netdev, 662 struct ethtool_channels *ch); 663 664 void hns3_clean_tx_ring(struct hns3_enet_ring *ring); 665 int hns3_init_all_ring(struct hns3_nic_priv *priv); 666 int hns3_uninit_all_ring(struct hns3_nic_priv *priv); 667 int hns3_nic_reset_all_ring(struct hnae3_handle *h); 668 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev); 669 int hns3_clean_rx_ring( 670 struct hns3_enet_ring *ring, int budget, 671 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)); 672 673 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 674 u32 gl_value); 675 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 676 u32 gl_value); 677 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 678 u32 rl_value); 679 680 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable); 681 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags); 682 683 #ifdef CONFIG_HNS3_DCB 684 void hns3_dcbnl_setup(struct hnae3_handle *handle); 685 #else 686 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {} 687 #endif 688 689 void hns3_dbg_init(struct hnae3_handle *handle); 690 void hns3_dbg_uninit(struct hnae3_handle *handle); 691 void hns3_dbg_register_debugfs(const char *debugfs_dir_name); 692 void hns3_dbg_unregister_debugfs(void); 693 #endif 694