1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #ifndef __HNS3_ENET_H 11 #define __HNS3_ENET_H 12 13 #include "hnae3.h" 14 15 extern const char hns3_driver_version[]; 16 17 enum hns3_nic_state { 18 HNS3_NIC_STATE_TESTING, 19 HNS3_NIC_STATE_RESETTING, 20 HNS3_NIC_STATE_REINITING, 21 HNS3_NIC_STATE_DOWN, 22 HNS3_NIC_STATE_DISABLED, 23 HNS3_NIC_STATE_REMOVING, 24 HNS3_NIC_STATE_SERVICE_INITED, 25 HNS3_NIC_STATE_SERVICE_SCHED, 26 HNS3_NIC_STATE2_RESET_REQUESTED, 27 HNS3_NIC_STATE_MAX 28 }; 29 30 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000 31 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004 32 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008 33 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C 34 #define HNS3_RING_RX_RING_TAIL_REG 0x00018 35 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C 36 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020 37 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C 38 39 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040 40 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044 41 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048 42 #define HNS3_RING_TX_RING_BD_LEN_REG 0x0004C 43 #define HNS3_RING_TX_RING_TAIL_REG 0x00058 44 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C 45 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060 46 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064 47 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C 48 49 #define HNS3_RING_PREFETCH_EN_REG 0x0007C 50 #define HNS3_RING_CFG_VF_NUM_REG 0x00080 51 #define HNS3_RING_ASID_REG 0x0008C 52 #define HNS3_RING_RX_VM_REG 0x00090 53 #define HNS3_RING_T0_BE_RST 0x00094 54 #define HNS3_RING_COULD_BE_RST 0x00098 55 #define HNS3_RING_WRR_WEIGHT_REG 0x0009c 56 57 #define HNS3_RING_INTMSK_RXWL_REG 0x000A0 58 #define HNS3_RING_INTSTS_RX_RING_REG 0x000A4 59 #define HNS3_RX_RING_INT_STS_REG 0x000A8 60 #define HNS3_RING_INTMSK_TXWL_REG 0x000AC 61 #define HNS3_RING_INTSTS_TX_RING_REG 0x000B0 62 #define HNS3_TX_RING_INT_STS_REG 0x000B4 63 #define HNS3_RING_INTMSK_RX_OVERTIME_REG 0x000B8 64 #define HNS3_RING_INTSTS_RX_OVERTIME_REG 0x000BC 65 #define HNS3_RING_INTMSK_TX_OVERTIME_REG 0x000C4 66 #define HNS3_RING_INTSTS_TX_OVERTIME_REG 0x000C8 67 68 #define HNS3_RING_MB_CTRL_REG 0x00100 69 #define HNS3_RING_MB_DATA_BASE_REG 0x00200 70 71 #define HNS3_TX_REG_OFFSET 0x40 72 73 #define HNS3_RX_HEAD_SIZE 256 74 75 #define HNS3_TX_TIMEOUT (5 * HZ) 76 #define HNS3_RING_NAME_LEN 16 77 #define HNS3_BUFFER_SIZE_2048 2048 78 #define HNS3_RING_MAX_PENDING 32768 79 #define HNS3_RING_MIN_PENDING 8 80 #define HNS3_RING_BD_MULTIPLE 8 81 #define HNS3_MAX_MTU 9728 82 83 #define HNS3_BD_SIZE_512_TYPE 0 84 #define HNS3_BD_SIZE_1024_TYPE 1 85 #define HNS3_BD_SIZE_2048_TYPE 2 86 #define HNS3_BD_SIZE_4096_TYPE 3 87 88 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1 89 #define HNS3_RX_FLAG_L3ID_IPV4 0x0 90 #define HNS3_RX_FLAG_L3ID_IPV6 0x1 91 #define HNS3_RX_FLAG_L4ID_UDP 0x0 92 #define HNS3_RX_FLAG_L4ID_TCP 0x1 93 94 #define HNS3_RXD_DMAC_S 0 95 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S) 96 #define HNS3_RXD_VLAN_S 2 97 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S) 98 #define HNS3_RXD_L3ID_S 4 99 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S) 100 #define HNS3_RXD_L4ID_S 8 101 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S) 102 #define HNS3_RXD_FRAG_B 12 103 #define HNS3_RXD_L2E_B 16 104 #define HNS3_RXD_L3E_B 17 105 #define HNS3_RXD_L4E_B 18 106 #define HNS3_RXD_TRUNCAT_B 19 107 #define HNS3_RXD_HOI_B 20 108 #define HNS3_RXD_DOI_B 21 109 #define HNS3_RXD_OL3E_B 22 110 #define HNS3_RXD_OL4E_B 23 111 112 #define HNS3_RXD_ODMAC_S 0 113 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S) 114 #define HNS3_RXD_OVLAN_S 2 115 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S) 116 #define HNS3_RXD_OL3ID_S 4 117 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S) 118 #define HNS3_RXD_OL4ID_S 8 119 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S) 120 #define HNS3_RXD_FBHI_S 12 121 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S) 122 #define HNS3_RXD_FBLI_S 14 123 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S) 124 125 #define HNS3_RXD_BDTYPE_S 0 126 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S) 127 #define HNS3_RXD_VLD_B 4 128 #define HNS3_RXD_UDP0_B 5 129 #define HNS3_RXD_EXTEND_B 7 130 #define HNS3_RXD_FE_B 8 131 #define HNS3_RXD_LUM_B 9 132 #define HNS3_RXD_CRCP_B 10 133 #define HNS3_RXD_L3L4P_B 11 134 #define HNS3_RXD_TSIND_S 12 135 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S) 136 #define HNS3_RXD_LKBK_B 15 137 #define HNS3_RXD_HDL_S 16 138 #define HNS3_RXD_HDL_M (0x7ff << HNS3_RXD_HDL_S) 139 #define HNS3_RXD_HSIND_B 31 140 141 #define HNS3_TXD_L3T_S 0 142 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S) 143 #define HNS3_TXD_L4T_S 2 144 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S) 145 #define HNS3_TXD_L3CS_B 4 146 #define HNS3_TXD_L4CS_B 5 147 #define HNS3_TXD_VLAN_B 6 148 #define HNS3_TXD_TSO_B 7 149 150 #define HNS3_TXD_L2LEN_S 8 151 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S) 152 #define HNS3_TXD_L3LEN_S 16 153 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S) 154 #define HNS3_TXD_L4LEN_S 24 155 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S) 156 157 #define HNS3_TXD_OL3T_S 0 158 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S) 159 #define HNS3_TXD_OVLAN_B 2 160 #define HNS3_TXD_MACSEC_B 3 161 #define HNS3_TXD_TUNTYPE_S 4 162 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S) 163 164 #define HNS3_TXD_BDTYPE_S 0 165 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S) 166 #define HNS3_TXD_FE_B 4 167 #define HNS3_TXD_SC_S 5 168 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S) 169 #define HNS3_TXD_EXTEND_B 7 170 #define HNS3_TXD_VLD_B 8 171 #define HNS3_TXD_RI_B 9 172 #define HNS3_TXD_RA_B 10 173 #define HNS3_TXD_TSYN_B 11 174 #define HNS3_TXD_DECTTL_S 12 175 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S) 176 177 #define HNS3_TXD_MSS_S 0 178 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) 179 180 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0) 181 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1) 182 183 #define HNS3_VECTOR_NOT_INITED 0 184 #define HNS3_VECTOR_INITED 1 185 186 #define HNS3_MAX_BD_SIZE 65535 187 #define HNS3_MAX_BD_PER_FRAG 8 188 #define HNS3_MAX_BD_PER_PKT MAX_SKB_FRAGS 189 190 #define HNS3_VECTOR_GL0_OFFSET 0x100 191 #define HNS3_VECTOR_GL1_OFFSET 0x200 192 #define HNS3_VECTOR_GL2_OFFSET 0x300 193 #define HNS3_VECTOR_RL_OFFSET 0x900 194 #define HNS3_VECTOR_RL_EN_B 6 195 196 enum hns3_pkt_l3t_type { 197 HNS3_L3T_NONE, 198 HNS3_L3T_IPV6, 199 HNS3_L3T_IPV4, 200 HNS3_L3T_RESERVED 201 }; 202 203 enum hns3_pkt_l4t_type { 204 HNS3_L4T_UNKNOWN, 205 HNS3_L4T_TCP, 206 HNS3_L4T_UDP, 207 HNS3_L4T_SCTP 208 }; 209 210 enum hns3_pkt_ol3t_type { 211 HNS3_OL3T_NONE, 212 HNS3_OL3T_IPV6, 213 HNS3_OL3T_IPV4_NO_CSUM, 214 HNS3_OL3T_IPV4_CSUM 215 }; 216 217 enum hns3_pkt_tun_type { 218 HNS3_TUN_NONE, 219 HNS3_TUN_MAC_IN_UDP, 220 HNS3_TUN_NVGRE, 221 HNS3_TUN_OTHER 222 }; 223 224 /* hardware spec ring buffer format */ 225 struct __packed hns3_desc { 226 __le64 addr; 227 union { 228 struct { 229 __le16 vlan_tag; 230 __le16 send_size; 231 union { 232 __le32 type_cs_vlan_tso_len; 233 struct { 234 __u8 type_cs_vlan_tso; 235 __u8 l2_len; 236 __u8 l3_len; 237 __u8 l4_len; 238 }; 239 }; 240 __le16 outer_vlan_tag; 241 __le16 tv; 242 243 union { 244 __le32 ol_type_vlan_len_msec; 245 struct { 246 __u8 ol_type_vlan_msec; 247 __u8 ol2_len; 248 __u8 ol3_len; 249 __u8 ol4_len; 250 }; 251 }; 252 253 __le32 paylen; 254 __le16 bdtp_fe_sc_vld_ra_ri; 255 __le16 mss; 256 } tx; 257 258 struct { 259 __le32 l234_info; 260 __le16 pkt_len; 261 __le16 size; 262 263 __le32 rss_hash; 264 __le16 fd_id; 265 __le16 vlan_tag; 266 267 union { 268 __le32 ol_info; 269 struct { 270 __le16 o_dm_vlan_id_fb; 271 __le16 ot_vlan_tag; 272 }; 273 }; 274 275 __le32 bd_base_info; 276 } rx; 277 }; 278 }; 279 280 struct hns3_desc_cb { 281 dma_addr_t dma; /* dma address of this desc */ 282 void *buf; /* cpu addr for a desc */ 283 284 /* priv data for the desc, e.g. skb when use with ip stack*/ 285 void *priv; 286 u16 page_offset; 287 u16 reuse_flag; 288 289 u16 length; /* length of the buffer */ 290 291 /* desc type, used by the ring user to mark the type of the priv data */ 292 u16 type; 293 }; 294 295 enum hns3_pkt_l3type { 296 HNS3_L3_TYPE_IPV4, 297 HNS3_L3_TYPE_IPV6, 298 HNS3_L3_TYPE_ARP, 299 HNS3_L3_TYPE_RARP, 300 HNS3_L3_TYPE_IPV4_OPT, 301 HNS3_L3_TYPE_IPV6_EXT, 302 HNS3_L3_TYPE_LLDP, 303 HNS3_L3_TYPE_BPDU, 304 HNS3_L3_TYPE_MAC_PAUSE, 305 HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/ 306 307 /* reserved for 0xA~0xB*/ 308 309 HNS3_L3_TYPE_CNM = 0xc, 310 311 /* reserved for 0xD~0xE*/ 312 313 HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */ 314 }; 315 316 enum hns3_pkt_l4type { 317 HNS3_L4_TYPE_UDP, 318 HNS3_L4_TYPE_TCP, 319 HNS3_L4_TYPE_GRE, 320 HNS3_L4_TYPE_SCTP, 321 HNS3_L4_TYPE_IGMP, 322 HNS3_L4_TYPE_ICMP, 323 324 /* reserved for 0x6~0xE */ 325 326 HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */ 327 }; 328 329 enum hns3_pkt_ol3type { 330 HNS3_OL3_TYPE_IPV4 = 0, 331 HNS3_OL3_TYPE_IPV6, 332 /* reserved for 0x2~0x3 */ 333 HNS3_OL3_TYPE_IPV4_OPT = 4, 334 HNS3_OL3_TYPE_IPV6_EXT, 335 336 /* reserved for 0x6~0xE*/ 337 338 HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */ 339 }; 340 341 enum hns3_pkt_ol4type { 342 HNS3_OL4_TYPE_NO_TUN, 343 HNS3_OL4_TYPE_MAC_IN_UDP, 344 HNS3_OL4_TYPE_NVGRE, 345 HNS3_OL4_TYPE_UNKNOWN 346 }; 347 348 struct ring_stats { 349 u64 io_err_cnt; 350 u64 sw_err_cnt; 351 u64 seg_pkt_cnt; 352 union { 353 struct { 354 u64 tx_pkts; 355 u64 tx_bytes; 356 u64 tx_err_cnt; 357 u64 restart_queue; 358 u64 tx_busy; 359 }; 360 struct { 361 u64 rx_pkts; 362 u64 rx_bytes; 363 u64 rx_err_cnt; 364 u64 reuse_pg_cnt; 365 u64 err_pkt_len; 366 u64 non_vld_descs; 367 u64 err_bd_num; 368 u64 l2_err; 369 u64 l3l4_csum_err; 370 }; 371 }; 372 }; 373 374 struct hns3_enet_ring { 375 u8 __iomem *io_base; /* base io address for the ring */ 376 struct hns3_desc *desc; /* dma map address space */ 377 struct hns3_desc_cb *desc_cb; 378 struct hns3_enet_ring *next; 379 struct hns3_enet_tqp_vector *tqp_vector; 380 struct hnae3_queue *tqp; 381 char ring_name[HNS3_RING_NAME_LEN]; 382 struct device *dev; /* will be used for DMA mapping of descriptors */ 383 384 /* statistic */ 385 struct ring_stats stats; 386 struct u64_stats_sync syncp; 387 388 dma_addr_t desc_dma_addr; 389 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 390 u16 desc_num; /* total number of desc */ 391 u16 max_desc_num_per_pkt; 392 u16 max_raw_data_sz_per_desc; 393 u16 max_pkt_size; 394 int next_to_use; /* idx of next spare desc */ 395 396 /* idx of lastest sent desc, the ring is empty when equal to 397 * next_to_use 398 */ 399 int next_to_clean; 400 401 u32 flag; /* ring attribute */ 402 int irq_init_flag; 403 404 int numa_node; 405 cpumask_t affinity_mask; 406 }; 407 408 struct hns_queue; 409 410 struct hns3_nic_ring_data { 411 struct hns3_enet_ring *ring; 412 struct napi_struct napi; 413 int queue_index; 414 int (*poll_one)(struct hns3_nic_ring_data *, int, void *); 415 void (*ex_process)(struct hns3_nic_ring_data *, struct sk_buff *); 416 void (*fini_process)(struct hns3_nic_ring_data *); 417 }; 418 419 struct hns3_nic_ops { 420 int (*fill_desc)(struct hns3_enet_ring *ring, void *priv, 421 int size, dma_addr_t dma, int frag_end, 422 enum hns_desc_type type); 423 int (*maybe_stop_tx)(struct sk_buff **out_skb, 424 int *bnum, struct hns3_enet_ring *ring); 425 void (*get_rxd_bnum)(u32 bnum_flag, int *out_bnum); 426 }; 427 428 enum hns3_flow_level_range { 429 HNS3_FLOW_LOW = 0, 430 HNS3_FLOW_MID = 1, 431 HNS3_FLOW_HIGH = 2, 432 HNS3_FLOW_ULTRA = 3, 433 }; 434 435 enum hns3_link_mode_bits { 436 HNS3_LM_FIBRE_BIT = BIT(0), 437 HNS3_LM_AUTONEG_BIT = BIT(1), 438 HNS3_LM_TP_BIT = BIT(2), 439 HNS3_LM_PAUSE_BIT = BIT(3), 440 HNS3_LM_BACKPLANE_BIT = BIT(4), 441 HNS3_LM_10BASET_HALF_BIT = BIT(5), 442 HNS3_LM_10BASET_FULL_BIT = BIT(6), 443 HNS3_LM_100BASET_HALF_BIT = BIT(7), 444 HNS3_LM_100BASET_FULL_BIT = BIT(8), 445 HNS3_LM_1000BASET_FULL_BIT = BIT(9), 446 HNS3_LM_10000BASEKR_FULL_BIT = BIT(10), 447 HNS3_LM_25000BASEKR_FULL_BIT = BIT(11), 448 HNS3_LM_40000BASELR4_FULL_BIT = BIT(12), 449 HNS3_LM_50000BASEKR2_FULL_BIT = BIT(13), 450 HNS3_LM_100000BASEKR4_FULL_BIT = BIT(14), 451 HNS3_LM_COUNT = 15 452 }; 453 454 #define HNS3_INT_GL_MAX 0x1FE0 455 #define HNS3_INT_GL_50K 0x0014 456 #define HNS3_INT_GL_20K 0x0032 457 #define HNS3_INT_GL_18K 0x0036 458 #define HNS3_INT_GL_8K 0x007C 459 460 #define HNS3_INT_RL_MAX 0x00EC 461 #define HNS3_INT_RL_ENABLE_MASK 0x40 462 463 struct hns3_enet_ring_group { 464 /* array of pointers to rings */ 465 struct hns3_enet_ring *ring; 466 u64 total_bytes; /* total bytes processed this group */ 467 u64 total_packets; /* total packets processed this group */ 468 u16 count; 469 enum hns3_flow_level_range flow_level; 470 u16 int_gl; 471 u8 gl_adapt_enable; 472 }; 473 474 struct hns3_enet_tqp_vector { 475 struct hnae3_handle *handle; 476 u8 __iomem *mask_addr; 477 int vector_irq; 478 int irq_init_flag; 479 480 u16 idx; /* index in the TQP vector array per handle. */ 481 482 struct napi_struct napi; 483 484 struct hns3_enet_ring_group rx_group; 485 struct hns3_enet_ring_group tx_group; 486 487 u16 num_tqps; /* total number of tqps in TQP vector */ 488 489 cpumask_t affinity_mask; 490 char name[HNAE3_INT_NAME_LEN]; 491 492 /* when 0 should adjust interrupt coalesce parameter */ 493 u8 int_adapt_down; 494 } ____cacheline_internodealigned_in_smp; 495 496 enum hns3_udp_tnl_type { 497 HNS3_UDP_TNL_VXLAN, 498 HNS3_UDP_TNL_GENEVE, 499 HNS3_UDP_TNL_MAX, 500 }; 501 502 struct hns3_udp_tunnel { 503 u16 dst_port; 504 int used; 505 }; 506 507 struct hns3_nic_priv { 508 struct hnae3_handle *ae_handle; 509 u32 enet_ver; 510 u32 port_id; 511 struct net_device *netdev; 512 struct device *dev; 513 struct hns3_nic_ops ops; 514 515 /** 516 * the cb for nic to manage the ring buffer, the first half of the 517 * array is for tx_ring and vice versa for the second half 518 */ 519 struct hns3_nic_ring_data *ring_data; 520 struct hns3_enet_tqp_vector *tqp_vector; 521 u16 vector_num; 522 523 /* The most recently read link state */ 524 int link; 525 u64 tx_timeout_count; 526 enum hnae3_reset_type reset_level; 527 unsigned long last_reset_time; 528 529 unsigned long state; 530 531 struct timer_list service_timer; 532 533 struct work_struct service_task; 534 535 struct notifier_block notifier_block; 536 /* Vxlan/Geneve information */ 537 struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX]; 538 }; 539 540 union l3_hdr_info { 541 struct iphdr *v4; 542 struct ipv6hdr *v6; 543 unsigned char *hdr; 544 }; 545 546 union l4_hdr_info { 547 struct tcphdr *tcp; 548 struct udphdr *udp; 549 unsigned char *hdr; 550 }; 551 552 /* the distance between [begin, end) in a ring buffer 553 * note: there is a unuse slot between the begin and the end 554 */ 555 static inline int ring_dist(struct hns3_enet_ring *ring, int begin, int end) 556 { 557 return (end - begin + ring->desc_num) % ring->desc_num; 558 } 559 560 static inline int ring_space(struct hns3_enet_ring *ring) 561 { 562 return ring->desc_num - 563 ring_dist(ring, ring->next_to_clean, ring->next_to_use) - 1; 564 } 565 566 static inline int is_ring_empty(struct hns3_enet_ring *ring) 567 { 568 return ring->next_to_use == ring->next_to_clean; 569 } 570 571 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value) 572 { 573 u8 __iomem *reg_addr = READ_ONCE(base); 574 575 writel(value, reg_addr + reg); 576 } 577 578 #define hns3_write_dev(a, reg, value) \ 579 hns3_write_reg((a)->io_base, (reg), (value)) 580 581 #define hnae_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \ 582 (tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG) 583 584 #define ring_to_dev(ring) (&(ring)->tqp->handle->pdev->dev) 585 586 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \ 587 DMA_TO_DEVICE : DMA_FROM_DEVICE) 588 589 #define tx_ring_data(priv, idx) ((priv)->ring_data[idx]) 590 591 #define hnae_buf_size(_ring) ((_ring)->buf_size) 592 #define hnae_page_order(_ring) (get_order(hnae_buf_size(_ring))) 593 #define hnae_page_size(_ring) (PAGE_SIZE << hnae_page_order(_ring)) 594 595 /* iterator for handling rings in ring group */ 596 #define hns3_for_each_ring(pos, head) \ 597 for (pos = (head).ring; pos; pos = pos->next) 598 599 #define hns3_get_handle(ndev) \ 600 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle) 601 602 #define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1) 603 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2) 604 605 #define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2) 606 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4) 607 608 void hns3_ethtool_set_ops(struct net_device *netdev); 609 int hns3_set_channels(struct net_device *netdev, 610 struct ethtool_channels *ch); 611 612 bool hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget); 613 int hns3_init_all_ring(struct hns3_nic_priv *priv); 614 int hns3_uninit_all_ring(struct hns3_nic_priv *priv); 615 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev); 616 int hns3_clean_rx_ring( 617 struct hns3_enet_ring *ring, int budget, 618 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)); 619 620 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 621 u32 gl_value); 622 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 623 u32 gl_value); 624 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 625 u32 rl_value); 626 627 #ifdef CONFIG_HNS3_DCB 628 void hns3_dcbnl_setup(struct hnae3_handle *handle); 629 #else 630 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {} 631 #endif 632 633 #endif 634