1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HNS3_ENET_H 5 #define __HNS3_ENET_H 6 7 #include <linux/dim.h> 8 #include <linux/if_vlan.h> 9 10 #include "hnae3.h" 11 12 enum hns3_nic_state { 13 HNS3_NIC_STATE_TESTING, 14 HNS3_NIC_STATE_RESETTING, 15 HNS3_NIC_STATE_INITED, 16 HNS3_NIC_STATE_DOWN, 17 HNS3_NIC_STATE_DISABLED, 18 HNS3_NIC_STATE_REMOVING, 19 HNS3_NIC_STATE_SERVICE_INITED, 20 HNS3_NIC_STATE_SERVICE_SCHED, 21 HNS3_NIC_STATE2_RESET_REQUESTED, 22 HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, 23 HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, 24 HNS3_NIC_STATE_MAX 25 }; 26 27 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000 28 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004 29 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008 30 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C 31 #define HNS3_RING_RX_RING_TAIL_REG 0x00018 32 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C 33 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020 34 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C 35 36 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040 37 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044 38 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048 39 #define HNS3_RING_TX_RING_TC_REG 0x00050 40 #define HNS3_RING_TX_RING_TAIL_REG 0x00058 41 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C 42 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060 43 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064 44 #define HNS3_RING_TX_RING_EBDNUM_REG 0x00068 45 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C 46 #define HNS3_RING_TX_RING_EBD_OFFSET_REG 0x00070 47 #define HNS3_RING_TX_RING_BD_ERR_REG 0x00074 48 #define HNS3_RING_EN_REG 0x00090 49 #define HNS3_RING_RX_EN_REG 0x00098 50 #define HNS3_RING_TX_EN_REG 0x000D4 51 52 #define HNS3_RX_HEAD_SIZE 256 53 54 #define HNS3_TX_TIMEOUT (5 * HZ) 55 #define HNS3_RING_NAME_LEN 16 56 #define HNS3_BUFFER_SIZE_2048 2048 57 #define HNS3_RING_MAX_PENDING 32760 58 #define HNS3_RING_MIN_PENDING 72 59 #define HNS3_RING_BD_MULTIPLE 8 60 /* max frame size of mac */ 61 #define HNS3_MAX_MTU(max_frm_size) \ 62 ((max_frm_size) - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN)) 63 64 #define HNS3_BD_SIZE_512_TYPE 0 65 #define HNS3_BD_SIZE_1024_TYPE 1 66 #define HNS3_BD_SIZE_2048_TYPE 2 67 #define HNS3_BD_SIZE_4096_TYPE 3 68 69 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1 70 #define HNS3_RX_FLAG_L3ID_IPV4 0x0 71 #define HNS3_RX_FLAG_L3ID_IPV6 0x1 72 #define HNS3_RX_FLAG_L4ID_UDP 0x0 73 #define HNS3_RX_FLAG_L4ID_TCP 0x1 74 75 #define HNS3_RXD_DMAC_S 0 76 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S) 77 #define HNS3_RXD_VLAN_S 2 78 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S) 79 #define HNS3_RXD_L3ID_S 4 80 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S) 81 #define HNS3_RXD_L4ID_S 8 82 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S) 83 #define HNS3_RXD_FRAG_B 12 84 #define HNS3_RXD_STRP_TAGP_S 13 85 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S) 86 87 #define HNS3_RXD_L2E_B 16 88 #define HNS3_RXD_L3E_B 17 89 #define HNS3_RXD_L4E_B 18 90 #define HNS3_RXD_TRUNCAT_B 19 91 #define HNS3_RXD_HOI_B 20 92 #define HNS3_RXD_DOI_B 21 93 #define HNS3_RXD_OL3E_B 22 94 #define HNS3_RXD_OL4E_B 23 95 #define HNS3_RXD_GRO_COUNT_S 24 96 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S) 97 #define HNS3_RXD_GRO_FIXID_B 30 98 #define HNS3_RXD_GRO_ECN_B 31 99 100 #define HNS3_RXD_ODMAC_S 0 101 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S) 102 #define HNS3_RXD_OVLAN_S 2 103 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S) 104 #define HNS3_RXD_OL3ID_S 4 105 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S) 106 #define HNS3_RXD_OL4ID_S 8 107 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S) 108 #define HNS3_RXD_FBHI_S 12 109 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S) 110 #define HNS3_RXD_FBLI_S 14 111 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S) 112 113 #define HNS3_RXD_PTYPE_S 4 114 #define HNS3_RXD_PTYPE_M GENMASK(11, 4) 115 116 #define HNS3_RXD_BDTYPE_S 0 117 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S) 118 #define HNS3_RXD_VLD_B 4 119 #define HNS3_RXD_UDP0_B 5 120 #define HNS3_RXD_EXTEND_B 7 121 #define HNS3_RXD_FE_B 8 122 #define HNS3_RXD_LUM_B 9 123 #define HNS3_RXD_CRCP_B 10 124 #define HNS3_RXD_L3L4P_B 11 125 #define HNS3_RXD_TSIND_S 12 126 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S) 127 #define HNS3_RXD_LKBK_B 15 128 #define HNS3_RXD_GRO_SIZE_S 16 129 #define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S) 130 131 #define HNS3_TXD_L3T_S 0 132 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S) 133 #define HNS3_TXD_L4T_S 2 134 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S) 135 #define HNS3_TXD_L3CS_B 4 136 #define HNS3_TXD_L4CS_B 5 137 #define HNS3_TXD_VLAN_B 6 138 #define HNS3_TXD_TSO_B 7 139 140 #define HNS3_TXD_L2LEN_S 8 141 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S) 142 #define HNS3_TXD_L3LEN_S 16 143 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S) 144 #define HNS3_TXD_L4LEN_S 24 145 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S) 146 147 #define HNS3_TXD_CSUM_START_S 8 148 #define HNS3_TXD_CSUM_START_M (0xffff << HNS3_TXD_CSUM_START_S) 149 150 #define HNS3_TXD_OL3T_S 0 151 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S) 152 #define HNS3_TXD_OVLAN_B 2 153 #define HNS3_TXD_MACSEC_B 3 154 #define HNS3_TXD_TUNTYPE_S 4 155 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S) 156 157 #define HNS3_TXD_CSUM_OFFSET_S 8 158 #define HNS3_TXD_CSUM_OFFSET_M (0xffff << HNS3_TXD_CSUM_OFFSET_S) 159 160 #define HNS3_TXD_BDTYPE_S 0 161 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S) 162 #define HNS3_TXD_FE_B 4 163 #define HNS3_TXD_SC_S 5 164 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S) 165 #define HNS3_TXD_EXTEND_B 7 166 #define HNS3_TXD_VLD_B 8 167 #define HNS3_TXD_RI_B 9 168 #define HNS3_TXD_RA_B 10 169 #define HNS3_TXD_TSYN_B 11 170 #define HNS3_TXD_DECTTL_S 12 171 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S) 172 173 #define HNS3_TXD_OL4CS_B 22 174 175 #define HNS3_TXD_MSS_S 0 176 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) 177 #define HNS3_TXD_HW_CS_B 14 178 179 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0) 180 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1) 181 182 #define HNS3_VECTOR_NOT_INITED 0 183 #define HNS3_VECTOR_INITED 1 184 185 #define HNS3_MAX_BD_SIZE 65535 186 #define HNS3_MAX_TSO_BD_NUM 63U 187 #define HNS3_MAX_TSO_SIZE \ 188 (HNS3_MAX_BD_SIZE * HNS3_MAX_TSO_BD_NUM) 189 190 #define HNS3_MAX_NON_TSO_SIZE(max_non_tso_bd_num) \ 191 (HNS3_MAX_BD_SIZE * (max_non_tso_bd_num)) 192 193 #define HNS3_VECTOR_GL0_OFFSET 0x100 194 #define HNS3_VECTOR_GL1_OFFSET 0x200 195 #define HNS3_VECTOR_GL2_OFFSET 0x300 196 #define HNS3_VECTOR_RL_OFFSET 0x900 197 #define HNS3_VECTOR_RL_EN_B 6 198 #define HNS3_VECTOR_TX_QL_OFFSET 0xe00 199 #define HNS3_VECTOR_RX_QL_OFFSET 0xf00 200 201 #define HNS3_RING_EN_B 0 202 203 enum hns3_pkt_l2t_type { 204 HNS3_L2_TYPE_UNICAST, 205 HNS3_L2_TYPE_MULTICAST, 206 HNS3_L2_TYPE_BROADCAST, 207 HNS3_L2_TYPE_INVALID, 208 }; 209 210 enum hns3_pkt_l3t_type { 211 HNS3_L3T_NONE, 212 HNS3_L3T_IPV6, 213 HNS3_L3T_IPV4, 214 HNS3_L3T_RESERVED 215 }; 216 217 enum hns3_pkt_l4t_type { 218 HNS3_L4T_UNKNOWN, 219 HNS3_L4T_TCP, 220 HNS3_L4T_UDP, 221 HNS3_L4T_SCTP 222 }; 223 224 enum hns3_pkt_ol3t_type { 225 HNS3_OL3T_NONE, 226 HNS3_OL3T_IPV6, 227 HNS3_OL3T_IPV4_NO_CSUM, 228 HNS3_OL3T_IPV4_CSUM 229 }; 230 231 enum hns3_pkt_tun_type { 232 HNS3_TUN_NONE, 233 HNS3_TUN_MAC_IN_UDP, 234 HNS3_TUN_NVGRE, 235 HNS3_TUN_OTHER 236 }; 237 238 /* hardware spec ring buffer format */ 239 struct __packed hns3_desc { 240 union { 241 __le64 addr; 242 __le16 csum; 243 }; 244 union { 245 struct { 246 __le16 vlan_tag; 247 __le16 send_size; 248 union { 249 __le32 type_cs_vlan_tso_len; 250 struct { 251 __u8 type_cs_vlan_tso; 252 __u8 l2_len; 253 __u8 l3_len; 254 __u8 l4_len; 255 }; 256 }; 257 __le16 outer_vlan_tag; 258 __le16 tv; 259 260 union { 261 __le32 ol_type_vlan_len_msec; 262 struct { 263 __u8 ol_type_vlan_msec; 264 __u8 ol2_len; 265 __u8 ol3_len; 266 __u8 ol4_len; 267 }; 268 }; 269 270 __le32 paylen_ol4cs; 271 __le16 bdtp_fe_sc_vld_ra_ri; 272 __le16 mss_hw_csum; 273 } tx; 274 275 struct { 276 __le32 l234_info; 277 __le16 pkt_len; 278 __le16 size; 279 280 __le32 rss_hash; 281 __le16 fd_id; 282 __le16 vlan_tag; 283 284 union { 285 __le32 ol_info; 286 struct { 287 __le16 o_dm_vlan_id_fb; 288 __le16 ot_vlan_tag; 289 }; 290 }; 291 292 __le32 bd_base_info; 293 } rx; 294 }; 295 }; 296 297 struct hns3_desc_cb { 298 dma_addr_t dma; /* dma address of this desc */ 299 void *buf; /* cpu addr for a desc */ 300 301 /* priv data for the desc, e.g. skb when use with ip stack */ 302 void *priv; 303 304 union { 305 u32 page_offset; /* for rx */ 306 u32 send_bytes; /* for tx */ 307 }; 308 309 u32 length; /* length of the buffer */ 310 311 u16 reuse_flag; 312 313 /* desc type, used by the ring user to mark the type of the priv data */ 314 u16 type; 315 u16 pagecnt_bias; 316 }; 317 318 enum hns3_pkt_l3type { 319 HNS3_L3_TYPE_IPV4, 320 HNS3_L3_TYPE_IPV6, 321 HNS3_L3_TYPE_ARP, 322 HNS3_L3_TYPE_RARP, 323 HNS3_L3_TYPE_IPV4_OPT, 324 HNS3_L3_TYPE_IPV6_EXT, 325 HNS3_L3_TYPE_LLDP, 326 HNS3_L3_TYPE_BPDU, 327 HNS3_L3_TYPE_MAC_PAUSE, 328 HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/ 329 330 /* reserved for 0xA~0xB */ 331 332 HNS3_L3_TYPE_CNM = 0xc, 333 334 /* reserved for 0xD~0xE */ 335 336 HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */ 337 }; 338 339 enum hns3_pkt_l4type { 340 HNS3_L4_TYPE_UDP, 341 HNS3_L4_TYPE_TCP, 342 HNS3_L4_TYPE_GRE, 343 HNS3_L4_TYPE_SCTP, 344 HNS3_L4_TYPE_IGMP, 345 HNS3_L4_TYPE_ICMP, 346 347 /* reserved for 0x6~0xE */ 348 349 HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */ 350 }; 351 352 enum hns3_pkt_ol3type { 353 HNS3_OL3_TYPE_IPV4 = 0, 354 HNS3_OL3_TYPE_IPV6, 355 /* reserved for 0x2~0x3 */ 356 HNS3_OL3_TYPE_IPV4_OPT = 4, 357 HNS3_OL3_TYPE_IPV6_EXT, 358 359 /* reserved for 0x6~0xE */ 360 361 HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */ 362 }; 363 364 enum hns3_pkt_ol4type { 365 HNS3_OL4_TYPE_NO_TUN, 366 HNS3_OL4_TYPE_MAC_IN_UDP, 367 HNS3_OL4_TYPE_NVGRE, 368 HNS3_OL4_TYPE_UNKNOWN 369 }; 370 371 struct hns3_rx_ptype { 372 u32 ptype:8; 373 u32 csum_level:2; 374 u32 ip_summed:2; 375 u32 l3_type:4; 376 u32 valid:1; 377 }; 378 379 struct ring_stats { 380 u64 sw_err_cnt; 381 u64 seg_pkt_cnt; 382 union { 383 struct { 384 u64 tx_pkts; 385 u64 tx_bytes; 386 u64 tx_more; 387 u64 restart_queue; 388 u64 tx_busy; 389 u64 tx_copy; 390 u64 tx_vlan_err; 391 u64 tx_l4_proto_err; 392 u64 tx_l2l3l4_err; 393 u64 tx_tso_err; 394 u64 over_max_recursion; 395 u64 hw_limitation; 396 }; 397 struct { 398 u64 rx_pkts; 399 u64 rx_bytes; 400 u64 rx_err_cnt; 401 u64 reuse_pg_cnt; 402 u64 err_pkt_len; 403 u64 err_bd_num; 404 u64 l2_err; 405 u64 l3l4_csum_err; 406 u64 csum_complete; 407 u64 rx_multicast; 408 u64 non_reuse_pg; 409 }; 410 __le16 csum; 411 }; 412 }; 413 414 struct hns3_enet_ring { 415 struct hns3_desc *desc; /* dma map address space */ 416 struct hns3_desc_cb *desc_cb; 417 struct hns3_enet_ring *next; 418 struct hns3_enet_tqp_vector *tqp_vector; 419 struct hnae3_queue *tqp; 420 int queue_index; 421 struct device *dev; /* will be used for DMA mapping of descriptors */ 422 423 /* statistic */ 424 struct ring_stats stats; 425 struct u64_stats_sync syncp; 426 427 dma_addr_t desc_dma_addr; 428 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 429 u16 desc_num; /* total number of desc */ 430 int next_to_use; /* idx of next spare desc */ 431 432 /* idx of lastest sent desc, the ring is empty when equal to 433 * next_to_use 434 */ 435 int next_to_clean; 436 union { 437 int last_to_use; /* last idx used by xmit */ 438 u32 pull_len; /* memcpy len for current rx packet */ 439 }; 440 u32 frag_num; 441 void *va; /* first buffer address for current packet */ 442 443 u32 flag; /* ring attribute */ 444 445 int pending_buf; 446 struct sk_buff *skb; 447 struct sk_buff *tail_skb; 448 } ____cacheline_internodealigned_in_smp; 449 450 enum hns3_flow_level_range { 451 HNS3_FLOW_LOW = 0, 452 HNS3_FLOW_MID = 1, 453 HNS3_FLOW_HIGH = 2, 454 HNS3_FLOW_ULTRA = 3, 455 }; 456 457 #define HNS3_INT_GL_50K 0x0014 458 #define HNS3_INT_GL_20K 0x0032 459 #define HNS3_INT_GL_18K 0x0036 460 #define HNS3_INT_GL_8K 0x007C 461 462 #define HNS3_INT_GL_1US BIT(31) 463 464 #define HNS3_INT_RL_MAX 0x00EC 465 #define HNS3_INT_RL_ENABLE_MASK 0x40 466 467 #define HNS3_INT_QL_DEFAULT_CFG 0x20 468 469 struct hns3_enet_coalesce { 470 u16 int_gl; 471 u16 int_ql; 472 u16 int_ql_max; 473 u8 adapt_enable:1; 474 u8 ql_enable:1; 475 u8 unit_1us:1; 476 enum hns3_flow_level_range flow_level; 477 }; 478 479 struct hns3_enet_ring_group { 480 /* array of pointers to rings */ 481 struct hns3_enet_ring *ring; 482 u64 total_bytes; /* total bytes processed this group */ 483 u64 total_packets; /* total packets processed this group */ 484 u16 count; 485 struct hns3_enet_coalesce coal; 486 struct dim dim; 487 }; 488 489 struct hns3_enet_tqp_vector { 490 struct hnae3_handle *handle; 491 u8 __iomem *mask_addr; 492 int vector_irq; 493 int irq_init_flag; 494 495 u16 idx; /* index in the TQP vector array per handle. */ 496 497 struct napi_struct napi; 498 499 struct hns3_enet_ring_group rx_group; 500 struct hns3_enet_ring_group tx_group; 501 502 cpumask_t affinity_mask; 503 u16 num_tqps; /* total number of tqps in TQP vector */ 504 struct irq_affinity_notify affinity_notify; 505 506 char name[HNAE3_INT_NAME_LEN]; 507 508 u64 event_cnt; 509 } ____cacheline_internodealigned_in_smp; 510 511 struct hns3_nic_priv { 512 struct hnae3_handle *ae_handle; 513 struct net_device *netdev; 514 struct device *dev; 515 516 /** 517 * the cb for nic to manage the ring buffer, the first half of the 518 * array is for tx_ring and vice versa for the second half 519 */ 520 struct hns3_enet_ring *ring; 521 struct hns3_enet_tqp_vector *tqp_vector; 522 u16 vector_num; 523 u8 max_non_tso_bd_num; 524 525 u64 tx_timeout_count; 526 527 unsigned long state; 528 529 struct hns3_enet_coalesce tx_coal; 530 struct hns3_enet_coalesce rx_coal; 531 }; 532 533 union l3_hdr_info { 534 struct iphdr *v4; 535 struct ipv6hdr *v6; 536 unsigned char *hdr; 537 }; 538 539 union l4_hdr_info { 540 struct tcphdr *tcp; 541 struct udphdr *udp; 542 struct gre_base_hdr *gre; 543 unsigned char *hdr; 544 }; 545 546 struct hns3_hw_error_info { 547 enum hnae3_hw_error_type type; 548 const char *msg; 549 }; 550 551 static inline int ring_space(struct hns3_enet_ring *ring) 552 { 553 /* This smp_load_acquire() pairs with smp_store_release() in 554 * hns3_nic_reclaim_one_desc called by hns3_clean_tx_ring. 555 */ 556 int begin = smp_load_acquire(&ring->next_to_clean); 557 int end = READ_ONCE(ring->next_to_use); 558 559 return ((end >= begin) ? (ring->desc_num - end + begin) : 560 (begin - end)) - 1; 561 } 562 563 static inline u32 hns3_read_reg(void __iomem *base, u32 reg) 564 { 565 return readl(base + reg); 566 } 567 568 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value) 569 { 570 u8 __iomem *reg_addr = READ_ONCE(base); 571 572 writel(value, reg_addr + reg); 573 } 574 575 #define hns3_read_dev(a, reg) \ 576 hns3_read_reg((a)->io_base, reg) 577 578 static inline bool hns3_nic_resetting(struct net_device *netdev) 579 { 580 struct hns3_nic_priv *priv = netdev_priv(netdev); 581 582 return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 583 } 584 585 #define hns3_write_dev(a, reg, value) \ 586 hns3_write_reg((a)->io_base, reg, value) 587 588 #define ring_to_dev(ring) ((ring)->dev) 589 590 #define ring_to_netdev(ring) ((ring)->tqp_vector->napi.dev) 591 592 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \ 593 DMA_TO_DEVICE : DMA_FROM_DEVICE) 594 595 #define hns3_buf_size(_ring) ((_ring)->buf_size) 596 597 static inline unsigned int hns3_page_order(struct hns3_enet_ring *ring) 598 { 599 #if (PAGE_SIZE < 8192) 600 if (ring->buf_size > (PAGE_SIZE / 2)) 601 return 1; 602 #endif 603 return 0; 604 } 605 606 #define hns3_page_size(_ring) (PAGE_SIZE << hns3_page_order(_ring)) 607 608 /* iterator for handling rings in ring group */ 609 #define hns3_for_each_ring(pos, head) \ 610 for (pos = (head).ring; (pos); pos = (pos)->next) 611 612 #define hns3_get_handle(ndev) \ 613 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle) 614 615 #define hns3_gl_usec_to_reg(int_gl) ((int_gl) >> 1) 616 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2) 617 618 #define hns3_rl_usec_to_reg(int_rl) ((int_rl) >> 2) 619 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4) 620 621 void hns3_ethtool_set_ops(struct net_device *netdev); 622 int hns3_set_channels(struct net_device *netdev, 623 struct ethtool_channels *ch); 624 625 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget); 626 int hns3_init_all_ring(struct hns3_nic_priv *priv); 627 int hns3_nic_reset_all_ring(struct hnae3_handle *h); 628 void hns3_fini_ring(struct hns3_enet_ring *ring); 629 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev); 630 bool hns3_is_phys_func(struct pci_dev *pdev); 631 int hns3_clean_rx_ring( 632 struct hns3_enet_ring *ring, int budget, 633 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)); 634 635 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 636 u32 gl_value); 637 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 638 u32 gl_value); 639 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 640 u32 rl_value); 641 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector, 642 u32 ql_value); 643 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector, 644 u32 ql_value); 645 646 void hns3_request_update_promisc_mode(struct hnae3_handle *handle); 647 648 #ifdef CONFIG_HNS3_DCB 649 void hns3_dcbnl_setup(struct hnae3_handle *handle); 650 #else 651 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {} 652 #endif 653 654 int hns3_dbg_init(struct hnae3_handle *handle); 655 void hns3_dbg_uninit(struct hnae3_handle *handle); 656 void hns3_dbg_register_debugfs(const char *debugfs_dir_name); 657 void hns3_dbg_unregister_debugfs(void); 658 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size); 659 u16 hns3_get_max_available_channels(struct hnae3_handle *h); 660 #endif 661