1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HNS3_ENET_H 5 #define __HNS3_ENET_H 6 7 #include <linux/dim.h> 8 #include <linux/if_vlan.h> 9 #include <net/page_pool.h> 10 11 #include "hnae3.h" 12 13 struct iphdr; 14 struct ipv6hdr; 15 16 enum hns3_nic_state { 17 HNS3_NIC_STATE_TESTING, 18 HNS3_NIC_STATE_RESETTING, 19 HNS3_NIC_STATE_INITED, 20 HNS3_NIC_STATE_DOWN, 21 HNS3_NIC_STATE_DISABLED, 22 HNS3_NIC_STATE_REMOVING, 23 HNS3_NIC_STATE_SERVICE_INITED, 24 HNS3_NIC_STATE_SERVICE_SCHED, 25 HNS3_NIC_STATE2_RESET_REQUESTED, 26 HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, 27 HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, 28 HNS3_NIC_STATE_MAX 29 }; 30 31 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000 32 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004 33 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008 34 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C 35 #define HNS3_RING_RX_RING_TAIL_REG 0x00018 36 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C 37 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020 38 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C 39 40 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040 41 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044 42 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048 43 #define HNS3_RING_TX_RING_TC_REG 0x00050 44 #define HNS3_RING_TX_RING_TAIL_REG 0x00058 45 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C 46 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060 47 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064 48 #define HNS3_RING_TX_RING_EBDNUM_REG 0x00068 49 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C 50 #define HNS3_RING_TX_RING_EBD_OFFSET_REG 0x00070 51 #define HNS3_RING_TX_RING_BD_ERR_REG 0x00074 52 #define HNS3_RING_EN_REG 0x00090 53 #define HNS3_RING_RX_EN_REG 0x00098 54 #define HNS3_RING_TX_EN_REG 0x000D4 55 56 #define HNS3_RX_HEAD_SIZE 256 57 58 #define HNS3_TX_TIMEOUT (5 * HZ) 59 #define HNS3_RING_NAME_LEN 16 60 #define HNS3_BUFFER_SIZE_2048 2048 61 #define HNS3_RING_MAX_PENDING 32760 62 #define HNS3_RING_MIN_PENDING 72 63 #define HNS3_RING_BD_MULTIPLE 8 64 /* max frame size of mac */ 65 #define HNS3_MAX_MTU(max_frm_size) \ 66 ((max_frm_size) - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN)) 67 68 #define HNS3_BD_SIZE_512_TYPE 0 69 #define HNS3_BD_SIZE_1024_TYPE 1 70 #define HNS3_BD_SIZE_2048_TYPE 2 71 #define HNS3_BD_SIZE_4096_TYPE 3 72 73 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1 74 #define HNS3_RX_FLAG_L3ID_IPV4 0x0 75 #define HNS3_RX_FLAG_L3ID_IPV6 0x1 76 #define HNS3_RX_FLAG_L4ID_UDP 0x0 77 #define HNS3_RX_FLAG_L4ID_TCP 0x1 78 79 #define HNS3_RXD_DMAC_S 0 80 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S) 81 #define HNS3_RXD_VLAN_S 2 82 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S) 83 #define HNS3_RXD_L3ID_S 4 84 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S) 85 #define HNS3_RXD_L4ID_S 8 86 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S) 87 #define HNS3_RXD_FRAG_B 12 88 #define HNS3_RXD_STRP_TAGP_S 13 89 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S) 90 91 #define HNS3_RXD_L2E_B 16 92 #define HNS3_RXD_L3E_B 17 93 #define HNS3_RXD_L4E_B 18 94 #define HNS3_RXD_TRUNCAT_B 19 95 #define HNS3_RXD_HOI_B 20 96 #define HNS3_RXD_DOI_B 21 97 #define HNS3_RXD_OL3E_B 22 98 #define HNS3_RXD_OL4E_B 23 99 #define HNS3_RXD_GRO_COUNT_S 24 100 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S) 101 #define HNS3_RXD_GRO_FIXID_B 30 102 #define HNS3_RXD_GRO_ECN_B 31 103 104 #define HNS3_RXD_ODMAC_S 0 105 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S) 106 #define HNS3_RXD_OVLAN_S 2 107 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S) 108 #define HNS3_RXD_OL3ID_S 4 109 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S) 110 #define HNS3_RXD_OL4ID_S 8 111 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S) 112 #define HNS3_RXD_FBHI_S 12 113 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S) 114 #define HNS3_RXD_FBLI_S 14 115 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S) 116 117 #define HNS3_RXD_PTYPE_S 4 118 #define HNS3_RXD_PTYPE_M GENMASK(11, 4) 119 120 #define HNS3_RXD_BDTYPE_S 0 121 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S) 122 #define HNS3_RXD_VLD_B 4 123 #define HNS3_RXD_UDP0_B 5 124 #define HNS3_RXD_EXTEND_B 7 125 #define HNS3_RXD_FE_B 8 126 #define HNS3_RXD_LUM_B 9 127 #define HNS3_RXD_CRCP_B 10 128 #define HNS3_RXD_L3L4P_B 11 129 #define HNS3_RXD_TSIDX_S 12 130 #define HNS3_RXD_TSIDX_M (0x3 << HNS3_RXD_TSIDX_S) 131 #define HNS3_RXD_TS_VLD_B 14 132 #define HNS3_RXD_LKBK_B 15 133 #define HNS3_RXD_GRO_SIZE_S 16 134 #define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S) 135 136 #define HNS3_TXD_L3T_S 0 137 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S) 138 #define HNS3_TXD_L4T_S 2 139 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S) 140 #define HNS3_TXD_L3CS_B 4 141 #define HNS3_TXD_L4CS_B 5 142 #define HNS3_TXD_VLAN_B 6 143 #define HNS3_TXD_TSO_B 7 144 145 #define HNS3_TXD_L2LEN_S 8 146 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S) 147 #define HNS3_TXD_L3LEN_S 16 148 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S) 149 #define HNS3_TXD_L4LEN_S 24 150 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S) 151 152 #define HNS3_TXD_CSUM_START_S 8 153 #define HNS3_TXD_CSUM_START_M (0xffff << HNS3_TXD_CSUM_START_S) 154 155 #define HNS3_TXD_OL3T_S 0 156 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S) 157 #define HNS3_TXD_OVLAN_B 2 158 #define HNS3_TXD_MACSEC_B 3 159 #define HNS3_TXD_TUNTYPE_S 4 160 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S) 161 162 #define HNS3_TXD_CSUM_OFFSET_S 8 163 #define HNS3_TXD_CSUM_OFFSET_M (0xffff << HNS3_TXD_CSUM_OFFSET_S) 164 165 #define HNS3_TXD_BDTYPE_S 0 166 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S) 167 #define HNS3_TXD_FE_B 4 168 #define HNS3_TXD_SC_S 5 169 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S) 170 #define HNS3_TXD_EXTEND_B 7 171 #define HNS3_TXD_VLD_B 8 172 #define HNS3_TXD_RI_B 9 173 #define HNS3_TXD_RA_B 10 174 #define HNS3_TXD_TSYN_B 11 175 #define HNS3_TXD_DECTTL_S 12 176 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S) 177 178 #define HNS3_TXD_OL4CS_B 22 179 180 #define HNS3_TXD_MSS_S 0 181 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) 182 #define HNS3_TXD_HW_CS_B 14 183 184 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0) 185 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1) 186 187 #define HNS3_VECTOR_NOT_INITED 0 188 #define HNS3_VECTOR_INITED 1 189 190 #define HNS3_MAX_BD_SIZE 65535 191 #define HNS3_MAX_TSO_BD_NUM 63U 192 #define HNS3_MAX_TSO_SIZE 1048576U 193 #define HNS3_MAX_NON_TSO_SIZE 9728U 194 195 #define HNS3_VECTOR_GL_MASK GENMASK(11, 0) 196 #define HNS3_VECTOR_GL0_OFFSET 0x100 197 #define HNS3_VECTOR_GL1_OFFSET 0x200 198 #define HNS3_VECTOR_GL2_OFFSET 0x300 199 #define HNS3_VECTOR_RL_OFFSET 0x900 200 #define HNS3_VECTOR_RL_EN_B 6 201 #define HNS3_VECTOR_QL_MASK GENMASK(9, 0) 202 #define HNS3_VECTOR_TX_QL_OFFSET 0xe00 203 #define HNS3_VECTOR_RX_QL_OFFSET 0xf00 204 205 #define HNS3_RING_EN_B 0 206 207 #define HNS3_GL0_CQ_MODE_REG 0x20d00 208 #define HNS3_GL1_CQ_MODE_REG 0x20d04 209 #define HNS3_GL2_CQ_MODE_REG 0x20d08 210 #define HNS3_CQ_MODE_EQE 1U 211 #define HNS3_CQ_MODE_CQE 0U 212 213 enum hns3_pkt_l2t_type { 214 HNS3_L2_TYPE_UNICAST, 215 HNS3_L2_TYPE_MULTICAST, 216 HNS3_L2_TYPE_BROADCAST, 217 HNS3_L2_TYPE_INVALID, 218 }; 219 220 enum hns3_pkt_l3t_type { 221 HNS3_L3T_NONE, 222 HNS3_L3T_IPV6, 223 HNS3_L3T_IPV4, 224 HNS3_L3T_RESERVED 225 }; 226 227 enum hns3_pkt_l4t_type { 228 HNS3_L4T_UNKNOWN, 229 HNS3_L4T_TCP, 230 HNS3_L4T_UDP, 231 HNS3_L4T_SCTP 232 }; 233 234 enum hns3_pkt_ol3t_type { 235 HNS3_OL3T_NONE, 236 HNS3_OL3T_IPV6, 237 HNS3_OL3T_IPV4_NO_CSUM, 238 HNS3_OL3T_IPV4_CSUM 239 }; 240 241 enum hns3_pkt_tun_type { 242 HNS3_TUN_NONE, 243 HNS3_TUN_MAC_IN_UDP, 244 HNS3_TUN_NVGRE, 245 HNS3_TUN_OTHER 246 }; 247 248 /* hardware spec ring buffer format */ 249 struct __packed hns3_desc { 250 union { 251 __le64 addr; 252 __le16 csum; 253 struct { 254 __le32 ts_nsec; 255 __le32 ts_sec; 256 }; 257 }; 258 union { 259 struct { 260 __le16 vlan_tag; 261 __le16 send_size; 262 union { 263 __le32 type_cs_vlan_tso_len; 264 struct { 265 __u8 type_cs_vlan_tso; 266 __u8 l2_len; 267 __u8 l3_len; 268 __u8 l4_len; 269 }; 270 }; 271 __le16 outer_vlan_tag; 272 __le16 tv; 273 274 union { 275 __le32 ol_type_vlan_len_msec; 276 struct { 277 __u8 ol_type_vlan_msec; 278 __u8 ol2_len; 279 __u8 ol3_len; 280 __u8 ol4_len; 281 }; 282 }; 283 284 __le32 paylen_ol4cs; 285 __le16 bdtp_fe_sc_vld_ra_ri; 286 __le16 mss_hw_csum; 287 } tx; 288 289 struct { 290 __le32 l234_info; 291 __le16 pkt_len; 292 __le16 size; 293 294 __le32 rss_hash; 295 __le16 fd_id; 296 __le16 vlan_tag; 297 298 union { 299 __le32 ol_info; 300 struct { 301 __le16 o_dm_vlan_id_fb; 302 __le16 ot_vlan_tag; 303 }; 304 }; 305 306 __le32 bd_base_info; 307 } rx; 308 }; 309 }; 310 311 enum hns3_desc_type { 312 DESC_TYPE_UNKNOWN = 0, 313 DESC_TYPE_SKB = 1 << 0, 314 DESC_TYPE_FRAGLIST_SKB = 1 << 1, 315 DESC_TYPE_PAGE = 1 << 2, 316 DESC_TYPE_BOUNCE_ALL = 1 << 3, 317 DESC_TYPE_BOUNCE_HEAD = 1 << 4, 318 DESC_TYPE_SGL_SKB = 1 << 5, 319 DESC_TYPE_PP_FRAG = 1 << 6, 320 }; 321 322 struct hns3_desc_cb { 323 dma_addr_t dma; /* dma address of this desc */ 324 void *buf; /* cpu addr for a desc */ 325 326 /* priv data for the desc, e.g. skb when use with ip stack */ 327 void *priv; 328 329 union { 330 u32 page_offset; /* for rx */ 331 u32 send_bytes; /* for tx */ 332 }; 333 334 u32 length; /* length of the buffer */ 335 336 u16 reuse_flag; 337 u16 refill; 338 339 /* desc type, used by the ring user to mark the type of the priv data */ 340 u16 type; 341 u16 pagecnt_bias; 342 }; 343 344 enum hns3_pkt_l3type { 345 HNS3_L3_TYPE_IPV4, 346 HNS3_L3_TYPE_IPV6, 347 HNS3_L3_TYPE_ARP, 348 HNS3_L3_TYPE_RARP, 349 HNS3_L3_TYPE_IPV4_OPT, 350 HNS3_L3_TYPE_IPV6_EXT, 351 HNS3_L3_TYPE_LLDP, 352 HNS3_L3_TYPE_BPDU, 353 HNS3_L3_TYPE_MAC_PAUSE, 354 HNS3_L3_TYPE_PFC_PAUSE, /* 0x9 */ 355 356 /* reserved for 0xA~0xB */ 357 358 HNS3_L3_TYPE_CNM = 0xc, 359 360 /* reserved for 0xD~0xE */ 361 362 HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */ 363 }; 364 365 enum hns3_pkt_l4type { 366 HNS3_L4_TYPE_UDP, 367 HNS3_L4_TYPE_TCP, 368 HNS3_L4_TYPE_GRE, 369 HNS3_L4_TYPE_SCTP, 370 HNS3_L4_TYPE_IGMP, 371 HNS3_L4_TYPE_ICMP, 372 373 /* reserved for 0x6~0xE */ 374 375 HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */ 376 }; 377 378 enum hns3_pkt_ol3type { 379 HNS3_OL3_TYPE_IPV4 = 0, 380 HNS3_OL3_TYPE_IPV6, 381 /* reserved for 0x2~0x3 */ 382 HNS3_OL3_TYPE_IPV4_OPT = 4, 383 HNS3_OL3_TYPE_IPV6_EXT, 384 385 /* reserved for 0x6~0xE */ 386 387 HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */ 388 }; 389 390 enum hns3_pkt_ol4type { 391 HNS3_OL4_TYPE_NO_TUN, 392 HNS3_OL4_TYPE_MAC_IN_UDP, 393 HNS3_OL4_TYPE_NVGRE, 394 HNS3_OL4_TYPE_UNKNOWN 395 }; 396 397 struct hns3_rx_ptype { 398 u32 ptype : 8; 399 u32 csum_level : 2; 400 u32 ip_summed : 2; 401 u32 l3_type : 4; 402 u32 valid : 1; 403 }; 404 405 struct ring_stats { 406 u64 sw_err_cnt; 407 u64 seg_pkt_cnt; 408 union { 409 struct { 410 u64 tx_pkts; 411 u64 tx_bytes; 412 u64 tx_more; 413 u64 restart_queue; 414 u64 tx_busy; 415 u64 tx_copy; 416 u64 tx_vlan_err; 417 u64 tx_l4_proto_err; 418 u64 tx_l2l3l4_err; 419 u64 tx_tso_err; 420 u64 over_max_recursion; 421 u64 hw_limitation; 422 u64 tx_bounce; 423 u64 tx_spare_full; 424 u64 copy_bits_err; 425 u64 tx_sgl; 426 u64 skb2sgl_err; 427 u64 map_sg_err; 428 }; 429 struct { 430 u64 rx_pkts; 431 u64 rx_bytes; 432 u64 rx_err_cnt; 433 u64 reuse_pg_cnt; 434 u64 err_pkt_len; 435 u64 err_bd_num; 436 u64 l2_err; 437 u64 l3l4_csum_err; 438 u64 csum_complete; 439 u64 rx_multicast; 440 u64 non_reuse_pg; 441 u64 frag_alloc_err; 442 u64 frag_alloc; 443 }; 444 __le16 csum; 445 }; 446 }; 447 448 struct hns3_tx_spare { 449 dma_addr_t dma; 450 void *buf; 451 u32 next_to_use; 452 u32 next_to_clean; 453 u32 last_to_clean; 454 u32 len; 455 }; 456 457 struct hns3_enet_ring { 458 struct hns3_desc *desc; /* dma map address space */ 459 struct hns3_desc_cb *desc_cb; 460 struct hns3_enet_ring *next; 461 struct hns3_enet_tqp_vector *tqp_vector; 462 struct hnae3_queue *tqp; 463 int queue_index; 464 struct device *dev; /* will be used for DMA mapping of descriptors */ 465 struct page_pool *page_pool; 466 467 /* statistic */ 468 struct ring_stats stats; 469 struct u64_stats_sync syncp; 470 471 dma_addr_t desc_dma_addr; 472 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 473 u16 desc_num; /* total number of desc */ 474 int next_to_use; /* idx of next spare desc */ 475 476 /* idx of lastest sent desc, the ring is empty when equal to 477 * next_to_use 478 */ 479 int next_to_clean; 480 u32 flag; /* ring attribute */ 481 482 int pending_buf; 483 union { 484 /* for Tx ring */ 485 struct { 486 u32 fd_qb_tx_sample; 487 int last_to_use; /* last idx used by xmit */ 488 u32 tx_copybreak; 489 struct hns3_tx_spare *tx_spare; 490 }; 491 492 /* for Rx ring */ 493 struct { 494 u32 pull_len; /* memcpy len for current rx packet */ 495 u32 rx_copybreak; 496 u32 frag_num; 497 /* first buffer address for current packet */ 498 unsigned char *va; 499 struct sk_buff *skb; 500 struct sk_buff *tail_skb; 501 }; 502 }; 503 } ____cacheline_internodealigned_in_smp; 504 505 enum hns3_flow_level_range { 506 HNS3_FLOW_LOW = 0, 507 HNS3_FLOW_MID = 1, 508 HNS3_FLOW_HIGH = 2, 509 HNS3_FLOW_ULTRA = 3, 510 }; 511 512 #define HNS3_INT_GL_50K 0x0014 513 #define HNS3_INT_GL_20K 0x0032 514 #define HNS3_INT_GL_18K 0x0036 515 #define HNS3_INT_GL_8K 0x007C 516 517 #define HNS3_INT_GL_1US BIT(31) 518 519 #define HNS3_INT_RL_MAX 0x00EC 520 #define HNS3_INT_RL_ENABLE_MASK 0x40 521 522 #define HNS3_INT_QL_DEFAULT_CFG 0x20 523 524 struct hns3_enet_coalesce { 525 u16 int_gl; 526 u16 int_ql; 527 u16 int_ql_max; 528 u8 adapt_enable : 1; 529 u8 ql_enable : 1; 530 u8 unit_1us : 1; 531 enum hns3_flow_level_range flow_level; 532 }; 533 534 struct hns3_enet_ring_group { 535 /* array of pointers to rings */ 536 struct hns3_enet_ring *ring; 537 u64 total_bytes; /* total bytes processed this group */ 538 u64 total_packets; /* total packets processed this group */ 539 u16 count; 540 struct hns3_enet_coalesce coal; 541 struct dim dim; 542 }; 543 544 struct hns3_enet_tqp_vector { 545 struct hnae3_handle *handle; 546 u8 __iomem *mask_addr; 547 int vector_irq; 548 int irq_init_flag; 549 550 u16 idx; /* index in the TQP vector array per handle. */ 551 552 struct napi_struct napi; 553 554 struct hns3_enet_ring_group rx_group; 555 struct hns3_enet_ring_group tx_group; 556 557 cpumask_t affinity_mask; 558 u16 num_tqps; /* total number of tqps in TQP vector */ 559 struct irq_affinity_notify affinity_notify; 560 561 char name[HNAE3_INT_NAME_LEN]; 562 563 u64 event_cnt; 564 } ____cacheline_internodealigned_in_smp; 565 566 struct hns3_nic_priv { 567 struct hnae3_handle *ae_handle; 568 struct net_device *netdev; 569 struct device *dev; 570 571 /** 572 * the cb for nic to manage the ring buffer, the first half of the 573 * array is for tx_ring and vice versa for the second half 574 */ 575 struct hns3_enet_ring *ring; 576 struct hns3_enet_tqp_vector *tqp_vector; 577 u16 vector_num; 578 u8 max_non_tso_bd_num; 579 580 u64 tx_timeout_count; 581 582 unsigned long state; 583 584 enum dim_cq_period_mode tx_cqe_mode; 585 enum dim_cq_period_mode rx_cqe_mode; 586 struct hns3_enet_coalesce tx_coal; 587 struct hns3_enet_coalesce rx_coal; 588 u32 tx_copybreak; 589 u32 rx_copybreak; 590 }; 591 592 union l3_hdr_info { 593 struct iphdr *v4; 594 struct ipv6hdr *v6; 595 unsigned char *hdr; 596 }; 597 598 union l4_hdr_info { 599 struct tcphdr *tcp; 600 struct udphdr *udp; 601 struct gre_base_hdr *gre; 602 unsigned char *hdr; 603 }; 604 605 struct hns3_hw_error_info { 606 enum hnae3_hw_error_type type; 607 const char *msg; 608 }; 609 610 struct hns3_reset_type_map { 611 enum ethtool_reset_flags rst_flags; 612 enum hnae3_reset_type rst_type; 613 }; 614 615 static inline int ring_space(struct hns3_enet_ring *ring) 616 { 617 /* This smp_load_acquire() pairs with smp_store_release() in 618 * hns3_nic_reclaim_one_desc called by hns3_clean_tx_ring. 619 */ 620 int begin = smp_load_acquire(&ring->next_to_clean); 621 int end = READ_ONCE(ring->next_to_use); 622 623 return ((end >= begin) ? (ring->desc_num - end + begin) : 624 (begin - end)) - 1; 625 } 626 627 static inline u32 hns3_tqp_read_reg(struct hns3_enet_ring *ring, u32 reg) 628 { 629 return readl_relaxed(ring->tqp->io_base + reg); 630 } 631 632 static inline u32 hns3_read_reg(void __iomem *base, u32 reg) 633 { 634 return readl(base + reg); 635 } 636 637 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value) 638 { 639 u8 __iomem *reg_addr = READ_ONCE(base); 640 641 writel(value, reg_addr + reg); 642 } 643 644 #define hns3_read_dev(a, reg) \ 645 hns3_read_reg((a)->io_base, reg) 646 647 static inline bool hns3_nic_resetting(struct net_device *netdev) 648 { 649 struct hns3_nic_priv *priv = netdev_priv(netdev); 650 651 return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 652 } 653 654 #define hns3_write_dev(a, reg, value) \ 655 hns3_write_reg((a)->io_base, reg, value) 656 657 #define ring_to_dev(ring) ((ring)->dev) 658 659 #define ring_to_netdev(ring) ((ring)->tqp_vector->napi.dev) 660 661 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \ 662 DMA_TO_DEVICE : DMA_FROM_DEVICE) 663 664 #define hns3_buf_size(_ring) ((_ring)->buf_size) 665 666 #define hns3_ring_stats_update(ring, cnt) do { \ 667 typeof(ring) (tmp) = (ring); \ 668 u64_stats_update_begin(&(tmp)->syncp); \ 669 ((tmp)->stats.cnt)++; \ 670 u64_stats_update_end(&(tmp)->syncp); \ 671 } while (0) \ 672 673 static inline unsigned int hns3_page_order(struct hns3_enet_ring *ring) 674 { 675 #if (PAGE_SIZE < 8192) 676 if (ring->buf_size > (PAGE_SIZE / 2)) 677 return 1; 678 #endif 679 return 0; 680 } 681 682 #define hns3_page_size(_ring) (PAGE_SIZE << hns3_page_order(_ring)) 683 684 /* iterator for handling rings in ring group */ 685 #define hns3_for_each_ring(pos, head) \ 686 for (pos = (head).ring; (pos); pos = (pos)->next) 687 688 #define hns3_get_handle(ndev) \ 689 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle) 690 691 #define hns3_gl_usec_to_reg(int_gl) ((int_gl) >> 1) 692 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2) 693 694 #define hns3_rl_usec_to_reg(int_rl) ((int_rl) >> 2) 695 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4) 696 697 void hns3_ethtool_set_ops(struct net_device *netdev); 698 int hns3_set_channels(struct net_device *netdev, 699 struct ethtool_channels *ch); 700 701 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget); 702 int hns3_init_all_ring(struct hns3_nic_priv *priv); 703 int hns3_nic_reset_all_ring(struct hnae3_handle *h); 704 void hns3_fini_ring(struct hns3_enet_ring *ring); 705 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev); 706 bool hns3_is_phys_func(struct pci_dev *pdev); 707 int hns3_clean_rx_ring( 708 struct hns3_enet_ring *ring, int budget, 709 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)); 710 711 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 712 u32 gl_value); 713 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 714 u32 gl_value); 715 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 716 u32 rl_value); 717 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector, 718 u32 ql_value); 719 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector, 720 u32 ql_value); 721 722 void hns3_request_update_promisc_mode(struct hnae3_handle *handle); 723 int hns3_reset_notify(struct hnae3_handle *handle, 724 enum hnae3_reset_notify_type type); 725 726 #ifdef CONFIG_HNS3_DCB 727 void hns3_dcbnl_setup(struct hnae3_handle *handle); 728 #else 729 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {} 730 #endif 731 732 int hns3_dbg_init(struct hnae3_handle *handle); 733 void hns3_dbg_uninit(struct hnae3_handle *handle); 734 void hns3_dbg_register_debugfs(const char *debugfs_dir_name); 735 void hns3_dbg_unregister_debugfs(void); 736 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size); 737 u16 hns3_get_max_available_channels(struct hnae3_handle *h); 738 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv, 739 enum dim_cq_period_mode tx_mode, 740 enum dim_cq_period_mode rx_mode); 741 #endif 742