1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HNS3_ENET_H 5 #define __HNS3_ENET_H 6 7 #include <linux/if_vlan.h> 8 9 #include "hnae3.h" 10 11 #define HNS3_MOD_VERSION "1.0" 12 13 extern const char hns3_driver_version[]; 14 15 enum hns3_nic_state { 16 HNS3_NIC_STATE_TESTING, 17 HNS3_NIC_STATE_RESETTING, 18 HNS3_NIC_STATE_INITED, 19 HNS3_NIC_STATE_DOWN, 20 HNS3_NIC_STATE_DISABLED, 21 HNS3_NIC_STATE_REMOVING, 22 HNS3_NIC_STATE_SERVICE_INITED, 23 HNS3_NIC_STATE_SERVICE_SCHED, 24 HNS3_NIC_STATE2_RESET_REQUESTED, 25 HNS3_NIC_STATE_MAX 26 }; 27 28 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000 29 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004 30 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008 31 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C 32 #define HNS3_RING_RX_RING_TAIL_REG 0x00018 33 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C 34 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020 35 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C 36 37 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040 38 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044 39 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048 40 #define HNS3_RING_TX_RING_TC_REG 0x00050 41 #define HNS3_RING_TX_RING_TAIL_REG 0x00058 42 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C 43 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060 44 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064 45 #define HNS3_RING_TX_RING_EBDNUM_REG 0x00068 46 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C 47 #define HNS3_RING_TX_RING_EBD_OFFSET_REG 0x00070 48 #define HNS3_RING_TX_RING_BD_ERR_REG 0x00074 49 #define HNS3_RING_PREFETCH_EN_REG 0x0007C 50 #define HNS3_RING_CFG_VF_NUM_REG 0x00080 51 #define HNS3_RING_ASID_REG 0x0008C 52 #define HNS3_RING_EN_REG 0x00090 53 #define HNS3_RING_T0_BE_RST 0x00094 54 #define HNS3_RING_COULD_BE_RST 0x00098 55 #define HNS3_RING_WRR_WEIGHT_REG 0x0009c 56 57 #define HNS3_RING_INTMSK_RXWL_REG 0x000A0 58 #define HNS3_RING_INTSTS_RX_RING_REG 0x000A4 59 #define HNS3_RX_RING_INT_STS_REG 0x000A8 60 #define HNS3_RING_INTMSK_TXWL_REG 0x000AC 61 #define HNS3_RING_INTSTS_TX_RING_REG 0x000B0 62 #define HNS3_TX_RING_INT_STS_REG 0x000B4 63 #define HNS3_RING_INTMSK_RX_OVERTIME_REG 0x000B8 64 #define HNS3_RING_INTSTS_RX_OVERTIME_REG 0x000BC 65 #define HNS3_RING_INTMSK_TX_OVERTIME_REG 0x000C4 66 #define HNS3_RING_INTSTS_TX_OVERTIME_REG 0x000C8 67 68 #define HNS3_RING_MB_CTRL_REG 0x00100 69 #define HNS3_RING_MB_DATA_BASE_REG 0x00200 70 71 #define HNS3_TX_REG_OFFSET 0x40 72 73 #define HNS3_RX_HEAD_SIZE 256 74 75 #define HNS3_TX_TIMEOUT (5 * HZ) 76 #define HNS3_RING_NAME_LEN 16 77 #define HNS3_BUFFER_SIZE_2048 2048 78 #define HNS3_RING_MAX_PENDING 32768 79 #define HNS3_RING_MIN_PENDING 24 80 #define HNS3_RING_BD_MULTIPLE 8 81 /* max frame size of mac */ 82 #define HNS3_MAC_MAX_FRAME 9728 83 #define HNS3_MAX_MTU \ 84 (HNS3_MAC_MAX_FRAME - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN)) 85 86 #define HNS3_BD_SIZE_512_TYPE 0 87 #define HNS3_BD_SIZE_1024_TYPE 1 88 #define HNS3_BD_SIZE_2048_TYPE 2 89 #define HNS3_BD_SIZE_4096_TYPE 3 90 91 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1 92 #define HNS3_RX_FLAG_L3ID_IPV4 0x0 93 #define HNS3_RX_FLAG_L3ID_IPV6 0x1 94 #define HNS3_RX_FLAG_L4ID_UDP 0x0 95 #define HNS3_RX_FLAG_L4ID_TCP 0x1 96 97 #define HNS3_RXD_DMAC_S 0 98 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S) 99 #define HNS3_RXD_VLAN_S 2 100 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S) 101 #define HNS3_RXD_L3ID_S 4 102 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S) 103 #define HNS3_RXD_L4ID_S 8 104 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S) 105 #define HNS3_RXD_FRAG_B 12 106 #define HNS3_RXD_STRP_TAGP_S 13 107 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S) 108 109 #define HNS3_RXD_L2E_B 16 110 #define HNS3_RXD_L3E_B 17 111 #define HNS3_RXD_L4E_B 18 112 #define HNS3_RXD_TRUNCAT_B 19 113 #define HNS3_RXD_HOI_B 20 114 #define HNS3_RXD_DOI_B 21 115 #define HNS3_RXD_OL3E_B 22 116 #define HNS3_RXD_OL4E_B 23 117 #define HNS3_RXD_GRO_COUNT_S 24 118 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S) 119 #define HNS3_RXD_GRO_FIXID_B 30 120 #define HNS3_RXD_GRO_ECN_B 31 121 122 #define HNS3_RXD_ODMAC_S 0 123 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S) 124 #define HNS3_RXD_OVLAN_S 2 125 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S) 126 #define HNS3_RXD_OL3ID_S 4 127 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S) 128 #define HNS3_RXD_OL4ID_S 8 129 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S) 130 #define HNS3_RXD_FBHI_S 12 131 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S) 132 #define HNS3_RXD_FBLI_S 14 133 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S) 134 135 #define HNS3_RXD_BDTYPE_S 0 136 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S) 137 #define HNS3_RXD_VLD_B 4 138 #define HNS3_RXD_UDP0_B 5 139 #define HNS3_RXD_EXTEND_B 7 140 #define HNS3_RXD_FE_B 8 141 #define HNS3_RXD_LUM_B 9 142 #define HNS3_RXD_CRCP_B 10 143 #define HNS3_RXD_L3L4P_B 11 144 #define HNS3_RXD_TSIND_S 12 145 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S) 146 #define HNS3_RXD_LKBK_B 15 147 #define HNS3_RXD_GRO_SIZE_S 16 148 #define HNS3_RXD_GRO_SIZE_M (0x3ff << HNS3_RXD_GRO_SIZE_S) 149 150 #define HNS3_TXD_L3T_S 0 151 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S) 152 #define HNS3_TXD_L4T_S 2 153 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S) 154 #define HNS3_TXD_L3CS_B 4 155 #define HNS3_TXD_L4CS_B 5 156 #define HNS3_TXD_VLAN_B 6 157 #define HNS3_TXD_TSO_B 7 158 159 #define HNS3_TXD_L2LEN_S 8 160 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S) 161 #define HNS3_TXD_L3LEN_S 16 162 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S) 163 #define HNS3_TXD_L4LEN_S 24 164 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S) 165 166 #define HNS3_TXD_OL3T_S 0 167 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S) 168 #define HNS3_TXD_OVLAN_B 2 169 #define HNS3_TXD_MACSEC_B 3 170 #define HNS3_TXD_TUNTYPE_S 4 171 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S) 172 173 #define HNS3_TXD_BDTYPE_S 0 174 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S) 175 #define HNS3_TXD_FE_B 4 176 #define HNS3_TXD_SC_S 5 177 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S) 178 #define HNS3_TXD_EXTEND_B 7 179 #define HNS3_TXD_VLD_B 8 180 #define HNS3_TXD_RI_B 9 181 #define HNS3_TXD_RA_B 10 182 #define HNS3_TXD_TSYN_B 11 183 #define HNS3_TXD_DECTTL_S 12 184 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S) 185 186 #define HNS3_TXD_MSS_S 0 187 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) 188 189 #define HNS3_TX_LAST_SIZE_M 0xffff 190 191 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0) 192 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1) 193 194 #define HNS3_VECTOR_NOT_INITED 0 195 #define HNS3_VECTOR_INITED 1 196 197 #define HNS3_MAX_BD_SIZE 65535 198 #define HNS3_MAX_BD_PER_FRAG 8 199 #define HNS3_MAX_BD_PER_PKT MAX_SKB_FRAGS 200 201 #define HNS3_VECTOR_GL0_OFFSET 0x100 202 #define HNS3_VECTOR_GL1_OFFSET 0x200 203 #define HNS3_VECTOR_GL2_OFFSET 0x300 204 #define HNS3_VECTOR_RL_OFFSET 0x900 205 #define HNS3_VECTOR_RL_EN_B 6 206 207 #define HNS3_RING_EN_B 0 208 209 enum hns3_pkt_l2t_type { 210 HNS3_L2_TYPE_UNICAST, 211 HNS3_L2_TYPE_MULTICAST, 212 HNS3_L2_TYPE_BROADCAST, 213 HNS3_L2_TYPE_INVALID, 214 }; 215 216 enum hns3_pkt_l3t_type { 217 HNS3_L3T_NONE, 218 HNS3_L3T_IPV6, 219 HNS3_L3T_IPV4, 220 HNS3_L3T_RESERVED 221 }; 222 223 enum hns3_pkt_l4t_type { 224 HNS3_L4T_UNKNOWN, 225 HNS3_L4T_TCP, 226 HNS3_L4T_UDP, 227 HNS3_L4T_SCTP 228 }; 229 230 enum hns3_pkt_ol3t_type { 231 HNS3_OL3T_NONE, 232 HNS3_OL3T_IPV6, 233 HNS3_OL3T_IPV4_NO_CSUM, 234 HNS3_OL3T_IPV4_CSUM 235 }; 236 237 enum hns3_pkt_tun_type { 238 HNS3_TUN_NONE, 239 HNS3_TUN_MAC_IN_UDP, 240 HNS3_TUN_NVGRE, 241 HNS3_TUN_OTHER 242 }; 243 244 /* hardware spec ring buffer format */ 245 struct __packed hns3_desc { 246 __le64 addr; 247 union { 248 struct { 249 __le16 vlan_tag; 250 __le16 send_size; 251 union { 252 __le32 type_cs_vlan_tso_len; 253 struct { 254 __u8 type_cs_vlan_tso; 255 __u8 l2_len; 256 __u8 l3_len; 257 __u8 l4_len; 258 }; 259 }; 260 __le16 outer_vlan_tag; 261 __le16 tv; 262 263 union { 264 __le32 ol_type_vlan_len_msec; 265 struct { 266 __u8 ol_type_vlan_msec; 267 __u8 ol2_len; 268 __u8 ol3_len; 269 __u8 ol4_len; 270 }; 271 }; 272 273 __le32 paylen; 274 __le16 bdtp_fe_sc_vld_ra_ri; 275 __le16 mss; 276 } tx; 277 278 struct { 279 __le32 l234_info; 280 __le16 pkt_len; 281 __le16 size; 282 283 __le32 rss_hash; 284 __le16 fd_id; 285 __le16 vlan_tag; 286 287 union { 288 __le32 ol_info; 289 struct { 290 __le16 o_dm_vlan_id_fb; 291 __le16 ot_vlan_tag; 292 }; 293 }; 294 295 __le32 bd_base_info; 296 } rx; 297 }; 298 }; 299 300 struct hns3_desc_cb { 301 dma_addr_t dma; /* dma address of this desc */ 302 void *buf; /* cpu addr for a desc */ 303 304 /* priv data for the desc, e.g. skb when use with ip stack*/ 305 void *priv; 306 u32 page_offset; 307 u32 length; /* length of the buffer */ 308 309 u16 reuse_flag; 310 311 /* desc type, used by the ring user to mark the type of the priv data */ 312 u16 type; 313 }; 314 315 enum hns3_pkt_l3type { 316 HNS3_L3_TYPE_IPV4, 317 HNS3_L3_TYPE_IPV6, 318 HNS3_L3_TYPE_ARP, 319 HNS3_L3_TYPE_RARP, 320 HNS3_L3_TYPE_IPV4_OPT, 321 HNS3_L3_TYPE_IPV6_EXT, 322 HNS3_L3_TYPE_LLDP, 323 HNS3_L3_TYPE_BPDU, 324 HNS3_L3_TYPE_MAC_PAUSE, 325 HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/ 326 327 /* reserved for 0xA~0xB*/ 328 329 HNS3_L3_TYPE_CNM = 0xc, 330 331 /* reserved for 0xD~0xE*/ 332 333 HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */ 334 }; 335 336 enum hns3_pkt_l4type { 337 HNS3_L4_TYPE_UDP, 338 HNS3_L4_TYPE_TCP, 339 HNS3_L4_TYPE_GRE, 340 HNS3_L4_TYPE_SCTP, 341 HNS3_L4_TYPE_IGMP, 342 HNS3_L4_TYPE_ICMP, 343 344 /* reserved for 0x6~0xE */ 345 346 HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */ 347 }; 348 349 enum hns3_pkt_ol3type { 350 HNS3_OL3_TYPE_IPV4 = 0, 351 HNS3_OL3_TYPE_IPV6, 352 /* reserved for 0x2~0x3 */ 353 HNS3_OL3_TYPE_IPV4_OPT = 4, 354 HNS3_OL3_TYPE_IPV6_EXT, 355 356 /* reserved for 0x6~0xE*/ 357 358 HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */ 359 }; 360 361 enum hns3_pkt_ol4type { 362 HNS3_OL4_TYPE_NO_TUN, 363 HNS3_OL4_TYPE_MAC_IN_UDP, 364 HNS3_OL4_TYPE_NVGRE, 365 HNS3_OL4_TYPE_UNKNOWN 366 }; 367 368 struct ring_stats { 369 u64 io_err_cnt; 370 u64 sw_err_cnt; 371 u64 seg_pkt_cnt; 372 union { 373 struct { 374 u64 tx_pkts; 375 u64 tx_bytes; 376 u64 tx_err_cnt; 377 u64 restart_queue; 378 u64 tx_busy; 379 }; 380 struct { 381 u64 rx_pkts; 382 u64 rx_bytes; 383 u64 rx_err_cnt; 384 u64 reuse_pg_cnt; 385 u64 err_pkt_len; 386 u64 non_vld_descs; 387 u64 err_bd_num; 388 u64 l2_err; 389 u64 l3l4_csum_err; 390 u64 rx_multicast; 391 }; 392 }; 393 }; 394 395 struct hns3_enet_ring { 396 u8 __iomem *io_base; /* base io address for the ring */ 397 struct hns3_desc *desc; /* dma map address space */ 398 struct hns3_desc_cb *desc_cb; 399 struct hns3_enet_ring *next; 400 struct hns3_enet_tqp_vector *tqp_vector; 401 struct hnae3_queue *tqp; 402 char ring_name[HNS3_RING_NAME_LEN]; 403 struct device *dev; /* will be used for DMA mapping of descriptors */ 404 405 /* statistic */ 406 struct ring_stats stats; 407 struct u64_stats_sync syncp; 408 409 dma_addr_t desc_dma_addr; 410 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 411 u16 desc_num; /* total number of desc */ 412 u16 max_desc_num_per_pkt; 413 u16 max_raw_data_sz_per_desc; 414 u16 max_pkt_size; 415 int next_to_use; /* idx of next spare desc */ 416 417 /* idx of lastest sent desc, the ring is empty when equal to 418 * next_to_use 419 */ 420 int next_to_clean; 421 422 int pull_len; /* head length for current packet */ 423 u32 frag_num; 424 unsigned char *va; /* first buffer address for current packet */ 425 426 u32 flag; /* ring attribute */ 427 428 int numa_node; 429 cpumask_t affinity_mask; 430 431 int pending_buf; 432 struct sk_buff *skb; 433 struct sk_buff *tail_skb; 434 }; 435 436 struct hns_queue; 437 438 struct hns3_nic_ring_data { 439 struct hns3_enet_ring *ring; 440 struct napi_struct napi; 441 int queue_index; 442 int (*poll_one)(struct hns3_nic_ring_data *, int, void *); 443 void (*ex_process)(struct hns3_nic_ring_data *, struct sk_buff *); 444 void (*fini_process)(struct hns3_nic_ring_data *); 445 }; 446 447 struct hns3_nic_ops { 448 int (*maybe_stop_tx)(struct sk_buff **out_skb, 449 int *bnum, struct hns3_enet_ring *ring); 450 }; 451 452 enum hns3_flow_level_range { 453 HNS3_FLOW_LOW = 0, 454 HNS3_FLOW_MID = 1, 455 HNS3_FLOW_HIGH = 2, 456 HNS3_FLOW_ULTRA = 3, 457 }; 458 459 enum hns3_link_mode_bits { 460 HNS3_LM_FIBRE_BIT = BIT(0), 461 HNS3_LM_AUTONEG_BIT = BIT(1), 462 HNS3_LM_TP_BIT = BIT(2), 463 HNS3_LM_PAUSE_BIT = BIT(3), 464 HNS3_LM_BACKPLANE_BIT = BIT(4), 465 HNS3_LM_10BASET_HALF_BIT = BIT(5), 466 HNS3_LM_10BASET_FULL_BIT = BIT(6), 467 HNS3_LM_100BASET_HALF_BIT = BIT(7), 468 HNS3_LM_100BASET_FULL_BIT = BIT(8), 469 HNS3_LM_1000BASET_FULL_BIT = BIT(9), 470 HNS3_LM_10000BASEKR_FULL_BIT = BIT(10), 471 HNS3_LM_25000BASEKR_FULL_BIT = BIT(11), 472 HNS3_LM_40000BASELR4_FULL_BIT = BIT(12), 473 HNS3_LM_50000BASEKR2_FULL_BIT = BIT(13), 474 HNS3_LM_100000BASEKR4_FULL_BIT = BIT(14), 475 HNS3_LM_COUNT = 15 476 }; 477 478 #define HNS3_INT_GL_MAX 0x1FE0 479 #define HNS3_INT_GL_50K 0x0014 480 #define HNS3_INT_GL_20K 0x0032 481 #define HNS3_INT_GL_18K 0x0036 482 #define HNS3_INT_GL_8K 0x007C 483 484 #define HNS3_INT_RL_MAX 0x00EC 485 #define HNS3_INT_RL_ENABLE_MASK 0x40 486 487 struct hns3_enet_coalesce { 488 u16 int_gl; 489 u8 gl_adapt_enable; 490 enum hns3_flow_level_range flow_level; 491 }; 492 493 struct hns3_enet_ring_group { 494 /* array of pointers to rings */ 495 struct hns3_enet_ring *ring; 496 u64 total_bytes; /* total bytes processed this group */ 497 u64 total_packets; /* total packets processed this group */ 498 u16 count; 499 struct hns3_enet_coalesce coal; 500 }; 501 502 struct hns3_enet_tqp_vector { 503 struct hnae3_handle *handle; 504 u8 __iomem *mask_addr; 505 int vector_irq; 506 int irq_init_flag; 507 508 u16 idx; /* index in the TQP vector array per handle. */ 509 510 struct napi_struct napi; 511 512 struct hns3_enet_ring_group rx_group; 513 struct hns3_enet_ring_group tx_group; 514 515 cpumask_t affinity_mask; 516 u16 num_tqps; /* total number of tqps in TQP vector */ 517 struct irq_affinity_notify affinity_notify; 518 519 char name[HNAE3_INT_NAME_LEN]; 520 521 unsigned long last_jiffies; 522 } ____cacheline_internodealigned_in_smp; 523 524 enum hns3_udp_tnl_type { 525 HNS3_UDP_TNL_VXLAN, 526 HNS3_UDP_TNL_GENEVE, 527 HNS3_UDP_TNL_MAX, 528 }; 529 530 struct hns3_udp_tunnel { 531 u16 dst_port; 532 int used; 533 }; 534 535 struct hns3_nic_priv { 536 struct hnae3_handle *ae_handle; 537 u32 enet_ver; 538 u32 port_id; 539 struct net_device *netdev; 540 struct device *dev; 541 struct hns3_nic_ops ops; 542 543 /** 544 * the cb for nic to manage the ring buffer, the first half of the 545 * array is for tx_ring and vice versa for the second half 546 */ 547 struct hns3_nic_ring_data *ring_data; 548 struct hns3_enet_tqp_vector *tqp_vector; 549 u16 vector_num; 550 551 /* The most recently read link state */ 552 int link; 553 u64 tx_timeout_count; 554 555 unsigned long state; 556 557 struct timer_list service_timer; 558 559 struct work_struct service_task; 560 561 struct notifier_block notifier_block; 562 /* Vxlan/Geneve information */ 563 struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX]; 564 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 565 struct hns3_enet_coalesce tx_coal; 566 struct hns3_enet_coalesce rx_coal; 567 }; 568 569 union l3_hdr_info { 570 struct iphdr *v4; 571 struct ipv6hdr *v6; 572 unsigned char *hdr; 573 }; 574 575 union l4_hdr_info { 576 struct tcphdr *tcp; 577 struct udphdr *udp; 578 struct gre_base_hdr *gre; 579 unsigned char *hdr; 580 }; 581 582 static inline int ring_space(struct hns3_enet_ring *ring) 583 { 584 int begin = ring->next_to_clean; 585 int end = ring->next_to_use; 586 587 return ((end >= begin) ? (ring->desc_num - end + begin) : 588 (begin - end)) - 1; 589 } 590 591 static inline int is_ring_empty(struct hns3_enet_ring *ring) 592 { 593 return ring->next_to_use == ring->next_to_clean; 594 } 595 596 static inline u32 hns3_read_reg(void __iomem *base, u32 reg) 597 { 598 return readl(base + reg); 599 } 600 601 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value) 602 { 603 u8 __iomem *reg_addr = READ_ONCE(base); 604 605 writel(value, reg_addr + reg); 606 } 607 608 static inline bool hns3_dev_ongoing_func_reset(struct hnae3_ae_dev *ae_dev) 609 { 610 return (ae_dev && (ae_dev->reset_type == HNAE3_FUNC_RESET || 611 ae_dev->reset_type == HNAE3_FLR_RESET || 612 ae_dev->reset_type == HNAE3_VF_FUNC_RESET || 613 ae_dev->reset_type == HNAE3_VF_FULL_RESET || 614 ae_dev->reset_type == HNAE3_VF_PF_FUNC_RESET)); 615 } 616 617 #define hns3_read_dev(a, reg) \ 618 hns3_read_reg((a)->io_base, (reg)) 619 620 static inline bool hns3_nic_resetting(struct net_device *netdev) 621 { 622 struct hns3_nic_priv *priv = netdev_priv(netdev); 623 624 return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 625 } 626 627 #define hns3_write_dev(a, reg, value) \ 628 hns3_write_reg((a)->io_base, (reg), (value)) 629 630 #define hnae3_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \ 631 (tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG) 632 633 #define ring_to_dev(ring) (&(ring)->tqp->handle->pdev->dev) 634 635 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \ 636 DMA_TO_DEVICE : DMA_FROM_DEVICE) 637 638 #define tx_ring_data(priv, idx) ((priv)->ring_data[idx]) 639 640 #define hnae3_buf_size(_ring) ((_ring)->buf_size) 641 #define hnae3_page_order(_ring) (get_order(hnae3_buf_size(_ring))) 642 #define hnae3_page_size(_ring) (PAGE_SIZE << hnae3_page_order(_ring)) 643 644 /* iterator for handling rings in ring group */ 645 #define hns3_for_each_ring(pos, head) \ 646 for (pos = (head).ring; pos; pos = pos->next) 647 648 #define hns3_get_handle(ndev) \ 649 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle) 650 651 #define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1) 652 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2) 653 654 #define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2) 655 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4) 656 657 void hns3_ethtool_set_ops(struct net_device *netdev); 658 int hns3_set_channels(struct net_device *netdev, 659 struct ethtool_channels *ch); 660 661 void hns3_clean_tx_ring(struct hns3_enet_ring *ring); 662 int hns3_init_all_ring(struct hns3_nic_priv *priv); 663 int hns3_uninit_all_ring(struct hns3_nic_priv *priv); 664 int hns3_nic_reset_all_ring(struct hnae3_handle *h); 665 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev); 666 bool hns3_is_phys_func(struct pci_dev *pdev); 667 int hns3_clean_rx_ring( 668 struct hns3_enet_ring *ring, int budget, 669 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)); 670 671 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 672 u32 gl_value); 673 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 674 u32 gl_value); 675 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 676 u32 rl_value); 677 678 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable); 679 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags); 680 681 #ifdef CONFIG_HNS3_DCB 682 void hns3_dcbnl_setup(struct hnae3_handle *handle); 683 #else 684 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {} 685 #endif 686 687 void hns3_dbg_init(struct hnae3_handle *handle); 688 void hns3_dbg_uninit(struct hnae3_handle *handle); 689 void hns3_dbg_register_debugfs(const char *debugfs_dir_name); 690 void hns3_dbg_unregister_debugfs(void); 691 #endif 692