1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HNS3_ENET_H 5 #define __HNS3_ENET_H 6 7 #include <linux/if_vlan.h> 8 9 #include "hnae3.h" 10 11 enum hns3_nic_state { 12 HNS3_NIC_STATE_TESTING, 13 HNS3_NIC_STATE_RESETTING, 14 HNS3_NIC_STATE_INITED, 15 HNS3_NIC_STATE_DOWN, 16 HNS3_NIC_STATE_DISABLED, 17 HNS3_NIC_STATE_REMOVING, 18 HNS3_NIC_STATE_SERVICE_INITED, 19 HNS3_NIC_STATE_SERVICE_SCHED, 20 HNS3_NIC_STATE2_RESET_REQUESTED, 21 HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, 22 HNS3_NIC_STATE_MAX 23 }; 24 25 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000 26 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004 27 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008 28 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C 29 #define HNS3_RING_RX_RING_TAIL_REG 0x00018 30 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C 31 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020 32 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C 33 34 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040 35 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044 36 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048 37 #define HNS3_RING_TX_RING_TC_REG 0x00050 38 #define HNS3_RING_TX_RING_TAIL_REG 0x00058 39 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C 40 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060 41 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064 42 #define HNS3_RING_TX_RING_EBDNUM_REG 0x00068 43 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C 44 #define HNS3_RING_TX_RING_EBD_OFFSET_REG 0x00070 45 #define HNS3_RING_TX_RING_BD_ERR_REG 0x00074 46 #define HNS3_RING_EN_REG 0x00090 47 #define HNS3_RING_RX_EN_REG 0x00098 48 #define HNS3_RING_TX_EN_REG 0x000D4 49 50 #define HNS3_RX_HEAD_SIZE 256 51 52 #define HNS3_TX_TIMEOUT (5 * HZ) 53 #define HNS3_RING_NAME_LEN 16 54 #define HNS3_BUFFER_SIZE_2048 2048 55 #define HNS3_RING_MAX_PENDING 32760 56 #define HNS3_RING_MIN_PENDING 72 57 #define HNS3_RING_BD_MULTIPLE 8 58 /* max frame size of mac */ 59 #define HNS3_MAC_MAX_FRAME 9728 60 #define HNS3_MAX_MTU \ 61 (HNS3_MAC_MAX_FRAME - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN)) 62 63 #define HNS3_BD_SIZE_512_TYPE 0 64 #define HNS3_BD_SIZE_1024_TYPE 1 65 #define HNS3_BD_SIZE_2048_TYPE 2 66 #define HNS3_BD_SIZE_4096_TYPE 3 67 68 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1 69 #define HNS3_RX_FLAG_L3ID_IPV4 0x0 70 #define HNS3_RX_FLAG_L3ID_IPV6 0x1 71 #define HNS3_RX_FLAG_L4ID_UDP 0x0 72 #define HNS3_RX_FLAG_L4ID_TCP 0x1 73 74 #define HNS3_RXD_DMAC_S 0 75 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S) 76 #define HNS3_RXD_VLAN_S 2 77 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S) 78 #define HNS3_RXD_L3ID_S 4 79 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S) 80 #define HNS3_RXD_L4ID_S 8 81 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S) 82 #define HNS3_RXD_FRAG_B 12 83 #define HNS3_RXD_STRP_TAGP_S 13 84 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S) 85 86 #define HNS3_RXD_L2_CSUM_B 15 87 #define HNS3_RXD_L2_CSUM_L_S 4 88 #define HNS3_RXD_L2_CSUM_L_M (0xff << HNS3_RXD_L2_CSUM_L_S) 89 #define HNS3_RXD_L2_CSUM_H_S 24 90 #define HNS3_RXD_L2_CSUM_H_M (0xff << HNS3_RXD_L2_CSUM_H_S) 91 92 #define HNS3_RXD_L2E_B 16 93 #define HNS3_RXD_L3E_B 17 94 #define HNS3_RXD_L4E_B 18 95 #define HNS3_RXD_TRUNCAT_B 19 96 #define HNS3_RXD_HOI_B 20 97 #define HNS3_RXD_DOI_B 21 98 #define HNS3_RXD_OL3E_B 22 99 #define HNS3_RXD_OL4E_B 23 100 #define HNS3_RXD_GRO_COUNT_S 24 101 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S) 102 #define HNS3_RXD_GRO_FIXID_B 30 103 #define HNS3_RXD_GRO_ECN_B 31 104 105 #define HNS3_RXD_ODMAC_S 0 106 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S) 107 #define HNS3_RXD_OVLAN_S 2 108 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S) 109 #define HNS3_RXD_OL3ID_S 4 110 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S) 111 #define HNS3_RXD_OL4ID_S 8 112 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S) 113 #define HNS3_RXD_FBHI_S 12 114 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S) 115 #define HNS3_RXD_FBLI_S 14 116 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S) 117 118 #define HNS3_RXD_BDTYPE_S 0 119 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S) 120 #define HNS3_RXD_VLD_B 4 121 #define HNS3_RXD_UDP0_B 5 122 #define HNS3_RXD_EXTEND_B 7 123 #define HNS3_RXD_FE_B 8 124 #define HNS3_RXD_LUM_B 9 125 #define HNS3_RXD_CRCP_B 10 126 #define HNS3_RXD_L3L4P_B 11 127 #define HNS3_RXD_TSIND_S 12 128 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S) 129 #define HNS3_RXD_LKBK_B 15 130 #define HNS3_RXD_GRO_SIZE_S 16 131 #define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S) 132 133 #define HNS3_TXD_L3T_S 0 134 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S) 135 #define HNS3_TXD_L4T_S 2 136 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S) 137 #define HNS3_TXD_L3CS_B 4 138 #define HNS3_TXD_L4CS_B 5 139 #define HNS3_TXD_VLAN_B 6 140 #define HNS3_TXD_TSO_B 7 141 142 #define HNS3_TXD_L2LEN_S 8 143 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S) 144 #define HNS3_TXD_L3LEN_S 16 145 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S) 146 #define HNS3_TXD_L4LEN_S 24 147 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S) 148 149 #define HNS3_TXD_CSUM_START_S 8 150 #define HNS3_TXD_CSUM_START_M (0xffff << HNS3_TXD_CSUM_START_S) 151 152 #define HNS3_TXD_OL3T_S 0 153 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S) 154 #define HNS3_TXD_OVLAN_B 2 155 #define HNS3_TXD_MACSEC_B 3 156 #define HNS3_TXD_TUNTYPE_S 4 157 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S) 158 159 #define HNS3_TXD_CSUM_OFFSET_S 8 160 #define HNS3_TXD_CSUM_OFFSET_M (0xffff << HNS3_TXD_CSUM_OFFSET_S) 161 162 #define HNS3_TXD_BDTYPE_S 0 163 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S) 164 #define HNS3_TXD_FE_B 4 165 #define HNS3_TXD_SC_S 5 166 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S) 167 #define HNS3_TXD_EXTEND_B 7 168 #define HNS3_TXD_VLD_B 8 169 #define HNS3_TXD_RI_B 9 170 #define HNS3_TXD_RA_B 10 171 #define HNS3_TXD_TSYN_B 11 172 #define HNS3_TXD_DECTTL_S 12 173 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S) 174 175 #define HNS3_TXD_OL4CS_B 22 176 177 #define HNS3_TXD_MSS_S 0 178 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) 179 #define HNS3_TXD_HW_CS_B 14 180 181 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0) 182 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1) 183 184 #define HNS3_VECTOR_NOT_INITED 0 185 #define HNS3_VECTOR_INITED 1 186 187 #define HNS3_MAX_BD_SIZE 65535 188 #define HNS3_MAX_TSO_BD_NUM 63U 189 #define HNS3_MAX_TSO_SIZE \ 190 (HNS3_MAX_BD_SIZE * HNS3_MAX_TSO_BD_NUM) 191 192 #define HNS3_MAX_NON_TSO_SIZE(max_non_tso_bd_num) \ 193 (HNS3_MAX_BD_SIZE * (max_non_tso_bd_num)) 194 195 #define HNS3_VECTOR_GL0_OFFSET 0x100 196 #define HNS3_VECTOR_GL1_OFFSET 0x200 197 #define HNS3_VECTOR_GL2_OFFSET 0x300 198 #define HNS3_VECTOR_RL_OFFSET 0x900 199 #define HNS3_VECTOR_RL_EN_B 6 200 #define HNS3_VECTOR_TX_QL_OFFSET 0xe00 201 #define HNS3_VECTOR_RX_QL_OFFSET 0xf00 202 203 #define HNS3_RING_EN_B 0 204 205 enum hns3_pkt_l2t_type { 206 HNS3_L2_TYPE_UNICAST, 207 HNS3_L2_TYPE_MULTICAST, 208 HNS3_L2_TYPE_BROADCAST, 209 HNS3_L2_TYPE_INVALID, 210 }; 211 212 enum hns3_pkt_l3t_type { 213 HNS3_L3T_NONE, 214 HNS3_L3T_IPV6, 215 HNS3_L3T_IPV4, 216 HNS3_L3T_RESERVED 217 }; 218 219 enum hns3_pkt_l4t_type { 220 HNS3_L4T_UNKNOWN, 221 HNS3_L4T_TCP, 222 HNS3_L4T_UDP, 223 HNS3_L4T_SCTP 224 }; 225 226 enum hns3_pkt_ol3t_type { 227 HNS3_OL3T_NONE, 228 HNS3_OL3T_IPV6, 229 HNS3_OL3T_IPV4_NO_CSUM, 230 HNS3_OL3T_IPV4_CSUM 231 }; 232 233 enum hns3_pkt_tun_type { 234 HNS3_TUN_NONE, 235 HNS3_TUN_MAC_IN_UDP, 236 HNS3_TUN_NVGRE, 237 HNS3_TUN_OTHER 238 }; 239 240 /* hardware spec ring buffer format */ 241 struct __packed hns3_desc { 242 __le64 addr; 243 union { 244 struct { 245 __le16 vlan_tag; 246 __le16 send_size; 247 union { 248 __le32 type_cs_vlan_tso_len; 249 struct { 250 __u8 type_cs_vlan_tso; 251 __u8 l2_len; 252 __u8 l3_len; 253 __u8 l4_len; 254 }; 255 }; 256 __le16 outer_vlan_tag; 257 __le16 tv; 258 259 union { 260 __le32 ol_type_vlan_len_msec; 261 struct { 262 __u8 ol_type_vlan_msec; 263 __u8 ol2_len; 264 __u8 ol3_len; 265 __u8 ol4_len; 266 }; 267 }; 268 269 __le32 paylen_ol4cs; 270 __le16 bdtp_fe_sc_vld_ra_ri; 271 __le16 mss_hw_csum; 272 } tx; 273 274 struct { 275 __le32 l234_info; 276 __le16 pkt_len; 277 __le16 size; 278 279 __le32 rss_hash; 280 __le16 fd_id; 281 __le16 vlan_tag; 282 283 union { 284 __le32 ol_info; 285 struct { 286 __le16 o_dm_vlan_id_fb; 287 __le16 ot_vlan_tag; 288 }; 289 }; 290 291 __le32 bd_base_info; 292 } rx; 293 }; 294 }; 295 296 struct hns3_desc_cb { 297 dma_addr_t dma; /* dma address of this desc */ 298 void *buf; /* cpu addr for a desc */ 299 300 /* priv data for the desc, e.g. skb when use with ip stack */ 301 void *priv; 302 u32 page_offset; 303 u32 length; /* length of the buffer */ 304 305 u16 reuse_flag; 306 307 /* desc type, used by the ring user to mark the type of the priv data */ 308 u16 type; 309 u16 pagecnt_bias; 310 }; 311 312 enum hns3_pkt_l3type { 313 HNS3_L3_TYPE_IPV4, 314 HNS3_L3_TYPE_IPV6, 315 HNS3_L3_TYPE_ARP, 316 HNS3_L3_TYPE_RARP, 317 HNS3_L3_TYPE_IPV4_OPT, 318 HNS3_L3_TYPE_IPV6_EXT, 319 HNS3_L3_TYPE_LLDP, 320 HNS3_L3_TYPE_BPDU, 321 HNS3_L3_TYPE_MAC_PAUSE, 322 HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/ 323 324 /* reserved for 0xA~0xB */ 325 326 HNS3_L3_TYPE_CNM = 0xc, 327 328 /* reserved for 0xD~0xE */ 329 330 HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */ 331 }; 332 333 enum hns3_pkt_l4type { 334 HNS3_L4_TYPE_UDP, 335 HNS3_L4_TYPE_TCP, 336 HNS3_L4_TYPE_GRE, 337 HNS3_L4_TYPE_SCTP, 338 HNS3_L4_TYPE_IGMP, 339 HNS3_L4_TYPE_ICMP, 340 341 /* reserved for 0x6~0xE */ 342 343 HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */ 344 }; 345 346 enum hns3_pkt_ol3type { 347 HNS3_OL3_TYPE_IPV4 = 0, 348 HNS3_OL3_TYPE_IPV6, 349 /* reserved for 0x2~0x3 */ 350 HNS3_OL3_TYPE_IPV4_OPT = 4, 351 HNS3_OL3_TYPE_IPV6_EXT, 352 353 /* reserved for 0x6~0xE */ 354 355 HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */ 356 }; 357 358 enum hns3_pkt_ol4type { 359 HNS3_OL4_TYPE_NO_TUN, 360 HNS3_OL4_TYPE_MAC_IN_UDP, 361 HNS3_OL4_TYPE_NVGRE, 362 HNS3_OL4_TYPE_UNKNOWN 363 }; 364 365 struct ring_stats { 366 u64 sw_err_cnt; 367 u64 seg_pkt_cnt; 368 union { 369 struct { 370 u64 tx_pkts; 371 u64 tx_bytes; 372 u64 tx_more; 373 u64 restart_queue; 374 u64 tx_busy; 375 u64 tx_copy; 376 u64 tx_vlan_err; 377 u64 tx_l4_proto_err; 378 u64 tx_l2l3l4_err; 379 u64 tx_tso_err; 380 }; 381 struct { 382 u64 rx_pkts; 383 u64 rx_bytes; 384 u64 rx_err_cnt; 385 u64 reuse_pg_cnt; 386 u64 err_pkt_len; 387 u64 err_bd_num; 388 u64 l2_err; 389 u64 l3l4_csum_err; 390 u64 csum_complete; 391 u64 rx_multicast; 392 u64 non_reuse_pg; 393 }; 394 }; 395 }; 396 397 struct hns3_enet_ring { 398 struct hns3_desc *desc; /* dma map address space */ 399 struct hns3_desc_cb *desc_cb; 400 struct hns3_enet_ring *next; 401 struct hns3_enet_tqp_vector *tqp_vector; 402 struct hnae3_queue *tqp; 403 int queue_index; 404 struct device *dev; /* will be used for DMA mapping of descriptors */ 405 406 /* statistic */ 407 struct ring_stats stats; 408 struct u64_stats_sync syncp; 409 410 dma_addr_t desc_dma_addr; 411 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 412 u16 desc_num; /* total number of desc */ 413 int next_to_use; /* idx of next spare desc */ 414 415 /* idx of lastest sent desc, the ring is empty when equal to 416 * next_to_use 417 */ 418 int next_to_clean; 419 union { 420 int last_to_use; /* last idx used by xmit */ 421 u32 pull_len; /* memcpy len for current rx packet */ 422 }; 423 u32 frag_num; 424 void *va; /* first buffer address for current packet */ 425 426 u32 flag; /* ring attribute */ 427 428 int pending_buf; 429 struct sk_buff *skb; 430 struct sk_buff *tail_skb; 431 } ____cacheline_internodealigned_in_smp; 432 433 enum hns3_flow_level_range { 434 HNS3_FLOW_LOW = 0, 435 HNS3_FLOW_MID = 1, 436 HNS3_FLOW_HIGH = 2, 437 HNS3_FLOW_ULTRA = 3, 438 }; 439 440 #define HNS3_INT_GL_50K 0x0014 441 #define HNS3_INT_GL_20K 0x0032 442 #define HNS3_INT_GL_18K 0x0036 443 #define HNS3_INT_GL_8K 0x007C 444 445 #define HNS3_INT_GL_1US BIT(31) 446 447 #define HNS3_INT_RL_MAX 0x00EC 448 #define HNS3_INT_RL_ENABLE_MASK 0x40 449 450 #define HNS3_INT_QL_DEFAULT_CFG 0x20 451 452 struct hns3_enet_coalesce { 453 u16 int_gl; 454 u16 int_ql; 455 u16 int_ql_max; 456 u8 adapt_enable:1; 457 u8 ql_enable:1; 458 u8 unit_1us:1; 459 enum hns3_flow_level_range flow_level; 460 }; 461 462 struct hns3_enet_ring_group { 463 /* array of pointers to rings */ 464 struct hns3_enet_ring *ring; 465 u64 total_bytes; /* total bytes processed this group */ 466 u64 total_packets; /* total packets processed this group */ 467 u16 count; 468 struct hns3_enet_coalesce coal; 469 }; 470 471 struct hns3_enet_tqp_vector { 472 struct hnae3_handle *handle; 473 u8 __iomem *mask_addr; 474 int vector_irq; 475 int irq_init_flag; 476 477 u16 idx; /* index in the TQP vector array per handle. */ 478 479 struct napi_struct napi; 480 481 struct hns3_enet_ring_group rx_group; 482 struct hns3_enet_ring_group tx_group; 483 484 cpumask_t affinity_mask; 485 u16 num_tqps; /* total number of tqps in TQP vector */ 486 struct irq_affinity_notify affinity_notify; 487 488 char name[HNAE3_INT_NAME_LEN]; 489 490 unsigned long last_jiffies; 491 } ____cacheline_internodealigned_in_smp; 492 493 struct hns3_nic_priv { 494 struct hnae3_handle *ae_handle; 495 struct net_device *netdev; 496 struct device *dev; 497 498 /** 499 * the cb for nic to manage the ring buffer, the first half of the 500 * array is for tx_ring and vice versa for the second half 501 */ 502 struct hns3_enet_ring *ring; 503 struct hns3_enet_tqp_vector *tqp_vector; 504 u16 vector_num; 505 u8 max_non_tso_bd_num; 506 507 u64 tx_timeout_count; 508 509 unsigned long state; 510 511 struct hns3_enet_coalesce tx_coal; 512 struct hns3_enet_coalesce rx_coal; 513 }; 514 515 union l3_hdr_info { 516 struct iphdr *v4; 517 struct ipv6hdr *v6; 518 unsigned char *hdr; 519 }; 520 521 union l4_hdr_info { 522 struct tcphdr *tcp; 523 struct udphdr *udp; 524 struct gre_base_hdr *gre; 525 unsigned char *hdr; 526 }; 527 528 struct hns3_hw_error_info { 529 enum hnae3_hw_error_type type; 530 const char *msg; 531 }; 532 533 static inline int ring_space(struct hns3_enet_ring *ring) 534 { 535 /* This smp_load_acquire() pairs with smp_store_release() in 536 * hns3_nic_reclaim_one_desc called by hns3_clean_tx_ring. 537 */ 538 int begin = smp_load_acquire(&ring->next_to_clean); 539 int end = READ_ONCE(ring->next_to_use); 540 541 return ((end >= begin) ? (ring->desc_num - end + begin) : 542 (begin - end)) - 1; 543 } 544 545 static inline u32 hns3_read_reg(void __iomem *base, u32 reg) 546 { 547 return readl(base + reg); 548 } 549 550 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value) 551 { 552 u8 __iomem *reg_addr = READ_ONCE(base); 553 554 writel(value, reg_addr + reg); 555 } 556 557 #define hns3_read_dev(a, reg) \ 558 hns3_read_reg((a)->io_base, (reg)) 559 560 static inline bool hns3_nic_resetting(struct net_device *netdev) 561 { 562 struct hns3_nic_priv *priv = netdev_priv(netdev); 563 564 return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 565 } 566 567 #define hns3_write_dev(a, reg, value) \ 568 hns3_write_reg((a)->io_base, (reg), (value)) 569 570 #define ring_to_dev(ring) ((ring)->dev) 571 572 #define ring_to_netdev(ring) ((ring)->tqp_vector->napi.dev) 573 574 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \ 575 DMA_TO_DEVICE : DMA_FROM_DEVICE) 576 577 #define hns3_buf_size(_ring) ((_ring)->buf_size) 578 579 static inline unsigned int hns3_page_order(struct hns3_enet_ring *ring) 580 { 581 #if (PAGE_SIZE < 8192) 582 if (ring->buf_size > (PAGE_SIZE / 2)) 583 return 1; 584 #endif 585 return 0; 586 } 587 588 #define hns3_page_size(_ring) (PAGE_SIZE << hns3_page_order(_ring)) 589 590 /* iterator for handling rings in ring group */ 591 #define hns3_for_each_ring(pos, head) \ 592 for (pos = (head).ring; pos; pos = pos->next) 593 594 #define hns3_get_handle(ndev) \ 595 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle) 596 597 #define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1) 598 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2) 599 600 #define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2) 601 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4) 602 603 void hns3_ethtool_set_ops(struct net_device *netdev); 604 int hns3_set_channels(struct net_device *netdev, 605 struct ethtool_channels *ch); 606 607 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget); 608 int hns3_init_all_ring(struct hns3_nic_priv *priv); 609 int hns3_uninit_all_ring(struct hns3_nic_priv *priv); 610 int hns3_nic_reset_all_ring(struct hnae3_handle *h); 611 void hns3_fini_ring(struct hns3_enet_ring *ring); 612 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev); 613 bool hns3_is_phys_func(struct pci_dev *pdev); 614 int hns3_clean_rx_ring( 615 struct hns3_enet_ring *ring, int budget, 616 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)); 617 618 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 619 u32 gl_value); 620 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 621 u32 gl_value); 622 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 623 u32 rl_value); 624 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector, 625 u32 ql_value); 626 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector, 627 u32 ql_value); 628 629 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable); 630 void hns3_request_update_promisc_mode(struct hnae3_handle *handle); 631 632 #ifdef CONFIG_HNS3_DCB 633 void hns3_dcbnl_setup(struct hnae3_handle *handle); 634 #else 635 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {} 636 #endif 637 638 void hns3_dbg_init(struct hnae3_handle *handle); 639 void hns3_dbg_uninit(struct hnae3_handle *handle); 640 void hns3_dbg_register_debugfs(const char *debugfs_dir_name); 641 void hns3_dbg_unregister_debugfs(void); 642 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size); 643 #endif 644