1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #ifndef __HNS3_ENET_H 5 #define __HNS3_ENET_H 6 7 #include <linux/if_vlan.h> 8 9 #include "hnae3.h" 10 11 enum hns3_nic_state { 12 HNS3_NIC_STATE_TESTING, 13 HNS3_NIC_STATE_RESETTING, 14 HNS3_NIC_STATE_INITED, 15 HNS3_NIC_STATE_DOWN, 16 HNS3_NIC_STATE_DISABLED, 17 HNS3_NIC_STATE_REMOVING, 18 HNS3_NIC_STATE_SERVICE_INITED, 19 HNS3_NIC_STATE_SERVICE_SCHED, 20 HNS3_NIC_STATE2_RESET_REQUESTED, 21 HNS3_NIC_STATE_MAX 22 }; 23 24 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000 25 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004 26 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008 27 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C 28 #define HNS3_RING_RX_RING_TAIL_REG 0x00018 29 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C 30 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020 31 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C 32 33 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040 34 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044 35 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048 36 #define HNS3_RING_TX_RING_TC_REG 0x00050 37 #define HNS3_RING_TX_RING_TAIL_REG 0x00058 38 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C 39 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060 40 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064 41 #define HNS3_RING_TX_RING_EBDNUM_REG 0x00068 42 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C 43 #define HNS3_RING_TX_RING_EBD_OFFSET_REG 0x00070 44 #define HNS3_RING_TX_RING_BD_ERR_REG 0x00074 45 #define HNS3_RING_EN_REG 0x00090 46 #define HNS3_RING_RX_EN_REG 0x00098 47 #define HNS3_RING_TX_EN_REG 0x000D4 48 49 #define HNS3_RX_HEAD_SIZE 256 50 51 #define HNS3_TX_TIMEOUT (5 * HZ) 52 #define HNS3_RING_NAME_LEN 16 53 #define HNS3_BUFFER_SIZE_2048 2048 54 #define HNS3_RING_MAX_PENDING 32760 55 #define HNS3_RING_MIN_PENDING 72 56 #define HNS3_RING_BD_MULTIPLE 8 57 /* max frame size of mac */ 58 #define HNS3_MAC_MAX_FRAME 9728 59 #define HNS3_MAX_MTU \ 60 (HNS3_MAC_MAX_FRAME - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN)) 61 62 #define HNS3_BD_SIZE_512_TYPE 0 63 #define HNS3_BD_SIZE_1024_TYPE 1 64 #define HNS3_BD_SIZE_2048_TYPE 2 65 #define HNS3_BD_SIZE_4096_TYPE 3 66 67 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1 68 #define HNS3_RX_FLAG_L3ID_IPV4 0x0 69 #define HNS3_RX_FLAG_L3ID_IPV6 0x1 70 #define HNS3_RX_FLAG_L4ID_UDP 0x0 71 #define HNS3_RX_FLAG_L4ID_TCP 0x1 72 73 #define HNS3_RXD_DMAC_S 0 74 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S) 75 #define HNS3_RXD_VLAN_S 2 76 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S) 77 #define HNS3_RXD_L3ID_S 4 78 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S) 79 #define HNS3_RXD_L4ID_S 8 80 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S) 81 #define HNS3_RXD_FRAG_B 12 82 #define HNS3_RXD_STRP_TAGP_S 13 83 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S) 84 85 #define HNS3_RXD_L2E_B 16 86 #define HNS3_RXD_L3E_B 17 87 #define HNS3_RXD_L4E_B 18 88 #define HNS3_RXD_TRUNCAT_B 19 89 #define HNS3_RXD_HOI_B 20 90 #define HNS3_RXD_DOI_B 21 91 #define HNS3_RXD_OL3E_B 22 92 #define HNS3_RXD_OL4E_B 23 93 #define HNS3_RXD_GRO_COUNT_S 24 94 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S) 95 #define HNS3_RXD_GRO_FIXID_B 30 96 #define HNS3_RXD_GRO_ECN_B 31 97 98 #define HNS3_RXD_ODMAC_S 0 99 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S) 100 #define HNS3_RXD_OVLAN_S 2 101 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S) 102 #define HNS3_RXD_OL3ID_S 4 103 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S) 104 #define HNS3_RXD_OL4ID_S 8 105 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S) 106 #define HNS3_RXD_FBHI_S 12 107 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S) 108 #define HNS3_RXD_FBLI_S 14 109 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S) 110 111 #define HNS3_RXD_BDTYPE_S 0 112 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S) 113 #define HNS3_RXD_VLD_B 4 114 #define HNS3_RXD_UDP0_B 5 115 #define HNS3_RXD_EXTEND_B 7 116 #define HNS3_RXD_FE_B 8 117 #define HNS3_RXD_LUM_B 9 118 #define HNS3_RXD_CRCP_B 10 119 #define HNS3_RXD_L3L4P_B 11 120 #define HNS3_RXD_TSIND_S 12 121 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S) 122 #define HNS3_RXD_LKBK_B 15 123 #define HNS3_RXD_GRO_SIZE_S 16 124 #define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S) 125 126 #define HNS3_TXD_L3T_S 0 127 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S) 128 #define HNS3_TXD_L4T_S 2 129 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S) 130 #define HNS3_TXD_L3CS_B 4 131 #define HNS3_TXD_L4CS_B 5 132 #define HNS3_TXD_VLAN_B 6 133 #define HNS3_TXD_TSO_B 7 134 135 #define HNS3_TXD_L2LEN_S 8 136 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S) 137 #define HNS3_TXD_L3LEN_S 16 138 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S) 139 #define HNS3_TXD_L4LEN_S 24 140 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S) 141 142 #define HNS3_TXD_OL3T_S 0 143 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S) 144 #define HNS3_TXD_OVLAN_B 2 145 #define HNS3_TXD_MACSEC_B 3 146 #define HNS3_TXD_TUNTYPE_S 4 147 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S) 148 149 #define HNS3_TXD_BDTYPE_S 0 150 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S) 151 #define HNS3_TXD_FE_B 4 152 #define HNS3_TXD_SC_S 5 153 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S) 154 #define HNS3_TXD_EXTEND_B 7 155 #define HNS3_TXD_VLD_B 8 156 #define HNS3_TXD_RI_B 9 157 #define HNS3_TXD_RA_B 10 158 #define HNS3_TXD_TSYN_B 11 159 #define HNS3_TXD_DECTTL_S 12 160 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S) 161 162 #define HNS3_TXD_MSS_S 0 163 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) 164 165 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0) 166 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1) 167 168 #define HNS3_VECTOR_NOT_INITED 0 169 #define HNS3_VECTOR_INITED 1 170 171 #define HNS3_MAX_BD_SIZE 65535 172 #define HNS3_MAX_TSO_BD_NUM 63U 173 #define HNS3_MAX_TSO_SIZE \ 174 (HNS3_MAX_BD_SIZE * HNS3_MAX_TSO_BD_NUM) 175 176 #define HNS3_MAX_NON_TSO_SIZE(max_non_tso_bd_num) \ 177 (HNS3_MAX_BD_SIZE * (max_non_tso_bd_num)) 178 179 #define HNS3_VECTOR_GL0_OFFSET 0x100 180 #define HNS3_VECTOR_GL1_OFFSET 0x200 181 #define HNS3_VECTOR_GL2_OFFSET 0x300 182 #define HNS3_VECTOR_RL_OFFSET 0x900 183 #define HNS3_VECTOR_RL_EN_B 6 184 #define HNS3_VECTOR_TX_QL_OFFSET 0xe00 185 #define HNS3_VECTOR_RX_QL_OFFSET 0xf00 186 187 #define HNS3_RING_EN_B 0 188 189 enum hns3_pkt_l2t_type { 190 HNS3_L2_TYPE_UNICAST, 191 HNS3_L2_TYPE_MULTICAST, 192 HNS3_L2_TYPE_BROADCAST, 193 HNS3_L2_TYPE_INVALID, 194 }; 195 196 enum hns3_pkt_l3t_type { 197 HNS3_L3T_NONE, 198 HNS3_L3T_IPV6, 199 HNS3_L3T_IPV4, 200 HNS3_L3T_RESERVED 201 }; 202 203 enum hns3_pkt_l4t_type { 204 HNS3_L4T_UNKNOWN, 205 HNS3_L4T_TCP, 206 HNS3_L4T_UDP, 207 HNS3_L4T_SCTP 208 }; 209 210 enum hns3_pkt_ol3t_type { 211 HNS3_OL3T_NONE, 212 HNS3_OL3T_IPV6, 213 HNS3_OL3T_IPV4_NO_CSUM, 214 HNS3_OL3T_IPV4_CSUM 215 }; 216 217 enum hns3_pkt_tun_type { 218 HNS3_TUN_NONE, 219 HNS3_TUN_MAC_IN_UDP, 220 HNS3_TUN_NVGRE, 221 HNS3_TUN_OTHER 222 }; 223 224 /* hardware spec ring buffer format */ 225 struct __packed hns3_desc { 226 __le64 addr; 227 union { 228 struct { 229 __le16 vlan_tag; 230 __le16 send_size; 231 union { 232 __le32 type_cs_vlan_tso_len; 233 struct { 234 __u8 type_cs_vlan_tso; 235 __u8 l2_len; 236 __u8 l3_len; 237 __u8 l4_len; 238 }; 239 }; 240 __le16 outer_vlan_tag; 241 __le16 tv; 242 243 union { 244 __le32 ol_type_vlan_len_msec; 245 struct { 246 __u8 ol_type_vlan_msec; 247 __u8 ol2_len; 248 __u8 ol3_len; 249 __u8 ol4_len; 250 }; 251 }; 252 253 __le32 paylen; 254 __le16 bdtp_fe_sc_vld_ra_ri; 255 __le16 mss; 256 } tx; 257 258 struct { 259 __le32 l234_info; 260 __le16 pkt_len; 261 __le16 size; 262 263 __le32 rss_hash; 264 __le16 fd_id; 265 __le16 vlan_tag; 266 267 union { 268 __le32 ol_info; 269 struct { 270 __le16 o_dm_vlan_id_fb; 271 __le16 ot_vlan_tag; 272 }; 273 }; 274 275 __le32 bd_base_info; 276 } rx; 277 }; 278 }; 279 280 struct hns3_desc_cb { 281 dma_addr_t dma; /* dma address of this desc */ 282 void *buf; /* cpu addr for a desc */ 283 284 /* priv data for the desc, e.g. skb when use with ip stack */ 285 void *priv; 286 u32 page_offset; 287 u32 length; /* length of the buffer */ 288 289 u16 reuse_flag; 290 291 /* desc type, used by the ring user to mark the type of the priv data */ 292 u16 type; 293 u16 pagecnt_bias; 294 }; 295 296 enum hns3_pkt_l3type { 297 HNS3_L3_TYPE_IPV4, 298 HNS3_L3_TYPE_IPV6, 299 HNS3_L3_TYPE_ARP, 300 HNS3_L3_TYPE_RARP, 301 HNS3_L3_TYPE_IPV4_OPT, 302 HNS3_L3_TYPE_IPV6_EXT, 303 HNS3_L3_TYPE_LLDP, 304 HNS3_L3_TYPE_BPDU, 305 HNS3_L3_TYPE_MAC_PAUSE, 306 HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/ 307 308 /* reserved for 0xA~0xB */ 309 310 HNS3_L3_TYPE_CNM = 0xc, 311 312 /* reserved for 0xD~0xE */ 313 314 HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */ 315 }; 316 317 enum hns3_pkt_l4type { 318 HNS3_L4_TYPE_UDP, 319 HNS3_L4_TYPE_TCP, 320 HNS3_L4_TYPE_GRE, 321 HNS3_L4_TYPE_SCTP, 322 HNS3_L4_TYPE_IGMP, 323 HNS3_L4_TYPE_ICMP, 324 325 /* reserved for 0x6~0xE */ 326 327 HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */ 328 }; 329 330 enum hns3_pkt_ol3type { 331 HNS3_OL3_TYPE_IPV4 = 0, 332 HNS3_OL3_TYPE_IPV6, 333 /* reserved for 0x2~0x3 */ 334 HNS3_OL3_TYPE_IPV4_OPT = 4, 335 HNS3_OL3_TYPE_IPV6_EXT, 336 337 /* reserved for 0x6~0xE */ 338 339 HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */ 340 }; 341 342 enum hns3_pkt_ol4type { 343 HNS3_OL4_TYPE_NO_TUN, 344 HNS3_OL4_TYPE_MAC_IN_UDP, 345 HNS3_OL4_TYPE_NVGRE, 346 HNS3_OL4_TYPE_UNKNOWN 347 }; 348 349 struct ring_stats { 350 u64 sw_err_cnt; 351 u64 seg_pkt_cnt; 352 union { 353 struct { 354 u64 tx_pkts; 355 u64 tx_bytes; 356 u64 tx_more; 357 u64 restart_queue; 358 u64 tx_busy; 359 u64 tx_copy; 360 u64 tx_vlan_err; 361 u64 tx_l4_proto_err; 362 u64 tx_l2l3l4_err; 363 u64 tx_tso_err; 364 }; 365 struct { 366 u64 rx_pkts; 367 u64 rx_bytes; 368 u64 rx_err_cnt; 369 u64 reuse_pg_cnt; 370 u64 err_pkt_len; 371 u64 err_bd_num; 372 u64 l2_err; 373 u64 l3l4_csum_err; 374 u64 rx_multicast; 375 u64 non_reuse_pg; 376 }; 377 }; 378 }; 379 380 struct hns3_enet_ring { 381 struct hns3_desc *desc; /* dma map address space */ 382 struct hns3_desc_cb *desc_cb; 383 struct hns3_enet_ring *next; 384 struct hns3_enet_tqp_vector *tqp_vector; 385 struct hnae3_queue *tqp; 386 int queue_index; 387 struct device *dev; /* will be used for DMA mapping of descriptors */ 388 389 /* statistic */ 390 struct ring_stats stats; 391 struct u64_stats_sync syncp; 392 393 dma_addr_t desc_dma_addr; 394 u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 395 u16 desc_num; /* total number of desc */ 396 int next_to_use; /* idx of next spare desc */ 397 398 /* idx of lastest sent desc, the ring is empty when equal to 399 * next_to_use 400 */ 401 int next_to_clean; 402 union { 403 int last_to_use; /* last idx used by xmit */ 404 u32 pull_len; /* memcpy len for current rx packet */ 405 }; 406 u32 frag_num; 407 void *va; /* first buffer address for current packet */ 408 409 u32 flag; /* ring attribute */ 410 411 int pending_buf; 412 struct sk_buff *skb; 413 struct sk_buff *tail_skb; 414 } ____cacheline_internodealigned_in_smp; 415 416 enum hns3_flow_level_range { 417 HNS3_FLOW_LOW = 0, 418 HNS3_FLOW_MID = 1, 419 HNS3_FLOW_HIGH = 2, 420 HNS3_FLOW_ULTRA = 3, 421 }; 422 423 #define HNS3_INT_GL_50K 0x0014 424 #define HNS3_INT_GL_20K 0x0032 425 #define HNS3_INT_GL_18K 0x0036 426 #define HNS3_INT_GL_8K 0x007C 427 428 #define HNS3_INT_GL_1US BIT(31) 429 430 #define HNS3_INT_RL_MAX 0x00EC 431 #define HNS3_INT_RL_ENABLE_MASK 0x40 432 433 #define HNS3_INT_QL_DEFAULT_CFG 0x20 434 435 struct hns3_enet_coalesce { 436 u16 int_gl; 437 u16 int_ql; 438 u16 int_ql_max; 439 u8 adapt_enable:1; 440 u8 ql_enable:1; 441 u8 unit_1us:1; 442 enum hns3_flow_level_range flow_level; 443 }; 444 445 struct hns3_enet_ring_group { 446 /* array of pointers to rings */ 447 struct hns3_enet_ring *ring; 448 u64 total_bytes; /* total bytes processed this group */ 449 u64 total_packets; /* total packets processed this group */ 450 u16 count; 451 struct hns3_enet_coalesce coal; 452 }; 453 454 struct hns3_enet_tqp_vector { 455 struct hnae3_handle *handle; 456 u8 __iomem *mask_addr; 457 int vector_irq; 458 int irq_init_flag; 459 460 u16 idx; /* index in the TQP vector array per handle. */ 461 462 struct napi_struct napi; 463 464 struct hns3_enet_ring_group rx_group; 465 struct hns3_enet_ring_group tx_group; 466 467 cpumask_t affinity_mask; 468 u16 num_tqps; /* total number of tqps in TQP vector */ 469 struct irq_affinity_notify affinity_notify; 470 471 char name[HNAE3_INT_NAME_LEN]; 472 473 unsigned long last_jiffies; 474 } ____cacheline_internodealigned_in_smp; 475 476 struct hns3_nic_priv { 477 struct hnae3_handle *ae_handle; 478 struct net_device *netdev; 479 struct device *dev; 480 481 /** 482 * the cb for nic to manage the ring buffer, the first half of the 483 * array is for tx_ring and vice versa for the second half 484 */ 485 struct hns3_enet_ring *ring; 486 struct hns3_enet_tqp_vector *tqp_vector; 487 u16 vector_num; 488 u8 max_non_tso_bd_num; 489 490 u64 tx_timeout_count; 491 492 unsigned long state; 493 494 struct hns3_enet_coalesce tx_coal; 495 struct hns3_enet_coalesce rx_coal; 496 }; 497 498 union l3_hdr_info { 499 struct iphdr *v4; 500 struct ipv6hdr *v6; 501 unsigned char *hdr; 502 }; 503 504 union l4_hdr_info { 505 struct tcphdr *tcp; 506 struct udphdr *udp; 507 struct gre_base_hdr *gre; 508 unsigned char *hdr; 509 }; 510 511 struct hns3_hw_error_info { 512 enum hnae3_hw_error_type type; 513 const char *msg; 514 }; 515 516 static inline int ring_space(struct hns3_enet_ring *ring) 517 { 518 /* This smp_load_acquire() pairs with smp_store_release() in 519 * hns3_nic_reclaim_one_desc called by hns3_clean_tx_ring. 520 */ 521 int begin = smp_load_acquire(&ring->next_to_clean); 522 int end = READ_ONCE(ring->next_to_use); 523 524 return ((end >= begin) ? (ring->desc_num - end + begin) : 525 (begin - end)) - 1; 526 } 527 528 static inline u32 hns3_read_reg(void __iomem *base, u32 reg) 529 { 530 return readl(base + reg); 531 } 532 533 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value) 534 { 535 u8 __iomem *reg_addr = READ_ONCE(base); 536 537 writel(value, reg_addr + reg); 538 } 539 540 #define hns3_read_dev(a, reg) \ 541 hns3_read_reg((a)->io_base, (reg)) 542 543 static inline bool hns3_nic_resetting(struct net_device *netdev) 544 { 545 struct hns3_nic_priv *priv = netdev_priv(netdev); 546 547 return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 548 } 549 550 #define hns3_write_dev(a, reg, value) \ 551 hns3_write_reg((a)->io_base, (reg), (value)) 552 553 #define ring_to_dev(ring) ((ring)->dev) 554 555 #define ring_to_netdev(ring) ((ring)->tqp_vector->napi.dev) 556 557 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \ 558 DMA_TO_DEVICE : DMA_FROM_DEVICE) 559 560 #define hns3_buf_size(_ring) ((_ring)->buf_size) 561 562 static inline unsigned int hns3_page_order(struct hns3_enet_ring *ring) 563 { 564 #if (PAGE_SIZE < 8192) 565 if (ring->buf_size > (PAGE_SIZE / 2)) 566 return 1; 567 #endif 568 return 0; 569 } 570 571 #define hns3_page_size(_ring) (PAGE_SIZE << hns3_page_order(_ring)) 572 573 /* iterator for handling rings in ring group */ 574 #define hns3_for_each_ring(pos, head) \ 575 for (pos = (head).ring; pos; pos = pos->next) 576 577 #define hns3_get_handle(ndev) \ 578 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle) 579 580 #define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1) 581 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2) 582 583 #define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2) 584 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4) 585 586 void hns3_ethtool_set_ops(struct net_device *netdev); 587 int hns3_set_channels(struct net_device *netdev, 588 struct ethtool_channels *ch); 589 590 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget); 591 int hns3_init_all_ring(struct hns3_nic_priv *priv); 592 int hns3_uninit_all_ring(struct hns3_nic_priv *priv); 593 int hns3_nic_reset_all_ring(struct hnae3_handle *h); 594 void hns3_fini_ring(struct hns3_enet_ring *ring); 595 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev); 596 bool hns3_is_phys_func(struct pci_dev *pdev); 597 int hns3_clean_rx_ring( 598 struct hns3_enet_ring *ring, int budget, 599 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)); 600 601 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 602 u32 gl_value); 603 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 604 u32 gl_value); 605 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 606 u32 rl_value); 607 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector, 608 u32 ql_value); 609 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector, 610 u32 ql_value); 611 612 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable); 613 void hns3_request_update_promisc_mode(struct hnae3_handle *handle); 614 615 #ifdef CONFIG_HNS3_DCB 616 void hns3_dcbnl_setup(struct hnae3_handle *handle); 617 #else 618 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {} 619 #endif 620 621 void hns3_dbg_init(struct hnae3_handle *handle); 622 void hns3_dbg_uninit(struct hnae3_handle *handle); 623 void hns3_dbg_register_debugfs(const char *debugfs_dir_name); 624 void hns3_dbg_unregister_debugfs(void); 625 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size); 626 #endif 627