1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #ifdef CONFIG_RFS_ACCEL 8 #include <linux/cpu_rmap.h> 9 #endif 10 #include <linux/if_vlan.h> 11 #include <linux/irq.h> 12 #include <linux/ip.h> 13 #include <linux/ipv6.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/aer.h> 17 #include <linux/skbuff.h> 18 #include <linux/sctp.h> 19 #include <net/gre.h> 20 #include <net/ip6_checksum.h> 21 #include <net/pkt_cls.h> 22 #include <net/tcp.h> 23 #include <net/vxlan.h> 24 #include <net/geneve.h> 25 26 #include "hnae3.h" 27 #include "hns3_enet.h" 28 /* All hns3 tracepoints are defined by the include below, which 29 * must be included exactly once across the whole kernel with 30 * CREATE_TRACE_POINTS defined 31 */ 32 #define CREATE_TRACE_POINTS 33 #include "hns3_trace.h" 34 35 #define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift)) 36 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE) 37 38 #define hns3_rl_err(fmt, ...) \ 39 do { \ 40 if (net_ratelimit()) \ 41 netdev_err(fmt, ##__VA_ARGS__); \ 42 } while (0) 43 44 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force); 45 46 static const char hns3_driver_name[] = "hns3"; 47 static const char hns3_driver_string[] = 48 "Hisilicon Ethernet Network Driver for Hip08 Family"; 49 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 50 static struct hnae3_client client; 51 52 static int debug = -1; 53 module_param(debug, int, 0); 54 MODULE_PARM_DESC(debug, " Network interface message level setting"); 55 56 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 57 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) 58 59 #define HNS3_INNER_VLAN_TAG 1 60 #define HNS3_OUTER_VLAN_TAG 2 61 62 #define HNS3_MIN_TX_LEN 33U 63 64 /* hns3_pci_tbl - PCI Device ID Table 65 * 66 * Last entry must be all 0s 67 * 68 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 69 * Class, Class Mask, private data (not used) } 70 */ 71 static const struct pci_device_id hns3_pci_tbl[] = { 72 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 74 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 75 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 76 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 77 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 79 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 80 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 81 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 82 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 83 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 84 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 85 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 86 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 88 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 89 /* required last entry */ 90 {0, } 91 }; 92 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 93 94 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t) \ 95 { ptype, \ 96 l, \ 97 CHECKSUM_##s, \ 98 HNS3_L3_TYPE_##t, \ 99 1 } 100 101 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \ 102 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0 } 103 104 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = { 105 HNS3_RX_PTYPE_UNUSED_ENTRY(0), 106 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP), 107 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP), 108 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP), 109 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL), 110 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL), 111 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL), 112 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM), 113 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL), 114 HNS3_RX_PTYPE_UNUSED_ENTRY(9), 115 HNS3_RX_PTYPE_UNUSED_ENTRY(10), 116 HNS3_RX_PTYPE_UNUSED_ENTRY(11), 117 HNS3_RX_PTYPE_UNUSED_ENTRY(12), 118 HNS3_RX_PTYPE_UNUSED_ENTRY(13), 119 HNS3_RX_PTYPE_UNUSED_ENTRY(14), 120 HNS3_RX_PTYPE_UNUSED_ENTRY(15), 121 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL), 122 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4), 123 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4), 124 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4), 125 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4), 126 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4), 127 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4), 128 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4), 129 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4), 130 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4), 131 HNS3_RX_PTYPE_UNUSED_ENTRY(26), 132 HNS3_RX_PTYPE_UNUSED_ENTRY(27), 133 HNS3_RX_PTYPE_UNUSED_ENTRY(28), 134 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL), 135 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL), 136 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4), 137 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4), 138 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4), 139 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4), 140 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4), 141 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4), 142 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4), 143 HNS3_RX_PTYPE_UNUSED_ENTRY(38), 144 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6), 145 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6), 146 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6), 147 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6), 148 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6), 149 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6), 150 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6), 151 HNS3_RX_PTYPE_UNUSED_ENTRY(46), 152 HNS3_RX_PTYPE_UNUSED_ENTRY(47), 153 HNS3_RX_PTYPE_UNUSED_ENTRY(48), 154 HNS3_RX_PTYPE_UNUSED_ENTRY(49), 155 HNS3_RX_PTYPE_UNUSED_ENTRY(50), 156 HNS3_RX_PTYPE_UNUSED_ENTRY(51), 157 HNS3_RX_PTYPE_UNUSED_ENTRY(52), 158 HNS3_RX_PTYPE_UNUSED_ENTRY(53), 159 HNS3_RX_PTYPE_UNUSED_ENTRY(54), 160 HNS3_RX_PTYPE_UNUSED_ENTRY(55), 161 HNS3_RX_PTYPE_UNUSED_ENTRY(56), 162 HNS3_RX_PTYPE_UNUSED_ENTRY(57), 163 HNS3_RX_PTYPE_UNUSED_ENTRY(58), 164 HNS3_RX_PTYPE_UNUSED_ENTRY(59), 165 HNS3_RX_PTYPE_UNUSED_ENTRY(60), 166 HNS3_RX_PTYPE_UNUSED_ENTRY(61), 167 HNS3_RX_PTYPE_UNUSED_ENTRY(62), 168 HNS3_RX_PTYPE_UNUSED_ENTRY(63), 169 HNS3_RX_PTYPE_UNUSED_ENTRY(64), 170 HNS3_RX_PTYPE_UNUSED_ENTRY(65), 171 HNS3_RX_PTYPE_UNUSED_ENTRY(66), 172 HNS3_RX_PTYPE_UNUSED_ENTRY(67), 173 HNS3_RX_PTYPE_UNUSED_ENTRY(68), 174 HNS3_RX_PTYPE_UNUSED_ENTRY(69), 175 HNS3_RX_PTYPE_UNUSED_ENTRY(70), 176 HNS3_RX_PTYPE_UNUSED_ENTRY(71), 177 HNS3_RX_PTYPE_UNUSED_ENTRY(72), 178 HNS3_RX_PTYPE_UNUSED_ENTRY(73), 179 HNS3_RX_PTYPE_UNUSED_ENTRY(74), 180 HNS3_RX_PTYPE_UNUSED_ENTRY(75), 181 HNS3_RX_PTYPE_UNUSED_ENTRY(76), 182 HNS3_RX_PTYPE_UNUSED_ENTRY(77), 183 HNS3_RX_PTYPE_UNUSED_ENTRY(78), 184 HNS3_RX_PTYPE_UNUSED_ENTRY(79), 185 HNS3_RX_PTYPE_UNUSED_ENTRY(80), 186 HNS3_RX_PTYPE_UNUSED_ENTRY(81), 187 HNS3_RX_PTYPE_UNUSED_ENTRY(82), 188 HNS3_RX_PTYPE_UNUSED_ENTRY(83), 189 HNS3_RX_PTYPE_UNUSED_ENTRY(84), 190 HNS3_RX_PTYPE_UNUSED_ENTRY(85), 191 HNS3_RX_PTYPE_UNUSED_ENTRY(86), 192 HNS3_RX_PTYPE_UNUSED_ENTRY(87), 193 HNS3_RX_PTYPE_UNUSED_ENTRY(88), 194 HNS3_RX_PTYPE_UNUSED_ENTRY(89), 195 HNS3_RX_PTYPE_UNUSED_ENTRY(90), 196 HNS3_RX_PTYPE_UNUSED_ENTRY(91), 197 HNS3_RX_PTYPE_UNUSED_ENTRY(92), 198 HNS3_RX_PTYPE_UNUSED_ENTRY(93), 199 HNS3_RX_PTYPE_UNUSED_ENTRY(94), 200 HNS3_RX_PTYPE_UNUSED_ENTRY(95), 201 HNS3_RX_PTYPE_UNUSED_ENTRY(96), 202 HNS3_RX_PTYPE_UNUSED_ENTRY(97), 203 HNS3_RX_PTYPE_UNUSED_ENTRY(98), 204 HNS3_RX_PTYPE_UNUSED_ENTRY(99), 205 HNS3_RX_PTYPE_UNUSED_ENTRY(100), 206 HNS3_RX_PTYPE_UNUSED_ENTRY(101), 207 HNS3_RX_PTYPE_UNUSED_ENTRY(102), 208 HNS3_RX_PTYPE_UNUSED_ENTRY(103), 209 HNS3_RX_PTYPE_UNUSED_ENTRY(104), 210 HNS3_RX_PTYPE_UNUSED_ENTRY(105), 211 HNS3_RX_PTYPE_UNUSED_ENTRY(106), 212 HNS3_RX_PTYPE_UNUSED_ENTRY(107), 213 HNS3_RX_PTYPE_UNUSED_ENTRY(108), 214 HNS3_RX_PTYPE_UNUSED_ENTRY(109), 215 HNS3_RX_PTYPE_UNUSED_ENTRY(110), 216 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6), 217 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6), 218 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6), 219 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6), 220 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6), 221 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6), 222 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6), 223 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6), 224 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6), 225 HNS3_RX_PTYPE_UNUSED_ENTRY(120), 226 HNS3_RX_PTYPE_UNUSED_ENTRY(121), 227 HNS3_RX_PTYPE_UNUSED_ENTRY(122), 228 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL), 229 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL), 230 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4), 231 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4), 232 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4), 233 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4), 234 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4), 235 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4), 236 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4), 237 HNS3_RX_PTYPE_UNUSED_ENTRY(132), 238 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6), 239 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6), 240 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6), 241 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6), 242 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6), 243 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6), 244 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6), 245 HNS3_RX_PTYPE_UNUSED_ENTRY(140), 246 HNS3_RX_PTYPE_UNUSED_ENTRY(141), 247 HNS3_RX_PTYPE_UNUSED_ENTRY(142), 248 HNS3_RX_PTYPE_UNUSED_ENTRY(143), 249 HNS3_RX_PTYPE_UNUSED_ENTRY(144), 250 HNS3_RX_PTYPE_UNUSED_ENTRY(145), 251 HNS3_RX_PTYPE_UNUSED_ENTRY(146), 252 HNS3_RX_PTYPE_UNUSED_ENTRY(147), 253 HNS3_RX_PTYPE_UNUSED_ENTRY(148), 254 HNS3_RX_PTYPE_UNUSED_ENTRY(149), 255 HNS3_RX_PTYPE_UNUSED_ENTRY(150), 256 HNS3_RX_PTYPE_UNUSED_ENTRY(151), 257 HNS3_RX_PTYPE_UNUSED_ENTRY(152), 258 HNS3_RX_PTYPE_UNUSED_ENTRY(153), 259 HNS3_RX_PTYPE_UNUSED_ENTRY(154), 260 HNS3_RX_PTYPE_UNUSED_ENTRY(155), 261 HNS3_RX_PTYPE_UNUSED_ENTRY(156), 262 HNS3_RX_PTYPE_UNUSED_ENTRY(157), 263 HNS3_RX_PTYPE_UNUSED_ENTRY(158), 264 HNS3_RX_PTYPE_UNUSED_ENTRY(159), 265 HNS3_RX_PTYPE_UNUSED_ENTRY(160), 266 HNS3_RX_PTYPE_UNUSED_ENTRY(161), 267 HNS3_RX_PTYPE_UNUSED_ENTRY(162), 268 HNS3_RX_PTYPE_UNUSED_ENTRY(163), 269 HNS3_RX_PTYPE_UNUSED_ENTRY(164), 270 HNS3_RX_PTYPE_UNUSED_ENTRY(165), 271 HNS3_RX_PTYPE_UNUSED_ENTRY(166), 272 HNS3_RX_PTYPE_UNUSED_ENTRY(167), 273 HNS3_RX_PTYPE_UNUSED_ENTRY(168), 274 HNS3_RX_PTYPE_UNUSED_ENTRY(169), 275 HNS3_RX_PTYPE_UNUSED_ENTRY(170), 276 HNS3_RX_PTYPE_UNUSED_ENTRY(171), 277 HNS3_RX_PTYPE_UNUSED_ENTRY(172), 278 HNS3_RX_PTYPE_UNUSED_ENTRY(173), 279 HNS3_RX_PTYPE_UNUSED_ENTRY(174), 280 HNS3_RX_PTYPE_UNUSED_ENTRY(175), 281 HNS3_RX_PTYPE_UNUSED_ENTRY(176), 282 HNS3_RX_PTYPE_UNUSED_ENTRY(177), 283 HNS3_RX_PTYPE_UNUSED_ENTRY(178), 284 HNS3_RX_PTYPE_UNUSED_ENTRY(179), 285 HNS3_RX_PTYPE_UNUSED_ENTRY(180), 286 HNS3_RX_PTYPE_UNUSED_ENTRY(181), 287 HNS3_RX_PTYPE_UNUSED_ENTRY(182), 288 HNS3_RX_PTYPE_UNUSED_ENTRY(183), 289 HNS3_RX_PTYPE_UNUSED_ENTRY(184), 290 HNS3_RX_PTYPE_UNUSED_ENTRY(185), 291 HNS3_RX_PTYPE_UNUSED_ENTRY(186), 292 HNS3_RX_PTYPE_UNUSED_ENTRY(187), 293 HNS3_RX_PTYPE_UNUSED_ENTRY(188), 294 HNS3_RX_PTYPE_UNUSED_ENTRY(189), 295 HNS3_RX_PTYPE_UNUSED_ENTRY(190), 296 HNS3_RX_PTYPE_UNUSED_ENTRY(191), 297 HNS3_RX_PTYPE_UNUSED_ENTRY(192), 298 HNS3_RX_PTYPE_UNUSED_ENTRY(193), 299 HNS3_RX_PTYPE_UNUSED_ENTRY(194), 300 HNS3_RX_PTYPE_UNUSED_ENTRY(195), 301 HNS3_RX_PTYPE_UNUSED_ENTRY(196), 302 HNS3_RX_PTYPE_UNUSED_ENTRY(197), 303 HNS3_RX_PTYPE_UNUSED_ENTRY(198), 304 HNS3_RX_PTYPE_UNUSED_ENTRY(199), 305 HNS3_RX_PTYPE_UNUSED_ENTRY(200), 306 HNS3_RX_PTYPE_UNUSED_ENTRY(201), 307 HNS3_RX_PTYPE_UNUSED_ENTRY(202), 308 HNS3_RX_PTYPE_UNUSED_ENTRY(203), 309 HNS3_RX_PTYPE_UNUSED_ENTRY(204), 310 HNS3_RX_PTYPE_UNUSED_ENTRY(205), 311 HNS3_RX_PTYPE_UNUSED_ENTRY(206), 312 HNS3_RX_PTYPE_UNUSED_ENTRY(207), 313 HNS3_RX_PTYPE_UNUSED_ENTRY(208), 314 HNS3_RX_PTYPE_UNUSED_ENTRY(209), 315 HNS3_RX_PTYPE_UNUSED_ENTRY(210), 316 HNS3_RX_PTYPE_UNUSED_ENTRY(211), 317 HNS3_RX_PTYPE_UNUSED_ENTRY(212), 318 HNS3_RX_PTYPE_UNUSED_ENTRY(213), 319 HNS3_RX_PTYPE_UNUSED_ENTRY(214), 320 HNS3_RX_PTYPE_UNUSED_ENTRY(215), 321 HNS3_RX_PTYPE_UNUSED_ENTRY(216), 322 HNS3_RX_PTYPE_UNUSED_ENTRY(217), 323 HNS3_RX_PTYPE_UNUSED_ENTRY(218), 324 HNS3_RX_PTYPE_UNUSED_ENTRY(219), 325 HNS3_RX_PTYPE_UNUSED_ENTRY(220), 326 HNS3_RX_PTYPE_UNUSED_ENTRY(221), 327 HNS3_RX_PTYPE_UNUSED_ENTRY(222), 328 HNS3_RX_PTYPE_UNUSED_ENTRY(223), 329 HNS3_RX_PTYPE_UNUSED_ENTRY(224), 330 HNS3_RX_PTYPE_UNUSED_ENTRY(225), 331 HNS3_RX_PTYPE_UNUSED_ENTRY(226), 332 HNS3_RX_PTYPE_UNUSED_ENTRY(227), 333 HNS3_RX_PTYPE_UNUSED_ENTRY(228), 334 HNS3_RX_PTYPE_UNUSED_ENTRY(229), 335 HNS3_RX_PTYPE_UNUSED_ENTRY(230), 336 HNS3_RX_PTYPE_UNUSED_ENTRY(231), 337 HNS3_RX_PTYPE_UNUSED_ENTRY(232), 338 HNS3_RX_PTYPE_UNUSED_ENTRY(233), 339 HNS3_RX_PTYPE_UNUSED_ENTRY(234), 340 HNS3_RX_PTYPE_UNUSED_ENTRY(235), 341 HNS3_RX_PTYPE_UNUSED_ENTRY(236), 342 HNS3_RX_PTYPE_UNUSED_ENTRY(237), 343 HNS3_RX_PTYPE_UNUSED_ENTRY(238), 344 HNS3_RX_PTYPE_UNUSED_ENTRY(239), 345 HNS3_RX_PTYPE_UNUSED_ENTRY(240), 346 HNS3_RX_PTYPE_UNUSED_ENTRY(241), 347 HNS3_RX_PTYPE_UNUSED_ENTRY(242), 348 HNS3_RX_PTYPE_UNUSED_ENTRY(243), 349 HNS3_RX_PTYPE_UNUSED_ENTRY(244), 350 HNS3_RX_PTYPE_UNUSED_ENTRY(245), 351 HNS3_RX_PTYPE_UNUSED_ENTRY(246), 352 HNS3_RX_PTYPE_UNUSED_ENTRY(247), 353 HNS3_RX_PTYPE_UNUSED_ENTRY(248), 354 HNS3_RX_PTYPE_UNUSED_ENTRY(249), 355 HNS3_RX_PTYPE_UNUSED_ENTRY(250), 356 HNS3_RX_PTYPE_UNUSED_ENTRY(251), 357 HNS3_RX_PTYPE_UNUSED_ENTRY(252), 358 HNS3_RX_PTYPE_UNUSED_ENTRY(253), 359 HNS3_RX_PTYPE_UNUSED_ENTRY(254), 360 HNS3_RX_PTYPE_UNUSED_ENTRY(255), 361 }; 362 363 #define HNS3_INVALID_PTYPE \ 364 ARRAY_SIZE(hns3_rx_ptype_tbl) 365 366 static irqreturn_t hns3_irq_handle(int irq, void *vector) 367 { 368 struct hns3_enet_tqp_vector *tqp_vector = vector; 369 370 napi_schedule_irqoff(&tqp_vector->napi); 371 tqp_vector->event_cnt++; 372 373 return IRQ_HANDLED; 374 } 375 376 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 377 { 378 struct hns3_enet_tqp_vector *tqp_vectors; 379 unsigned int i; 380 381 for (i = 0; i < priv->vector_num; i++) { 382 tqp_vectors = &priv->tqp_vector[i]; 383 384 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 385 continue; 386 387 /* clear the affinity mask */ 388 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 389 390 /* release the irq resource */ 391 free_irq(tqp_vectors->vector_irq, tqp_vectors); 392 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 393 } 394 } 395 396 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 397 { 398 struct hns3_enet_tqp_vector *tqp_vectors; 399 int txrx_int_idx = 0; 400 int rx_int_idx = 0; 401 int tx_int_idx = 0; 402 unsigned int i; 403 int ret; 404 405 for (i = 0; i < priv->vector_num; i++) { 406 tqp_vectors = &priv->tqp_vector[i]; 407 408 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 409 continue; 410 411 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 412 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 413 "%s-%s-%s-%d", hns3_driver_name, 414 pci_name(priv->ae_handle->pdev), 415 "TxRx", txrx_int_idx++); 416 txrx_int_idx++; 417 } else if (tqp_vectors->rx_group.ring) { 418 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 419 "%s-%s-%s-%d", hns3_driver_name, 420 pci_name(priv->ae_handle->pdev), 421 "Rx", rx_int_idx++); 422 } else if (tqp_vectors->tx_group.ring) { 423 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 424 "%s-%s-%s-%d", hns3_driver_name, 425 pci_name(priv->ae_handle->pdev), 426 "Tx", tx_int_idx++); 427 } else { 428 /* Skip this unused q_vector */ 429 continue; 430 } 431 432 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 433 434 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN); 435 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 436 tqp_vectors->name, tqp_vectors); 437 if (ret) { 438 netdev_err(priv->netdev, "request irq(%d) fail\n", 439 tqp_vectors->vector_irq); 440 hns3_nic_uninit_irq(priv); 441 return ret; 442 } 443 444 irq_set_affinity_hint(tqp_vectors->vector_irq, 445 &tqp_vectors->affinity_mask); 446 447 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 448 } 449 450 return 0; 451 } 452 453 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 454 u32 mask_en) 455 { 456 writel(mask_en, tqp_vector->mask_addr); 457 } 458 459 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 460 { 461 napi_enable(&tqp_vector->napi); 462 enable_irq(tqp_vector->vector_irq); 463 464 /* enable vector */ 465 hns3_mask_vector_irq(tqp_vector, 1); 466 } 467 468 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 469 { 470 /* disable vector */ 471 hns3_mask_vector_irq(tqp_vector, 0); 472 473 disable_irq(tqp_vector->vector_irq); 474 napi_disable(&tqp_vector->napi); 475 cancel_work_sync(&tqp_vector->rx_group.dim.work); 476 cancel_work_sync(&tqp_vector->tx_group.dim.work); 477 } 478 479 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 480 u32 rl_value) 481 { 482 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 483 484 /* this defines the configuration for RL (Interrupt Rate Limiter). 485 * Rl defines rate of interrupts i.e. number of interrupts-per-second 486 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 487 */ 488 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable && 489 !tqp_vector->rx_group.coal.adapt_enable) 490 /* According to the hardware, the range of rl_reg is 491 * 0-59 and the unit is 4. 492 */ 493 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 494 495 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 496 } 497 498 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 499 u32 gl_value) 500 { 501 u32 new_val; 502 503 if (tqp_vector->rx_group.coal.unit_1us) 504 new_val = gl_value | HNS3_INT_GL_1US; 505 else 506 new_val = hns3_gl_usec_to_reg(gl_value); 507 508 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 509 } 510 511 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 512 u32 gl_value) 513 { 514 u32 new_val; 515 516 if (tqp_vector->tx_group.coal.unit_1us) 517 new_val = gl_value | HNS3_INT_GL_1US; 518 else 519 new_val = hns3_gl_usec_to_reg(gl_value); 520 521 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 522 } 523 524 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector, 525 u32 ql_value) 526 { 527 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET); 528 } 529 530 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector, 531 u32 ql_value) 532 { 533 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET); 534 } 535 536 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector, 537 struct hns3_nic_priv *priv) 538 { 539 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 540 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 541 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 542 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal; 543 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal; 544 545 tx_coal->adapt_enable = ptx_coal->adapt_enable; 546 rx_coal->adapt_enable = prx_coal->adapt_enable; 547 548 tx_coal->int_gl = ptx_coal->int_gl; 549 rx_coal->int_gl = prx_coal->int_gl; 550 551 rx_coal->flow_level = prx_coal->flow_level; 552 tx_coal->flow_level = ptx_coal->flow_level; 553 554 /* device version above V3(include V3), GL can configure 1us 555 * unit, so uses 1us unit. 556 */ 557 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) { 558 tx_coal->unit_1us = 1; 559 rx_coal->unit_1us = 1; 560 } 561 562 if (ae_dev->dev_specs.int_ql_max) { 563 tx_coal->ql_enable = 1; 564 rx_coal->ql_enable = 1; 565 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 566 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 567 tx_coal->int_ql = ptx_coal->int_ql; 568 rx_coal->int_ql = prx_coal->int_ql; 569 } 570 } 571 572 static void 573 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 574 struct hns3_nic_priv *priv) 575 { 576 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 577 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 578 struct hnae3_handle *h = priv->ae_handle; 579 580 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl); 581 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl); 582 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 583 584 if (tx_coal->ql_enable) 585 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql); 586 587 if (rx_coal->ql_enable) 588 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql); 589 } 590 591 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 592 { 593 struct hnae3_handle *h = hns3_get_handle(netdev); 594 struct hnae3_knic_private_info *kinfo = &h->kinfo; 595 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 596 unsigned int queue_size = kinfo->num_tqps; 597 int i, ret; 598 599 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) { 600 netdev_reset_tc(netdev); 601 } else { 602 ret = netdev_set_num_tc(netdev, tc_info->num_tc); 603 if (ret) { 604 netdev_err(netdev, 605 "netdev_set_num_tc fail, ret=%d!\n", ret); 606 return ret; 607 } 608 609 for (i = 0; i < HNAE3_MAX_TC; i++) { 610 if (!test_bit(i, &tc_info->tc_en)) 611 continue; 612 613 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i], 614 tc_info->tqp_offset[i]); 615 } 616 } 617 618 ret = netif_set_real_num_tx_queues(netdev, queue_size); 619 if (ret) { 620 netdev_err(netdev, 621 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret); 622 return ret; 623 } 624 625 ret = netif_set_real_num_rx_queues(netdev, queue_size); 626 if (ret) { 627 netdev_err(netdev, 628 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 629 return ret; 630 } 631 632 return 0; 633 } 634 635 u16 hns3_get_max_available_channels(struct hnae3_handle *h) 636 { 637 u16 alloc_tqps, max_rss_size, rss_size; 638 639 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 640 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc; 641 642 return min_t(u16, rss_size, max_rss_size); 643 } 644 645 static void hns3_tqp_enable(struct hnae3_queue *tqp) 646 { 647 u32 rcb_reg; 648 649 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 650 rcb_reg |= BIT(HNS3_RING_EN_B); 651 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 652 } 653 654 static void hns3_tqp_disable(struct hnae3_queue *tqp) 655 { 656 u32 rcb_reg; 657 658 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 659 rcb_reg &= ~BIT(HNS3_RING_EN_B); 660 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 661 } 662 663 static void hns3_free_rx_cpu_rmap(struct net_device *netdev) 664 { 665 #ifdef CONFIG_RFS_ACCEL 666 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 667 netdev->rx_cpu_rmap = NULL; 668 #endif 669 } 670 671 static int hns3_set_rx_cpu_rmap(struct net_device *netdev) 672 { 673 #ifdef CONFIG_RFS_ACCEL 674 struct hns3_nic_priv *priv = netdev_priv(netdev); 675 struct hns3_enet_tqp_vector *tqp_vector; 676 int i, ret; 677 678 if (!netdev->rx_cpu_rmap) { 679 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num); 680 if (!netdev->rx_cpu_rmap) 681 return -ENOMEM; 682 } 683 684 for (i = 0; i < priv->vector_num; i++) { 685 tqp_vector = &priv->tqp_vector[i]; 686 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap, 687 tqp_vector->vector_irq); 688 if (ret) { 689 hns3_free_rx_cpu_rmap(netdev); 690 return ret; 691 } 692 } 693 #endif 694 return 0; 695 } 696 697 static int hns3_nic_net_up(struct net_device *netdev) 698 { 699 struct hns3_nic_priv *priv = netdev_priv(netdev); 700 struct hnae3_handle *h = priv->ae_handle; 701 int i, j; 702 int ret; 703 704 ret = hns3_nic_reset_all_ring(h); 705 if (ret) 706 return ret; 707 708 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 709 710 /* enable the vectors */ 711 for (i = 0; i < priv->vector_num; i++) 712 hns3_vector_enable(&priv->tqp_vector[i]); 713 714 /* enable rcb */ 715 for (j = 0; j < h->kinfo.num_tqps; j++) 716 hns3_tqp_enable(h->kinfo.tqp[j]); 717 718 /* start the ae_dev */ 719 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 720 if (ret) { 721 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 722 while (j--) 723 hns3_tqp_disable(h->kinfo.tqp[j]); 724 725 for (j = i - 1; j >= 0; j--) 726 hns3_vector_disable(&priv->tqp_vector[j]); 727 } 728 729 return ret; 730 } 731 732 static void hns3_config_xps(struct hns3_nic_priv *priv) 733 { 734 int i; 735 736 for (i = 0; i < priv->vector_num; i++) { 737 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 738 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 739 740 while (ring) { 741 int ret; 742 743 ret = netif_set_xps_queue(priv->netdev, 744 &tqp_vector->affinity_mask, 745 ring->tqp->tqp_index); 746 if (ret) 747 netdev_warn(priv->netdev, 748 "set xps queue failed: %d", ret); 749 750 ring = ring->next; 751 } 752 } 753 } 754 755 static int hns3_nic_net_open(struct net_device *netdev) 756 { 757 struct hns3_nic_priv *priv = netdev_priv(netdev); 758 struct hnae3_handle *h = hns3_get_handle(netdev); 759 struct hnae3_knic_private_info *kinfo; 760 int i, ret; 761 762 if (hns3_nic_resetting(netdev)) 763 return -EBUSY; 764 765 netif_carrier_off(netdev); 766 767 ret = hns3_nic_set_real_num_queue(netdev); 768 if (ret) 769 return ret; 770 771 ret = hns3_nic_net_up(netdev); 772 if (ret) { 773 netdev_err(netdev, "net up fail, ret=%d!\n", ret); 774 return ret; 775 } 776 777 kinfo = &h->kinfo; 778 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 779 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]); 780 781 if (h->ae_algo->ops->set_timer_task) 782 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 783 784 hns3_config_xps(priv); 785 786 netif_dbg(h, drv, netdev, "net open\n"); 787 788 return 0; 789 } 790 791 static void hns3_reset_tx_queue(struct hnae3_handle *h) 792 { 793 struct net_device *ndev = h->kinfo.netdev; 794 struct hns3_nic_priv *priv = netdev_priv(ndev); 795 struct netdev_queue *dev_queue; 796 u32 i; 797 798 for (i = 0; i < h->kinfo.num_tqps; i++) { 799 dev_queue = netdev_get_tx_queue(ndev, 800 priv->ring[i].queue_index); 801 netdev_tx_reset_queue(dev_queue); 802 } 803 } 804 805 static void hns3_nic_net_down(struct net_device *netdev) 806 { 807 struct hns3_nic_priv *priv = netdev_priv(netdev); 808 struct hnae3_handle *h = hns3_get_handle(netdev); 809 const struct hnae3_ae_ops *ops; 810 int i; 811 812 /* disable vectors */ 813 for (i = 0; i < priv->vector_num; i++) 814 hns3_vector_disable(&priv->tqp_vector[i]); 815 816 /* disable rcb */ 817 for (i = 0; i < h->kinfo.num_tqps; i++) 818 hns3_tqp_disable(h->kinfo.tqp[i]); 819 820 /* stop ae_dev */ 821 ops = priv->ae_handle->ae_algo->ops; 822 if (ops->stop) 823 ops->stop(priv->ae_handle); 824 825 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 826 * during reset process, because driver may not be able 827 * to disable the ring through firmware when downing the netdev. 828 */ 829 if (!hns3_nic_resetting(netdev)) 830 hns3_clear_all_ring(priv->ae_handle, false); 831 832 hns3_reset_tx_queue(priv->ae_handle); 833 } 834 835 static int hns3_nic_net_stop(struct net_device *netdev) 836 { 837 struct hns3_nic_priv *priv = netdev_priv(netdev); 838 struct hnae3_handle *h = hns3_get_handle(netdev); 839 840 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 841 return 0; 842 843 netif_dbg(h, drv, netdev, "net stop\n"); 844 845 if (h->ae_algo->ops->set_timer_task) 846 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 847 848 netif_carrier_off(netdev); 849 netif_tx_disable(netdev); 850 851 hns3_nic_net_down(netdev); 852 853 return 0; 854 } 855 856 static int hns3_nic_uc_sync(struct net_device *netdev, 857 const unsigned char *addr) 858 { 859 struct hnae3_handle *h = hns3_get_handle(netdev); 860 861 if (h->ae_algo->ops->add_uc_addr) 862 return h->ae_algo->ops->add_uc_addr(h, addr); 863 864 return 0; 865 } 866 867 static int hns3_nic_uc_unsync(struct net_device *netdev, 868 const unsigned char *addr) 869 { 870 struct hnae3_handle *h = hns3_get_handle(netdev); 871 872 /* need ignore the request of removing device address, because 873 * we store the device address and other addresses of uc list 874 * in the function's mac filter list. 875 */ 876 if (ether_addr_equal(addr, netdev->dev_addr)) 877 return 0; 878 879 if (h->ae_algo->ops->rm_uc_addr) 880 return h->ae_algo->ops->rm_uc_addr(h, addr); 881 882 return 0; 883 } 884 885 static int hns3_nic_mc_sync(struct net_device *netdev, 886 const unsigned char *addr) 887 { 888 struct hnae3_handle *h = hns3_get_handle(netdev); 889 890 if (h->ae_algo->ops->add_mc_addr) 891 return h->ae_algo->ops->add_mc_addr(h, addr); 892 893 return 0; 894 } 895 896 static int hns3_nic_mc_unsync(struct net_device *netdev, 897 const unsigned char *addr) 898 { 899 struct hnae3_handle *h = hns3_get_handle(netdev); 900 901 if (h->ae_algo->ops->rm_mc_addr) 902 return h->ae_algo->ops->rm_mc_addr(h, addr); 903 904 return 0; 905 } 906 907 static u8 hns3_get_netdev_flags(struct net_device *netdev) 908 { 909 u8 flags = 0; 910 911 if (netdev->flags & IFF_PROMISC) 912 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 913 else if (netdev->flags & IFF_ALLMULTI) 914 flags = HNAE3_USER_MPE; 915 916 return flags; 917 } 918 919 static void hns3_nic_set_rx_mode(struct net_device *netdev) 920 { 921 struct hnae3_handle *h = hns3_get_handle(netdev); 922 u8 new_flags; 923 924 new_flags = hns3_get_netdev_flags(netdev); 925 926 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 927 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync); 928 929 /* User mode Promisc mode enable and vlan filtering is disabled to 930 * let all packets in. 931 */ 932 h->netdev_flags = new_flags; 933 hns3_request_update_promisc_mode(h); 934 } 935 936 void hns3_request_update_promisc_mode(struct hnae3_handle *handle) 937 { 938 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 939 940 if (ops->request_update_promisc_mode) 941 ops->request_update_promisc_mode(handle); 942 } 943 944 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs, 945 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes) 946 { 947 u32 l4_offset, hdr_len; 948 union l3_hdr_info l3; 949 union l4_hdr_info l4; 950 u32 l4_paylen; 951 int ret; 952 953 if (!skb_is_gso(skb)) 954 return 0; 955 956 ret = skb_cow_head(skb, 0); 957 if (unlikely(ret < 0)) 958 return ret; 959 960 l3.hdr = skb_network_header(skb); 961 l4.hdr = skb_transport_header(skb); 962 963 /* Software should clear the IPv4's checksum field when tso is 964 * needed. 965 */ 966 if (l3.v4->version == 4) 967 l3.v4->check = 0; 968 969 /* tunnel packet */ 970 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 971 SKB_GSO_GRE_CSUM | 972 SKB_GSO_UDP_TUNNEL | 973 SKB_GSO_UDP_TUNNEL_CSUM)) { 974 /* reset l3&l4 pointers from outer to inner headers */ 975 l3.hdr = skb_inner_network_header(skb); 976 l4.hdr = skb_inner_transport_header(skb); 977 978 /* Software should clear the IPv4's checksum field when 979 * tso is needed. 980 */ 981 if (l3.v4->version == 4) 982 l3.v4->check = 0; 983 } 984 985 /* normal or tunnel packet */ 986 l4_offset = l4.hdr - skb->data; 987 988 /* remove payload length from inner pseudo checksum when tso */ 989 l4_paylen = skb->len - l4_offset; 990 991 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 992 hdr_len = sizeof(*l4.udp) + l4_offset; 993 csum_replace_by_diff(&l4.udp->check, 994 (__force __wsum)htonl(l4_paylen)); 995 } else { 996 hdr_len = (l4.tcp->doff << 2) + l4_offset; 997 csum_replace_by_diff(&l4.tcp->check, 998 (__force __wsum)htonl(l4_paylen)); 999 } 1000 1001 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len; 1002 1003 /* find the txbd field values */ 1004 *paylen_fdop_ol4cs = skb->len - hdr_len; 1005 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 1006 1007 /* offload outer UDP header checksum */ 1008 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM) 1009 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1); 1010 1011 /* get MSS for TSO */ 1012 *mss = skb_shinfo(skb)->gso_size; 1013 1014 trace_hns3_tso(skb); 1015 1016 return 0; 1017 } 1018 1019 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 1020 u8 *il4_proto) 1021 { 1022 union l3_hdr_info l3; 1023 unsigned char *l4_hdr; 1024 unsigned char *exthdr; 1025 u8 l4_proto_tmp; 1026 __be16 frag_off; 1027 1028 /* find outer header point */ 1029 l3.hdr = skb_network_header(skb); 1030 l4_hdr = skb_transport_header(skb); 1031 1032 if (skb->protocol == htons(ETH_P_IPV6)) { 1033 exthdr = l3.hdr + sizeof(*l3.v6); 1034 l4_proto_tmp = l3.v6->nexthdr; 1035 if (l4_hdr != exthdr) 1036 ipv6_skip_exthdr(skb, exthdr - skb->data, 1037 &l4_proto_tmp, &frag_off); 1038 } else if (skb->protocol == htons(ETH_P_IP)) { 1039 l4_proto_tmp = l3.v4->protocol; 1040 } else { 1041 return -EINVAL; 1042 } 1043 1044 *ol4_proto = l4_proto_tmp; 1045 1046 /* tunnel packet */ 1047 if (!skb->encapsulation) { 1048 *il4_proto = 0; 1049 return 0; 1050 } 1051 1052 /* find inner header point */ 1053 l3.hdr = skb_inner_network_header(skb); 1054 l4_hdr = skb_inner_transport_header(skb); 1055 1056 if (l3.v6->version == 6) { 1057 exthdr = l3.hdr + sizeof(*l3.v6); 1058 l4_proto_tmp = l3.v6->nexthdr; 1059 if (l4_hdr != exthdr) 1060 ipv6_skip_exthdr(skb, exthdr - skb->data, 1061 &l4_proto_tmp, &frag_off); 1062 } else if (l3.v4->version == 4) { 1063 l4_proto_tmp = l3.v4->protocol; 1064 } 1065 1066 *il4_proto = l4_proto_tmp; 1067 1068 return 0; 1069 } 1070 1071 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 1072 * and it is udp packet, which has a dest port as the IANA assigned. 1073 * the hardware is expected to do the checksum offload, but the 1074 * hardware will not do the checksum offload when udp dest port is 1075 * 4789, 4790 or 6081. 1076 */ 1077 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 1078 { 1079 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 1080 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 1081 union l4_hdr_info l4; 1082 1083 /* device version above V3(include V3), the hardware can 1084 * do this checksum offload. 1085 */ 1086 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 1087 return false; 1088 1089 l4.hdr = skb_transport_header(skb); 1090 1091 if (!(!skb->encapsulation && 1092 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) || 1093 l4.udp->dest == htons(GENEVE_UDP_PORT) || 1094 l4.udp->dest == htons(4790)))) 1095 return false; 1096 1097 return true; 1098 } 1099 1100 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 1101 u32 *ol_type_vlan_len_msec) 1102 { 1103 u32 l2_len, l3_len, l4_len; 1104 unsigned char *il2_hdr; 1105 union l3_hdr_info l3; 1106 union l4_hdr_info l4; 1107 1108 l3.hdr = skb_network_header(skb); 1109 l4.hdr = skb_transport_header(skb); 1110 1111 /* compute OL2 header size, defined in 2 Bytes */ 1112 l2_len = l3.hdr - skb->data; 1113 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1); 1114 1115 /* compute OL3 header size, defined in 4 Bytes */ 1116 l3_len = l4.hdr - l3.hdr; 1117 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2); 1118 1119 il2_hdr = skb_inner_mac_header(skb); 1120 /* compute OL4 header size, defined in 4 Bytes */ 1121 l4_len = il2_hdr - l4.hdr; 1122 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2); 1123 1124 /* define outer network header type */ 1125 if (skb->protocol == htons(ETH_P_IP)) { 1126 if (skb_is_gso(skb)) 1127 hns3_set_field(*ol_type_vlan_len_msec, 1128 HNS3_TXD_OL3T_S, 1129 HNS3_OL3T_IPV4_CSUM); 1130 else 1131 hns3_set_field(*ol_type_vlan_len_msec, 1132 HNS3_TXD_OL3T_S, 1133 HNS3_OL3T_IPV4_NO_CSUM); 1134 } else if (skb->protocol == htons(ETH_P_IPV6)) { 1135 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 1136 HNS3_OL3T_IPV6); 1137 } 1138 1139 if (ol4_proto == IPPROTO_UDP) 1140 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 1141 HNS3_TUN_MAC_IN_UDP); 1142 else if (ol4_proto == IPPROTO_GRE) 1143 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 1144 HNS3_TUN_NVGRE); 1145 } 1146 1147 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 1148 u8 il4_proto, u32 *type_cs_vlan_tso, 1149 u32 *ol_type_vlan_len_msec) 1150 { 1151 unsigned char *l2_hdr = skb->data; 1152 u32 l4_proto = ol4_proto; 1153 union l4_hdr_info l4; 1154 union l3_hdr_info l3; 1155 u32 l2_len, l3_len; 1156 1157 l4.hdr = skb_transport_header(skb); 1158 l3.hdr = skb_network_header(skb); 1159 1160 /* handle encapsulation skb */ 1161 if (skb->encapsulation) { 1162 /* If this is a not UDP/GRE encapsulation skb */ 1163 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) { 1164 /* drop the skb tunnel packet if hardware don't support, 1165 * because hardware can't calculate csum when TSO. 1166 */ 1167 if (skb_is_gso(skb)) 1168 return -EDOM; 1169 1170 /* the stack computes the IP header already, 1171 * driver calculate l4 checksum when not TSO. 1172 */ 1173 return skb_checksum_help(skb); 1174 } 1175 1176 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec); 1177 1178 /* switch to inner header */ 1179 l2_hdr = skb_inner_mac_header(skb); 1180 l3.hdr = skb_inner_network_header(skb); 1181 l4.hdr = skb_inner_transport_header(skb); 1182 l4_proto = il4_proto; 1183 } 1184 1185 if (l3.v4->version == 4) { 1186 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 1187 HNS3_L3T_IPV4); 1188 1189 /* the stack computes the IP header already, the only time we 1190 * need the hardware to recompute it is in the case of TSO. 1191 */ 1192 if (skb_is_gso(skb)) 1193 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 1194 } else if (l3.v6->version == 6) { 1195 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 1196 HNS3_L3T_IPV6); 1197 } 1198 1199 /* compute inner(/normal) L2 header size, defined in 2 Bytes */ 1200 l2_len = l3.hdr - l2_hdr; 1201 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 1202 1203 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 1204 l3_len = l4.hdr - l3.hdr; 1205 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 1206 1207 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 1208 switch (l4_proto) { 1209 case IPPROTO_TCP: 1210 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1211 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1212 HNS3_L4T_TCP); 1213 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1214 l4.tcp->doff); 1215 break; 1216 case IPPROTO_UDP: 1217 if (hns3_tunnel_csum_bug(skb)) 1218 return skb_checksum_help(skb); 1219 1220 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1221 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1222 HNS3_L4T_UDP); 1223 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1224 (sizeof(struct udphdr) >> 2)); 1225 break; 1226 case IPPROTO_SCTP: 1227 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1228 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1229 HNS3_L4T_SCTP); 1230 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1231 (sizeof(struct sctphdr) >> 2)); 1232 break; 1233 default: 1234 /* drop the skb tunnel packet if hardware don't support, 1235 * because hardware can't calculate csum when TSO. 1236 */ 1237 if (skb_is_gso(skb)) 1238 return -EDOM; 1239 1240 /* the stack computes the IP header already, 1241 * driver calculate l4 checksum when not TSO. 1242 */ 1243 return skb_checksum_help(skb); 1244 } 1245 1246 return 0; 1247 } 1248 1249 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring, 1250 struct sk_buff *skb) 1251 { 1252 struct hnae3_handle *handle = tx_ring->tqp->handle; 1253 struct hnae3_ae_dev *ae_dev; 1254 struct vlan_ethhdr *vhdr; 1255 int rc; 1256 1257 if (!(skb->protocol == htons(ETH_P_8021Q) || 1258 skb_vlan_tag_present(skb))) 1259 return 0; 1260 1261 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert 1262 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it 1263 * will cause RAS error. 1264 */ 1265 ae_dev = pci_get_drvdata(handle->pdev); 1266 if (unlikely(skb_vlan_tagged_multi(skb) && 1267 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 && 1268 handle->port_base_vlan_state == 1269 HNAE3_PORT_BASE_VLAN_ENABLE)) 1270 return -EINVAL; 1271 1272 if (skb->protocol == htons(ETH_P_8021Q) && 1273 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 1274 /* When HW VLAN acceleration is turned off, and the stack 1275 * sets the protocol to 802.1q, the driver just need to 1276 * set the protocol to the encapsulated ethertype. 1277 */ 1278 skb->protocol = vlan_get_protocol(skb); 1279 return 0; 1280 } 1281 1282 if (skb_vlan_tag_present(skb)) { 1283 /* Based on hw strategy, use out_vtag in two layer tag case, 1284 * and use inner_vtag in one tag case. 1285 */ 1286 if (skb->protocol == htons(ETH_P_8021Q) && 1287 handle->port_base_vlan_state == 1288 HNAE3_PORT_BASE_VLAN_DISABLE) 1289 rc = HNS3_OUTER_VLAN_TAG; 1290 else 1291 rc = HNS3_INNER_VLAN_TAG; 1292 1293 skb->protocol = vlan_get_protocol(skb); 1294 return rc; 1295 } 1296 1297 rc = skb_cow_head(skb, 0); 1298 if (unlikely(rc < 0)) 1299 return rc; 1300 1301 vhdr = (struct vlan_ethhdr *)skb->data; 1302 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT) 1303 & VLAN_PRIO_MASK); 1304 1305 skb->protocol = vlan_get_protocol(skb); 1306 return 0; 1307 } 1308 1309 /* check if the hardware is capable of checksum offloading */ 1310 static bool hns3_check_hw_tx_csum(struct sk_buff *skb) 1311 { 1312 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 1313 1314 /* Kindly note, due to backward compatibility of the TX descriptor, 1315 * HW checksum of the non-IP packets and GSO packets is handled at 1316 * different place in the following code 1317 */ 1318 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) || 1319 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state)) 1320 return false; 1321 1322 return true; 1323 } 1324 1325 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring, 1326 struct sk_buff *skb, struct hns3_desc *desc, 1327 struct hns3_desc_cb *desc_cb) 1328 { 1329 u32 ol_type_vlan_len_msec = 0; 1330 u32 paylen_ol4cs = skb->len; 1331 u32 type_cs_vlan_tso = 0; 1332 u16 mss_hw_csum = 0; 1333 u16 inner_vtag = 0; 1334 u16 out_vtag = 0; 1335 int ret; 1336 1337 ret = hns3_handle_vtags(ring, skb); 1338 if (unlikely(ret < 0)) { 1339 u64_stats_update_begin(&ring->syncp); 1340 ring->stats.tx_vlan_err++; 1341 u64_stats_update_end(&ring->syncp); 1342 return ret; 1343 } else if (ret == HNS3_INNER_VLAN_TAG) { 1344 inner_vtag = skb_vlan_tag_get(skb); 1345 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1346 VLAN_PRIO_MASK; 1347 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1); 1348 } else if (ret == HNS3_OUTER_VLAN_TAG) { 1349 out_vtag = skb_vlan_tag_get(skb); 1350 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1351 VLAN_PRIO_MASK; 1352 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B, 1353 1); 1354 } 1355 1356 desc_cb->send_bytes = skb->len; 1357 1358 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1359 u8 ol4_proto, il4_proto; 1360 1361 if (hns3_check_hw_tx_csum(skb)) { 1362 /* set checksum start and offset, defined in 2 Bytes */ 1363 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_CSUM_START_S, 1364 skb_checksum_start_offset(skb) >> 1); 1365 hns3_set_field(ol_type_vlan_len_msec, 1366 HNS3_TXD_CSUM_OFFSET_S, 1367 skb->csum_offset >> 1); 1368 mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B); 1369 goto out_hw_tx_csum; 1370 } 1371 1372 skb_reset_mac_len(skb); 1373 1374 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1375 if (unlikely(ret < 0)) { 1376 u64_stats_update_begin(&ring->syncp); 1377 ring->stats.tx_l4_proto_err++; 1378 u64_stats_update_end(&ring->syncp); 1379 return ret; 1380 } 1381 1382 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto, 1383 &type_cs_vlan_tso, 1384 &ol_type_vlan_len_msec); 1385 if (unlikely(ret < 0)) { 1386 u64_stats_update_begin(&ring->syncp); 1387 ring->stats.tx_l2l3l4_err++; 1388 u64_stats_update_end(&ring->syncp); 1389 return ret; 1390 } 1391 1392 ret = hns3_set_tso(skb, &paylen_ol4cs, &mss_hw_csum, 1393 &type_cs_vlan_tso, &desc_cb->send_bytes); 1394 if (unlikely(ret < 0)) { 1395 u64_stats_update_begin(&ring->syncp); 1396 ring->stats.tx_tso_err++; 1397 u64_stats_update_end(&ring->syncp); 1398 return ret; 1399 } 1400 } 1401 1402 out_hw_tx_csum: 1403 /* Set txbd */ 1404 desc->tx.ol_type_vlan_len_msec = 1405 cpu_to_le32(ol_type_vlan_len_msec); 1406 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso); 1407 desc->tx.paylen_ol4cs = cpu_to_le32(paylen_ol4cs); 1408 desc->tx.mss_hw_csum = cpu_to_le16(mss_hw_csum); 1409 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1410 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1411 1412 return 0; 1413 } 1414 1415 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 1416 unsigned int size, enum hns_desc_type type) 1417 { 1418 #define HNS3_LIKELY_BD_NUM 1 1419 1420 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1421 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1422 struct device *dev = ring_to_dev(ring); 1423 skb_frag_t *frag; 1424 unsigned int frag_buf_num; 1425 int k, sizeoflast; 1426 dma_addr_t dma; 1427 1428 if (type == DESC_TYPE_FRAGLIST_SKB || 1429 type == DESC_TYPE_SKB) { 1430 struct sk_buff *skb = (struct sk_buff *)priv; 1431 1432 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1433 } else { 1434 frag = (skb_frag_t *)priv; 1435 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1436 } 1437 1438 if (unlikely(dma_mapping_error(dev, dma))) { 1439 u64_stats_update_begin(&ring->syncp); 1440 ring->stats.sw_err_cnt++; 1441 u64_stats_update_end(&ring->syncp); 1442 return -ENOMEM; 1443 } 1444 1445 desc_cb->priv = priv; 1446 desc_cb->length = size; 1447 desc_cb->dma = dma; 1448 desc_cb->type = type; 1449 1450 if (likely(size <= HNS3_MAX_BD_SIZE)) { 1451 desc->addr = cpu_to_le64(dma); 1452 desc->tx.send_size = cpu_to_le16(size); 1453 desc->tx.bdtp_fe_sc_vld_ra_ri = 1454 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1455 1456 trace_hns3_tx_desc(ring, ring->next_to_use); 1457 ring_ptr_move_fw(ring, next_to_use); 1458 return HNS3_LIKELY_BD_NUM; 1459 } 1460 1461 frag_buf_num = hns3_tx_bd_count(size); 1462 sizeoflast = size % HNS3_MAX_BD_SIZE; 1463 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1464 1465 /* When frag size is bigger than hardware limit, split this frag */ 1466 for (k = 0; k < frag_buf_num; k++) { 1467 /* now, fill the descriptor */ 1468 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1469 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1470 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1471 desc->tx.bdtp_fe_sc_vld_ra_ri = 1472 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1473 1474 trace_hns3_tx_desc(ring, ring->next_to_use); 1475 /* move ring pointer to next */ 1476 ring_ptr_move_fw(ring, next_to_use); 1477 1478 desc = &ring->desc[ring->next_to_use]; 1479 } 1480 1481 return frag_buf_num; 1482 } 1483 1484 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1485 unsigned int bd_num) 1486 { 1487 unsigned int size; 1488 int i; 1489 1490 size = skb_headlen(skb); 1491 while (size > HNS3_MAX_BD_SIZE) { 1492 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1493 size -= HNS3_MAX_BD_SIZE; 1494 1495 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1496 return bd_num; 1497 } 1498 1499 if (size) { 1500 bd_size[bd_num++] = size; 1501 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1502 return bd_num; 1503 } 1504 1505 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1506 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1507 size = skb_frag_size(frag); 1508 if (!size) 1509 continue; 1510 1511 while (size > HNS3_MAX_BD_SIZE) { 1512 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1513 size -= HNS3_MAX_BD_SIZE; 1514 1515 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1516 return bd_num; 1517 } 1518 1519 bd_size[bd_num++] = size; 1520 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1521 return bd_num; 1522 } 1523 1524 return bd_num; 1525 } 1526 1527 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1528 u8 max_non_tso_bd_num, unsigned int bd_num, 1529 unsigned int recursion_level) 1530 { 1531 #define HNS3_MAX_RECURSION_LEVEL 24 1532 1533 struct sk_buff *frag_skb; 1534 1535 /* If the total len is within the max bd limit */ 1536 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level && 1537 !skb_has_frag_list(skb) && 1538 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num)) 1539 return skb_shinfo(skb)->nr_frags + 1U; 1540 1541 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL)) 1542 return UINT_MAX; 1543 1544 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num); 1545 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM) 1546 return bd_num; 1547 1548 skb_walk_frags(skb, frag_skb) { 1549 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num, 1550 bd_num, recursion_level + 1); 1551 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1552 return bd_num; 1553 } 1554 1555 return bd_num; 1556 } 1557 1558 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb) 1559 { 1560 if (!skb->encapsulation) 1561 return skb_transport_offset(skb) + tcp_hdrlen(skb); 1562 1563 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb); 1564 } 1565 1566 /* HW need every continuous max_non_tso_bd_num buffer data to be larger 1567 * than MSS, we simplify it by ensuring skb_headlen + the first continuous 1568 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss, 1569 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger 1570 * than MSS except the last max_non_tso_bd_num - 1 frags. 1571 */ 1572 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size, 1573 unsigned int bd_num, u8 max_non_tso_bd_num) 1574 { 1575 unsigned int tot_len = 0; 1576 int i; 1577 1578 for (i = 0; i < max_non_tso_bd_num - 1U; i++) 1579 tot_len += bd_size[i]; 1580 1581 /* ensure the first max_non_tso_bd_num frags is greater than 1582 * mss + header 1583 */ 1584 if (tot_len + bd_size[max_non_tso_bd_num - 1U] < 1585 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb)) 1586 return true; 1587 1588 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater 1589 * than mss except the last one. 1590 */ 1591 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) { 1592 tot_len -= bd_size[i]; 1593 tot_len += bd_size[i + max_non_tso_bd_num - 1U]; 1594 1595 if (tot_len < skb_shinfo(skb)->gso_size) 1596 return true; 1597 } 1598 1599 return false; 1600 } 1601 1602 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size) 1603 { 1604 int i; 1605 1606 for (i = 0; i < MAX_SKB_FRAGS; i++) 1607 size[i] = skb_frag_size(&shinfo->frags[i]); 1608 } 1609 1610 static int hns3_skb_linearize(struct hns3_enet_ring *ring, 1611 struct sk_buff *skb, 1612 u8 max_non_tso_bd_num, 1613 unsigned int bd_num) 1614 { 1615 /* 'bd_num == UINT_MAX' means the skb' fraglist has a 1616 * recursion level of over HNS3_MAX_RECURSION_LEVEL. 1617 */ 1618 if (bd_num == UINT_MAX) { 1619 u64_stats_update_begin(&ring->syncp); 1620 ring->stats.over_max_recursion++; 1621 u64_stats_update_end(&ring->syncp); 1622 return -ENOMEM; 1623 } 1624 1625 /* The skb->len has exceeded the hw limitation, linearization 1626 * will not help. 1627 */ 1628 if (skb->len > HNS3_MAX_TSO_SIZE || 1629 (!skb_is_gso(skb) && skb->len > 1630 HNS3_MAX_NON_TSO_SIZE(max_non_tso_bd_num))) { 1631 u64_stats_update_begin(&ring->syncp); 1632 ring->stats.hw_limitation++; 1633 u64_stats_update_end(&ring->syncp); 1634 return -ENOMEM; 1635 } 1636 1637 if (__skb_linearize(skb)) { 1638 u64_stats_update_begin(&ring->syncp); 1639 ring->stats.sw_err_cnt++; 1640 u64_stats_update_end(&ring->syncp); 1641 return -ENOMEM; 1642 } 1643 1644 return 0; 1645 } 1646 1647 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring, 1648 struct net_device *netdev, 1649 struct sk_buff *skb) 1650 { 1651 struct hns3_nic_priv *priv = netdev_priv(netdev); 1652 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num; 1653 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U]; 1654 unsigned int bd_num; 1655 1656 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0); 1657 if (unlikely(bd_num > max_non_tso_bd_num)) { 1658 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) && 1659 !hns3_skb_need_linearized(skb, bd_size, bd_num, 1660 max_non_tso_bd_num)) { 1661 trace_hns3_over_max_bd(skb); 1662 goto out; 1663 } 1664 1665 if (hns3_skb_linearize(ring, skb, max_non_tso_bd_num, 1666 bd_num)) 1667 return -ENOMEM; 1668 1669 bd_num = hns3_tx_bd_count(skb->len); 1670 1671 u64_stats_update_begin(&ring->syncp); 1672 ring->stats.tx_copy++; 1673 u64_stats_update_end(&ring->syncp); 1674 } 1675 1676 out: 1677 if (likely(ring_space(ring) >= bd_num)) 1678 return bd_num; 1679 1680 netif_stop_subqueue(netdev, ring->queue_index); 1681 smp_mb(); /* Memory barrier before checking ring_space */ 1682 1683 /* Start queue in case hns3_clean_tx_ring has just made room 1684 * available and has not seen the queue stopped state performed 1685 * by netif_stop_subqueue above. 1686 */ 1687 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) && 1688 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 1689 netif_start_subqueue(netdev, ring->queue_index); 1690 return bd_num; 1691 } 1692 1693 u64_stats_update_begin(&ring->syncp); 1694 ring->stats.tx_busy++; 1695 u64_stats_update_end(&ring->syncp); 1696 1697 return -EBUSY; 1698 } 1699 1700 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1701 { 1702 struct device *dev = ring_to_dev(ring); 1703 unsigned int i; 1704 1705 for (i = 0; i < ring->desc_num; i++) { 1706 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1707 1708 memset(desc, 0, sizeof(*desc)); 1709 1710 /* check if this is where we started */ 1711 if (ring->next_to_use == next_to_use_orig) 1712 break; 1713 1714 /* rollback one */ 1715 ring_ptr_move_bw(ring, next_to_use); 1716 1717 if (!ring->desc_cb[ring->next_to_use].dma) 1718 continue; 1719 1720 /* unmap the descriptor dma address */ 1721 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB || 1722 ring->desc_cb[ring->next_to_use].type == 1723 DESC_TYPE_FRAGLIST_SKB) 1724 dma_unmap_single(dev, 1725 ring->desc_cb[ring->next_to_use].dma, 1726 ring->desc_cb[ring->next_to_use].length, 1727 DMA_TO_DEVICE); 1728 else if (ring->desc_cb[ring->next_to_use].length) 1729 dma_unmap_page(dev, 1730 ring->desc_cb[ring->next_to_use].dma, 1731 ring->desc_cb[ring->next_to_use].length, 1732 DMA_TO_DEVICE); 1733 1734 ring->desc_cb[ring->next_to_use].length = 0; 1735 ring->desc_cb[ring->next_to_use].dma = 0; 1736 ring->desc_cb[ring->next_to_use].type = DESC_TYPE_UNKNOWN; 1737 } 1738 } 1739 1740 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring, 1741 struct sk_buff *skb, enum hns_desc_type type) 1742 { 1743 unsigned int size = skb_headlen(skb); 1744 struct sk_buff *frag_skb; 1745 int i, ret, bd_num = 0; 1746 1747 if (size) { 1748 ret = hns3_fill_desc(ring, skb, size, type); 1749 if (unlikely(ret < 0)) 1750 return ret; 1751 1752 bd_num += ret; 1753 } 1754 1755 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1756 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1757 1758 size = skb_frag_size(frag); 1759 if (!size) 1760 continue; 1761 1762 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE); 1763 if (unlikely(ret < 0)) 1764 return ret; 1765 1766 bd_num += ret; 1767 } 1768 1769 skb_walk_frags(skb, frag_skb) { 1770 ret = hns3_fill_skb_to_desc(ring, frag_skb, 1771 DESC_TYPE_FRAGLIST_SKB); 1772 if (unlikely(ret < 0)) 1773 return ret; 1774 1775 bd_num += ret; 1776 } 1777 1778 return bd_num; 1779 } 1780 1781 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num, 1782 bool doorbell) 1783 { 1784 ring->pending_buf += num; 1785 1786 if (!doorbell) { 1787 u64_stats_update_begin(&ring->syncp); 1788 ring->stats.tx_more++; 1789 u64_stats_update_end(&ring->syncp); 1790 return; 1791 } 1792 1793 if (!ring->pending_buf) 1794 return; 1795 1796 writel(ring->pending_buf, 1797 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG); 1798 ring->pending_buf = 0; 1799 WRITE_ONCE(ring->last_to_use, ring->next_to_use); 1800 } 1801 1802 static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb, 1803 struct hns3_desc *desc) 1804 { 1805 struct hnae3_handle *h = hns3_get_handle(netdev); 1806 1807 if (!(h->ae_algo->ops->set_tx_hwts_info && 1808 h->ae_algo->ops->set_tx_hwts_info(h, skb))) 1809 return; 1810 1811 desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B)); 1812 } 1813 1814 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1815 { 1816 struct hns3_nic_priv *priv = netdev_priv(netdev); 1817 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping]; 1818 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1819 struct netdev_queue *dev_queue; 1820 int pre_ntu, next_to_use_head; 1821 bool doorbell; 1822 int ret; 1823 1824 /* Hardware can only handle short frames above 32 bytes */ 1825 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) { 1826 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 1827 1828 u64_stats_update_begin(&ring->syncp); 1829 ring->stats.sw_err_cnt++; 1830 u64_stats_update_end(&ring->syncp); 1831 1832 return NETDEV_TX_OK; 1833 } 1834 1835 /* Prefetch the data used later */ 1836 prefetch(skb->data); 1837 1838 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb); 1839 if (unlikely(ret <= 0)) { 1840 if (ret == -EBUSY) { 1841 hns3_tx_doorbell(ring, 0, true); 1842 return NETDEV_TX_BUSY; 1843 } 1844 1845 hns3_rl_err(netdev, "xmit error: %d!\n", ret); 1846 goto out_err_tx_ok; 1847 } 1848 1849 next_to_use_head = ring->next_to_use; 1850 1851 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use], 1852 desc_cb); 1853 if (unlikely(ret < 0)) 1854 goto fill_err; 1855 1856 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is 1857 * zero, which is unlikely, and 'ret > 0' means how many tx desc 1858 * need to be notified to the hw. 1859 */ 1860 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB); 1861 if (unlikely(ret <= 0)) 1862 goto fill_err; 1863 1864 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) : 1865 (ring->desc_num - 1); 1866 1867 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 1868 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]); 1869 1870 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |= 1871 cpu_to_le16(BIT(HNS3_TXD_FE_B)); 1872 trace_hns3_tx_desc(ring, pre_ntu); 1873 1874 skb_tx_timestamp(skb); 1875 1876 /* Complete translate all packets */ 1877 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index); 1878 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes, 1879 netdev_xmit_more()); 1880 hns3_tx_doorbell(ring, ret, doorbell); 1881 1882 return NETDEV_TX_OK; 1883 1884 fill_err: 1885 hns3_clear_desc(ring, next_to_use_head); 1886 1887 out_err_tx_ok: 1888 dev_kfree_skb_any(skb); 1889 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 1890 return NETDEV_TX_OK; 1891 } 1892 1893 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1894 { 1895 struct hnae3_handle *h = hns3_get_handle(netdev); 1896 struct sockaddr *mac_addr = p; 1897 int ret; 1898 1899 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1900 return -EADDRNOTAVAIL; 1901 1902 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1903 netdev_info(netdev, "already using mac address %pM\n", 1904 mac_addr->sa_data); 1905 return 0; 1906 } 1907 1908 /* For VF device, if there is a perm_addr, then the user will not 1909 * be allowed to change the address. 1910 */ 1911 if (!hns3_is_phys_func(h->pdev) && 1912 !is_zero_ether_addr(netdev->perm_addr)) { 1913 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n", 1914 netdev->perm_addr, mac_addr->sa_data); 1915 return -EPERM; 1916 } 1917 1918 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1919 if (ret) { 1920 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1921 return ret; 1922 } 1923 1924 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1925 1926 return 0; 1927 } 1928 1929 static int hns3_nic_do_ioctl(struct net_device *netdev, 1930 struct ifreq *ifr, int cmd) 1931 { 1932 struct hnae3_handle *h = hns3_get_handle(netdev); 1933 1934 if (!netif_running(netdev)) 1935 return -EINVAL; 1936 1937 if (!h->ae_algo->ops->do_ioctl) 1938 return -EOPNOTSUPP; 1939 1940 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 1941 } 1942 1943 static int hns3_nic_set_features(struct net_device *netdev, 1944 netdev_features_t features) 1945 { 1946 netdev_features_t changed = netdev->features ^ features; 1947 struct hns3_nic_priv *priv = netdev_priv(netdev); 1948 struct hnae3_handle *h = priv->ae_handle; 1949 bool enable; 1950 int ret; 1951 1952 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 1953 enable = !!(features & NETIF_F_GRO_HW); 1954 ret = h->ae_algo->ops->set_gro_en(h, enable); 1955 if (ret) 1956 return ret; 1957 } 1958 1959 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1960 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1961 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 1962 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 1963 if (ret) 1964 return ret; 1965 } 1966 1967 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 1968 enable = !!(features & NETIF_F_NTUPLE); 1969 h->ae_algo->ops->enable_fd(h, enable); 1970 } 1971 1972 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) && 1973 h->ae_algo->ops->cls_flower_active(h)) { 1974 netdev_err(netdev, 1975 "there are offloaded TC filters active, cannot disable HW TC offload"); 1976 return -EINVAL; 1977 } 1978 1979 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 1980 h->ae_algo->ops->enable_vlan_filter) { 1981 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER); 1982 ret = h->ae_algo->ops->enable_vlan_filter(h, enable); 1983 if (ret) 1984 return ret; 1985 } 1986 1987 netdev->features = features; 1988 return 0; 1989 } 1990 1991 static netdev_features_t hns3_features_check(struct sk_buff *skb, 1992 struct net_device *dev, 1993 netdev_features_t features) 1994 { 1995 #define HNS3_MAX_HDR_LEN 480U 1996 #define HNS3_MAX_L4_HDR_LEN 60U 1997 1998 size_t len; 1999 2000 if (skb->ip_summed != CHECKSUM_PARTIAL) 2001 return features; 2002 2003 if (skb->encapsulation) 2004 len = skb_inner_transport_header(skb) - skb->data; 2005 else 2006 len = skb_transport_header(skb) - skb->data; 2007 2008 /* Assume L4 is 60 byte as TCP is the only protocol with a 2009 * a flexible value, and it's max len is 60 bytes. 2010 */ 2011 len += HNS3_MAX_L4_HDR_LEN; 2012 2013 /* Hardware only supports checksum on the skb with a max header 2014 * len of 480 bytes. 2015 */ 2016 if (len > HNS3_MAX_HDR_LEN) 2017 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2018 2019 return features; 2020 } 2021 2022 static void hns3_nic_get_stats64(struct net_device *netdev, 2023 struct rtnl_link_stats64 *stats) 2024 { 2025 struct hns3_nic_priv *priv = netdev_priv(netdev); 2026 int queue_num = priv->ae_handle->kinfo.num_tqps; 2027 struct hnae3_handle *handle = priv->ae_handle; 2028 struct hns3_enet_ring *ring; 2029 u64 rx_length_errors = 0; 2030 u64 rx_crc_errors = 0; 2031 u64 rx_multicast = 0; 2032 unsigned int start; 2033 u64 tx_errors = 0; 2034 u64 rx_errors = 0; 2035 unsigned int idx; 2036 u64 tx_bytes = 0; 2037 u64 rx_bytes = 0; 2038 u64 tx_pkts = 0; 2039 u64 rx_pkts = 0; 2040 u64 tx_drop = 0; 2041 u64 rx_drop = 0; 2042 2043 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 2044 return; 2045 2046 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 2047 2048 for (idx = 0; idx < queue_num; idx++) { 2049 /* fetch the tx stats */ 2050 ring = &priv->ring[idx]; 2051 do { 2052 start = u64_stats_fetch_begin_irq(&ring->syncp); 2053 tx_bytes += ring->stats.tx_bytes; 2054 tx_pkts += ring->stats.tx_pkts; 2055 tx_drop += ring->stats.sw_err_cnt; 2056 tx_drop += ring->stats.tx_vlan_err; 2057 tx_drop += ring->stats.tx_l4_proto_err; 2058 tx_drop += ring->stats.tx_l2l3l4_err; 2059 tx_drop += ring->stats.tx_tso_err; 2060 tx_drop += ring->stats.over_max_recursion; 2061 tx_drop += ring->stats.hw_limitation; 2062 tx_errors += ring->stats.sw_err_cnt; 2063 tx_errors += ring->stats.tx_vlan_err; 2064 tx_errors += ring->stats.tx_l4_proto_err; 2065 tx_errors += ring->stats.tx_l2l3l4_err; 2066 tx_errors += ring->stats.tx_tso_err; 2067 tx_errors += ring->stats.over_max_recursion; 2068 tx_errors += ring->stats.hw_limitation; 2069 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 2070 2071 /* fetch the rx stats */ 2072 ring = &priv->ring[idx + queue_num]; 2073 do { 2074 start = u64_stats_fetch_begin_irq(&ring->syncp); 2075 rx_bytes += ring->stats.rx_bytes; 2076 rx_pkts += ring->stats.rx_pkts; 2077 rx_drop += ring->stats.l2_err; 2078 rx_errors += ring->stats.l2_err; 2079 rx_errors += ring->stats.l3l4_csum_err; 2080 rx_crc_errors += ring->stats.l2_err; 2081 rx_multicast += ring->stats.rx_multicast; 2082 rx_length_errors += ring->stats.err_pkt_len; 2083 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 2084 } 2085 2086 stats->tx_bytes = tx_bytes; 2087 stats->tx_packets = tx_pkts; 2088 stats->rx_bytes = rx_bytes; 2089 stats->rx_packets = rx_pkts; 2090 2091 stats->rx_errors = rx_errors; 2092 stats->multicast = rx_multicast; 2093 stats->rx_length_errors = rx_length_errors; 2094 stats->rx_crc_errors = rx_crc_errors; 2095 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 2096 2097 stats->tx_errors = tx_errors; 2098 stats->rx_dropped = rx_drop; 2099 stats->tx_dropped = tx_drop; 2100 stats->collisions = netdev->stats.collisions; 2101 stats->rx_over_errors = netdev->stats.rx_over_errors; 2102 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 2103 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 2104 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 2105 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 2106 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 2107 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 2108 stats->tx_window_errors = netdev->stats.tx_window_errors; 2109 stats->rx_compressed = netdev->stats.rx_compressed; 2110 stats->tx_compressed = netdev->stats.tx_compressed; 2111 } 2112 2113 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 2114 { 2115 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 2116 struct hnae3_knic_private_info *kinfo; 2117 u8 tc = mqprio_qopt->qopt.num_tc; 2118 u16 mode = mqprio_qopt->mode; 2119 u8 hw = mqprio_qopt->qopt.hw; 2120 struct hnae3_handle *h; 2121 2122 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 2123 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 2124 return -EOPNOTSUPP; 2125 2126 if (tc > HNAE3_MAX_TC) 2127 return -EINVAL; 2128 2129 if (!netdev) 2130 return -EINVAL; 2131 2132 h = hns3_get_handle(netdev); 2133 kinfo = &h->kinfo; 2134 2135 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc); 2136 2137 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 2138 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP; 2139 } 2140 2141 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv, 2142 struct flow_cls_offload *flow) 2143 { 2144 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid); 2145 struct hnae3_handle *h = hns3_get_handle(priv->netdev); 2146 2147 switch (flow->command) { 2148 case FLOW_CLS_REPLACE: 2149 if (h->ae_algo->ops->add_cls_flower) 2150 return h->ae_algo->ops->add_cls_flower(h, flow, tc); 2151 break; 2152 case FLOW_CLS_DESTROY: 2153 if (h->ae_algo->ops->del_cls_flower) 2154 return h->ae_algo->ops->del_cls_flower(h, flow); 2155 break; 2156 default: 2157 break; 2158 } 2159 2160 return -EOPNOTSUPP; 2161 } 2162 2163 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2164 void *cb_priv) 2165 { 2166 struct hns3_nic_priv *priv = cb_priv; 2167 2168 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data)) 2169 return -EOPNOTSUPP; 2170 2171 switch (type) { 2172 case TC_SETUP_CLSFLOWER: 2173 return hns3_setup_tc_cls_flower(priv, type_data); 2174 default: 2175 return -EOPNOTSUPP; 2176 } 2177 } 2178 2179 static LIST_HEAD(hns3_block_cb_list); 2180 2181 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 2182 void *type_data) 2183 { 2184 struct hns3_nic_priv *priv = netdev_priv(dev); 2185 int ret; 2186 2187 switch (type) { 2188 case TC_SETUP_QDISC_MQPRIO: 2189 ret = hns3_setup_tc(dev, type_data); 2190 break; 2191 case TC_SETUP_BLOCK: 2192 ret = flow_block_cb_setup_simple(type_data, 2193 &hns3_block_cb_list, 2194 hns3_setup_tc_block_cb, 2195 priv, priv, true); 2196 break; 2197 default: 2198 return -EOPNOTSUPP; 2199 } 2200 2201 return ret; 2202 } 2203 2204 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 2205 __be16 proto, u16 vid) 2206 { 2207 struct hnae3_handle *h = hns3_get_handle(netdev); 2208 int ret = -EIO; 2209 2210 if (h->ae_algo->ops->set_vlan_filter) 2211 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 2212 2213 return ret; 2214 } 2215 2216 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 2217 __be16 proto, u16 vid) 2218 { 2219 struct hnae3_handle *h = hns3_get_handle(netdev); 2220 int ret = -EIO; 2221 2222 if (h->ae_algo->ops->set_vlan_filter) 2223 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 2224 2225 return ret; 2226 } 2227 2228 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2229 u8 qos, __be16 vlan_proto) 2230 { 2231 struct hnae3_handle *h = hns3_get_handle(netdev); 2232 int ret = -EIO; 2233 2234 netif_dbg(h, drv, netdev, 2235 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n", 2236 vf, vlan, qos, ntohs(vlan_proto)); 2237 2238 if (h->ae_algo->ops->set_vf_vlan_filter) 2239 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 2240 qos, vlan_proto); 2241 2242 return ret; 2243 } 2244 2245 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable) 2246 { 2247 struct hnae3_handle *handle = hns3_get_handle(netdev); 2248 2249 if (hns3_nic_resetting(netdev)) 2250 return -EBUSY; 2251 2252 if (!handle->ae_algo->ops->set_vf_spoofchk) 2253 return -EOPNOTSUPP; 2254 2255 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable); 2256 } 2257 2258 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable) 2259 { 2260 struct hnae3_handle *handle = hns3_get_handle(netdev); 2261 2262 if (!handle->ae_algo->ops->set_vf_trust) 2263 return -EOPNOTSUPP; 2264 2265 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable); 2266 } 2267 2268 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 2269 { 2270 struct hnae3_handle *h = hns3_get_handle(netdev); 2271 int ret; 2272 2273 if (hns3_nic_resetting(netdev)) 2274 return -EBUSY; 2275 2276 if (!h->ae_algo->ops->set_mtu) 2277 return -EOPNOTSUPP; 2278 2279 netif_dbg(h, drv, netdev, 2280 "change mtu from %u to %d\n", netdev->mtu, new_mtu); 2281 2282 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 2283 if (ret) 2284 netdev_err(netdev, "failed to change MTU in hardware %d\n", 2285 ret); 2286 else 2287 netdev->mtu = new_mtu; 2288 2289 return ret; 2290 } 2291 2292 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 2293 { 2294 struct hns3_nic_priv *priv = netdev_priv(ndev); 2295 struct hnae3_handle *h = hns3_get_handle(ndev); 2296 struct hns3_enet_ring *tx_ring; 2297 struct napi_struct *napi; 2298 int timeout_queue = 0; 2299 int hw_head, hw_tail; 2300 int fbd_num, fbd_oft; 2301 int ebd_num, ebd_oft; 2302 int bd_num, bd_err; 2303 int ring_en, tc; 2304 int i; 2305 2306 /* Find the stopped queue the same way the stack does */ 2307 for (i = 0; i < ndev->num_tx_queues; i++) { 2308 struct netdev_queue *q; 2309 unsigned long trans_start; 2310 2311 q = netdev_get_tx_queue(ndev, i); 2312 trans_start = q->trans_start; 2313 if (netif_xmit_stopped(q) && 2314 time_after(jiffies, 2315 (trans_start + ndev->watchdog_timeo))) { 2316 timeout_queue = i; 2317 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n", 2318 q->state, 2319 jiffies_to_msecs(jiffies - trans_start)); 2320 break; 2321 } 2322 } 2323 2324 if (i == ndev->num_tx_queues) { 2325 netdev_info(ndev, 2326 "no netdev TX timeout queue found, timeout count: %llu\n", 2327 priv->tx_timeout_count); 2328 return false; 2329 } 2330 2331 priv->tx_timeout_count++; 2332 2333 tx_ring = &priv->ring[timeout_queue]; 2334 napi = &tx_ring->tqp_vector->napi; 2335 2336 netdev_info(ndev, 2337 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n", 2338 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use, 2339 tx_ring->next_to_clean, napi->state); 2340 2341 netdev_info(ndev, 2342 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n", 2343 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes, 2344 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf); 2345 2346 netdev_info(ndev, 2347 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n", 2348 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more, 2349 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy); 2350 2351 /* When mac received many pause frames continuous, it's unable to send 2352 * packets, which may cause tx timeout 2353 */ 2354 if (h->ae_algo->ops->get_mac_stats) { 2355 struct hns3_mac_stats mac_stats; 2356 2357 h->ae_algo->ops->get_mac_stats(h, &mac_stats); 2358 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n", 2359 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt); 2360 } 2361 2362 hw_head = readl_relaxed(tx_ring->tqp->io_base + 2363 HNS3_RING_TX_RING_HEAD_REG); 2364 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 2365 HNS3_RING_TX_RING_TAIL_REG); 2366 fbd_num = readl_relaxed(tx_ring->tqp->io_base + 2367 HNS3_RING_TX_RING_FBDNUM_REG); 2368 fbd_oft = readl_relaxed(tx_ring->tqp->io_base + 2369 HNS3_RING_TX_RING_OFFSET_REG); 2370 ebd_num = readl_relaxed(tx_ring->tqp->io_base + 2371 HNS3_RING_TX_RING_EBDNUM_REG); 2372 ebd_oft = readl_relaxed(tx_ring->tqp->io_base + 2373 HNS3_RING_TX_RING_EBD_OFFSET_REG); 2374 bd_num = readl_relaxed(tx_ring->tqp->io_base + 2375 HNS3_RING_TX_RING_BD_NUM_REG); 2376 bd_err = readl_relaxed(tx_ring->tqp->io_base + 2377 HNS3_RING_TX_RING_BD_ERR_REG); 2378 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG); 2379 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG); 2380 2381 netdev_info(ndev, 2382 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n", 2383 bd_num, hw_head, hw_tail, bd_err, 2384 readl(tx_ring->tqp_vector->mask_addr)); 2385 netdev_info(ndev, 2386 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n", 2387 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft); 2388 2389 return true; 2390 } 2391 2392 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue) 2393 { 2394 struct hns3_nic_priv *priv = netdev_priv(ndev); 2395 struct hnae3_handle *h = priv->ae_handle; 2396 2397 if (!hns3_get_tx_timeo_queue_info(ndev)) 2398 return; 2399 2400 /* request the reset, and let the hclge to determine 2401 * which reset level should be done 2402 */ 2403 if (h->ae_algo->ops->reset_event) 2404 h->ae_algo->ops->reset_event(h->pdev, h); 2405 } 2406 2407 #ifdef CONFIG_RFS_ACCEL 2408 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 2409 u16 rxq_index, u32 flow_id) 2410 { 2411 struct hnae3_handle *h = hns3_get_handle(dev); 2412 struct flow_keys fkeys; 2413 2414 if (!h->ae_algo->ops->add_arfs_entry) 2415 return -EOPNOTSUPP; 2416 2417 if (skb->encapsulation) 2418 return -EPROTONOSUPPORT; 2419 2420 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0)) 2421 return -EPROTONOSUPPORT; 2422 2423 if ((fkeys.basic.n_proto != htons(ETH_P_IP) && 2424 fkeys.basic.n_proto != htons(ETH_P_IPV6)) || 2425 (fkeys.basic.ip_proto != IPPROTO_TCP && 2426 fkeys.basic.ip_proto != IPPROTO_UDP)) 2427 return -EPROTONOSUPPORT; 2428 2429 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys); 2430 } 2431 #endif 2432 2433 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf, 2434 struct ifla_vf_info *ivf) 2435 { 2436 struct hnae3_handle *h = hns3_get_handle(ndev); 2437 2438 if (!h->ae_algo->ops->get_vf_config) 2439 return -EOPNOTSUPP; 2440 2441 return h->ae_algo->ops->get_vf_config(h, vf, ivf); 2442 } 2443 2444 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf, 2445 int link_state) 2446 { 2447 struct hnae3_handle *h = hns3_get_handle(ndev); 2448 2449 if (!h->ae_algo->ops->set_vf_link_state) 2450 return -EOPNOTSUPP; 2451 2452 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state); 2453 } 2454 2455 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf, 2456 int min_tx_rate, int max_tx_rate) 2457 { 2458 struct hnae3_handle *h = hns3_get_handle(ndev); 2459 2460 if (!h->ae_algo->ops->set_vf_rate) 2461 return -EOPNOTSUPP; 2462 2463 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate, 2464 false); 2465 } 2466 2467 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) 2468 { 2469 struct hnae3_handle *h = hns3_get_handle(netdev); 2470 2471 if (!h->ae_algo->ops->set_vf_mac) 2472 return -EOPNOTSUPP; 2473 2474 if (is_multicast_ether_addr(mac)) { 2475 netdev_err(netdev, 2476 "Invalid MAC:%pM specified. Could not set MAC\n", 2477 mac); 2478 return -EINVAL; 2479 } 2480 2481 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac); 2482 } 2483 2484 static const struct net_device_ops hns3_nic_netdev_ops = { 2485 .ndo_open = hns3_nic_net_open, 2486 .ndo_stop = hns3_nic_net_stop, 2487 .ndo_start_xmit = hns3_nic_net_xmit, 2488 .ndo_tx_timeout = hns3_nic_net_timeout, 2489 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 2490 .ndo_do_ioctl = hns3_nic_do_ioctl, 2491 .ndo_change_mtu = hns3_nic_change_mtu, 2492 .ndo_set_features = hns3_nic_set_features, 2493 .ndo_features_check = hns3_features_check, 2494 .ndo_get_stats64 = hns3_nic_get_stats64, 2495 .ndo_setup_tc = hns3_nic_setup_tc, 2496 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 2497 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 2498 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 2499 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 2500 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk, 2501 .ndo_set_vf_trust = hns3_set_vf_trust, 2502 #ifdef CONFIG_RFS_ACCEL 2503 .ndo_rx_flow_steer = hns3_rx_flow_steer, 2504 #endif 2505 .ndo_get_vf_config = hns3_nic_get_vf_config, 2506 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state, 2507 .ndo_set_vf_rate = hns3_nic_set_vf_rate, 2508 .ndo_set_vf_mac = hns3_nic_set_vf_mac, 2509 }; 2510 2511 bool hns3_is_phys_func(struct pci_dev *pdev) 2512 { 2513 u32 dev_id = pdev->device; 2514 2515 switch (dev_id) { 2516 case HNAE3_DEV_ID_GE: 2517 case HNAE3_DEV_ID_25GE: 2518 case HNAE3_DEV_ID_25GE_RDMA: 2519 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 2520 case HNAE3_DEV_ID_50GE_RDMA: 2521 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 2522 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 2523 case HNAE3_DEV_ID_200G_RDMA: 2524 return true; 2525 case HNAE3_DEV_ID_VF: 2526 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF: 2527 return false; 2528 default: 2529 dev_warn(&pdev->dev, "un-recognized pci device-id %u", 2530 dev_id); 2531 } 2532 2533 return false; 2534 } 2535 2536 static void hns3_disable_sriov(struct pci_dev *pdev) 2537 { 2538 /* If our VFs are assigned we cannot shut down SR-IOV 2539 * without causing issues, so just leave the hardware 2540 * available but disabled 2541 */ 2542 if (pci_vfs_assigned(pdev)) { 2543 dev_warn(&pdev->dev, 2544 "disabling driver while VFs are assigned\n"); 2545 return; 2546 } 2547 2548 pci_disable_sriov(pdev); 2549 } 2550 2551 /* hns3_probe - Device initialization routine 2552 * @pdev: PCI device information struct 2553 * @ent: entry in hns3_pci_tbl 2554 * 2555 * hns3_probe initializes a PF identified by a pci_dev structure. 2556 * The OS initialization, configuring of the PF private structure, 2557 * and a hardware reset occur. 2558 * 2559 * Returns 0 on success, negative on failure 2560 */ 2561 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2562 { 2563 struct hnae3_ae_dev *ae_dev; 2564 int ret; 2565 2566 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL); 2567 if (!ae_dev) 2568 return -ENOMEM; 2569 2570 ae_dev->pdev = pdev; 2571 ae_dev->flag = ent->driver_data; 2572 pci_set_drvdata(pdev, ae_dev); 2573 2574 ret = hnae3_register_ae_dev(ae_dev); 2575 if (ret) 2576 pci_set_drvdata(pdev, NULL); 2577 2578 return ret; 2579 } 2580 2581 /* hns3_remove - Device removal routine 2582 * @pdev: PCI device information struct 2583 */ 2584 static void hns3_remove(struct pci_dev *pdev) 2585 { 2586 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2587 2588 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 2589 hns3_disable_sriov(pdev); 2590 2591 hnae3_unregister_ae_dev(ae_dev); 2592 pci_set_drvdata(pdev, NULL); 2593 } 2594 2595 /** 2596 * hns3_pci_sriov_configure 2597 * @pdev: pointer to a pci_dev structure 2598 * @num_vfs: number of VFs to allocate 2599 * 2600 * Enable or change the number of VFs. Called when the user updates the number 2601 * of VFs in sysfs. 2602 **/ 2603 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 2604 { 2605 int ret; 2606 2607 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 2608 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 2609 return -EINVAL; 2610 } 2611 2612 if (num_vfs) { 2613 ret = pci_enable_sriov(pdev, num_vfs); 2614 if (ret) 2615 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 2616 else 2617 return num_vfs; 2618 } else if (!pci_vfs_assigned(pdev)) { 2619 pci_disable_sriov(pdev); 2620 } else { 2621 dev_warn(&pdev->dev, 2622 "Unable to free VFs because some are assigned to VMs.\n"); 2623 } 2624 2625 return 0; 2626 } 2627 2628 static void hns3_shutdown(struct pci_dev *pdev) 2629 { 2630 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2631 2632 hnae3_unregister_ae_dev(ae_dev); 2633 pci_set_drvdata(pdev, NULL); 2634 2635 if (system_state == SYSTEM_POWER_OFF) 2636 pci_set_power_state(pdev, PCI_D3hot); 2637 } 2638 2639 static int __maybe_unused hns3_suspend(struct device *dev) 2640 { 2641 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev); 2642 2643 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) { 2644 dev_info(dev, "Begin to suspend.\n"); 2645 if (ae_dev->ops && ae_dev->ops->reset_prepare) 2646 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET); 2647 } 2648 2649 return 0; 2650 } 2651 2652 static int __maybe_unused hns3_resume(struct device *dev) 2653 { 2654 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev); 2655 2656 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) { 2657 dev_info(dev, "Begin to resume.\n"); 2658 if (ae_dev->ops && ae_dev->ops->reset_done) 2659 ae_dev->ops->reset_done(ae_dev); 2660 } 2661 2662 return 0; 2663 } 2664 2665 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 2666 pci_channel_state_t state) 2667 { 2668 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2669 pci_ers_result_t ret; 2670 2671 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state); 2672 2673 if (state == pci_channel_io_perm_failure) 2674 return PCI_ERS_RESULT_DISCONNECT; 2675 2676 if (!ae_dev || !ae_dev->ops) { 2677 dev_err(&pdev->dev, 2678 "Can't recover - error happened before device initialized\n"); 2679 return PCI_ERS_RESULT_NONE; 2680 } 2681 2682 if (ae_dev->ops->handle_hw_ras_error) 2683 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 2684 else 2685 return PCI_ERS_RESULT_NONE; 2686 2687 return ret; 2688 } 2689 2690 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 2691 { 2692 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2693 const struct hnae3_ae_ops *ops; 2694 enum hnae3_reset_type reset_type; 2695 struct device *dev = &pdev->dev; 2696 2697 if (!ae_dev || !ae_dev->ops) 2698 return PCI_ERS_RESULT_NONE; 2699 2700 ops = ae_dev->ops; 2701 /* request the reset */ 2702 if (ops->reset_event && ops->get_reset_level && 2703 ops->set_default_reset_request) { 2704 if (ae_dev->hw_err_reset_req) { 2705 reset_type = ops->get_reset_level(ae_dev, 2706 &ae_dev->hw_err_reset_req); 2707 ops->set_default_reset_request(ae_dev, reset_type); 2708 dev_info(dev, "requesting reset due to PCI error\n"); 2709 ops->reset_event(pdev, NULL); 2710 } 2711 2712 return PCI_ERS_RESULT_RECOVERED; 2713 } 2714 2715 return PCI_ERS_RESULT_DISCONNECT; 2716 } 2717 2718 static void hns3_reset_prepare(struct pci_dev *pdev) 2719 { 2720 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2721 2722 dev_info(&pdev->dev, "FLR prepare\n"); 2723 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare) 2724 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET); 2725 } 2726 2727 static void hns3_reset_done(struct pci_dev *pdev) 2728 { 2729 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2730 2731 dev_info(&pdev->dev, "FLR done\n"); 2732 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done) 2733 ae_dev->ops->reset_done(ae_dev); 2734 } 2735 2736 static const struct pci_error_handlers hns3_err_handler = { 2737 .error_detected = hns3_error_detected, 2738 .slot_reset = hns3_slot_reset, 2739 .reset_prepare = hns3_reset_prepare, 2740 .reset_done = hns3_reset_done, 2741 }; 2742 2743 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume); 2744 2745 static struct pci_driver hns3_driver = { 2746 .name = hns3_driver_name, 2747 .id_table = hns3_pci_tbl, 2748 .probe = hns3_probe, 2749 .remove = hns3_remove, 2750 .shutdown = hns3_shutdown, 2751 .driver.pm = &hns3_pm_ops, 2752 .sriov_configure = hns3_pci_sriov_configure, 2753 .err_handler = &hns3_err_handler, 2754 }; 2755 2756 /* set default feature to hns3 */ 2757 static void hns3_set_default_feature(struct net_device *netdev) 2758 { 2759 struct hnae3_handle *h = hns3_get_handle(netdev); 2760 struct pci_dev *pdev = h->pdev; 2761 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2762 2763 netdev->priv_flags |= IFF_UNICAST_FLT; 2764 2765 netdev->hw_enc_features |= NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2766 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2767 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2768 NETIF_F_SCTP_CRC | NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST; 2769 2770 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 2771 2772 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 2773 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2774 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2775 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2776 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2777 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 2778 2779 netdev->vlan_features |= NETIF_F_RXCSUM | 2780 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 2781 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2782 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2783 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 2784 2785 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 2786 NETIF_F_HW_VLAN_CTAG_RX | 2787 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2788 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2789 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2790 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 2791 2792 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 2793 netdev->hw_features |= NETIF_F_GRO_HW; 2794 netdev->features |= NETIF_F_GRO_HW; 2795 2796 if (!(h->flags & HNAE3_SUPPORT_VF)) { 2797 netdev->hw_features |= NETIF_F_NTUPLE; 2798 netdev->features |= NETIF_F_NTUPLE; 2799 } 2800 } 2801 2802 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps)) { 2803 netdev->hw_features |= NETIF_F_GSO_UDP_L4; 2804 netdev->features |= NETIF_F_GSO_UDP_L4; 2805 netdev->vlan_features |= NETIF_F_GSO_UDP_L4; 2806 netdev->hw_enc_features |= NETIF_F_GSO_UDP_L4; 2807 } 2808 2809 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) { 2810 netdev->hw_features |= NETIF_F_HW_CSUM; 2811 netdev->features |= NETIF_F_HW_CSUM; 2812 netdev->vlan_features |= NETIF_F_HW_CSUM; 2813 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 2814 } else { 2815 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2816 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2817 netdev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2818 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2819 } 2820 2821 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps)) { 2822 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 2823 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 2824 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 2825 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 2826 } 2827 2828 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) { 2829 netdev->hw_features |= NETIF_F_HW_TC; 2830 netdev->features |= NETIF_F_HW_TC; 2831 } 2832 2833 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 2834 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2835 } 2836 2837 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 2838 struct hns3_desc_cb *cb) 2839 { 2840 unsigned int order = hns3_page_order(ring); 2841 struct page *p; 2842 2843 p = dev_alloc_pages(order); 2844 if (!p) 2845 return -ENOMEM; 2846 2847 cb->priv = p; 2848 cb->page_offset = 0; 2849 cb->reuse_flag = 0; 2850 cb->buf = page_address(p); 2851 cb->length = hns3_page_size(ring); 2852 cb->type = DESC_TYPE_PAGE; 2853 page_ref_add(p, USHRT_MAX - 1); 2854 cb->pagecnt_bias = USHRT_MAX; 2855 2856 return 0; 2857 } 2858 2859 static void hns3_free_buffer(struct hns3_enet_ring *ring, 2860 struct hns3_desc_cb *cb, int budget) 2861 { 2862 if (cb->type == DESC_TYPE_SKB) 2863 napi_consume_skb(cb->priv, budget); 2864 else if (!HNAE3_IS_TX_RING(ring) && cb->pagecnt_bias) 2865 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias); 2866 memset(cb, 0, sizeof(*cb)); 2867 } 2868 2869 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 2870 { 2871 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 2872 cb->length, ring_to_dma_dir(ring)); 2873 2874 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 2875 return -EIO; 2876 2877 return 0; 2878 } 2879 2880 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 2881 struct hns3_desc_cb *cb) 2882 { 2883 if (cb->type == DESC_TYPE_SKB || cb->type == DESC_TYPE_FRAGLIST_SKB) 2884 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 2885 ring_to_dma_dir(ring)); 2886 else if (cb->length) 2887 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 2888 ring_to_dma_dir(ring)); 2889 } 2890 2891 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 2892 { 2893 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2894 ring->desc[i].addr = 0; 2895 } 2896 2897 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i, 2898 int budget) 2899 { 2900 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 2901 2902 if (!ring->desc_cb[i].dma) 2903 return; 2904 2905 hns3_buffer_detach(ring, i); 2906 hns3_free_buffer(ring, cb, budget); 2907 } 2908 2909 static void hns3_free_buffers(struct hns3_enet_ring *ring) 2910 { 2911 int i; 2912 2913 for (i = 0; i < ring->desc_num; i++) 2914 hns3_free_buffer_detach(ring, i, 0); 2915 } 2916 2917 /* free desc along with its attached buffer */ 2918 static void hns3_free_desc(struct hns3_enet_ring *ring) 2919 { 2920 int size = ring->desc_num * sizeof(ring->desc[0]); 2921 2922 hns3_free_buffers(ring); 2923 2924 if (ring->desc) { 2925 dma_free_coherent(ring_to_dev(ring), size, 2926 ring->desc, ring->desc_dma_addr); 2927 ring->desc = NULL; 2928 } 2929 } 2930 2931 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 2932 { 2933 int size = ring->desc_num * sizeof(ring->desc[0]); 2934 2935 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 2936 &ring->desc_dma_addr, GFP_KERNEL); 2937 if (!ring->desc) 2938 return -ENOMEM; 2939 2940 return 0; 2941 } 2942 2943 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring, 2944 struct hns3_desc_cb *cb) 2945 { 2946 int ret; 2947 2948 ret = hns3_alloc_buffer(ring, cb); 2949 if (ret) 2950 goto out; 2951 2952 ret = hns3_map_buffer(ring, cb); 2953 if (ret) 2954 goto out_with_buf; 2955 2956 return 0; 2957 2958 out_with_buf: 2959 hns3_free_buffer(ring, cb, 0); 2960 out: 2961 return ret; 2962 } 2963 2964 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i) 2965 { 2966 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]); 2967 2968 if (ret) 2969 return ret; 2970 2971 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2972 2973 return 0; 2974 } 2975 2976 /* Allocate memory for raw pkg, and map with dma */ 2977 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 2978 { 2979 int i, j, ret; 2980 2981 for (i = 0; i < ring->desc_num; i++) { 2982 ret = hns3_alloc_and_attach_buffer(ring, i); 2983 if (ret) 2984 goto out_buffer_fail; 2985 } 2986 2987 return 0; 2988 2989 out_buffer_fail: 2990 for (j = i - 1; j >= 0; j--) 2991 hns3_free_buffer_detach(ring, j, 0); 2992 return ret; 2993 } 2994 2995 /* detach a in-used buffer and replace with a reserved one */ 2996 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 2997 struct hns3_desc_cb *res_cb) 2998 { 2999 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 3000 ring->desc_cb[i] = *res_cb; 3001 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 3002 ring->desc[i].rx.bd_base_info = 0; 3003 } 3004 3005 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 3006 { 3007 ring->desc_cb[i].reuse_flag = 0; 3008 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 3009 ring->desc_cb[i].page_offset); 3010 ring->desc[i].rx.bd_base_info = 0; 3011 3012 dma_sync_single_for_device(ring_to_dev(ring), 3013 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset, 3014 hns3_buf_size(ring), 3015 DMA_FROM_DEVICE); 3016 } 3017 3018 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, 3019 int *bytes, int *pkts, int budget) 3020 { 3021 /* pair with ring->last_to_use update in hns3_tx_doorbell(), 3022 * smp_store_release() is not used in hns3_tx_doorbell() because 3023 * the doorbell operation already have the needed barrier operation. 3024 */ 3025 int ltu = smp_load_acquire(&ring->last_to_use); 3026 int ntc = ring->next_to_clean; 3027 struct hns3_desc_cb *desc_cb; 3028 bool reclaimed = false; 3029 struct hns3_desc *desc; 3030 3031 while (ltu != ntc) { 3032 desc = &ring->desc[ntc]; 3033 3034 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) & 3035 BIT(HNS3_TXD_VLD_B)) 3036 break; 3037 3038 desc_cb = &ring->desc_cb[ntc]; 3039 3040 if (desc_cb->type == DESC_TYPE_SKB) { 3041 (*pkts)++; 3042 (*bytes) += desc_cb->send_bytes; 3043 } 3044 3045 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */ 3046 hns3_free_buffer_detach(ring, ntc, budget); 3047 3048 if (++ntc == ring->desc_num) 3049 ntc = 0; 3050 3051 /* Issue prefetch for next Tx descriptor */ 3052 prefetch(&ring->desc_cb[ntc]); 3053 reclaimed = true; 3054 } 3055 3056 if (unlikely(!reclaimed)) 3057 return false; 3058 3059 /* This smp_store_release() pairs with smp_load_acquire() in 3060 * ring_space called by hns3_nic_net_xmit. 3061 */ 3062 smp_store_release(&ring->next_to_clean, ntc); 3063 return true; 3064 } 3065 3066 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget) 3067 { 3068 struct net_device *netdev = ring_to_netdev(ring); 3069 struct hns3_nic_priv *priv = netdev_priv(netdev); 3070 struct netdev_queue *dev_queue; 3071 int bytes, pkts; 3072 3073 bytes = 0; 3074 pkts = 0; 3075 3076 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget))) 3077 return; 3078 3079 ring->tqp_vector->tx_group.total_bytes += bytes; 3080 ring->tqp_vector->tx_group.total_packets += pkts; 3081 3082 u64_stats_update_begin(&ring->syncp); 3083 ring->stats.tx_bytes += bytes; 3084 ring->stats.tx_pkts += pkts; 3085 u64_stats_update_end(&ring->syncp); 3086 3087 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 3088 netdev_tx_completed_queue(dev_queue, pkts, bytes); 3089 3090 if (unlikely(netif_carrier_ok(netdev) && 3091 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) { 3092 /* Make sure that anybody stopping the queue after this 3093 * sees the new next_to_clean. 3094 */ 3095 smp_mb(); 3096 if (netif_tx_queue_stopped(dev_queue) && 3097 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 3098 netif_tx_wake_queue(dev_queue); 3099 ring->stats.restart_queue++; 3100 } 3101 } 3102 } 3103 3104 static int hns3_desc_unused(struct hns3_enet_ring *ring) 3105 { 3106 int ntc = ring->next_to_clean; 3107 int ntu = ring->next_to_use; 3108 3109 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 3110 } 3111 3112 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, 3113 int cleand_count) 3114 { 3115 struct hns3_desc_cb *desc_cb; 3116 struct hns3_desc_cb res_cbs; 3117 int i, ret; 3118 3119 for (i = 0; i < cleand_count; i++) { 3120 desc_cb = &ring->desc_cb[ring->next_to_use]; 3121 if (desc_cb->reuse_flag) { 3122 u64_stats_update_begin(&ring->syncp); 3123 ring->stats.reuse_pg_cnt++; 3124 u64_stats_update_end(&ring->syncp); 3125 3126 hns3_reuse_buffer(ring, ring->next_to_use); 3127 } else { 3128 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 3129 if (ret) { 3130 u64_stats_update_begin(&ring->syncp); 3131 ring->stats.sw_err_cnt++; 3132 u64_stats_update_end(&ring->syncp); 3133 3134 hns3_rl_err(ring_to_netdev(ring), 3135 "alloc rx buffer failed: %d\n", 3136 ret); 3137 break; 3138 } 3139 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 3140 3141 u64_stats_update_begin(&ring->syncp); 3142 ring->stats.non_reuse_pg++; 3143 u64_stats_update_end(&ring->syncp); 3144 } 3145 3146 ring_ptr_move_fw(ring, next_to_use); 3147 } 3148 3149 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 3150 } 3151 3152 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb) 3153 { 3154 return (page_count(cb->priv) - cb->pagecnt_bias) == 1; 3155 } 3156 3157 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 3158 struct hns3_enet_ring *ring, int pull_len, 3159 struct hns3_desc_cb *desc_cb) 3160 { 3161 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 3162 int size = le16_to_cpu(desc->rx.size); 3163 u32 truesize = hns3_buf_size(ring); 3164 3165 desc_cb->pagecnt_bias--; 3166 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 3167 size - pull_len, truesize); 3168 3169 /* Avoid re-using remote and pfmemalloc pages, or the stack is still 3170 * using the page when page_offset rollback to zero, flag default 3171 * unreuse 3172 */ 3173 if (!dev_page_is_reusable(desc_cb->priv) || 3174 (!desc_cb->page_offset && !hns3_can_reuse_page(desc_cb))) { 3175 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias); 3176 return; 3177 } 3178 3179 /* Move offset up to the next cache line */ 3180 desc_cb->page_offset += truesize; 3181 3182 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) { 3183 desc_cb->reuse_flag = 1; 3184 } else if (hns3_can_reuse_page(desc_cb)) { 3185 desc_cb->reuse_flag = 1; 3186 desc_cb->page_offset = 0; 3187 } else if (desc_cb->pagecnt_bias) { 3188 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias); 3189 return; 3190 } 3191 3192 if (unlikely(!desc_cb->pagecnt_bias)) { 3193 page_ref_add(desc_cb->priv, USHRT_MAX); 3194 desc_cb->pagecnt_bias = USHRT_MAX; 3195 } 3196 } 3197 3198 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) 3199 { 3200 __be16 type = skb->protocol; 3201 struct tcphdr *th; 3202 int depth = 0; 3203 3204 while (eth_type_vlan(type)) { 3205 struct vlan_hdr *vh; 3206 3207 if ((depth + VLAN_HLEN) > skb_headlen(skb)) 3208 return -EFAULT; 3209 3210 vh = (struct vlan_hdr *)(skb->data + depth); 3211 type = vh->h_vlan_encapsulated_proto; 3212 depth += VLAN_HLEN; 3213 } 3214 3215 skb_set_network_header(skb, depth); 3216 3217 if (type == htons(ETH_P_IP)) { 3218 const struct iphdr *iph = ip_hdr(skb); 3219 3220 depth += sizeof(struct iphdr); 3221 skb_set_transport_header(skb, depth); 3222 th = tcp_hdr(skb); 3223 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr, 3224 iph->daddr, 0); 3225 } else if (type == htons(ETH_P_IPV6)) { 3226 const struct ipv6hdr *iph = ipv6_hdr(skb); 3227 3228 depth += sizeof(struct ipv6hdr); 3229 skb_set_transport_header(skb, depth); 3230 th = tcp_hdr(skb); 3231 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr, 3232 &iph->daddr, 0); 3233 } else { 3234 hns3_rl_err(skb->dev, 3235 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n", 3236 be16_to_cpu(type), depth); 3237 return -EFAULT; 3238 } 3239 3240 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 3241 if (th->cwr) 3242 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 3243 3244 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B)) 3245 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID; 3246 3247 skb->csum_start = (unsigned char *)th - skb->head; 3248 skb->csum_offset = offsetof(struct tcphdr, check); 3249 skb->ip_summed = CHECKSUM_PARTIAL; 3250 3251 trace_hns3_gro(skb); 3252 3253 return 0; 3254 } 3255 3256 static bool hns3_checksum_complete(struct hns3_enet_ring *ring, 3257 struct sk_buff *skb, u32 ptype, u16 csum) 3258 { 3259 if (ptype == HNS3_INVALID_PTYPE || 3260 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE) 3261 return false; 3262 3263 u64_stats_update_begin(&ring->syncp); 3264 ring->stats.csum_complete++; 3265 u64_stats_update_end(&ring->syncp); 3266 skb->ip_summed = CHECKSUM_COMPLETE; 3267 skb->csum = csum_unfold((__force __sum16)csum); 3268 3269 return true; 3270 } 3271 3272 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info, 3273 u32 ol_info, u32 ptype) 3274 { 3275 int l3_type, l4_type; 3276 int ol4_type; 3277 3278 if (ptype != HNS3_INVALID_PTYPE) { 3279 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level; 3280 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed; 3281 3282 return; 3283 } 3284 3285 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M, 3286 HNS3_RXD_OL4ID_S); 3287 switch (ol4_type) { 3288 case HNS3_OL4_TYPE_MAC_IN_UDP: 3289 case HNS3_OL4_TYPE_NVGRE: 3290 skb->csum_level = 1; 3291 fallthrough; 3292 case HNS3_OL4_TYPE_NO_TUN: 3293 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 3294 HNS3_RXD_L3ID_S); 3295 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 3296 HNS3_RXD_L4ID_S); 3297 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 3298 if ((l3_type == HNS3_L3_TYPE_IPV4 || 3299 l3_type == HNS3_L3_TYPE_IPV6) && 3300 (l4_type == HNS3_L4_TYPE_UDP || 3301 l4_type == HNS3_L4_TYPE_TCP || 3302 l4_type == HNS3_L4_TYPE_SCTP)) 3303 skb->ip_summed = CHECKSUM_UNNECESSARY; 3304 break; 3305 default: 3306 break; 3307 } 3308 } 3309 3310 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 3311 u32 l234info, u32 bd_base_info, u32 ol_info, 3312 u16 csum) 3313 { 3314 struct net_device *netdev = ring_to_netdev(ring); 3315 struct hns3_nic_priv *priv = netdev_priv(netdev); 3316 u32 ptype = HNS3_INVALID_PTYPE; 3317 3318 skb->ip_summed = CHECKSUM_NONE; 3319 3320 skb_checksum_none_assert(skb); 3321 3322 if (!(netdev->features & NETIF_F_RXCSUM)) 3323 return; 3324 3325 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) 3326 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, 3327 HNS3_RXD_PTYPE_S); 3328 3329 if (hns3_checksum_complete(ring, skb, ptype, csum)) 3330 return; 3331 3332 /* check if hardware has done checksum */ 3333 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 3334 return; 3335 3336 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | 3337 BIT(HNS3_RXD_OL3E_B) | 3338 BIT(HNS3_RXD_OL4E_B)))) { 3339 u64_stats_update_begin(&ring->syncp); 3340 ring->stats.l3l4_csum_err++; 3341 u64_stats_update_end(&ring->syncp); 3342 3343 return; 3344 } 3345 3346 hns3_rx_handle_csum(skb, l234info, ol_info, ptype); 3347 } 3348 3349 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 3350 { 3351 if (skb_has_frag_list(skb)) 3352 napi_gro_flush(&ring->tqp_vector->napi, false); 3353 3354 napi_gro_receive(&ring->tqp_vector->napi, skb); 3355 } 3356 3357 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 3358 struct hns3_desc *desc, u32 l234info, 3359 u16 *vlan_tag) 3360 { 3361 struct hnae3_handle *handle = ring->tqp->handle; 3362 struct pci_dev *pdev = ring->tqp->handle->pdev; 3363 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3364 3365 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) { 3366 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3367 if (!(*vlan_tag & VLAN_VID_MASK)) 3368 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3369 3370 return (*vlan_tag != 0); 3371 } 3372 3373 #define HNS3_STRP_OUTER_VLAN 0x1 3374 #define HNS3_STRP_INNER_VLAN 0x2 3375 #define HNS3_STRP_BOTH 0x3 3376 3377 /* Hardware always insert VLAN tag into RX descriptor when 3378 * remove the tag from packet, driver needs to determine 3379 * reporting which tag to stack. 3380 */ 3381 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 3382 HNS3_RXD_STRP_TAGP_S)) { 3383 case HNS3_STRP_OUTER_VLAN: 3384 if (handle->port_base_vlan_state != 3385 HNAE3_PORT_BASE_VLAN_DISABLE) 3386 return false; 3387 3388 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3389 return true; 3390 case HNS3_STRP_INNER_VLAN: 3391 if (handle->port_base_vlan_state != 3392 HNAE3_PORT_BASE_VLAN_DISABLE) 3393 return false; 3394 3395 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3396 return true; 3397 case HNS3_STRP_BOTH: 3398 if (handle->port_base_vlan_state == 3399 HNAE3_PORT_BASE_VLAN_DISABLE) 3400 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3401 else 3402 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3403 3404 return true; 3405 default: 3406 return false; 3407 } 3408 } 3409 3410 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring) 3411 { 3412 ring->desc[ring->next_to_clean].rx.bd_base_info &= 3413 cpu_to_le32(~BIT(HNS3_RXD_VLD_B)); 3414 ring->next_to_clean += 1; 3415 3416 if (unlikely(ring->next_to_clean == ring->desc_num)) 3417 ring->next_to_clean = 0; 3418 } 3419 3420 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length, 3421 unsigned char *va) 3422 { 3423 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 3424 struct net_device *netdev = ring_to_netdev(ring); 3425 struct sk_buff *skb; 3426 3427 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 3428 skb = ring->skb; 3429 if (unlikely(!skb)) { 3430 hns3_rl_err(netdev, "alloc rx skb fail\n"); 3431 3432 u64_stats_update_begin(&ring->syncp); 3433 ring->stats.sw_err_cnt++; 3434 u64_stats_update_end(&ring->syncp); 3435 3436 return -ENOMEM; 3437 } 3438 3439 trace_hns3_rx_desc(ring); 3440 prefetchw(skb->data); 3441 3442 ring->pending_buf = 1; 3443 ring->frag_num = 0; 3444 ring->tail_skb = NULL; 3445 if (length <= HNS3_RX_HEAD_SIZE) { 3446 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 3447 3448 /* We can reuse buffer as-is, just make sure it is reusable */ 3449 if (dev_page_is_reusable(desc_cb->priv)) 3450 desc_cb->reuse_flag = 1; 3451 else /* This page cannot be reused so discard it */ 3452 __page_frag_cache_drain(desc_cb->priv, 3453 desc_cb->pagecnt_bias); 3454 3455 hns3_rx_ring_move_fw(ring); 3456 return 0; 3457 } 3458 u64_stats_update_begin(&ring->syncp); 3459 ring->stats.seg_pkt_cnt++; 3460 u64_stats_update_end(&ring->syncp); 3461 3462 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE); 3463 __skb_put(skb, ring->pull_len); 3464 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 3465 desc_cb); 3466 hns3_rx_ring_move_fw(ring); 3467 3468 return 0; 3469 } 3470 3471 static int hns3_add_frag(struct hns3_enet_ring *ring) 3472 { 3473 struct sk_buff *skb = ring->skb; 3474 struct sk_buff *head_skb = skb; 3475 struct sk_buff *new_skb; 3476 struct hns3_desc_cb *desc_cb; 3477 struct hns3_desc *desc; 3478 u32 bd_base_info; 3479 3480 do { 3481 desc = &ring->desc[ring->next_to_clean]; 3482 desc_cb = &ring->desc_cb[ring->next_to_clean]; 3483 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3484 /* make sure HW write desc complete */ 3485 dma_rmb(); 3486 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 3487 return -ENXIO; 3488 3489 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 3490 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0); 3491 if (unlikely(!new_skb)) { 3492 hns3_rl_err(ring_to_netdev(ring), 3493 "alloc rx fraglist skb fail\n"); 3494 return -ENXIO; 3495 } 3496 ring->frag_num = 0; 3497 3498 if (ring->tail_skb) { 3499 ring->tail_skb->next = new_skb; 3500 ring->tail_skb = new_skb; 3501 } else { 3502 skb_shinfo(skb)->frag_list = new_skb; 3503 ring->tail_skb = new_skb; 3504 } 3505 } 3506 3507 if (ring->tail_skb) { 3508 head_skb->truesize += hns3_buf_size(ring); 3509 head_skb->data_len += le16_to_cpu(desc->rx.size); 3510 head_skb->len += le16_to_cpu(desc->rx.size); 3511 skb = ring->tail_skb; 3512 } 3513 3514 dma_sync_single_for_cpu(ring_to_dev(ring), 3515 desc_cb->dma + desc_cb->page_offset, 3516 hns3_buf_size(ring), 3517 DMA_FROM_DEVICE); 3518 3519 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 3520 trace_hns3_rx_desc(ring); 3521 hns3_rx_ring_move_fw(ring); 3522 ring->pending_buf++; 3523 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B))); 3524 3525 return 0; 3526 } 3527 3528 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring, 3529 struct sk_buff *skb, u32 l234info, 3530 u32 bd_base_info, u32 ol_info, u16 csum) 3531 { 3532 struct net_device *netdev = ring_to_netdev(ring); 3533 struct hns3_nic_priv *priv = netdev_priv(netdev); 3534 u32 l3_type; 3535 3536 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 3537 HNS3_RXD_GRO_SIZE_M, 3538 HNS3_RXD_GRO_SIZE_S); 3539 /* if there is no HW GRO, do not set gro params */ 3540 if (!skb_shinfo(skb)->gso_size) { 3541 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info, 3542 csum); 3543 return 0; 3544 } 3545 3546 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info, 3547 HNS3_RXD_GRO_COUNT_M, 3548 HNS3_RXD_GRO_COUNT_S); 3549 3550 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) { 3551 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, 3552 HNS3_RXD_PTYPE_S); 3553 3554 l3_type = hns3_rx_ptype_tbl[ptype].l3_type; 3555 } else { 3556 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 3557 HNS3_RXD_L3ID_S); 3558 } 3559 3560 if (l3_type == HNS3_L3_TYPE_IPV4) 3561 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 3562 else if (l3_type == HNS3_L3_TYPE_IPV6) 3563 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 3564 else 3565 return -EFAULT; 3566 3567 return hns3_gro_complete(skb, l234info); 3568 } 3569 3570 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 3571 struct sk_buff *skb, u32 rss_hash) 3572 { 3573 struct hnae3_handle *handle = ring->tqp->handle; 3574 enum pkt_hash_types rss_type; 3575 3576 if (rss_hash) 3577 rss_type = handle->kinfo.rss_type; 3578 else 3579 rss_type = PKT_HASH_TYPE_NONE; 3580 3581 skb_set_hash(skb, rss_hash, rss_type); 3582 } 3583 3584 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb) 3585 { 3586 struct net_device *netdev = ring_to_netdev(ring); 3587 enum hns3_pkt_l2t_type l2_frame_type; 3588 u32 bd_base_info, l234info, ol_info; 3589 struct hns3_desc *desc; 3590 unsigned int len; 3591 int pre_ntc, ret; 3592 u16 csum; 3593 3594 /* bdinfo handled below is only valid on the last BD of the 3595 * current packet, and ring->next_to_clean indicates the first 3596 * descriptor of next packet, so need - 1 below. 3597 */ 3598 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) : 3599 (ring->desc_num - 1); 3600 desc = &ring->desc[pre_ntc]; 3601 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3602 l234info = le32_to_cpu(desc->rx.l234_info); 3603 ol_info = le32_to_cpu(desc->rx.ol_info); 3604 csum = le16_to_cpu(desc->csum); 3605 3606 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) { 3607 struct hnae3_handle *h = hns3_get_handle(netdev); 3608 u32 nsec = le32_to_cpu(desc->ts_nsec); 3609 u32 sec = le32_to_cpu(desc->ts_sec); 3610 3611 if (h->ae_algo->ops->get_rx_hwts) 3612 h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec); 3613 } 3614 3615 /* Based on hw strategy, the tag offloaded will be stored at 3616 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 3617 * in one layer tag case. 3618 */ 3619 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 3620 u16 vlan_tag; 3621 3622 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 3623 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 3624 vlan_tag); 3625 } 3626 3627 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 3628 BIT(HNS3_RXD_L2E_B))))) { 3629 u64_stats_update_begin(&ring->syncp); 3630 if (l234info & BIT(HNS3_RXD_L2E_B)) 3631 ring->stats.l2_err++; 3632 else 3633 ring->stats.err_pkt_len++; 3634 u64_stats_update_end(&ring->syncp); 3635 3636 return -EFAULT; 3637 } 3638 3639 len = skb->len; 3640 3641 /* Do update ip stack process */ 3642 skb->protocol = eth_type_trans(skb, netdev); 3643 3644 /* This is needed in order to enable forwarding support */ 3645 ret = hns3_set_gro_and_checksum(ring, skb, l234info, 3646 bd_base_info, ol_info, csum); 3647 if (unlikely(ret)) { 3648 u64_stats_update_begin(&ring->syncp); 3649 ring->stats.rx_err_cnt++; 3650 u64_stats_update_end(&ring->syncp); 3651 return ret; 3652 } 3653 3654 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 3655 HNS3_RXD_DMAC_S); 3656 3657 u64_stats_update_begin(&ring->syncp); 3658 ring->stats.rx_pkts++; 3659 ring->stats.rx_bytes += len; 3660 3661 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 3662 ring->stats.rx_multicast++; 3663 3664 u64_stats_update_end(&ring->syncp); 3665 3666 ring->tqp_vector->rx_group.total_bytes += len; 3667 3668 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash)); 3669 return 0; 3670 } 3671 3672 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring) 3673 { 3674 struct sk_buff *skb = ring->skb; 3675 struct hns3_desc_cb *desc_cb; 3676 struct hns3_desc *desc; 3677 unsigned int length; 3678 u32 bd_base_info; 3679 int ret; 3680 3681 desc = &ring->desc[ring->next_to_clean]; 3682 desc_cb = &ring->desc_cb[ring->next_to_clean]; 3683 3684 prefetch(desc); 3685 3686 if (!skb) { 3687 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3688 /* Check valid BD */ 3689 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 3690 return -ENXIO; 3691 3692 dma_rmb(); 3693 length = le16_to_cpu(desc->rx.size); 3694 3695 ring->va = desc_cb->buf + desc_cb->page_offset; 3696 3697 dma_sync_single_for_cpu(ring_to_dev(ring), 3698 desc_cb->dma + desc_cb->page_offset, 3699 hns3_buf_size(ring), 3700 DMA_FROM_DEVICE); 3701 3702 /* Prefetch first cache line of first page. 3703 * Idea is to cache few bytes of the header of the packet. 3704 * Our L1 Cache line size is 64B so need to prefetch twice to make 3705 * it 128B. But in actual we can have greater size of caches with 3706 * 128B Level 1 cache lines. In such a case, single fetch would 3707 * suffice to cache in the relevant part of the header. 3708 */ 3709 net_prefetch(ring->va); 3710 3711 ret = hns3_alloc_skb(ring, length, ring->va); 3712 skb = ring->skb; 3713 3714 if (ret < 0) /* alloc buffer fail */ 3715 return ret; 3716 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */ 3717 ret = hns3_add_frag(ring); 3718 if (ret) 3719 return ret; 3720 } 3721 } else { 3722 ret = hns3_add_frag(ring); 3723 if (ret) 3724 return ret; 3725 } 3726 3727 /* As the head data may be changed when GRO enable, copy 3728 * the head data in after other data rx completed 3729 */ 3730 if (skb->len > HNS3_RX_HEAD_SIZE) 3731 memcpy(skb->data, ring->va, 3732 ALIGN(ring->pull_len, sizeof(long))); 3733 3734 ret = hns3_handle_bdinfo(ring, skb); 3735 if (unlikely(ret)) { 3736 dev_kfree_skb_any(skb); 3737 return ret; 3738 } 3739 3740 skb_record_rx_queue(skb, ring->tqp->tqp_index); 3741 return 0; 3742 } 3743 3744 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget, 3745 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 3746 { 3747 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 3748 int unused_count = hns3_desc_unused(ring); 3749 int recv_pkts = 0; 3750 int err; 3751 3752 unused_count -= ring->pending_buf; 3753 3754 while (recv_pkts < budget) { 3755 /* Reuse or realloc buffers */ 3756 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 3757 hns3_nic_alloc_rx_buffers(ring, unused_count); 3758 unused_count = hns3_desc_unused(ring) - 3759 ring->pending_buf; 3760 } 3761 3762 /* Poll one pkt */ 3763 err = hns3_handle_rx_bd(ring); 3764 /* Do not get FE for the packet or failed to alloc skb */ 3765 if (unlikely(!ring->skb || err == -ENXIO)) { 3766 goto out; 3767 } else if (likely(!err)) { 3768 rx_fn(ring, ring->skb); 3769 recv_pkts++; 3770 } 3771 3772 unused_count += ring->pending_buf; 3773 ring->skb = NULL; 3774 ring->pending_buf = 0; 3775 } 3776 3777 out: 3778 /* Make all data has been write before submit */ 3779 if (unused_count > 0) 3780 hns3_nic_alloc_rx_buffers(ring, unused_count); 3781 3782 return recv_pkts; 3783 } 3784 3785 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector) 3786 { 3787 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 3788 struct dim_sample sample = {}; 3789 3790 if (!rx_group->coal.adapt_enable) 3791 return; 3792 3793 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets, 3794 rx_group->total_bytes, &sample); 3795 net_dim(&rx_group->dim, sample); 3796 } 3797 3798 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector) 3799 { 3800 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 3801 struct dim_sample sample = {}; 3802 3803 if (!tx_group->coal.adapt_enable) 3804 return; 3805 3806 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets, 3807 tx_group->total_bytes, &sample); 3808 net_dim(&tx_group->dim, sample); 3809 } 3810 3811 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 3812 { 3813 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 3814 struct hns3_enet_ring *ring; 3815 int rx_pkt_total = 0; 3816 3817 struct hns3_enet_tqp_vector *tqp_vector = 3818 container_of(napi, struct hns3_enet_tqp_vector, napi); 3819 bool clean_complete = true; 3820 int rx_budget = budget; 3821 3822 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3823 napi_complete(napi); 3824 return 0; 3825 } 3826 3827 /* Since the actual Tx work is minimal, we can give the Tx a larger 3828 * budget and be more aggressive about cleaning up the Tx descriptors. 3829 */ 3830 hns3_for_each_ring(ring, tqp_vector->tx_group) 3831 hns3_clean_tx_ring(ring, budget); 3832 3833 /* make sure rx ring budget not smaller than 1 */ 3834 if (tqp_vector->num_tqps > 1) 3835 rx_budget = max(budget / tqp_vector->num_tqps, 1); 3836 3837 hns3_for_each_ring(ring, tqp_vector->rx_group) { 3838 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 3839 hns3_rx_skb); 3840 if (rx_cleaned >= rx_budget) 3841 clean_complete = false; 3842 3843 rx_pkt_total += rx_cleaned; 3844 } 3845 3846 tqp_vector->rx_group.total_packets += rx_pkt_total; 3847 3848 if (!clean_complete) 3849 return budget; 3850 3851 if (napi_complete(napi) && 3852 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3853 hns3_update_rx_int_coalesce(tqp_vector); 3854 hns3_update_tx_int_coalesce(tqp_vector); 3855 3856 hns3_mask_vector_irq(tqp_vector, 1); 3857 } 3858 3859 return rx_pkt_total; 3860 } 3861 3862 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3863 struct hnae3_ring_chain_node *head) 3864 { 3865 struct pci_dev *pdev = tqp_vector->handle->pdev; 3866 struct hnae3_ring_chain_node *cur_chain = head; 3867 struct hnae3_ring_chain_node *chain; 3868 struct hns3_enet_ring *tx_ring; 3869 struct hns3_enet_ring *rx_ring; 3870 3871 tx_ring = tqp_vector->tx_group.ring; 3872 if (tx_ring) { 3873 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 3874 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3875 HNAE3_RING_TYPE_TX); 3876 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3877 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 3878 3879 cur_chain->next = NULL; 3880 3881 while (tx_ring->next) { 3882 tx_ring = tx_ring->next; 3883 3884 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 3885 GFP_KERNEL); 3886 if (!chain) 3887 goto err_free_chain; 3888 3889 cur_chain->next = chain; 3890 chain->tqp_index = tx_ring->tqp->tqp_index; 3891 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3892 HNAE3_RING_TYPE_TX); 3893 hnae3_set_field(chain->int_gl_idx, 3894 HNAE3_RING_GL_IDX_M, 3895 HNAE3_RING_GL_IDX_S, 3896 HNAE3_RING_GL_TX); 3897 3898 cur_chain = chain; 3899 } 3900 } 3901 3902 rx_ring = tqp_vector->rx_group.ring; 3903 if (!tx_ring && rx_ring) { 3904 cur_chain->next = NULL; 3905 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 3906 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3907 HNAE3_RING_TYPE_RX); 3908 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3909 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3910 3911 rx_ring = rx_ring->next; 3912 } 3913 3914 while (rx_ring) { 3915 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 3916 if (!chain) 3917 goto err_free_chain; 3918 3919 cur_chain->next = chain; 3920 chain->tqp_index = rx_ring->tqp->tqp_index; 3921 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3922 HNAE3_RING_TYPE_RX); 3923 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3924 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3925 3926 cur_chain = chain; 3927 3928 rx_ring = rx_ring->next; 3929 } 3930 3931 return 0; 3932 3933 err_free_chain: 3934 cur_chain = head->next; 3935 while (cur_chain) { 3936 chain = cur_chain->next; 3937 devm_kfree(&pdev->dev, cur_chain); 3938 cur_chain = chain; 3939 } 3940 head->next = NULL; 3941 3942 return -ENOMEM; 3943 } 3944 3945 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3946 struct hnae3_ring_chain_node *head) 3947 { 3948 struct pci_dev *pdev = tqp_vector->handle->pdev; 3949 struct hnae3_ring_chain_node *chain_tmp, *chain; 3950 3951 chain = head->next; 3952 3953 while (chain) { 3954 chain_tmp = chain->next; 3955 devm_kfree(&pdev->dev, chain); 3956 chain = chain_tmp; 3957 } 3958 } 3959 3960 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 3961 struct hns3_enet_ring *ring) 3962 { 3963 ring->next = group->ring; 3964 group->ring = ring; 3965 3966 group->count++; 3967 } 3968 3969 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 3970 { 3971 struct pci_dev *pdev = priv->ae_handle->pdev; 3972 struct hns3_enet_tqp_vector *tqp_vector; 3973 int num_vectors = priv->vector_num; 3974 int numa_node; 3975 int vector_i; 3976 3977 numa_node = dev_to_node(&pdev->dev); 3978 3979 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 3980 tqp_vector = &priv->tqp_vector[vector_i]; 3981 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 3982 &tqp_vector->affinity_mask); 3983 } 3984 } 3985 3986 static void hns3_rx_dim_work(struct work_struct *work) 3987 { 3988 struct dim *dim = container_of(work, struct dim, work); 3989 struct hns3_enet_ring_group *group = container_of(dim, 3990 struct hns3_enet_ring_group, dim); 3991 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector; 3992 struct dim_cq_moder cur_moder = 3993 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 3994 3995 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec); 3996 tqp_vector->rx_group.coal.int_gl = cur_moder.usec; 3997 3998 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) { 3999 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts); 4000 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts; 4001 } 4002 4003 dim->state = DIM_START_MEASURE; 4004 } 4005 4006 static void hns3_tx_dim_work(struct work_struct *work) 4007 { 4008 struct dim *dim = container_of(work, struct dim, work); 4009 struct hns3_enet_ring_group *group = container_of(dim, 4010 struct hns3_enet_ring_group, dim); 4011 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector; 4012 struct dim_cq_moder cur_moder = 4013 net_dim_get_tx_moderation(dim->mode, dim->profile_ix); 4014 4015 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec); 4016 tqp_vector->tx_group.coal.int_gl = cur_moder.usec; 4017 4018 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) { 4019 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts); 4020 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts; 4021 } 4022 4023 dim->state = DIM_START_MEASURE; 4024 } 4025 4026 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector) 4027 { 4028 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work); 4029 tqp_vector->rx_group.dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4030 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work); 4031 tqp_vector->tx_group.dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4032 } 4033 4034 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 4035 { 4036 struct hnae3_handle *h = priv->ae_handle; 4037 struct hns3_enet_tqp_vector *tqp_vector; 4038 int ret; 4039 int i; 4040 4041 hns3_nic_set_cpumask(priv); 4042 4043 for (i = 0; i < priv->vector_num; i++) { 4044 tqp_vector = &priv->tqp_vector[i]; 4045 hns3_vector_coalesce_init_hw(tqp_vector, priv); 4046 tqp_vector->num_tqps = 0; 4047 hns3_nic_init_dim(tqp_vector); 4048 } 4049 4050 for (i = 0; i < h->kinfo.num_tqps; i++) { 4051 u16 vector_i = i % priv->vector_num; 4052 u16 tqp_num = h->kinfo.num_tqps; 4053 4054 tqp_vector = &priv->tqp_vector[vector_i]; 4055 4056 hns3_add_ring_to_group(&tqp_vector->tx_group, 4057 &priv->ring[i]); 4058 4059 hns3_add_ring_to_group(&tqp_vector->rx_group, 4060 &priv->ring[i + tqp_num]); 4061 4062 priv->ring[i].tqp_vector = tqp_vector; 4063 priv->ring[i + tqp_num].tqp_vector = tqp_vector; 4064 tqp_vector->num_tqps++; 4065 } 4066 4067 for (i = 0; i < priv->vector_num; i++) { 4068 struct hnae3_ring_chain_node vector_ring_chain; 4069 4070 tqp_vector = &priv->tqp_vector[i]; 4071 4072 tqp_vector->rx_group.total_bytes = 0; 4073 tqp_vector->rx_group.total_packets = 0; 4074 tqp_vector->tx_group.total_bytes = 0; 4075 tqp_vector->tx_group.total_packets = 0; 4076 tqp_vector->handle = h; 4077 4078 ret = hns3_get_vector_ring_chain(tqp_vector, 4079 &vector_ring_chain); 4080 if (ret) 4081 goto map_ring_fail; 4082 4083 ret = h->ae_algo->ops->map_ring_to_vector(h, 4084 tqp_vector->vector_irq, &vector_ring_chain); 4085 4086 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 4087 4088 if (ret) 4089 goto map_ring_fail; 4090 4091 netif_napi_add(priv->netdev, &tqp_vector->napi, 4092 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 4093 } 4094 4095 return 0; 4096 4097 map_ring_fail: 4098 while (i--) 4099 netif_napi_del(&priv->tqp_vector[i].napi); 4100 4101 return ret; 4102 } 4103 4104 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv) 4105 { 4106 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 4107 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal; 4108 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal; 4109 4110 /* initialize the configuration for interrupt coalescing. 4111 * 1. GL (Interrupt Gap Limiter) 4112 * 2. RL (Interrupt Rate Limiter) 4113 * 3. QL (Interrupt Quantity Limiter) 4114 * 4115 * Default: enable interrupt coalescing self-adaptive and GL 4116 */ 4117 tx_coal->adapt_enable = 1; 4118 rx_coal->adapt_enable = 1; 4119 4120 tx_coal->int_gl = HNS3_INT_GL_50K; 4121 rx_coal->int_gl = HNS3_INT_GL_50K; 4122 4123 rx_coal->flow_level = HNS3_FLOW_LOW; 4124 tx_coal->flow_level = HNS3_FLOW_LOW; 4125 4126 if (ae_dev->dev_specs.int_ql_max) { 4127 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 4128 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 4129 } 4130 } 4131 4132 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 4133 { 4134 struct hnae3_handle *h = priv->ae_handle; 4135 struct hns3_enet_tqp_vector *tqp_vector; 4136 struct hnae3_vector_info *vector; 4137 struct pci_dev *pdev = h->pdev; 4138 u16 tqp_num = h->kinfo.num_tqps; 4139 u16 vector_num; 4140 int ret = 0; 4141 u16 i; 4142 4143 /* RSS size, cpu online and vector_num should be the same */ 4144 /* Should consider 2p/4p later */ 4145 vector_num = min_t(u16, num_online_cpus(), tqp_num); 4146 4147 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 4148 GFP_KERNEL); 4149 if (!vector) 4150 return -ENOMEM; 4151 4152 /* save the actual available vector number */ 4153 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 4154 4155 priv->vector_num = vector_num; 4156 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 4157 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 4158 GFP_KERNEL); 4159 if (!priv->tqp_vector) { 4160 ret = -ENOMEM; 4161 goto out; 4162 } 4163 4164 for (i = 0; i < priv->vector_num; i++) { 4165 tqp_vector = &priv->tqp_vector[i]; 4166 tqp_vector->idx = i; 4167 tqp_vector->mask_addr = vector[i].io_addr; 4168 tqp_vector->vector_irq = vector[i].vector; 4169 hns3_vector_coalesce_init(tqp_vector, priv); 4170 } 4171 4172 out: 4173 devm_kfree(&pdev->dev, vector); 4174 return ret; 4175 } 4176 4177 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 4178 { 4179 group->ring = NULL; 4180 group->count = 0; 4181 } 4182 4183 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 4184 { 4185 struct hnae3_ring_chain_node vector_ring_chain; 4186 struct hnae3_handle *h = priv->ae_handle; 4187 struct hns3_enet_tqp_vector *tqp_vector; 4188 int i; 4189 4190 for (i = 0; i < priv->vector_num; i++) { 4191 tqp_vector = &priv->tqp_vector[i]; 4192 4193 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 4194 continue; 4195 4196 /* Since the mapping can be overwritten, when fail to get the 4197 * chain between vector and ring, we should go on to deal with 4198 * the remaining options. 4199 */ 4200 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain)) 4201 dev_warn(priv->dev, "failed to get ring chain\n"); 4202 4203 h->ae_algo->ops->unmap_ring_from_vector(h, 4204 tqp_vector->vector_irq, &vector_ring_chain); 4205 4206 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 4207 4208 hns3_clear_ring_group(&tqp_vector->rx_group); 4209 hns3_clear_ring_group(&tqp_vector->tx_group); 4210 netif_napi_del(&priv->tqp_vector[i].napi); 4211 } 4212 } 4213 4214 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 4215 { 4216 struct hnae3_handle *h = priv->ae_handle; 4217 struct pci_dev *pdev = h->pdev; 4218 int i, ret; 4219 4220 for (i = 0; i < priv->vector_num; i++) { 4221 struct hns3_enet_tqp_vector *tqp_vector; 4222 4223 tqp_vector = &priv->tqp_vector[i]; 4224 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 4225 if (ret) 4226 return; 4227 } 4228 4229 devm_kfree(&pdev->dev, priv->tqp_vector); 4230 } 4231 4232 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 4233 unsigned int ring_type) 4234 { 4235 int queue_num = priv->ae_handle->kinfo.num_tqps; 4236 struct hns3_enet_ring *ring; 4237 int desc_num; 4238 4239 if (ring_type == HNAE3_RING_TYPE_TX) { 4240 ring = &priv->ring[q->tqp_index]; 4241 desc_num = priv->ae_handle->kinfo.num_tx_desc; 4242 ring->queue_index = q->tqp_index; 4243 } else { 4244 ring = &priv->ring[q->tqp_index + queue_num]; 4245 desc_num = priv->ae_handle->kinfo.num_rx_desc; 4246 ring->queue_index = q->tqp_index; 4247 } 4248 4249 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 4250 4251 ring->tqp = q; 4252 ring->desc = NULL; 4253 ring->desc_cb = NULL; 4254 ring->dev = priv->dev; 4255 ring->desc_dma_addr = 0; 4256 ring->buf_size = q->buf_size; 4257 ring->desc_num = desc_num; 4258 ring->next_to_use = 0; 4259 ring->next_to_clean = 0; 4260 ring->last_to_use = 0; 4261 } 4262 4263 static void hns3_queue_to_ring(struct hnae3_queue *tqp, 4264 struct hns3_nic_priv *priv) 4265 { 4266 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 4267 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 4268 } 4269 4270 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 4271 { 4272 struct hnae3_handle *h = priv->ae_handle; 4273 struct pci_dev *pdev = h->pdev; 4274 int i; 4275 4276 priv->ring = devm_kzalloc(&pdev->dev, 4277 array3_size(h->kinfo.num_tqps, 4278 sizeof(*priv->ring), 2), 4279 GFP_KERNEL); 4280 if (!priv->ring) 4281 return -ENOMEM; 4282 4283 for (i = 0; i < h->kinfo.num_tqps; i++) 4284 hns3_queue_to_ring(h->kinfo.tqp[i], priv); 4285 4286 return 0; 4287 } 4288 4289 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 4290 { 4291 if (!priv->ring) 4292 return; 4293 4294 devm_kfree(priv->dev, priv->ring); 4295 priv->ring = NULL; 4296 } 4297 4298 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 4299 { 4300 int ret; 4301 4302 if (ring->desc_num <= 0 || ring->buf_size <= 0) 4303 return -EINVAL; 4304 4305 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num, 4306 sizeof(ring->desc_cb[0]), GFP_KERNEL); 4307 if (!ring->desc_cb) { 4308 ret = -ENOMEM; 4309 goto out; 4310 } 4311 4312 ret = hns3_alloc_desc(ring); 4313 if (ret) 4314 goto out_with_desc_cb; 4315 4316 if (!HNAE3_IS_TX_RING(ring)) { 4317 ret = hns3_alloc_ring_buffers(ring); 4318 if (ret) 4319 goto out_with_desc; 4320 } 4321 4322 return 0; 4323 4324 out_with_desc: 4325 hns3_free_desc(ring); 4326 out_with_desc_cb: 4327 devm_kfree(ring_to_dev(ring), ring->desc_cb); 4328 ring->desc_cb = NULL; 4329 out: 4330 return ret; 4331 } 4332 4333 void hns3_fini_ring(struct hns3_enet_ring *ring) 4334 { 4335 hns3_free_desc(ring); 4336 devm_kfree(ring_to_dev(ring), ring->desc_cb); 4337 ring->desc_cb = NULL; 4338 ring->next_to_clean = 0; 4339 ring->next_to_use = 0; 4340 ring->last_to_use = 0; 4341 ring->pending_buf = 0; 4342 if (ring->skb) { 4343 dev_kfree_skb_any(ring->skb); 4344 ring->skb = NULL; 4345 } 4346 } 4347 4348 static int hns3_buf_size2type(u32 buf_size) 4349 { 4350 int bd_size_type; 4351 4352 switch (buf_size) { 4353 case 512: 4354 bd_size_type = HNS3_BD_SIZE_512_TYPE; 4355 break; 4356 case 1024: 4357 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 4358 break; 4359 case 2048: 4360 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 4361 break; 4362 case 4096: 4363 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 4364 break; 4365 default: 4366 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 4367 } 4368 4369 return bd_size_type; 4370 } 4371 4372 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 4373 { 4374 dma_addr_t dma = ring->desc_dma_addr; 4375 struct hnae3_queue *q = ring->tqp; 4376 4377 if (!HNAE3_IS_TX_RING(ring)) { 4378 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma); 4379 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 4380 (u32)((dma >> 31) >> 1)); 4381 4382 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 4383 hns3_buf_size2type(ring->buf_size)); 4384 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 4385 ring->desc_num / 8 - 1); 4386 } else { 4387 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 4388 (u32)dma); 4389 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 4390 (u32)((dma >> 31) >> 1)); 4391 4392 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 4393 ring->desc_num / 8 - 1); 4394 } 4395 } 4396 4397 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 4398 { 4399 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 4400 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 4401 int i; 4402 4403 for (i = 0; i < HNAE3_MAX_TC; i++) { 4404 int j; 4405 4406 if (!test_bit(i, &tc_info->tc_en)) 4407 continue; 4408 4409 for (j = 0; j < tc_info->tqp_count[i]; j++) { 4410 struct hnae3_queue *q; 4411 4412 q = priv->ring[tc_info->tqp_offset[i] + j].tqp; 4413 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i); 4414 } 4415 } 4416 } 4417 4418 int hns3_init_all_ring(struct hns3_nic_priv *priv) 4419 { 4420 struct hnae3_handle *h = priv->ae_handle; 4421 int ring_num = h->kinfo.num_tqps * 2; 4422 int i, j; 4423 int ret; 4424 4425 for (i = 0; i < ring_num; i++) { 4426 ret = hns3_alloc_ring_memory(&priv->ring[i]); 4427 if (ret) { 4428 dev_err(priv->dev, 4429 "Alloc ring memory fail! ret=%d\n", ret); 4430 goto out_when_alloc_ring_memory; 4431 } 4432 4433 u64_stats_init(&priv->ring[i].syncp); 4434 } 4435 4436 return 0; 4437 4438 out_when_alloc_ring_memory: 4439 for (j = i - 1; j >= 0; j--) 4440 hns3_fini_ring(&priv->ring[j]); 4441 4442 return -ENOMEM; 4443 } 4444 4445 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv) 4446 { 4447 struct hnae3_handle *h = priv->ae_handle; 4448 int i; 4449 4450 for (i = 0; i < h->kinfo.num_tqps; i++) { 4451 hns3_fini_ring(&priv->ring[i]); 4452 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]); 4453 } 4454 } 4455 4456 /* Set mac addr if it is configured. or leave it to the AE driver */ 4457 static int hns3_init_mac_addr(struct net_device *netdev) 4458 { 4459 struct hns3_nic_priv *priv = netdev_priv(netdev); 4460 struct hnae3_handle *h = priv->ae_handle; 4461 u8 mac_addr_temp[ETH_ALEN]; 4462 int ret = 0; 4463 4464 if (h->ae_algo->ops->get_mac_addr) 4465 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 4466 4467 /* Check if the MAC address is valid, if not get a random one */ 4468 if (!is_valid_ether_addr(mac_addr_temp)) { 4469 eth_hw_addr_random(netdev); 4470 dev_warn(priv->dev, "using random MAC address %pM\n", 4471 netdev->dev_addr); 4472 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) { 4473 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 4474 ether_addr_copy(netdev->perm_addr, mac_addr_temp); 4475 } else { 4476 return 0; 4477 } 4478 4479 if (h->ae_algo->ops->set_mac_addr) 4480 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 4481 4482 return ret; 4483 } 4484 4485 static int hns3_init_phy(struct net_device *netdev) 4486 { 4487 struct hnae3_handle *h = hns3_get_handle(netdev); 4488 int ret = 0; 4489 4490 if (h->ae_algo->ops->mac_connect_phy) 4491 ret = h->ae_algo->ops->mac_connect_phy(h); 4492 4493 return ret; 4494 } 4495 4496 static void hns3_uninit_phy(struct net_device *netdev) 4497 { 4498 struct hnae3_handle *h = hns3_get_handle(netdev); 4499 4500 if (h->ae_algo->ops->mac_disconnect_phy) 4501 h->ae_algo->ops->mac_disconnect_phy(h); 4502 } 4503 4504 static int hns3_client_start(struct hnae3_handle *handle) 4505 { 4506 if (!handle->ae_algo->ops->client_start) 4507 return 0; 4508 4509 return handle->ae_algo->ops->client_start(handle); 4510 } 4511 4512 static void hns3_client_stop(struct hnae3_handle *handle) 4513 { 4514 if (!handle->ae_algo->ops->client_stop) 4515 return; 4516 4517 handle->ae_algo->ops->client_stop(handle); 4518 } 4519 4520 static void hns3_info_show(struct hns3_nic_priv *priv) 4521 { 4522 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 4523 4524 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr); 4525 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps); 4526 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size); 4527 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size); 4528 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len); 4529 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc); 4530 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc); 4531 dev_info(priv->dev, "Total number of enabled TCs: %u\n", 4532 kinfo->tc_info.num_tc); 4533 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu); 4534 } 4535 4536 static int hns3_client_init(struct hnae3_handle *handle) 4537 { 4538 struct pci_dev *pdev = handle->pdev; 4539 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4540 u16 alloc_tqps, max_rss_size; 4541 struct hns3_nic_priv *priv; 4542 struct net_device *netdev; 4543 int ret; 4544 4545 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 4546 &max_rss_size); 4547 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 4548 if (!netdev) 4549 return -ENOMEM; 4550 4551 priv = netdev_priv(netdev); 4552 priv->dev = &pdev->dev; 4553 priv->netdev = netdev; 4554 priv->ae_handle = handle; 4555 priv->tx_timeout_count = 0; 4556 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num; 4557 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 4558 4559 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL); 4560 4561 handle->kinfo.netdev = netdev; 4562 handle->priv = (void *)priv; 4563 4564 hns3_init_mac_addr(netdev); 4565 4566 hns3_set_default_feature(netdev); 4567 4568 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 4569 netdev->priv_flags |= IFF_UNICAST_FLT; 4570 netdev->netdev_ops = &hns3_nic_netdev_ops; 4571 SET_NETDEV_DEV(netdev, &pdev->dev); 4572 hns3_ethtool_set_ops(netdev); 4573 4574 /* Carrier off reporting is important to ethtool even BEFORE open */ 4575 netif_carrier_off(netdev); 4576 4577 ret = hns3_get_ring_config(priv); 4578 if (ret) { 4579 ret = -ENOMEM; 4580 goto out_get_ring_cfg; 4581 } 4582 4583 hns3_nic_init_coal_cfg(priv); 4584 4585 ret = hns3_nic_alloc_vector_data(priv); 4586 if (ret) { 4587 ret = -ENOMEM; 4588 goto out_alloc_vector_data; 4589 } 4590 4591 ret = hns3_nic_init_vector_data(priv); 4592 if (ret) { 4593 ret = -ENOMEM; 4594 goto out_init_vector_data; 4595 } 4596 4597 ret = hns3_init_all_ring(priv); 4598 if (ret) { 4599 ret = -ENOMEM; 4600 goto out_init_ring; 4601 } 4602 4603 ret = hns3_init_phy(netdev); 4604 if (ret) 4605 goto out_init_phy; 4606 4607 /* the device can work without cpu rmap, only aRFS needs it */ 4608 ret = hns3_set_rx_cpu_rmap(netdev); 4609 if (ret) 4610 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 4611 4612 ret = hns3_nic_init_irq(priv); 4613 if (ret) { 4614 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 4615 hns3_free_rx_cpu_rmap(netdev); 4616 goto out_init_irq_fail; 4617 } 4618 4619 ret = hns3_client_start(handle); 4620 if (ret) { 4621 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4622 goto out_client_start; 4623 } 4624 4625 hns3_dcbnl_setup(handle); 4626 4627 ret = hns3_dbg_init(handle); 4628 if (ret) { 4629 dev_err(priv->dev, "failed to init debugfs, ret = %d\n", 4630 ret); 4631 goto out_client_start; 4632 } 4633 4634 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size); 4635 4636 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) 4637 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state); 4638 4639 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev)) 4640 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state); 4641 4642 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4643 4644 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 4645 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags); 4646 4647 ret = register_netdev(netdev); 4648 if (ret) { 4649 dev_err(priv->dev, "probe register netdev fail!\n"); 4650 goto out_reg_netdev_fail; 4651 } 4652 4653 if (netif_msg_drv(handle)) 4654 hns3_info_show(priv); 4655 4656 return ret; 4657 4658 out_reg_netdev_fail: 4659 hns3_dbg_uninit(handle); 4660 out_client_start: 4661 hns3_free_rx_cpu_rmap(netdev); 4662 hns3_nic_uninit_irq(priv); 4663 out_init_irq_fail: 4664 hns3_uninit_phy(netdev); 4665 out_init_phy: 4666 hns3_uninit_all_ring(priv); 4667 out_init_ring: 4668 hns3_nic_uninit_vector_data(priv); 4669 out_init_vector_data: 4670 hns3_nic_dealloc_vector_data(priv); 4671 out_alloc_vector_data: 4672 priv->ring = NULL; 4673 out_get_ring_cfg: 4674 priv->ae_handle = NULL; 4675 free_netdev(netdev); 4676 return ret; 4677 } 4678 4679 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 4680 { 4681 struct net_device *netdev = handle->kinfo.netdev; 4682 struct hns3_nic_priv *priv = netdev_priv(netdev); 4683 4684 if (netdev->reg_state != NETREG_UNINITIALIZED) 4685 unregister_netdev(netdev); 4686 4687 hns3_client_stop(handle); 4688 4689 hns3_uninit_phy(netdev); 4690 4691 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4692 netdev_warn(netdev, "already uninitialized\n"); 4693 goto out_netdev_free; 4694 } 4695 4696 hns3_free_rx_cpu_rmap(netdev); 4697 4698 hns3_nic_uninit_irq(priv); 4699 4700 hns3_clear_all_ring(handle, true); 4701 4702 hns3_nic_uninit_vector_data(priv); 4703 4704 hns3_nic_dealloc_vector_data(priv); 4705 4706 hns3_uninit_all_ring(priv); 4707 4708 hns3_put_ring_config(priv); 4709 4710 out_netdev_free: 4711 hns3_dbg_uninit(handle); 4712 free_netdev(netdev); 4713 } 4714 4715 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 4716 { 4717 struct net_device *netdev = handle->kinfo.netdev; 4718 4719 if (!netdev) 4720 return; 4721 4722 if (linkup) { 4723 netif_tx_wake_all_queues(netdev); 4724 netif_carrier_on(netdev); 4725 if (netif_msg_link(handle)) 4726 netdev_info(netdev, "link up\n"); 4727 } else { 4728 netif_carrier_off(netdev); 4729 netif_tx_stop_all_queues(netdev); 4730 if (netif_msg_link(handle)) 4731 netdev_info(netdev, "link down\n"); 4732 } 4733 } 4734 4735 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 4736 { 4737 while (ring->next_to_clean != ring->next_to_use) { 4738 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 4739 hns3_free_buffer_detach(ring, ring->next_to_clean, 0); 4740 ring_ptr_move_fw(ring, next_to_clean); 4741 } 4742 4743 ring->pending_buf = 0; 4744 } 4745 4746 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 4747 { 4748 struct hns3_desc_cb res_cbs; 4749 int ret; 4750 4751 while (ring->next_to_use != ring->next_to_clean) { 4752 /* When a buffer is not reused, it's memory has been 4753 * freed in hns3_handle_rx_bd or will be freed by 4754 * stack, so we need to replace the buffer here. 4755 */ 4756 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4757 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 4758 if (ret) { 4759 u64_stats_update_begin(&ring->syncp); 4760 ring->stats.sw_err_cnt++; 4761 u64_stats_update_end(&ring->syncp); 4762 /* if alloc new buffer fail, exit directly 4763 * and reclear in up flow. 4764 */ 4765 netdev_warn(ring_to_netdev(ring), 4766 "reserve buffer map failed, ret = %d\n", 4767 ret); 4768 return ret; 4769 } 4770 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 4771 } 4772 ring_ptr_move_fw(ring, next_to_use); 4773 } 4774 4775 /* Free the pending skb in rx ring */ 4776 if (ring->skb) { 4777 dev_kfree_skb_any(ring->skb); 4778 ring->skb = NULL; 4779 ring->pending_buf = 0; 4780 } 4781 4782 return 0; 4783 } 4784 4785 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 4786 { 4787 while (ring->next_to_use != ring->next_to_clean) { 4788 /* When a buffer is not reused, it's memory has been 4789 * freed in hns3_handle_rx_bd or will be freed by 4790 * stack, so only need to unmap the buffer here. 4791 */ 4792 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4793 hns3_unmap_buffer(ring, 4794 &ring->desc_cb[ring->next_to_use]); 4795 ring->desc_cb[ring->next_to_use].dma = 0; 4796 } 4797 4798 ring_ptr_move_fw(ring, next_to_use); 4799 } 4800 } 4801 4802 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force) 4803 { 4804 struct net_device *ndev = h->kinfo.netdev; 4805 struct hns3_nic_priv *priv = netdev_priv(ndev); 4806 u32 i; 4807 4808 for (i = 0; i < h->kinfo.num_tqps; i++) { 4809 struct hns3_enet_ring *ring; 4810 4811 ring = &priv->ring[i]; 4812 hns3_clear_tx_ring(ring); 4813 4814 ring = &priv->ring[i + h->kinfo.num_tqps]; 4815 /* Continue to clear other rings even if clearing some 4816 * rings failed. 4817 */ 4818 if (force) 4819 hns3_force_clear_rx_ring(ring); 4820 else 4821 hns3_clear_rx_ring(ring); 4822 } 4823 } 4824 4825 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 4826 { 4827 struct net_device *ndev = h->kinfo.netdev; 4828 struct hns3_nic_priv *priv = netdev_priv(ndev); 4829 struct hns3_enet_ring *rx_ring; 4830 int i, j; 4831 int ret; 4832 4833 ret = h->ae_algo->ops->reset_queue(h); 4834 if (ret) 4835 return ret; 4836 4837 for (i = 0; i < h->kinfo.num_tqps; i++) { 4838 hns3_init_ring_hw(&priv->ring[i]); 4839 4840 /* We need to clear tx ring here because self test will 4841 * use the ring and will not run down before up 4842 */ 4843 hns3_clear_tx_ring(&priv->ring[i]); 4844 priv->ring[i].next_to_clean = 0; 4845 priv->ring[i].next_to_use = 0; 4846 priv->ring[i].last_to_use = 0; 4847 4848 rx_ring = &priv->ring[i + h->kinfo.num_tqps]; 4849 hns3_init_ring_hw(rx_ring); 4850 ret = hns3_clear_rx_ring(rx_ring); 4851 if (ret) 4852 return ret; 4853 4854 /* We can not know the hardware head and tail when this 4855 * function is called in reset flow, so we reuse all desc. 4856 */ 4857 for (j = 0; j < rx_ring->desc_num; j++) 4858 hns3_reuse_buffer(rx_ring, j); 4859 4860 rx_ring->next_to_clean = 0; 4861 rx_ring->next_to_use = 0; 4862 } 4863 4864 hns3_init_tx_ring_tc(priv); 4865 4866 return 0; 4867 } 4868 4869 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 4870 { 4871 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4872 struct net_device *ndev = kinfo->netdev; 4873 struct hns3_nic_priv *priv = netdev_priv(ndev); 4874 4875 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 4876 return 0; 4877 4878 if (!netif_running(ndev)) 4879 return 0; 4880 4881 return hns3_nic_net_stop(ndev); 4882 } 4883 4884 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 4885 { 4886 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4887 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 4888 int ret = 0; 4889 4890 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4891 netdev_err(kinfo->netdev, "device is not initialized yet\n"); 4892 return -EFAULT; 4893 } 4894 4895 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4896 4897 if (netif_running(kinfo->netdev)) { 4898 ret = hns3_nic_net_open(kinfo->netdev); 4899 if (ret) { 4900 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4901 netdev_err(kinfo->netdev, 4902 "net up fail, ret=%d!\n", ret); 4903 return ret; 4904 } 4905 } 4906 4907 return ret; 4908 } 4909 4910 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 4911 { 4912 struct net_device *netdev = handle->kinfo.netdev; 4913 struct hns3_nic_priv *priv = netdev_priv(netdev); 4914 int ret; 4915 4916 /* Carrier off reporting is important to ethtool even BEFORE open */ 4917 netif_carrier_off(netdev); 4918 4919 ret = hns3_get_ring_config(priv); 4920 if (ret) 4921 return ret; 4922 4923 ret = hns3_nic_alloc_vector_data(priv); 4924 if (ret) 4925 goto err_put_ring; 4926 4927 ret = hns3_nic_init_vector_data(priv); 4928 if (ret) 4929 goto err_dealloc_vector; 4930 4931 ret = hns3_init_all_ring(priv); 4932 if (ret) 4933 goto err_uninit_vector; 4934 4935 /* the device can work without cpu rmap, only aRFS needs it */ 4936 ret = hns3_set_rx_cpu_rmap(netdev); 4937 if (ret) 4938 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 4939 4940 ret = hns3_nic_init_irq(priv); 4941 if (ret) { 4942 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 4943 hns3_free_rx_cpu_rmap(netdev); 4944 goto err_init_irq_fail; 4945 } 4946 4947 if (!hns3_is_phys_func(handle->pdev)) 4948 hns3_init_mac_addr(netdev); 4949 4950 ret = hns3_client_start(handle); 4951 if (ret) { 4952 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4953 goto err_client_start_fail; 4954 } 4955 4956 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4957 4958 return ret; 4959 4960 err_client_start_fail: 4961 hns3_free_rx_cpu_rmap(netdev); 4962 hns3_nic_uninit_irq(priv); 4963 err_init_irq_fail: 4964 hns3_uninit_all_ring(priv); 4965 err_uninit_vector: 4966 hns3_nic_uninit_vector_data(priv); 4967 err_dealloc_vector: 4968 hns3_nic_dealloc_vector_data(priv); 4969 err_put_ring: 4970 hns3_put_ring_config(priv); 4971 4972 return ret; 4973 } 4974 4975 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 4976 { 4977 struct net_device *netdev = handle->kinfo.netdev; 4978 struct hns3_nic_priv *priv = netdev_priv(netdev); 4979 4980 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4981 netdev_warn(netdev, "already uninitialized\n"); 4982 return 0; 4983 } 4984 4985 hns3_free_rx_cpu_rmap(netdev); 4986 hns3_nic_uninit_irq(priv); 4987 hns3_clear_all_ring(handle, true); 4988 hns3_reset_tx_queue(priv->ae_handle); 4989 4990 hns3_nic_uninit_vector_data(priv); 4991 4992 hns3_nic_dealloc_vector_data(priv); 4993 4994 hns3_uninit_all_ring(priv); 4995 4996 hns3_put_ring_config(priv); 4997 4998 return 0; 4999 } 5000 5001 static int hns3_reset_notify(struct hnae3_handle *handle, 5002 enum hnae3_reset_notify_type type) 5003 { 5004 int ret = 0; 5005 5006 switch (type) { 5007 case HNAE3_UP_CLIENT: 5008 ret = hns3_reset_notify_up_enet(handle); 5009 break; 5010 case HNAE3_DOWN_CLIENT: 5011 ret = hns3_reset_notify_down_enet(handle); 5012 break; 5013 case HNAE3_INIT_CLIENT: 5014 ret = hns3_reset_notify_init_enet(handle); 5015 break; 5016 case HNAE3_UNINIT_CLIENT: 5017 ret = hns3_reset_notify_uninit_enet(handle); 5018 break; 5019 default: 5020 break; 5021 } 5022 5023 return ret; 5024 } 5025 5026 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num, 5027 bool rxfh_configured) 5028 { 5029 int ret; 5030 5031 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num, 5032 rxfh_configured); 5033 if (ret) { 5034 dev_err(&handle->pdev->dev, 5035 "Change tqp num(%u) fail.\n", new_tqp_num); 5036 return ret; 5037 } 5038 5039 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT); 5040 if (ret) 5041 return ret; 5042 5043 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT); 5044 if (ret) 5045 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT); 5046 5047 return ret; 5048 } 5049 5050 int hns3_set_channels(struct net_device *netdev, 5051 struct ethtool_channels *ch) 5052 { 5053 struct hnae3_handle *h = hns3_get_handle(netdev); 5054 struct hnae3_knic_private_info *kinfo = &h->kinfo; 5055 bool rxfh_configured = netif_is_rxfh_configured(netdev); 5056 u32 new_tqp_num = ch->combined_count; 5057 u16 org_tqp_num; 5058 int ret; 5059 5060 if (hns3_nic_resetting(netdev)) 5061 return -EBUSY; 5062 5063 if (ch->rx_count || ch->tx_count) 5064 return -EINVAL; 5065 5066 if (kinfo->tc_info.mqprio_active) { 5067 dev_err(&netdev->dev, 5068 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n"); 5069 return -EINVAL; 5070 } 5071 5072 if (new_tqp_num > hns3_get_max_available_channels(h) || 5073 new_tqp_num < 1) { 5074 dev_err(&netdev->dev, 5075 "Change tqps fail, the tqp range is from 1 to %u", 5076 hns3_get_max_available_channels(h)); 5077 return -EINVAL; 5078 } 5079 5080 if (kinfo->rss_size == new_tqp_num) 5081 return 0; 5082 5083 netif_dbg(h, drv, netdev, 5084 "set channels: tqp_num=%u, rxfh=%d\n", 5085 new_tqp_num, rxfh_configured); 5086 5087 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 5088 if (ret) 5089 return ret; 5090 5091 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 5092 if (ret) 5093 return ret; 5094 5095 org_tqp_num = h->kinfo.num_tqps; 5096 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured); 5097 if (ret) { 5098 int ret1; 5099 5100 netdev_warn(netdev, 5101 "Change channels fail, revert to old value\n"); 5102 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured); 5103 if (ret1) { 5104 netdev_err(netdev, 5105 "revert to old channel fail\n"); 5106 return ret1; 5107 } 5108 5109 return ret; 5110 } 5111 5112 return 0; 5113 } 5114 5115 static const struct hns3_hw_error_info hns3_hw_err[] = { 5116 { .type = HNAE3_PPU_POISON_ERROR, 5117 .msg = "PPU poison" }, 5118 { .type = HNAE3_CMDQ_ECC_ERROR, 5119 .msg = "IMP CMDQ error" }, 5120 { .type = HNAE3_IMP_RD_POISON_ERROR, 5121 .msg = "IMP RD poison" }, 5122 { .type = HNAE3_ROCEE_AXI_RESP_ERROR, 5123 .msg = "ROCEE AXI RESP error" }, 5124 }; 5125 5126 static void hns3_process_hw_error(struct hnae3_handle *handle, 5127 enum hnae3_hw_error_type type) 5128 { 5129 int i; 5130 5131 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) { 5132 if (hns3_hw_err[i].type == type) { 5133 dev_err(&handle->pdev->dev, "Detected %s!\n", 5134 hns3_hw_err[i].msg); 5135 break; 5136 } 5137 } 5138 } 5139 5140 static const struct hnae3_client_ops client_ops = { 5141 .init_instance = hns3_client_init, 5142 .uninit_instance = hns3_client_uninit, 5143 .link_status_change = hns3_link_status_change, 5144 .reset_notify = hns3_reset_notify, 5145 .process_hw_error = hns3_process_hw_error, 5146 }; 5147 5148 /* hns3_init_module - Driver registration routine 5149 * hns3_init_module is the first routine called when the driver is 5150 * loaded. All it does is register with the PCI subsystem. 5151 */ 5152 static int __init hns3_init_module(void) 5153 { 5154 int ret; 5155 5156 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 5157 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 5158 5159 client.type = HNAE3_CLIENT_KNIC; 5160 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s", 5161 hns3_driver_name); 5162 5163 client.ops = &client_ops; 5164 5165 INIT_LIST_HEAD(&client.node); 5166 5167 hns3_dbg_register_debugfs(hns3_driver_name); 5168 5169 ret = hnae3_register_client(&client); 5170 if (ret) 5171 goto err_reg_client; 5172 5173 ret = pci_register_driver(&hns3_driver); 5174 if (ret) 5175 goto err_reg_driver; 5176 5177 return ret; 5178 5179 err_reg_driver: 5180 hnae3_unregister_client(&client); 5181 err_reg_client: 5182 hns3_dbg_unregister_debugfs(); 5183 return ret; 5184 } 5185 module_init(hns3_init_module); 5186 5187 /* hns3_exit_module - Driver exit cleanup routine 5188 * hns3_exit_module is called just before the driver is removed 5189 * from memory. 5190 */ 5191 static void __exit hns3_exit_module(void) 5192 { 5193 pci_unregister_driver(&hns3_driver); 5194 hnae3_unregister_client(&client); 5195 hns3_dbg_unregister_debugfs(); 5196 } 5197 module_exit(hns3_exit_module); 5198 5199 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 5200 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 5201 MODULE_LICENSE("GPL"); 5202 MODULE_ALIAS("pci:hns-nic"); 5203