1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #ifdef CONFIG_RFS_ACCEL 8 #include <linux/cpu_rmap.h> 9 #endif 10 #include <linux/if_vlan.h> 11 #include <linux/irq.h> 12 #include <linux/ip.h> 13 #include <linux/ipv6.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/aer.h> 17 #include <linux/skbuff.h> 18 #include <linux/sctp.h> 19 #include <net/gre.h> 20 #include <net/ip6_checksum.h> 21 #include <net/pkt_cls.h> 22 #include <net/tcp.h> 23 #include <net/vxlan.h> 24 #include <net/geneve.h> 25 26 #include "hnae3.h" 27 #include "hns3_enet.h" 28 /* All hns3 tracepoints are defined by the include below, which 29 * must be included exactly once across the whole kernel with 30 * CREATE_TRACE_POINTS defined 31 */ 32 #define CREATE_TRACE_POINTS 33 #include "hns3_trace.h" 34 35 #define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift)) 36 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE) 37 38 #define hns3_rl_err(fmt, ...) \ 39 do { \ 40 if (net_ratelimit()) \ 41 netdev_err(fmt, ##__VA_ARGS__); \ 42 } while (0) 43 44 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force); 45 46 static const char hns3_driver_name[] = "hns3"; 47 static const char hns3_driver_string[] = 48 "Hisilicon Ethernet Network Driver for Hip08 Family"; 49 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 50 static struct hnae3_client client; 51 52 static int debug = -1; 53 module_param(debug, int, 0); 54 MODULE_PARM_DESC(debug, " Network interface message level setting"); 55 56 static unsigned int tx_spare_buf_size; 57 module_param(tx_spare_buf_size, uint, 0400); 58 MODULE_PARM_DESC(tx_spare_buf_size, "Size used to allocate tx spare buffer"); 59 60 static unsigned int tx_sgl = 1; 61 module_param(tx_sgl, uint, 0600); 62 MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping"); 63 64 #define HNS3_SGL_SIZE(nfrag) (sizeof(struct scatterlist) * (nfrag) + \ 65 sizeof(struct sg_table)) 66 #define HNS3_MAX_SGL_SIZE ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM),\ 67 dma_get_cache_alignment()) 68 69 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 70 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) 71 72 #define HNS3_INNER_VLAN_TAG 1 73 #define HNS3_OUTER_VLAN_TAG 2 74 75 #define HNS3_MIN_TX_LEN 33U 76 77 /* hns3_pci_tbl - PCI Device ID Table 78 * 79 * Last entry must be all 0s 80 * 81 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 82 * Class, Class Mask, private data (not used) } 83 */ 84 static const struct pci_device_id hns3_pci_tbl[] = { 85 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 86 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 88 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 89 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 90 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 91 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 92 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 93 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 94 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 95 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 96 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 97 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 98 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 99 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 100 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 101 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 102 /* required last entry */ 103 {0, } 104 }; 105 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 106 107 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t) \ 108 { ptype, \ 109 l, \ 110 CHECKSUM_##s, \ 111 HNS3_L3_TYPE_##t, \ 112 1 } 113 114 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \ 115 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0 } 116 117 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = { 118 HNS3_RX_PTYPE_UNUSED_ENTRY(0), 119 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP), 120 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP), 121 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP), 122 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL), 123 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL), 124 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL), 125 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM), 126 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL), 127 HNS3_RX_PTYPE_UNUSED_ENTRY(9), 128 HNS3_RX_PTYPE_UNUSED_ENTRY(10), 129 HNS3_RX_PTYPE_UNUSED_ENTRY(11), 130 HNS3_RX_PTYPE_UNUSED_ENTRY(12), 131 HNS3_RX_PTYPE_UNUSED_ENTRY(13), 132 HNS3_RX_PTYPE_UNUSED_ENTRY(14), 133 HNS3_RX_PTYPE_UNUSED_ENTRY(15), 134 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL), 135 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4), 136 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4), 137 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4), 138 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4), 139 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4), 140 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4), 141 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4), 142 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4), 143 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4), 144 HNS3_RX_PTYPE_UNUSED_ENTRY(26), 145 HNS3_RX_PTYPE_UNUSED_ENTRY(27), 146 HNS3_RX_PTYPE_UNUSED_ENTRY(28), 147 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL), 148 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL), 149 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4), 150 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4), 151 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4), 152 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4), 153 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4), 154 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4), 155 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4), 156 HNS3_RX_PTYPE_UNUSED_ENTRY(38), 157 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6), 158 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6), 159 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6), 160 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6), 161 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6), 162 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6), 163 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6), 164 HNS3_RX_PTYPE_UNUSED_ENTRY(46), 165 HNS3_RX_PTYPE_UNUSED_ENTRY(47), 166 HNS3_RX_PTYPE_UNUSED_ENTRY(48), 167 HNS3_RX_PTYPE_UNUSED_ENTRY(49), 168 HNS3_RX_PTYPE_UNUSED_ENTRY(50), 169 HNS3_RX_PTYPE_UNUSED_ENTRY(51), 170 HNS3_RX_PTYPE_UNUSED_ENTRY(52), 171 HNS3_RX_PTYPE_UNUSED_ENTRY(53), 172 HNS3_RX_PTYPE_UNUSED_ENTRY(54), 173 HNS3_RX_PTYPE_UNUSED_ENTRY(55), 174 HNS3_RX_PTYPE_UNUSED_ENTRY(56), 175 HNS3_RX_PTYPE_UNUSED_ENTRY(57), 176 HNS3_RX_PTYPE_UNUSED_ENTRY(58), 177 HNS3_RX_PTYPE_UNUSED_ENTRY(59), 178 HNS3_RX_PTYPE_UNUSED_ENTRY(60), 179 HNS3_RX_PTYPE_UNUSED_ENTRY(61), 180 HNS3_RX_PTYPE_UNUSED_ENTRY(62), 181 HNS3_RX_PTYPE_UNUSED_ENTRY(63), 182 HNS3_RX_PTYPE_UNUSED_ENTRY(64), 183 HNS3_RX_PTYPE_UNUSED_ENTRY(65), 184 HNS3_RX_PTYPE_UNUSED_ENTRY(66), 185 HNS3_RX_PTYPE_UNUSED_ENTRY(67), 186 HNS3_RX_PTYPE_UNUSED_ENTRY(68), 187 HNS3_RX_PTYPE_UNUSED_ENTRY(69), 188 HNS3_RX_PTYPE_UNUSED_ENTRY(70), 189 HNS3_RX_PTYPE_UNUSED_ENTRY(71), 190 HNS3_RX_PTYPE_UNUSED_ENTRY(72), 191 HNS3_RX_PTYPE_UNUSED_ENTRY(73), 192 HNS3_RX_PTYPE_UNUSED_ENTRY(74), 193 HNS3_RX_PTYPE_UNUSED_ENTRY(75), 194 HNS3_RX_PTYPE_UNUSED_ENTRY(76), 195 HNS3_RX_PTYPE_UNUSED_ENTRY(77), 196 HNS3_RX_PTYPE_UNUSED_ENTRY(78), 197 HNS3_RX_PTYPE_UNUSED_ENTRY(79), 198 HNS3_RX_PTYPE_UNUSED_ENTRY(80), 199 HNS3_RX_PTYPE_UNUSED_ENTRY(81), 200 HNS3_RX_PTYPE_UNUSED_ENTRY(82), 201 HNS3_RX_PTYPE_UNUSED_ENTRY(83), 202 HNS3_RX_PTYPE_UNUSED_ENTRY(84), 203 HNS3_RX_PTYPE_UNUSED_ENTRY(85), 204 HNS3_RX_PTYPE_UNUSED_ENTRY(86), 205 HNS3_RX_PTYPE_UNUSED_ENTRY(87), 206 HNS3_RX_PTYPE_UNUSED_ENTRY(88), 207 HNS3_RX_PTYPE_UNUSED_ENTRY(89), 208 HNS3_RX_PTYPE_UNUSED_ENTRY(90), 209 HNS3_RX_PTYPE_UNUSED_ENTRY(91), 210 HNS3_RX_PTYPE_UNUSED_ENTRY(92), 211 HNS3_RX_PTYPE_UNUSED_ENTRY(93), 212 HNS3_RX_PTYPE_UNUSED_ENTRY(94), 213 HNS3_RX_PTYPE_UNUSED_ENTRY(95), 214 HNS3_RX_PTYPE_UNUSED_ENTRY(96), 215 HNS3_RX_PTYPE_UNUSED_ENTRY(97), 216 HNS3_RX_PTYPE_UNUSED_ENTRY(98), 217 HNS3_RX_PTYPE_UNUSED_ENTRY(99), 218 HNS3_RX_PTYPE_UNUSED_ENTRY(100), 219 HNS3_RX_PTYPE_UNUSED_ENTRY(101), 220 HNS3_RX_PTYPE_UNUSED_ENTRY(102), 221 HNS3_RX_PTYPE_UNUSED_ENTRY(103), 222 HNS3_RX_PTYPE_UNUSED_ENTRY(104), 223 HNS3_RX_PTYPE_UNUSED_ENTRY(105), 224 HNS3_RX_PTYPE_UNUSED_ENTRY(106), 225 HNS3_RX_PTYPE_UNUSED_ENTRY(107), 226 HNS3_RX_PTYPE_UNUSED_ENTRY(108), 227 HNS3_RX_PTYPE_UNUSED_ENTRY(109), 228 HNS3_RX_PTYPE_UNUSED_ENTRY(110), 229 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6), 230 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6), 231 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6), 232 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6), 233 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6), 234 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6), 235 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6), 236 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6), 237 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6), 238 HNS3_RX_PTYPE_UNUSED_ENTRY(120), 239 HNS3_RX_PTYPE_UNUSED_ENTRY(121), 240 HNS3_RX_PTYPE_UNUSED_ENTRY(122), 241 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL), 242 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL), 243 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4), 244 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4), 245 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4), 246 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4), 247 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4), 248 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4), 249 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4), 250 HNS3_RX_PTYPE_UNUSED_ENTRY(132), 251 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6), 252 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6), 253 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6), 254 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6), 255 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6), 256 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6), 257 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6), 258 HNS3_RX_PTYPE_UNUSED_ENTRY(140), 259 HNS3_RX_PTYPE_UNUSED_ENTRY(141), 260 HNS3_RX_PTYPE_UNUSED_ENTRY(142), 261 HNS3_RX_PTYPE_UNUSED_ENTRY(143), 262 HNS3_RX_PTYPE_UNUSED_ENTRY(144), 263 HNS3_RX_PTYPE_UNUSED_ENTRY(145), 264 HNS3_RX_PTYPE_UNUSED_ENTRY(146), 265 HNS3_RX_PTYPE_UNUSED_ENTRY(147), 266 HNS3_RX_PTYPE_UNUSED_ENTRY(148), 267 HNS3_RX_PTYPE_UNUSED_ENTRY(149), 268 HNS3_RX_PTYPE_UNUSED_ENTRY(150), 269 HNS3_RX_PTYPE_UNUSED_ENTRY(151), 270 HNS3_RX_PTYPE_UNUSED_ENTRY(152), 271 HNS3_RX_PTYPE_UNUSED_ENTRY(153), 272 HNS3_RX_PTYPE_UNUSED_ENTRY(154), 273 HNS3_RX_PTYPE_UNUSED_ENTRY(155), 274 HNS3_RX_PTYPE_UNUSED_ENTRY(156), 275 HNS3_RX_PTYPE_UNUSED_ENTRY(157), 276 HNS3_RX_PTYPE_UNUSED_ENTRY(158), 277 HNS3_RX_PTYPE_UNUSED_ENTRY(159), 278 HNS3_RX_PTYPE_UNUSED_ENTRY(160), 279 HNS3_RX_PTYPE_UNUSED_ENTRY(161), 280 HNS3_RX_PTYPE_UNUSED_ENTRY(162), 281 HNS3_RX_PTYPE_UNUSED_ENTRY(163), 282 HNS3_RX_PTYPE_UNUSED_ENTRY(164), 283 HNS3_RX_PTYPE_UNUSED_ENTRY(165), 284 HNS3_RX_PTYPE_UNUSED_ENTRY(166), 285 HNS3_RX_PTYPE_UNUSED_ENTRY(167), 286 HNS3_RX_PTYPE_UNUSED_ENTRY(168), 287 HNS3_RX_PTYPE_UNUSED_ENTRY(169), 288 HNS3_RX_PTYPE_UNUSED_ENTRY(170), 289 HNS3_RX_PTYPE_UNUSED_ENTRY(171), 290 HNS3_RX_PTYPE_UNUSED_ENTRY(172), 291 HNS3_RX_PTYPE_UNUSED_ENTRY(173), 292 HNS3_RX_PTYPE_UNUSED_ENTRY(174), 293 HNS3_RX_PTYPE_UNUSED_ENTRY(175), 294 HNS3_RX_PTYPE_UNUSED_ENTRY(176), 295 HNS3_RX_PTYPE_UNUSED_ENTRY(177), 296 HNS3_RX_PTYPE_UNUSED_ENTRY(178), 297 HNS3_RX_PTYPE_UNUSED_ENTRY(179), 298 HNS3_RX_PTYPE_UNUSED_ENTRY(180), 299 HNS3_RX_PTYPE_UNUSED_ENTRY(181), 300 HNS3_RX_PTYPE_UNUSED_ENTRY(182), 301 HNS3_RX_PTYPE_UNUSED_ENTRY(183), 302 HNS3_RX_PTYPE_UNUSED_ENTRY(184), 303 HNS3_RX_PTYPE_UNUSED_ENTRY(185), 304 HNS3_RX_PTYPE_UNUSED_ENTRY(186), 305 HNS3_RX_PTYPE_UNUSED_ENTRY(187), 306 HNS3_RX_PTYPE_UNUSED_ENTRY(188), 307 HNS3_RX_PTYPE_UNUSED_ENTRY(189), 308 HNS3_RX_PTYPE_UNUSED_ENTRY(190), 309 HNS3_RX_PTYPE_UNUSED_ENTRY(191), 310 HNS3_RX_PTYPE_UNUSED_ENTRY(192), 311 HNS3_RX_PTYPE_UNUSED_ENTRY(193), 312 HNS3_RX_PTYPE_UNUSED_ENTRY(194), 313 HNS3_RX_PTYPE_UNUSED_ENTRY(195), 314 HNS3_RX_PTYPE_UNUSED_ENTRY(196), 315 HNS3_RX_PTYPE_UNUSED_ENTRY(197), 316 HNS3_RX_PTYPE_UNUSED_ENTRY(198), 317 HNS3_RX_PTYPE_UNUSED_ENTRY(199), 318 HNS3_RX_PTYPE_UNUSED_ENTRY(200), 319 HNS3_RX_PTYPE_UNUSED_ENTRY(201), 320 HNS3_RX_PTYPE_UNUSED_ENTRY(202), 321 HNS3_RX_PTYPE_UNUSED_ENTRY(203), 322 HNS3_RX_PTYPE_UNUSED_ENTRY(204), 323 HNS3_RX_PTYPE_UNUSED_ENTRY(205), 324 HNS3_RX_PTYPE_UNUSED_ENTRY(206), 325 HNS3_RX_PTYPE_UNUSED_ENTRY(207), 326 HNS3_RX_PTYPE_UNUSED_ENTRY(208), 327 HNS3_RX_PTYPE_UNUSED_ENTRY(209), 328 HNS3_RX_PTYPE_UNUSED_ENTRY(210), 329 HNS3_RX_PTYPE_UNUSED_ENTRY(211), 330 HNS3_RX_PTYPE_UNUSED_ENTRY(212), 331 HNS3_RX_PTYPE_UNUSED_ENTRY(213), 332 HNS3_RX_PTYPE_UNUSED_ENTRY(214), 333 HNS3_RX_PTYPE_UNUSED_ENTRY(215), 334 HNS3_RX_PTYPE_UNUSED_ENTRY(216), 335 HNS3_RX_PTYPE_UNUSED_ENTRY(217), 336 HNS3_RX_PTYPE_UNUSED_ENTRY(218), 337 HNS3_RX_PTYPE_UNUSED_ENTRY(219), 338 HNS3_RX_PTYPE_UNUSED_ENTRY(220), 339 HNS3_RX_PTYPE_UNUSED_ENTRY(221), 340 HNS3_RX_PTYPE_UNUSED_ENTRY(222), 341 HNS3_RX_PTYPE_UNUSED_ENTRY(223), 342 HNS3_RX_PTYPE_UNUSED_ENTRY(224), 343 HNS3_RX_PTYPE_UNUSED_ENTRY(225), 344 HNS3_RX_PTYPE_UNUSED_ENTRY(226), 345 HNS3_RX_PTYPE_UNUSED_ENTRY(227), 346 HNS3_RX_PTYPE_UNUSED_ENTRY(228), 347 HNS3_RX_PTYPE_UNUSED_ENTRY(229), 348 HNS3_RX_PTYPE_UNUSED_ENTRY(230), 349 HNS3_RX_PTYPE_UNUSED_ENTRY(231), 350 HNS3_RX_PTYPE_UNUSED_ENTRY(232), 351 HNS3_RX_PTYPE_UNUSED_ENTRY(233), 352 HNS3_RX_PTYPE_UNUSED_ENTRY(234), 353 HNS3_RX_PTYPE_UNUSED_ENTRY(235), 354 HNS3_RX_PTYPE_UNUSED_ENTRY(236), 355 HNS3_RX_PTYPE_UNUSED_ENTRY(237), 356 HNS3_RX_PTYPE_UNUSED_ENTRY(238), 357 HNS3_RX_PTYPE_UNUSED_ENTRY(239), 358 HNS3_RX_PTYPE_UNUSED_ENTRY(240), 359 HNS3_RX_PTYPE_UNUSED_ENTRY(241), 360 HNS3_RX_PTYPE_UNUSED_ENTRY(242), 361 HNS3_RX_PTYPE_UNUSED_ENTRY(243), 362 HNS3_RX_PTYPE_UNUSED_ENTRY(244), 363 HNS3_RX_PTYPE_UNUSED_ENTRY(245), 364 HNS3_RX_PTYPE_UNUSED_ENTRY(246), 365 HNS3_RX_PTYPE_UNUSED_ENTRY(247), 366 HNS3_RX_PTYPE_UNUSED_ENTRY(248), 367 HNS3_RX_PTYPE_UNUSED_ENTRY(249), 368 HNS3_RX_PTYPE_UNUSED_ENTRY(250), 369 HNS3_RX_PTYPE_UNUSED_ENTRY(251), 370 HNS3_RX_PTYPE_UNUSED_ENTRY(252), 371 HNS3_RX_PTYPE_UNUSED_ENTRY(253), 372 HNS3_RX_PTYPE_UNUSED_ENTRY(254), 373 HNS3_RX_PTYPE_UNUSED_ENTRY(255), 374 }; 375 376 #define HNS3_INVALID_PTYPE \ 377 ARRAY_SIZE(hns3_rx_ptype_tbl) 378 379 static irqreturn_t hns3_irq_handle(int irq, void *vector) 380 { 381 struct hns3_enet_tqp_vector *tqp_vector = vector; 382 383 napi_schedule_irqoff(&tqp_vector->napi); 384 tqp_vector->event_cnt++; 385 386 return IRQ_HANDLED; 387 } 388 389 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 390 { 391 struct hns3_enet_tqp_vector *tqp_vectors; 392 unsigned int i; 393 394 for (i = 0; i < priv->vector_num; i++) { 395 tqp_vectors = &priv->tqp_vector[i]; 396 397 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 398 continue; 399 400 /* clear the affinity mask */ 401 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 402 403 /* release the irq resource */ 404 free_irq(tqp_vectors->vector_irq, tqp_vectors); 405 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 406 } 407 } 408 409 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 410 { 411 struct hns3_enet_tqp_vector *tqp_vectors; 412 int txrx_int_idx = 0; 413 int rx_int_idx = 0; 414 int tx_int_idx = 0; 415 unsigned int i; 416 int ret; 417 418 for (i = 0; i < priv->vector_num; i++) { 419 tqp_vectors = &priv->tqp_vector[i]; 420 421 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 422 continue; 423 424 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 425 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 426 "%s-%s-%s-%d", hns3_driver_name, 427 pci_name(priv->ae_handle->pdev), 428 "TxRx", txrx_int_idx++); 429 txrx_int_idx++; 430 } else if (tqp_vectors->rx_group.ring) { 431 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 432 "%s-%s-%s-%d", hns3_driver_name, 433 pci_name(priv->ae_handle->pdev), 434 "Rx", rx_int_idx++); 435 } else if (tqp_vectors->tx_group.ring) { 436 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 437 "%s-%s-%s-%d", hns3_driver_name, 438 pci_name(priv->ae_handle->pdev), 439 "Tx", tx_int_idx++); 440 } else { 441 /* Skip this unused q_vector */ 442 continue; 443 } 444 445 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 446 447 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN); 448 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 449 tqp_vectors->name, tqp_vectors); 450 if (ret) { 451 netdev_err(priv->netdev, "request irq(%d) fail\n", 452 tqp_vectors->vector_irq); 453 hns3_nic_uninit_irq(priv); 454 return ret; 455 } 456 457 irq_set_affinity_hint(tqp_vectors->vector_irq, 458 &tqp_vectors->affinity_mask); 459 460 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 461 } 462 463 return 0; 464 } 465 466 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 467 u32 mask_en) 468 { 469 writel(mask_en, tqp_vector->mask_addr); 470 } 471 472 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 473 { 474 napi_enable(&tqp_vector->napi); 475 enable_irq(tqp_vector->vector_irq); 476 477 /* enable vector */ 478 hns3_mask_vector_irq(tqp_vector, 1); 479 } 480 481 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 482 { 483 /* disable vector */ 484 hns3_mask_vector_irq(tqp_vector, 0); 485 486 disable_irq(tqp_vector->vector_irq); 487 napi_disable(&tqp_vector->napi); 488 cancel_work_sync(&tqp_vector->rx_group.dim.work); 489 cancel_work_sync(&tqp_vector->tx_group.dim.work); 490 } 491 492 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 493 u32 rl_value) 494 { 495 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 496 497 /* this defines the configuration for RL (Interrupt Rate Limiter). 498 * Rl defines rate of interrupts i.e. number of interrupts-per-second 499 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 500 */ 501 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable && 502 !tqp_vector->rx_group.coal.adapt_enable) 503 /* According to the hardware, the range of rl_reg is 504 * 0-59 and the unit is 4. 505 */ 506 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 507 508 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 509 } 510 511 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 512 u32 gl_value) 513 { 514 u32 new_val; 515 516 if (tqp_vector->rx_group.coal.unit_1us) 517 new_val = gl_value | HNS3_INT_GL_1US; 518 else 519 new_val = hns3_gl_usec_to_reg(gl_value); 520 521 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 522 } 523 524 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 525 u32 gl_value) 526 { 527 u32 new_val; 528 529 if (tqp_vector->tx_group.coal.unit_1us) 530 new_val = gl_value | HNS3_INT_GL_1US; 531 else 532 new_val = hns3_gl_usec_to_reg(gl_value); 533 534 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 535 } 536 537 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector, 538 u32 ql_value) 539 { 540 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET); 541 } 542 543 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector, 544 u32 ql_value) 545 { 546 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET); 547 } 548 549 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector, 550 struct hns3_nic_priv *priv) 551 { 552 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 553 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 554 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 555 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal; 556 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal; 557 558 tx_coal->adapt_enable = ptx_coal->adapt_enable; 559 rx_coal->adapt_enable = prx_coal->adapt_enable; 560 561 tx_coal->int_gl = ptx_coal->int_gl; 562 rx_coal->int_gl = prx_coal->int_gl; 563 564 rx_coal->flow_level = prx_coal->flow_level; 565 tx_coal->flow_level = ptx_coal->flow_level; 566 567 /* device version above V3(include V3), GL can configure 1us 568 * unit, so uses 1us unit. 569 */ 570 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) { 571 tx_coal->unit_1us = 1; 572 rx_coal->unit_1us = 1; 573 } 574 575 if (ae_dev->dev_specs.int_ql_max) { 576 tx_coal->ql_enable = 1; 577 rx_coal->ql_enable = 1; 578 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 579 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 580 tx_coal->int_ql = ptx_coal->int_ql; 581 rx_coal->int_ql = prx_coal->int_ql; 582 } 583 } 584 585 static void 586 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 587 struct hns3_nic_priv *priv) 588 { 589 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 590 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 591 struct hnae3_handle *h = priv->ae_handle; 592 593 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl); 594 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl); 595 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 596 597 if (tx_coal->ql_enable) 598 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql); 599 600 if (rx_coal->ql_enable) 601 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql); 602 } 603 604 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 605 { 606 struct hnae3_handle *h = hns3_get_handle(netdev); 607 struct hnae3_knic_private_info *kinfo = &h->kinfo; 608 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 609 unsigned int queue_size = kinfo->num_tqps; 610 int i, ret; 611 612 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) { 613 netdev_reset_tc(netdev); 614 } else { 615 ret = netdev_set_num_tc(netdev, tc_info->num_tc); 616 if (ret) { 617 netdev_err(netdev, 618 "netdev_set_num_tc fail, ret=%d!\n", ret); 619 return ret; 620 } 621 622 for (i = 0; i < HNAE3_MAX_TC; i++) { 623 if (!test_bit(i, &tc_info->tc_en)) 624 continue; 625 626 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i], 627 tc_info->tqp_offset[i]); 628 } 629 } 630 631 ret = netif_set_real_num_tx_queues(netdev, queue_size); 632 if (ret) { 633 netdev_err(netdev, 634 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret); 635 return ret; 636 } 637 638 ret = netif_set_real_num_rx_queues(netdev, queue_size); 639 if (ret) { 640 netdev_err(netdev, 641 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 642 return ret; 643 } 644 645 return 0; 646 } 647 648 u16 hns3_get_max_available_channels(struct hnae3_handle *h) 649 { 650 u16 alloc_tqps, max_rss_size, rss_size; 651 652 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 653 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc; 654 655 return min_t(u16, rss_size, max_rss_size); 656 } 657 658 static void hns3_tqp_enable(struct hnae3_queue *tqp) 659 { 660 u32 rcb_reg; 661 662 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 663 rcb_reg |= BIT(HNS3_RING_EN_B); 664 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 665 } 666 667 static void hns3_tqp_disable(struct hnae3_queue *tqp) 668 { 669 u32 rcb_reg; 670 671 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 672 rcb_reg &= ~BIT(HNS3_RING_EN_B); 673 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 674 } 675 676 static void hns3_free_rx_cpu_rmap(struct net_device *netdev) 677 { 678 #ifdef CONFIG_RFS_ACCEL 679 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 680 netdev->rx_cpu_rmap = NULL; 681 #endif 682 } 683 684 static int hns3_set_rx_cpu_rmap(struct net_device *netdev) 685 { 686 #ifdef CONFIG_RFS_ACCEL 687 struct hns3_nic_priv *priv = netdev_priv(netdev); 688 struct hns3_enet_tqp_vector *tqp_vector; 689 int i, ret; 690 691 if (!netdev->rx_cpu_rmap) { 692 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num); 693 if (!netdev->rx_cpu_rmap) 694 return -ENOMEM; 695 } 696 697 for (i = 0; i < priv->vector_num; i++) { 698 tqp_vector = &priv->tqp_vector[i]; 699 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap, 700 tqp_vector->vector_irq); 701 if (ret) { 702 hns3_free_rx_cpu_rmap(netdev); 703 return ret; 704 } 705 } 706 #endif 707 return 0; 708 } 709 710 static int hns3_nic_net_up(struct net_device *netdev) 711 { 712 struct hns3_nic_priv *priv = netdev_priv(netdev); 713 struct hnae3_handle *h = priv->ae_handle; 714 int i, j; 715 int ret; 716 717 ret = hns3_nic_reset_all_ring(h); 718 if (ret) 719 return ret; 720 721 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 722 723 /* enable the vectors */ 724 for (i = 0; i < priv->vector_num; i++) 725 hns3_vector_enable(&priv->tqp_vector[i]); 726 727 /* enable rcb */ 728 for (j = 0; j < h->kinfo.num_tqps; j++) 729 hns3_tqp_enable(h->kinfo.tqp[j]); 730 731 /* start the ae_dev */ 732 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 733 if (ret) { 734 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 735 while (j--) 736 hns3_tqp_disable(h->kinfo.tqp[j]); 737 738 for (j = i - 1; j >= 0; j--) 739 hns3_vector_disable(&priv->tqp_vector[j]); 740 } 741 742 return ret; 743 } 744 745 static void hns3_config_xps(struct hns3_nic_priv *priv) 746 { 747 int i; 748 749 for (i = 0; i < priv->vector_num; i++) { 750 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 751 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 752 753 while (ring) { 754 int ret; 755 756 ret = netif_set_xps_queue(priv->netdev, 757 &tqp_vector->affinity_mask, 758 ring->tqp->tqp_index); 759 if (ret) 760 netdev_warn(priv->netdev, 761 "set xps queue failed: %d", ret); 762 763 ring = ring->next; 764 } 765 } 766 } 767 768 static int hns3_nic_net_open(struct net_device *netdev) 769 { 770 struct hns3_nic_priv *priv = netdev_priv(netdev); 771 struct hnae3_handle *h = hns3_get_handle(netdev); 772 struct hnae3_knic_private_info *kinfo; 773 int i, ret; 774 775 if (hns3_nic_resetting(netdev)) 776 return -EBUSY; 777 778 netif_carrier_off(netdev); 779 780 ret = hns3_nic_set_real_num_queue(netdev); 781 if (ret) 782 return ret; 783 784 ret = hns3_nic_net_up(netdev); 785 if (ret) { 786 netdev_err(netdev, "net up fail, ret=%d!\n", ret); 787 return ret; 788 } 789 790 kinfo = &h->kinfo; 791 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 792 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]); 793 794 if (h->ae_algo->ops->set_timer_task) 795 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 796 797 hns3_config_xps(priv); 798 799 netif_dbg(h, drv, netdev, "net open\n"); 800 801 return 0; 802 } 803 804 static void hns3_reset_tx_queue(struct hnae3_handle *h) 805 { 806 struct net_device *ndev = h->kinfo.netdev; 807 struct hns3_nic_priv *priv = netdev_priv(ndev); 808 struct netdev_queue *dev_queue; 809 u32 i; 810 811 for (i = 0; i < h->kinfo.num_tqps; i++) { 812 dev_queue = netdev_get_tx_queue(ndev, 813 priv->ring[i].queue_index); 814 netdev_tx_reset_queue(dev_queue); 815 } 816 } 817 818 static void hns3_nic_net_down(struct net_device *netdev) 819 { 820 struct hns3_nic_priv *priv = netdev_priv(netdev); 821 struct hnae3_handle *h = hns3_get_handle(netdev); 822 const struct hnae3_ae_ops *ops; 823 int i; 824 825 /* disable vectors */ 826 for (i = 0; i < priv->vector_num; i++) 827 hns3_vector_disable(&priv->tqp_vector[i]); 828 829 /* disable rcb */ 830 for (i = 0; i < h->kinfo.num_tqps; i++) 831 hns3_tqp_disable(h->kinfo.tqp[i]); 832 833 /* stop ae_dev */ 834 ops = priv->ae_handle->ae_algo->ops; 835 if (ops->stop) 836 ops->stop(priv->ae_handle); 837 838 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 839 * during reset process, because driver may not be able 840 * to disable the ring through firmware when downing the netdev. 841 */ 842 if (!hns3_nic_resetting(netdev)) 843 hns3_clear_all_ring(priv->ae_handle, false); 844 845 hns3_reset_tx_queue(priv->ae_handle); 846 } 847 848 static int hns3_nic_net_stop(struct net_device *netdev) 849 { 850 struct hns3_nic_priv *priv = netdev_priv(netdev); 851 struct hnae3_handle *h = hns3_get_handle(netdev); 852 853 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 854 return 0; 855 856 netif_dbg(h, drv, netdev, "net stop\n"); 857 858 if (h->ae_algo->ops->set_timer_task) 859 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 860 861 netif_carrier_off(netdev); 862 netif_tx_disable(netdev); 863 864 hns3_nic_net_down(netdev); 865 866 return 0; 867 } 868 869 static int hns3_nic_uc_sync(struct net_device *netdev, 870 const unsigned char *addr) 871 { 872 struct hnae3_handle *h = hns3_get_handle(netdev); 873 874 if (h->ae_algo->ops->add_uc_addr) 875 return h->ae_algo->ops->add_uc_addr(h, addr); 876 877 return 0; 878 } 879 880 static int hns3_nic_uc_unsync(struct net_device *netdev, 881 const unsigned char *addr) 882 { 883 struct hnae3_handle *h = hns3_get_handle(netdev); 884 885 /* need ignore the request of removing device address, because 886 * we store the device address and other addresses of uc list 887 * in the function's mac filter list. 888 */ 889 if (ether_addr_equal(addr, netdev->dev_addr)) 890 return 0; 891 892 if (h->ae_algo->ops->rm_uc_addr) 893 return h->ae_algo->ops->rm_uc_addr(h, addr); 894 895 return 0; 896 } 897 898 static int hns3_nic_mc_sync(struct net_device *netdev, 899 const unsigned char *addr) 900 { 901 struct hnae3_handle *h = hns3_get_handle(netdev); 902 903 if (h->ae_algo->ops->add_mc_addr) 904 return h->ae_algo->ops->add_mc_addr(h, addr); 905 906 return 0; 907 } 908 909 static int hns3_nic_mc_unsync(struct net_device *netdev, 910 const unsigned char *addr) 911 { 912 struct hnae3_handle *h = hns3_get_handle(netdev); 913 914 if (h->ae_algo->ops->rm_mc_addr) 915 return h->ae_algo->ops->rm_mc_addr(h, addr); 916 917 return 0; 918 } 919 920 static u8 hns3_get_netdev_flags(struct net_device *netdev) 921 { 922 u8 flags = 0; 923 924 if (netdev->flags & IFF_PROMISC) 925 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 926 else if (netdev->flags & IFF_ALLMULTI) 927 flags = HNAE3_USER_MPE; 928 929 return flags; 930 } 931 932 static void hns3_nic_set_rx_mode(struct net_device *netdev) 933 { 934 struct hnae3_handle *h = hns3_get_handle(netdev); 935 u8 new_flags; 936 937 new_flags = hns3_get_netdev_flags(netdev); 938 939 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 940 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync); 941 942 /* User mode Promisc mode enable and vlan filtering is disabled to 943 * let all packets in. 944 */ 945 h->netdev_flags = new_flags; 946 hns3_request_update_promisc_mode(h); 947 } 948 949 void hns3_request_update_promisc_mode(struct hnae3_handle *handle) 950 { 951 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 952 953 if (ops->request_update_promisc_mode) 954 ops->request_update_promisc_mode(handle); 955 } 956 957 static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring) 958 { 959 struct hns3_tx_spare *tx_spare = ring->tx_spare; 960 u32 ntc, ntu; 961 962 /* This smp_load_acquire() pairs with smp_store_release() in 963 * hns3_tx_spare_update() called in tx desc cleaning process. 964 */ 965 ntc = smp_load_acquire(&tx_spare->last_to_clean); 966 ntu = tx_spare->next_to_use; 967 968 if (ntc > ntu) 969 return ntc - ntu - 1; 970 971 /* The free tx buffer is divided into two part, so pick the 972 * larger one. 973 */ 974 return (ntc > (tx_spare->len - ntu) ? ntc : 975 (tx_spare->len - ntu)) - 1; 976 } 977 978 static void hns3_tx_spare_update(struct hns3_enet_ring *ring) 979 { 980 struct hns3_tx_spare *tx_spare = ring->tx_spare; 981 982 if (!tx_spare || 983 tx_spare->last_to_clean == tx_spare->next_to_clean) 984 return; 985 986 /* This smp_store_release() pairs with smp_load_acquire() in 987 * hns3_tx_spare_space() called in xmit process. 988 */ 989 smp_store_release(&tx_spare->last_to_clean, 990 tx_spare->next_to_clean); 991 } 992 993 static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring, 994 struct sk_buff *skb, 995 u32 space) 996 { 997 u32 len = skb->len <= ring->tx_copybreak ? skb->len : 998 skb_headlen(skb); 999 1000 if (len > ring->tx_copybreak) 1001 return false; 1002 1003 if (ALIGN(len, dma_get_cache_alignment()) > space) { 1004 u64_stats_update_begin(&ring->syncp); 1005 ring->stats.tx_spare_full++; 1006 u64_stats_update_end(&ring->syncp); 1007 return false; 1008 } 1009 1010 return true; 1011 } 1012 1013 static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring, 1014 struct sk_buff *skb, 1015 u32 space) 1016 { 1017 if (skb->len <= ring->tx_copybreak || !tx_sgl || 1018 (!skb_has_frag_list(skb) && 1019 skb_shinfo(skb)->nr_frags < tx_sgl)) 1020 return false; 1021 1022 if (space < HNS3_MAX_SGL_SIZE) { 1023 u64_stats_update_begin(&ring->syncp); 1024 ring->stats.tx_spare_full++; 1025 u64_stats_update_end(&ring->syncp); 1026 return false; 1027 } 1028 1029 return true; 1030 } 1031 1032 static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring) 1033 { 1034 struct hns3_tx_spare *tx_spare; 1035 struct page *page; 1036 u32 alloc_size; 1037 dma_addr_t dma; 1038 int order; 1039 1040 alloc_size = tx_spare_buf_size ? tx_spare_buf_size : 1041 ring->tqp->handle->kinfo.tx_spare_buf_size; 1042 if (!alloc_size) 1043 return; 1044 1045 order = get_order(alloc_size); 1046 tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare), 1047 GFP_KERNEL); 1048 if (!tx_spare) { 1049 /* The driver still work without the tx spare buffer */ 1050 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n"); 1051 return; 1052 } 1053 1054 page = alloc_pages_node(dev_to_node(ring_to_dev(ring)), 1055 GFP_KERNEL, order); 1056 if (!page) { 1057 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n"); 1058 devm_kfree(ring_to_dev(ring), tx_spare); 1059 return; 1060 } 1061 1062 dma = dma_map_page(ring_to_dev(ring), page, 0, 1063 PAGE_SIZE << order, DMA_TO_DEVICE); 1064 if (dma_mapping_error(ring_to_dev(ring), dma)) { 1065 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n"); 1066 put_page(page); 1067 devm_kfree(ring_to_dev(ring), tx_spare); 1068 return; 1069 } 1070 1071 tx_spare->dma = dma; 1072 tx_spare->buf = page_address(page); 1073 tx_spare->len = PAGE_SIZE << order; 1074 ring->tx_spare = tx_spare; 1075 } 1076 1077 /* Use hns3_tx_spare_space() to make sure there is enough buffer 1078 * before calling below function to allocate tx buffer. 1079 */ 1080 static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring, 1081 unsigned int size, dma_addr_t *dma, 1082 u32 *cb_len) 1083 { 1084 struct hns3_tx_spare *tx_spare = ring->tx_spare; 1085 u32 ntu = tx_spare->next_to_use; 1086 1087 size = ALIGN(size, dma_get_cache_alignment()); 1088 *cb_len = size; 1089 1090 /* Tx spare buffer wraps back here because the end of 1091 * freed tx buffer is not enough. 1092 */ 1093 if (ntu + size > tx_spare->len) { 1094 *cb_len += (tx_spare->len - ntu); 1095 ntu = 0; 1096 } 1097 1098 tx_spare->next_to_use = ntu + size; 1099 if (tx_spare->next_to_use == tx_spare->len) 1100 tx_spare->next_to_use = 0; 1101 1102 *dma = tx_spare->dma + ntu; 1103 1104 return tx_spare->buf + ntu; 1105 } 1106 1107 static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len) 1108 { 1109 struct hns3_tx_spare *tx_spare = ring->tx_spare; 1110 1111 if (len > tx_spare->next_to_use) { 1112 len -= tx_spare->next_to_use; 1113 tx_spare->next_to_use = tx_spare->len - len; 1114 } else { 1115 tx_spare->next_to_use -= len; 1116 } 1117 } 1118 1119 static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring, 1120 struct hns3_desc_cb *cb) 1121 { 1122 struct hns3_tx_spare *tx_spare = ring->tx_spare; 1123 u32 ntc = tx_spare->next_to_clean; 1124 u32 len = cb->length; 1125 1126 tx_spare->next_to_clean += len; 1127 1128 if (tx_spare->next_to_clean >= tx_spare->len) { 1129 tx_spare->next_to_clean -= tx_spare->len; 1130 1131 if (tx_spare->next_to_clean) { 1132 ntc = 0; 1133 len = tx_spare->next_to_clean; 1134 } 1135 } 1136 1137 /* This tx spare buffer is only really reclaimed after calling 1138 * hns3_tx_spare_update(), so it is still safe to use the info in 1139 * the tx buffer to do the dma sync or sg unmapping after 1140 * tx_spare->next_to_clean is moved forword. 1141 */ 1142 if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) { 1143 dma_addr_t dma = tx_spare->dma + ntc; 1144 1145 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len, 1146 DMA_TO_DEVICE); 1147 } else { 1148 struct sg_table *sgt = tx_spare->buf + ntc; 1149 1150 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents, 1151 DMA_TO_DEVICE); 1152 } 1153 } 1154 1155 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs, 1156 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes) 1157 { 1158 u32 l4_offset, hdr_len; 1159 union l3_hdr_info l3; 1160 union l4_hdr_info l4; 1161 u32 l4_paylen; 1162 int ret; 1163 1164 if (!skb_is_gso(skb)) 1165 return 0; 1166 1167 ret = skb_cow_head(skb, 0); 1168 if (unlikely(ret < 0)) 1169 return ret; 1170 1171 l3.hdr = skb_network_header(skb); 1172 l4.hdr = skb_transport_header(skb); 1173 1174 /* Software should clear the IPv4's checksum field when tso is 1175 * needed. 1176 */ 1177 if (l3.v4->version == 4) 1178 l3.v4->check = 0; 1179 1180 /* tunnel packet */ 1181 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 1182 SKB_GSO_GRE_CSUM | 1183 SKB_GSO_UDP_TUNNEL | 1184 SKB_GSO_UDP_TUNNEL_CSUM)) { 1185 /* reset l3&l4 pointers from outer to inner headers */ 1186 l3.hdr = skb_inner_network_header(skb); 1187 l4.hdr = skb_inner_transport_header(skb); 1188 1189 /* Software should clear the IPv4's checksum field when 1190 * tso is needed. 1191 */ 1192 if (l3.v4->version == 4) 1193 l3.v4->check = 0; 1194 } 1195 1196 /* normal or tunnel packet */ 1197 l4_offset = l4.hdr - skb->data; 1198 1199 /* remove payload length from inner pseudo checksum when tso */ 1200 l4_paylen = skb->len - l4_offset; 1201 1202 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 1203 hdr_len = sizeof(*l4.udp) + l4_offset; 1204 csum_replace_by_diff(&l4.udp->check, 1205 (__force __wsum)htonl(l4_paylen)); 1206 } else { 1207 hdr_len = (l4.tcp->doff << 2) + l4_offset; 1208 csum_replace_by_diff(&l4.tcp->check, 1209 (__force __wsum)htonl(l4_paylen)); 1210 } 1211 1212 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len; 1213 1214 /* find the txbd field values */ 1215 *paylen_fdop_ol4cs = skb->len - hdr_len; 1216 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 1217 1218 /* offload outer UDP header checksum */ 1219 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM) 1220 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1); 1221 1222 /* get MSS for TSO */ 1223 *mss = skb_shinfo(skb)->gso_size; 1224 1225 trace_hns3_tso(skb); 1226 1227 return 0; 1228 } 1229 1230 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 1231 u8 *il4_proto) 1232 { 1233 union l3_hdr_info l3; 1234 unsigned char *l4_hdr; 1235 unsigned char *exthdr; 1236 u8 l4_proto_tmp; 1237 __be16 frag_off; 1238 1239 /* find outer header point */ 1240 l3.hdr = skb_network_header(skb); 1241 l4_hdr = skb_transport_header(skb); 1242 1243 if (skb->protocol == htons(ETH_P_IPV6)) { 1244 exthdr = l3.hdr + sizeof(*l3.v6); 1245 l4_proto_tmp = l3.v6->nexthdr; 1246 if (l4_hdr != exthdr) 1247 ipv6_skip_exthdr(skb, exthdr - skb->data, 1248 &l4_proto_tmp, &frag_off); 1249 } else if (skb->protocol == htons(ETH_P_IP)) { 1250 l4_proto_tmp = l3.v4->protocol; 1251 } else { 1252 return -EINVAL; 1253 } 1254 1255 *ol4_proto = l4_proto_tmp; 1256 1257 /* tunnel packet */ 1258 if (!skb->encapsulation) { 1259 *il4_proto = 0; 1260 return 0; 1261 } 1262 1263 /* find inner header point */ 1264 l3.hdr = skb_inner_network_header(skb); 1265 l4_hdr = skb_inner_transport_header(skb); 1266 1267 if (l3.v6->version == 6) { 1268 exthdr = l3.hdr + sizeof(*l3.v6); 1269 l4_proto_tmp = l3.v6->nexthdr; 1270 if (l4_hdr != exthdr) 1271 ipv6_skip_exthdr(skb, exthdr - skb->data, 1272 &l4_proto_tmp, &frag_off); 1273 } else if (l3.v4->version == 4) { 1274 l4_proto_tmp = l3.v4->protocol; 1275 } 1276 1277 *il4_proto = l4_proto_tmp; 1278 1279 return 0; 1280 } 1281 1282 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 1283 * and it is udp packet, which has a dest port as the IANA assigned. 1284 * the hardware is expected to do the checksum offload, but the 1285 * hardware will not do the checksum offload when udp dest port is 1286 * 4789, 4790 or 6081. 1287 */ 1288 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 1289 { 1290 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 1291 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 1292 union l4_hdr_info l4; 1293 1294 /* device version above V3(include V3), the hardware can 1295 * do this checksum offload. 1296 */ 1297 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 1298 return false; 1299 1300 l4.hdr = skb_transport_header(skb); 1301 1302 if (!(!skb->encapsulation && 1303 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) || 1304 l4.udp->dest == htons(GENEVE_UDP_PORT) || 1305 l4.udp->dest == htons(4790)))) 1306 return false; 1307 1308 return true; 1309 } 1310 1311 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 1312 u32 *ol_type_vlan_len_msec) 1313 { 1314 u32 l2_len, l3_len, l4_len; 1315 unsigned char *il2_hdr; 1316 union l3_hdr_info l3; 1317 union l4_hdr_info l4; 1318 1319 l3.hdr = skb_network_header(skb); 1320 l4.hdr = skb_transport_header(skb); 1321 1322 /* compute OL2 header size, defined in 2 Bytes */ 1323 l2_len = l3.hdr - skb->data; 1324 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1); 1325 1326 /* compute OL3 header size, defined in 4 Bytes */ 1327 l3_len = l4.hdr - l3.hdr; 1328 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2); 1329 1330 il2_hdr = skb_inner_mac_header(skb); 1331 /* compute OL4 header size, defined in 4 Bytes */ 1332 l4_len = il2_hdr - l4.hdr; 1333 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2); 1334 1335 /* define outer network header type */ 1336 if (skb->protocol == htons(ETH_P_IP)) { 1337 if (skb_is_gso(skb)) 1338 hns3_set_field(*ol_type_vlan_len_msec, 1339 HNS3_TXD_OL3T_S, 1340 HNS3_OL3T_IPV4_CSUM); 1341 else 1342 hns3_set_field(*ol_type_vlan_len_msec, 1343 HNS3_TXD_OL3T_S, 1344 HNS3_OL3T_IPV4_NO_CSUM); 1345 } else if (skb->protocol == htons(ETH_P_IPV6)) { 1346 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 1347 HNS3_OL3T_IPV6); 1348 } 1349 1350 if (ol4_proto == IPPROTO_UDP) 1351 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 1352 HNS3_TUN_MAC_IN_UDP); 1353 else if (ol4_proto == IPPROTO_GRE) 1354 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 1355 HNS3_TUN_NVGRE); 1356 } 1357 1358 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 1359 u8 il4_proto, u32 *type_cs_vlan_tso, 1360 u32 *ol_type_vlan_len_msec) 1361 { 1362 unsigned char *l2_hdr = skb->data; 1363 u32 l4_proto = ol4_proto; 1364 union l4_hdr_info l4; 1365 union l3_hdr_info l3; 1366 u32 l2_len, l3_len; 1367 1368 l4.hdr = skb_transport_header(skb); 1369 l3.hdr = skb_network_header(skb); 1370 1371 /* handle encapsulation skb */ 1372 if (skb->encapsulation) { 1373 /* If this is a not UDP/GRE encapsulation skb */ 1374 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) { 1375 /* drop the skb tunnel packet if hardware don't support, 1376 * because hardware can't calculate csum when TSO. 1377 */ 1378 if (skb_is_gso(skb)) 1379 return -EDOM; 1380 1381 /* the stack computes the IP header already, 1382 * driver calculate l4 checksum when not TSO. 1383 */ 1384 return skb_checksum_help(skb); 1385 } 1386 1387 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec); 1388 1389 /* switch to inner header */ 1390 l2_hdr = skb_inner_mac_header(skb); 1391 l3.hdr = skb_inner_network_header(skb); 1392 l4.hdr = skb_inner_transport_header(skb); 1393 l4_proto = il4_proto; 1394 } 1395 1396 if (l3.v4->version == 4) { 1397 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 1398 HNS3_L3T_IPV4); 1399 1400 /* the stack computes the IP header already, the only time we 1401 * need the hardware to recompute it is in the case of TSO. 1402 */ 1403 if (skb_is_gso(skb)) 1404 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 1405 } else if (l3.v6->version == 6) { 1406 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 1407 HNS3_L3T_IPV6); 1408 } 1409 1410 /* compute inner(/normal) L2 header size, defined in 2 Bytes */ 1411 l2_len = l3.hdr - l2_hdr; 1412 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 1413 1414 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 1415 l3_len = l4.hdr - l3.hdr; 1416 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 1417 1418 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 1419 switch (l4_proto) { 1420 case IPPROTO_TCP: 1421 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1422 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1423 HNS3_L4T_TCP); 1424 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1425 l4.tcp->doff); 1426 break; 1427 case IPPROTO_UDP: 1428 if (hns3_tunnel_csum_bug(skb)) 1429 return skb_checksum_help(skb); 1430 1431 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1432 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1433 HNS3_L4T_UDP); 1434 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1435 (sizeof(struct udphdr) >> 2)); 1436 break; 1437 case IPPROTO_SCTP: 1438 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1439 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1440 HNS3_L4T_SCTP); 1441 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1442 (sizeof(struct sctphdr) >> 2)); 1443 break; 1444 default: 1445 /* drop the skb tunnel packet if hardware don't support, 1446 * because hardware can't calculate csum when TSO. 1447 */ 1448 if (skb_is_gso(skb)) 1449 return -EDOM; 1450 1451 /* the stack computes the IP header already, 1452 * driver calculate l4 checksum when not TSO. 1453 */ 1454 return skb_checksum_help(skb); 1455 } 1456 1457 return 0; 1458 } 1459 1460 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring, 1461 struct sk_buff *skb) 1462 { 1463 struct hnae3_handle *handle = tx_ring->tqp->handle; 1464 struct hnae3_ae_dev *ae_dev; 1465 struct vlan_ethhdr *vhdr; 1466 int rc; 1467 1468 if (!(skb->protocol == htons(ETH_P_8021Q) || 1469 skb_vlan_tag_present(skb))) 1470 return 0; 1471 1472 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert 1473 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it 1474 * will cause RAS error. 1475 */ 1476 ae_dev = pci_get_drvdata(handle->pdev); 1477 if (unlikely(skb_vlan_tagged_multi(skb) && 1478 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 && 1479 handle->port_base_vlan_state == 1480 HNAE3_PORT_BASE_VLAN_ENABLE)) 1481 return -EINVAL; 1482 1483 if (skb->protocol == htons(ETH_P_8021Q) && 1484 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 1485 /* When HW VLAN acceleration is turned off, and the stack 1486 * sets the protocol to 802.1q, the driver just need to 1487 * set the protocol to the encapsulated ethertype. 1488 */ 1489 skb->protocol = vlan_get_protocol(skb); 1490 return 0; 1491 } 1492 1493 if (skb_vlan_tag_present(skb)) { 1494 /* Based on hw strategy, use out_vtag in two layer tag case, 1495 * and use inner_vtag in one tag case. 1496 */ 1497 if (skb->protocol == htons(ETH_P_8021Q) && 1498 handle->port_base_vlan_state == 1499 HNAE3_PORT_BASE_VLAN_DISABLE) 1500 rc = HNS3_OUTER_VLAN_TAG; 1501 else 1502 rc = HNS3_INNER_VLAN_TAG; 1503 1504 skb->protocol = vlan_get_protocol(skb); 1505 return rc; 1506 } 1507 1508 rc = skb_cow_head(skb, 0); 1509 if (unlikely(rc < 0)) 1510 return rc; 1511 1512 vhdr = (struct vlan_ethhdr *)skb->data; 1513 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT) 1514 & VLAN_PRIO_MASK); 1515 1516 skb->protocol = vlan_get_protocol(skb); 1517 return 0; 1518 } 1519 1520 /* check if the hardware is capable of checksum offloading */ 1521 static bool hns3_check_hw_tx_csum(struct sk_buff *skb) 1522 { 1523 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 1524 1525 /* Kindly note, due to backward compatibility of the TX descriptor, 1526 * HW checksum of the non-IP packets and GSO packets is handled at 1527 * different place in the following code 1528 */ 1529 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) || 1530 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state)) 1531 return false; 1532 1533 return true; 1534 } 1535 1536 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring, 1537 struct sk_buff *skb, struct hns3_desc *desc, 1538 struct hns3_desc_cb *desc_cb) 1539 { 1540 u32 ol_type_vlan_len_msec = 0; 1541 u32 paylen_ol4cs = skb->len; 1542 u32 type_cs_vlan_tso = 0; 1543 u16 mss_hw_csum = 0; 1544 u16 inner_vtag = 0; 1545 u16 out_vtag = 0; 1546 int ret; 1547 1548 ret = hns3_handle_vtags(ring, skb); 1549 if (unlikely(ret < 0)) { 1550 u64_stats_update_begin(&ring->syncp); 1551 ring->stats.tx_vlan_err++; 1552 u64_stats_update_end(&ring->syncp); 1553 return ret; 1554 } else if (ret == HNS3_INNER_VLAN_TAG) { 1555 inner_vtag = skb_vlan_tag_get(skb); 1556 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1557 VLAN_PRIO_MASK; 1558 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1); 1559 } else if (ret == HNS3_OUTER_VLAN_TAG) { 1560 out_vtag = skb_vlan_tag_get(skb); 1561 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1562 VLAN_PRIO_MASK; 1563 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B, 1564 1); 1565 } 1566 1567 desc_cb->send_bytes = skb->len; 1568 1569 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1570 u8 ol4_proto, il4_proto; 1571 1572 if (hns3_check_hw_tx_csum(skb)) { 1573 /* set checksum start and offset, defined in 2 Bytes */ 1574 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_CSUM_START_S, 1575 skb_checksum_start_offset(skb) >> 1); 1576 hns3_set_field(ol_type_vlan_len_msec, 1577 HNS3_TXD_CSUM_OFFSET_S, 1578 skb->csum_offset >> 1); 1579 mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B); 1580 goto out_hw_tx_csum; 1581 } 1582 1583 skb_reset_mac_len(skb); 1584 1585 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1586 if (unlikely(ret < 0)) { 1587 u64_stats_update_begin(&ring->syncp); 1588 ring->stats.tx_l4_proto_err++; 1589 u64_stats_update_end(&ring->syncp); 1590 return ret; 1591 } 1592 1593 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto, 1594 &type_cs_vlan_tso, 1595 &ol_type_vlan_len_msec); 1596 if (unlikely(ret < 0)) { 1597 u64_stats_update_begin(&ring->syncp); 1598 ring->stats.tx_l2l3l4_err++; 1599 u64_stats_update_end(&ring->syncp); 1600 return ret; 1601 } 1602 1603 ret = hns3_set_tso(skb, &paylen_ol4cs, &mss_hw_csum, 1604 &type_cs_vlan_tso, &desc_cb->send_bytes); 1605 if (unlikely(ret < 0)) { 1606 u64_stats_update_begin(&ring->syncp); 1607 ring->stats.tx_tso_err++; 1608 u64_stats_update_end(&ring->syncp); 1609 return ret; 1610 } 1611 } 1612 1613 out_hw_tx_csum: 1614 /* Set txbd */ 1615 desc->tx.ol_type_vlan_len_msec = 1616 cpu_to_le32(ol_type_vlan_len_msec); 1617 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso); 1618 desc->tx.paylen_ol4cs = cpu_to_le32(paylen_ol4cs); 1619 desc->tx.mss_hw_csum = cpu_to_le16(mss_hw_csum); 1620 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1621 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1622 1623 return 0; 1624 } 1625 1626 static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma, 1627 unsigned int size) 1628 { 1629 #define HNS3_LIKELY_BD_NUM 1 1630 1631 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1632 unsigned int frag_buf_num; 1633 int k, sizeoflast; 1634 1635 if (likely(size <= HNS3_MAX_BD_SIZE)) { 1636 desc->addr = cpu_to_le64(dma); 1637 desc->tx.send_size = cpu_to_le16(size); 1638 desc->tx.bdtp_fe_sc_vld_ra_ri = 1639 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1640 1641 trace_hns3_tx_desc(ring, ring->next_to_use); 1642 ring_ptr_move_fw(ring, next_to_use); 1643 return HNS3_LIKELY_BD_NUM; 1644 } 1645 1646 frag_buf_num = hns3_tx_bd_count(size); 1647 sizeoflast = size % HNS3_MAX_BD_SIZE; 1648 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1649 1650 /* When frag size is bigger than hardware limit, split this frag */ 1651 for (k = 0; k < frag_buf_num; k++) { 1652 /* now, fill the descriptor */ 1653 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1654 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1655 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1656 desc->tx.bdtp_fe_sc_vld_ra_ri = 1657 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1658 1659 trace_hns3_tx_desc(ring, ring->next_to_use); 1660 /* move ring pointer to next */ 1661 ring_ptr_move_fw(ring, next_to_use); 1662 1663 desc = &ring->desc[ring->next_to_use]; 1664 } 1665 1666 return frag_buf_num; 1667 } 1668 1669 static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv, 1670 unsigned int type) 1671 { 1672 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1673 struct device *dev = ring_to_dev(ring); 1674 unsigned int size; 1675 dma_addr_t dma; 1676 1677 if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) { 1678 struct sk_buff *skb = (struct sk_buff *)priv; 1679 1680 size = skb_headlen(skb); 1681 if (!size) 1682 return 0; 1683 1684 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1685 } else if (type & DESC_TYPE_BOUNCE_HEAD) { 1686 /* Head data has been filled in hns3_handle_tx_bounce(), 1687 * just return 0 here. 1688 */ 1689 return 0; 1690 } else { 1691 skb_frag_t *frag = (skb_frag_t *)priv; 1692 1693 size = skb_frag_size(frag); 1694 if (!size) 1695 return 0; 1696 1697 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1698 } 1699 1700 if (unlikely(dma_mapping_error(dev, dma))) { 1701 u64_stats_update_begin(&ring->syncp); 1702 ring->stats.sw_err_cnt++; 1703 u64_stats_update_end(&ring->syncp); 1704 return -ENOMEM; 1705 } 1706 1707 desc_cb->priv = priv; 1708 desc_cb->length = size; 1709 desc_cb->dma = dma; 1710 desc_cb->type = type; 1711 1712 return hns3_fill_desc(ring, dma, size); 1713 } 1714 1715 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1716 unsigned int bd_num) 1717 { 1718 unsigned int size; 1719 int i; 1720 1721 size = skb_headlen(skb); 1722 while (size > HNS3_MAX_BD_SIZE) { 1723 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1724 size -= HNS3_MAX_BD_SIZE; 1725 1726 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1727 return bd_num; 1728 } 1729 1730 if (size) { 1731 bd_size[bd_num++] = size; 1732 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1733 return bd_num; 1734 } 1735 1736 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1737 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1738 size = skb_frag_size(frag); 1739 if (!size) 1740 continue; 1741 1742 while (size > HNS3_MAX_BD_SIZE) { 1743 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1744 size -= HNS3_MAX_BD_SIZE; 1745 1746 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1747 return bd_num; 1748 } 1749 1750 bd_size[bd_num++] = size; 1751 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1752 return bd_num; 1753 } 1754 1755 return bd_num; 1756 } 1757 1758 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1759 u8 max_non_tso_bd_num, unsigned int bd_num, 1760 unsigned int recursion_level) 1761 { 1762 #define HNS3_MAX_RECURSION_LEVEL 24 1763 1764 struct sk_buff *frag_skb; 1765 1766 /* If the total len is within the max bd limit */ 1767 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level && 1768 !skb_has_frag_list(skb) && 1769 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num)) 1770 return skb_shinfo(skb)->nr_frags + 1U; 1771 1772 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL)) 1773 return UINT_MAX; 1774 1775 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num); 1776 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM) 1777 return bd_num; 1778 1779 skb_walk_frags(skb, frag_skb) { 1780 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num, 1781 bd_num, recursion_level + 1); 1782 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1783 return bd_num; 1784 } 1785 1786 return bd_num; 1787 } 1788 1789 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb) 1790 { 1791 if (!skb->encapsulation) 1792 return skb_transport_offset(skb) + tcp_hdrlen(skb); 1793 1794 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb); 1795 } 1796 1797 /* HW need every continuous max_non_tso_bd_num buffer data to be larger 1798 * than MSS, we simplify it by ensuring skb_headlen + the first continuous 1799 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss, 1800 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger 1801 * than MSS except the last max_non_tso_bd_num - 1 frags. 1802 */ 1803 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size, 1804 unsigned int bd_num, u8 max_non_tso_bd_num) 1805 { 1806 unsigned int tot_len = 0; 1807 int i; 1808 1809 for (i = 0; i < max_non_tso_bd_num - 1U; i++) 1810 tot_len += bd_size[i]; 1811 1812 /* ensure the first max_non_tso_bd_num frags is greater than 1813 * mss + header 1814 */ 1815 if (tot_len + bd_size[max_non_tso_bd_num - 1U] < 1816 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb)) 1817 return true; 1818 1819 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater 1820 * than mss except the last one. 1821 */ 1822 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) { 1823 tot_len -= bd_size[i]; 1824 tot_len += bd_size[i + max_non_tso_bd_num - 1U]; 1825 1826 if (tot_len < skb_shinfo(skb)->gso_size) 1827 return true; 1828 } 1829 1830 return false; 1831 } 1832 1833 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size) 1834 { 1835 int i; 1836 1837 for (i = 0; i < MAX_SKB_FRAGS; i++) 1838 size[i] = skb_frag_size(&shinfo->frags[i]); 1839 } 1840 1841 static int hns3_skb_linearize(struct hns3_enet_ring *ring, 1842 struct sk_buff *skb, 1843 u8 max_non_tso_bd_num, 1844 unsigned int bd_num) 1845 { 1846 /* 'bd_num == UINT_MAX' means the skb' fraglist has a 1847 * recursion level of over HNS3_MAX_RECURSION_LEVEL. 1848 */ 1849 if (bd_num == UINT_MAX) { 1850 u64_stats_update_begin(&ring->syncp); 1851 ring->stats.over_max_recursion++; 1852 u64_stats_update_end(&ring->syncp); 1853 return -ENOMEM; 1854 } 1855 1856 /* The skb->len has exceeded the hw limitation, linearization 1857 * will not help. 1858 */ 1859 if (skb->len > HNS3_MAX_TSO_SIZE || 1860 (!skb_is_gso(skb) && skb->len > 1861 HNS3_MAX_NON_TSO_SIZE(max_non_tso_bd_num))) { 1862 u64_stats_update_begin(&ring->syncp); 1863 ring->stats.hw_limitation++; 1864 u64_stats_update_end(&ring->syncp); 1865 return -ENOMEM; 1866 } 1867 1868 if (__skb_linearize(skb)) { 1869 u64_stats_update_begin(&ring->syncp); 1870 ring->stats.sw_err_cnt++; 1871 u64_stats_update_end(&ring->syncp); 1872 return -ENOMEM; 1873 } 1874 1875 return 0; 1876 } 1877 1878 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring, 1879 struct net_device *netdev, 1880 struct sk_buff *skb) 1881 { 1882 struct hns3_nic_priv *priv = netdev_priv(netdev); 1883 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num; 1884 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U]; 1885 unsigned int bd_num; 1886 1887 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0); 1888 if (unlikely(bd_num > max_non_tso_bd_num)) { 1889 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) && 1890 !hns3_skb_need_linearized(skb, bd_size, bd_num, 1891 max_non_tso_bd_num)) { 1892 trace_hns3_over_max_bd(skb); 1893 goto out; 1894 } 1895 1896 if (hns3_skb_linearize(ring, skb, max_non_tso_bd_num, 1897 bd_num)) 1898 return -ENOMEM; 1899 1900 bd_num = hns3_tx_bd_count(skb->len); 1901 1902 u64_stats_update_begin(&ring->syncp); 1903 ring->stats.tx_copy++; 1904 u64_stats_update_end(&ring->syncp); 1905 } 1906 1907 out: 1908 if (likely(ring_space(ring) >= bd_num)) 1909 return bd_num; 1910 1911 netif_stop_subqueue(netdev, ring->queue_index); 1912 smp_mb(); /* Memory barrier before checking ring_space */ 1913 1914 /* Start queue in case hns3_clean_tx_ring has just made room 1915 * available and has not seen the queue stopped state performed 1916 * by netif_stop_subqueue above. 1917 */ 1918 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) && 1919 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 1920 netif_start_subqueue(netdev, ring->queue_index); 1921 return bd_num; 1922 } 1923 1924 u64_stats_update_begin(&ring->syncp); 1925 ring->stats.tx_busy++; 1926 u64_stats_update_end(&ring->syncp); 1927 1928 return -EBUSY; 1929 } 1930 1931 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1932 { 1933 struct device *dev = ring_to_dev(ring); 1934 unsigned int i; 1935 1936 for (i = 0; i < ring->desc_num; i++) { 1937 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1938 struct hns3_desc_cb *desc_cb; 1939 1940 memset(desc, 0, sizeof(*desc)); 1941 1942 /* check if this is where we started */ 1943 if (ring->next_to_use == next_to_use_orig) 1944 break; 1945 1946 /* rollback one */ 1947 ring_ptr_move_bw(ring, next_to_use); 1948 1949 desc_cb = &ring->desc_cb[ring->next_to_use]; 1950 1951 if (!desc_cb->dma) 1952 continue; 1953 1954 /* unmap the descriptor dma address */ 1955 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB)) 1956 dma_unmap_single(dev, desc_cb->dma, desc_cb->length, 1957 DMA_TO_DEVICE); 1958 else if (desc_cb->type & 1959 (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) 1960 hns3_tx_spare_rollback(ring, desc_cb->length); 1961 else if (desc_cb->length) 1962 dma_unmap_page(dev, desc_cb->dma, desc_cb->length, 1963 DMA_TO_DEVICE); 1964 1965 desc_cb->length = 0; 1966 desc_cb->dma = 0; 1967 desc_cb->type = DESC_TYPE_UNKNOWN; 1968 } 1969 } 1970 1971 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring, 1972 struct sk_buff *skb, unsigned int type) 1973 { 1974 struct sk_buff *frag_skb; 1975 int i, ret, bd_num = 0; 1976 1977 ret = hns3_map_and_fill_desc(ring, skb, type); 1978 if (unlikely(ret < 0)) 1979 return ret; 1980 1981 bd_num += ret; 1982 1983 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1984 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1985 1986 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE); 1987 if (unlikely(ret < 0)) 1988 return ret; 1989 1990 bd_num += ret; 1991 } 1992 1993 skb_walk_frags(skb, frag_skb) { 1994 ret = hns3_fill_skb_to_desc(ring, frag_skb, 1995 DESC_TYPE_FRAGLIST_SKB); 1996 if (unlikely(ret < 0)) 1997 return ret; 1998 1999 bd_num += ret; 2000 } 2001 2002 return bd_num; 2003 } 2004 2005 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num, 2006 bool doorbell) 2007 { 2008 ring->pending_buf += num; 2009 2010 if (!doorbell) { 2011 u64_stats_update_begin(&ring->syncp); 2012 ring->stats.tx_more++; 2013 u64_stats_update_end(&ring->syncp); 2014 return; 2015 } 2016 2017 if (!ring->pending_buf) 2018 return; 2019 2020 writel(ring->pending_buf, 2021 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG); 2022 ring->pending_buf = 0; 2023 WRITE_ONCE(ring->last_to_use, ring->next_to_use); 2024 } 2025 2026 static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb, 2027 struct hns3_desc *desc) 2028 { 2029 struct hnae3_handle *h = hns3_get_handle(netdev); 2030 2031 if (!(h->ae_algo->ops->set_tx_hwts_info && 2032 h->ae_algo->ops->set_tx_hwts_info(h, skb))) 2033 return; 2034 2035 desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B)); 2036 } 2037 2038 static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring, 2039 struct sk_buff *skb) 2040 { 2041 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 2042 unsigned int type = DESC_TYPE_BOUNCE_HEAD; 2043 unsigned int size = skb_headlen(skb); 2044 dma_addr_t dma; 2045 int bd_num = 0; 2046 u32 cb_len; 2047 void *buf; 2048 int ret; 2049 2050 if (skb->len <= ring->tx_copybreak) { 2051 size = skb->len; 2052 type = DESC_TYPE_BOUNCE_ALL; 2053 } 2054 2055 /* hns3_can_use_tx_bounce() is called to ensure the below 2056 * function can always return the tx buffer. 2057 */ 2058 buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len); 2059 2060 ret = skb_copy_bits(skb, 0, buf, size); 2061 if (unlikely(ret < 0)) { 2062 hns3_tx_spare_rollback(ring, cb_len); 2063 u64_stats_update_begin(&ring->syncp); 2064 ring->stats.copy_bits_err++; 2065 u64_stats_update_end(&ring->syncp); 2066 return ret; 2067 } 2068 2069 desc_cb->priv = skb; 2070 desc_cb->length = cb_len; 2071 desc_cb->dma = dma; 2072 desc_cb->type = type; 2073 2074 bd_num += hns3_fill_desc(ring, dma, size); 2075 2076 if (type == DESC_TYPE_BOUNCE_HEAD) { 2077 ret = hns3_fill_skb_to_desc(ring, skb, 2078 DESC_TYPE_BOUNCE_HEAD); 2079 if (unlikely(ret < 0)) 2080 return ret; 2081 2082 bd_num += ret; 2083 } 2084 2085 dma_sync_single_for_device(ring_to_dev(ring), dma, size, 2086 DMA_TO_DEVICE); 2087 2088 u64_stats_update_begin(&ring->syncp); 2089 ring->stats.tx_bounce++; 2090 u64_stats_update_end(&ring->syncp); 2091 return bd_num; 2092 } 2093 2094 static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring, 2095 struct sk_buff *skb) 2096 { 2097 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 2098 u32 nfrag = skb_shinfo(skb)->nr_frags + 1; 2099 struct sg_table *sgt; 2100 int i, bd_num = 0; 2101 dma_addr_t dma; 2102 u32 cb_len; 2103 int nents; 2104 2105 if (skb_has_frag_list(skb)) 2106 nfrag = HNS3_MAX_TSO_BD_NUM; 2107 2108 /* hns3_can_use_tx_sgl() is called to ensure the below 2109 * function can always return the tx buffer. 2110 */ 2111 sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag), 2112 &dma, &cb_len); 2113 2114 /* scatterlist follows by the sg table */ 2115 sgt->sgl = (struct scatterlist *)(sgt + 1); 2116 sg_init_table(sgt->sgl, nfrag); 2117 nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len); 2118 if (unlikely(nents < 0)) { 2119 hns3_tx_spare_rollback(ring, cb_len); 2120 u64_stats_update_begin(&ring->syncp); 2121 ring->stats.skb2sgl_err++; 2122 u64_stats_update_end(&ring->syncp); 2123 return -ENOMEM; 2124 } 2125 2126 sgt->orig_nents = nents; 2127 sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents, 2128 DMA_TO_DEVICE); 2129 if (unlikely(!sgt->nents)) { 2130 hns3_tx_spare_rollback(ring, cb_len); 2131 u64_stats_update_begin(&ring->syncp); 2132 ring->stats.map_sg_err++; 2133 u64_stats_update_end(&ring->syncp); 2134 return -ENOMEM; 2135 } 2136 2137 desc_cb->priv = skb; 2138 desc_cb->length = cb_len; 2139 desc_cb->dma = dma; 2140 desc_cb->type = DESC_TYPE_SGL_SKB; 2141 2142 for (i = 0; i < sgt->nents; i++) 2143 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i), 2144 sg_dma_len(sgt->sgl + i)); 2145 2146 u64_stats_update_begin(&ring->syncp); 2147 ring->stats.tx_sgl++; 2148 u64_stats_update_end(&ring->syncp); 2149 2150 return bd_num; 2151 } 2152 2153 static int hns3_handle_desc_filling(struct hns3_enet_ring *ring, 2154 struct sk_buff *skb) 2155 { 2156 u32 space; 2157 2158 if (!ring->tx_spare) 2159 goto out; 2160 2161 space = hns3_tx_spare_space(ring); 2162 2163 if (hns3_can_use_tx_sgl(ring, skb, space)) 2164 return hns3_handle_tx_sgl(ring, skb); 2165 2166 if (hns3_can_use_tx_bounce(ring, skb, space)) 2167 return hns3_handle_tx_bounce(ring, skb); 2168 2169 out: 2170 return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB); 2171 } 2172 2173 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 2174 { 2175 struct hns3_nic_priv *priv = netdev_priv(netdev); 2176 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping]; 2177 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 2178 struct netdev_queue *dev_queue; 2179 int pre_ntu, next_to_use_head; 2180 bool doorbell; 2181 int ret; 2182 2183 /* Hardware can only handle short frames above 32 bytes */ 2184 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) { 2185 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 2186 2187 u64_stats_update_begin(&ring->syncp); 2188 ring->stats.sw_err_cnt++; 2189 u64_stats_update_end(&ring->syncp); 2190 2191 return NETDEV_TX_OK; 2192 } 2193 2194 /* Prefetch the data used later */ 2195 prefetch(skb->data); 2196 2197 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb); 2198 if (unlikely(ret <= 0)) { 2199 if (ret == -EBUSY) { 2200 hns3_tx_doorbell(ring, 0, true); 2201 return NETDEV_TX_BUSY; 2202 } 2203 2204 hns3_rl_err(netdev, "xmit error: %d!\n", ret); 2205 goto out_err_tx_ok; 2206 } 2207 2208 next_to_use_head = ring->next_to_use; 2209 2210 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use], 2211 desc_cb); 2212 if (unlikely(ret < 0)) 2213 goto fill_err; 2214 2215 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is 2216 * zero, which is unlikely, and 'ret > 0' means how many tx desc 2217 * need to be notified to the hw. 2218 */ 2219 ret = hns3_handle_desc_filling(ring, skb); 2220 if (unlikely(ret <= 0)) 2221 goto fill_err; 2222 2223 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) : 2224 (ring->desc_num - 1); 2225 2226 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 2227 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]); 2228 2229 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |= 2230 cpu_to_le16(BIT(HNS3_TXD_FE_B)); 2231 trace_hns3_tx_desc(ring, pre_ntu); 2232 2233 skb_tx_timestamp(skb); 2234 2235 /* Complete translate all packets */ 2236 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index); 2237 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes, 2238 netdev_xmit_more()); 2239 hns3_tx_doorbell(ring, ret, doorbell); 2240 2241 return NETDEV_TX_OK; 2242 2243 fill_err: 2244 hns3_clear_desc(ring, next_to_use_head); 2245 2246 out_err_tx_ok: 2247 dev_kfree_skb_any(skb); 2248 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 2249 return NETDEV_TX_OK; 2250 } 2251 2252 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 2253 { 2254 struct hnae3_handle *h = hns3_get_handle(netdev); 2255 struct sockaddr *mac_addr = p; 2256 int ret; 2257 2258 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 2259 return -EADDRNOTAVAIL; 2260 2261 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 2262 netdev_info(netdev, "already using mac address %pM\n", 2263 mac_addr->sa_data); 2264 return 0; 2265 } 2266 2267 /* For VF device, if there is a perm_addr, then the user will not 2268 * be allowed to change the address. 2269 */ 2270 if (!hns3_is_phys_func(h->pdev) && 2271 !is_zero_ether_addr(netdev->perm_addr)) { 2272 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n", 2273 netdev->perm_addr, mac_addr->sa_data); 2274 return -EPERM; 2275 } 2276 2277 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 2278 if (ret) { 2279 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 2280 return ret; 2281 } 2282 2283 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 2284 2285 return 0; 2286 } 2287 2288 static int hns3_nic_do_ioctl(struct net_device *netdev, 2289 struct ifreq *ifr, int cmd) 2290 { 2291 struct hnae3_handle *h = hns3_get_handle(netdev); 2292 2293 if (!netif_running(netdev)) 2294 return -EINVAL; 2295 2296 if (!h->ae_algo->ops->do_ioctl) 2297 return -EOPNOTSUPP; 2298 2299 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 2300 } 2301 2302 static int hns3_nic_set_features(struct net_device *netdev, 2303 netdev_features_t features) 2304 { 2305 netdev_features_t changed = netdev->features ^ features; 2306 struct hns3_nic_priv *priv = netdev_priv(netdev); 2307 struct hnae3_handle *h = priv->ae_handle; 2308 bool enable; 2309 int ret; 2310 2311 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 2312 enable = !!(features & NETIF_F_GRO_HW); 2313 ret = h->ae_algo->ops->set_gro_en(h, enable); 2314 if (ret) 2315 return ret; 2316 } 2317 2318 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 2319 h->ae_algo->ops->enable_hw_strip_rxvtag) { 2320 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 2321 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 2322 if (ret) 2323 return ret; 2324 } 2325 2326 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 2327 enable = !!(features & NETIF_F_NTUPLE); 2328 h->ae_algo->ops->enable_fd(h, enable); 2329 } 2330 2331 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) && 2332 h->ae_algo->ops->cls_flower_active(h)) { 2333 netdev_err(netdev, 2334 "there are offloaded TC filters active, cannot disable HW TC offload"); 2335 return -EINVAL; 2336 } 2337 2338 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 2339 h->ae_algo->ops->enable_vlan_filter) { 2340 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER); 2341 ret = h->ae_algo->ops->enable_vlan_filter(h, enable); 2342 if (ret) 2343 return ret; 2344 } 2345 2346 netdev->features = features; 2347 return 0; 2348 } 2349 2350 static netdev_features_t hns3_features_check(struct sk_buff *skb, 2351 struct net_device *dev, 2352 netdev_features_t features) 2353 { 2354 #define HNS3_MAX_HDR_LEN 480U 2355 #define HNS3_MAX_L4_HDR_LEN 60U 2356 2357 size_t len; 2358 2359 if (skb->ip_summed != CHECKSUM_PARTIAL) 2360 return features; 2361 2362 if (skb->encapsulation) 2363 len = skb_inner_transport_header(skb) - skb->data; 2364 else 2365 len = skb_transport_header(skb) - skb->data; 2366 2367 /* Assume L4 is 60 byte as TCP is the only protocol with a 2368 * a flexible value, and it's max len is 60 bytes. 2369 */ 2370 len += HNS3_MAX_L4_HDR_LEN; 2371 2372 /* Hardware only supports checksum on the skb with a max header 2373 * len of 480 bytes. 2374 */ 2375 if (len > HNS3_MAX_HDR_LEN) 2376 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2377 2378 return features; 2379 } 2380 2381 static void hns3_nic_get_stats64(struct net_device *netdev, 2382 struct rtnl_link_stats64 *stats) 2383 { 2384 struct hns3_nic_priv *priv = netdev_priv(netdev); 2385 int queue_num = priv->ae_handle->kinfo.num_tqps; 2386 struct hnae3_handle *handle = priv->ae_handle; 2387 struct hns3_enet_ring *ring; 2388 u64 rx_length_errors = 0; 2389 u64 rx_crc_errors = 0; 2390 u64 rx_multicast = 0; 2391 unsigned int start; 2392 u64 tx_errors = 0; 2393 u64 rx_errors = 0; 2394 unsigned int idx; 2395 u64 tx_bytes = 0; 2396 u64 rx_bytes = 0; 2397 u64 tx_pkts = 0; 2398 u64 rx_pkts = 0; 2399 u64 tx_drop = 0; 2400 u64 rx_drop = 0; 2401 2402 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 2403 return; 2404 2405 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 2406 2407 for (idx = 0; idx < queue_num; idx++) { 2408 /* fetch the tx stats */ 2409 ring = &priv->ring[idx]; 2410 do { 2411 start = u64_stats_fetch_begin_irq(&ring->syncp); 2412 tx_bytes += ring->stats.tx_bytes; 2413 tx_pkts += ring->stats.tx_pkts; 2414 tx_drop += ring->stats.sw_err_cnt; 2415 tx_drop += ring->stats.tx_vlan_err; 2416 tx_drop += ring->stats.tx_l4_proto_err; 2417 tx_drop += ring->stats.tx_l2l3l4_err; 2418 tx_drop += ring->stats.tx_tso_err; 2419 tx_drop += ring->stats.over_max_recursion; 2420 tx_drop += ring->stats.hw_limitation; 2421 tx_drop += ring->stats.copy_bits_err; 2422 tx_drop += ring->stats.skb2sgl_err; 2423 tx_drop += ring->stats.map_sg_err; 2424 tx_errors += ring->stats.sw_err_cnt; 2425 tx_errors += ring->stats.tx_vlan_err; 2426 tx_errors += ring->stats.tx_l4_proto_err; 2427 tx_errors += ring->stats.tx_l2l3l4_err; 2428 tx_errors += ring->stats.tx_tso_err; 2429 tx_errors += ring->stats.over_max_recursion; 2430 tx_errors += ring->stats.hw_limitation; 2431 tx_errors += ring->stats.copy_bits_err; 2432 tx_errors += ring->stats.skb2sgl_err; 2433 tx_errors += ring->stats.map_sg_err; 2434 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 2435 2436 /* fetch the rx stats */ 2437 ring = &priv->ring[idx + queue_num]; 2438 do { 2439 start = u64_stats_fetch_begin_irq(&ring->syncp); 2440 rx_bytes += ring->stats.rx_bytes; 2441 rx_pkts += ring->stats.rx_pkts; 2442 rx_drop += ring->stats.l2_err; 2443 rx_errors += ring->stats.l2_err; 2444 rx_errors += ring->stats.l3l4_csum_err; 2445 rx_crc_errors += ring->stats.l2_err; 2446 rx_multicast += ring->stats.rx_multicast; 2447 rx_length_errors += ring->stats.err_pkt_len; 2448 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 2449 } 2450 2451 stats->tx_bytes = tx_bytes; 2452 stats->tx_packets = tx_pkts; 2453 stats->rx_bytes = rx_bytes; 2454 stats->rx_packets = rx_pkts; 2455 2456 stats->rx_errors = rx_errors; 2457 stats->multicast = rx_multicast; 2458 stats->rx_length_errors = rx_length_errors; 2459 stats->rx_crc_errors = rx_crc_errors; 2460 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 2461 2462 stats->tx_errors = tx_errors; 2463 stats->rx_dropped = rx_drop; 2464 stats->tx_dropped = tx_drop; 2465 stats->collisions = netdev->stats.collisions; 2466 stats->rx_over_errors = netdev->stats.rx_over_errors; 2467 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 2468 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 2469 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 2470 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 2471 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 2472 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 2473 stats->tx_window_errors = netdev->stats.tx_window_errors; 2474 stats->rx_compressed = netdev->stats.rx_compressed; 2475 stats->tx_compressed = netdev->stats.tx_compressed; 2476 } 2477 2478 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 2479 { 2480 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 2481 struct hnae3_knic_private_info *kinfo; 2482 u8 tc = mqprio_qopt->qopt.num_tc; 2483 u16 mode = mqprio_qopt->mode; 2484 u8 hw = mqprio_qopt->qopt.hw; 2485 struct hnae3_handle *h; 2486 2487 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 2488 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 2489 return -EOPNOTSUPP; 2490 2491 if (tc > HNAE3_MAX_TC) 2492 return -EINVAL; 2493 2494 if (!netdev) 2495 return -EINVAL; 2496 2497 h = hns3_get_handle(netdev); 2498 kinfo = &h->kinfo; 2499 2500 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc); 2501 2502 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 2503 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP; 2504 } 2505 2506 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv, 2507 struct flow_cls_offload *flow) 2508 { 2509 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid); 2510 struct hnae3_handle *h = hns3_get_handle(priv->netdev); 2511 2512 switch (flow->command) { 2513 case FLOW_CLS_REPLACE: 2514 if (h->ae_algo->ops->add_cls_flower) 2515 return h->ae_algo->ops->add_cls_flower(h, flow, tc); 2516 break; 2517 case FLOW_CLS_DESTROY: 2518 if (h->ae_algo->ops->del_cls_flower) 2519 return h->ae_algo->ops->del_cls_flower(h, flow); 2520 break; 2521 default: 2522 break; 2523 } 2524 2525 return -EOPNOTSUPP; 2526 } 2527 2528 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2529 void *cb_priv) 2530 { 2531 struct hns3_nic_priv *priv = cb_priv; 2532 2533 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data)) 2534 return -EOPNOTSUPP; 2535 2536 switch (type) { 2537 case TC_SETUP_CLSFLOWER: 2538 return hns3_setup_tc_cls_flower(priv, type_data); 2539 default: 2540 return -EOPNOTSUPP; 2541 } 2542 } 2543 2544 static LIST_HEAD(hns3_block_cb_list); 2545 2546 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 2547 void *type_data) 2548 { 2549 struct hns3_nic_priv *priv = netdev_priv(dev); 2550 int ret; 2551 2552 switch (type) { 2553 case TC_SETUP_QDISC_MQPRIO: 2554 ret = hns3_setup_tc(dev, type_data); 2555 break; 2556 case TC_SETUP_BLOCK: 2557 ret = flow_block_cb_setup_simple(type_data, 2558 &hns3_block_cb_list, 2559 hns3_setup_tc_block_cb, 2560 priv, priv, true); 2561 break; 2562 default: 2563 return -EOPNOTSUPP; 2564 } 2565 2566 return ret; 2567 } 2568 2569 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 2570 __be16 proto, u16 vid) 2571 { 2572 struct hnae3_handle *h = hns3_get_handle(netdev); 2573 int ret = -EIO; 2574 2575 if (h->ae_algo->ops->set_vlan_filter) 2576 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 2577 2578 return ret; 2579 } 2580 2581 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 2582 __be16 proto, u16 vid) 2583 { 2584 struct hnae3_handle *h = hns3_get_handle(netdev); 2585 int ret = -EIO; 2586 2587 if (h->ae_algo->ops->set_vlan_filter) 2588 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 2589 2590 return ret; 2591 } 2592 2593 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2594 u8 qos, __be16 vlan_proto) 2595 { 2596 struct hnae3_handle *h = hns3_get_handle(netdev); 2597 int ret = -EIO; 2598 2599 netif_dbg(h, drv, netdev, 2600 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n", 2601 vf, vlan, qos, ntohs(vlan_proto)); 2602 2603 if (h->ae_algo->ops->set_vf_vlan_filter) 2604 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 2605 qos, vlan_proto); 2606 2607 return ret; 2608 } 2609 2610 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable) 2611 { 2612 struct hnae3_handle *handle = hns3_get_handle(netdev); 2613 2614 if (hns3_nic_resetting(netdev)) 2615 return -EBUSY; 2616 2617 if (!handle->ae_algo->ops->set_vf_spoofchk) 2618 return -EOPNOTSUPP; 2619 2620 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable); 2621 } 2622 2623 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable) 2624 { 2625 struct hnae3_handle *handle = hns3_get_handle(netdev); 2626 2627 if (!handle->ae_algo->ops->set_vf_trust) 2628 return -EOPNOTSUPP; 2629 2630 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable); 2631 } 2632 2633 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 2634 { 2635 struct hnae3_handle *h = hns3_get_handle(netdev); 2636 int ret; 2637 2638 if (hns3_nic_resetting(netdev)) 2639 return -EBUSY; 2640 2641 if (!h->ae_algo->ops->set_mtu) 2642 return -EOPNOTSUPP; 2643 2644 netif_dbg(h, drv, netdev, 2645 "change mtu from %u to %d\n", netdev->mtu, new_mtu); 2646 2647 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 2648 if (ret) 2649 netdev_err(netdev, "failed to change MTU in hardware %d\n", 2650 ret); 2651 else 2652 netdev->mtu = new_mtu; 2653 2654 return ret; 2655 } 2656 2657 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 2658 { 2659 struct hns3_nic_priv *priv = netdev_priv(ndev); 2660 struct hnae3_handle *h = hns3_get_handle(ndev); 2661 struct hns3_enet_ring *tx_ring; 2662 struct napi_struct *napi; 2663 int timeout_queue = 0; 2664 int hw_head, hw_tail; 2665 int fbd_num, fbd_oft; 2666 int ebd_num, ebd_oft; 2667 int bd_num, bd_err; 2668 int ring_en, tc; 2669 int i; 2670 2671 /* Find the stopped queue the same way the stack does */ 2672 for (i = 0; i < ndev->num_tx_queues; i++) { 2673 struct netdev_queue *q; 2674 unsigned long trans_start; 2675 2676 q = netdev_get_tx_queue(ndev, i); 2677 trans_start = q->trans_start; 2678 if (netif_xmit_stopped(q) && 2679 time_after(jiffies, 2680 (trans_start + ndev->watchdog_timeo))) { 2681 timeout_queue = i; 2682 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n", 2683 q->state, 2684 jiffies_to_msecs(jiffies - trans_start)); 2685 break; 2686 } 2687 } 2688 2689 if (i == ndev->num_tx_queues) { 2690 netdev_info(ndev, 2691 "no netdev TX timeout queue found, timeout count: %llu\n", 2692 priv->tx_timeout_count); 2693 return false; 2694 } 2695 2696 priv->tx_timeout_count++; 2697 2698 tx_ring = &priv->ring[timeout_queue]; 2699 napi = &tx_ring->tqp_vector->napi; 2700 2701 netdev_info(ndev, 2702 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n", 2703 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use, 2704 tx_ring->next_to_clean, napi->state); 2705 2706 netdev_info(ndev, 2707 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n", 2708 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes, 2709 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf); 2710 2711 netdev_info(ndev, 2712 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n", 2713 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more, 2714 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy); 2715 2716 /* When mac received many pause frames continuous, it's unable to send 2717 * packets, which may cause tx timeout 2718 */ 2719 if (h->ae_algo->ops->get_mac_stats) { 2720 struct hns3_mac_stats mac_stats; 2721 2722 h->ae_algo->ops->get_mac_stats(h, &mac_stats); 2723 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n", 2724 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt); 2725 } 2726 2727 hw_head = readl_relaxed(tx_ring->tqp->io_base + 2728 HNS3_RING_TX_RING_HEAD_REG); 2729 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 2730 HNS3_RING_TX_RING_TAIL_REG); 2731 fbd_num = readl_relaxed(tx_ring->tqp->io_base + 2732 HNS3_RING_TX_RING_FBDNUM_REG); 2733 fbd_oft = readl_relaxed(tx_ring->tqp->io_base + 2734 HNS3_RING_TX_RING_OFFSET_REG); 2735 ebd_num = readl_relaxed(tx_ring->tqp->io_base + 2736 HNS3_RING_TX_RING_EBDNUM_REG); 2737 ebd_oft = readl_relaxed(tx_ring->tqp->io_base + 2738 HNS3_RING_TX_RING_EBD_OFFSET_REG); 2739 bd_num = readl_relaxed(tx_ring->tqp->io_base + 2740 HNS3_RING_TX_RING_BD_NUM_REG); 2741 bd_err = readl_relaxed(tx_ring->tqp->io_base + 2742 HNS3_RING_TX_RING_BD_ERR_REG); 2743 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG); 2744 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG); 2745 2746 netdev_info(ndev, 2747 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n", 2748 bd_num, hw_head, hw_tail, bd_err, 2749 readl(tx_ring->tqp_vector->mask_addr)); 2750 netdev_info(ndev, 2751 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n", 2752 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft); 2753 2754 return true; 2755 } 2756 2757 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue) 2758 { 2759 struct hns3_nic_priv *priv = netdev_priv(ndev); 2760 struct hnae3_handle *h = priv->ae_handle; 2761 2762 if (!hns3_get_tx_timeo_queue_info(ndev)) 2763 return; 2764 2765 /* request the reset, and let the hclge to determine 2766 * which reset level should be done 2767 */ 2768 if (h->ae_algo->ops->reset_event) 2769 h->ae_algo->ops->reset_event(h->pdev, h); 2770 } 2771 2772 #ifdef CONFIG_RFS_ACCEL 2773 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 2774 u16 rxq_index, u32 flow_id) 2775 { 2776 struct hnae3_handle *h = hns3_get_handle(dev); 2777 struct flow_keys fkeys; 2778 2779 if (!h->ae_algo->ops->add_arfs_entry) 2780 return -EOPNOTSUPP; 2781 2782 if (skb->encapsulation) 2783 return -EPROTONOSUPPORT; 2784 2785 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0)) 2786 return -EPROTONOSUPPORT; 2787 2788 if ((fkeys.basic.n_proto != htons(ETH_P_IP) && 2789 fkeys.basic.n_proto != htons(ETH_P_IPV6)) || 2790 (fkeys.basic.ip_proto != IPPROTO_TCP && 2791 fkeys.basic.ip_proto != IPPROTO_UDP)) 2792 return -EPROTONOSUPPORT; 2793 2794 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys); 2795 } 2796 #endif 2797 2798 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf, 2799 struct ifla_vf_info *ivf) 2800 { 2801 struct hnae3_handle *h = hns3_get_handle(ndev); 2802 2803 if (!h->ae_algo->ops->get_vf_config) 2804 return -EOPNOTSUPP; 2805 2806 return h->ae_algo->ops->get_vf_config(h, vf, ivf); 2807 } 2808 2809 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf, 2810 int link_state) 2811 { 2812 struct hnae3_handle *h = hns3_get_handle(ndev); 2813 2814 if (!h->ae_algo->ops->set_vf_link_state) 2815 return -EOPNOTSUPP; 2816 2817 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state); 2818 } 2819 2820 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf, 2821 int min_tx_rate, int max_tx_rate) 2822 { 2823 struct hnae3_handle *h = hns3_get_handle(ndev); 2824 2825 if (!h->ae_algo->ops->set_vf_rate) 2826 return -EOPNOTSUPP; 2827 2828 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate, 2829 false); 2830 } 2831 2832 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) 2833 { 2834 struct hnae3_handle *h = hns3_get_handle(netdev); 2835 2836 if (!h->ae_algo->ops->set_vf_mac) 2837 return -EOPNOTSUPP; 2838 2839 if (is_multicast_ether_addr(mac)) { 2840 netdev_err(netdev, 2841 "Invalid MAC:%pM specified. Could not set MAC\n", 2842 mac); 2843 return -EINVAL; 2844 } 2845 2846 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac); 2847 } 2848 2849 static const struct net_device_ops hns3_nic_netdev_ops = { 2850 .ndo_open = hns3_nic_net_open, 2851 .ndo_stop = hns3_nic_net_stop, 2852 .ndo_start_xmit = hns3_nic_net_xmit, 2853 .ndo_tx_timeout = hns3_nic_net_timeout, 2854 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 2855 .ndo_eth_ioctl = hns3_nic_do_ioctl, 2856 .ndo_change_mtu = hns3_nic_change_mtu, 2857 .ndo_set_features = hns3_nic_set_features, 2858 .ndo_features_check = hns3_features_check, 2859 .ndo_get_stats64 = hns3_nic_get_stats64, 2860 .ndo_setup_tc = hns3_nic_setup_tc, 2861 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 2862 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 2863 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 2864 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 2865 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk, 2866 .ndo_set_vf_trust = hns3_set_vf_trust, 2867 #ifdef CONFIG_RFS_ACCEL 2868 .ndo_rx_flow_steer = hns3_rx_flow_steer, 2869 #endif 2870 .ndo_get_vf_config = hns3_nic_get_vf_config, 2871 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state, 2872 .ndo_set_vf_rate = hns3_nic_set_vf_rate, 2873 .ndo_set_vf_mac = hns3_nic_set_vf_mac, 2874 }; 2875 2876 bool hns3_is_phys_func(struct pci_dev *pdev) 2877 { 2878 u32 dev_id = pdev->device; 2879 2880 switch (dev_id) { 2881 case HNAE3_DEV_ID_GE: 2882 case HNAE3_DEV_ID_25GE: 2883 case HNAE3_DEV_ID_25GE_RDMA: 2884 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 2885 case HNAE3_DEV_ID_50GE_RDMA: 2886 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 2887 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 2888 case HNAE3_DEV_ID_200G_RDMA: 2889 return true; 2890 case HNAE3_DEV_ID_VF: 2891 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF: 2892 return false; 2893 default: 2894 dev_warn(&pdev->dev, "un-recognized pci device-id %u", 2895 dev_id); 2896 } 2897 2898 return false; 2899 } 2900 2901 static void hns3_disable_sriov(struct pci_dev *pdev) 2902 { 2903 /* If our VFs are assigned we cannot shut down SR-IOV 2904 * without causing issues, so just leave the hardware 2905 * available but disabled 2906 */ 2907 if (pci_vfs_assigned(pdev)) { 2908 dev_warn(&pdev->dev, 2909 "disabling driver while VFs are assigned\n"); 2910 return; 2911 } 2912 2913 pci_disable_sriov(pdev); 2914 } 2915 2916 /* hns3_probe - Device initialization routine 2917 * @pdev: PCI device information struct 2918 * @ent: entry in hns3_pci_tbl 2919 * 2920 * hns3_probe initializes a PF identified by a pci_dev structure. 2921 * The OS initialization, configuring of the PF private structure, 2922 * and a hardware reset occur. 2923 * 2924 * Returns 0 on success, negative on failure 2925 */ 2926 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2927 { 2928 struct hnae3_ae_dev *ae_dev; 2929 int ret; 2930 2931 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL); 2932 if (!ae_dev) 2933 return -ENOMEM; 2934 2935 ae_dev->pdev = pdev; 2936 ae_dev->flag = ent->driver_data; 2937 pci_set_drvdata(pdev, ae_dev); 2938 2939 ret = hnae3_register_ae_dev(ae_dev); 2940 if (ret) 2941 pci_set_drvdata(pdev, NULL); 2942 2943 return ret; 2944 } 2945 2946 /* hns3_remove - Device removal routine 2947 * @pdev: PCI device information struct 2948 */ 2949 static void hns3_remove(struct pci_dev *pdev) 2950 { 2951 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2952 2953 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 2954 hns3_disable_sriov(pdev); 2955 2956 hnae3_unregister_ae_dev(ae_dev); 2957 pci_set_drvdata(pdev, NULL); 2958 } 2959 2960 /** 2961 * hns3_pci_sriov_configure 2962 * @pdev: pointer to a pci_dev structure 2963 * @num_vfs: number of VFs to allocate 2964 * 2965 * Enable or change the number of VFs. Called when the user updates the number 2966 * of VFs in sysfs. 2967 **/ 2968 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 2969 { 2970 int ret; 2971 2972 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 2973 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 2974 return -EINVAL; 2975 } 2976 2977 if (num_vfs) { 2978 ret = pci_enable_sriov(pdev, num_vfs); 2979 if (ret) 2980 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 2981 else 2982 return num_vfs; 2983 } else if (!pci_vfs_assigned(pdev)) { 2984 pci_disable_sriov(pdev); 2985 } else { 2986 dev_warn(&pdev->dev, 2987 "Unable to free VFs because some are assigned to VMs.\n"); 2988 } 2989 2990 return 0; 2991 } 2992 2993 static void hns3_shutdown(struct pci_dev *pdev) 2994 { 2995 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2996 2997 hnae3_unregister_ae_dev(ae_dev); 2998 pci_set_drvdata(pdev, NULL); 2999 3000 if (system_state == SYSTEM_POWER_OFF) 3001 pci_set_power_state(pdev, PCI_D3hot); 3002 } 3003 3004 static int __maybe_unused hns3_suspend(struct device *dev) 3005 { 3006 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev); 3007 3008 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) { 3009 dev_info(dev, "Begin to suspend.\n"); 3010 if (ae_dev->ops && ae_dev->ops->reset_prepare) 3011 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET); 3012 } 3013 3014 return 0; 3015 } 3016 3017 static int __maybe_unused hns3_resume(struct device *dev) 3018 { 3019 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev); 3020 3021 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) { 3022 dev_info(dev, "Begin to resume.\n"); 3023 if (ae_dev->ops && ae_dev->ops->reset_done) 3024 ae_dev->ops->reset_done(ae_dev); 3025 } 3026 3027 return 0; 3028 } 3029 3030 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 3031 pci_channel_state_t state) 3032 { 3033 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3034 pci_ers_result_t ret; 3035 3036 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state); 3037 3038 if (state == pci_channel_io_perm_failure) 3039 return PCI_ERS_RESULT_DISCONNECT; 3040 3041 if (!ae_dev || !ae_dev->ops) { 3042 dev_err(&pdev->dev, 3043 "Can't recover - error happened before device initialized\n"); 3044 return PCI_ERS_RESULT_NONE; 3045 } 3046 3047 if (ae_dev->ops->handle_hw_ras_error) 3048 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 3049 else 3050 return PCI_ERS_RESULT_NONE; 3051 3052 return ret; 3053 } 3054 3055 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 3056 { 3057 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3058 const struct hnae3_ae_ops *ops; 3059 enum hnae3_reset_type reset_type; 3060 struct device *dev = &pdev->dev; 3061 3062 if (!ae_dev || !ae_dev->ops) 3063 return PCI_ERS_RESULT_NONE; 3064 3065 ops = ae_dev->ops; 3066 /* request the reset */ 3067 if (ops->reset_event && ops->get_reset_level && 3068 ops->set_default_reset_request) { 3069 if (ae_dev->hw_err_reset_req) { 3070 reset_type = ops->get_reset_level(ae_dev, 3071 &ae_dev->hw_err_reset_req); 3072 ops->set_default_reset_request(ae_dev, reset_type); 3073 dev_info(dev, "requesting reset due to PCI error\n"); 3074 ops->reset_event(pdev, NULL); 3075 } 3076 3077 return PCI_ERS_RESULT_RECOVERED; 3078 } 3079 3080 return PCI_ERS_RESULT_DISCONNECT; 3081 } 3082 3083 static void hns3_reset_prepare(struct pci_dev *pdev) 3084 { 3085 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3086 3087 dev_info(&pdev->dev, "FLR prepare\n"); 3088 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare) 3089 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET); 3090 } 3091 3092 static void hns3_reset_done(struct pci_dev *pdev) 3093 { 3094 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3095 3096 dev_info(&pdev->dev, "FLR done\n"); 3097 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done) 3098 ae_dev->ops->reset_done(ae_dev); 3099 } 3100 3101 static const struct pci_error_handlers hns3_err_handler = { 3102 .error_detected = hns3_error_detected, 3103 .slot_reset = hns3_slot_reset, 3104 .reset_prepare = hns3_reset_prepare, 3105 .reset_done = hns3_reset_done, 3106 }; 3107 3108 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume); 3109 3110 static struct pci_driver hns3_driver = { 3111 .name = hns3_driver_name, 3112 .id_table = hns3_pci_tbl, 3113 .probe = hns3_probe, 3114 .remove = hns3_remove, 3115 .shutdown = hns3_shutdown, 3116 .driver.pm = &hns3_pm_ops, 3117 .sriov_configure = hns3_pci_sriov_configure, 3118 .err_handler = &hns3_err_handler, 3119 }; 3120 3121 /* set default feature to hns3 */ 3122 static void hns3_set_default_feature(struct net_device *netdev) 3123 { 3124 struct hnae3_handle *h = hns3_get_handle(netdev); 3125 struct pci_dev *pdev = h->pdev; 3126 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3127 3128 netdev->priv_flags |= IFF_UNICAST_FLT; 3129 3130 netdev->hw_enc_features |= NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 3131 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 3132 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 3133 NETIF_F_SCTP_CRC | NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST; 3134 3135 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 3136 3137 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3138 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 3139 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 3140 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 3141 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 3142 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 3143 3144 netdev->vlan_features |= NETIF_F_RXCSUM | 3145 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 3146 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 3147 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 3148 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 3149 3150 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 3151 NETIF_F_HW_VLAN_CTAG_RX | 3152 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 3153 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 3154 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 3155 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 3156 3157 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3158 netdev->hw_features |= NETIF_F_GRO_HW; 3159 netdev->features |= NETIF_F_GRO_HW; 3160 3161 if (!(h->flags & HNAE3_SUPPORT_VF)) { 3162 netdev->hw_features |= NETIF_F_NTUPLE; 3163 netdev->features |= NETIF_F_NTUPLE; 3164 } 3165 } 3166 3167 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps)) { 3168 netdev->hw_features |= NETIF_F_GSO_UDP_L4; 3169 netdev->features |= NETIF_F_GSO_UDP_L4; 3170 netdev->vlan_features |= NETIF_F_GSO_UDP_L4; 3171 netdev->hw_enc_features |= NETIF_F_GSO_UDP_L4; 3172 } 3173 3174 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) { 3175 netdev->hw_features |= NETIF_F_HW_CSUM; 3176 netdev->features |= NETIF_F_HW_CSUM; 3177 netdev->vlan_features |= NETIF_F_HW_CSUM; 3178 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 3179 } else { 3180 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 3181 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 3182 netdev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 3183 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 3184 } 3185 3186 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps)) { 3187 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 3188 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 3189 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 3190 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 3191 } 3192 3193 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) { 3194 netdev->hw_features |= NETIF_F_HW_TC; 3195 netdev->features |= NETIF_F_HW_TC; 3196 } 3197 3198 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 3199 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 3200 } 3201 3202 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 3203 struct hns3_desc_cb *cb) 3204 { 3205 unsigned int order = hns3_page_order(ring); 3206 struct page *p; 3207 3208 if (ring->page_pool) { 3209 p = page_pool_dev_alloc_frag(ring->page_pool, 3210 &cb->page_offset, 3211 hns3_buf_size(ring)); 3212 if (unlikely(!p)) 3213 return -ENOMEM; 3214 3215 cb->priv = p; 3216 cb->buf = page_address(p); 3217 cb->dma = page_pool_get_dma_addr(p); 3218 cb->type = DESC_TYPE_PP_FRAG; 3219 cb->reuse_flag = 0; 3220 return 0; 3221 } 3222 3223 p = dev_alloc_pages(order); 3224 if (!p) 3225 return -ENOMEM; 3226 3227 cb->priv = p; 3228 cb->page_offset = 0; 3229 cb->reuse_flag = 0; 3230 cb->buf = page_address(p); 3231 cb->length = hns3_page_size(ring); 3232 cb->type = DESC_TYPE_PAGE; 3233 page_ref_add(p, USHRT_MAX - 1); 3234 cb->pagecnt_bias = USHRT_MAX; 3235 3236 return 0; 3237 } 3238 3239 static void hns3_free_buffer(struct hns3_enet_ring *ring, 3240 struct hns3_desc_cb *cb, int budget) 3241 { 3242 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD | 3243 DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB)) 3244 napi_consume_skb(cb->priv, budget); 3245 else if (!HNAE3_IS_TX_RING(ring)) { 3246 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias) 3247 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias); 3248 else if (cb->type & DESC_TYPE_PP_FRAG) 3249 page_pool_put_full_page(ring->page_pool, cb->priv, 3250 false); 3251 } 3252 memset(cb, 0, sizeof(*cb)); 3253 } 3254 3255 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 3256 { 3257 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 3258 cb->length, ring_to_dma_dir(ring)); 3259 3260 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 3261 return -EIO; 3262 3263 return 0; 3264 } 3265 3266 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 3267 struct hns3_desc_cb *cb) 3268 { 3269 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB)) 3270 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 3271 ring_to_dma_dir(ring)); 3272 else if ((cb->type & DESC_TYPE_PAGE) && cb->length) 3273 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 3274 ring_to_dma_dir(ring)); 3275 else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD | 3276 DESC_TYPE_SGL_SKB)) 3277 hns3_tx_spare_reclaim_cb(ring, cb); 3278 } 3279 3280 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 3281 { 3282 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 3283 ring->desc[i].addr = 0; 3284 } 3285 3286 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i, 3287 int budget) 3288 { 3289 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 3290 3291 if (!ring->desc_cb[i].dma) 3292 return; 3293 3294 hns3_buffer_detach(ring, i); 3295 hns3_free_buffer(ring, cb, budget); 3296 } 3297 3298 static void hns3_free_buffers(struct hns3_enet_ring *ring) 3299 { 3300 int i; 3301 3302 for (i = 0; i < ring->desc_num; i++) 3303 hns3_free_buffer_detach(ring, i, 0); 3304 } 3305 3306 /* free desc along with its attached buffer */ 3307 static void hns3_free_desc(struct hns3_enet_ring *ring) 3308 { 3309 int size = ring->desc_num * sizeof(ring->desc[0]); 3310 3311 hns3_free_buffers(ring); 3312 3313 if (ring->desc) { 3314 dma_free_coherent(ring_to_dev(ring), size, 3315 ring->desc, ring->desc_dma_addr); 3316 ring->desc = NULL; 3317 } 3318 } 3319 3320 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 3321 { 3322 int size = ring->desc_num * sizeof(ring->desc[0]); 3323 3324 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 3325 &ring->desc_dma_addr, GFP_KERNEL); 3326 if (!ring->desc) 3327 return -ENOMEM; 3328 3329 return 0; 3330 } 3331 3332 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring, 3333 struct hns3_desc_cb *cb) 3334 { 3335 int ret; 3336 3337 ret = hns3_alloc_buffer(ring, cb); 3338 if (ret || ring->page_pool) 3339 goto out; 3340 3341 ret = hns3_map_buffer(ring, cb); 3342 if (ret) 3343 goto out_with_buf; 3344 3345 return 0; 3346 3347 out_with_buf: 3348 hns3_free_buffer(ring, cb, 0); 3349 out: 3350 return ret; 3351 } 3352 3353 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i) 3354 { 3355 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]); 3356 3357 if (ret) 3358 return ret; 3359 3360 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 3361 ring->desc_cb[i].page_offset); 3362 3363 return 0; 3364 } 3365 3366 /* Allocate memory for raw pkg, and map with dma */ 3367 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 3368 { 3369 int i, j, ret; 3370 3371 for (i = 0; i < ring->desc_num; i++) { 3372 ret = hns3_alloc_and_attach_buffer(ring, i); 3373 if (ret) 3374 goto out_buffer_fail; 3375 } 3376 3377 return 0; 3378 3379 out_buffer_fail: 3380 for (j = i - 1; j >= 0; j--) 3381 hns3_free_buffer_detach(ring, j, 0); 3382 return ret; 3383 } 3384 3385 /* detach a in-used buffer and replace with a reserved one */ 3386 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 3387 struct hns3_desc_cb *res_cb) 3388 { 3389 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 3390 ring->desc_cb[i] = *res_cb; 3391 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 3392 ring->desc_cb[i].page_offset); 3393 ring->desc[i].rx.bd_base_info = 0; 3394 } 3395 3396 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 3397 { 3398 ring->desc_cb[i].reuse_flag = 0; 3399 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 3400 ring->desc_cb[i].page_offset); 3401 ring->desc[i].rx.bd_base_info = 0; 3402 3403 dma_sync_single_for_device(ring_to_dev(ring), 3404 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset, 3405 hns3_buf_size(ring), 3406 DMA_FROM_DEVICE); 3407 } 3408 3409 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, 3410 int *bytes, int *pkts, int budget) 3411 { 3412 /* pair with ring->last_to_use update in hns3_tx_doorbell(), 3413 * smp_store_release() is not used in hns3_tx_doorbell() because 3414 * the doorbell operation already have the needed barrier operation. 3415 */ 3416 int ltu = smp_load_acquire(&ring->last_to_use); 3417 int ntc = ring->next_to_clean; 3418 struct hns3_desc_cb *desc_cb; 3419 bool reclaimed = false; 3420 struct hns3_desc *desc; 3421 3422 while (ltu != ntc) { 3423 desc = &ring->desc[ntc]; 3424 3425 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) & 3426 BIT(HNS3_TXD_VLD_B)) 3427 break; 3428 3429 desc_cb = &ring->desc_cb[ntc]; 3430 3431 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL | 3432 DESC_TYPE_BOUNCE_HEAD | 3433 DESC_TYPE_SGL_SKB)) { 3434 (*pkts)++; 3435 (*bytes) += desc_cb->send_bytes; 3436 } 3437 3438 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */ 3439 hns3_free_buffer_detach(ring, ntc, budget); 3440 3441 if (++ntc == ring->desc_num) 3442 ntc = 0; 3443 3444 /* Issue prefetch for next Tx descriptor */ 3445 prefetch(&ring->desc_cb[ntc]); 3446 reclaimed = true; 3447 } 3448 3449 if (unlikely(!reclaimed)) 3450 return false; 3451 3452 /* This smp_store_release() pairs with smp_load_acquire() in 3453 * ring_space called by hns3_nic_net_xmit. 3454 */ 3455 smp_store_release(&ring->next_to_clean, ntc); 3456 3457 hns3_tx_spare_update(ring); 3458 3459 return true; 3460 } 3461 3462 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget) 3463 { 3464 struct net_device *netdev = ring_to_netdev(ring); 3465 struct hns3_nic_priv *priv = netdev_priv(netdev); 3466 struct netdev_queue *dev_queue; 3467 int bytes, pkts; 3468 3469 bytes = 0; 3470 pkts = 0; 3471 3472 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget))) 3473 return; 3474 3475 ring->tqp_vector->tx_group.total_bytes += bytes; 3476 ring->tqp_vector->tx_group.total_packets += pkts; 3477 3478 u64_stats_update_begin(&ring->syncp); 3479 ring->stats.tx_bytes += bytes; 3480 ring->stats.tx_pkts += pkts; 3481 u64_stats_update_end(&ring->syncp); 3482 3483 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 3484 netdev_tx_completed_queue(dev_queue, pkts, bytes); 3485 3486 if (unlikely(netif_carrier_ok(netdev) && 3487 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) { 3488 /* Make sure that anybody stopping the queue after this 3489 * sees the new next_to_clean. 3490 */ 3491 smp_mb(); 3492 if (netif_tx_queue_stopped(dev_queue) && 3493 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 3494 netif_tx_wake_queue(dev_queue); 3495 ring->stats.restart_queue++; 3496 } 3497 } 3498 } 3499 3500 static int hns3_desc_unused(struct hns3_enet_ring *ring) 3501 { 3502 int ntc = ring->next_to_clean; 3503 int ntu = ring->next_to_use; 3504 3505 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 3506 } 3507 3508 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, 3509 int cleand_count) 3510 { 3511 struct hns3_desc_cb *desc_cb; 3512 struct hns3_desc_cb res_cbs; 3513 int i, ret; 3514 3515 for (i = 0; i < cleand_count; i++) { 3516 desc_cb = &ring->desc_cb[ring->next_to_use]; 3517 if (desc_cb->reuse_flag) { 3518 u64_stats_update_begin(&ring->syncp); 3519 ring->stats.reuse_pg_cnt++; 3520 u64_stats_update_end(&ring->syncp); 3521 3522 hns3_reuse_buffer(ring, ring->next_to_use); 3523 } else { 3524 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 3525 if (ret) { 3526 u64_stats_update_begin(&ring->syncp); 3527 ring->stats.sw_err_cnt++; 3528 u64_stats_update_end(&ring->syncp); 3529 3530 hns3_rl_err(ring_to_netdev(ring), 3531 "alloc rx buffer failed: %d\n", 3532 ret); 3533 break; 3534 } 3535 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 3536 3537 u64_stats_update_begin(&ring->syncp); 3538 ring->stats.non_reuse_pg++; 3539 u64_stats_update_end(&ring->syncp); 3540 } 3541 3542 ring_ptr_move_fw(ring, next_to_use); 3543 } 3544 3545 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 3546 } 3547 3548 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb) 3549 { 3550 return page_count(cb->priv) == cb->pagecnt_bias; 3551 } 3552 3553 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 3554 struct hns3_enet_ring *ring, int pull_len, 3555 struct hns3_desc_cb *desc_cb) 3556 { 3557 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 3558 u32 frag_offset = desc_cb->page_offset + pull_len; 3559 int size = le16_to_cpu(desc->rx.size); 3560 u32 truesize = hns3_buf_size(ring); 3561 u32 frag_size = size - pull_len; 3562 bool reused; 3563 3564 if (ring->page_pool) { 3565 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset, 3566 frag_size, truesize); 3567 return; 3568 } 3569 3570 /* Avoid re-using remote or pfmem page */ 3571 if (unlikely(!dev_page_is_reusable(desc_cb->priv))) 3572 goto out; 3573 3574 reused = hns3_can_reuse_page(desc_cb); 3575 3576 /* Rx page can be reused when: 3577 * 1. Rx page is only owned by the driver when page_offset 3578 * is zero, which means 0 @ truesize will be used by 3579 * stack after skb_add_rx_frag() is called, and the rest 3580 * of rx page can be reused by driver. 3581 * Or 3582 * 2. Rx page is only owned by the driver when page_offset 3583 * is non-zero, which means page_offset @ truesize will 3584 * be used by stack after skb_add_rx_frag() is called, 3585 * and 0 @ truesize can be reused by driver. 3586 */ 3587 if ((!desc_cb->page_offset && reused) || 3588 ((desc_cb->page_offset + truesize + truesize) <= 3589 hns3_page_size(ring) && desc_cb->page_offset)) { 3590 desc_cb->page_offset += truesize; 3591 desc_cb->reuse_flag = 1; 3592 } else if (desc_cb->page_offset && reused) { 3593 desc_cb->page_offset = 0; 3594 desc_cb->reuse_flag = 1; 3595 } else if (frag_size <= ring->rx_copybreak) { 3596 void *frag = napi_alloc_frag(frag_size); 3597 3598 if (unlikely(!frag)) { 3599 u64_stats_update_begin(&ring->syncp); 3600 ring->stats.frag_alloc_err++; 3601 u64_stats_update_end(&ring->syncp); 3602 3603 hns3_rl_err(ring_to_netdev(ring), 3604 "failed to allocate rx frag\n"); 3605 goto out; 3606 } 3607 3608 desc_cb->reuse_flag = 1; 3609 memcpy(frag, desc_cb->buf + frag_offset, frag_size); 3610 skb_add_rx_frag(skb, i, virt_to_page(frag), 3611 offset_in_page(frag), frag_size, frag_size); 3612 3613 u64_stats_update_begin(&ring->syncp); 3614 ring->stats.frag_alloc++; 3615 u64_stats_update_end(&ring->syncp); 3616 return; 3617 } 3618 3619 out: 3620 desc_cb->pagecnt_bias--; 3621 3622 if (unlikely(!desc_cb->pagecnt_bias)) { 3623 page_ref_add(desc_cb->priv, USHRT_MAX); 3624 desc_cb->pagecnt_bias = USHRT_MAX; 3625 } 3626 3627 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset, 3628 frag_size, truesize); 3629 3630 if (unlikely(!desc_cb->reuse_flag)) 3631 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias); 3632 } 3633 3634 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) 3635 { 3636 __be16 type = skb->protocol; 3637 struct tcphdr *th; 3638 int depth = 0; 3639 3640 while (eth_type_vlan(type)) { 3641 struct vlan_hdr *vh; 3642 3643 if ((depth + VLAN_HLEN) > skb_headlen(skb)) 3644 return -EFAULT; 3645 3646 vh = (struct vlan_hdr *)(skb->data + depth); 3647 type = vh->h_vlan_encapsulated_proto; 3648 depth += VLAN_HLEN; 3649 } 3650 3651 skb_set_network_header(skb, depth); 3652 3653 if (type == htons(ETH_P_IP)) { 3654 const struct iphdr *iph = ip_hdr(skb); 3655 3656 depth += sizeof(struct iphdr); 3657 skb_set_transport_header(skb, depth); 3658 th = tcp_hdr(skb); 3659 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr, 3660 iph->daddr, 0); 3661 } else if (type == htons(ETH_P_IPV6)) { 3662 const struct ipv6hdr *iph = ipv6_hdr(skb); 3663 3664 depth += sizeof(struct ipv6hdr); 3665 skb_set_transport_header(skb, depth); 3666 th = tcp_hdr(skb); 3667 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr, 3668 &iph->daddr, 0); 3669 } else { 3670 hns3_rl_err(skb->dev, 3671 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n", 3672 be16_to_cpu(type), depth); 3673 return -EFAULT; 3674 } 3675 3676 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 3677 if (th->cwr) 3678 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 3679 3680 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B)) 3681 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID; 3682 3683 skb->csum_start = (unsigned char *)th - skb->head; 3684 skb->csum_offset = offsetof(struct tcphdr, check); 3685 skb->ip_summed = CHECKSUM_PARTIAL; 3686 3687 trace_hns3_gro(skb); 3688 3689 return 0; 3690 } 3691 3692 static bool hns3_checksum_complete(struct hns3_enet_ring *ring, 3693 struct sk_buff *skb, u32 ptype, u16 csum) 3694 { 3695 if (ptype == HNS3_INVALID_PTYPE || 3696 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE) 3697 return false; 3698 3699 u64_stats_update_begin(&ring->syncp); 3700 ring->stats.csum_complete++; 3701 u64_stats_update_end(&ring->syncp); 3702 skb->ip_summed = CHECKSUM_COMPLETE; 3703 skb->csum = csum_unfold((__force __sum16)csum); 3704 3705 return true; 3706 } 3707 3708 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info, 3709 u32 ol_info, u32 ptype) 3710 { 3711 int l3_type, l4_type; 3712 int ol4_type; 3713 3714 if (ptype != HNS3_INVALID_PTYPE) { 3715 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level; 3716 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed; 3717 3718 return; 3719 } 3720 3721 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M, 3722 HNS3_RXD_OL4ID_S); 3723 switch (ol4_type) { 3724 case HNS3_OL4_TYPE_MAC_IN_UDP: 3725 case HNS3_OL4_TYPE_NVGRE: 3726 skb->csum_level = 1; 3727 fallthrough; 3728 case HNS3_OL4_TYPE_NO_TUN: 3729 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 3730 HNS3_RXD_L3ID_S); 3731 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 3732 HNS3_RXD_L4ID_S); 3733 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 3734 if ((l3_type == HNS3_L3_TYPE_IPV4 || 3735 l3_type == HNS3_L3_TYPE_IPV6) && 3736 (l4_type == HNS3_L4_TYPE_UDP || 3737 l4_type == HNS3_L4_TYPE_TCP || 3738 l4_type == HNS3_L4_TYPE_SCTP)) 3739 skb->ip_summed = CHECKSUM_UNNECESSARY; 3740 break; 3741 default: 3742 break; 3743 } 3744 } 3745 3746 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 3747 u32 l234info, u32 bd_base_info, u32 ol_info, 3748 u16 csum) 3749 { 3750 struct net_device *netdev = ring_to_netdev(ring); 3751 struct hns3_nic_priv *priv = netdev_priv(netdev); 3752 u32 ptype = HNS3_INVALID_PTYPE; 3753 3754 skb->ip_summed = CHECKSUM_NONE; 3755 3756 skb_checksum_none_assert(skb); 3757 3758 if (!(netdev->features & NETIF_F_RXCSUM)) 3759 return; 3760 3761 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) 3762 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, 3763 HNS3_RXD_PTYPE_S); 3764 3765 if (hns3_checksum_complete(ring, skb, ptype, csum)) 3766 return; 3767 3768 /* check if hardware has done checksum */ 3769 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 3770 return; 3771 3772 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | 3773 BIT(HNS3_RXD_OL3E_B) | 3774 BIT(HNS3_RXD_OL4E_B)))) { 3775 u64_stats_update_begin(&ring->syncp); 3776 ring->stats.l3l4_csum_err++; 3777 u64_stats_update_end(&ring->syncp); 3778 3779 return; 3780 } 3781 3782 hns3_rx_handle_csum(skb, l234info, ol_info, ptype); 3783 } 3784 3785 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 3786 { 3787 if (skb_has_frag_list(skb)) 3788 napi_gro_flush(&ring->tqp_vector->napi, false); 3789 3790 napi_gro_receive(&ring->tqp_vector->napi, skb); 3791 } 3792 3793 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 3794 struct hns3_desc *desc, u32 l234info, 3795 u16 *vlan_tag) 3796 { 3797 struct hnae3_handle *handle = ring->tqp->handle; 3798 struct pci_dev *pdev = ring->tqp->handle->pdev; 3799 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3800 3801 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) { 3802 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3803 if (!(*vlan_tag & VLAN_VID_MASK)) 3804 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3805 3806 return (*vlan_tag != 0); 3807 } 3808 3809 #define HNS3_STRP_OUTER_VLAN 0x1 3810 #define HNS3_STRP_INNER_VLAN 0x2 3811 #define HNS3_STRP_BOTH 0x3 3812 3813 /* Hardware always insert VLAN tag into RX descriptor when 3814 * remove the tag from packet, driver needs to determine 3815 * reporting which tag to stack. 3816 */ 3817 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 3818 HNS3_RXD_STRP_TAGP_S)) { 3819 case HNS3_STRP_OUTER_VLAN: 3820 if (handle->port_base_vlan_state != 3821 HNAE3_PORT_BASE_VLAN_DISABLE) 3822 return false; 3823 3824 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3825 return true; 3826 case HNS3_STRP_INNER_VLAN: 3827 if (handle->port_base_vlan_state != 3828 HNAE3_PORT_BASE_VLAN_DISABLE) 3829 return false; 3830 3831 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3832 return true; 3833 case HNS3_STRP_BOTH: 3834 if (handle->port_base_vlan_state == 3835 HNAE3_PORT_BASE_VLAN_DISABLE) 3836 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3837 else 3838 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3839 3840 return true; 3841 default: 3842 return false; 3843 } 3844 } 3845 3846 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring) 3847 { 3848 ring->desc[ring->next_to_clean].rx.bd_base_info &= 3849 cpu_to_le32(~BIT(HNS3_RXD_VLD_B)); 3850 ring->next_to_clean += 1; 3851 3852 if (unlikely(ring->next_to_clean == ring->desc_num)) 3853 ring->next_to_clean = 0; 3854 } 3855 3856 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length, 3857 unsigned char *va) 3858 { 3859 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 3860 struct net_device *netdev = ring_to_netdev(ring); 3861 struct sk_buff *skb; 3862 3863 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 3864 skb = ring->skb; 3865 if (unlikely(!skb)) { 3866 hns3_rl_err(netdev, "alloc rx skb fail\n"); 3867 3868 u64_stats_update_begin(&ring->syncp); 3869 ring->stats.sw_err_cnt++; 3870 u64_stats_update_end(&ring->syncp); 3871 3872 return -ENOMEM; 3873 } 3874 3875 trace_hns3_rx_desc(ring); 3876 prefetchw(skb->data); 3877 3878 ring->pending_buf = 1; 3879 ring->frag_num = 0; 3880 ring->tail_skb = NULL; 3881 if (length <= HNS3_RX_HEAD_SIZE) { 3882 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 3883 3884 /* We can reuse buffer as-is, just make sure it is reusable */ 3885 if (dev_page_is_reusable(desc_cb->priv)) 3886 desc_cb->reuse_flag = 1; 3887 else if (desc_cb->type & DESC_TYPE_PP_FRAG) 3888 page_pool_put_full_page(ring->page_pool, desc_cb->priv, 3889 false); 3890 else /* This page cannot be reused so discard it */ 3891 __page_frag_cache_drain(desc_cb->priv, 3892 desc_cb->pagecnt_bias); 3893 3894 hns3_rx_ring_move_fw(ring); 3895 return 0; 3896 } 3897 3898 if (ring->page_pool) 3899 skb_mark_for_recycle(skb); 3900 3901 u64_stats_update_begin(&ring->syncp); 3902 ring->stats.seg_pkt_cnt++; 3903 u64_stats_update_end(&ring->syncp); 3904 3905 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE); 3906 __skb_put(skb, ring->pull_len); 3907 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 3908 desc_cb); 3909 hns3_rx_ring_move_fw(ring); 3910 3911 return 0; 3912 } 3913 3914 static int hns3_add_frag(struct hns3_enet_ring *ring) 3915 { 3916 struct sk_buff *skb = ring->skb; 3917 struct sk_buff *head_skb = skb; 3918 struct sk_buff *new_skb; 3919 struct hns3_desc_cb *desc_cb; 3920 struct hns3_desc *desc; 3921 u32 bd_base_info; 3922 3923 do { 3924 desc = &ring->desc[ring->next_to_clean]; 3925 desc_cb = &ring->desc_cb[ring->next_to_clean]; 3926 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3927 /* make sure HW write desc complete */ 3928 dma_rmb(); 3929 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 3930 return -ENXIO; 3931 3932 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 3933 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0); 3934 if (unlikely(!new_skb)) { 3935 hns3_rl_err(ring_to_netdev(ring), 3936 "alloc rx fraglist skb fail\n"); 3937 return -ENXIO; 3938 } 3939 3940 if (ring->page_pool) 3941 skb_mark_for_recycle(new_skb); 3942 3943 ring->frag_num = 0; 3944 3945 if (ring->tail_skb) { 3946 ring->tail_skb->next = new_skb; 3947 ring->tail_skb = new_skb; 3948 } else { 3949 skb_shinfo(skb)->frag_list = new_skb; 3950 ring->tail_skb = new_skb; 3951 } 3952 } 3953 3954 if (ring->tail_skb) { 3955 head_skb->truesize += hns3_buf_size(ring); 3956 head_skb->data_len += le16_to_cpu(desc->rx.size); 3957 head_skb->len += le16_to_cpu(desc->rx.size); 3958 skb = ring->tail_skb; 3959 } 3960 3961 dma_sync_single_for_cpu(ring_to_dev(ring), 3962 desc_cb->dma + desc_cb->page_offset, 3963 hns3_buf_size(ring), 3964 DMA_FROM_DEVICE); 3965 3966 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 3967 trace_hns3_rx_desc(ring); 3968 hns3_rx_ring_move_fw(ring); 3969 ring->pending_buf++; 3970 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B))); 3971 3972 return 0; 3973 } 3974 3975 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring, 3976 struct sk_buff *skb, u32 l234info, 3977 u32 bd_base_info, u32 ol_info, u16 csum) 3978 { 3979 struct net_device *netdev = ring_to_netdev(ring); 3980 struct hns3_nic_priv *priv = netdev_priv(netdev); 3981 u32 l3_type; 3982 3983 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 3984 HNS3_RXD_GRO_SIZE_M, 3985 HNS3_RXD_GRO_SIZE_S); 3986 /* if there is no HW GRO, do not set gro params */ 3987 if (!skb_shinfo(skb)->gso_size) { 3988 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info, 3989 csum); 3990 return 0; 3991 } 3992 3993 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info, 3994 HNS3_RXD_GRO_COUNT_M, 3995 HNS3_RXD_GRO_COUNT_S); 3996 3997 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) { 3998 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, 3999 HNS3_RXD_PTYPE_S); 4000 4001 l3_type = hns3_rx_ptype_tbl[ptype].l3_type; 4002 } else { 4003 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 4004 HNS3_RXD_L3ID_S); 4005 } 4006 4007 if (l3_type == HNS3_L3_TYPE_IPV4) 4008 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 4009 else if (l3_type == HNS3_L3_TYPE_IPV6) 4010 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 4011 else 4012 return -EFAULT; 4013 4014 return hns3_gro_complete(skb, l234info); 4015 } 4016 4017 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 4018 struct sk_buff *skb, u32 rss_hash) 4019 { 4020 struct hnae3_handle *handle = ring->tqp->handle; 4021 enum pkt_hash_types rss_type; 4022 4023 if (rss_hash) 4024 rss_type = handle->kinfo.rss_type; 4025 else 4026 rss_type = PKT_HASH_TYPE_NONE; 4027 4028 skb_set_hash(skb, rss_hash, rss_type); 4029 } 4030 4031 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb) 4032 { 4033 struct net_device *netdev = ring_to_netdev(ring); 4034 enum hns3_pkt_l2t_type l2_frame_type; 4035 u32 bd_base_info, l234info, ol_info; 4036 struct hns3_desc *desc; 4037 unsigned int len; 4038 int pre_ntc, ret; 4039 u16 csum; 4040 4041 /* bdinfo handled below is only valid on the last BD of the 4042 * current packet, and ring->next_to_clean indicates the first 4043 * descriptor of next packet, so need - 1 below. 4044 */ 4045 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) : 4046 (ring->desc_num - 1); 4047 desc = &ring->desc[pre_ntc]; 4048 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 4049 l234info = le32_to_cpu(desc->rx.l234_info); 4050 ol_info = le32_to_cpu(desc->rx.ol_info); 4051 csum = le16_to_cpu(desc->csum); 4052 4053 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) { 4054 struct hnae3_handle *h = hns3_get_handle(netdev); 4055 u32 nsec = le32_to_cpu(desc->ts_nsec); 4056 u32 sec = le32_to_cpu(desc->ts_sec); 4057 4058 if (h->ae_algo->ops->get_rx_hwts) 4059 h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec); 4060 } 4061 4062 /* Based on hw strategy, the tag offloaded will be stored at 4063 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 4064 * in one layer tag case. 4065 */ 4066 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 4067 u16 vlan_tag; 4068 4069 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 4070 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 4071 vlan_tag); 4072 } 4073 4074 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 4075 BIT(HNS3_RXD_L2E_B))))) { 4076 u64_stats_update_begin(&ring->syncp); 4077 if (l234info & BIT(HNS3_RXD_L2E_B)) 4078 ring->stats.l2_err++; 4079 else 4080 ring->stats.err_pkt_len++; 4081 u64_stats_update_end(&ring->syncp); 4082 4083 return -EFAULT; 4084 } 4085 4086 len = skb->len; 4087 4088 /* Do update ip stack process */ 4089 skb->protocol = eth_type_trans(skb, netdev); 4090 4091 /* This is needed in order to enable forwarding support */ 4092 ret = hns3_set_gro_and_checksum(ring, skb, l234info, 4093 bd_base_info, ol_info, csum); 4094 if (unlikely(ret)) { 4095 u64_stats_update_begin(&ring->syncp); 4096 ring->stats.rx_err_cnt++; 4097 u64_stats_update_end(&ring->syncp); 4098 return ret; 4099 } 4100 4101 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 4102 HNS3_RXD_DMAC_S); 4103 4104 u64_stats_update_begin(&ring->syncp); 4105 ring->stats.rx_pkts++; 4106 ring->stats.rx_bytes += len; 4107 4108 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 4109 ring->stats.rx_multicast++; 4110 4111 u64_stats_update_end(&ring->syncp); 4112 4113 ring->tqp_vector->rx_group.total_bytes += len; 4114 4115 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash)); 4116 return 0; 4117 } 4118 4119 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring) 4120 { 4121 struct sk_buff *skb = ring->skb; 4122 struct hns3_desc_cb *desc_cb; 4123 struct hns3_desc *desc; 4124 unsigned int length; 4125 u32 bd_base_info; 4126 int ret; 4127 4128 desc = &ring->desc[ring->next_to_clean]; 4129 desc_cb = &ring->desc_cb[ring->next_to_clean]; 4130 4131 prefetch(desc); 4132 4133 if (!skb) { 4134 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 4135 /* Check valid BD */ 4136 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 4137 return -ENXIO; 4138 4139 dma_rmb(); 4140 length = le16_to_cpu(desc->rx.size); 4141 4142 ring->va = desc_cb->buf + desc_cb->page_offset; 4143 4144 dma_sync_single_for_cpu(ring_to_dev(ring), 4145 desc_cb->dma + desc_cb->page_offset, 4146 hns3_buf_size(ring), 4147 DMA_FROM_DEVICE); 4148 4149 /* Prefetch first cache line of first page. 4150 * Idea is to cache few bytes of the header of the packet. 4151 * Our L1 Cache line size is 64B so need to prefetch twice to make 4152 * it 128B. But in actual we can have greater size of caches with 4153 * 128B Level 1 cache lines. In such a case, single fetch would 4154 * suffice to cache in the relevant part of the header. 4155 */ 4156 net_prefetch(ring->va); 4157 4158 ret = hns3_alloc_skb(ring, length, ring->va); 4159 skb = ring->skb; 4160 4161 if (ret < 0) /* alloc buffer fail */ 4162 return ret; 4163 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */ 4164 ret = hns3_add_frag(ring); 4165 if (ret) 4166 return ret; 4167 } 4168 } else { 4169 ret = hns3_add_frag(ring); 4170 if (ret) 4171 return ret; 4172 } 4173 4174 /* As the head data may be changed when GRO enable, copy 4175 * the head data in after other data rx completed 4176 */ 4177 if (skb->len > HNS3_RX_HEAD_SIZE) 4178 memcpy(skb->data, ring->va, 4179 ALIGN(ring->pull_len, sizeof(long))); 4180 4181 ret = hns3_handle_bdinfo(ring, skb); 4182 if (unlikely(ret)) { 4183 dev_kfree_skb_any(skb); 4184 return ret; 4185 } 4186 4187 skb_record_rx_queue(skb, ring->tqp->tqp_index); 4188 return 0; 4189 } 4190 4191 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget, 4192 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 4193 { 4194 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 4195 int unused_count = hns3_desc_unused(ring); 4196 int recv_pkts = 0; 4197 int err; 4198 4199 unused_count -= ring->pending_buf; 4200 4201 while (recv_pkts < budget) { 4202 /* Reuse or realloc buffers */ 4203 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 4204 hns3_nic_alloc_rx_buffers(ring, unused_count); 4205 unused_count = hns3_desc_unused(ring) - 4206 ring->pending_buf; 4207 } 4208 4209 /* Poll one pkt */ 4210 err = hns3_handle_rx_bd(ring); 4211 /* Do not get FE for the packet or failed to alloc skb */ 4212 if (unlikely(!ring->skb || err == -ENXIO)) { 4213 goto out; 4214 } else if (likely(!err)) { 4215 rx_fn(ring, ring->skb); 4216 recv_pkts++; 4217 } 4218 4219 unused_count += ring->pending_buf; 4220 ring->skb = NULL; 4221 ring->pending_buf = 0; 4222 } 4223 4224 out: 4225 /* Make all data has been write before submit */ 4226 if (unused_count > 0) 4227 hns3_nic_alloc_rx_buffers(ring, unused_count); 4228 4229 return recv_pkts; 4230 } 4231 4232 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector) 4233 { 4234 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 4235 struct dim_sample sample = {}; 4236 4237 if (!rx_group->coal.adapt_enable) 4238 return; 4239 4240 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets, 4241 rx_group->total_bytes, &sample); 4242 net_dim(&rx_group->dim, sample); 4243 } 4244 4245 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector) 4246 { 4247 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 4248 struct dim_sample sample = {}; 4249 4250 if (!tx_group->coal.adapt_enable) 4251 return; 4252 4253 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets, 4254 tx_group->total_bytes, &sample); 4255 net_dim(&tx_group->dim, sample); 4256 } 4257 4258 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 4259 { 4260 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 4261 struct hns3_enet_ring *ring; 4262 int rx_pkt_total = 0; 4263 4264 struct hns3_enet_tqp_vector *tqp_vector = 4265 container_of(napi, struct hns3_enet_tqp_vector, napi); 4266 bool clean_complete = true; 4267 int rx_budget = budget; 4268 4269 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 4270 napi_complete(napi); 4271 return 0; 4272 } 4273 4274 /* Since the actual Tx work is minimal, we can give the Tx a larger 4275 * budget and be more aggressive about cleaning up the Tx descriptors. 4276 */ 4277 hns3_for_each_ring(ring, tqp_vector->tx_group) 4278 hns3_clean_tx_ring(ring, budget); 4279 4280 /* make sure rx ring budget not smaller than 1 */ 4281 if (tqp_vector->num_tqps > 1) 4282 rx_budget = max(budget / tqp_vector->num_tqps, 1); 4283 4284 hns3_for_each_ring(ring, tqp_vector->rx_group) { 4285 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 4286 hns3_rx_skb); 4287 if (rx_cleaned >= rx_budget) 4288 clean_complete = false; 4289 4290 rx_pkt_total += rx_cleaned; 4291 } 4292 4293 tqp_vector->rx_group.total_packets += rx_pkt_total; 4294 4295 if (!clean_complete) 4296 return budget; 4297 4298 if (napi_complete(napi) && 4299 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 4300 hns3_update_rx_int_coalesce(tqp_vector); 4301 hns3_update_tx_int_coalesce(tqp_vector); 4302 4303 hns3_mask_vector_irq(tqp_vector, 1); 4304 } 4305 4306 return rx_pkt_total; 4307 } 4308 4309 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 4310 struct hnae3_ring_chain_node *head) 4311 { 4312 struct pci_dev *pdev = tqp_vector->handle->pdev; 4313 struct hnae3_ring_chain_node *cur_chain = head; 4314 struct hnae3_ring_chain_node *chain; 4315 struct hns3_enet_ring *tx_ring; 4316 struct hns3_enet_ring *rx_ring; 4317 4318 tx_ring = tqp_vector->tx_group.ring; 4319 if (tx_ring) { 4320 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 4321 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 4322 HNAE3_RING_TYPE_TX); 4323 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 4324 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 4325 4326 cur_chain->next = NULL; 4327 4328 while (tx_ring->next) { 4329 tx_ring = tx_ring->next; 4330 4331 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 4332 GFP_KERNEL); 4333 if (!chain) 4334 goto err_free_chain; 4335 4336 cur_chain->next = chain; 4337 chain->tqp_index = tx_ring->tqp->tqp_index; 4338 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 4339 HNAE3_RING_TYPE_TX); 4340 hnae3_set_field(chain->int_gl_idx, 4341 HNAE3_RING_GL_IDX_M, 4342 HNAE3_RING_GL_IDX_S, 4343 HNAE3_RING_GL_TX); 4344 4345 cur_chain = chain; 4346 } 4347 } 4348 4349 rx_ring = tqp_vector->rx_group.ring; 4350 if (!tx_ring && rx_ring) { 4351 cur_chain->next = NULL; 4352 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 4353 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 4354 HNAE3_RING_TYPE_RX); 4355 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 4356 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 4357 4358 rx_ring = rx_ring->next; 4359 } 4360 4361 while (rx_ring) { 4362 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 4363 if (!chain) 4364 goto err_free_chain; 4365 4366 cur_chain->next = chain; 4367 chain->tqp_index = rx_ring->tqp->tqp_index; 4368 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 4369 HNAE3_RING_TYPE_RX); 4370 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 4371 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 4372 4373 cur_chain = chain; 4374 4375 rx_ring = rx_ring->next; 4376 } 4377 4378 return 0; 4379 4380 err_free_chain: 4381 cur_chain = head->next; 4382 while (cur_chain) { 4383 chain = cur_chain->next; 4384 devm_kfree(&pdev->dev, cur_chain); 4385 cur_chain = chain; 4386 } 4387 head->next = NULL; 4388 4389 return -ENOMEM; 4390 } 4391 4392 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 4393 struct hnae3_ring_chain_node *head) 4394 { 4395 struct pci_dev *pdev = tqp_vector->handle->pdev; 4396 struct hnae3_ring_chain_node *chain_tmp, *chain; 4397 4398 chain = head->next; 4399 4400 while (chain) { 4401 chain_tmp = chain->next; 4402 devm_kfree(&pdev->dev, chain); 4403 chain = chain_tmp; 4404 } 4405 } 4406 4407 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 4408 struct hns3_enet_ring *ring) 4409 { 4410 ring->next = group->ring; 4411 group->ring = ring; 4412 4413 group->count++; 4414 } 4415 4416 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 4417 { 4418 struct pci_dev *pdev = priv->ae_handle->pdev; 4419 struct hns3_enet_tqp_vector *tqp_vector; 4420 int num_vectors = priv->vector_num; 4421 int numa_node; 4422 int vector_i; 4423 4424 numa_node = dev_to_node(&pdev->dev); 4425 4426 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 4427 tqp_vector = &priv->tqp_vector[vector_i]; 4428 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 4429 &tqp_vector->affinity_mask); 4430 } 4431 } 4432 4433 static void hns3_rx_dim_work(struct work_struct *work) 4434 { 4435 struct dim *dim = container_of(work, struct dim, work); 4436 struct hns3_enet_ring_group *group = container_of(dim, 4437 struct hns3_enet_ring_group, dim); 4438 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector; 4439 struct dim_cq_moder cur_moder = 4440 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 4441 4442 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec); 4443 tqp_vector->rx_group.coal.int_gl = cur_moder.usec; 4444 4445 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) { 4446 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts); 4447 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts; 4448 } 4449 4450 dim->state = DIM_START_MEASURE; 4451 } 4452 4453 static void hns3_tx_dim_work(struct work_struct *work) 4454 { 4455 struct dim *dim = container_of(work, struct dim, work); 4456 struct hns3_enet_ring_group *group = container_of(dim, 4457 struct hns3_enet_ring_group, dim); 4458 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector; 4459 struct dim_cq_moder cur_moder = 4460 net_dim_get_tx_moderation(dim->mode, dim->profile_ix); 4461 4462 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec); 4463 tqp_vector->tx_group.coal.int_gl = cur_moder.usec; 4464 4465 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) { 4466 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts); 4467 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts; 4468 } 4469 4470 dim->state = DIM_START_MEASURE; 4471 } 4472 4473 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector) 4474 { 4475 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work); 4476 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work); 4477 } 4478 4479 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 4480 { 4481 struct hnae3_handle *h = priv->ae_handle; 4482 struct hns3_enet_tqp_vector *tqp_vector; 4483 int ret; 4484 int i; 4485 4486 hns3_nic_set_cpumask(priv); 4487 4488 for (i = 0; i < priv->vector_num; i++) { 4489 tqp_vector = &priv->tqp_vector[i]; 4490 hns3_vector_coalesce_init_hw(tqp_vector, priv); 4491 tqp_vector->num_tqps = 0; 4492 hns3_nic_init_dim(tqp_vector); 4493 } 4494 4495 for (i = 0; i < h->kinfo.num_tqps; i++) { 4496 u16 vector_i = i % priv->vector_num; 4497 u16 tqp_num = h->kinfo.num_tqps; 4498 4499 tqp_vector = &priv->tqp_vector[vector_i]; 4500 4501 hns3_add_ring_to_group(&tqp_vector->tx_group, 4502 &priv->ring[i]); 4503 4504 hns3_add_ring_to_group(&tqp_vector->rx_group, 4505 &priv->ring[i + tqp_num]); 4506 4507 priv->ring[i].tqp_vector = tqp_vector; 4508 priv->ring[i + tqp_num].tqp_vector = tqp_vector; 4509 tqp_vector->num_tqps++; 4510 } 4511 4512 for (i = 0; i < priv->vector_num; i++) { 4513 struct hnae3_ring_chain_node vector_ring_chain; 4514 4515 tqp_vector = &priv->tqp_vector[i]; 4516 4517 tqp_vector->rx_group.total_bytes = 0; 4518 tqp_vector->rx_group.total_packets = 0; 4519 tqp_vector->tx_group.total_bytes = 0; 4520 tqp_vector->tx_group.total_packets = 0; 4521 tqp_vector->handle = h; 4522 4523 ret = hns3_get_vector_ring_chain(tqp_vector, 4524 &vector_ring_chain); 4525 if (ret) 4526 goto map_ring_fail; 4527 4528 ret = h->ae_algo->ops->map_ring_to_vector(h, 4529 tqp_vector->vector_irq, &vector_ring_chain); 4530 4531 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 4532 4533 if (ret) 4534 goto map_ring_fail; 4535 4536 netif_napi_add(priv->netdev, &tqp_vector->napi, 4537 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 4538 } 4539 4540 return 0; 4541 4542 map_ring_fail: 4543 while (i--) 4544 netif_napi_del(&priv->tqp_vector[i].napi); 4545 4546 return ret; 4547 } 4548 4549 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv) 4550 { 4551 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 4552 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal; 4553 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal; 4554 4555 /* initialize the configuration for interrupt coalescing. 4556 * 1. GL (Interrupt Gap Limiter) 4557 * 2. RL (Interrupt Rate Limiter) 4558 * 3. QL (Interrupt Quantity Limiter) 4559 * 4560 * Default: enable interrupt coalescing self-adaptive and GL 4561 */ 4562 tx_coal->adapt_enable = 1; 4563 rx_coal->adapt_enable = 1; 4564 4565 tx_coal->int_gl = HNS3_INT_GL_50K; 4566 rx_coal->int_gl = HNS3_INT_GL_50K; 4567 4568 rx_coal->flow_level = HNS3_FLOW_LOW; 4569 tx_coal->flow_level = HNS3_FLOW_LOW; 4570 4571 if (ae_dev->dev_specs.int_ql_max) { 4572 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 4573 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 4574 } 4575 } 4576 4577 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 4578 { 4579 struct hnae3_handle *h = priv->ae_handle; 4580 struct hns3_enet_tqp_vector *tqp_vector; 4581 struct hnae3_vector_info *vector; 4582 struct pci_dev *pdev = h->pdev; 4583 u16 tqp_num = h->kinfo.num_tqps; 4584 u16 vector_num; 4585 int ret = 0; 4586 u16 i; 4587 4588 /* RSS size, cpu online and vector_num should be the same */ 4589 /* Should consider 2p/4p later */ 4590 vector_num = min_t(u16, num_online_cpus(), tqp_num); 4591 4592 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 4593 GFP_KERNEL); 4594 if (!vector) 4595 return -ENOMEM; 4596 4597 /* save the actual available vector number */ 4598 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 4599 4600 priv->vector_num = vector_num; 4601 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 4602 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 4603 GFP_KERNEL); 4604 if (!priv->tqp_vector) { 4605 ret = -ENOMEM; 4606 goto out; 4607 } 4608 4609 for (i = 0; i < priv->vector_num; i++) { 4610 tqp_vector = &priv->tqp_vector[i]; 4611 tqp_vector->idx = i; 4612 tqp_vector->mask_addr = vector[i].io_addr; 4613 tqp_vector->vector_irq = vector[i].vector; 4614 hns3_vector_coalesce_init(tqp_vector, priv); 4615 } 4616 4617 out: 4618 devm_kfree(&pdev->dev, vector); 4619 return ret; 4620 } 4621 4622 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 4623 { 4624 group->ring = NULL; 4625 group->count = 0; 4626 } 4627 4628 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 4629 { 4630 struct hnae3_ring_chain_node vector_ring_chain; 4631 struct hnae3_handle *h = priv->ae_handle; 4632 struct hns3_enet_tqp_vector *tqp_vector; 4633 int i; 4634 4635 for (i = 0; i < priv->vector_num; i++) { 4636 tqp_vector = &priv->tqp_vector[i]; 4637 4638 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 4639 continue; 4640 4641 /* Since the mapping can be overwritten, when fail to get the 4642 * chain between vector and ring, we should go on to deal with 4643 * the remaining options. 4644 */ 4645 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain)) 4646 dev_warn(priv->dev, "failed to get ring chain\n"); 4647 4648 h->ae_algo->ops->unmap_ring_from_vector(h, 4649 tqp_vector->vector_irq, &vector_ring_chain); 4650 4651 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 4652 4653 hns3_clear_ring_group(&tqp_vector->rx_group); 4654 hns3_clear_ring_group(&tqp_vector->tx_group); 4655 netif_napi_del(&priv->tqp_vector[i].napi); 4656 } 4657 } 4658 4659 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 4660 { 4661 struct hnae3_handle *h = priv->ae_handle; 4662 struct pci_dev *pdev = h->pdev; 4663 int i, ret; 4664 4665 for (i = 0; i < priv->vector_num; i++) { 4666 struct hns3_enet_tqp_vector *tqp_vector; 4667 4668 tqp_vector = &priv->tqp_vector[i]; 4669 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 4670 if (ret) 4671 return; 4672 } 4673 4674 devm_kfree(&pdev->dev, priv->tqp_vector); 4675 } 4676 4677 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 4678 unsigned int ring_type) 4679 { 4680 int queue_num = priv->ae_handle->kinfo.num_tqps; 4681 struct hns3_enet_ring *ring; 4682 int desc_num; 4683 4684 if (ring_type == HNAE3_RING_TYPE_TX) { 4685 ring = &priv->ring[q->tqp_index]; 4686 desc_num = priv->ae_handle->kinfo.num_tx_desc; 4687 ring->queue_index = q->tqp_index; 4688 ring->tx_copybreak = priv->tx_copybreak; 4689 ring->last_to_use = 0; 4690 } else { 4691 ring = &priv->ring[q->tqp_index + queue_num]; 4692 desc_num = priv->ae_handle->kinfo.num_rx_desc; 4693 ring->queue_index = q->tqp_index; 4694 ring->rx_copybreak = priv->rx_copybreak; 4695 } 4696 4697 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 4698 4699 ring->tqp = q; 4700 ring->desc = NULL; 4701 ring->desc_cb = NULL; 4702 ring->dev = priv->dev; 4703 ring->desc_dma_addr = 0; 4704 ring->buf_size = q->buf_size; 4705 ring->desc_num = desc_num; 4706 ring->next_to_use = 0; 4707 ring->next_to_clean = 0; 4708 } 4709 4710 static void hns3_queue_to_ring(struct hnae3_queue *tqp, 4711 struct hns3_nic_priv *priv) 4712 { 4713 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 4714 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 4715 } 4716 4717 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 4718 { 4719 struct hnae3_handle *h = priv->ae_handle; 4720 struct pci_dev *pdev = h->pdev; 4721 int i; 4722 4723 priv->ring = devm_kzalloc(&pdev->dev, 4724 array3_size(h->kinfo.num_tqps, 4725 sizeof(*priv->ring), 2), 4726 GFP_KERNEL); 4727 if (!priv->ring) 4728 return -ENOMEM; 4729 4730 for (i = 0; i < h->kinfo.num_tqps; i++) 4731 hns3_queue_to_ring(h->kinfo.tqp[i], priv); 4732 4733 return 0; 4734 } 4735 4736 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 4737 { 4738 if (!priv->ring) 4739 return; 4740 4741 devm_kfree(priv->dev, priv->ring); 4742 priv->ring = NULL; 4743 } 4744 4745 static void hns3_alloc_page_pool(struct hns3_enet_ring *ring) 4746 { 4747 struct page_pool_params pp_params = { 4748 .flags = PP_FLAG_DMA_MAP | PP_FLAG_PAGE_FRAG | 4749 PP_FLAG_DMA_SYNC_DEV, 4750 .order = hns3_page_order(ring), 4751 .pool_size = ring->desc_num * hns3_buf_size(ring) / 4752 (PAGE_SIZE << hns3_page_order(ring)), 4753 .nid = dev_to_node(ring_to_dev(ring)), 4754 .dev = ring_to_dev(ring), 4755 .dma_dir = DMA_FROM_DEVICE, 4756 .offset = 0, 4757 .max_len = PAGE_SIZE << hns3_page_order(ring), 4758 }; 4759 4760 ring->page_pool = page_pool_create(&pp_params); 4761 if (IS_ERR(ring->page_pool)) { 4762 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n", 4763 PTR_ERR(ring->page_pool)); 4764 ring->page_pool = NULL; 4765 } 4766 } 4767 4768 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 4769 { 4770 int ret; 4771 4772 if (ring->desc_num <= 0 || ring->buf_size <= 0) 4773 return -EINVAL; 4774 4775 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num, 4776 sizeof(ring->desc_cb[0]), GFP_KERNEL); 4777 if (!ring->desc_cb) { 4778 ret = -ENOMEM; 4779 goto out; 4780 } 4781 4782 ret = hns3_alloc_desc(ring); 4783 if (ret) 4784 goto out_with_desc_cb; 4785 4786 if (!HNAE3_IS_TX_RING(ring)) { 4787 hns3_alloc_page_pool(ring); 4788 4789 ret = hns3_alloc_ring_buffers(ring); 4790 if (ret) 4791 goto out_with_desc; 4792 } else { 4793 hns3_init_tx_spare_buffer(ring); 4794 } 4795 4796 return 0; 4797 4798 out_with_desc: 4799 hns3_free_desc(ring); 4800 out_with_desc_cb: 4801 devm_kfree(ring_to_dev(ring), ring->desc_cb); 4802 ring->desc_cb = NULL; 4803 out: 4804 return ret; 4805 } 4806 4807 void hns3_fini_ring(struct hns3_enet_ring *ring) 4808 { 4809 hns3_free_desc(ring); 4810 devm_kfree(ring_to_dev(ring), ring->desc_cb); 4811 ring->desc_cb = NULL; 4812 ring->next_to_clean = 0; 4813 ring->next_to_use = 0; 4814 ring->last_to_use = 0; 4815 ring->pending_buf = 0; 4816 if (!HNAE3_IS_TX_RING(ring) && ring->skb) { 4817 dev_kfree_skb_any(ring->skb); 4818 ring->skb = NULL; 4819 } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) { 4820 struct hns3_tx_spare *tx_spare = ring->tx_spare; 4821 4822 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len, 4823 DMA_TO_DEVICE); 4824 free_pages((unsigned long)tx_spare->buf, 4825 get_order(tx_spare->len)); 4826 devm_kfree(ring_to_dev(ring), tx_spare); 4827 ring->tx_spare = NULL; 4828 } 4829 4830 if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) { 4831 page_pool_destroy(ring->page_pool); 4832 ring->page_pool = NULL; 4833 } 4834 } 4835 4836 static int hns3_buf_size2type(u32 buf_size) 4837 { 4838 int bd_size_type; 4839 4840 switch (buf_size) { 4841 case 512: 4842 bd_size_type = HNS3_BD_SIZE_512_TYPE; 4843 break; 4844 case 1024: 4845 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 4846 break; 4847 case 2048: 4848 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 4849 break; 4850 case 4096: 4851 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 4852 break; 4853 default: 4854 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 4855 } 4856 4857 return bd_size_type; 4858 } 4859 4860 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 4861 { 4862 dma_addr_t dma = ring->desc_dma_addr; 4863 struct hnae3_queue *q = ring->tqp; 4864 4865 if (!HNAE3_IS_TX_RING(ring)) { 4866 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma); 4867 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 4868 (u32)((dma >> 31) >> 1)); 4869 4870 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 4871 hns3_buf_size2type(ring->buf_size)); 4872 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 4873 ring->desc_num / 8 - 1); 4874 } else { 4875 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 4876 (u32)dma); 4877 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 4878 (u32)((dma >> 31) >> 1)); 4879 4880 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 4881 ring->desc_num / 8 - 1); 4882 } 4883 } 4884 4885 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 4886 { 4887 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 4888 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 4889 int i; 4890 4891 for (i = 0; i < HNAE3_MAX_TC; i++) { 4892 int j; 4893 4894 if (!test_bit(i, &tc_info->tc_en)) 4895 continue; 4896 4897 for (j = 0; j < tc_info->tqp_count[i]; j++) { 4898 struct hnae3_queue *q; 4899 4900 q = priv->ring[tc_info->tqp_offset[i] + j].tqp; 4901 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i); 4902 } 4903 } 4904 } 4905 4906 int hns3_init_all_ring(struct hns3_nic_priv *priv) 4907 { 4908 struct hnae3_handle *h = priv->ae_handle; 4909 int ring_num = h->kinfo.num_tqps * 2; 4910 int i, j; 4911 int ret; 4912 4913 for (i = 0; i < ring_num; i++) { 4914 ret = hns3_alloc_ring_memory(&priv->ring[i]); 4915 if (ret) { 4916 dev_err(priv->dev, 4917 "Alloc ring memory fail! ret=%d\n", ret); 4918 goto out_when_alloc_ring_memory; 4919 } 4920 4921 u64_stats_init(&priv->ring[i].syncp); 4922 } 4923 4924 return 0; 4925 4926 out_when_alloc_ring_memory: 4927 for (j = i - 1; j >= 0; j--) 4928 hns3_fini_ring(&priv->ring[j]); 4929 4930 return -ENOMEM; 4931 } 4932 4933 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv) 4934 { 4935 struct hnae3_handle *h = priv->ae_handle; 4936 int i; 4937 4938 for (i = 0; i < h->kinfo.num_tqps; i++) { 4939 hns3_fini_ring(&priv->ring[i]); 4940 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]); 4941 } 4942 } 4943 4944 /* Set mac addr if it is configured. or leave it to the AE driver */ 4945 static int hns3_init_mac_addr(struct net_device *netdev) 4946 { 4947 struct hns3_nic_priv *priv = netdev_priv(netdev); 4948 struct hnae3_handle *h = priv->ae_handle; 4949 u8 mac_addr_temp[ETH_ALEN]; 4950 int ret = 0; 4951 4952 if (h->ae_algo->ops->get_mac_addr) 4953 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 4954 4955 /* Check if the MAC address is valid, if not get a random one */ 4956 if (!is_valid_ether_addr(mac_addr_temp)) { 4957 eth_hw_addr_random(netdev); 4958 dev_warn(priv->dev, "using random MAC address %pM\n", 4959 netdev->dev_addr); 4960 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) { 4961 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 4962 ether_addr_copy(netdev->perm_addr, mac_addr_temp); 4963 } else { 4964 return 0; 4965 } 4966 4967 if (h->ae_algo->ops->set_mac_addr) 4968 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 4969 4970 return ret; 4971 } 4972 4973 static int hns3_init_phy(struct net_device *netdev) 4974 { 4975 struct hnae3_handle *h = hns3_get_handle(netdev); 4976 int ret = 0; 4977 4978 if (h->ae_algo->ops->mac_connect_phy) 4979 ret = h->ae_algo->ops->mac_connect_phy(h); 4980 4981 return ret; 4982 } 4983 4984 static void hns3_uninit_phy(struct net_device *netdev) 4985 { 4986 struct hnae3_handle *h = hns3_get_handle(netdev); 4987 4988 if (h->ae_algo->ops->mac_disconnect_phy) 4989 h->ae_algo->ops->mac_disconnect_phy(h); 4990 } 4991 4992 static int hns3_client_start(struct hnae3_handle *handle) 4993 { 4994 if (!handle->ae_algo->ops->client_start) 4995 return 0; 4996 4997 return handle->ae_algo->ops->client_start(handle); 4998 } 4999 5000 static void hns3_client_stop(struct hnae3_handle *handle) 5001 { 5002 if (!handle->ae_algo->ops->client_stop) 5003 return; 5004 5005 handle->ae_algo->ops->client_stop(handle); 5006 } 5007 5008 static void hns3_info_show(struct hns3_nic_priv *priv) 5009 { 5010 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 5011 5012 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr); 5013 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps); 5014 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size); 5015 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size); 5016 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len); 5017 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc); 5018 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc); 5019 dev_info(priv->dev, "Total number of enabled TCs: %u\n", 5020 kinfo->tc_info.num_tc); 5021 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu); 5022 } 5023 5024 static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv, 5025 enum dim_cq_period_mode mode, bool is_tx) 5026 { 5027 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 5028 struct hnae3_handle *handle = priv->ae_handle; 5029 int i; 5030 5031 if (is_tx) { 5032 priv->tx_cqe_mode = mode; 5033 5034 for (i = 0; i < priv->vector_num; i++) 5035 priv->tqp_vector[i].tx_group.dim.mode = mode; 5036 } else { 5037 priv->rx_cqe_mode = mode; 5038 5039 for (i = 0; i < priv->vector_num; i++) 5040 priv->tqp_vector[i].rx_group.dim.mode = mode; 5041 } 5042 5043 /* only device version above V3(include V3), GL can switch CQ/EQ 5044 * period mode. 5045 */ 5046 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) { 5047 u32 new_mode; 5048 u64 reg; 5049 5050 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ? 5051 HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE; 5052 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG; 5053 5054 writel(new_mode, handle->kinfo.io_base + reg); 5055 } 5056 } 5057 5058 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv, 5059 enum dim_cq_period_mode tx_mode, 5060 enum dim_cq_period_mode rx_mode) 5061 { 5062 hns3_set_cq_period_mode(priv, tx_mode, true); 5063 hns3_set_cq_period_mode(priv, rx_mode, false); 5064 } 5065 5066 static int hns3_client_init(struct hnae3_handle *handle) 5067 { 5068 struct pci_dev *pdev = handle->pdev; 5069 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 5070 u16 alloc_tqps, max_rss_size; 5071 struct hns3_nic_priv *priv; 5072 struct net_device *netdev; 5073 int ret; 5074 5075 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 5076 &max_rss_size); 5077 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 5078 if (!netdev) 5079 return -ENOMEM; 5080 5081 priv = netdev_priv(netdev); 5082 priv->dev = &pdev->dev; 5083 priv->netdev = netdev; 5084 priv->ae_handle = handle; 5085 priv->tx_timeout_count = 0; 5086 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num; 5087 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 5088 5089 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL); 5090 5091 handle->kinfo.netdev = netdev; 5092 handle->priv = (void *)priv; 5093 5094 hns3_init_mac_addr(netdev); 5095 5096 hns3_set_default_feature(netdev); 5097 5098 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 5099 netdev->priv_flags |= IFF_UNICAST_FLT; 5100 netdev->netdev_ops = &hns3_nic_netdev_ops; 5101 SET_NETDEV_DEV(netdev, &pdev->dev); 5102 hns3_ethtool_set_ops(netdev); 5103 5104 /* Carrier off reporting is important to ethtool even BEFORE open */ 5105 netif_carrier_off(netdev); 5106 5107 ret = hns3_get_ring_config(priv); 5108 if (ret) { 5109 ret = -ENOMEM; 5110 goto out_get_ring_cfg; 5111 } 5112 5113 hns3_nic_init_coal_cfg(priv); 5114 5115 ret = hns3_nic_alloc_vector_data(priv); 5116 if (ret) { 5117 ret = -ENOMEM; 5118 goto out_alloc_vector_data; 5119 } 5120 5121 ret = hns3_nic_init_vector_data(priv); 5122 if (ret) { 5123 ret = -ENOMEM; 5124 goto out_init_vector_data; 5125 } 5126 5127 ret = hns3_init_all_ring(priv); 5128 if (ret) { 5129 ret = -ENOMEM; 5130 goto out_init_ring; 5131 } 5132 5133 hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE, 5134 DIM_CQ_PERIOD_MODE_START_FROM_EQE); 5135 5136 ret = hns3_init_phy(netdev); 5137 if (ret) 5138 goto out_init_phy; 5139 5140 /* the device can work without cpu rmap, only aRFS needs it */ 5141 ret = hns3_set_rx_cpu_rmap(netdev); 5142 if (ret) 5143 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 5144 5145 ret = hns3_nic_init_irq(priv); 5146 if (ret) { 5147 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 5148 hns3_free_rx_cpu_rmap(netdev); 5149 goto out_init_irq_fail; 5150 } 5151 5152 ret = hns3_client_start(handle); 5153 if (ret) { 5154 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 5155 goto out_client_start; 5156 } 5157 5158 hns3_dcbnl_setup(handle); 5159 5160 ret = hns3_dbg_init(handle); 5161 if (ret) { 5162 dev_err(priv->dev, "failed to init debugfs, ret = %d\n", 5163 ret); 5164 goto out_client_start; 5165 } 5166 5167 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size); 5168 5169 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) 5170 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state); 5171 5172 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev)) 5173 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state); 5174 5175 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 5176 5177 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5178 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags); 5179 5180 ret = register_netdev(netdev); 5181 if (ret) { 5182 dev_err(priv->dev, "probe register netdev fail!\n"); 5183 goto out_reg_netdev_fail; 5184 } 5185 5186 if (netif_msg_drv(handle)) 5187 hns3_info_show(priv); 5188 5189 return ret; 5190 5191 out_reg_netdev_fail: 5192 hns3_dbg_uninit(handle); 5193 out_client_start: 5194 hns3_free_rx_cpu_rmap(netdev); 5195 hns3_nic_uninit_irq(priv); 5196 out_init_irq_fail: 5197 hns3_uninit_phy(netdev); 5198 out_init_phy: 5199 hns3_uninit_all_ring(priv); 5200 out_init_ring: 5201 hns3_nic_uninit_vector_data(priv); 5202 out_init_vector_data: 5203 hns3_nic_dealloc_vector_data(priv); 5204 out_alloc_vector_data: 5205 priv->ring = NULL; 5206 out_get_ring_cfg: 5207 priv->ae_handle = NULL; 5208 free_netdev(netdev); 5209 return ret; 5210 } 5211 5212 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 5213 { 5214 struct net_device *netdev = handle->kinfo.netdev; 5215 struct hns3_nic_priv *priv = netdev_priv(netdev); 5216 5217 if (netdev->reg_state != NETREG_UNINITIALIZED) 5218 unregister_netdev(netdev); 5219 5220 hns3_client_stop(handle); 5221 5222 hns3_uninit_phy(netdev); 5223 5224 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 5225 netdev_warn(netdev, "already uninitialized\n"); 5226 goto out_netdev_free; 5227 } 5228 5229 hns3_free_rx_cpu_rmap(netdev); 5230 5231 hns3_nic_uninit_irq(priv); 5232 5233 hns3_clear_all_ring(handle, true); 5234 5235 hns3_nic_uninit_vector_data(priv); 5236 5237 hns3_nic_dealloc_vector_data(priv); 5238 5239 hns3_uninit_all_ring(priv); 5240 5241 hns3_put_ring_config(priv); 5242 5243 out_netdev_free: 5244 hns3_dbg_uninit(handle); 5245 free_netdev(netdev); 5246 } 5247 5248 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 5249 { 5250 struct net_device *netdev = handle->kinfo.netdev; 5251 5252 if (!netdev) 5253 return; 5254 5255 if (linkup) { 5256 netif_tx_wake_all_queues(netdev); 5257 netif_carrier_on(netdev); 5258 if (netif_msg_link(handle)) 5259 netdev_info(netdev, "link up\n"); 5260 } else { 5261 netif_carrier_off(netdev); 5262 netif_tx_stop_all_queues(netdev); 5263 if (netif_msg_link(handle)) 5264 netdev_info(netdev, "link down\n"); 5265 } 5266 } 5267 5268 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 5269 { 5270 while (ring->next_to_clean != ring->next_to_use) { 5271 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 5272 hns3_free_buffer_detach(ring, ring->next_to_clean, 0); 5273 ring_ptr_move_fw(ring, next_to_clean); 5274 } 5275 5276 ring->pending_buf = 0; 5277 } 5278 5279 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 5280 { 5281 struct hns3_desc_cb res_cbs; 5282 int ret; 5283 5284 while (ring->next_to_use != ring->next_to_clean) { 5285 /* When a buffer is not reused, it's memory has been 5286 * freed in hns3_handle_rx_bd or will be freed by 5287 * stack, so we need to replace the buffer here. 5288 */ 5289 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 5290 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 5291 if (ret) { 5292 u64_stats_update_begin(&ring->syncp); 5293 ring->stats.sw_err_cnt++; 5294 u64_stats_update_end(&ring->syncp); 5295 /* if alloc new buffer fail, exit directly 5296 * and reclear in up flow. 5297 */ 5298 netdev_warn(ring_to_netdev(ring), 5299 "reserve buffer map failed, ret = %d\n", 5300 ret); 5301 return ret; 5302 } 5303 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 5304 } 5305 ring_ptr_move_fw(ring, next_to_use); 5306 } 5307 5308 /* Free the pending skb in rx ring */ 5309 if (ring->skb) { 5310 dev_kfree_skb_any(ring->skb); 5311 ring->skb = NULL; 5312 ring->pending_buf = 0; 5313 } 5314 5315 return 0; 5316 } 5317 5318 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 5319 { 5320 while (ring->next_to_use != ring->next_to_clean) { 5321 /* When a buffer is not reused, it's memory has been 5322 * freed in hns3_handle_rx_bd or will be freed by 5323 * stack, so only need to unmap the buffer here. 5324 */ 5325 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 5326 hns3_unmap_buffer(ring, 5327 &ring->desc_cb[ring->next_to_use]); 5328 ring->desc_cb[ring->next_to_use].dma = 0; 5329 } 5330 5331 ring_ptr_move_fw(ring, next_to_use); 5332 } 5333 } 5334 5335 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force) 5336 { 5337 struct net_device *ndev = h->kinfo.netdev; 5338 struct hns3_nic_priv *priv = netdev_priv(ndev); 5339 u32 i; 5340 5341 for (i = 0; i < h->kinfo.num_tqps; i++) { 5342 struct hns3_enet_ring *ring; 5343 5344 ring = &priv->ring[i]; 5345 hns3_clear_tx_ring(ring); 5346 5347 ring = &priv->ring[i + h->kinfo.num_tqps]; 5348 /* Continue to clear other rings even if clearing some 5349 * rings failed. 5350 */ 5351 if (force) 5352 hns3_force_clear_rx_ring(ring); 5353 else 5354 hns3_clear_rx_ring(ring); 5355 } 5356 } 5357 5358 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 5359 { 5360 struct net_device *ndev = h->kinfo.netdev; 5361 struct hns3_nic_priv *priv = netdev_priv(ndev); 5362 struct hns3_enet_ring *rx_ring; 5363 int i, j; 5364 int ret; 5365 5366 ret = h->ae_algo->ops->reset_queue(h); 5367 if (ret) 5368 return ret; 5369 5370 for (i = 0; i < h->kinfo.num_tqps; i++) { 5371 hns3_init_ring_hw(&priv->ring[i]); 5372 5373 /* We need to clear tx ring here because self test will 5374 * use the ring and will not run down before up 5375 */ 5376 hns3_clear_tx_ring(&priv->ring[i]); 5377 priv->ring[i].next_to_clean = 0; 5378 priv->ring[i].next_to_use = 0; 5379 priv->ring[i].last_to_use = 0; 5380 5381 rx_ring = &priv->ring[i + h->kinfo.num_tqps]; 5382 hns3_init_ring_hw(rx_ring); 5383 ret = hns3_clear_rx_ring(rx_ring); 5384 if (ret) 5385 return ret; 5386 5387 /* We can not know the hardware head and tail when this 5388 * function is called in reset flow, so we reuse all desc. 5389 */ 5390 for (j = 0; j < rx_ring->desc_num; j++) 5391 hns3_reuse_buffer(rx_ring, j); 5392 5393 rx_ring->next_to_clean = 0; 5394 rx_ring->next_to_use = 0; 5395 } 5396 5397 hns3_init_tx_ring_tc(priv); 5398 5399 return 0; 5400 } 5401 5402 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 5403 { 5404 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 5405 struct net_device *ndev = kinfo->netdev; 5406 struct hns3_nic_priv *priv = netdev_priv(ndev); 5407 5408 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 5409 return 0; 5410 5411 if (!netif_running(ndev)) 5412 return 0; 5413 5414 return hns3_nic_net_stop(ndev); 5415 } 5416 5417 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 5418 { 5419 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 5420 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 5421 int ret = 0; 5422 5423 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 5424 netdev_err(kinfo->netdev, "device is not initialized yet\n"); 5425 return -EFAULT; 5426 } 5427 5428 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 5429 5430 if (netif_running(kinfo->netdev)) { 5431 ret = hns3_nic_net_open(kinfo->netdev); 5432 if (ret) { 5433 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 5434 netdev_err(kinfo->netdev, 5435 "net up fail, ret=%d!\n", ret); 5436 return ret; 5437 } 5438 } 5439 5440 return ret; 5441 } 5442 5443 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 5444 { 5445 struct net_device *netdev = handle->kinfo.netdev; 5446 struct hns3_nic_priv *priv = netdev_priv(netdev); 5447 int ret; 5448 5449 /* Carrier off reporting is important to ethtool even BEFORE open */ 5450 netif_carrier_off(netdev); 5451 5452 ret = hns3_get_ring_config(priv); 5453 if (ret) 5454 return ret; 5455 5456 ret = hns3_nic_alloc_vector_data(priv); 5457 if (ret) 5458 goto err_put_ring; 5459 5460 ret = hns3_nic_init_vector_data(priv); 5461 if (ret) 5462 goto err_dealloc_vector; 5463 5464 ret = hns3_init_all_ring(priv); 5465 if (ret) 5466 goto err_uninit_vector; 5467 5468 hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode); 5469 5470 /* the device can work without cpu rmap, only aRFS needs it */ 5471 ret = hns3_set_rx_cpu_rmap(netdev); 5472 if (ret) 5473 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 5474 5475 ret = hns3_nic_init_irq(priv); 5476 if (ret) { 5477 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 5478 hns3_free_rx_cpu_rmap(netdev); 5479 goto err_init_irq_fail; 5480 } 5481 5482 if (!hns3_is_phys_func(handle->pdev)) 5483 hns3_init_mac_addr(netdev); 5484 5485 ret = hns3_client_start(handle); 5486 if (ret) { 5487 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 5488 goto err_client_start_fail; 5489 } 5490 5491 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 5492 5493 return ret; 5494 5495 err_client_start_fail: 5496 hns3_free_rx_cpu_rmap(netdev); 5497 hns3_nic_uninit_irq(priv); 5498 err_init_irq_fail: 5499 hns3_uninit_all_ring(priv); 5500 err_uninit_vector: 5501 hns3_nic_uninit_vector_data(priv); 5502 err_dealloc_vector: 5503 hns3_nic_dealloc_vector_data(priv); 5504 err_put_ring: 5505 hns3_put_ring_config(priv); 5506 5507 return ret; 5508 } 5509 5510 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 5511 { 5512 struct net_device *netdev = handle->kinfo.netdev; 5513 struct hns3_nic_priv *priv = netdev_priv(netdev); 5514 5515 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 5516 netdev_warn(netdev, "already uninitialized\n"); 5517 return 0; 5518 } 5519 5520 hns3_free_rx_cpu_rmap(netdev); 5521 hns3_nic_uninit_irq(priv); 5522 hns3_clear_all_ring(handle, true); 5523 hns3_reset_tx_queue(priv->ae_handle); 5524 5525 hns3_nic_uninit_vector_data(priv); 5526 5527 hns3_nic_dealloc_vector_data(priv); 5528 5529 hns3_uninit_all_ring(priv); 5530 5531 hns3_put_ring_config(priv); 5532 5533 return 0; 5534 } 5535 5536 static int hns3_reset_notify(struct hnae3_handle *handle, 5537 enum hnae3_reset_notify_type type) 5538 { 5539 int ret = 0; 5540 5541 switch (type) { 5542 case HNAE3_UP_CLIENT: 5543 ret = hns3_reset_notify_up_enet(handle); 5544 break; 5545 case HNAE3_DOWN_CLIENT: 5546 ret = hns3_reset_notify_down_enet(handle); 5547 break; 5548 case HNAE3_INIT_CLIENT: 5549 ret = hns3_reset_notify_init_enet(handle); 5550 break; 5551 case HNAE3_UNINIT_CLIENT: 5552 ret = hns3_reset_notify_uninit_enet(handle); 5553 break; 5554 default: 5555 break; 5556 } 5557 5558 return ret; 5559 } 5560 5561 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num, 5562 bool rxfh_configured) 5563 { 5564 int ret; 5565 5566 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num, 5567 rxfh_configured); 5568 if (ret) { 5569 dev_err(&handle->pdev->dev, 5570 "Change tqp num(%u) fail.\n", new_tqp_num); 5571 return ret; 5572 } 5573 5574 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT); 5575 if (ret) 5576 return ret; 5577 5578 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT); 5579 if (ret) 5580 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT); 5581 5582 return ret; 5583 } 5584 5585 int hns3_set_channels(struct net_device *netdev, 5586 struct ethtool_channels *ch) 5587 { 5588 struct hnae3_handle *h = hns3_get_handle(netdev); 5589 struct hnae3_knic_private_info *kinfo = &h->kinfo; 5590 bool rxfh_configured = netif_is_rxfh_configured(netdev); 5591 u32 new_tqp_num = ch->combined_count; 5592 u16 org_tqp_num; 5593 int ret; 5594 5595 if (hns3_nic_resetting(netdev)) 5596 return -EBUSY; 5597 5598 if (ch->rx_count || ch->tx_count) 5599 return -EINVAL; 5600 5601 if (kinfo->tc_info.mqprio_active) { 5602 dev_err(&netdev->dev, 5603 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n"); 5604 return -EINVAL; 5605 } 5606 5607 if (new_tqp_num > hns3_get_max_available_channels(h) || 5608 new_tqp_num < 1) { 5609 dev_err(&netdev->dev, 5610 "Change tqps fail, the tqp range is from 1 to %u", 5611 hns3_get_max_available_channels(h)); 5612 return -EINVAL; 5613 } 5614 5615 if (kinfo->rss_size == new_tqp_num) 5616 return 0; 5617 5618 netif_dbg(h, drv, netdev, 5619 "set channels: tqp_num=%u, rxfh=%d\n", 5620 new_tqp_num, rxfh_configured); 5621 5622 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 5623 if (ret) 5624 return ret; 5625 5626 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 5627 if (ret) 5628 return ret; 5629 5630 org_tqp_num = h->kinfo.num_tqps; 5631 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured); 5632 if (ret) { 5633 int ret1; 5634 5635 netdev_warn(netdev, 5636 "Change channels fail, revert to old value\n"); 5637 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured); 5638 if (ret1) { 5639 netdev_err(netdev, 5640 "revert to old channel fail\n"); 5641 return ret1; 5642 } 5643 5644 return ret; 5645 } 5646 5647 return 0; 5648 } 5649 5650 static const struct hns3_hw_error_info hns3_hw_err[] = { 5651 { .type = HNAE3_PPU_POISON_ERROR, 5652 .msg = "PPU poison" }, 5653 { .type = HNAE3_CMDQ_ECC_ERROR, 5654 .msg = "IMP CMDQ error" }, 5655 { .type = HNAE3_IMP_RD_POISON_ERROR, 5656 .msg = "IMP RD poison" }, 5657 { .type = HNAE3_ROCEE_AXI_RESP_ERROR, 5658 .msg = "ROCEE AXI RESP error" }, 5659 }; 5660 5661 static void hns3_process_hw_error(struct hnae3_handle *handle, 5662 enum hnae3_hw_error_type type) 5663 { 5664 int i; 5665 5666 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) { 5667 if (hns3_hw_err[i].type == type) { 5668 dev_err(&handle->pdev->dev, "Detected %s!\n", 5669 hns3_hw_err[i].msg); 5670 break; 5671 } 5672 } 5673 } 5674 5675 static const struct hnae3_client_ops client_ops = { 5676 .init_instance = hns3_client_init, 5677 .uninit_instance = hns3_client_uninit, 5678 .link_status_change = hns3_link_status_change, 5679 .reset_notify = hns3_reset_notify, 5680 .process_hw_error = hns3_process_hw_error, 5681 }; 5682 5683 /* hns3_init_module - Driver registration routine 5684 * hns3_init_module is the first routine called when the driver is 5685 * loaded. All it does is register with the PCI subsystem. 5686 */ 5687 static int __init hns3_init_module(void) 5688 { 5689 int ret; 5690 5691 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 5692 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 5693 5694 client.type = HNAE3_CLIENT_KNIC; 5695 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s", 5696 hns3_driver_name); 5697 5698 client.ops = &client_ops; 5699 5700 INIT_LIST_HEAD(&client.node); 5701 5702 hns3_dbg_register_debugfs(hns3_driver_name); 5703 5704 ret = hnae3_register_client(&client); 5705 if (ret) 5706 goto err_reg_client; 5707 5708 ret = pci_register_driver(&hns3_driver); 5709 if (ret) 5710 goto err_reg_driver; 5711 5712 return ret; 5713 5714 err_reg_driver: 5715 hnae3_unregister_client(&client); 5716 err_reg_client: 5717 hns3_dbg_unregister_debugfs(); 5718 return ret; 5719 } 5720 module_init(hns3_init_module); 5721 5722 /* hns3_exit_module - Driver exit cleanup routine 5723 * hns3_exit_module is called just before the driver is removed 5724 * from memory. 5725 */ 5726 static void __exit hns3_exit_module(void) 5727 { 5728 pci_unregister_driver(&hns3_driver); 5729 hnae3_unregister_client(&client); 5730 hns3_dbg_unregister_debugfs(); 5731 } 5732 module_exit(hns3_exit_module); 5733 5734 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 5735 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 5736 MODULE_LICENSE("GPL"); 5737 MODULE_ALIAS("pci:hns-nic"); 5738