1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #include <linux/if_vlan.h> 8 #include <linux/ip.h> 9 #include <linux/ipv6.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/skbuff.h> 13 #include <linux/sctp.h> 14 #include <linux/vermagic.h> 15 #include <net/gre.h> 16 #include <net/pkt_cls.h> 17 #include <net/vxlan.h> 18 19 #include "hnae3.h" 20 #include "hns3_enet.h" 21 22 static void hns3_clear_all_ring(struct hnae3_handle *h); 23 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h); 24 25 static const char hns3_driver_name[] = "hns3"; 26 const char hns3_driver_version[] = VERMAGIC_STRING; 27 static const char hns3_driver_string[] = 28 "Hisilicon Ethernet Network Driver for Hip08 Family"; 29 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 30 static struct hnae3_client client; 31 32 /* hns3_pci_tbl - PCI Device ID Table 33 * 34 * Last entry must be all 0s 35 * 36 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 37 * Class, Class Mask, private data (not used) } 38 */ 39 static const struct pci_device_id hns3_pci_tbl[] = { 40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 43 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 45 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 47 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 49 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 51 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 52 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 54 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 55 /* required last entry */ 56 {0, } 57 }; 58 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 59 60 static irqreturn_t hns3_irq_handle(int irq, void *vector) 61 { 62 struct hns3_enet_tqp_vector *tqp_vector = vector; 63 64 napi_schedule(&tqp_vector->napi); 65 66 return IRQ_HANDLED; 67 } 68 69 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 70 { 71 struct hns3_enet_tqp_vector *tqp_vectors; 72 unsigned int i; 73 74 for (i = 0; i < priv->vector_num; i++) { 75 tqp_vectors = &priv->tqp_vector[i]; 76 77 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 78 continue; 79 80 /* release the irq resource */ 81 free_irq(tqp_vectors->vector_irq, tqp_vectors); 82 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 83 } 84 } 85 86 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 87 { 88 struct hns3_enet_tqp_vector *tqp_vectors; 89 int txrx_int_idx = 0; 90 int rx_int_idx = 0; 91 int tx_int_idx = 0; 92 unsigned int i; 93 int ret; 94 95 for (i = 0; i < priv->vector_num; i++) { 96 tqp_vectors = &priv->tqp_vector[i]; 97 98 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 99 continue; 100 101 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 102 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 103 "%s-%s-%d", priv->netdev->name, "TxRx", 104 txrx_int_idx++); 105 txrx_int_idx++; 106 } else if (tqp_vectors->rx_group.ring) { 107 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 108 "%s-%s-%d", priv->netdev->name, "Rx", 109 rx_int_idx++); 110 } else if (tqp_vectors->tx_group.ring) { 111 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 112 "%s-%s-%d", priv->netdev->name, "Tx", 113 tx_int_idx++); 114 } else { 115 /* Skip this unused q_vector */ 116 continue; 117 } 118 119 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 120 121 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 122 tqp_vectors->name, 123 tqp_vectors); 124 if (ret) { 125 netdev_err(priv->netdev, "request irq(%d) fail\n", 126 tqp_vectors->vector_irq); 127 return ret; 128 } 129 130 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 131 } 132 133 return 0; 134 } 135 136 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 137 u32 mask_en) 138 { 139 writel(mask_en, tqp_vector->mask_addr); 140 } 141 142 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 143 { 144 napi_enable(&tqp_vector->napi); 145 146 /* enable vector */ 147 hns3_mask_vector_irq(tqp_vector, 1); 148 } 149 150 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 151 { 152 /* disable vector */ 153 hns3_mask_vector_irq(tqp_vector, 0); 154 155 disable_irq(tqp_vector->vector_irq); 156 napi_disable(&tqp_vector->napi); 157 } 158 159 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 160 u32 rl_value) 161 { 162 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 163 164 /* this defines the configuration for RL (Interrupt Rate Limiter). 165 * Rl defines rate of interrupts i.e. number of interrupts-per-second 166 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 167 */ 168 169 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable && 170 !tqp_vector->rx_group.coal.gl_adapt_enable) 171 /* According to the hardware, the range of rl_reg is 172 * 0-59 and the unit is 4. 173 */ 174 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 175 176 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 177 } 178 179 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 180 u32 gl_value) 181 { 182 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value); 183 184 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 185 } 186 187 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 188 u32 gl_value) 189 { 190 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value); 191 192 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 193 } 194 195 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector, 196 struct hns3_nic_priv *priv) 197 { 198 struct hnae3_handle *h = priv->ae_handle; 199 200 /* initialize the configuration for interrupt coalescing. 201 * 1. GL (Interrupt Gap Limiter) 202 * 2. RL (Interrupt Rate Limiter) 203 */ 204 205 /* Default: enable interrupt coalescing self-adaptive and GL */ 206 tqp_vector->tx_group.coal.gl_adapt_enable = 1; 207 tqp_vector->rx_group.coal.gl_adapt_enable = 1; 208 209 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K; 210 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K; 211 212 /* Default: disable RL */ 213 h->kinfo.int_rl_setting = 0; 214 215 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START; 216 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW; 217 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW; 218 } 219 220 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 221 struct hns3_nic_priv *priv) 222 { 223 struct hnae3_handle *h = priv->ae_handle; 224 225 hns3_set_vector_coalesce_tx_gl(tqp_vector, 226 tqp_vector->tx_group.coal.int_gl); 227 hns3_set_vector_coalesce_rx_gl(tqp_vector, 228 tqp_vector->rx_group.coal.int_gl); 229 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 230 } 231 232 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 233 { 234 struct hnae3_handle *h = hns3_get_handle(netdev); 235 struct hnae3_knic_private_info *kinfo = &h->kinfo; 236 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc; 237 int i, ret; 238 239 if (kinfo->num_tc <= 1) { 240 netdev_reset_tc(netdev); 241 } else { 242 ret = netdev_set_num_tc(netdev, kinfo->num_tc); 243 if (ret) { 244 netdev_err(netdev, 245 "netdev_set_num_tc fail, ret=%d!\n", ret); 246 return ret; 247 } 248 249 for (i = 0; i < HNAE3_MAX_TC; i++) { 250 if (!kinfo->tc_info[i].enable) 251 continue; 252 253 netdev_set_tc_queue(netdev, 254 kinfo->tc_info[i].tc, 255 kinfo->tc_info[i].tqp_count, 256 kinfo->tc_info[i].tqp_offset); 257 } 258 } 259 260 ret = netif_set_real_num_tx_queues(netdev, queue_size); 261 if (ret) { 262 netdev_err(netdev, 263 "netif_set_real_num_tx_queues fail, ret=%d!\n", 264 ret); 265 return ret; 266 } 267 268 ret = netif_set_real_num_rx_queues(netdev, queue_size); 269 if (ret) { 270 netdev_err(netdev, 271 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 272 return ret; 273 } 274 275 return 0; 276 } 277 278 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 279 { 280 u16 free_tqps, max_rss_size, max_tqps; 281 282 h->ae_algo->ops->get_tqps_and_rss_info(h, &free_tqps, &max_rss_size); 283 max_tqps = h->kinfo.num_tc * max_rss_size; 284 285 return min_t(u16, max_tqps, (free_tqps + h->kinfo.num_tqps)); 286 } 287 288 static int hns3_nic_net_up(struct net_device *netdev) 289 { 290 struct hns3_nic_priv *priv = netdev_priv(netdev); 291 struct hnae3_handle *h = priv->ae_handle; 292 int i, j; 293 int ret; 294 295 ret = hns3_nic_reset_all_ring(h); 296 if (ret) 297 return ret; 298 299 /* get irq resource for all vectors */ 300 ret = hns3_nic_init_irq(priv); 301 if (ret) { 302 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret); 303 return ret; 304 } 305 306 /* enable the vectors */ 307 for (i = 0; i < priv->vector_num; i++) 308 hns3_vector_enable(&priv->tqp_vector[i]); 309 310 /* start the ae_dev */ 311 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 312 if (ret) 313 goto out_start_err; 314 315 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 316 317 return 0; 318 319 out_start_err: 320 for (j = i - 1; j >= 0; j--) 321 hns3_vector_disable(&priv->tqp_vector[j]); 322 323 hns3_nic_uninit_irq(priv); 324 325 return ret; 326 } 327 328 static int hns3_nic_net_open(struct net_device *netdev) 329 { 330 struct hns3_nic_priv *priv = netdev_priv(netdev); 331 struct hnae3_handle *h = hns3_get_handle(netdev); 332 struct hnae3_knic_private_info *kinfo; 333 int i, ret; 334 335 netif_carrier_off(netdev); 336 337 ret = hns3_nic_set_real_num_queue(netdev); 338 if (ret) 339 return ret; 340 341 ret = hns3_nic_net_up(netdev); 342 if (ret) { 343 netdev_err(netdev, 344 "hns net up fail, ret=%d!\n", ret); 345 return ret; 346 } 347 348 kinfo = &h->kinfo; 349 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { 350 netdev_set_prio_tc_map(netdev, i, 351 kinfo->prio_tc[i]); 352 } 353 354 priv->ae_handle->last_reset_time = jiffies; 355 return 0; 356 } 357 358 static void hns3_nic_net_down(struct net_device *netdev) 359 { 360 struct hns3_nic_priv *priv = netdev_priv(netdev); 361 const struct hnae3_ae_ops *ops; 362 int i; 363 364 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 365 return; 366 367 /* disable vectors */ 368 for (i = 0; i < priv->vector_num; i++) 369 hns3_vector_disable(&priv->tqp_vector[i]); 370 371 /* stop ae_dev */ 372 ops = priv->ae_handle->ae_algo->ops; 373 if (ops->stop) 374 ops->stop(priv->ae_handle); 375 376 /* free irq resources */ 377 hns3_nic_uninit_irq(priv); 378 379 hns3_clear_all_ring(priv->ae_handle); 380 } 381 382 static int hns3_nic_net_stop(struct net_device *netdev) 383 { 384 netif_tx_stop_all_queues(netdev); 385 netif_carrier_off(netdev); 386 387 hns3_nic_net_down(netdev); 388 389 return 0; 390 } 391 392 static int hns3_nic_uc_sync(struct net_device *netdev, 393 const unsigned char *addr) 394 { 395 struct hnae3_handle *h = hns3_get_handle(netdev); 396 397 if (h->ae_algo->ops->add_uc_addr) 398 return h->ae_algo->ops->add_uc_addr(h, addr); 399 400 return 0; 401 } 402 403 static int hns3_nic_uc_unsync(struct net_device *netdev, 404 const unsigned char *addr) 405 { 406 struct hnae3_handle *h = hns3_get_handle(netdev); 407 408 if (h->ae_algo->ops->rm_uc_addr) 409 return h->ae_algo->ops->rm_uc_addr(h, addr); 410 411 return 0; 412 } 413 414 static int hns3_nic_mc_sync(struct net_device *netdev, 415 const unsigned char *addr) 416 { 417 struct hnae3_handle *h = hns3_get_handle(netdev); 418 419 if (h->ae_algo->ops->add_mc_addr) 420 return h->ae_algo->ops->add_mc_addr(h, addr); 421 422 return 0; 423 } 424 425 static int hns3_nic_mc_unsync(struct net_device *netdev, 426 const unsigned char *addr) 427 { 428 struct hnae3_handle *h = hns3_get_handle(netdev); 429 430 if (h->ae_algo->ops->rm_mc_addr) 431 return h->ae_algo->ops->rm_mc_addr(h, addr); 432 433 return 0; 434 } 435 436 static void hns3_nic_set_rx_mode(struct net_device *netdev) 437 { 438 struct hnae3_handle *h = hns3_get_handle(netdev); 439 440 if (h->ae_algo->ops->set_promisc_mode) { 441 if (netdev->flags & IFF_PROMISC) 442 h->ae_algo->ops->set_promisc_mode(h, true, true); 443 else if (netdev->flags & IFF_ALLMULTI) 444 h->ae_algo->ops->set_promisc_mode(h, false, true); 445 else 446 h->ae_algo->ops->set_promisc_mode(h, false, false); 447 } 448 if (__dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync)) 449 netdev_err(netdev, "sync uc address fail\n"); 450 if (netdev->flags & IFF_MULTICAST) { 451 if (__dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync)) 452 netdev_err(netdev, "sync mc address fail\n"); 453 454 if (h->ae_algo->ops->update_mta_status) 455 h->ae_algo->ops->update_mta_status(h); 456 } 457 } 458 459 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen, 460 u16 *mss, u32 *type_cs_vlan_tso) 461 { 462 u32 l4_offset, hdr_len; 463 union l3_hdr_info l3; 464 union l4_hdr_info l4; 465 u32 l4_paylen; 466 int ret; 467 468 if (!skb_is_gso(skb)) 469 return 0; 470 471 ret = skb_cow_head(skb, 0); 472 if (ret) 473 return ret; 474 475 l3.hdr = skb_network_header(skb); 476 l4.hdr = skb_transport_header(skb); 477 478 /* Software should clear the IPv4's checksum field when tso is 479 * needed. 480 */ 481 if (l3.v4->version == 4) 482 l3.v4->check = 0; 483 484 /* tunnel packet.*/ 485 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 486 SKB_GSO_GRE_CSUM | 487 SKB_GSO_UDP_TUNNEL | 488 SKB_GSO_UDP_TUNNEL_CSUM)) { 489 if ((!(skb_shinfo(skb)->gso_type & 490 SKB_GSO_PARTIAL)) && 491 (skb_shinfo(skb)->gso_type & 492 SKB_GSO_UDP_TUNNEL_CSUM)) { 493 /* Software should clear the udp's checksum 494 * field when tso is needed. 495 */ 496 l4.udp->check = 0; 497 } 498 /* reset l3&l4 pointers from outer to inner headers */ 499 l3.hdr = skb_inner_network_header(skb); 500 l4.hdr = skb_inner_transport_header(skb); 501 502 /* Software should clear the IPv4's checksum field when 503 * tso is needed. 504 */ 505 if (l3.v4->version == 4) 506 l3.v4->check = 0; 507 } 508 509 /* normal or tunnel packet*/ 510 l4_offset = l4.hdr - skb->data; 511 hdr_len = (l4.tcp->doff * 4) + l4_offset; 512 513 /* remove payload length from inner pseudo checksum when tso*/ 514 l4_paylen = skb->len - l4_offset; 515 csum_replace_by_diff(&l4.tcp->check, 516 (__force __wsum)htonl(l4_paylen)); 517 518 /* find the txbd field values */ 519 *paylen = skb->len - hdr_len; 520 hnae3_set_bit(*type_cs_vlan_tso, 521 HNS3_TXD_TSO_B, 1); 522 523 /* get MSS for TSO */ 524 *mss = skb_shinfo(skb)->gso_size; 525 526 return 0; 527 } 528 529 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 530 u8 *il4_proto) 531 { 532 union { 533 struct iphdr *v4; 534 struct ipv6hdr *v6; 535 unsigned char *hdr; 536 } l3; 537 unsigned char *l4_hdr; 538 unsigned char *exthdr; 539 u8 l4_proto_tmp; 540 __be16 frag_off; 541 542 /* find outer header point */ 543 l3.hdr = skb_network_header(skb); 544 l4_hdr = skb_transport_header(skb); 545 546 if (skb->protocol == htons(ETH_P_IPV6)) { 547 exthdr = l3.hdr + sizeof(*l3.v6); 548 l4_proto_tmp = l3.v6->nexthdr; 549 if (l4_hdr != exthdr) 550 ipv6_skip_exthdr(skb, exthdr - skb->data, 551 &l4_proto_tmp, &frag_off); 552 } else if (skb->protocol == htons(ETH_P_IP)) { 553 l4_proto_tmp = l3.v4->protocol; 554 } else { 555 return -EINVAL; 556 } 557 558 *ol4_proto = l4_proto_tmp; 559 560 /* tunnel packet */ 561 if (!skb->encapsulation) { 562 *il4_proto = 0; 563 return 0; 564 } 565 566 /* find inner header point */ 567 l3.hdr = skb_inner_network_header(skb); 568 l4_hdr = skb_inner_transport_header(skb); 569 570 if (l3.v6->version == 6) { 571 exthdr = l3.hdr + sizeof(*l3.v6); 572 l4_proto_tmp = l3.v6->nexthdr; 573 if (l4_hdr != exthdr) 574 ipv6_skip_exthdr(skb, exthdr - skb->data, 575 &l4_proto_tmp, &frag_off); 576 } else if (l3.v4->version == 4) { 577 l4_proto_tmp = l3.v4->protocol; 578 } 579 580 *il4_proto = l4_proto_tmp; 581 582 return 0; 583 } 584 585 static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto, 586 u8 il4_proto, u32 *type_cs_vlan_tso, 587 u32 *ol_type_vlan_len_msec) 588 { 589 union { 590 struct iphdr *v4; 591 struct ipv6hdr *v6; 592 unsigned char *hdr; 593 } l3; 594 union { 595 struct tcphdr *tcp; 596 struct udphdr *udp; 597 struct gre_base_hdr *gre; 598 unsigned char *hdr; 599 } l4; 600 unsigned char *l2_hdr; 601 u8 l4_proto = ol4_proto; 602 u32 ol2_len; 603 u32 ol3_len; 604 u32 ol4_len; 605 u32 l2_len; 606 u32 l3_len; 607 608 l3.hdr = skb_network_header(skb); 609 l4.hdr = skb_transport_header(skb); 610 611 /* compute L2 header size for normal packet, defined in 2 Bytes */ 612 l2_len = l3.hdr - skb->data; 613 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M, 614 HNS3_TXD_L2LEN_S, l2_len >> 1); 615 616 /* tunnel packet*/ 617 if (skb->encapsulation) { 618 /* compute OL2 header size, defined in 2 Bytes */ 619 ol2_len = l2_len; 620 hnae3_set_field(*ol_type_vlan_len_msec, 621 HNS3_TXD_L2LEN_M, 622 HNS3_TXD_L2LEN_S, ol2_len >> 1); 623 624 /* compute OL3 header size, defined in 4 Bytes */ 625 ol3_len = l4.hdr - l3.hdr; 626 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M, 627 HNS3_TXD_L3LEN_S, ol3_len >> 2); 628 629 /* MAC in UDP, MAC in GRE (0x6558)*/ 630 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) { 631 /* switch MAC header ptr from outer to inner header.*/ 632 l2_hdr = skb_inner_mac_header(skb); 633 634 /* compute OL4 header size, defined in 4 Bytes. */ 635 ol4_len = l2_hdr - l4.hdr; 636 hnae3_set_field(*ol_type_vlan_len_msec, 637 HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S, 638 ol4_len >> 2); 639 640 /* switch IP header ptr from outer to inner header */ 641 l3.hdr = skb_inner_network_header(skb); 642 643 /* compute inner l2 header size, defined in 2 Bytes. */ 644 l2_len = l3.hdr - l2_hdr; 645 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M, 646 HNS3_TXD_L2LEN_S, l2_len >> 1); 647 } else { 648 /* skb packet types not supported by hardware, 649 * txbd len fild doesn't be filled. 650 */ 651 return; 652 } 653 654 /* switch L4 header pointer from outer to inner */ 655 l4.hdr = skb_inner_transport_header(skb); 656 657 l4_proto = il4_proto; 658 } 659 660 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 661 l3_len = l4.hdr - l3.hdr; 662 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M, 663 HNS3_TXD_L3LEN_S, l3_len >> 2); 664 665 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 666 switch (l4_proto) { 667 case IPPROTO_TCP: 668 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 669 HNS3_TXD_L4LEN_S, l4.tcp->doff); 670 break; 671 case IPPROTO_SCTP: 672 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 673 HNS3_TXD_L4LEN_S, 674 (sizeof(struct sctphdr) >> 2)); 675 break; 676 case IPPROTO_UDP: 677 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 678 HNS3_TXD_L4LEN_S, 679 (sizeof(struct udphdr) >> 2)); 680 break; 681 default: 682 /* skb packet types not supported by hardware, 683 * txbd len fild doesn't be filled. 684 */ 685 return; 686 } 687 } 688 689 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 690 * and it is udp packet, which has a dest port as the IANA assigned. 691 * the hardware is expected to do the checksum offload, but the 692 * hardware will not do the checksum offload when udp dest port is 693 * 4789. 694 */ 695 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 696 { 697 #define IANA_VXLAN_PORT 4789 698 union { 699 struct tcphdr *tcp; 700 struct udphdr *udp; 701 struct gre_base_hdr *gre; 702 unsigned char *hdr; 703 } l4; 704 705 l4.hdr = skb_transport_header(skb); 706 707 if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT))) 708 return false; 709 710 skb_checksum_help(skb); 711 712 return true; 713 } 714 715 static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto, 716 u8 il4_proto, u32 *type_cs_vlan_tso, 717 u32 *ol_type_vlan_len_msec) 718 { 719 union { 720 struct iphdr *v4; 721 struct ipv6hdr *v6; 722 unsigned char *hdr; 723 } l3; 724 u32 l4_proto = ol4_proto; 725 726 l3.hdr = skb_network_header(skb); 727 728 /* define OL3 type and tunnel type(OL4).*/ 729 if (skb->encapsulation) { 730 /* define outer network header type.*/ 731 if (skb->protocol == htons(ETH_P_IP)) { 732 if (skb_is_gso(skb)) 733 hnae3_set_field(*ol_type_vlan_len_msec, 734 HNS3_TXD_OL3T_M, 735 HNS3_TXD_OL3T_S, 736 HNS3_OL3T_IPV4_CSUM); 737 else 738 hnae3_set_field(*ol_type_vlan_len_msec, 739 HNS3_TXD_OL3T_M, 740 HNS3_TXD_OL3T_S, 741 HNS3_OL3T_IPV4_NO_CSUM); 742 743 } else if (skb->protocol == htons(ETH_P_IPV6)) { 744 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M, 745 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6); 746 } 747 748 /* define tunnel type(OL4).*/ 749 switch (l4_proto) { 750 case IPPROTO_UDP: 751 hnae3_set_field(*ol_type_vlan_len_msec, 752 HNS3_TXD_TUNTYPE_M, 753 HNS3_TXD_TUNTYPE_S, 754 HNS3_TUN_MAC_IN_UDP); 755 break; 756 case IPPROTO_GRE: 757 hnae3_set_field(*ol_type_vlan_len_msec, 758 HNS3_TXD_TUNTYPE_M, 759 HNS3_TXD_TUNTYPE_S, 760 HNS3_TUN_NVGRE); 761 break; 762 default: 763 /* drop the skb tunnel packet if hardware don't support, 764 * because hardware can't calculate csum when TSO. 765 */ 766 if (skb_is_gso(skb)) 767 return -EDOM; 768 769 /* the stack computes the IP header already, 770 * driver calculate l4 checksum when not TSO. 771 */ 772 skb_checksum_help(skb); 773 return 0; 774 } 775 776 l3.hdr = skb_inner_network_header(skb); 777 l4_proto = il4_proto; 778 } 779 780 if (l3.v4->version == 4) { 781 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M, 782 HNS3_TXD_L3T_S, HNS3_L3T_IPV4); 783 784 /* the stack computes the IP header already, the only time we 785 * need the hardware to recompute it is in the case of TSO. 786 */ 787 if (skb_is_gso(skb)) 788 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 789 } else if (l3.v6->version == 6) { 790 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M, 791 HNS3_TXD_L3T_S, HNS3_L3T_IPV6); 792 } 793 794 switch (l4_proto) { 795 case IPPROTO_TCP: 796 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 797 hnae3_set_field(*type_cs_vlan_tso, 798 HNS3_TXD_L4T_M, 799 HNS3_TXD_L4T_S, 800 HNS3_L4T_TCP); 801 break; 802 case IPPROTO_UDP: 803 if (hns3_tunnel_csum_bug(skb)) 804 break; 805 806 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 807 hnae3_set_field(*type_cs_vlan_tso, 808 HNS3_TXD_L4T_M, 809 HNS3_TXD_L4T_S, 810 HNS3_L4T_UDP); 811 break; 812 case IPPROTO_SCTP: 813 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 814 hnae3_set_field(*type_cs_vlan_tso, 815 HNS3_TXD_L4T_M, 816 HNS3_TXD_L4T_S, 817 HNS3_L4T_SCTP); 818 break; 819 default: 820 /* drop the skb tunnel packet if hardware don't support, 821 * because hardware can't calculate csum when TSO. 822 */ 823 if (skb_is_gso(skb)) 824 return -EDOM; 825 826 /* the stack computes the IP header already, 827 * driver calculate l4 checksum when not TSO. 828 */ 829 skb_checksum_help(skb); 830 return 0; 831 } 832 833 return 0; 834 } 835 836 static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end) 837 { 838 /* Config bd buffer end */ 839 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M, 840 HNS3_TXD_BDTYPE_S, 0); 841 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end); 842 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1); 843 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0); 844 } 845 846 static int hns3_fill_desc_vtags(struct sk_buff *skb, 847 struct hns3_enet_ring *tx_ring, 848 u32 *inner_vlan_flag, 849 u32 *out_vlan_flag, 850 u16 *inner_vtag, 851 u16 *out_vtag) 852 { 853 #define HNS3_TX_VLAN_PRIO_SHIFT 13 854 855 if (skb->protocol == htons(ETH_P_8021Q) && 856 !(tx_ring->tqp->handle->kinfo.netdev->features & 857 NETIF_F_HW_VLAN_CTAG_TX)) { 858 /* When HW VLAN acceleration is turned off, and the stack 859 * sets the protocol to 802.1q, the driver just need to 860 * set the protocol to the encapsulated ethertype. 861 */ 862 skb->protocol = vlan_get_protocol(skb); 863 return 0; 864 } 865 866 if (skb_vlan_tag_present(skb)) { 867 u16 vlan_tag; 868 869 vlan_tag = skb_vlan_tag_get(skb); 870 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT; 871 872 /* Based on hw strategy, use out_vtag in two layer tag case, 873 * and use inner_vtag in one tag case. 874 */ 875 if (skb->protocol == htons(ETH_P_8021Q)) { 876 hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1); 877 *out_vtag = vlan_tag; 878 } else { 879 hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1); 880 *inner_vtag = vlan_tag; 881 } 882 } else if (skb->protocol == htons(ETH_P_8021Q)) { 883 struct vlan_ethhdr *vhdr; 884 int rc; 885 886 rc = skb_cow_head(skb, 0); 887 if (rc < 0) 888 return rc; 889 vhdr = (struct vlan_ethhdr *)skb->data; 890 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7) 891 << HNS3_TX_VLAN_PRIO_SHIFT); 892 } 893 894 skb->protocol = vlan_get_protocol(skb); 895 return 0; 896 } 897 898 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 899 int size, dma_addr_t dma, int frag_end, 900 enum hns_desc_type type) 901 { 902 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 903 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 904 u32 ol_type_vlan_len_msec = 0; 905 u16 bdtp_fe_sc_vld_ra_ri = 0; 906 u32 type_cs_vlan_tso = 0; 907 struct sk_buff *skb; 908 u16 inner_vtag = 0; 909 u16 out_vtag = 0; 910 u32 paylen = 0; 911 u16 mss = 0; 912 u8 ol4_proto; 913 u8 il4_proto; 914 int ret; 915 916 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */ 917 desc_cb->priv = priv; 918 desc_cb->length = size; 919 desc_cb->dma = dma; 920 desc_cb->type = type; 921 922 /* now, fill the descriptor */ 923 desc->addr = cpu_to_le64(dma); 924 desc->tx.send_size = cpu_to_le16((u16)size); 925 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, frag_end); 926 desc->tx.bdtp_fe_sc_vld_ra_ri = cpu_to_le16(bdtp_fe_sc_vld_ra_ri); 927 928 if (type == DESC_TYPE_SKB) { 929 skb = (struct sk_buff *)priv; 930 paylen = skb->len; 931 932 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso, 933 &ol_type_vlan_len_msec, 934 &inner_vtag, &out_vtag); 935 if (unlikely(ret)) 936 return ret; 937 938 if (skb->ip_summed == CHECKSUM_PARTIAL) { 939 skb_reset_mac_len(skb); 940 941 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 942 if (ret) 943 return ret; 944 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto, 945 &type_cs_vlan_tso, 946 &ol_type_vlan_len_msec); 947 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto, 948 &type_cs_vlan_tso, 949 &ol_type_vlan_len_msec); 950 if (ret) 951 return ret; 952 953 ret = hns3_set_tso(skb, &paylen, &mss, 954 &type_cs_vlan_tso); 955 if (ret) 956 return ret; 957 } 958 959 /* Set txbd */ 960 desc->tx.ol_type_vlan_len_msec = 961 cpu_to_le32(ol_type_vlan_len_msec); 962 desc->tx.type_cs_vlan_tso_len = 963 cpu_to_le32(type_cs_vlan_tso); 964 desc->tx.paylen = cpu_to_le32(paylen); 965 desc->tx.mss = cpu_to_le16(mss); 966 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 967 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 968 } 969 970 /* move ring pointer to next.*/ 971 ring_ptr_move_fw(ring, next_to_use); 972 973 return 0; 974 } 975 976 static int hns3_fill_desc_tso(struct hns3_enet_ring *ring, void *priv, 977 int size, dma_addr_t dma, int frag_end, 978 enum hns_desc_type type) 979 { 980 unsigned int frag_buf_num; 981 unsigned int k; 982 int sizeoflast; 983 int ret; 984 985 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 986 sizeoflast = size % HNS3_MAX_BD_SIZE; 987 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 988 989 /* When the frag size is bigger than hardware, split this frag */ 990 for (k = 0; k < frag_buf_num; k++) { 991 ret = hns3_fill_desc(ring, priv, 992 (k == frag_buf_num - 1) ? 993 sizeoflast : HNS3_MAX_BD_SIZE, 994 dma + HNS3_MAX_BD_SIZE * k, 995 frag_end && (k == frag_buf_num - 1) ? 1 : 0, 996 (type == DESC_TYPE_SKB && !k) ? 997 DESC_TYPE_SKB : DESC_TYPE_PAGE); 998 if (ret) 999 return ret; 1000 } 1001 1002 return 0; 1003 } 1004 1005 static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum, 1006 struct hns3_enet_ring *ring) 1007 { 1008 struct sk_buff *skb = *out_skb; 1009 struct skb_frag_struct *frag; 1010 int bdnum_for_frag; 1011 int frag_num; 1012 int buf_num; 1013 int size; 1014 int i; 1015 1016 size = skb_headlen(skb); 1017 buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1018 1019 frag_num = skb_shinfo(skb)->nr_frags; 1020 for (i = 0; i < frag_num; i++) { 1021 frag = &skb_shinfo(skb)->frags[i]; 1022 size = skb_frag_size(frag); 1023 bdnum_for_frag = 1024 (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1025 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG) 1026 return -ENOMEM; 1027 1028 buf_num += bdnum_for_frag; 1029 } 1030 1031 if (buf_num > ring_space(ring)) 1032 return -EBUSY; 1033 1034 *bnum = buf_num; 1035 return 0; 1036 } 1037 1038 static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum, 1039 struct hns3_enet_ring *ring) 1040 { 1041 struct sk_buff *skb = *out_skb; 1042 int buf_num; 1043 1044 /* No. of segments (plus a header) */ 1045 buf_num = skb_shinfo(skb)->nr_frags + 1; 1046 1047 if (buf_num > ring_space(ring)) 1048 return -EBUSY; 1049 1050 *bnum = buf_num; 1051 1052 return 0; 1053 } 1054 1055 static void hns_nic_dma_unmap(struct hns3_enet_ring *ring, int next_to_use_orig) 1056 { 1057 struct device *dev = ring_to_dev(ring); 1058 unsigned int i; 1059 1060 for (i = 0; i < ring->desc_num; i++) { 1061 /* check if this is where we started */ 1062 if (ring->next_to_use == next_to_use_orig) 1063 break; 1064 1065 /* unmap the descriptor dma address */ 1066 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB) 1067 dma_unmap_single(dev, 1068 ring->desc_cb[ring->next_to_use].dma, 1069 ring->desc_cb[ring->next_to_use].length, 1070 DMA_TO_DEVICE); 1071 else 1072 dma_unmap_page(dev, 1073 ring->desc_cb[ring->next_to_use].dma, 1074 ring->desc_cb[ring->next_to_use].length, 1075 DMA_TO_DEVICE); 1076 1077 /* rollback one */ 1078 ring_ptr_move_bw(ring, next_to_use); 1079 } 1080 } 1081 1082 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1083 { 1084 struct hns3_nic_priv *priv = netdev_priv(netdev); 1085 struct hns3_nic_ring_data *ring_data = 1086 &tx_ring_data(priv, skb->queue_mapping); 1087 struct hns3_enet_ring *ring = ring_data->ring; 1088 struct device *dev = priv->dev; 1089 struct netdev_queue *dev_queue; 1090 struct skb_frag_struct *frag; 1091 int next_to_use_head; 1092 int next_to_use_frag; 1093 dma_addr_t dma; 1094 int buf_num; 1095 int seg_num; 1096 int size; 1097 int ret; 1098 int i; 1099 1100 /* Prefetch the data used later */ 1101 prefetch(skb->data); 1102 1103 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) { 1104 case -EBUSY: 1105 u64_stats_update_begin(&ring->syncp); 1106 ring->stats.tx_busy++; 1107 u64_stats_update_end(&ring->syncp); 1108 1109 goto out_net_tx_busy; 1110 case -ENOMEM: 1111 u64_stats_update_begin(&ring->syncp); 1112 ring->stats.sw_err_cnt++; 1113 u64_stats_update_end(&ring->syncp); 1114 netdev_err(netdev, "no memory to xmit!\n"); 1115 1116 goto out_err_tx_ok; 1117 default: 1118 break; 1119 } 1120 1121 /* No. of segments (plus a header) */ 1122 seg_num = skb_shinfo(skb)->nr_frags + 1; 1123 /* Fill the first part */ 1124 size = skb_headlen(skb); 1125 1126 next_to_use_head = ring->next_to_use; 1127 1128 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1129 if (dma_mapping_error(dev, dma)) { 1130 netdev_err(netdev, "TX head DMA map failed\n"); 1131 ring->stats.sw_err_cnt++; 1132 goto out_err_tx_ok; 1133 } 1134 1135 ret = priv->ops.fill_desc(ring, skb, size, dma, seg_num == 1 ? 1 : 0, 1136 DESC_TYPE_SKB); 1137 if (ret) 1138 goto head_dma_map_err; 1139 1140 next_to_use_frag = ring->next_to_use; 1141 /* Fill the fragments */ 1142 for (i = 1; i < seg_num; i++) { 1143 frag = &skb_shinfo(skb)->frags[i - 1]; 1144 size = skb_frag_size(frag); 1145 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1146 if (dma_mapping_error(dev, dma)) { 1147 netdev_err(netdev, "TX frag(%d) DMA map failed\n", i); 1148 ring->stats.sw_err_cnt++; 1149 goto frag_dma_map_err; 1150 } 1151 ret = priv->ops.fill_desc(ring, skb_frag_page(frag), size, dma, 1152 seg_num - 1 == i ? 1 : 0, 1153 DESC_TYPE_PAGE); 1154 1155 if (ret) 1156 goto frag_dma_map_err; 1157 } 1158 1159 /* Complete translate all packets */ 1160 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index); 1161 netdev_tx_sent_queue(dev_queue, skb->len); 1162 1163 wmb(); /* Commit all data before submit */ 1164 1165 hnae3_queue_xmit(ring->tqp, buf_num); 1166 1167 return NETDEV_TX_OK; 1168 1169 frag_dma_map_err: 1170 hns_nic_dma_unmap(ring, next_to_use_frag); 1171 1172 head_dma_map_err: 1173 hns_nic_dma_unmap(ring, next_to_use_head); 1174 1175 out_err_tx_ok: 1176 dev_kfree_skb_any(skb); 1177 return NETDEV_TX_OK; 1178 1179 out_net_tx_busy: 1180 netif_stop_subqueue(netdev, ring_data->queue_index); 1181 smp_mb(); /* Commit all data before submit */ 1182 1183 return NETDEV_TX_BUSY; 1184 } 1185 1186 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1187 { 1188 struct hnae3_handle *h = hns3_get_handle(netdev); 1189 struct sockaddr *mac_addr = p; 1190 int ret; 1191 1192 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1193 return -EADDRNOTAVAIL; 1194 1195 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1196 netdev_info(netdev, "already using mac address %pM\n", 1197 mac_addr->sa_data); 1198 return 0; 1199 } 1200 1201 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1202 if (ret) { 1203 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1204 return ret; 1205 } 1206 1207 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1208 1209 return 0; 1210 } 1211 1212 static int hns3_nic_set_features(struct net_device *netdev, 1213 netdev_features_t features) 1214 { 1215 netdev_features_t changed = netdev->features ^ features; 1216 struct hns3_nic_priv *priv = netdev_priv(netdev); 1217 struct hnae3_handle *h = priv->ae_handle; 1218 int ret; 1219 1220 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) { 1221 if (features & (NETIF_F_TSO | NETIF_F_TSO6)) { 1222 priv->ops.fill_desc = hns3_fill_desc_tso; 1223 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 1224 } else { 1225 priv->ops.fill_desc = hns3_fill_desc; 1226 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 1227 } 1228 } 1229 1230 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 1231 h->ae_algo->ops->enable_vlan_filter) { 1232 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1233 h->ae_algo->ops->enable_vlan_filter(h, true); 1234 else 1235 h->ae_algo->ops->enable_vlan_filter(h, false); 1236 } 1237 1238 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1239 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1240 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1241 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true); 1242 else 1243 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false); 1244 1245 if (ret) 1246 return ret; 1247 } 1248 1249 netdev->features = features; 1250 return 0; 1251 } 1252 1253 static void hns3_nic_get_stats64(struct net_device *netdev, 1254 struct rtnl_link_stats64 *stats) 1255 { 1256 struct hns3_nic_priv *priv = netdev_priv(netdev); 1257 int queue_num = priv->ae_handle->kinfo.num_tqps; 1258 struct hnae3_handle *handle = priv->ae_handle; 1259 struct hns3_enet_ring *ring; 1260 unsigned int start; 1261 unsigned int idx; 1262 u64 tx_bytes = 0; 1263 u64 rx_bytes = 0; 1264 u64 tx_pkts = 0; 1265 u64 rx_pkts = 0; 1266 u64 tx_drop = 0; 1267 u64 rx_drop = 0; 1268 1269 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1270 return; 1271 1272 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1273 1274 for (idx = 0; idx < queue_num; idx++) { 1275 /* fetch the tx stats */ 1276 ring = priv->ring_data[idx].ring; 1277 do { 1278 start = u64_stats_fetch_begin_irq(&ring->syncp); 1279 tx_bytes += ring->stats.tx_bytes; 1280 tx_pkts += ring->stats.tx_pkts; 1281 tx_drop += ring->stats.tx_busy; 1282 tx_drop += ring->stats.sw_err_cnt; 1283 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1284 1285 /* fetch the rx stats */ 1286 ring = priv->ring_data[idx + queue_num].ring; 1287 do { 1288 start = u64_stats_fetch_begin_irq(&ring->syncp); 1289 rx_bytes += ring->stats.rx_bytes; 1290 rx_pkts += ring->stats.rx_pkts; 1291 rx_drop += ring->stats.non_vld_descs; 1292 rx_drop += ring->stats.err_pkt_len; 1293 rx_drop += ring->stats.l2_err; 1294 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1295 } 1296 1297 stats->tx_bytes = tx_bytes; 1298 stats->tx_packets = tx_pkts; 1299 stats->rx_bytes = rx_bytes; 1300 stats->rx_packets = rx_pkts; 1301 1302 stats->rx_errors = netdev->stats.rx_errors; 1303 stats->multicast = netdev->stats.multicast; 1304 stats->rx_length_errors = netdev->stats.rx_length_errors; 1305 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 1306 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1307 1308 stats->tx_errors = netdev->stats.tx_errors; 1309 stats->rx_dropped = rx_drop + netdev->stats.rx_dropped; 1310 stats->tx_dropped = tx_drop + netdev->stats.tx_dropped; 1311 stats->collisions = netdev->stats.collisions; 1312 stats->rx_over_errors = netdev->stats.rx_over_errors; 1313 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1314 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1315 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1316 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1317 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1318 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1319 stats->tx_window_errors = netdev->stats.tx_window_errors; 1320 stats->rx_compressed = netdev->stats.rx_compressed; 1321 stats->tx_compressed = netdev->stats.tx_compressed; 1322 } 1323 1324 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1325 { 1326 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1327 struct hnae3_handle *h = hns3_get_handle(netdev); 1328 struct hnae3_knic_private_info *kinfo = &h->kinfo; 1329 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map; 1330 u8 tc = mqprio_qopt->qopt.num_tc; 1331 u16 mode = mqprio_qopt->mode; 1332 u8 hw = mqprio_qopt->qopt.hw; 1333 bool if_running; 1334 int ret; 1335 1336 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1337 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1338 return -EOPNOTSUPP; 1339 1340 if (tc > HNAE3_MAX_TC) 1341 return -EINVAL; 1342 1343 if (!netdev) 1344 return -EINVAL; 1345 1346 if_running = netif_running(netdev); 1347 if (if_running) { 1348 hns3_nic_net_stop(netdev); 1349 msleep(100); 1350 } 1351 1352 ret = (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1353 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP; 1354 if (ret) 1355 goto out; 1356 1357 ret = hns3_nic_set_real_num_queue(netdev); 1358 1359 out: 1360 if (if_running) 1361 hns3_nic_net_open(netdev); 1362 1363 return ret; 1364 } 1365 1366 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1367 void *type_data) 1368 { 1369 if (type != TC_SETUP_QDISC_MQPRIO) 1370 return -EOPNOTSUPP; 1371 1372 return hns3_setup_tc(dev, type_data); 1373 } 1374 1375 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1376 __be16 proto, u16 vid) 1377 { 1378 struct hnae3_handle *h = hns3_get_handle(netdev); 1379 struct hns3_nic_priv *priv = netdev_priv(netdev); 1380 int ret = -EIO; 1381 1382 if (h->ae_algo->ops->set_vlan_filter) 1383 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1384 1385 if (!ret) 1386 set_bit(vid, priv->active_vlans); 1387 1388 return ret; 1389 } 1390 1391 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1392 __be16 proto, u16 vid) 1393 { 1394 struct hnae3_handle *h = hns3_get_handle(netdev); 1395 struct hns3_nic_priv *priv = netdev_priv(netdev); 1396 int ret = -EIO; 1397 1398 if (h->ae_algo->ops->set_vlan_filter) 1399 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1400 1401 if (!ret) 1402 clear_bit(vid, priv->active_vlans); 1403 1404 return ret; 1405 } 1406 1407 static void hns3_restore_vlan(struct net_device *netdev) 1408 { 1409 struct hns3_nic_priv *priv = netdev_priv(netdev); 1410 u16 vid; 1411 int ret; 1412 1413 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 1414 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 1415 if (ret) 1416 netdev_warn(netdev, "Restore vlan: %d filter, ret:%d\n", 1417 vid, ret); 1418 } 1419 } 1420 1421 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1422 u8 qos, __be16 vlan_proto) 1423 { 1424 struct hnae3_handle *h = hns3_get_handle(netdev); 1425 int ret = -EIO; 1426 1427 if (h->ae_algo->ops->set_vf_vlan_filter) 1428 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1429 qos, vlan_proto); 1430 1431 return ret; 1432 } 1433 1434 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1435 { 1436 struct hnae3_handle *h = hns3_get_handle(netdev); 1437 bool if_running = netif_running(netdev); 1438 int ret; 1439 1440 if (!h->ae_algo->ops->set_mtu) 1441 return -EOPNOTSUPP; 1442 1443 /* if this was called with netdev up then bring netdevice down */ 1444 if (if_running) { 1445 (void)hns3_nic_net_stop(netdev); 1446 msleep(100); 1447 } 1448 1449 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 1450 if (ret) { 1451 netdev_err(netdev, "failed to change MTU in hardware %d\n", 1452 ret); 1453 return ret; 1454 } 1455 1456 netdev->mtu = new_mtu; 1457 1458 /* if the netdev was running earlier, bring it up again */ 1459 if (if_running && hns3_nic_net_open(netdev)) 1460 ret = -EINVAL; 1461 1462 return ret; 1463 } 1464 1465 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 1466 { 1467 struct hns3_nic_priv *priv = netdev_priv(ndev); 1468 struct hns3_enet_ring *tx_ring = NULL; 1469 int timeout_queue = 0; 1470 int hw_head, hw_tail; 1471 int i; 1472 1473 /* Find the stopped queue the same way the stack does */ 1474 for (i = 0; i < ndev->real_num_tx_queues; i++) { 1475 struct netdev_queue *q; 1476 unsigned long trans_start; 1477 1478 q = netdev_get_tx_queue(ndev, i); 1479 trans_start = q->trans_start; 1480 if (netif_xmit_stopped(q) && 1481 time_after(jiffies, 1482 (trans_start + ndev->watchdog_timeo))) { 1483 timeout_queue = i; 1484 break; 1485 } 1486 } 1487 1488 if (i == ndev->num_tx_queues) { 1489 netdev_info(ndev, 1490 "no netdev TX timeout queue found, timeout count: %llu\n", 1491 priv->tx_timeout_count); 1492 return false; 1493 } 1494 1495 tx_ring = priv->ring_data[timeout_queue].ring; 1496 1497 hw_head = readl_relaxed(tx_ring->tqp->io_base + 1498 HNS3_RING_TX_RING_HEAD_REG); 1499 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 1500 HNS3_RING_TX_RING_TAIL_REG); 1501 netdev_info(ndev, 1502 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n", 1503 priv->tx_timeout_count, 1504 timeout_queue, 1505 tx_ring->next_to_use, 1506 tx_ring->next_to_clean, 1507 hw_head, 1508 hw_tail, 1509 readl(tx_ring->tqp_vector->mask_addr)); 1510 1511 return true; 1512 } 1513 1514 static void hns3_nic_net_timeout(struct net_device *ndev) 1515 { 1516 struct hns3_nic_priv *priv = netdev_priv(ndev); 1517 struct hnae3_handle *h = priv->ae_handle; 1518 1519 if (!hns3_get_tx_timeo_queue_info(ndev)) 1520 return; 1521 1522 priv->tx_timeout_count++; 1523 1524 if (time_before(jiffies, (h->last_reset_time + ndev->watchdog_timeo))) 1525 return; 1526 1527 /* request the reset */ 1528 if (h->ae_algo->ops->reset_event) 1529 h->ae_algo->ops->reset_event(h); 1530 } 1531 1532 static const struct net_device_ops hns3_nic_netdev_ops = { 1533 .ndo_open = hns3_nic_net_open, 1534 .ndo_stop = hns3_nic_net_stop, 1535 .ndo_start_xmit = hns3_nic_net_xmit, 1536 .ndo_tx_timeout = hns3_nic_net_timeout, 1537 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 1538 .ndo_change_mtu = hns3_nic_change_mtu, 1539 .ndo_set_features = hns3_nic_set_features, 1540 .ndo_get_stats64 = hns3_nic_get_stats64, 1541 .ndo_setup_tc = hns3_nic_setup_tc, 1542 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 1543 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 1544 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 1545 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 1546 }; 1547 1548 static bool hns3_is_phys_func(struct pci_dev *pdev) 1549 { 1550 u32 dev_id = pdev->device; 1551 1552 switch (dev_id) { 1553 case HNAE3_DEV_ID_GE: 1554 case HNAE3_DEV_ID_25GE: 1555 case HNAE3_DEV_ID_25GE_RDMA: 1556 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 1557 case HNAE3_DEV_ID_50GE_RDMA: 1558 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 1559 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 1560 return true; 1561 case HNAE3_DEV_ID_100G_VF: 1562 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF: 1563 return false; 1564 default: 1565 dev_warn(&pdev->dev, "un-recognized pci device-id %d", 1566 dev_id); 1567 } 1568 1569 return false; 1570 } 1571 1572 static void hns3_disable_sriov(struct pci_dev *pdev) 1573 { 1574 /* If our VFs are assigned we cannot shut down SR-IOV 1575 * without causing issues, so just leave the hardware 1576 * available but disabled 1577 */ 1578 if (pci_vfs_assigned(pdev)) { 1579 dev_warn(&pdev->dev, 1580 "disabling driver while VFs are assigned\n"); 1581 return; 1582 } 1583 1584 pci_disable_sriov(pdev); 1585 } 1586 1587 /* hns3_probe - Device initialization routine 1588 * @pdev: PCI device information struct 1589 * @ent: entry in hns3_pci_tbl 1590 * 1591 * hns3_probe initializes a PF identified by a pci_dev structure. 1592 * The OS initialization, configuring of the PF private structure, 1593 * and a hardware reset occur. 1594 * 1595 * Returns 0 on success, negative on failure 1596 */ 1597 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1598 { 1599 struct hnae3_ae_dev *ae_dev; 1600 int ret; 1601 1602 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), 1603 GFP_KERNEL); 1604 if (!ae_dev) { 1605 ret = -ENOMEM; 1606 return ret; 1607 } 1608 1609 ae_dev->pdev = pdev; 1610 ae_dev->flag = ent->driver_data; 1611 ae_dev->dev_type = HNAE3_DEV_KNIC; 1612 pci_set_drvdata(pdev, ae_dev); 1613 1614 hnae3_register_ae_dev(ae_dev); 1615 1616 return 0; 1617 } 1618 1619 /* hns3_remove - Device removal routine 1620 * @pdev: PCI device information struct 1621 */ 1622 static void hns3_remove(struct pci_dev *pdev) 1623 { 1624 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1625 1626 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 1627 hns3_disable_sriov(pdev); 1628 1629 hnae3_unregister_ae_dev(ae_dev); 1630 } 1631 1632 /** 1633 * hns3_pci_sriov_configure 1634 * @pdev: pointer to a pci_dev structure 1635 * @num_vfs: number of VFs to allocate 1636 * 1637 * Enable or change the number of VFs. Called when the user updates the number 1638 * of VFs in sysfs. 1639 **/ 1640 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 1641 { 1642 int ret; 1643 1644 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 1645 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 1646 return -EINVAL; 1647 } 1648 1649 if (num_vfs) { 1650 ret = pci_enable_sriov(pdev, num_vfs); 1651 if (ret) 1652 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 1653 else 1654 return num_vfs; 1655 } else if (!pci_vfs_assigned(pdev)) { 1656 pci_disable_sriov(pdev); 1657 } else { 1658 dev_warn(&pdev->dev, 1659 "Unable to free VFs because some are assigned to VMs.\n"); 1660 } 1661 1662 return 0; 1663 } 1664 1665 static void hns3_shutdown(struct pci_dev *pdev) 1666 { 1667 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1668 1669 hnae3_unregister_ae_dev(ae_dev); 1670 devm_kfree(&pdev->dev, ae_dev); 1671 pci_set_drvdata(pdev, NULL); 1672 1673 if (system_state == SYSTEM_POWER_OFF) 1674 pci_set_power_state(pdev, PCI_D3hot); 1675 } 1676 1677 static struct pci_driver hns3_driver = { 1678 .name = hns3_driver_name, 1679 .id_table = hns3_pci_tbl, 1680 .probe = hns3_probe, 1681 .remove = hns3_remove, 1682 .shutdown = hns3_shutdown, 1683 .sriov_configure = hns3_pci_sriov_configure, 1684 }; 1685 1686 /* set default feature to hns3 */ 1687 static void hns3_set_default_feature(struct net_device *netdev) 1688 { 1689 struct hnae3_handle *h = hns3_get_handle(netdev); 1690 struct pci_dev *pdev = h->pdev; 1691 1692 netdev->priv_flags |= IFF_UNICAST_FLT; 1693 1694 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1695 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1696 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1697 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1698 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1699 1700 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID; 1701 1702 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 1703 1704 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1705 NETIF_F_HW_VLAN_CTAG_FILTER | 1706 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1707 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1708 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1709 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1710 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1711 1712 netdev->vlan_features |= 1713 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | 1714 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 1715 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1716 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1717 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1718 1719 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1720 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1721 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1722 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1723 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1724 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1725 1726 if (pdev->revision != 0x20) 1727 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1728 } 1729 1730 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 1731 struct hns3_desc_cb *cb) 1732 { 1733 unsigned int order = hnae3_page_order(ring); 1734 struct page *p; 1735 1736 p = dev_alloc_pages(order); 1737 if (!p) 1738 return -ENOMEM; 1739 1740 cb->priv = p; 1741 cb->page_offset = 0; 1742 cb->reuse_flag = 0; 1743 cb->buf = page_address(p); 1744 cb->length = hnae3_page_size(ring); 1745 cb->type = DESC_TYPE_PAGE; 1746 1747 return 0; 1748 } 1749 1750 static void hns3_free_buffer(struct hns3_enet_ring *ring, 1751 struct hns3_desc_cb *cb) 1752 { 1753 if (cb->type == DESC_TYPE_SKB) 1754 dev_kfree_skb_any((struct sk_buff *)cb->priv); 1755 else if (!HNAE3_IS_TX_RING(ring)) 1756 put_page((struct page *)cb->priv); 1757 memset(cb, 0, sizeof(*cb)); 1758 } 1759 1760 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 1761 { 1762 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 1763 cb->length, ring_to_dma_dir(ring)); 1764 1765 if (dma_mapping_error(ring_to_dev(ring), cb->dma)) 1766 return -EIO; 1767 1768 return 0; 1769 } 1770 1771 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 1772 struct hns3_desc_cb *cb) 1773 { 1774 if (cb->type == DESC_TYPE_SKB) 1775 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 1776 ring_to_dma_dir(ring)); 1777 else 1778 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 1779 ring_to_dma_dir(ring)); 1780 } 1781 1782 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 1783 { 1784 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 1785 ring->desc[i].addr = 0; 1786 } 1787 1788 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i) 1789 { 1790 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 1791 1792 if (!ring->desc_cb[i].dma) 1793 return; 1794 1795 hns3_buffer_detach(ring, i); 1796 hns3_free_buffer(ring, cb); 1797 } 1798 1799 static void hns3_free_buffers(struct hns3_enet_ring *ring) 1800 { 1801 int i; 1802 1803 for (i = 0; i < ring->desc_num; i++) 1804 hns3_free_buffer_detach(ring, i); 1805 } 1806 1807 /* free desc along with its attached buffer */ 1808 static void hns3_free_desc(struct hns3_enet_ring *ring) 1809 { 1810 int size = ring->desc_num * sizeof(ring->desc[0]); 1811 1812 hns3_free_buffers(ring); 1813 1814 if (ring->desc) { 1815 dma_free_coherent(ring_to_dev(ring), size, 1816 ring->desc, ring->desc_dma_addr); 1817 ring->desc = NULL; 1818 } 1819 } 1820 1821 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 1822 { 1823 int size = ring->desc_num * sizeof(ring->desc[0]); 1824 1825 ring->desc = dma_zalloc_coherent(ring_to_dev(ring), size, 1826 &ring->desc_dma_addr, 1827 GFP_KERNEL); 1828 if (!ring->desc) 1829 return -ENOMEM; 1830 1831 return 0; 1832 } 1833 1834 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring, 1835 struct hns3_desc_cb *cb) 1836 { 1837 int ret; 1838 1839 ret = hns3_alloc_buffer(ring, cb); 1840 if (ret) 1841 goto out; 1842 1843 ret = hns3_map_buffer(ring, cb); 1844 if (ret) 1845 goto out_with_buf; 1846 1847 return 0; 1848 1849 out_with_buf: 1850 hns3_free_buffer(ring, cb); 1851 out: 1852 return ret; 1853 } 1854 1855 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i) 1856 { 1857 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]); 1858 1859 if (ret) 1860 return ret; 1861 1862 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 1863 1864 return 0; 1865 } 1866 1867 /* Allocate memory for raw pkg, and map with dma */ 1868 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 1869 { 1870 int i, j, ret; 1871 1872 for (i = 0; i < ring->desc_num; i++) { 1873 ret = hns3_alloc_buffer_attach(ring, i); 1874 if (ret) 1875 goto out_buffer_fail; 1876 } 1877 1878 return 0; 1879 1880 out_buffer_fail: 1881 for (j = i - 1; j >= 0; j--) 1882 hns3_free_buffer_detach(ring, j); 1883 return ret; 1884 } 1885 1886 /* detach a in-used buffer and replace with a reserved one */ 1887 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 1888 struct hns3_desc_cb *res_cb) 1889 { 1890 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 1891 ring->desc_cb[i] = *res_cb; 1892 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 1893 ring->desc[i].rx.bd_base_info = 0; 1894 } 1895 1896 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 1897 { 1898 ring->desc_cb[i].reuse_flag = 0; 1899 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma 1900 + ring->desc_cb[i].page_offset); 1901 ring->desc[i].rx.bd_base_info = 0; 1902 } 1903 1904 static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes, 1905 int *pkts) 1906 { 1907 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 1908 1909 (*pkts) += (desc_cb->type == DESC_TYPE_SKB); 1910 (*bytes) += desc_cb->length; 1911 /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/ 1912 hns3_free_buffer_detach(ring, ring->next_to_clean); 1913 1914 ring_ptr_move_fw(ring, next_to_clean); 1915 } 1916 1917 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h) 1918 { 1919 int u = ring->next_to_use; 1920 int c = ring->next_to_clean; 1921 1922 if (unlikely(h > ring->desc_num)) 1923 return 0; 1924 1925 return u > c ? (h > c && h <= u) : (h > c || h <= u); 1926 } 1927 1928 bool hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget) 1929 { 1930 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 1931 struct netdev_queue *dev_queue; 1932 int bytes, pkts; 1933 int head; 1934 1935 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG); 1936 rmb(); /* Make sure head is ready before touch any data */ 1937 1938 if (is_ring_empty(ring) || head == ring->next_to_clean) 1939 return true; /* no data to poll */ 1940 1941 if (unlikely(!is_valid_clean_head(ring, head))) { 1942 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head, 1943 ring->next_to_use, ring->next_to_clean); 1944 1945 u64_stats_update_begin(&ring->syncp); 1946 ring->stats.io_err_cnt++; 1947 u64_stats_update_end(&ring->syncp); 1948 return true; 1949 } 1950 1951 bytes = 0; 1952 pkts = 0; 1953 while (head != ring->next_to_clean && budget) { 1954 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts); 1955 /* Issue prefetch for next Tx descriptor */ 1956 prefetch(&ring->desc_cb[ring->next_to_clean]); 1957 budget--; 1958 } 1959 1960 ring->tqp_vector->tx_group.total_bytes += bytes; 1961 ring->tqp_vector->tx_group.total_packets += pkts; 1962 1963 u64_stats_update_begin(&ring->syncp); 1964 ring->stats.tx_bytes += bytes; 1965 ring->stats.tx_pkts += pkts; 1966 u64_stats_update_end(&ring->syncp); 1967 1968 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 1969 netdev_tx_completed_queue(dev_queue, pkts, bytes); 1970 1971 if (unlikely(pkts && netif_carrier_ok(netdev) && 1972 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) { 1973 /* Make sure that anybody stopping the queue after this 1974 * sees the new next_to_clean. 1975 */ 1976 smp_mb(); 1977 if (netif_tx_queue_stopped(dev_queue)) { 1978 netif_tx_wake_queue(dev_queue); 1979 ring->stats.restart_queue++; 1980 } 1981 } 1982 1983 return !!budget; 1984 } 1985 1986 static int hns3_desc_unused(struct hns3_enet_ring *ring) 1987 { 1988 int ntc = ring->next_to_clean; 1989 int ntu = ring->next_to_use; 1990 1991 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 1992 } 1993 1994 static void 1995 hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count) 1996 { 1997 struct hns3_desc_cb *desc_cb; 1998 struct hns3_desc_cb res_cbs; 1999 int i, ret; 2000 2001 for (i = 0; i < cleand_count; i++) { 2002 desc_cb = &ring->desc_cb[ring->next_to_use]; 2003 if (desc_cb->reuse_flag) { 2004 u64_stats_update_begin(&ring->syncp); 2005 ring->stats.reuse_pg_cnt++; 2006 u64_stats_update_end(&ring->syncp); 2007 2008 hns3_reuse_buffer(ring, ring->next_to_use); 2009 } else { 2010 ret = hns3_reserve_buffer_map(ring, &res_cbs); 2011 if (ret) { 2012 u64_stats_update_begin(&ring->syncp); 2013 ring->stats.sw_err_cnt++; 2014 u64_stats_update_end(&ring->syncp); 2015 2016 netdev_err(ring->tqp->handle->kinfo.netdev, 2017 "hnae reserve buffer map failed.\n"); 2018 break; 2019 } 2020 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 2021 } 2022 2023 ring_ptr_move_fw(ring, next_to_use); 2024 } 2025 2026 wmb(); /* Make all data has been write before submit */ 2027 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2028 } 2029 2030 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2031 struct hns3_enet_ring *ring, int pull_len, 2032 struct hns3_desc_cb *desc_cb) 2033 { 2034 struct hns3_desc *desc; 2035 u32 truesize; 2036 int size; 2037 int last_offset; 2038 bool twobufs; 2039 2040 twobufs = ((PAGE_SIZE < 8192) && 2041 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048); 2042 2043 desc = &ring->desc[ring->next_to_clean]; 2044 size = le16_to_cpu(desc->rx.size); 2045 2046 truesize = hnae3_buf_size(ring); 2047 2048 if (!twobufs) 2049 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring); 2050 2051 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2052 size - pull_len, truesize); 2053 2054 /* Avoid re-using remote pages,flag default unreuse */ 2055 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id())) 2056 return; 2057 2058 if (twobufs) { 2059 /* If we are only owner of page we can reuse it */ 2060 if (likely(page_count(desc_cb->priv) == 1)) { 2061 /* Flip page offset to other buffer */ 2062 desc_cb->page_offset ^= truesize; 2063 2064 desc_cb->reuse_flag = 1; 2065 /* bump ref count on page before it is given*/ 2066 get_page(desc_cb->priv); 2067 } 2068 return; 2069 } 2070 2071 /* Move offset up to the next cache line */ 2072 desc_cb->page_offset += truesize; 2073 2074 if (desc_cb->page_offset <= last_offset) { 2075 desc_cb->reuse_flag = 1; 2076 /* Bump ref count on page before it is given*/ 2077 get_page(desc_cb->priv); 2078 } 2079 } 2080 2081 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2082 struct hns3_desc *desc) 2083 { 2084 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2085 int l3_type, l4_type; 2086 u32 bd_base_info; 2087 int ol4_type; 2088 u32 l234info; 2089 2090 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2091 l234info = le32_to_cpu(desc->rx.l234_info); 2092 2093 skb->ip_summed = CHECKSUM_NONE; 2094 2095 skb_checksum_none_assert(skb); 2096 2097 if (!(netdev->features & NETIF_F_RXCSUM)) 2098 return; 2099 2100 /* check if hardware has done checksum */ 2101 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B)) 2102 return; 2103 2104 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) || 2105 hnae3_get_bit(l234info, HNS3_RXD_L4E_B) || 2106 hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) || 2107 hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) { 2108 netdev_err(netdev, "L3/L4 error pkt\n"); 2109 u64_stats_update_begin(&ring->syncp); 2110 ring->stats.l3l4_csum_err++; 2111 u64_stats_update_end(&ring->syncp); 2112 2113 return; 2114 } 2115 2116 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2117 HNS3_RXD_L3ID_S); 2118 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 2119 HNS3_RXD_L4ID_S); 2120 2121 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M, 2122 HNS3_RXD_OL4ID_S); 2123 switch (ol4_type) { 2124 case HNS3_OL4_TYPE_MAC_IN_UDP: 2125 case HNS3_OL4_TYPE_NVGRE: 2126 skb->csum_level = 1; 2127 /* fall through */ 2128 case HNS3_OL4_TYPE_NO_TUN: 2129 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 2130 if ((l3_type == HNS3_L3_TYPE_IPV4 || 2131 l3_type == HNS3_L3_TYPE_IPV6) && 2132 (l4_type == HNS3_L4_TYPE_UDP || 2133 l4_type == HNS3_L4_TYPE_TCP || 2134 l4_type == HNS3_L4_TYPE_SCTP)) 2135 skb->ip_summed = CHECKSUM_UNNECESSARY; 2136 break; 2137 } 2138 } 2139 2140 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 2141 { 2142 napi_gro_receive(&ring->tqp_vector->napi, skb); 2143 } 2144 2145 static u16 hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 2146 struct hns3_desc *desc, u32 l234info) 2147 { 2148 struct pci_dev *pdev = ring->tqp->handle->pdev; 2149 u16 vlan_tag; 2150 2151 if (pdev->revision == 0x20) { 2152 vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2153 if (!(vlan_tag & VLAN_VID_MASK)) 2154 vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2155 2156 return vlan_tag; 2157 } 2158 2159 #define HNS3_STRP_OUTER_VLAN 0x1 2160 #define HNS3_STRP_INNER_VLAN 0x2 2161 2162 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 2163 HNS3_RXD_STRP_TAGP_S)) { 2164 case HNS3_STRP_OUTER_VLAN: 2165 vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2166 break; 2167 case HNS3_STRP_INNER_VLAN: 2168 vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2169 break; 2170 default: 2171 vlan_tag = 0; 2172 break; 2173 } 2174 2175 return vlan_tag; 2176 } 2177 2178 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring, 2179 struct sk_buff **out_skb, int *out_bnum) 2180 { 2181 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2182 struct hns3_desc_cb *desc_cb; 2183 struct hns3_desc *desc; 2184 struct sk_buff *skb; 2185 unsigned char *va; 2186 u32 bd_base_info; 2187 int pull_len; 2188 u32 l234info; 2189 int length; 2190 int bnum; 2191 2192 desc = &ring->desc[ring->next_to_clean]; 2193 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2194 2195 prefetch(desc); 2196 2197 length = le16_to_cpu(desc->rx.size); 2198 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2199 2200 /* Check valid BD */ 2201 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) 2202 return -EFAULT; 2203 2204 va = (unsigned char *)desc_cb->buf + desc_cb->page_offset; 2205 2206 /* Prefetch first cache line of first page 2207 * Idea is to cache few bytes of the header of the packet. Our L1 Cache 2208 * line size is 64B so need to prefetch twice to make it 128B. But in 2209 * actual we can have greater size of caches with 128B Level 1 cache 2210 * lines. In such a case, single fetch would suffice to cache in the 2211 * relevant part of the header. 2212 */ 2213 prefetch(va); 2214 #if L1_CACHE_BYTES < 128 2215 prefetch(va + L1_CACHE_BYTES); 2216 #endif 2217 2218 skb = *out_skb = napi_alloc_skb(&ring->tqp_vector->napi, 2219 HNS3_RX_HEAD_SIZE); 2220 if (unlikely(!skb)) { 2221 netdev_err(netdev, "alloc rx skb fail\n"); 2222 2223 u64_stats_update_begin(&ring->syncp); 2224 ring->stats.sw_err_cnt++; 2225 u64_stats_update_end(&ring->syncp); 2226 2227 return -ENOMEM; 2228 } 2229 2230 prefetchw(skb->data); 2231 2232 bnum = 1; 2233 if (length <= HNS3_RX_HEAD_SIZE) { 2234 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 2235 2236 /* We can reuse buffer as-is, just make sure it is local */ 2237 if (likely(page_to_nid(desc_cb->priv) == numa_node_id())) 2238 desc_cb->reuse_flag = 1; 2239 else /* This page cannot be reused so discard it */ 2240 put_page(desc_cb->priv); 2241 2242 ring_ptr_move_fw(ring, next_to_clean); 2243 } else { 2244 u64_stats_update_begin(&ring->syncp); 2245 ring->stats.seg_pkt_cnt++; 2246 u64_stats_update_end(&ring->syncp); 2247 2248 pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE); 2249 2250 memcpy(__skb_put(skb, pull_len), va, 2251 ALIGN(pull_len, sizeof(long))); 2252 2253 hns3_nic_reuse_page(skb, 0, ring, pull_len, desc_cb); 2254 ring_ptr_move_fw(ring, next_to_clean); 2255 2256 while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) { 2257 desc = &ring->desc[ring->next_to_clean]; 2258 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2259 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2260 hns3_nic_reuse_page(skb, bnum, ring, 0, desc_cb); 2261 ring_ptr_move_fw(ring, next_to_clean); 2262 bnum++; 2263 } 2264 } 2265 2266 *out_bnum = bnum; 2267 2268 l234info = le32_to_cpu(desc->rx.l234_info); 2269 2270 /* Based on hw strategy, the tag offloaded will be stored at 2271 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 2272 * in one layer tag case. 2273 */ 2274 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 2275 u16 vlan_tag; 2276 2277 vlan_tag = hns3_parse_vlan_tag(ring, desc, l234info); 2278 if (vlan_tag & VLAN_VID_MASK) 2279 __vlan_hwaccel_put_tag(skb, 2280 htons(ETH_P_8021Q), 2281 vlan_tag); 2282 } 2283 2284 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) { 2285 netdev_err(netdev, "no valid bd,%016llx,%016llx\n", 2286 ((u64 *)desc)[0], ((u64 *)desc)[1]); 2287 u64_stats_update_begin(&ring->syncp); 2288 ring->stats.non_vld_descs++; 2289 u64_stats_update_end(&ring->syncp); 2290 2291 dev_kfree_skb_any(skb); 2292 return -EINVAL; 2293 } 2294 2295 if (unlikely((!desc->rx.pkt_len) || 2296 hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) { 2297 netdev_err(netdev, "truncated pkt\n"); 2298 u64_stats_update_begin(&ring->syncp); 2299 ring->stats.err_pkt_len++; 2300 u64_stats_update_end(&ring->syncp); 2301 2302 dev_kfree_skb_any(skb); 2303 return -EFAULT; 2304 } 2305 2306 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) { 2307 netdev_err(netdev, "L2 error pkt\n"); 2308 u64_stats_update_begin(&ring->syncp); 2309 ring->stats.l2_err++; 2310 u64_stats_update_end(&ring->syncp); 2311 2312 dev_kfree_skb_any(skb); 2313 return -EFAULT; 2314 } 2315 2316 u64_stats_update_begin(&ring->syncp); 2317 ring->stats.rx_pkts++; 2318 ring->stats.rx_bytes += skb->len; 2319 u64_stats_update_end(&ring->syncp); 2320 2321 ring->tqp_vector->rx_group.total_bytes += skb->len; 2322 2323 hns3_rx_checksum(ring, skb, desc); 2324 return 0; 2325 } 2326 2327 int hns3_clean_rx_ring( 2328 struct hns3_enet_ring *ring, int budget, 2329 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 2330 { 2331 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 2332 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2333 int recv_pkts, recv_bds, clean_count, err; 2334 int unused_count = hns3_desc_unused(ring); 2335 struct sk_buff *skb = NULL; 2336 int num, bnum = 0; 2337 2338 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG); 2339 rmb(); /* Make sure num taken effect before the other data is touched */ 2340 2341 recv_pkts = 0, recv_bds = 0, clean_count = 0; 2342 num -= unused_count; 2343 2344 while (recv_pkts < budget && recv_bds < num) { 2345 /* Reuse or realloc buffers */ 2346 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 2347 hns3_nic_alloc_rx_buffers(ring, 2348 clean_count + unused_count); 2349 clean_count = 0; 2350 unused_count = hns3_desc_unused(ring); 2351 } 2352 2353 /* Poll one pkt */ 2354 err = hns3_handle_rx_bd(ring, &skb, &bnum); 2355 if (unlikely(!skb)) /* This fault cannot be repaired */ 2356 goto out; 2357 2358 recv_bds += bnum; 2359 clean_count += bnum; 2360 if (unlikely(err)) { /* Do jump the err */ 2361 recv_pkts++; 2362 continue; 2363 } 2364 2365 /* Do update ip stack process */ 2366 skb->protocol = eth_type_trans(skb, netdev); 2367 rx_fn(ring, skb); 2368 2369 recv_pkts++; 2370 } 2371 2372 out: 2373 /* Make all data has been write before submit */ 2374 if (clean_count + unused_count > 0) 2375 hns3_nic_alloc_rx_buffers(ring, 2376 clean_count + unused_count); 2377 2378 return recv_pkts; 2379 } 2380 2381 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 2382 { 2383 struct hns3_enet_tqp_vector *tqp_vector = 2384 ring_group->ring->tqp_vector; 2385 enum hns3_flow_level_range new_flow_level; 2386 int packets_per_msecs; 2387 int bytes_per_msecs; 2388 u32 time_passed_ms; 2389 u16 new_int_gl; 2390 2391 if (!ring_group->coal.int_gl || !tqp_vector->last_jiffies) 2392 return false; 2393 2394 if (ring_group->total_packets == 0) { 2395 ring_group->coal.int_gl = HNS3_INT_GL_50K; 2396 ring_group->coal.flow_level = HNS3_FLOW_LOW; 2397 return true; 2398 } 2399 2400 /* Simple throttlerate management 2401 * 0-10MB/s lower (50000 ints/s) 2402 * 10-20MB/s middle (20000 ints/s) 2403 * 20-1249MB/s high (18000 ints/s) 2404 * > 40000pps ultra (8000 ints/s) 2405 */ 2406 new_flow_level = ring_group->coal.flow_level; 2407 new_int_gl = ring_group->coal.int_gl; 2408 time_passed_ms = 2409 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 2410 2411 if (!time_passed_ms) 2412 return false; 2413 2414 do_div(ring_group->total_packets, time_passed_ms); 2415 packets_per_msecs = ring_group->total_packets; 2416 2417 do_div(ring_group->total_bytes, time_passed_ms); 2418 bytes_per_msecs = ring_group->total_bytes; 2419 2420 #define HNS3_RX_LOW_BYTE_RATE 10000 2421 #define HNS3_RX_MID_BYTE_RATE 20000 2422 2423 switch (new_flow_level) { 2424 case HNS3_FLOW_LOW: 2425 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 2426 new_flow_level = HNS3_FLOW_MID; 2427 break; 2428 case HNS3_FLOW_MID: 2429 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 2430 new_flow_level = HNS3_FLOW_HIGH; 2431 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 2432 new_flow_level = HNS3_FLOW_LOW; 2433 break; 2434 case HNS3_FLOW_HIGH: 2435 case HNS3_FLOW_ULTRA: 2436 default: 2437 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 2438 new_flow_level = HNS3_FLOW_MID; 2439 break; 2440 } 2441 2442 #define HNS3_RX_ULTRA_PACKET_RATE 40 2443 2444 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 2445 &tqp_vector->rx_group == ring_group) 2446 new_flow_level = HNS3_FLOW_ULTRA; 2447 2448 switch (new_flow_level) { 2449 case HNS3_FLOW_LOW: 2450 new_int_gl = HNS3_INT_GL_50K; 2451 break; 2452 case HNS3_FLOW_MID: 2453 new_int_gl = HNS3_INT_GL_20K; 2454 break; 2455 case HNS3_FLOW_HIGH: 2456 new_int_gl = HNS3_INT_GL_18K; 2457 break; 2458 case HNS3_FLOW_ULTRA: 2459 new_int_gl = HNS3_INT_GL_8K; 2460 break; 2461 default: 2462 break; 2463 } 2464 2465 ring_group->total_bytes = 0; 2466 ring_group->total_packets = 0; 2467 ring_group->coal.flow_level = new_flow_level; 2468 if (new_int_gl != ring_group->coal.int_gl) { 2469 ring_group->coal.int_gl = new_int_gl; 2470 return true; 2471 } 2472 return false; 2473 } 2474 2475 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 2476 { 2477 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 2478 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 2479 bool rx_update, tx_update; 2480 2481 if (tqp_vector->int_adapt_down > 0) { 2482 tqp_vector->int_adapt_down--; 2483 return; 2484 } 2485 2486 if (rx_group->coal.gl_adapt_enable) { 2487 rx_update = hns3_get_new_int_gl(rx_group); 2488 if (rx_update) 2489 hns3_set_vector_coalesce_rx_gl(tqp_vector, 2490 rx_group->coal.int_gl); 2491 } 2492 2493 if (tx_group->coal.gl_adapt_enable) { 2494 tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group); 2495 if (tx_update) 2496 hns3_set_vector_coalesce_tx_gl(tqp_vector, 2497 tx_group->coal.int_gl); 2498 } 2499 2500 tqp_vector->last_jiffies = jiffies; 2501 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START; 2502 } 2503 2504 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 2505 { 2506 struct hns3_enet_ring *ring; 2507 int rx_pkt_total = 0; 2508 2509 struct hns3_enet_tqp_vector *tqp_vector = 2510 container_of(napi, struct hns3_enet_tqp_vector, napi); 2511 bool clean_complete = true; 2512 int rx_budget; 2513 2514 /* Since the actual Tx work is minimal, we can give the Tx a larger 2515 * budget and be more aggressive about cleaning up the Tx descriptors. 2516 */ 2517 hns3_for_each_ring(ring, tqp_vector->tx_group) { 2518 if (!hns3_clean_tx_ring(ring, budget)) 2519 clean_complete = false; 2520 } 2521 2522 /* make sure rx ring budget not smaller than 1 */ 2523 rx_budget = max(budget / tqp_vector->num_tqps, 1); 2524 2525 hns3_for_each_ring(ring, tqp_vector->rx_group) { 2526 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 2527 hns3_rx_skb); 2528 2529 if (rx_cleaned >= rx_budget) 2530 clean_complete = false; 2531 2532 rx_pkt_total += rx_cleaned; 2533 } 2534 2535 tqp_vector->rx_group.total_packets += rx_pkt_total; 2536 2537 if (!clean_complete) 2538 return budget; 2539 2540 napi_complete(napi); 2541 hns3_update_new_int_gl(tqp_vector); 2542 hns3_mask_vector_irq(tqp_vector, 1); 2543 2544 return rx_pkt_total; 2545 } 2546 2547 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 2548 struct hnae3_ring_chain_node *head) 2549 { 2550 struct pci_dev *pdev = tqp_vector->handle->pdev; 2551 struct hnae3_ring_chain_node *cur_chain = head; 2552 struct hnae3_ring_chain_node *chain; 2553 struct hns3_enet_ring *tx_ring; 2554 struct hns3_enet_ring *rx_ring; 2555 2556 tx_ring = tqp_vector->tx_group.ring; 2557 if (tx_ring) { 2558 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 2559 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 2560 HNAE3_RING_TYPE_TX); 2561 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2562 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 2563 2564 cur_chain->next = NULL; 2565 2566 while (tx_ring->next) { 2567 tx_ring = tx_ring->next; 2568 2569 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 2570 GFP_KERNEL); 2571 if (!chain) 2572 return -ENOMEM; 2573 2574 cur_chain->next = chain; 2575 chain->tqp_index = tx_ring->tqp->tqp_index; 2576 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 2577 HNAE3_RING_TYPE_TX); 2578 hnae3_set_field(chain->int_gl_idx, 2579 HNAE3_RING_GL_IDX_M, 2580 HNAE3_RING_GL_IDX_S, 2581 HNAE3_RING_GL_TX); 2582 2583 cur_chain = chain; 2584 } 2585 } 2586 2587 rx_ring = tqp_vector->rx_group.ring; 2588 if (!tx_ring && rx_ring) { 2589 cur_chain->next = NULL; 2590 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 2591 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 2592 HNAE3_RING_TYPE_RX); 2593 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2594 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 2595 2596 rx_ring = rx_ring->next; 2597 } 2598 2599 while (rx_ring) { 2600 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 2601 if (!chain) 2602 return -ENOMEM; 2603 2604 cur_chain->next = chain; 2605 chain->tqp_index = rx_ring->tqp->tqp_index; 2606 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 2607 HNAE3_RING_TYPE_RX); 2608 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2609 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 2610 2611 cur_chain = chain; 2612 2613 rx_ring = rx_ring->next; 2614 } 2615 2616 return 0; 2617 } 2618 2619 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 2620 struct hnae3_ring_chain_node *head) 2621 { 2622 struct pci_dev *pdev = tqp_vector->handle->pdev; 2623 struct hnae3_ring_chain_node *chain_tmp, *chain; 2624 2625 chain = head->next; 2626 2627 while (chain) { 2628 chain_tmp = chain->next; 2629 devm_kfree(&pdev->dev, chain); 2630 chain = chain_tmp; 2631 } 2632 } 2633 2634 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 2635 struct hns3_enet_ring *ring) 2636 { 2637 ring->next = group->ring; 2638 group->ring = ring; 2639 2640 group->count++; 2641 } 2642 2643 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 2644 { 2645 struct hnae3_ring_chain_node vector_ring_chain; 2646 struct hnae3_handle *h = priv->ae_handle; 2647 struct hns3_enet_tqp_vector *tqp_vector; 2648 int ret = 0; 2649 u16 i; 2650 2651 for (i = 0; i < priv->vector_num; i++) { 2652 tqp_vector = &priv->tqp_vector[i]; 2653 hns3_vector_gl_rl_init_hw(tqp_vector, priv); 2654 tqp_vector->num_tqps = 0; 2655 } 2656 2657 for (i = 0; i < h->kinfo.num_tqps; i++) { 2658 u16 vector_i = i % priv->vector_num; 2659 u16 tqp_num = h->kinfo.num_tqps; 2660 2661 tqp_vector = &priv->tqp_vector[vector_i]; 2662 2663 hns3_add_ring_to_group(&tqp_vector->tx_group, 2664 priv->ring_data[i].ring); 2665 2666 hns3_add_ring_to_group(&tqp_vector->rx_group, 2667 priv->ring_data[i + tqp_num].ring); 2668 2669 priv->ring_data[i].ring->tqp_vector = tqp_vector; 2670 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector; 2671 tqp_vector->num_tqps++; 2672 } 2673 2674 for (i = 0; i < priv->vector_num; i++) { 2675 tqp_vector = &priv->tqp_vector[i]; 2676 2677 tqp_vector->rx_group.total_bytes = 0; 2678 tqp_vector->rx_group.total_packets = 0; 2679 tqp_vector->tx_group.total_bytes = 0; 2680 tqp_vector->tx_group.total_packets = 0; 2681 tqp_vector->handle = h; 2682 2683 ret = hns3_get_vector_ring_chain(tqp_vector, 2684 &vector_ring_chain); 2685 if (ret) 2686 return ret; 2687 2688 ret = h->ae_algo->ops->map_ring_to_vector(h, 2689 tqp_vector->vector_irq, &vector_ring_chain); 2690 2691 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 2692 2693 if (ret) 2694 return ret; 2695 2696 netif_napi_add(priv->netdev, &tqp_vector->napi, 2697 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 2698 } 2699 2700 return 0; 2701 } 2702 2703 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 2704 { 2705 struct hnae3_handle *h = priv->ae_handle; 2706 struct hns3_enet_tqp_vector *tqp_vector; 2707 struct hnae3_vector_info *vector; 2708 struct pci_dev *pdev = h->pdev; 2709 u16 tqp_num = h->kinfo.num_tqps; 2710 u16 vector_num; 2711 int ret = 0; 2712 u16 i; 2713 2714 /* RSS size, cpu online and vector_num should be the same */ 2715 /* Should consider 2p/4p later */ 2716 vector_num = min_t(u16, num_online_cpus(), tqp_num); 2717 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 2718 GFP_KERNEL); 2719 if (!vector) 2720 return -ENOMEM; 2721 2722 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 2723 2724 priv->vector_num = vector_num; 2725 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 2726 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 2727 GFP_KERNEL); 2728 if (!priv->tqp_vector) { 2729 ret = -ENOMEM; 2730 goto out; 2731 } 2732 2733 for (i = 0; i < priv->vector_num; i++) { 2734 tqp_vector = &priv->tqp_vector[i]; 2735 tqp_vector->idx = i; 2736 tqp_vector->mask_addr = vector[i].io_addr; 2737 tqp_vector->vector_irq = vector[i].vector; 2738 hns3_vector_gl_rl_init(tqp_vector, priv); 2739 } 2740 2741 out: 2742 devm_kfree(&pdev->dev, vector); 2743 return ret; 2744 } 2745 2746 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 2747 { 2748 group->ring = NULL; 2749 group->count = 0; 2750 } 2751 2752 static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 2753 { 2754 struct hnae3_ring_chain_node vector_ring_chain; 2755 struct hnae3_handle *h = priv->ae_handle; 2756 struct hns3_enet_tqp_vector *tqp_vector; 2757 int i, ret; 2758 2759 for (i = 0; i < priv->vector_num; i++) { 2760 tqp_vector = &priv->tqp_vector[i]; 2761 2762 ret = hns3_get_vector_ring_chain(tqp_vector, 2763 &vector_ring_chain); 2764 if (ret) 2765 return ret; 2766 2767 ret = h->ae_algo->ops->unmap_ring_from_vector(h, 2768 tqp_vector->vector_irq, &vector_ring_chain); 2769 if (ret) 2770 return ret; 2771 2772 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 2773 2774 if (priv->tqp_vector[i].irq_init_flag == HNS3_VECTOR_INITED) { 2775 (void)irq_set_affinity_hint( 2776 priv->tqp_vector[i].vector_irq, 2777 NULL); 2778 free_irq(priv->tqp_vector[i].vector_irq, 2779 &priv->tqp_vector[i]); 2780 } 2781 2782 priv->ring_data[i].ring->irq_init_flag = HNS3_VECTOR_NOT_INITED; 2783 hns3_clear_ring_group(&tqp_vector->rx_group); 2784 hns3_clear_ring_group(&tqp_vector->tx_group); 2785 netif_napi_del(&priv->tqp_vector[i].napi); 2786 } 2787 2788 return 0; 2789 } 2790 2791 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 2792 { 2793 struct hnae3_handle *h = priv->ae_handle; 2794 struct pci_dev *pdev = h->pdev; 2795 int i, ret; 2796 2797 for (i = 0; i < priv->vector_num; i++) { 2798 struct hns3_enet_tqp_vector *tqp_vector; 2799 2800 tqp_vector = &priv->tqp_vector[i]; 2801 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 2802 if (ret) 2803 return ret; 2804 } 2805 2806 devm_kfree(&pdev->dev, priv->tqp_vector); 2807 return 0; 2808 } 2809 2810 static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 2811 int ring_type) 2812 { 2813 struct hns3_nic_ring_data *ring_data = priv->ring_data; 2814 int queue_num = priv->ae_handle->kinfo.num_tqps; 2815 struct pci_dev *pdev = priv->ae_handle->pdev; 2816 struct hns3_enet_ring *ring; 2817 2818 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL); 2819 if (!ring) 2820 return -ENOMEM; 2821 2822 if (ring_type == HNAE3_RING_TYPE_TX) { 2823 ring_data[q->tqp_index].ring = ring; 2824 ring_data[q->tqp_index].queue_index = q->tqp_index; 2825 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET; 2826 } else { 2827 ring_data[q->tqp_index + queue_num].ring = ring; 2828 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index; 2829 ring->io_base = q->io_base; 2830 } 2831 2832 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 2833 2834 ring->tqp = q; 2835 ring->desc = NULL; 2836 ring->desc_cb = NULL; 2837 ring->dev = priv->dev; 2838 ring->desc_dma_addr = 0; 2839 ring->buf_size = q->buf_size; 2840 ring->desc_num = q->desc_num; 2841 ring->next_to_use = 0; 2842 ring->next_to_clean = 0; 2843 2844 return 0; 2845 } 2846 2847 static int hns3_queue_to_ring(struct hnae3_queue *tqp, 2848 struct hns3_nic_priv *priv) 2849 { 2850 int ret; 2851 2852 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 2853 if (ret) 2854 return ret; 2855 2856 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 2857 if (ret) 2858 return ret; 2859 2860 return 0; 2861 } 2862 2863 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 2864 { 2865 struct hnae3_handle *h = priv->ae_handle; 2866 struct pci_dev *pdev = h->pdev; 2867 int i, ret; 2868 2869 priv->ring_data = devm_kzalloc(&pdev->dev, 2870 array3_size(h->kinfo.num_tqps, 2871 sizeof(*priv->ring_data), 2872 2), 2873 GFP_KERNEL); 2874 if (!priv->ring_data) 2875 return -ENOMEM; 2876 2877 for (i = 0; i < h->kinfo.num_tqps; i++) { 2878 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv); 2879 if (ret) 2880 goto err; 2881 } 2882 2883 return 0; 2884 err: 2885 devm_kfree(&pdev->dev, priv->ring_data); 2886 return ret; 2887 } 2888 2889 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 2890 { 2891 struct hnae3_handle *h = priv->ae_handle; 2892 int i; 2893 2894 for (i = 0; i < h->kinfo.num_tqps; i++) { 2895 devm_kfree(priv->dev, priv->ring_data[i].ring); 2896 devm_kfree(priv->dev, 2897 priv->ring_data[i + h->kinfo.num_tqps].ring); 2898 } 2899 devm_kfree(priv->dev, priv->ring_data); 2900 } 2901 2902 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 2903 { 2904 int ret; 2905 2906 if (ring->desc_num <= 0 || ring->buf_size <= 0) 2907 return -EINVAL; 2908 2909 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]), 2910 GFP_KERNEL); 2911 if (!ring->desc_cb) { 2912 ret = -ENOMEM; 2913 goto out; 2914 } 2915 2916 ret = hns3_alloc_desc(ring); 2917 if (ret) 2918 goto out_with_desc_cb; 2919 2920 if (!HNAE3_IS_TX_RING(ring)) { 2921 ret = hns3_alloc_ring_buffers(ring); 2922 if (ret) 2923 goto out_with_desc; 2924 } 2925 2926 return 0; 2927 2928 out_with_desc: 2929 hns3_free_desc(ring); 2930 out_with_desc_cb: 2931 kfree(ring->desc_cb); 2932 ring->desc_cb = NULL; 2933 out: 2934 return ret; 2935 } 2936 2937 static void hns3_fini_ring(struct hns3_enet_ring *ring) 2938 { 2939 hns3_free_desc(ring); 2940 kfree(ring->desc_cb); 2941 ring->desc_cb = NULL; 2942 ring->next_to_clean = 0; 2943 ring->next_to_use = 0; 2944 } 2945 2946 static int hns3_buf_size2type(u32 buf_size) 2947 { 2948 int bd_size_type; 2949 2950 switch (buf_size) { 2951 case 512: 2952 bd_size_type = HNS3_BD_SIZE_512_TYPE; 2953 break; 2954 case 1024: 2955 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 2956 break; 2957 case 2048: 2958 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 2959 break; 2960 case 4096: 2961 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 2962 break; 2963 default: 2964 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 2965 } 2966 2967 return bd_size_type; 2968 } 2969 2970 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 2971 { 2972 dma_addr_t dma = ring->desc_dma_addr; 2973 struct hnae3_queue *q = ring->tqp; 2974 2975 if (!HNAE3_IS_TX_RING(ring)) { 2976 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, 2977 (u32)dma); 2978 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 2979 (u32)((dma >> 31) >> 1)); 2980 2981 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 2982 hns3_buf_size2type(ring->buf_size)); 2983 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 2984 ring->desc_num / 8 - 1); 2985 2986 } else { 2987 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 2988 (u32)dma); 2989 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 2990 (u32)((dma >> 31) >> 1)); 2991 2992 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 2993 ring->desc_num / 8 - 1); 2994 } 2995 } 2996 2997 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 2998 { 2999 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3000 int i; 3001 3002 for (i = 0; i < HNAE3_MAX_TC; i++) { 3003 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i]; 3004 int j; 3005 3006 if (!tc_info->enable) 3007 continue; 3008 3009 for (j = 0; j < tc_info->tqp_count; j++) { 3010 struct hnae3_queue *q; 3011 3012 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp; 3013 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, 3014 tc_info->tc); 3015 } 3016 } 3017 } 3018 3019 int hns3_init_all_ring(struct hns3_nic_priv *priv) 3020 { 3021 struct hnae3_handle *h = priv->ae_handle; 3022 int ring_num = h->kinfo.num_tqps * 2; 3023 int i, j; 3024 int ret; 3025 3026 for (i = 0; i < ring_num; i++) { 3027 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring); 3028 if (ret) { 3029 dev_err(priv->dev, 3030 "Alloc ring memory fail! ret=%d\n", ret); 3031 goto out_when_alloc_ring_memory; 3032 } 3033 3034 u64_stats_init(&priv->ring_data[i].ring->syncp); 3035 } 3036 3037 return 0; 3038 3039 out_when_alloc_ring_memory: 3040 for (j = i - 1; j >= 0; j--) 3041 hns3_fini_ring(priv->ring_data[j].ring); 3042 3043 return -ENOMEM; 3044 } 3045 3046 int hns3_uninit_all_ring(struct hns3_nic_priv *priv) 3047 { 3048 struct hnae3_handle *h = priv->ae_handle; 3049 int i; 3050 3051 for (i = 0; i < h->kinfo.num_tqps; i++) { 3052 if (h->ae_algo->ops->reset_queue) 3053 h->ae_algo->ops->reset_queue(h, i); 3054 3055 hns3_fini_ring(priv->ring_data[i].ring); 3056 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring); 3057 } 3058 return 0; 3059 } 3060 3061 /* Set mac addr if it is configured. or leave it to the AE driver */ 3062 static void hns3_init_mac_addr(struct net_device *netdev, bool init) 3063 { 3064 struct hns3_nic_priv *priv = netdev_priv(netdev); 3065 struct hnae3_handle *h = priv->ae_handle; 3066 u8 mac_addr_temp[ETH_ALEN]; 3067 3068 if (h->ae_algo->ops->get_mac_addr && init) { 3069 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 3070 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 3071 } 3072 3073 /* Check if the MAC address is valid, if not get a random one */ 3074 if (!is_valid_ether_addr(netdev->dev_addr)) { 3075 eth_hw_addr_random(netdev); 3076 dev_warn(priv->dev, "using random MAC address %pM\n", 3077 netdev->dev_addr); 3078 } 3079 3080 if (h->ae_algo->ops->set_mac_addr) 3081 h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 3082 3083 } 3084 3085 static void hns3_uninit_mac_addr(struct net_device *netdev) 3086 { 3087 struct hns3_nic_priv *priv = netdev_priv(netdev); 3088 struct hnae3_handle *h = priv->ae_handle; 3089 3090 if (h->ae_algo->ops->rm_uc_addr) 3091 h->ae_algo->ops->rm_uc_addr(h, netdev->dev_addr); 3092 } 3093 3094 static void hns3_nic_set_priv_ops(struct net_device *netdev) 3095 { 3096 struct hns3_nic_priv *priv = netdev_priv(netdev); 3097 3098 if ((netdev->features & NETIF_F_TSO) || 3099 (netdev->features & NETIF_F_TSO6)) { 3100 priv->ops.fill_desc = hns3_fill_desc_tso; 3101 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 3102 } else { 3103 priv->ops.fill_desc = hns3_fill_desc; 3104 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 3105 } 3106 } 3107 3108 static int hns3_client_init(struct hnae3_handle *handle) 3109 { 3110 struct pci_dev *pdev = handle->pdev; 3111 struct hns3_nic_priv *priv; 3112 struct net_device *netdev; 3113 int ret; 3114 3115 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), 3116 hns3_get_max_available_channels(handle)); 3117 if (!netdev) 3118 return -ENOMEM; 3119 3120 priv = netdev_priv(netdev); 3121 priv->dev = &pdev->dev; 3122 priv->netdev = netdev; 3123 priv->ae_handle = handle; 3124 priv->ae_handle->last_reset_time = jiffies; 3125 priv->tx_timeout_count = 0; 3126 3127 handle->kinfo.netdev = netdev; 3128 handle->priv = (void *)priv; 3129 3130 hns3_init_mac_addr(netdev, true); 3131 3132 hns3_set_default_feature(netdev); 3133 3134 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 3135 netdev->priv_flags |= IFF_UNICAST_FLT; 3136 netdev->netdev_ops = &hns3_nic_netdev_ops; 3137 SET_NETDEV_DEV(netdev, &pdev->dev); 3138 hns3_ethtool_set_ops(netdev); 3139 hns3_nic_set_priv_ops(netdev); 3140 3141 /* Carrier off reporting is important to ethtool even BEFORE open */ 3142 netif_carrier_off(netdev); 3143 3144 if (handle->flags & HNAE3_SUPPORT_VF) 3145 handle->reset_level = HNAE3_VF_RESET; 3146 else 3147 handle->reset_level = HNAE3_FUNC_RESET; 3148 3149 ret = hns3_get_ring_config(priv); 3150 if (ret) { 3151 ret = -ENOMEM; 3152 goto out_get_ring_cfg; 3153 } 3154 3155 ret = hns3_nic_alloc_vector_data(priv); 3156 if (ret) { 3157 ret = -ENOMEM; 3158 goto out_alloc_vector_data; 3159 } 3160 3161 ret = hns3_nic_init_vector_data(priv); 3162 if (ret) { 3163 ret = -ENOMEM; 3164 goto out_init_vector_data; 3165 } 3166 3167 ret = hns3_init_all_ring(priv); 3168 if (ret) { 3169 ret = -ENOMEM; 3170 goto out_init_ring_data; 3171 } 3172 3173 ret = register_netdev(netdev); 3174 if (ret) { 3175 dev_err(priv->dev, "probe register netdev fail!\n"); 3176 goto out_reg_netdev_fail; 3177 } 3178 3179 hns3_dcbnl_setup(handle); 3180 3181 /* MTU range: (ETH_MIN_MTU(kernel default) - 9706) */ 3182 netdev->max_mtu = HNS3_MAX_MTU - (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); 3183 3184 return ret; 3185 3186 out_reg_netdev_fail: 3187 out_init_ring_data: 3188 (void)hns3_nic_uninit_vector_data(priv); 3189 out_init_vector_data: 3190 hns3_nic_dealloc_vector_data(priv); 3191 out_alloc_vector_data: 3192 priv->ring_data = NULL; 3193 out_get_ring_cfg: 3194 priv->ae_handle = NULL; 3195 free_netdev(netdev); 3196 return ret; 3197 } 3198 3199 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 3200 { 3201 struct net_device *netdev = handle->kinfo.netdev; 3202 struct hns3_nic_priv *priv = netdev_priv(netdev); 3203 int ret; 3204 3205 if (netdev->reg_state != NETREG_UNINITIALIZED) 3206 unregister_netdev(netdev); 3207 3208 hns3_force_clear_all_rx_ring(handle); 3209 3210 ret = hns3_nic_uninit_vector_data(priv); 3211 if (ret) 3212 netdev_err(netdev, "uninit vector error\n"); 3213 3214 ret = hns3_nic_dealloc_vector_data(priv); 3215 if (ret) 3216 netdev_err(netdev, "dealloc vector error\n"); 3217 3218 ret = hns3_uninit_all_ring(priv); 3219 if (ret) 3220 netdev_err(netdev, "uninit ring error\n"); 3221 3222 hns3_put_ring_config(priv); 3223 3224 priv->ring_data = NULL; 3225 3226 hns3_uninit_mac_addr(netdev); 3227 3228 free_netdev(netdev); 3229 } 3230 3231 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 3232 { 3233 struct net_device *netdev = handle->kinfo.netdev; 3234 3235 if (!netdev) 3236 return; 3237 3238 if (linkup) { 3239 netif_carrier_on(netdev); 3240 netif_tx_wake_all_queues(netdev); 3241 netdev_info(netdev, "link up\n"); 3242 } else { 3243 netif_carrier_off(netdev); 3244 netif_tx_stop_all_queues(netdev); 3245 netdev_info(netdev, "link down\n"); 3246 } 3247 } 3248 3249 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc) 3250 { 3251 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3252 struct net_device *ndev = kinfo->netdev; 3253 bool if_running; 3254 int ret; 3255 3256 if (tc > HNAE3_MAX_TC) 3257 return -EINVAL; 3258 3259 if (!ndev) 3260 return -ENODEV; 3261 3262 if_running = netif_running(ndev); 3263 3264 if (if_running) { 3265 (void)hns3_nic_net_stop(ndev); 3266 msleep(100); 3267 } 3268 3269 ret = (kinfo->dcb_ops && kinfo->dcb_ops->map_update) ? 3270 kinfo->dcb_ops->map_update(handle) : -EOPNOTSUPP; 3271 if (ret) 3272 goto err_out; 3273 3274 ret = hns3_nic_set_real_num_queue(ndev); 3275 3276 err_out: 3277 if (if_running) 3278 (void)hns3_nic_net_open(ndev); 3279 3280 return ret; 3281 } 3282 3283 static void hns3_recover_hw_addr(struct net_device *ndev) 3284 { 3285 struct netdev_hw_addr_list *list; 3286 struct netdev_hw_addr *ha, *tmp; 3287 3288 /* go through and sync uc_addr entries to the device */ 3289 list = &ndev->uc; 3290 list_for_each_entry_safe(ha, tmp, &list->list, list) 3291 hns3_nic_uc_sync(ndev, ha->addr); 3292 3293 /* go through and sync mc_addr entries to the device */ 3294 list = &ndev->mc; 3295 list_for_each_entry_safe(ha, tmp, &list->list, list) 3296 hns3_nic_mc_sync(ndev, ha->addr); 3297 } 3298 3299 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 3300 { 3301 while (ring->next_to_clean != ring->next_to_use) { 3302 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 3303 hns3_free_buffer_detach(ring, ring->next_to_clean); 3304 ring_ptr_move_fw(ring, next_to_clean); 3305 } 3306 } 3307 3308 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 3309 { 3310 struct hns3_desc_cb res_cbs; 3311 int ret; 3312 3313 while (ring->next_to_use != ring->next_to_clean) { 3314 /* When a buffer is not reused, it's memory has been 3315 * freed in hns3_handle_rx_bd or will be freed by 3316 * stack, so we need to replace the buffer here. 3317 */ 3318 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3319 ret = hns3_reserve_buffer_map(ring, &res_cbs); 3320 if (ret) { 3321 u64_stats_update_begin(&ring->syncp); 3322 ring->stats.sw_err_cnt++; 3323 u64_stats_update_end(&ring->syncp); 3324 /* if alloc new buffer fail, exit directly 3325 * and reclear in up flow. 3326 */ 3327 netdev_warn(ring->tqp->handle->kinfo.netdev, 3328 "reserve buffer map failed, ret = %d\n", 3329 ret); 3330 return ret; 3331 } 3332 hns3_replace_buffer(ring, ring->next_to_use, 3333 &res_cbs); 3334 } 3335 ring_ptr_move_fw(ring, next_to_use); 3336 } 3337 3338 return 0; 3339 } 3340 3341 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 3342 { 3343 while (ring->next_to_use != ring->next_to_clean) { 3344 /* When a buffer is not reused, it's memory has been 3345 * freed in hns3_handle_rx_bd or will be freed by 3346 * stack, so only need to unmap the buffer here. 3347 */ 3348 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3349 hns3_unmap_buffer(ring, 3350 &ring->desc_cb[ring->next_to_use]); 3351 ring->desc_cb[ring->next_to_use].dma = 0; 3352 } 3353 3354 ring_ptr_move_fw(ring, next_to_use); 3355 } 3356 } 3357 3358 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h) 3359 { 3360 struct net_device *ndev = h->kinfo.netdev; 3361 struct hns3_nic_priv *priv = netdev_priv(ndev); 3362 struct hns3_enet_ring *ring; 3363 u32 i; 3364 3365 for (i = 0; i < h->kinfo.num_tqps; i++) { 3366 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3367 hns3_force_clear_rx_ring(ring); 3368 } 3369 } 3370 3371 static void hns3_clear_all_ring(struct hnae3_handle *h) 3372 { 3373 struct net_device *ndev = h->kinfo.netdev; 3374 struct hns3_nic_priv *priv = netdev_priv(ndev); 3375 u32 i; 3376 3377 for (i = 0; i < h->kinfo.num_tqps; i++) { 3378 struct netdev_queue *dev_queue; 3379 struct hns3_enet_ring *ring; 3380 3381 ring = priv->ring_data[i].ring; 3382 hns3_clear_tx_ring(ring); 3383 dev_queue = netdev_get_tx_queue(ndev, 3384 priv->ring_data[i].queue_index); 3385 netdev_tx_reset_queue(dev_queue); 3386 3387 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3388 /* Continue to clear other rings even if clearing some 3389 * rings failed. 3390 */ 3391 hns3_clear_rx_ring(ring); 3392 } 3393 } 3394 3395 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 3396 { 3397 struct net_device *ndev = h->kinfo.netdev; 3398 struct hns3_nic_priv *priv = netdev_priv(ndev); 3399 struct hns3_enet_ring *rx_ring; 3400 int i, j; 3401 int ret; 3402 3403 for (i = 0; i < h->kinfo.num_tqps; i++) { 3404 h->ae_algo->ops->reset_queue(h, i); 3405 hns3_init_ring_hw(priv->ring_data[i].ring); 3406 3407 /* We need to clear tx ring here because self test will 3408 * use the ring and will not run down before up 3409 */ 3410 hns3_clear_tx_ring(priv->ring_data[i].ring); 3411 priv->ring_data[i].ring->next_to_clean = 0; 3412 priv->ring_data[i].ring->next_to_use = 0; 3413 3414 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3415 hns3_init_ring_hw(rx_ring); 3416 ret = hns3_clear_rx_ring(rx_ring); 3417 if (ret) 3418 return ret; 3419 3420 /* We can not know the hardware head and tail when this 3421 * function is called in reset flow, so we reuse all desc. 3422 */ 3423 for (j = 0; j < rx_ring->desc_num; j++) 3424 hns3_reuse_buffer(rx_ring, j); 3425 3426 rx_ring->next_to_clean = 0; 3427 rx_ring->next_to_use = 0; 3428 } 3429 3430 hns3_init_tx_ring_tc(priv); 3431 3432 return 0; 3433 } 3434 3435 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 3436 { 3437 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3438 struct net_device *ndev = kinfo->netdev; 3439 3440 if (!netif_running(ndev)) 3441 return 0; 3442 3443 return hns3_nic_net_stop(ndev); 3444 } 3445 3446 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 3447 { 3448 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3449 int ret = 0; 3450 3451 if (netif_running(kinfo->netdev)) { 3452 ret = hns3_nic_net_up(kinfo->netdev); 3453 if (ret) { 3454 netdev_err(kinfo->netdev, 3455 "hns net up fail, ret=%d!\n", ret); 3456 return ret; 3457 } 3458 handle->last_reset_time = jiffies; 3459 } 3460 3461 return ret; 3462 } 3463 3464 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 3465 { 3466 struct net_device *netdev = handle->kinfo.netdev; 3467 struct hns3_nic_priv *priv = netdev_priv(netdev); 3468 int ret; 3469 3470 hns3_init_mac_addr(netdev, false); 3471 hns3_nic_set_rx_mode(netdev); 3472 hns3_recover_hw_addr(netdev); 3473 3474 /* Hardware table is only clear when pf resets */ 3475 if (!(handle->flags & HNAE3_SUPPORT_VF)) 3476 hns3_restore_vlan(netdev); 3477 3478 /* Carrier off reporting is important to ethtool even BEFORE open */ 3479 netif_carrier_off(netdev); 3480 3481 ret = hns3_nic_init_vector_data(priv); 3482 if (ret) 3483 return ret; 3484 3485 ret = hns3_init_all_ring(priv); 3486 if (ret) { 3487 hns3_nic_uninit_vector_data(priv); 3488 priv->ring_data = NULL; 3489 } 3490 3491 return ret; 3492 } 3493 3494 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 3495 { 3496 struct net_device *netdev = handle->kinfo.netdev; 3497 struct hns3_nic_priv *priv = netdev_priv(netdev); 3498 int ret; 3499 3500 hns3_force_clear_all_rx_ring(handle); 3501 3502 ret = hns3_nic_uninit_vector_data(priv); 3503 if (ret) { 3504 netdev_err(netdev, "uninit vector error\n"); 3505 return ret; 3506 } 3507 3508 ret = hns3_uninit_all_ring(priv); 3509 if (ret) 3510 netdev_err(netdev, "uninit ring error\n"); 3511 3512 hns3_uninit_mac_addr(netdev); 3513 3514 return ret; 3515 } 3516 3517 static int hns3_reset_notify(struct hnae3_handle *handle, 3518 enum hnae3_reset_notify_type type) 3519 { 3520 int ret = 0; 3521 3522 switch (type) { 3523 case HNAE3_UP_CLIENT: 3524 ret = hns3_reset_notify_up_enet(handle); 3525 break; 3526 case HNAE3_DOWN_CLIENT: 3527 ret = hns3_reset_notify_down_enet(handle); 3528 break; 3529 case HNAE3_INIT_CLIENT: 3530 ret = hns3_reset_notify_init_enet(handle); 3531 break; 3532 case HNAE3_UNINIT_CLIENT: 3533 ret = hns3_reset_notify_uninit_enet(handle); 3534 break; 3535 default: 3536 break; 3537 } 3538 3539 return ret; 3540 } 3541 3542 static void hns3_restore_coal(struct hns3_nic_priv *priv, 3543 struct hns3_enet_coalesce *tx, 3544 struct hns3_enet_coalesce *rx) 3545 { 3546 u16 vector_num = priv->vector_num; 3547 int i; 3548 3549 for (i = 0; i < vector_num; i++) { 3550 memcpy(&priv->tqp_vector[i].tx_group.coal, tx, 3551 sizeof(struct hns3_enet_coalesce)); 3552 memcpy(&priv->tqp_vector[i].rx_group.coal, rx, 3553 sizeof(struct hns3_enet_coalesce)); 3554 } 3555 } 3556 3557 static int hns3_modify_tqp_num(struct net_device *netdev, u16 new_tqp_num, 3558 struct hns3_enet_coalesce *tx, 3559 struct hns3_enet_coalesce *rx) 3560 { 3561 struct hns3_nic_priv *priv = netdev_priv(netdev); 3562 struct hnae3_handle *h = hns3_get_handle(netdev); 3563 int ret; 3564 3565 ret = h->ae_algo->ops->set_channels(h, new_tqp_num); 3566 if (ret) 3567 return ret; 3568 3569 ret = hns3_get_ring_config(priv); 3570 if (ret) 3571 return ret; 3572 3573 ret = hns3_nic_alloc_vector_data(priv); 3574 if (ret) 3575 goto err_alloc_vector; 3576 3577 hns3_restore_coal(priv, tx, rx); 3578 3579 ret = hns3_nic_init_vector_data(priv); 3580 if (ret) 3581 goto err_uninit_vector; 3582 3583 ret = hns3_init_all_ring(priv); 3584 if (ret) 3585 goto err_put_ring; 3586 3587 return 0; 3588 3589 err_put_ring: 3590 hns3_put_ring_config(priv); 3591 err_uninit_vector: 3592 hns3_nic_uninit_vector_data(priv); 3593 err_alloc_vector: 3594 hns3_nic_dealloc_vector_data(priv); 3595 return ret; 3596 } 3597 3598 static int hns3_adjust_tqps_num(u8 num_tc, u32 new_tqp_num) 3599 { 3600 return (new_tqp_num / num_tc) * num_tc; 3601 } 3602 3603 int hns3_set_channels(struct net_device *netdev, 3604 struct ethtool_channels *ch) 3605 { 3606 struct hns3_nic_priv *priv = netdev_priv(netdev); 3607 struct hnae3_handle *h = hns3_get_handle(netdev); 3608 struct hnae3_knic_private_info *kinfo = &h->kinfo; 3609 struct hns3_enet_coalesce tx_coal, rx_coal; 3610 bool if_running = netif_running(netdev); 3611 u32 new_tqp_num = ch->combined_count; 3612 u16 org_tqp_num; 3613 int ret; 3614 3615 if (ch->rx_count || ch->tx_count) 3616 return -EINVAL; 3617 3618 if (new_tqp_num > hns3_get_max_available_channels(h) || 3619 new_tqp_num < kinfo->num_tc) { 3620 dev_err(&netdev->dev, 3621 "Change tqps fail, the tqp range is from %d to %d", 3622 kinfo->num_tc, 3623 hns3_get_max_available_channels(h)); 3624 return -EINVAL; 3625 } 3626 3627 new_tqp_num = hns3_adjust_tqps_num(kinfo->num_tc, new_tqp_num); 3628 if (kinfo->num_tqps == new_tqp_num) 3629 return 0; 3630 3631 if (if_running) 3632 hns3_nic_net_stop(netdev); 3633 3634 ret = hns3_nic_uninit_vector_data(priv); 3635 if (ret) { 3636 dev_err(&netdev->dev, 3637 "Unbind vector with tqp fail, nothing is changed"); 3638 goto open_netdev; 3639 } 3640 3641 /* Changing the tqp num may also change the vector num, 3642 * ethtool only support setting and querying one coal 3643 * configuation for now, so save the vector 0' coal 3644 * configuation here in order to restore it. 3645 */ 3646 memcpy(&tx_coal, &priv->tqp_vector[0].tx_group.coal, 3647 sizeof(struct hns3_enet_coalesce)); 3648 memcpy(&rx_coal, &priv->tqp_vector[0].rx_group.coal, 3649 sizeof(struct hns3_enet_coalesce)); 3650 3651 hns3_nic_dealloc_vector_data(priv); 3652 3653 hns3_uninit_all_ring(priv); 3654 hns3_put_ring_config(priv); 3655 3656 org_tqp_num = h->kinfo.num_tqps; 3657 ret = hns3_modify_tqp_num(netdev, new_tqp_num, &tx_coal, &rx_coal); 3658 if (ret) { 3659 ret = hns3_modify_tqp_num(netdev, org_tqp_num, 3660 &tx_coal, &rx_coal); 3661 if (ret) { 3662 /* If revert to old tqp failed, fatal error occurred */ 3663 dev_err(&netdev->dev, 3664 "Revert to old tqp num fail, ret=%d", ret); 3665 return ret; 3666 } 3667 dev_info(&netdev->dev, 3668 "Change tqp num fail, Revert to old tqp num"); 3669 } 3670 3671 open_netdev: 3672 if (if_running) 3673 hns3_nic_net_open(netdev); 3674 3675 return ret; 3676 } 3677 3678 static const struct hnae3_client_ops client_ops = { 3679 .init_instance = hns3_client_init, 3680 .uninit_instance = hns3_client_uninit, 3681 .link_status_change = hns3_link_status_change, 3682 .setup_tc = hns3_client_setup_tc, 3683 .reset_notify = hns3_reset_notify, 3684 }; 3685 3686 /* hns3_init_module - Driver registration routine 3687 * hns3_init_module is the first routine called when the driver is 3688 * loaded. All it does is register with the PCI subsystem. 3689 */ 3690 static int __init hns3_init_module(void) 3691 { 3692 int ret; 3693 3694 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 3695 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 3696 3697 client.type = HNAE3_CLIENT_KNIC; 3698 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s", 3699 hns3_driver_name); 3700 3701 client.ops = &client_ops; 3702 3703 INIT_LIST_HEAD(&client.node); 3704 3705 ret = hnae3_register_client(&client); 3706 if (ret) 3707 return ret; 3708 3709 ret = pci_register_driver(&hns3_driver); 3710 if (ret) 3711 hnae3_unregister_client(&client); 3712 3713 return ret; 3714 } 3715 module_init(hns3_init_module); 3716 3717 /* hns3_exit_module - Driver exit cleanup routine 3718 * hns3_exit_module is called just before the driver is removed 3719 * from memory. 3720 */ 3721 static void __exit hns3_exit_module(void) 3722 { 3723 pci_unregister_driver(&hns3_driver); 3724 hnae3_unregister_client(&client); 3725 } 3726 module_exit(hns3_exit_module); 3727 3728 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 3729 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3730 MODULE_LICENSE("GPL"); 3731 MODULE_ALIAS("pci:hns-nic"); 3732 MODULE_VERSION(HNS3_MOD_VERSION); 3733