1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #include <linux/if_vlan.h> 8 #include <linux/ip.h> 9 #include <linux/ipv6.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/skbuff.h> 13 #include <linux/sctp.h> 14 #include <linux/vermagic.h> 15 #include <net/gre.h> 16 #include <net/pkt_cls.h> 17 #include <net/vxlan.h> 18 19 #include "hnae3.h" 20 #include "hns3_enet.h" 21 22 static void hns3_clear_all_ring(struct hnae3_handle *h); 23 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h); 24 25 static const char hns3_driver_name[] = "hns3"; 26 const char hns3_driver_version[] = VERMAGIC_STRING; 27 static const char hns3_driver_string[] = 28 "Hisilicon Ethernet Network Driver for Hip08 Family"; 29 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 30 static struct hnae3_client client; 31 32 /* hns3_pci_tbl - PCI Device ID Table 33 * 34 * Last entry must be all 0s 35 * 36 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 37 * Class, Class Mask, private data (not used) } 38 */ 39 static const struct pci_device_id hns3_pci_tbl[] = { 40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 43 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 45 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 47 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 49 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 51 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 52 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 54 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 55 /* required last entry */ 56 {0, } 57 }; 58 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 59 60 static irqreturn_t hns3_irq_handle(int irq, void *vector) 61 { 62 struct hns3_enet_tqp_vector *tqp_vector = vector; 63 64 napi_schedule(&tqp_vector->napi); 65 66 return IRQ_HANDLED; 67 } 68 69 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 70 { 71 struct hns3_enet_tqp_vector *tqp_vectors; 72 unsigned int i; 73 74 for (i = 0; i < priv->vector_num; i++) { 75 tqp_vectors = &priv->tqp_vector[i]; 76 77 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 78 continue; 79 80 /* release the irq resource */ 81 free_irq(tqp_vectors->vector_irq, tqp_vectors); 82 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 83 } 84 } 85 86 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 87 { 88 struct hns3_enet_tqp_vector *tqp_vectors; 89 int txrx_int_idx = 0; 90 int rx_int_idx = 0; 91 int tx_int_idx = 0; 92 unsigned int i; 93 int ret; 94 95 for (i = 0; i < priv->vector_num; i++) { 96 tqp_vectors = &priv->tqp_vector[i]; 97 98 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 99 continue; 100 101 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 102 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 103 "%s-%s-%d", priv->netdev->name, "TxRx", 104 txrx_int_idx++); 105 txrx_int_idx++; 106 } else if (tqp_vectors->rx_group.ring) { 107 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 108 "%s-%s-%d", priv->netdev->name, "Rx", 109 rx_int_idx++); 110 } else if (tqp_vectors->tx_group.ring) { 111 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 112 "%s-%s-%d", priv->netdev->name, "Tx", 113 tx_int_idx++); 114 } else { 115 /* Skip this unused q_vector */ 116 continue; 117 } 118 119 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 120 121 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 122 tqp_vectors->name, 123 tqp_vectors); 124 if (ret) { 125 netdev_err(priv->netdev, "request irq(%d) fail\n", 126 tqp_vectors->vector_irq); 127 return ret; 128 } 129 130 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 131 } 132 133 return 0; 134 } 135 136 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 137 u32 mask_en) 138 { 139 writel(mask_en, tqp_vector->mask_addr); 140 } 141 142 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 143 { 144 napi_enable(&tqp_vector->napi); 145 146 /* enable vector */ 147 hns3_mask_vector_irq(tqp_vector, 1); 148 } 149 150 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 151 { 152 /* disable vector */ 153 hns3_mask_vector_irq(tqp_vector, 0); 154 155 disable_irq(tqp_vector->vector_irq); 156 napi_disable(&tqp_vector->napi); 157 } 158 159 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 160 u32 rl_value) 161 { 162 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 163 164 /* this defines the configuration for RL (Interrupt Rate Limiter). 165 * Rl defines rate of interrupts i.e. number of interrupts-per-second 166 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 167 */ 168 169 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable && 170 !tqp_vector->rx_group.coal.gl_adapt_enable) 171 /* According to the hardware, the range of rl_reg is 172 * 0-59 and the unit is 4. 173 */ 174 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 175 176 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 177 } 178 179 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 180 u32 gl_value) 181 { 182 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value); 183 184 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 185 } 186 187 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 188 u32 gl_value) 189 { 190 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value); 191 192 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 193 } 194 195 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector, 196 struct hns3_nic_priv *priv) 197 { 198 struct hnae3_handle *h = priv->ae_handle; 199 200 /* initialize the configuration for interrupt coalescing. 201 * 1. GL (Interrupt Gap Limiter) 202 * 2. RL (Interrupt Rate Limiter) 203 */ 204 205 /* Default: enable interrupt coalescing self-adaptive and GL */ 206 tqp_vector->tx_group.coal.gl_adapt_enable = 1; 207 tqp_vector->rx_group.coal.gl_adapt_enable = 1; 208 209 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K; 210 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K; 211 212 /* Default: disable RL */ 213 h->kinfo.int_rl_setting = 0; 214 215 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START; 216 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW; 217 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW; 218 } 219 220 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 221 struct hns3_nic_priv *priv) 222 { 223 struct hnae3_handle *h = priv->ae_handle; 224 225 hns3_set_vector_coalesce_tx_gl(tqp_vector, 226 tqp_vector->tx_group.coal.int_gl); 227 hns3_set_vector_coalesce_rx_gl(tqp_vector, 228 tqp_vector->rx_group.coal.int_gl); 229 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 230 } 231 232 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 233 { 234 struct hnae3_handle *h = hns3_get_handle(netdev); 235 struct hnae3_knic_private_info *kinfo = &h->kinfo; 236 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc; 237 int i, ret; 238 239 if (kinfo->num_tc <= 1) { 240 netdev_reset_tc(netdev); 241 } else { 242 ret = netdev_set_num_tc(netdev, kinfo->num_tc); 243 if (ret) { 244 netdev_err(netdev, 245 "netdev_set_num_tc fail, ret=%d!\n", ret); 246 return ret; 247 } 248 249 for (i = 0; i < HNAE3_MAX_TC; i++) { 250 if (!kinfo->tc_info[i].enable) 251 continue; 252 253 netdev_set_tc_queue(netdev, 254 kinfo->tc_info[i].tc, 255 kinfo->tc_info[i].tqp_count, 256 kinfo->tc_info[i].tqp_offset); 257 } 258 } 259 260 ret = netif_set_real_num_tx_queues(netdev, queue_size); 261 if (ret) { 262 netdev_err(netdev, 263 "netif_set_real_num_tx_queues fail, ret=%d!\n", 264 ret); 265 return ret; 266 } 267 268 ret = netif_set_real_num_rx_queues(netdev, queue_size); 269 if (ret) { 270 netdev_err(netdev, 271 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 272 return ret; 273 } 274 275 return 0; 276 } 277 278 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 279 { 280 u16 free_tqps, max_rss_size, max_tqps; 281 282 h->ae_algo->ops->get_tqps_and_rss_info(h, &free_tqps, &max_rss_size); 283 max_tqps = h->kinfo.num_tc * max_rss_size; 284 285 return min_t(u16, max_tqps, (free_tqps + h->kinfo.num_tqps)); 286 } 287 288 static int hns3_nic_net_up(struct net_device *netdev) 289 { 290 struct hns3_nic_priv *priv = netdev_priv(netdev); 291 struct hnae3_handle *h = priv->ae_handle; 292 int i, j; 293 int ret; 294 295 ret = hns3_nic_reset_all_ring(h); 296 if (ret) 297 return ret; 298 299 /* get irq resource for all vectors */ 300 ret = hns3_nic_init_irq(priv); 301 if (ret) { 302 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret); 303 return ret; 304 } 305 306 /* enable the vectors */ 307 for (i = 0; i < priv->vector_num; i++) 308 hns3_vector_enable(&priv->tqp_vector[i]); 309 310 /* start the ae_dev */ 311 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 312 if (ret) 313 goto out_start_err; 314 315 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 316 317 return 0; 318 319 out_start_err: 320 for (j = i - 1; j >= 0; j--) 321 hns3_vector_disable(&priv->tqp_vector[j]); 322 323 hns3_nic_uninit_irq(priv); 324 325 return ret; 326 } 327 328 static int hns3_nic_net_open(struct net_device *netdev) 329 { 330 struct hns3_nic_priv *priv = netdev_priv(netdev); 331 struct hnae3_handle *h = hns3_get_handle(netdev); 332 struct hnae3_knic_private_info *kinfo; 333 int i, ret; 334 335 netif_carrier_off(netdev); 336 337 ret = hns3_nic_set_real_num_queue(netdev); 338 if (ret) 339 return ret; 340 341 ret = hns3_nic_net_up(netdev); 342 if (ret) { 343 netdev_err(netdev, 344 "hns net up fail, ret=%d!\n", ret); 345 return ret; 346 } 347 348 kinfo = &h->kinfo; 349 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { 350 netdev_set_prio_tc_map(netdev, i, 351 kinfo->prio_tc[i]); 352 } 353 354 priv->ae_handle->last_reset_time = jiffies; 355 return 0; 356 } 357 358 static void hns3_nic_net_down(struct net_device *netdev) 359 { 360 struct hns3_nic_priv *priv = netdev_priv(netdev); 361 const struct hnae3_ae_ops *ops; 362 int i; 363 364 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 365 return; 366 367 /* disable vectors */ 368 for (i = 0; i < priv->vector_num; i++) 369 hns3_vector_disable(&priv->tqp_vector[i]); 370 371 /* stop ae_dev */ 372 ops = priv->ae_handle->ae_algo->ops; 373 if (ops->stop) 374 ops->stop(priv->ae_handle); 375 376 /* free irq resources */ 377 hns3_nic_uninit_irq(priv); 378 379 hns3_clear_all_ring(priv->ae_handle); 380 } 381 382 static int hns3_nic_net_stop(struct net_device *netdev) 383 { 384 netif_tx_stop_all_queues(netdev); 385 netif_carrier_off(netdev); 386 387 hns3_nic_net_down(netdev); 388 389 return 0; 390 } 391 392 static int hns3_nic_uc_sync(struct net_device *netdev, 393 const unsigned char *addr) 394 { 395 struct hnae3_handle *h = hns3_get_handle(netdev); 396 397 if (h->ae_algo->ops->add_uc_addr) 398 return h->ae_algo->ops->add_uc_addr(h, addr); 399 400 return 0; 401 } 402 403 static int hns3_nic_uc_unsync(struct net_device *netdev, 404 const unsigned char *addr) 405 { 406 struct hnae3_handle *h = hns3_get_handle(netdev); 407 408 if (h->ae_algo->ops->rm_uc_addr) 409 return h->ae_algo->ops->rm_uc_addr(h, addr); 410 411 return 0; 412 } 413 414 static int hns3_nic_mc_sync(struct net_device *netdev, 415 const unsigned char *addr) 416 { 417 struct hnae3_handle *h = hns3_get_handle(netdev); 418 419 if (h->ae_algo->ops->add_mc_addr) 420 return h->ae_algo->ops->add_mc_addr(h, addr); 421 422 return 0; 423 } 424 425 static int hns3_nic_mc_unsync(struct net_device *netdev, 426 const unsigned char *addr) 427 { 428 struct hnae3_handle *h = hns3_get_handle(netdev); 429 430 if (h->ae_algo->ops->rm_mc_addr) 431 return h->ae_algo->ops->rm_mc_addr(h, addr); 432 433 return 0; 434 } 435 436 static void hns3_nic_set_rx_mode(struct net_device *netdev) 437 { 438 struct hnae3_handle *h = hns3_get_handle(netdev); 439 440 if (h->ae_algo->ops->set_promisc_mode) { 441 if (netdev->flags & IFF_PROMISC) 442 h->ae_algo->ops->set_promisc_mode(h, true, true); 443 else if (netdev->flags & IFF_ALLMULTI) 444 h->ae_algo->ops->set_promisc_mode(h, false, true); 445 else 446 h->ae_algo->ops->set_promisc_mode(h, false, false); 447 } 448 if (__dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync)) 449 netdev_err(netdev, "sync uc address fail\n"); 450 if (netdev->flags & IFF_MULTICAST) { 451 if (__dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync)) 452 netdev_err(netdev, "sync mc address fail\n"); 453 454 if (h->ae_algo->ops->update_mta_status) 455 h->ae_algo->ops->update_mta_status(h); 456 } 457 } 458 459 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen, 460 u16 *mss, u32 *type_cs_vlan_tso) 461 { 462 u32 l4_offset, hdr_len; 463 union l3_hdr_info l3; 464 union l4_hdr_info l4; 465 u32 l4_paylen; 466 int ret; 467 468 if (!skb_is_gso(skb)) 469 return 0; 470 471 ret = skb_cow_head(skb, 0); 472 if (ret) 473 return ret; 474 475 l3.hdr = skb_network_header(skb); 476 l4.hdr = skb_transport_header(skb); 477 478 /* Software should clear the IPv4's checksum field when tso is 479 * needed. 480 */ 481 if (l3.v4->version == 4) 482 l3.v4->check = 0; 483 484 /* tunnel packet.*/ 485 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 486 SKB_GSO_GRE_CSUM | 487 SKB_GSO_UDP_TUNNEL | 488 SKB_GSO_UDP_TUNNEL_CSUM)) { 489 if ((!(skb_shinfo(skb)->gso_type & 490 SKB_GSO_PARTIAL)) && 491 (skb_shinfo(skb)->gso_type & 492 SKB_GSO_UDP_TUNNEL_CSUM)) { 493 /* Software should clear the udp's checksum 494 * field when tso is needed. 495 */ 496 l4.udp->check = 0; 497 } 498 /* reset l3&l4 pointers from outer to inner headers */ 499 l3.hdr = skb_inner_network_header(skb); 500 l4.hdr = skb_inner_transport_header(skb); 501 502 /* Software should clear the IPv4's checksum field when 503 * tso is needed. 504 */ 505 if (l3.v4->version == 4) 506 l3.v4->check = 0; 507 } 508 509 /* normal or tunnel packet*/ 510 l4_offset = l4.hdr - skb->data; 511 hdr_len = (l4.tcp->doff * 4) + l4_offset; 512 513 /* remove payload length from inner pseudo checksum when tso*/ 514 l4_paylen = skb->len - l4_offset; 515 csum_replace_by_diff(&l4.tcp->check, 516 (__force __wsum)htonl(l4_paylen)); 517 518 /* find the txbd field values */ 519 *paylen = skb->len - hdr_len; 520 hnae3_set_bit(*type_cs_vlan_tso, 521 HNS3_TXD_TSO_B, 1); 522 523 /* get MSS for TSO */ 524 *mss = skb_shinfo(skb)->gso_size; 525 526 return 0; 527 } 528 529 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 530 u8 *il4_proto) 531 { 532 union { 533 struct iphdr *v4; 534 struct ipv6hdr *v6; 535 unsigned char *hdr; 536 } l3; 537 unsigned char *l4_hdr; 538 unsigned char *exthdr; 539 u8 l4_proto_tmp; 540 __be16 frag_off; 541 542 /* find outer header point */ 543 l3.hdr = skb_network_header(skb); 544 l4_hdr = skb_transport_header(skb); 545 546 if (skb->protocol == htons(ETH_P_IPV6)) { 547 exthdr = l3.hdr + sizeof(*l3.v6); 548 l4_proto_tmp = l3.v6->nexthdr; 549 if (l4_hdr != exthdr) 550 ipv6_skip_exthdr(skb, exthdr - skb->data, 551 &l4_proto_tmp, &frag_off); 552 } else if (skb->protocol == htons(ETH_P_IP)) { 553 l4_proto_tmp = l3.v4->protocol; 554 } else { 555 return -EINVAL; 556 } 557 558 *ol4_proto = l4_proto_tmp; 559 560 /* tunnel packet */ 561 if (!skb->encapsulation) { 562 *il4_proto = 0; 563 return 0; 564 } 565 566 /* find inner header point */ 567 l3.hdr = skb_inner_network_header(skb); 568 l4_hdr = skb_inner_transport_header(skb); 569 570 if (l3.v6->version == 6) { 571 exthdr = l3.hdr + sizeof(*l3.v6); 572 l4_proto_tmp = l3.v6->nexthdr; 573 if (l4_hdr != exthdr) 574 ipv6_skip_exthdr(skb, exthdr - skb->data, 575 &l4_proto_tmp, &frag_off); 576 } else if (l3.v4->version == 4) { 577 l4_proto_tmp = l3.v4->protocol; 578 } 579 580 *il4_proto = l4_proto_tmp; 581 582 return 0; 583 } 584 585 static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto, 586 u8 il4_proto, u32 *type_cs_vlan_tso, 587 u32 *ol_type_vlan_len_msec) 588 { 589 union { 590 struct iphdr *v4; 591 struct ipv6hdr *v6; 592 unsigned char *hdr; 593 } l3; 594 union { 595 struct tcphdr *tcp; 596 struct udphdr *udp; 597 struct gre_base_hdr *gre; 598 unsigned char *hdr; 599 } l4; 600 unsigned char *l2_hdr; 601 u8 l4_proto = ol4_proto; 602 u32 ol2_len; 603 u32 ol3_len; 604 u32 ol4_len; 605 u32 l2_len; 606 u32 l3_len; 607 608 l3.hdr = skb_network_header(skb); 609 l4.hdr = skb_transport_header(skb); 610 611 /* compute L2 header size for normal packet, defined in 2 Bytes */ 612 l2_len = l3.hdr - skb->data; 613 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M, 614 HNS3_TXD_L2LEN_S, l2_len >> 1); 615 616 /* tunnel packet*/ 617 if (skb->encapsulation) { 618 /* compute OL2 header size, defined in 2 Bytes */ 619 ol2_len = l2_len; 620 hnae3_set_field(*ol_type_vlan_len_msec, 621 HNS3_TXD_L2LEN_M, 622 HNS3_TXD_L2LEN_S, ol2_len >> 1); 623 624 /* compute OL3 header size, defined in 4 Bytes */ 625 ol3_len = l4.hdr - l3.hdr; 626 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M, 627 HNS3_TXD_L3LEN_S, ol3_len >> 2); 628 629 /* MAC in UDP, MAC in GRE (0x6558)*/ 630 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) { 631 /* switch MAC header ptr from outer to inner header.*/ 632 l2_hdr = skb_inner_mac_header(skb); 633 634 /* compute OL4 header size, defined in 4 Bytes. */ 635 ol4_len = l2_hdr - l4.hdr; 636 hnae3_set_field(*ol_type_vlan_len_msec, 637 HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S, 638 ol4_len >> 2); 639 640 /* switch IP header ptr from outer to inner header */ 641 l3.hdr = skb_inner_network_header(skb); 642 643 /* compute inner l2 header size, defined in 2 Bytes. */ 644 l2_len = l3.hdr - l2_hdr; 645 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M, 646 HNS3_TXD_L2LEN_S, l2_len >> 1); 647 } else { 648 /* skb packet types not supported by hardware, 649 * txbd len fild doesn't be filled. 650 */ 651 return; 652 } 653 654 /* switch L4 header pointer from outer to inner */ 655 l4.hdr = skb_inner_transport_header(skb); 656 657 l4_proto = il4_proto; 658 } 659 660 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 661 l3_len = l4.hdr - l3.hdr; 662 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M, 663 HNS3_TXD_L3LEN_S, l3_len >> 2); 664 665 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 666 switch (l4_proto) { 667 case IPPROTO_TCP: 668 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 669 HNS3_TXD_L4LEN_S, l4.tcp->doff); 670 break; 671 case IPPROTO_SCTP: 672 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 673 HNS3_TXD_L4LEN_S, 674 (sizeof(struct sctphdr) >> 2)); 675 break; 676 case IPPROTO_UDP: 677 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 678 HNS3_TXD_L4LEN_S, 679 (sizeof(struct udphdr) >> 2)); 680 break; 681 default: 682 /* skb packet types not supported by hardware, 683 * txbd len fild doesn't be filled. 684 */ 685 return; 686 } 687 } 688 689 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 690 * and it is udp packet, which has a dest port as the IANA assigned. 691 * the hardware is expected to do the checksum offload, but the 692 * hardware will not do the checksum offload when udp dest port is 693 * 4789. 694 */ 695 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 696 { 697 #define IANA_VXLAN_PORT 4789 698 union { 699 struct tcphdr *tcp; 700 struct udphdr *udp; 701 struct gre_base_hdr *gre; 702 unsigned char *hdr; 703 } l4; 704 705 l4.hdr = skb_transport_header(skb); 706 707 if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT))) 708 return false; 709 710 skb_checksum_help(skb); 711 712 return true; 713 } 714 715 static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto, 716 u8 il4_proto, u32 *type_cs_vlan_tso, 717 u32 *ol_type_vlan_len_msec) 718 { 719 union { 720 struct iphdr *v4; 721 struct ipv6hdr *v6; 722 unsigned char *hdr; 723 } l3; 724 u32 l4_proto = ol4_proto; 725 726 l3.hdr = skb_network_header(skb); 727 728 /* define OL3 type and tunnel type(OL4).*/ 729 if (skb->encapsulation) { 730 /* define outer network header type.*/ 731 if (skb->protocol == htons(ETH_P_IP)) { 732 if (skb_is_gso(skb)) 733 hnae3_set_field(*ol_type_vlan_len_msec, 734 HNS3_TXD_OL3T_M, 735 HNS3_TXD_OL3T_S, 736 HNS3_OL3T_IPV4_CSUM); 737 else 738 hnae3_set_field(*ol_type_vlan_len_msec, 739 HNS3_TXD_OL3T_M, 740 HNS3_TXD_OL3T_S, 741 HNS3_OL3T_IPV4_NO_CSUM); 742 743 } else if (skb->protocol == htons(ETH_P_IPV6)) { 744 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M, 745 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6); 746 } 747 748 /* define tunnel type(OL4).*/ 749 switch (l4_proto) { 750 case IPPROTO_UDP: 751 hnae3_set_field(*ol_type_vlan_len_msec, 752 HNS3_TXD_TUNTYPE_M, 753 HNS3_TXD_TUNTYPE_S, 754 HNS3_TUN_MAC_IN_UDP); 755 break; 756 case IPPROTO_GRE: 757 hnae3_set_field(*ol_type_vlan_len_msec, 758 HNS3_TXD_TUNTYPE_M, 759 HNS3_TXD_TUNTYPE_S, 760 HNS3_TUN_NVGRE); 761 break; 762 default: 763 /* drop the skb tunnel packet if hardware don't support, 764 * because hardware can't calculate csum when TSO. 765 */ 766 if (skb_is_gso(skb)) 767 return -EDOM; 768 769 /* the stack computes the IP header already, 770 * driver calculate l4 checksum when not TSO. 771 */ 772 skb_checksum_help(skb); 773 return 0; 774 } 775 776 l3.hdr = skb_inner_network_header(skb); 777 l4_proto = il4_proto; 778 } 779 780 if (l3.v4->version == 4) { 781 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M, 782 HNS3_TXD_L3T_S, HNS3_L3T_IPV4); 783 784 /* the stack computes the IP header already, the only time we 785 * need the hardware to recompute it is in the case of TSO. 786 */ 787 if (skb_is_gso(skb)) 788 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 789 } else if (l3.v6->version == 6) { 790 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M, 791 HNS3_TXD_L3T_S, HNS3_L3T_IPV6); 792 } 793 794 switch (l4_proto) { 795 case IPPROTO_TCP: 796 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 797 hnae3_set_field(*type_cs_vlan_tso, 798 HNS3_TXD_L4T_M, 799 HNS3_TXD_L4T_S, 800 HNS3_L4T_TCP); 801 break; 802 case IPPROTO_UDP: 803 if (hns3_tunnel_csum_bug(skb)) 804 break; 805 806 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 807 hnae3_set_field(*type_cs_vlan_tso, 808 HNS3_TXD_L4T_M, 809 HNS3_TXD_L4T_S, 810 HNS3_L4T_UDP); 811 break; 812 case IPPROTO_SCTP: 813 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 814 hnae3_set_field(*type_cs_vlan_tso, 815 HNS3_TXD_L4T_M, 816 HNS3_TXD_L4T_S, 817 HNS3_L4T_SCTP); 818 break; 819 default: 820 /* drop the skb tunnel packet if hardware don't support, 821 * because hardware can't calculate csum when TSO. 822 */ 823 if (skb_is_gso(skb)) 824 return -EDOM; 825 826 /* the stack computes the IP header already, 827 * driver calculate l4 checksum when not TSO. 828 */ 829 skb_checksum_help(skb); 830 return 0; 831 } 832 833 return 0; 834 } 835 836 static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end) 837 { 838 /* Config bd buffer end */ 839 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M, 840 HNS3_TXD_BDTYPE_S, 0); 841 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end); 842 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1); 843 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0); 844 } 845 846 static int hns3_fill_desc_vtags(struct sk_buff *skb, 847 struct hns3_enet_ring *tx_ring, 848 u32 *inner_vlan_flag, 849 u32 *out_vlan_flag, 850 u16 *inner_vtag, 851 u16 *out_vtag) 852 { 853 #define HNS3_TX_VLAN_PRIO_SHIFT 13 854 855 if (skb->protocol == htons(ETH_P_8021Q) && 856 !(tx_ring->tqp->handle->kinfo.netdev->features & 857 NETIF_F_HW_VLAN_CTAG_TX)) { 858 /* When HW VLAN acceleration is turned off, and the stack 859 * sets the protocol to 802.1q, the driver just need to 860 * set the protocol to the encapsulated ethertype. 861 */ 862 skb->protocol = vlan_get_protocol(skb); 863 return 0; 864 } 865 866 if (skb_vlan_tag_present(skb)) { 867 u16 vlan_tag; 868 869 vlan_tag = skb_vlan_tag_get(skb); 870 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT; 871 872 /* Based on hw strategy, use out_vtag in two layer tag case, 873 * and use inner_vtag in one tag case. 874 */ 875 if (skb->protocol == htons(ETH_P_8021Q)) { 876 hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1); 877 *out_vtag = vlan_tag; 878 } else { 879 hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1); 880 *inner_vtag = vlan_tag; 881 } 882 } else if (skb->protocol == htons(ETH_P_8021Q)) { 883 struct vlan_ethhdr *vhdr; 884 int rc; 885 886 rc = skb_cow_head(skb, 0); 887 if (rc < 0) 888 return rc; 889 vhdr = (struct vlan_ethhdr *)skb->data; 890 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7) 891 << HNS3_TX_VLAN_PRIO_SHIFT); 892 } 893 894 skb->protocol = vlan_get_protocol(skb); 895 return 0; 896 } 897 898 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 899 int size, dma_addr_t dma, int frag_end, 900 enum hns_desc_type type) 901 { 902 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 903 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 904 u32 ol_type_vlan_len_msec = 0; 905 u16 bdtp_fe_sc_vld_ra_ri = 0; 906 u32 type_cs_vlan_tso = 0; 907 struct sk_buff *skb; 908 u16 inner_vtag = 0; 909 u16 out_vtag = 0; 910 u32 paylen = 0; 911 u16 mss = 0; 912 u8 ol4_proto; 913 u8 il4_proto; 914 int ret; 915 916 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */ 917 desc_cb->priv = priv; 918 desc_cb->length = size; 919 desc_cb->dma = dma; 920 desc_cb->type = type; 921 922 /* now, fill the descriptor */ 923 desc->addr = cpu_to_le64(dma); 924 desc->tx.send_size = cpu_to_le16((u16)size); 925 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, frag_end); 926 desc->tx.bdtp_fe_sc_vld_ra_ri = cpu_to_le16(bdtp_fe_sc_vld_ra_ri); 927 928 if (type == DESC_TYPE_SKB) { 929 skb = (struct sk_buff *)priv; 930 paylen = skb->len; 931 932 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso, 933 &ol_type_vlan_len_msec, 934 &inner_vtag, &out_vtag); 935 if (unlikely(ret)) 936 return ret; 937 938 if (skb->ip_summed == CHECKSUM_PARTIAL) { 939 skb_reset_mac_len(skb); 940 941 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 942 if (ret) 943 return ret; 944 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto, 945 &type_cs_vlan_tso, 946 &ol_type_vlan_len_msec); 947 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto, 948 &type_cs_vlan_tso, 949 &ol_type_vlan_len_msec); 950 if (ret) 951 return ret; 952 953 ret = hns3_set_tso(skb, &paylen, &mss, 954 &type_cs_vlan_tso); 955 if (ret) 956 return ret; 957 } 958 959 /* Set txbd */ 960 desc->tx.ol_type_vlan_len_msec = 961 cpu_to_le32(ol_type_vlan_len_msec); 962 desc->tx.type_cs_vlan_tso_len = 963 cpu_to_le32(type_cs_vlan_tso); 964 desc->tx.paylen = cpu_to_le32(paylen); 965 desc->tx.mss = cpu_to_le16(mss); 966 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 967 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 968 } 969 970 /* move ring pointer to next.*/ 971 ring_ptr_move_fw(ring, next_to_use); 972 973 return 0; 974 } 975 976 static int hns3_fill_desc_tso(struct hns3_enet_ring *ring, void *priv, 977 int size, dma_addr_t dma, int frag_end, 978 enum hns_desc_type type) 979 { 980 unsigned int frag_buf_num; 981 unsigned int k; 982 int sizeoflast; 983 int ret; 984 985 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 986 sizeoflast = size % HNS3_MAX_BD_SIZE; 987 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 988 989 /* When the frag size is bigger than hardware, split this frag */ 990 for (k = 0; k < frag_buf_num; k++) { 991 ret = hns3_fill_desc(ring, priv, 992 (k == frag_buf_num - 1) ? 993 sizeoflast : HNS3_MAX_BD_SIZE, 994 dma + HNS3_MAX_BD_SIZE * k, 995 frag_end && (k == frag_buf_num - 1) ? 1 : 0, 996 (type == DESC_TYPE_SKB && !k) ? 997 DESC_TYPE_SKB : DESC_TYPE_PAGE); 998 if (ret) 999 return ret; 1000 } 1001 1002 return 0; 1003 } 1004 1005 static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum, 1006 struct hns3_enet_ring *ring) 1007 { 1008 struct sk_buff *skb = *out_skb; 1009 struct skb_frag_struct *frag; 1010 int bdnum_for_frag; 1011 int frag_num; 1012 int buf_num; 1013 int size; 1014 int i; 1015 1016 size = skb_headlen(skb); 1017 buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1018 1019 frag_num = skb_shinfo(skb)->nr_frags; 1020 for (i = 0; i < frag_num; i++) { 1021 frag = &skb_shinfo(skb)->frags[i]; 1022 size = skb_frag_size(frag); 1023 bdnum_for_frag = 1024 (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1025 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG) 1026 return -ENOMEM; 1027 1028 buf_num += bdnum_for_frag; 1029 } 1030 1031 if (buf_num > ring_space(ring)) 1032 return -EBUSY; 1033 1034 *bnum = buf_num; 1035 return 0; 1036 } 1037 1038 static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum, 1039 struct hns3_enet_ring *ring) 1040 { 1041 struct sk_buff *skb = *out_skb; 1042 int buf_num; 1043 1044 /* No. of segments (plus a header) */ 1045 buf_num = skb_shinfo(skb)->nr_frags + 1; 1046 1047 if (buf_num > ring_space(ring)) 1048 return -EBUSY; 1049 1050 *bnum = buf_num; 1051 1052 return 0; 1053 } 1054 1055 static void hns_nic_dma_unmap(struct hns3_enet_ring *ring, int next_to_use_orig) 1056 { 1057 struct device *dev = ring_to_dev(ring); 1058 unsigned int i; 1059 1060 for (i = 0; i < ring->desc_num; i++) { 1061 /* check if this is where we started */ 1062 if (ring->next_to_use == next_to_use_orig) 1063 break; 1064 1065 /* unmap the descriptor dma address */ 1066 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB) 1067 dma_unmap_single(dev, 1068 ring->desc_cb[ring->next_to_use].dma, 1069 ring->desc_cb[ring->next_to_use].length, 1070 DMA_TO_DEVICE); 1071 else 1072 dma_unmap_page(dev, 1073 ring->desc_cb[ring->next_to_use].dma, 1074 ring->desc_cb[ring->next_to_use].length, 1075 DMA_TO_DEVICE); 1076 1077 /* rollback one */ 1078 ring_ptr_move_bw(ring, next_to_use); 1079 } 1080 } 1081 1082 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1083 { 1084 struct hns3_nic_priv *priv = netdev_priv(netdev); 1085 struct hns3_nic_ring_data *ring_data = 1086 &tx_ring_data(priv, skb->queue_mapping); 1087 struct hns3_enet_ring *ring = ring_data->ring; 1088 struct device *dev = priv->dev; 1089 struct netdev_queue *dev_queue; 1090 struct skb_frag_struct *frag; 1091 int next_to_use_head; 1092 int next_to_use_frag; 1093 dma_addr_t dma; 1094 int buf_num; 1095 int seg_num; 1096 int size; 1097 int ret; 1098 int i; 1099 1100 /* Prefetch the data used later */ 1101 prefetch(skb->data); 1102 1103 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) { 1104 case -EBUSY: 1105 u64_stats_update_begin(&ring->syncp); 1106 ring->stats.tx_busy++; 1107 u64_stats_update_end(&ring->syncp); 1108 1109 goto out_net_tx_busy; 1110 case -ENOMEM: 1111 u64_stats_update_begin(&ring->syncp); 1112 ring->stats.sw_err_cnt++; 1113 u64_stats_update_end(&ring->syncp); 1114 netdev_err(netdev, "no memory to xmit!\n"); 1115 1116 goto out_err_tx_ok; 1117 default: 1118 break; 1119 } 1120 1121 /* No. of segments (plus a header) */ 1122 seg_num = skb_shinfo(skb)->nr_frags + 1; 1123 /* Fill the first part */ 1124 size = skb_headlen(skb); 1125 1126 next_to_use_head = ring->next_to_use; 1127 1128 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1129 if (dma_mapping_error(dev, dma)) { 1130 netdev_err(netdev, "TX head DMA map failed\n"); 1131 ring->stats.sw_err_cnt++; 1132 goto out_err_tx_ok; 1133 } 1134 1135 ret = priv->ops.fill_desc(ring, skb, size, dma, seg_num == 1 ? 1 : 0, 1136 DESC_TYPE_SKB); 1137 if (ret) 1138 goto head_dma_map_err; 1139 1140 next_to_use_frag = ring->next_to_use; 1141 /* Fill the fragments */ 1142 for (i = 1; i < seg_num; i++) { 1143 frag = &skb_shinfo(skb)->frags[i - 1]; 1144 size = skb_frag_size(frag); 1145 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1146 if (dma_mapping_error(dev, dma)) { 1147 netdev_err(netdev, "TX frag(%d) DMA map failed\n", i); 1148 ring->stats.sw_err_cnt++; 1149 goto frag_dma_map_err; 1150 } 1151 ret = priv->ops.fill_desc(ring, skb_frag_page(frag), size, dma, 1152 seg_num - 1 == i ? 1 : 0, 1153 DESC_TYPE_PAGE); 1154 1155 if (ret) 1156 goto frag_dma_map_err; 1157 } 1158 1159 /* Complete translate all packets */ 1160 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index); 1161 netdev_tx_sent_queue(dev_queue, skb->len); 1162 1163 wmb(); /* Commit all data before submit */ 1164 1165 hnae3_queue_xmit(ring->tqp, buf_num); 1166 1167 return NETDEV_TX_OK; 1168 1169 frag_dma_map_err: 1170 hns_nic_dma_unmap(ring, next_to_use_frag); 1171 1172 head_dma_map_err: 1173 hns_nic_dma_unmap(ring, next_to_use_head); 1174 1175 out_err_tx_ok: 1176 dev_kfree_skb_any(skb); 1177 return NETDEV_TX_OK; 1178 1179 out_net_tx_busy: 1180 netif_stop_subqueue(netdev, ring_data->queue_index); 1181 smp_mb(); /* Commit all data before submit */ 1182 1183 return NETDEV_TX_BUSY; 1184 } 1185 1186 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1187 { 1188 struct hnae3_handle *h = hns3_get_handle(netdev); 1189 struct sockaddr *mac_addr = p; 1190 int ret; 1191 1192 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1193 return -EADDRNOTAVAIL; 1194 1195 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1196 netdev_info(netdev, "already using mac address %pM\n", 1197 mac_addr->sa_data); 1198 return 0; 1199 } 1200 1201 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1202 if (ret) { 1203 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1204 return ret; 1205 } 1206 1207 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1208 1209 return 0; 1210 } 1211 1212 static int hns3_nic_set_features(struct net_device *netdev, 1213 netdev_features_t features) 1214 { 1215 netdev_features_t changed = netdev->features ^ features; 1216 struct hns3_nic_priv *priv = netdev_priv(netdev); 1217 struct hnae3_handle *h = priv->ae_handle; 1218 int ret; 1219 1220 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) { 1221 if (features & (NETIF_F_TSO | NETIF_F_TSO6)) { 1222 priv->ops.fill_desc = hns3_fill_desc_tso; 1223 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 1224 } else { 1225 priv->ops.fill_desc = hns3_fill_desc; 1226 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 1227 } 1228 } 1229 1230 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 1231 h->ae_algo->ops->enable_vlan_filter) { 1232 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1233 h->ae_algo->ops->enable_vlan_filter(h, true); 1234 else 1235 h->ae_algo->ops->enable_vlan_filter(h, false); 1236 } 1237 1238 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1239 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1240 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1241 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true); 1242 else 1243 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false); 1244 1245 if (ret) 1246 return ret; 1247 } 1248 1249 netdev->features = features; 1250 return 0; 1251 } 1252 1253 static void hns3_nic_get_stats64(struct net_device *netdev, 1254 struct rtnl_link_stats64 *stats) 1255 { 1256 struct hns3_nic_priv *priv = netdev_priv(netdev); 1257 int queue_num = priv->ae_handle->kinfo.num_tqps; 1258 struct hnae3_handle *handle = priv->ae_handle; 1259 struct hns3_enet_ring *ring; 1260 unsigned int start; 1261 unsigned int idx; 1262 u64 tx_bytes = 0; 1263 u64 rx_bytes = 0; 1264 u64 tx_pkts = 0; 1265 u64 rx_pkts = 0; 1266 u64 tx_drop = 0; 1267 u64 rx_drop = 0; 1268 1269 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1270 return; 1271 1272 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1273 1274 for (idx = 0; idx < queue_num; idx++) { 1275 /* fetch the tx stats */ 1276 ring = priv->ring_data[idx].ring; 1277 do { 1278 start = u64_stats_fetch_begin_irq(&ring->syncp); 1279 tx_bytes += ring->stats.tx_bytes; 1280 tx_pkts += ring->stats.tx_pkts; 1281 tx_drop += ring->stats.tx_busy; 1282 tx_drop += ring->stats.sw_err_cnt; 1283 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1284 1285 /* fetch the rx stats */ 1286 ring = priv->ring_data[idx + queue_num].ring; 1287 do { 1288 start = u64_stats_fetch_begin_irq(&ring->syncp); 1289 rx_bytes += ring->stats.rx_bytes; 1290 rx_pkts += ring->stats.rx_pkts; 1291 rx_drop += ring->stats.non_vld_descs; 1292 rx_drop += ring->stats.err_pkt_len; 1293 rx_drop += ring->stats.l2_err; 1294 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1295 } 1296 1297 stats->tx_bytes = tx_bytes; 1298 stats->tx_packets = tx_pkts; 1299 stats->rx_bytes = rx_bytes; 1300 stats->rx_packets = rx_pkts; 1301 1302 stats->rx_errors = netdev->stats.rx_errors; 1303 stats->multicast = netdev->stats.multicast; 1304 stats->rx_length_errors = netdev->stats.rx_length_errors; 1305 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 1306 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1307 1308 stats->tx_errors = netdev->stats.tx_errors; 1309 stats->rx_dropped = rx_drop + netdev->stats.rx_dropped; 1310 stats->tx_dropped = tx_drop + netdev->stats.tx_dropped; 1311 stats->collisions = netdev->stats.collisions; 1312 stats->rx_over_errors = netdev->stats.rx_over_errors; 1313 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1314 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1315 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1316 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1317 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1318 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1319 stats->tx_window_errors = netdev->stats.tx_window_errors; 1320 stats->rx_compressed = netdev->stats.rx_compressed; 1321 stats->tx_compressed = netdev->stats.tx_compressed; 1322 } 1323 1324 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1325 { 1326 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1327 struct hnae3_handle *h = hns3_get_handle(netdev); 1328 struct hnae3_knic_private_info *kinfo = &h->kinfo; 1329 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map; 1330 u8 tc = mqprio_qopt->qopt.num_tc; 1331 u16 mode = mqprio_qopt->mode; 1332 u8 hw = mqprio_qopt->qopt.hw; 1333 bool if_running; 1334 int ret; 1335 1336 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1337 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1338 return -EOPNOTSUPP; 1339 1340 if (tc > HNAE3_MAX_TC) 1341 return -EINVAL; 1342 1343 if (!netdev) 1344 return -EINVAL; 1345 1346 if_running = netif_running(netdev); 1347 if (if_running) { 1348 hns3_nic_net_stop(netdev); 1349 msleep(100); 1350 } 1351 1352 ret = (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1353 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP; 1354 if (ret) 1355 goto out; 1356 1357 ret = hns3_nic_set_real_num_queue(netdev); 1358 1359 out: 1360 if (if_running) 1361 hns3_nic_net_open(netdev); 1362 1363 return ret; 1364 } 1365 1366 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1367 void *type_data) 1368 { 1369 if (type != TC_SETUP_QDISC_MQPRIO) 1370 return -EOPNOTSUPP; 1371 1372 return hns3_setup_tc(dev, type_data); 1373 } 1374 1375 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1376 __be16 proto, u16 vid) 1377 { 1378 struct hnae3_handle *h = hns3_get_handle(netdev); 1379 struct hns3_nic_priv *priv = netdev_priv(netdev); 1380 int ret = -EIO; 1381 1382 if (h->ae_algo->ops->set_vlan_filter) 1383 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1384 1385 if (!ret) 1386 set_bit(vid, priv->active_vlans); 1387 1388 return ret; 1389 } 1390 1391 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1392 __be16 proto, u16 vid) 1393 { 1394 struct hnae3_handle *h = hns3_get_handle(netdev); 1395 struct hns3_nic_priv *priv = netdev_priv(netdev); 1396 int ret = -EIO; 1397 1398 if (h->ae_algo->ops->set_vlan_filter) 1399 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1400 1401 if (!ret) 1402 clear_bit(vid, priv->active_vlans); 1403 1404 return ret; 1405 } 1406 1407 static void hns3_restore_vlan(struct net_device *netdev) 1408 { 1409 struct hns3_nic_priv *priv = netdev_priv(netdev); 1410 u16 vid; 1411 int ret; 1412 1413 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 1414 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 1415 if (ret) 1416 netdev_warn(netdev, "Restore vlan: %d filter, ret:%d\n", 1417 vid, ret); 1418 } 1419 } 1420 1421 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1422 u8 qos, __be16 vlan_proto) 1423 { 1424 struct hnae3_handle *h = hns3_get_handle(netdev); 1425 int ret = -EIO; 1426 1427 if (h->ae_algo->ops->set_vf_vlan_filter) 1428 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1429 qos, vlan_proto); 1430 1431 return ret; 1432 } 1433 1434 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1435 { 1436 struct hnae3_handle *h = hns3_get_handle(netdev); 1437 bool if_running = netif_running(netdev); 1438 int ret; 1439 1440 if (!h->ae_algo->ops->set_mtu) 1441 return -EOPNOTSUPP; 1442 1443 /* if this was called with netdev up then bring netdevice down */ 1444 if (if_running) { 1445 (void)hns3_nic_net_stop(netdev); 1446 msleep(100); 1447 } 1448 1449 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 1450 if (ret) { 1451 netdev_err(netdev, "failed to change MTU in hardware %d\n", 1452 ret); 1453 return ret; 1454 } 1455 1456 netdev->mtu = new_mtu; 1457 1458 /* if the netdev was running earlier, bring it up again */ 1459 if (if_running && hns3_nic_net_open(netdev)) 1460 ret = -EINVAL; 1461 1462 return ret; 1463 } 1464 1465 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 1466 { 1467 struct hns3_nic_priv *priv = netdev_priv(ndev); 1468 struct hns3_enet_ring *tx_ring = NULL; 1469 int timeout_queue = 0; 1470 int hw_head, hw_tail; 1471 int i; 1472 1473 /* Find the stopped queue the same way the stack does */ 1474 for (i = 0; i < ndev->real_num_tx_queues; i++) { 1475 struct netdev_queue *q; 1476 unsigned long trans_start; 1477 1478 q = netdev_get_tx_queue(ndev, i); 1479 trans_start = q->trans_start; 1480 if (netif_xmit_stopped(q) && 1481 time_after(jiffies, 1482 (trans_start + ndev->watchdog_timeo))) { 1483 timeout_queue = i; 1484 break; 1485 } 1486 } 1487 1488 if (i == ndev->num_tx_queues) { 1489 netdev_info(ndev, 1490 "no netdev TX timeout queue found, timeout count: %llu\n", 1491 priv->tx_timeout_count); 1492 return false; 1493 } 1494 1495 tx_ring = priv->ring_data[timeout_queue].ring; 1496 1497 hw_head = readl_relaxed(tx_ring->tqp->io_base + 1498 HNS3_RING_TX_RING_HEAD_REG); 1499 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 1500 HNS3_RING_TX_RING_TAIL_REG); 1501 netdev_info(ndev, 1502 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n", 1503 priv->tx_timeout_count, 1504 timeout_queue, 1505 tx_ring->next_to_use, 1506 tx_ring->next_to_clean, 1507 hw_head, 1508 hw_tail, 1509 readl(tx_ring->tqp_vector->mask_addr)); 1510 1511 return true; 1512 } 1513 1514 static void hns3_nic_net_timeout(struct net_device *ndev) 1515 { 1516 struct hns3_nic_priv *priv = netdev_priv(ndev); 1517 struct hnae3_handle *h = priv->ae_handle; 1518 1519 if (!hns3_get_tx_timeo_queue_info(ndev)) 1520 return; 1521 1522 priv->tx_timeout_count++; 1523 1524 if (time_before(jiffies, (h->last_reset_time + ndev->watchdog_timeo))) 1525 return; 1526 1527 /* request the reset */ 1528 if (h->ae_algo->ops->reset_event) 1529 h->ae_algo->ops->reset_event(h); 1530 } 1531 1532 static const struct net_device_ops hns3_nic_netdev_ops = { 1533 .ndo_open = hns3_nic_net_open, 1534 .ndo_stop = hns3_nic_net_stop, 1535 .ndo_start_xmit = hns3_nic_net_xmit, 1536 .ndo_tx_timeout = hns3_nic_net_timeout, 1537 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 1538 .ndo_change_mtu = hns3_nic_change_mtu, 1539 .ndo_set_features = hns3_nic_set_features, 1540 .ndo_get_stats64 = hns3_nic_get_stats64, 1541 .ndo_setup_tc = hns3_nic_setup_tc, 1542 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 1543 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 1544 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 1545 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 1546 }; 1547 1548 static bool hns3_is_phys_func(struct pci_dev *pdev) 1549 { 1550 u32 dev_id = pdev->device; 1551 1552 switch (dev_id) { 1553 case HNAE3_DEV_ID_GE: 1554 case HNAE3_DEV_ID_25GE: 1555 case HNAE3_DEV_ID_25GE_RDMA: 1556 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 1557 case HNAE3_DEV_ID_50GE_RDMA: 1558 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 1559 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 1560 return true; 1561 case HNAE3_DEV_ID_100G_VF: 1562 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF: 1563 return false; 1564 default: 1565 dev_warn(&pdev->dev, "un-recognized pci device-id %d", 1566 dev_id); 1567 } 1568 1569 return false; 1570 } 1571 1572 static void hns3_disable_sriov(struct pci_dev *pdev) 1573 { 1574 /* If our VFs are assigned we cannot shut down SR-IOV 1575 * without causing issues, so just leave the hardware 1576 * available but disabled 1577 */ 1578 if (pci_vfs_assigned(pdev)) { 1579 dev_warn(&pdev->dev, 1580 "disabling driver while VFs are assigned\n"); 1581 return; 1582 } 1583 1584 pci_disable_sriov(pdev); 1585 } 1586 1587 /* hns3_probe - Device initialization routine 1588 * @pdev: PCI device information struct 1589 * @ent: entry in hns3_pci_tbl 1590 * 1591 * hns3_probe initializes a PF identified by a pci_dev structure. 1592 * The OS initialization, configuring of the PF private structure, 1593 * and a hardware reset occur. 1594 * 1595 * Returns 0 on success, negative on failure 1596 */ 1597 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1598 { 1599 struct hnae3_ae_dev *ae_dev; 1600 int ret; 1601 1602 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), 1603 GFP_KERNEL); 1604 if (!ae_dev) { 1605 ret = -ENOMEM; 1606 return ret; 1607 } 1608 1609 ae_dev->pdev = pdev; 1610 ae_dev->flag = ent->driver_data; 1611 ae_dev->dev_type = HNAE3_DEV_KNIC; 1612 pci_set_drvdata(pdev, ae_dev); 1613 1614 hnae3_register_ae_dev(ae_dev); 1615 1616 return 0; 1617 } 1618 1619 /* hns3_remove - Device removal routine 1620 * @pdev: PCI device information struct 1621 */ 1622 static void hns3_remove(struct pci_dev *pdev) 1623 { 1624 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1625 1626 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 1627 hns3_disable_sriov(pdev); 1628 1629 hnae3_unregister_ae_dev(ae_dev); 1630 } 1631 1632 /** 1633 * hns3_pci_sriov_configure 1634 * @pdev: pointer to a pci_dev structure 1635 * @num_vfs: number of VFs to allocate 1636 * 1637 * Enable or change the number of VFs. Called when the user updates the number 1638 * of VFs in sysfs. 1639 **/ 1640 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 1641 { 1642 int ret; 1643 1644 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 1645 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 1646 return -EINVAL; 1647 } 1648 1649 if (num_vfs) { 1650 ret = pci_enable_sriov(pdev, num_vfs); 1651 if (ret) 1652 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 1653 else 1654 return num_vfs; 1655 } else if (!pci_vfs_assigned(pdev)) { 1656 pci_disable_sriov(pdev); 1657 } else { 1658 dev_warn(&pdev->dev, 1659 "Unable to free VFs because some are assigned to VMs.\n"); 1660 } 1661 1662 return 0; 1663 } 1664 1665 static struct pci_driver hns3_driver = { 1666 .name = hns3_driver_name, 1667 .id_table = hns3_pci_tbl, 1668 .probe = hns3_probe, 1669 .remove = hns3_remove, 1670 .sriov_configure = hns3_pci_sriov_configure, 1671 }; 1672 1673 /* set default feature to hns3 */ 1674 static void hns3_set_default_feature(struct net_device *netdev) 1675 { 1676 struct hnae3_handle *h = hns3_get_handle(netdev); 1677 struct pci_dev *pdev = h->pdev; 1678 1679 netdev->priv_flags |= IFF_UNICAST_FLT; 1680 1681 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1682 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1683 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1684 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1685 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1686 1687 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID; 1688 1689 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 1690 1691 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1692 NETIF_F_HW_VLAN_CTAG_FILTER | 1693 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1694 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1695 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1696 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1697 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1698 1699 netdev->vlan_features |= 1700 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | 1701 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 1702 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1703 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1704 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1705 1706 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1707 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1708 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1709 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1710 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1711 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1712 1713 if (pdev->revision != 0x20) 1714 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1715 } 1716 1717 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 1718 struct hns3_desc_cb *cb) 1719 { 1720 unsigned int order = hnae3_page_order(ring); 1721 struct page *p; 1722 1723 p = dev_alloc_pages(order); 1724 if (!p) 1725 return -ENOMEM; 1726 1727 cb->priv = p; 1728 cb->page_offset = 0; 1729 cb->reuse_flag = 0; 1730 cb->buf = page_address(p); 1731 cb->length = hnae3_page_size(ring); 1732 cb->type = DESC_TYPE_PAGE; 1733 1734 return 0; 1735 } 1736 1737 static void hns3_free_buffer(struct hns3_enet_ring *ring, 1738 struct hns3_desc_cb *cb) 1739 { 1740 if (cb->type == DESC_TYPE_SKB) 1741 dev_kfree_skb_any((struct sk_buff *)cb->priv); 1742 else if (!HNAE3_IS_TX_RING(ring)) 1743 put_page((struct page *)cb->priv); 1744 memset(cb, 0, sizeof(*cb)); 1745 } 1746 1747 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 1748 { 1749 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 1750 cb->length, ring_to_dma_dir(ring)); 1751 1752 if (dma_mapping_error(ring_to_dev(ring), cb->dma)) 1753 return -EIO; 1754 1755 return 0; 1756 } 1757 1758 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 1759 struct hns3_desc_cb *cb) 1760 { 1761 if (cb->type == DESC_TYPE_SKB) 1762 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 1763 ring_to_dma_dir(ring)); 1764 else 1765 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 1766 ring_to_dma_dir(ring)); 1767 } 1768 1769 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 1770 { 1771 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 1772 ring->desc[i].addr = 0; 1773 } 1774 1775 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i) 1776 { 1777 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 1778 1779 if (!ring->desc_cb[i].dma) 1780 return; 1781 1782 hns3_buffer_detach(ring, i); 1783 hns3_free_buffer(ring, cb); 1784 } 1785 1786 static void hns3_free_buffers(struct hns3_enet_ring *ring) 1787 { 1788 int i; 1789 1790 for (i = 0; i < ring->desc_num; i++) 1791 hns3_free_buffer_detach(ring, i); 1792 } 1793 1794 /* free desc along with its attached buffer */ 1795 static void hns3_free_desc(struct hns3_enet_ring *ring) 1796 { 1797 int size = ring->desc_num * sizeof(ring->desc[0]); 1798 1799 hns3_free_buffers(ring); 1800 1801 if (ring->desc) { 1802 dma_free_coherent(ring_to_dev(ring), size, 1803 ring->desc, ring->desc_dma_addr); 1804 ring->desc = NULL; 1805 } 1806 } 1807 1808 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 1809 { 1810 int size = ring->desc_num * sizeof(ring->desc[0]); 1811 1812 ring->desc = dma_zalloc_coherent(ring_to_dev(ring), size, 1813 &ring->desc_dma_addr, 1814 GFP_KERNEL); 1815 if (!ring->desc) 1816 return -ENOMEM; 1817 1818 return 0; 1819 } 1820 1821 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring, 1822 struct hns3_desc_cb *cb) 1823 { 1824 int ret; 1825 1826 ret = hns3_alloc_buffer(ring, cb); 1827 if (ret) 1828 goto out; 1829 1830 ret = hns3_map_buffer(ring, cb); 1831 if (ret) 1832 goto out_with_buf; 1833 1834 return 0; 1835 1836 out_with_buf: 1837 hns3_free_buffer(ring, cb); 1838 out: 1839 return ret; 1840 } 1841 1842 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i) 1843 { 1844 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]); 1845 1846 if (ret) 1847 return ret; 1848 1849 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 1850 1851 return 0; 1852 } 1853 1854 /* Allocate memory for raw pkg, and map with dma */ 1855 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 1856 { 1857 int i, j, ret; 1858 1859 for (i = 0; i < ring->desc_num; i++) { 1860 ret = hns3_alloc_buffer_attach(ring, i); 1861 if (ret) 1862 goto out_buffer_fail; 1863 } 1864 1865 return 0; 1866 1867 out_buffer_fail: 1868 for (j = i - 1; j >= 0; j--) 1869 hns3_free_buffer_detach(ring, j); 1870 return ret; 1871 } 1872 1873 /* detach a in-used buffer and replace with a reserved one */ 1874 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 1875 struct hns3_desc_cb *res_cb) 1876 { 1877 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 1878 ring->desc_cb[i] = *res_cb; 1879 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 1880 ring->desc[i].rx.bd_base_info = 0; 1881 } 1882 1883 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 1884 { 1885 ring->desc_cb[i].reuse_flag = 0; 1886 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma 1887 + ring->desc_cb[i].page_offset); 1888 ring->desc[i].rx.bd_base_info = 0; 1889 } 1890 1891 static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes, 1892 int *pkts) 1893 { 1894 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 1895 1896 (*pkts) += (desc_cb->type == DESC_TYPE_SKB); 1897 (*bytes) += desc_cb->length; 1898 /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/ 1899 hns3_free_buffer_detach(ring, ring->next_to_clean); 1900 1901 ring_ptr_move_fw(ring, next_to_clean); 1902 } 1903 1904 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h) 1905 { 1906 int u = ring->next_to_use; 1907 int c = ring->next_to_clean; 1908 1909 if (unlikely(h > ring->desc_num)) 1910 return 0; 1911 1912 return u > c ? (h > c && h <= u) : (h > c || h <= u); 1913 } 1914 1915 bool hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget) 1916 { 1917 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 1918 struct netdev_queue *dev_queue; 1919 int bytes, pkts; 1920 int head; 1921 1922 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG); 1923 rmb(); /* Make sure head is ready before touch any data */ 1924 1925 if (is_ring_empty(ring) || head == ring->next_to_clean) 1926 return true; /* no data to poll */ 1927 1928 if (unlikely(!is_valid_clean_head(ring, head))) { 1929 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head, 1930 ring->next_to_use, ring->next_to_clean); 1931 1932 u64_stats_update_begin(&ring->syncp); 1933 ring->stats.io_err_cnt++; 1934 u64_stats_update_end(&ring->syncp); 1935 return true; 1936 } 1937 1938 bytes = 0; 1939 pkts = 0; 1940 while (head != ring->next_to_clean && budget) { 1941 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts); 1942 /* Issue prefetch for next Tx descriptor */ 1943 prefetch(&ring->desc_cb[ring->next_to_clean]); 1944 budget--; 1945 } 1946 1947 ring->tqp_vector->tx_group.total_bytes += bytes; 1948 ring->tqp_vector->tx_group.total_packets += pkts; 1949 1950 u64_stats_update_begin(&ring->syncp); 1951 ring->stats.tx_bytes += bytes; 1952 ring->stats.tx_pkts += pkts; 1953 u64_stats_update_end(&ring->syncp); 1954 1955 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 1956 netdev_tx_completed_queue(dev_queue, pkts, bytes); 1957 1958 if (unlikely(pkts && netif_carrier_ok(netdev) && 1959 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) { 1960 /* Make sure that anybody stopping the queue after this 1961 * sees the new next_to_clean. 1962 */ 1963 smp_mb(); 1964 if (netif_tx_queue_stopped(dev_queue)) { 1965 netif_tx_wake_queue(dev_queue); 1966 ring->stats.restart_queue++; 1967 } 1968 } 1969 1970 return !!budget; 1971 } 1972 1973 static int hns3_desc_unused(struct hns3_enet_ring *ring) 1974 { 1975 int ntc = ring->next_to_clean; 1976 int ntu = ring->next_to_use; 1977 1978 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 1979 } 1980 1981 static void 1982 hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count) 1983 { 1984 struct hns3_desc_cb *desc_cb; 1985 struct hns3_desc_cb res_cbs; 1986 int i, ret; 1987 1988 for (i = 0; i < cleand_count; i++) { 1989 desc_cb = &ring->desc_cb[ring->next_to_use]; 1990 if (desc_cb->reuse_flag) { 1991 u64_stats_update_begin(&ring->syncp); 1992 ring->stats.reuse_pg_cnt++; 1993 u64_stats_update_end(&ring->syncp); 1994 1995 hns3_reuse_buffer(ring, ring->next_to_use); 1996 } else { 1997 ret = hns3_reserve_buffer_map(ring, &res_cbs); 1998 if (ret) { 1999 u64_stats_update_begin(&ring->syncp); 2000 ring->stats.sw_err_cnt++; 2001 u64_stats_update_end(&ring->syncp); 2002 2003 netdev_err(ring->tqp->handle->kinfo.netdev, 2004 "hnae reserve buffer map failed.\n"); 2005 break; 2006 } 2007 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 2008 } 2009 2010 ring_ptr_move_fw(ring, next_to_use); 2011 } 2012 2013 wmb(); /* Make all data has been write before submit */ 2014 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2015 } 2016 2017 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2018 struct hns3_enet_ring *ring, int pull_len, 2019 struct hns3_desc_cb *desc_cb) 2020 { 2021 struct hns3_desc *desc; 2022 u32 truesize; 2023 int size; 2024 int last_offset; 2025 bool twobufs; 2026 2027 twobufs = ((PAGE_SIZE < 8192) && 2028 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048); 2029 2030 desc = &ring->desc[ring->next_to_clean]; 2031 size = le16_to_cpu(desc->rx.size); 2032 2033 truesize = hnae3_buf_size(ring); 2034 2035 if (!twobufs) 2036 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring); 2037 2038 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2039 size - pull_len, truesize); 2040 2041 /* Avoid re-using remote pages,flag default unreuse */ 2042 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id())) 2043 return; 2044 2045 if (twobufs) { 2046 /* If we are only owner of page we can reuse it */ 2047 if (likely(page_count(desc_cb->priv) == 1)) { 2048 /* Flip page offset to other buffer */ 2049 desc_cb->page_offset ^= truesize; 2050 2051 desc_cb->reuse_flag = 1; 2052 /* bump ref count on page before it is given*/ 2053 get_page(desc_cb->priv); 2054 } 2055 return; 2056 } 2057 2058 /* Move offset up to the next cache line */ 2059 desc_cb->page_offset += truesize; 2060 2061 if (desc_cb->page_offset <= last_offset) { 2062 desc_cb->reuse_flag = 1; 2063 /* Bump ref count on page before it is given*/ 2064 get_page(desc_cb->priv); 2065 } 2066 } 2067 2068 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2069 struct hns3_desc *desc) 2070 { 2071 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2072 int l3_type, l4_type; 2073 u32 bd_base_info; 2074 int ol4_type; 2075 u32 l234info; 2076 2077 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2078 l234info = le32_to_cpu(desc->rx.l234_info); 2079 2080 skb->ip_summed = CHECKSUM_NONE; 2081 2082 skb_checksum_none_assert(skb); 2083 2084 if (!(netdev->features & NETIF_F_RXCSUM)) 2085 return; 2086 2087 /* check if hardware has done checksum */ 2088 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B)) 2089 return; 2090 2091 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) || 2092 hnae3_get_bit(l234info, HNS3_RXD_L4E_B) || 2093 hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) || 2094 hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) { 2095 netdev_err(netdev, "L3/L4 error pkt\n"); 2096 u64_stats_update_begin(&ring->syncp); 2097 ring->stats.l3l4_csum_err++; 2098 u64_stats_update_end(&ring->syncp); 2099 2100 return; 2101 } 2102 2103 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2104 HNS3_RXD_L3ID_S); 2105 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 2106 HNS3_RXD_L4ID_S); 2107 2108 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M, 2109 HNS3_RXD_OL4ID_S); 2110 switch (ol4_type) { 2111 case HNS3_OL4_TYPE_MAC_IN_UDP: 2112 case HNS3_OL4_TYPE_NVGRE: 2113 skb->csum_level = 1; 2114 /* fall through */ 2115 case HNS3_OL4_TYPE_NO_TUN: 2116 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 2117 if ((l3_type == HNS3_L3_TYPE_IPV4 || 2118 l3_type == HNS3_L3_TYPE_IPV6) && 2119 (l4_type == HNS3_L4_TYPE_UDP || 2120 l4_type == HNS3_L4_TYPE_TCP || 2121 l4_type == HNS3_L4_TYPE_SCTP)) 2122 skb->ip_summed = CHECKSUM_UNNECESSARY; 2123 break; 2124 } 2125 } 2126 2127 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 2128 { 2129 napi_gro_receive(&ring->tqp_vector->napi, skb); 2130 } 2131 2132 static u16 hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 2133 struct hns3_desc *desc, u32 l234info) 2134 { 2135 struct pci_dev *pdev = ring->tqp->handle->pdev; 2136 u16 vlan_tag; 2137 2138 if (pdev->revision == 0x20) { 2139 vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2140 if (!(vlan_tag & VLAN_VID_MASK)) 2141 vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2142 2143 return vlan_tag; 2144 } 2145 2146 #define HNS3_STRP_OUTER_VLAN 0x1 2147 #define HNS3_STRP_INNER_VLAN 0x2 2148 2149 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 2150 HNS3_RXD_STRP_TAGP_S)) { 2151 case HNS3_STRP_OUTER_VLAN: 2152 vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2153 break; 2154 case HNS3_STRP_INNER_VLAN: 2155 vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2156 break; 2157 default: 2158 vlan_tag = 0; 2159 break; 2160 } 2161 2162 return vlan_tag; 2163 } 2164 2165 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring, 2166 struct sk_buff **out_skb, int *out_bnum) 2167 { 2168 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2169 struct hns3_desc_cb *desc_cb; 2170 struct hns3_desc *desc; 2171 struct sk_buff *skb; 2172 unsigned char *va; 2173 u32 bd_base_info; 2174 int pull_len; 2175 u32 l234info; 2176 int length; 2177 int bnum; 2178 2179 desc = &ring->desc[ring->next_to_clean]; 2180 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2181 2182 prefetch(desc); 2183 2184 length = le16_to_cpu(desc->rx.size); 2185 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2186 2187 /* Check valid BD */ 2188 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) 2189 return -EFAULT; 2190 2191 va = (unsigned char *)desc_cb->buf + desc_cb->page_offset; 2192 2193 /* Prefetch first cache line of first page 2194 * Idea is to cache few bytes of the header of the packet. Our L1 Cache 2195 * line size is 64B so need to prefetch twice to make it 128B. But in 2196 * actual we can have greater size of caches with 128B Level 1 cache 2197 * lines. In such a case, single fetch would suffice to cache in the 2198 * relevant part of the header. 2199 */ 2200 prefetch(va); 2201 #if L1_CACHE_BYTES < 128 2202 prefetch(va + L1_CACHE_BYTES); 2203 #endif 2204 2205 skb = *out_skb = napi_alloc_skb(&ring->tqp_vector->napi, 2206 HNS3_RX_HEAD_SIZE); 2207 if (unlikely(!skb)) { 2208 netdev_err(netdev, "alloc rx skb fail\n"); 2209 2210 u64_stats_update_begin(&ring->syncp); 2211 ring->stats.sw_err_cnt++; 2212 u64_stats_update_end(&ring->syncp); 2213 2214 return -ENOMEM; 2215 } 2216 2217 prefetchw(skb->data); 2218 2219 bnum = 1; 2220 if (length <= HNS3_RX_HEAD_SIZE) { 2221 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 2222 2223 /* We can reuse buffer as-is, just make sure it is local */ 2224 if (likely(page_to_nid(desc_cb->priv) == numa_node_id())) 2225 desc_cb->reuse_flag = 1; 2226 else /* This page cannot be reused so discard it */ 2227 put_page(desc_cb->priv); 2228 2229 ring_ptr_move_fw(ring, next_to_clean); 2230 } else { 2231 u64_stats_update_begin(&ring->syncp); 2232 ring->stats.seg_pkt_cnt++; 2233 u64_stats_update_end(&ring->syncp); 2234 2235 pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE); 2236 2237 memcpy(__skb_put(skb, pull_len), va, 2238 ALIGN(pull_len, sizeof(long))); 2239 2240 hns3_nic_reuse_page(skb, 0, ring, pull_len, desc_cb); 2241 ring_ptr_move_fw(ring, next_to_clean); 2242 2243 while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) { 2244 desc = &ring->desc[ring->next_to_clean]; 2245 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2246 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2247 hns3_nic_reuse_page(skb, bnum, ring, 0, desc_cb); 2248 ring_ptr_move_fw(ring, next_to_clean); 2249 bnum++; 2250 } 2251 } 2252 2253 *out_bnum = bnum; 2254 2255 l234info = le32_to_cpu(desc->rx.l234_info); 2256 2257 /* Based on hw strategy, the tag offloaded will be stored at 2258 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 2259 * in one layer tag case. 2260 */ 2261 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 2262 u16 vlan_tag; 2263 2264 vlan_tag = hns3_parse_vlan_tag(ring, desc, l234info); 2265 if (vlan_tag & VLAN_VID_MASK) 2266 __vlan_hwaccel_put_tag(skb, 2267 htons(ETH_P_8021Q), 2268 vlan_tag); 2269 } 2270 2271 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) { 2272 netdev_err(netdev, "no valid bd,%016llx,%016llx\n", 2273 ((u64 *)desc)[0], ((u64 *)desc)[1]); 2274 u64_stats_update_begin(&ring->syncp); 2275 ring->stats.non_vld_descs++; 2276 u64_stats_update_end(&ring->syncp); 2277 2278 dev_kfree_skb_any(skb); 2279 return -EINVAL; 2280 } 2281 2282 if (unlikely((!desc->rx.pkt_len) || 2283 hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) { 2284 netdev_err(netdev, "truncated pkt\n"); 2285 u64_stats_update_begin(&ring->syncp); 2286 ring->stats.err_pkt_len++; 2287 u64_stats_update_end(&ring->syncp); 2288 2289 dev_kfree_skb_any(skb); 2290 return -EFAULT; 2291 } 2292 2293 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) { 2294 netdev_err(netdev, "L2 error pkt\n"); 2295 u64_stats_update_begin(&ring->syncp); 2296 ring->stats.l2_err++; 2297 u64_stats_update_end(&ring->syncp); 2298 2299 dev_kfree_skb_any(skb); 2300 return -EFAULT; 2301 } 2302 2303 u64_stats_update_begin(&ring->syncp); 2304 ring->stats.rx_pkts++; 2305 ring->stats.rx_bytes += skb->len; 2306 u64_stats_update_end(&ring->syncp); 2307 2308 ring->tqp_vector->rx_group.total_bytes += skb->len; 2309 2310 hns3_rx_checksum(ring, skb, desc); 2311 return 0; 2312 } 2313 2314 int hns3_clean_rx_ring( 2315 struct hns3_enet_ring *ring, int budget, 2316 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 2317 { 2318 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 2319 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2320 int recv_pkts, recv_bds, clean_count, err; 2321 int unused_count = hns3_desc_unused(ring); 2322 struct sk_buff *skb = NULL; 2323 int num, bnum = 0; 2324 2325 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG); 2326 rmb(); /* Make sure num taken effect before the other data is touched */ 2327 2328 recv_pkts = 0, recv_bds = 0, clean_count = 0; 2329 num -= unused_count; 2330 2331 while (recv_pkts < budget && recv_bds < num) { 2332 /* Reuse or realloc buffers */ 2333 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 2334 hns3_nic_alloc_rx_buffers(ring, 2335 clean_count + unused_count); 2336 clean_count = 0; 2337 unused_count = hns3_desc_unused(ring); 2338 } 2339 2340 /* Poll one pkt */ 2341 err = hns3_handle_rx_bd(ring, &skb, &bnum); 2342 if (unlikely(!skb)) /* This fault cannot be repaired */ 2343 goto out; 2344 2345 recv_bds += bnum; 2346 clean_count += bnum; 2347 if (unlikely(err)) { /* Do jump the err */ 2348 recv_pkts++; 2349 continue; 2350 } 2351 2352 /* Do update ip stack process */ 2353 skb->protocol = eth_type_trans(skb, netdev); 2354 rx_fn(ring, skb); 2355 2356 recv_pkts++; 2357 } 2358 2359 out: 2360 /* Make all data has been write before submit */ 2361 if (clean_count + unused_count > 0) 2362 hns3_nic_alloc_rx_buffers(ring, 2363 clean_count + unused_count); 2364 2365 return recv_pkts; 2366 } 2367 2368 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 2369 { 2370 struct hns3_enet_tqp_vector *tqp_vector = 2371 ring_group->ring->tqp_vector; 2372 enum hns3_flow_level_range new_flow_level; 2373 int packets_per_msecs; 2374 int bytes_per_msecs; 2375 u32 time_passed_ms; 2376 u16 new_int_gl; 2377 2378 if (!ring_group->coal.int_gl || !tqp_vector->last_jiffies) 2379 return false; 2380 2381 if (ring_group->total_packets == 0) { 2382 ring_group->coal.int_gl = HNS3_INT_GL_50K; 2383 ring_group->coal.flow_level = HNS3_FLOW_LOW; 2384 return true; 2385 } 2386 2387 /* Simple throttlerate management 2388 * 0-10MB/s lower (50000 ints/s) 2389 * 10-20MB/s middle (20000 ints/s) 2390 * 20-1249MB/s high (18000 ints/s) 2391 * > 40000pps ultra (8000 ints/s) 2392 */ 2393 new_flow_level = ring_group->coal.flow_level; 2394 new_int_gl = ring_group->coal.int_gl; 2395 time_passed_ms = 2396 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 2397 2398 if (!time_passed_ms) 2399 return false; 2400 2401 do_div(ring_group->total_packets, time_passed_ms); 2402 packets_per_msecs = ring_group->total_packets; 2403 2404 do_div(ring_group->total_bytes, time_passed_ms); 2405 bytes_per_msecs = ring_group->total_bytes; 2406 2407 #define HNS3_RX_LOW_BYTE_RATE 10000 2408 #define HNS3_RX_MID_BYTE_RATE 20000 2409 2410 switch (new_flow_level) { 2411 case HNS3_FLOW_LOW: 2412 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 2413 new_flow_level = HNS3_FLOW_MID; 2414 break; 2415 case HNS3_FLOW_MID: 2416 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 2417 new_flow_level = HNS3_FLOW_HIGH; 2418 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 2419 new_flow_level = HNS3_FLOW_LOW; 2420 break; 2421 case HNS3_FLOW_HIGH: 2422 case HNS3_FLOW_ULTRA: 2423 default: 2424 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 2425 new_flow_level = HNS3_FLOW_MID; 2426 break; 2427 } 2428 2429 #define HNS3_RX_ULTRA_PACKET_RATE 40 2430 2431 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 2432 &tqp_vector->rx_group == ring_group) 2433 new_flow_level = HNS3_FLOW_ULTRA; 2434 2435 switch (new_flow_level) { 2436 case HNS3_FLOW_LOW: 2437 new_int_gl = HNS3_INT_GL_50K; 2438 break; 2439 case HNS3_FLOW_MID: 2440 new_int_gl = HNS3_INT_GL_20K; 2441 break; 2442 case HNS3_FLOW_HIGH: 2443 new_int_gl = HNS3_INT_GL_18K; 2444 break; 2445 case HNS3_FLOW_ULTRA: 2446 new_int_gl = HNS3_INT_GL_8K; 2447 break; 2448 default: 2449 break; 2450 } 2451 2452 ring_group->total_bytes = 0; 2453 ring_group->total_packets = 0; 2454 ring_group->coal.flow_level = new_flow_level; 2455 if (new_int_gl != ring_group->coal.int_gl) { 2456 ring_group->coal.int_gl = new_int_gl; 2457 return true; 2458 } 2459 return false; 2460 } 2461 2462 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 2463 { 2464 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 2465 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 2466 bool rx_update, tx_update; 2467 2468 if (tqp_vector->int_adapt_down > 0) { 2469 tqp_vector->int_adapt_down--; 2470 return; 2471 } 2472 2473 if (rx_group->coal.gl_adapt_enable) { 2474 rx_update = hns3_get_new_int_gl(rx_group); 2475 if (rx_update) 2476 hns3_set_vector_coalesce_rx_gl(tqp_vector, 2477 rx_group->coal.int_gl); 2478 } 2479 2480 if (tx_group->coal.gl_adapt_enable) { 2481 tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group); 2482 if (tx_update) 2483 hns3_set_vector_coalesce_tx_gl(tqp_vector, 2484 tx_group->coal.int_gl); 2485 } 2486 2487 tqp_vector->last_jiffies = jiffies; 2488 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START; 2489 } 2490 2491 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 2492 { 2493 struct hns3_enet_ring *ring; 2494 int rx_pkt_total = 0; 2495 2496 struct hns3_enet_tqp_vector *tqp_vector = 2497 container_of(napi, struct hns3_enet_tqp_vector, napi); 2498 bool clean_complete = true; 2499 int rx_budget; 2500 2501 /* Since the actual Tx work is minimal, we can give the Tx a larger 2502 * budget and be more aggressive about cleaning up the Tx descriptors. 2503 */ 2504 hns3_for_each_ring(ring, tqp_vector->tx_group) { 2505 if (!hns3_clean_tx_ring(ring, budget)) 2506 clean_complete = false; 2507 } 2508 2509 /* make sure rx ring budget not smaller than 1 */ 2510 rx_budget = max(budget / tqp_vector->num_tqps, 1); 2511 2512 hns3_for_each_ring(ring, tqp_vector->rx_group) { 2513 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 2514 hns3_rx_skb); 2515 2516 if (rx_cleaned >= rx_budget) 2517 clean_complete = false; 2518 2519 rx_pkt_total += rx_cleaned; 2520 } 2521 2522 tqp_vector->rx_group.total_packets += rx_pkt_total; 2523 2524 if (!clean_complete) 2525 return budget; 2526 2527 napi_complete(napi); 2528 hns3_update_new_int_gl(tqp_vector); 2529 hns3_mask_vector_irq(tqp_vector, 1); 2530 2531 return rx_pkt_total; 2532 } 2533 2534 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 2535 struct hnae3_ring_chain_node *head) 2536 { 2537 struct pci_dev *pdev = tqp_vector->handle->pdev; 2538 struct hnae3_ring_chain_node *cur_chain = head; 2539 struct hnae3_ring_chain_node *chain; 2540 struct hns3_enet_ring *tx_ring; 2541 struct hns3_enet_ring *rx_ring; 2542 2543 tx_ring = tqp_vector->tx_group.ring; 2544 if (tx_ring) { 2545 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 2546 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 2547 HNAE3_RING_TYPE_TX); 2548 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2549 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 2550 2551 cur_chain->next = NULL; 2552 2553 while (tx_ring->next) { 2554 tx_ring = tx_ring->next; 2555 2556 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 2557 GFP_KERNEL); 2558 if (!chain) 2559 return -ENOMEM; 2560 2561 cur_chain->next = chain; 2562 chain->tqp_index = tx_ring->tqp->tqp_index; 2563 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 2564 HNAE3_RING_TYPE_TX); 2565 hnae3_set_field(chain->int_gl_idx, 2566 HNAE3_RING_GL_IDX_M, 2567 HNAE3_RING_GL_IDX_S, 2568 HNAE3_RING_GL_TX); 2569 2570 cur_chain = chain; 2571 } 2572 } 2573 2574 rx_ring = tqp_vector->rx_group.ring; 2575 if (!tx_ring && rx_ring) { 2576 cur_chain->next = NULL; 2577 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 2578 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 2579 HNAE3_RING_TYPE_RX); 2580 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2581 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 2582 2583 rx_ring = rx_ring->next; 2584 } 2585 2586 while (rx_ring) { 2587 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 2588 if (!chain) 2589 return -ENOMEM; 2590 2591 cur_chain->next = chain; 2592 chain->tqp_index = rx_ring->tqp->tqp_index; 2593 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 2594 HNAE3_RING_TYPE_RX); 2595 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2596 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 2597 2598 cur_chain = chain; 2599 2600 rx_ring = rx_ring->next; 2601 } 2602 2603 return 0; 2604 } 2605 2606 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 2607 struct hnae3_ring_chain_node *head) 2608 { 2609 struct pci_dev *pdev = tqp_vector->handle->pdev; 2610 struct hnae3_ring_chain_node *chain_tmp, *chain; 2611 2612 chain = head->next; 2613 2614 while (chain) { 2615 chain_tmp = chain->next; 2616 devm_kfree(&pdev->dev, chain); 2617 chain = chain_tmp; 2618 } 2619 } 2620 2621 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 2622 struct hns3_enet_ring *ring) 2623 { 2624 ring->next = group->ring; 2625 group->ring = ring; 2626 2627 group->count++; 2628 } 2629 2630 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 2631 { 2632 struct hnae3_ring_chain_node vector_ring_chain; 2633 struct hnae3_handle *h = priv->ae_handle; 2634 struct hns3_enet_tqp_vector *tqp_vector; 2635 int ret = 0; 2636 u16 i; 2637 2638 for (i = 0; i < priv->vector_num; i++) { 2639 tqp_vector = &priv->tqp_vector[i]; 2640 hns3_vector_gl_rl_init_hw(tqp_vector, priv); 2641 tqp_vector->num_tqps = 0; 2642 } 2643 2644 for (i = 0; i < h->kinfo.num_tqps; i++) { 2645 u16 vector_i = i % priv->vector_num; 2646 u16 tqp_num = h->kinfo.num_tqps; 2647 2648 tqp_vector = &priv->tqp_vector[vector_i]; 2649 2650 hns3_add_ring_to_group(&tqp_vector->tx_group, 2651 priv->ring_data[i].ring); 2652 2653 hns3_add_ring_to_group(&tqp_vector->rx_group, 2654 priv->ring_data[i + tqp_num].ring); 2655 2656 priv->ring_data[i].ring->tqp_vector = tqp_vector; 2657 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector; 2658 tqp_vector->num_tqps++; 2659 } 2660 2661 for (i = 0; i < priv->vector_num; i++) { 2662 tqp_vector = &priv->tqp_vector[i]; 2663 2664 tqp_vector->rx_group.total_bytes = 0; 2665 tqp_vector->rx_group.total_packets = 0; 2666 tqp_vector->tx_group.total_bytes = 0; 2667 tqp_vector->tx_group.total_packets = 0; 2668 tqp_vector->handle = h; 2669 2670 ret = hns3_get_vector_ring_chain(tqp_vector, 2671 &vector_ring_chain); 2672 if (ret) 2673 return ret; 2674 2675 ret = h->ae_algo->ops->map_ring_to_vector(h, 2676 tqp_vector->vector_irq, &vector_ring_chain); 2677 2678 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 2679 2680 if (ret) 2681 return ret; 2682 2683 netif_napi_add(priv->netdev, &tqp_vector->napi, 2684 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 2685 } 2686 2687 return 0; 2688 } 2689 2690 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 2691 { 2692 struct hnae3_handle *h = priv->ae_handle; 2693 struct hns3_enet_tqp_vector *tqp_vector; 2694 struct hnae3_vector_info *vector; 2695 struct pci_dev *pdev = h->pdev; 2696 u16 tqp_num = h->kinfo.num_tqps; 2697 u16 vector_num; 2698 int ret = 0; 2699 u16 i; 2700 2701 /* RSS size, cpu online and vector_num should be the same */ 2702 /* Should consider 2p/4p later */ 2703 vector_num = min_t(u16, num_online_cpus(), tqp_num); 2704 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 2705 GFP_KERNEL); 2706 if (!vector) 2707 return -ENOMEM; 2708 2709 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 2710 2711 priv->vector_num = vector_num; 2712 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 2713 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 2714 GFP_KERNEL); 2715 if (!priv->tqp_vector) { 2716 ret = -ENOMEM; 2717 goto out; 2718 } 2719 2720 for (i = 0; i < priv->vector_num; i++) { 2721 tqp_vector = &priv->tqp_vector[i]; 2722 tqp_vector->idx = i; 2723 tqp_vector->mask_addr = vector[i].io_addr; 2724 tqp_vector->vector_irq = vector[i].vector; 2725 hns3_vector_gl_rl_init(tqp_vector, priv); 2726 } 2727 2728 out: 2729 devm_kfree(&pdev->dev, vector); 2730 return ret; 2731 } 2732 2733 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 2734 { 2735 group->ring = NULL; 2736 group->count = 0; 2737 } 2738 2739 static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 2740 { 2741 struct hnae3_ring_chain_node vector_ring_chain; 2742 struct hnae3_handle *h = priv->ae_handle; 2743 struct hns3_enet_tqp_vector *tqp_vector; 2744 int i, ret; 2745 2746 for (i = 0; i < priv->vector_num; i++) { 2747 tqp_vector = &priv->tqp_vector[i]; 2748 2749 ret = hns3_get_vector_ring_chain(tqp_vector, 2750 &vector_ring_chain); 2751 if (ret) 2752 return ret; 2753 2754 ret = h->ae_algo->ops->unmap_ring_from_vector(h, 2755 tqp_vector->vector_irq, &vector_ring_chain); 2756 if (ret) 2757 return ret; 2758 2759 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 2760 2761 if (priv->tqp_vector[i].irq_init_flag == HNS3_VECTOR_INITED) { 2762 (void)irq_set_affinity_hint( 2763 priv->tqp_vector[i].vector_irq, 2764 NULL); 2765 free_irq(priv->tqp_vector[i].vector_irq, 2766 &priv->tqp_vector[i]); 2767 } 2768 2769 priv->ring_data[i].ring->irq_init_flag = HNS3_VECTOR_NOT_INITED; 2770 hns3_clear_ring_group(&tqp_vector->rx_group); 2771 hns3_clear_ring_group(&tqp_vector->tx_group); 2772 netif_napi_del(&priv->tqp_vector[i].napi); 2773 } 2774 2775 return 0; 2776 } 2777 2778 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 2779 { 2780 struct hnae3_handle *h = priv->ae_handle; 2781 struct pci_dev *pdev = h->pdev; 2782 int i, ret; 2783 2784 for (i = 0; i < priv->vector_num; i++) { 2785 struct hns3_enet_tqp_vector *tqp_vector; 2786 2787 tqp_vector = &priv->tqp_vector[i]; 2788 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 2789 if (ret) 2790 return ret; 2791 } 2792 2793 devm_kfree(&pdev->dev, priv->tqp_vector); 2794 return 0; 2795 } 2796 2797 static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 2798 int ring_type) 2799 { 2800 struct hns3_nic_ring_data *ring_data = priv->ring_data; 2801 int queue_num = priv->ae_handle->kinfo.num_tqps; 2802 struct pci_dev *pdev = priv->ae_handle->pdev; 2803 struct hns3_enet_ring *ring; 2804 2805 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL); 2806 if (!ring) 2807 return -ENOMEM; 2808 2809 if (ring_type == HNAE3_RING_TYPE_TX) { 2810 ring_data[q->tqp_index].ring = ring; 2811 ring_data[q->tqp_index].queue_index = q->tqp_index; 2812 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET; 2813 } else { 2814 ring_data[q->tqp_index + queue_num].ring = ring; 2815 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index; 2816 ring->io_base = q->io_base; 2817 } 2818 2819 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 2820 2821 ring->tqp = q; 2822 ring->desc = NULL; 2823 ring->desc_cb = NULL; 2824 ring->dev = priv->dev; 2825 ring->desc_dma_addr = 0; 2826 ring->buf_size = q->buf_size; 2827 ring->desc_num = q->desc_num; 2828 ring->next_to_use = 0; 2829 ring->next_to_clean = 0; 2830 2831 return 0; 2832 } 2833 2834 static int hns3_queue_to_ring(struct hnae3_queue *tqp, 2835 struct hns3_nic_priv *priv) 2836 { 2837 int ret; 2838 2839 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 2840 if (ret) 2841 return ret; 2842 2843 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 2844 if (ret) 2845 return ret; 2846 2847 return 0; 2848 } 2849 2850 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 2851 { 2852 struct hnae3_handle *h = priv->ae_handle; 2853 struct pci_dev *pdev = h->pdev; 2854 int i, ret; 2855 2856 priv->ring_data = devm_kzalloc(&pdev->dev, 2857 array3_size(h->kinfo.num_tqps, 2858 sizeof(*priv->ring_data), 2859 2), 2860 GFP_KERNEL); 2861 if (!priv->ring_data) 2862 return -ENOMEM; 2863 2864 for (i = 0; i < h->kinfo.num_tqps; i++) { 2865 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv); 2866 if (ret) 2867 goto err; 2868 } 2869 2870 return 0; 2871 err: 2872 devm_kfree(&pdev->dev, priv->ring_data); 2873 return ret; 2874 } 2875 2876 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 2877 { 2878 struct hnae3_handle *h = priv->ae_handle; 2879 int i; 2880 2881 for (i = 0; i < h->kinfo.num_tqps; i++) { 2882 devm_kfree(priv->dev, priv->ring_data[i].ring); 2883 devm_kfree(priv->dev, 2884 priv->ring_data[i + h->kinfo.num_tqps].ring); 2885 } 2886 devm_kfree(priv->dev, priv->ring_data); 2887 } 2888 2889 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 2890 { 2891 int ret; 2892 2893 if (ring->desc_num <= 0 || ring->buf_size <= 0) 2894 return -EINVAL; 2895 2896 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]), 2897 GFP_KERNEL); 2898 if (!ring->desc_cb) { 2899 ret = -ENOMEM; 2900 goto out; 2901 } 2902 2903 ret = hns3_alloc_desc(ring); 2904 if (ret) 2905 goto out_with_desc_cb; 2906 2907 if (!HNAE3_IS_TX_RING(ring)) { 2908 ret = hns3_alloc_ring_buffers(ring); 2909 if (ret) 2910 goto out_with_desc; 2911 } 2912 2913 return 0; 2914 2915 out_with_desc: 2916 hns3_free_desc(ring); 2917 out_with_desc_cb: 2918 kfree(ring->desc_cb); 2919 ring->desc_cb = NULL; 2920 out: 2921 return ret; 2922 } 2923 2924 static void hns3_fini_ring(struct hns3_enet_ring *ring) 2925 { 2926 hns3_free_desc(ring); 2927 kfree(ring->desc_cb); 2928 ring->desc_cb = NULL; 2929 ring->next_to_clean = 0; 2930 ring->next_to_use = 0; 2931 } 2932 2933 static int hns3_buf_size2type(u32 buf_size) 2934 { 2935 int bd_size_type; 2936 2937 switch (buf_size) { 2938 case 512: 2939 bd_size_type = HNS3_BD_SIZE_512_TYPE; 2940 break; 2941 case 1024: 2942 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 2943 break; 2944 case 2048: 2945 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 2946 break; 2947 case 4096: 2948 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 2949 break; 2950 default: 2951 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 2952 } 2953 2954 return bd_size_type; 2955 } 2956 2957 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 2958 { 2959 dma_addr_t dma = ring->desc_dma_addr; 2960 struct hnae3_queue *q = ring->tqp; 2961 2962 if (!HNAE3_IS_TX_RING(ring)) { 2963 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, 2964 (u32)dma); 2965 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 2966 (u32)((dma >> 31) >> 1)); 2967 2968 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 2969 hns3_buf_size2type(ring->buf_size)); 2970 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 2971 ring->desc_num / 8 - 1); 2972 2973 } else { 2974 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 2975 (u32)dma); 2976 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 2977 (u32)((dma >> 31) >> 1)); 2978 2979 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 2980 ring->desc_num / 8 - 1); 2981 } 2982 } 2983 2984 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 2985 { 2986 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 2987 int i; 2988 2989 for (i = 0; i < HNAE3_MAX_TC; i++) { 2990 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i]; 2991 int j; 2992 2993 if (!tc_info->enable) 2994 continue; 2995 2996 for (j = 0; j < tc_info->tqp_count; j++) { 2997 struct hnae3_queue *q; 2998 2999 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp; 3000 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, 3001 tc_info->tc); 3002 } 3003 } 3004 } 3005 3006 int hns3_init_all_ring(struct hns3_nic_priv *priv) 3007 { 3008 struct hnae3_handle *h = priv->ae_handle; 3009 int ring_num = h->kinfo.num_tqps * 2; 3010 int i, j; 3011 int ret; 3012 3013 for (i = 0; i < ring_num; i++) { 3014 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring); 3015 if (ret) { 3016 dev_err(priv->dev, 3017 "Alloc ring memory fail! ret=%d\n", ret); 3018 goto out_when_alloc_ring_memory; 3019 } 3020 3021 u64_stats_init(&priv->ring_data[i].ring->syncp); 3022 } 3023 3024 return 0; 3025 3026 out_when_alloc_ring_memory: 3027 for (j = i - 1; j >= 0; j--) 3028 hns3_fini_ring(priv->ring_data[j].ring); 3029 3030 return -ENOMEM; 3031 } 3032 3033 int hns3_uninit_all_ring(struct hns3_nic_priv *priv) 3034 { 3035 struct hnae3_handle *h = priv->ae_handle; 3036 int i; 3037 3038 for (i = 0; i < h->kinfo.num_tqps; i++) { 3039 if (h->ae_algo->ops->reset_queue) 3040 h->ae_algo->ops->reset_queue(h, i); 3041 3042 hns3_fini_ring(priv->ring_data[i].ring); 3043 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring); 3044 } 3045 return 0; 3046 } 3047 3048 /* Set mac addr if it is configured. or leave it to the AE driver */ 3049 static void hns3_init_mac_addr(struct net_device *netdev, bool init) 3050 { 3051 struct hns3_nic_priv *priv = netdev_priv(netdev); 3052 struct hnae3_handle *h = priv->ae_handle; 3053 u8 mac_addr_temp[ETH_ALEN]; 3054 3055 if (h->ae_algo->ops->get_mac_addr && init) { 3056 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 3057 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 3058 } 3059 3060 /* Check if the MAC address is valid, if not get a random one */ 3061 if (!is_valid_ether_addr(netdev->dev_addr)) { 3062 eth_hw_addr_random(netdev); 3063 dev_warn(priv->dev, "using random MAC address %pM\n", 3064 netdev->dev_addr); 3065 } 3066 3067 if (h->ae_algo->ops->set_mac_addr) 3068 h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 3069 3070 } 3071 3072 static void hns3_uninit_mac_addr(struct net_device *netdev) 3073 { 3074 struct hns3_nic_priv *priv = netdev_priv(netdev); 3075 struct hnae3_handle *h = priv->ae_handle; 3076 3077 if (h->ae_algo->ops->rm_uc_addr) 3078 h->ae_algo->ops->rm_uc_addr(h, netdev->dev_addr); 3079 } 3080 3081 static void hns3_nic_set_priv_ops(struct net_device *netdev) 3082 { 3083 struct hns3_nic_priv *priv = netdev_priv(netdev); 3084 3085 if ((netdev->features & NETIF_F_TSO) || 3086 (netdev->features & NETIF_F_TSO6)) { 3087 priv->ops.fill_desc = hns3_fill_desc_tso; 3088 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 3089 } else { 3090 priv->ops.fill_desc = hns3_fill_desc; 3091 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 3092 } 3093 } 3094 3095 static int hns3_client_init(struct hnae3_handle *handle) 3096 { 3097 struct pci_dev *pdev = handle->pdev; 3098 struct hns3_nic_priv *priv; 3099 struct net_device *netdev; 3100 int ret; 3101 3102 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), 3103 hns3_get_max_available_channels(handle)); 3104 if (!netdev) 3105 return -ENOMEM; 3106 3107 priv = netdev_priv(netdev); 3108 priv->dev = &pdev->dev; 3109 priv->netdev = netdev; 3110 priv->ae_handle = handle; 3111 priv->ae_handle->last_reset_time = jiffies; 3112 priv->tx_timeout_count = 0; 3113 3114 handle->kinfo.netdev = netdev; 3115 handle->priv = (void *)priv; 3116 3117 hns3_init_mac_addr(netdev, true); 3118 3119 hns3_set_default_feature(netdev); 3120 3121 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 3122 netdev->priv_flags |= IFF_UNICAST_FLT; 3123 netdev->netdev_ops = &hns3_nic_netdev_ops; 3124 SET_NETDEV_DEV(netdev, &pdev->dev); 3125 hns3_ethtool_set_ops(netdev); 3126 hns3_nic_set_priv_ops(netdev); 3127 3128 /* Carrier off reporting is important to ethtool even BEFORE open */ 3129 netif_carrier_off(netdev); 3130 3131 if (handle->flags & HNAE3_SUPPORT_VF) 3132 handle->reset_level = HNAE3_VF_RESET; 3133 else 3134 handle->reset_level = HNAE3_FUNC_RESET; 3135 3136 ret = hns3_get_ring_config(priv); 3137 if (ret) { 3138 ret = -ENOMEM; 3139 goto out_get_ring_cfg; 3140 } 3141 3142 ret = hns3_nic_alloc_vector_data(priv); 3143 if (ret) { 3144 ret = -ENOMEM; 3145 goto out_alloc_vector_data; 3146 } 3147 3148 ret = hns3_nic_init_vector_data(priv); 3149 if (ret) { 3150 ret = -ENOMEM; 3151 goto out_init_vector_data; 3152 } 3153 3154 ret = hns3_init_all_ring(priv); 3155 if (ret) { 3156 ret = -ENOMEM; 3157 goto out_init_ring_data; 3158 } 3159 3160 ret = register_netdev(netdev); 3161 if (ret) { 3162 dev_err(priv->dev, "probe register netdev fail!\n"); 3163 goto out_reg_netdev_fail; 3164 } 3165 3166 hns3_dcbnl_setup(handle); 3167 3168 /* MTU range: (ETH_MIN_MTU(kernel default) - 9706) */ 3169 netdev->max_mtu = HNS3_MAX_MTU - (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); 3170 3171 return ret; 3172 3173 out_reg_netdev_fail: 3174 out_init_ring_data: 3175 (void)hns3_nic_uninit_vector_data(priv); 3176 out_init_vector_data: 3177 hns3_nic_dealloc_vector_data(priv); 3178 out_alloc_vector_data: 3179 priv->ring_data = NULL; 3180 out_get_ring_cfg: 3181 priv->ae_handle = NULL; 3182 free_netdev(netdev); 3183 return ret; 3184 } 3185 3186 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 3187 { 3188 struct net_device *netdev = handle->kinfo.netdev; 3189 struct hns3_nic_priv *priv = netdev_priv(netdev); 3190 int ret; 3191 3192 if (netdev->reg_state != NETREG_UNINITIALIZED) 3193 unregister_netdev(netdev); 3194 3195 hns3_force_clear_all_rx_ring(handle); 3196 3197 ret = hns3_nic_uninit_vector_data(priv); 3198 if (ret) 3199 netdev_err(netdev, "uninit vector error\n"); 3200 3201 ret = hns3_nic_dealloc_vector_data(priv); 3202 if (ret) 3203 netdev_err(netdev, "dealloc vector error\n"); 3204 3205 ret = hns3_uninit_all_ring(priv); 3206 if (ret) 3207 netdev_err(netdev, "uninit ring error\n"); 3208 3209 hns3_put_ring_config(priv); 3210 3211 priv->ring_data = NULL; 3212 3213 hns3_uninit_mac_addr(netdev); 3214 3215 free_netdev(netdev); 3216 } 3217 3218 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 3219 { 3220 struct net_device *netdev = handle->kinfo.netdev; 3221 3222 if (!netdev) 3223 return; 3224 3225 if (linkup) { 3226 netif_carrier_on(netdev); 3227 netif_tx_wake_all_queues(netdev); 3228 netdev_info(netdev, "link up\n"); 3229 } else { 3230 netif_carrier_off(netdev); 3231 netif_tx_stop_all_queues(netdev); 3232 netdev_info(netdev, "link down\n"); 3233 } 3234 } 3235 3236 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc) 3237 { 3238 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3239 struct net_device *ndev = kinfo->netdev; 3240 bool if_running; 3241 int ret; 3242 3243 if (tc > HNAE3_MAX_TC) 3244 return -EINVAL; 3245 3246 if (!ndev) 3247 return -ENODEV; 3248 3249 if_running = netif_running(ndev); 3250 3251 if (if_running) { 3252 (void)hns3_nic_net_stop(ndev); 3253 msleep(100); 3254 } 3255 3256 ret = (kinfo->dcb_ops && kinfo->dcb_ops->map_update) ? 3257 kinfo->dcb_ops->map_update(handle) : -EOPNOTSUPP; 3258 if (ret) 3259 goto err_out; 3260 3261 ret = hns3_nic_set_real_num_queue(ndev); 3262 3263 err_out: 3264 if (if_running) 3265 (void)hns3_nic_net_open(ndev); 3266 3267 return ret; 3268 } 3269 3270 static void hns3_recover_hw_addr(struct net_device *ndev) 3271 { 3272 struct netdev_hw_addr_list *list; 3273 struct netdev_hw_addr *ha, *tmp; 3274 3275 /* go through and sync uc_addr entries to the device */ 3276 list = &ndev->uc; 3277 list_for_each_entry_safe(ha, tmp, &list->list, list) 3278 hns3_nic_uc_sync(ndev, ha->addr); 3279 3280 /* go through and sync mc_addr entries to the device */ 3281 list = &ndev->mc; 3282 list_for_each_entry_safe(ha, tmp, &list->list, list) 3283 hns3_nic_mc_sync(ndev, ha->addr); 3284 } 3285 3286 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 3287 { 3288 while (ring->next_to_clean != ring->next_to_use) { 3289 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 3290 hns3_free_buffer_detach(ring, ring->next_to_clean); 3291 ring_ptr_move_fw(ring, next_to_clean); 3292 } 3293 } 3294 3295 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 3296 { 3297 struct hns3_desc_cb res_cbs; 3298 int ret; 3299 3300 while (ring->next_to_use != ring->next_to_clean) { 3301 /* When a buffer is not reused, it's memory has been 3302 * freed in hns3_handle_rx_bd or will be freed by 3303 * stack, so we need to replace the buffer here. 3304 */ 3305 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3306 ret = hns3_reserve_buffer_map(ring, &res_cbs); 3307 if (ret) { 3308 u64_stats_update_begin(&ring->syncp); 3309 ring->stats.sw_err_cnt++; 3310 u64_stats_update_end(&ring->syncp); 3311 /* if alloc new buffer fail, exit directly 3312 * and reclear in up flow. 3313 */ 3314 netdev_warn(ring->tqp->handle->kinfo.netdev, 3315 "reserve buffer map failed, ret = %d\n", 3316 ret); 3317 return ret; 3318 } 3319 hns3_replace_buffer(ring, ring->next_to_use, 3320 &res_cbs); 3321 } 3322 ring_ptr_move_fw(ring, next_to_use); 3323 } 3324 3325 return 0; 3326 } 3327 3328 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 3329 { 3330 while (ring->next_to_use != ring->next_to_clean) { 3331 /* When a buffer is not reused, it's memory has been 3332 * freed in hns3_handle_rx_bd or will be freed by 3333 * stack, so only need to unmap the buffer here. 3334 */ 3335 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3336 hns3_unmap_buffer(ring, 3337 &ring->desc_cb[ring->next_to_use]); 3338 ring->desc_cb[ring->next_to_use].dma = 0; 3339 } 3340 3341 ring_ptr_move_fw(ring, next_to_use); 3342 } 3343 } 3344 3345 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h) 3346 { 3347 struct net_device *ndev = h->kinfo.netdev; 3348 struct hns3_nic_priv *priv = netdev_priv(ndev); 3349 struct hns3_enet_ring *ring; 3350 u32 i; 3351 3352 for (i = 0; i < h->kinfo.num_tqps; i++) { 3353 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3354 hns3_force_clear_rx_ring(ring); 3355 } 3356 } 3357 3358 static void hns3_clear_all_ring(struct hnae3_handle *h) 3359 { 3360 struct net_device *ndev = h->kinfo.netdev; 3361 struct hns3_nic_priv *priv = netdev_priv(ndev); 3362 u32 i; 3363 3364 for (i = 0; i < h->kinfo.num_tqps; i++) { 3365 struct netdev_queue *dev_queue; 3366 struct hns3_enet_ring *ring; 3367 3368 ring = priv->ring_data[i].ring; 3369 hns3_clear_tx_ring(ring); 3370 dev_queue = netdev_get_tx_queue(ndev, 3371 priv->ring_data[i].queue_index); 3372 netdev_tx_reset_queue(dev_queue); 3373 3374 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3375 /* Continue to clear other rings even if clearing some 3376 * rings failed. 3377 */ 3378 hns3_clear_rx_ring(ring); 3379 } 3380 } 3381 3382 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 3383 { 3384 struct net_device *ndev = h->kinfo.netdev; 3385 struct hns3_nic_priv *priv = netdev_priv(ndev); 3386 struct hns3_enet_ring *rx_ring; 3387 int i, j; 3388 int ret; 3389 3390 for (i = 0; i < h->kinfo.num_tqps; i++) { 3391 h->ae_algo->ops->reset_queue(h, i); 3392 hns3_init_ring_hw(priv->ring_data[i].ring); 3393 3394 /* We need to clear tx ring here because self test will 3395 * use the ring and will not run down before up 3396 */ 3397 hns3_clear_tx_ring(priv->ring_data[i].ring); 3398 priv->ring_data[i].ring->next_to_clean = 0; 3399 priv->ring_data[i].ring->next_to_use = 0; 3400 3401 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3402 hns3_init_ring_hw(rx_ring); 3403 ret = hns3_clear_rx_ring(rx_ring); 3404 if (ret) 3405 return ret; 3406 3407 /* We can not know the hardware head and tail when this 3408 * function is called in reset flow, so we reuse all desc. 3409 */ 3410 for (j = 0; j < rx_ring->desc_num; j++) 3411 hns3_reuse_buffer(rx_ring, j); 3412 3413 rx_ring->next_to_clean = 0; 3414 rx_ring->next_to_use = 0; 3415 } 3416 3417 hns3_init_tx_ring_tc(priv); 3418 3419 return 0; 3420 } 3421 3422 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 3423 { 3424 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3425 struct net_device *ndev = kinfo->netdev; 3426 3427 if (!netif_running(ndev)) 3428 return 0; 3429 3430 return hns3_nic_net_stop(ndev); 3431 } 3432 3433 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 3434 { 3435 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3436 int ret = 0; 3437 3438 if (netif_running(kinfo->netdev)) { 3439 ret = hns3_nic_net_up(kinfo->netdev); 3440 if (ret) { 3441 netdev_err(kinfo->netdev, 3442 "hns net up fail, ret=%d!\n", ret); 3443 return ret; 3444 } 3445 handle->last_reset_time = jiffies; 3446 } 3447 3448 return ret; 3449 } 3450 3451 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 3452 { 3453 struct net_device *netdev = handle->kinfo.netdev; 3454 struct hns3_nic_priv *priv = netdev_priv(netdev); 3455 int ret; 3456 3457 hns3_init_mac_addr(netdev, false); 3458 hns3_nic_set_rx_mode(netdev); 3459 hns3_recover_hw_addr(netdev); 3460 3461 /* Hardware table is only clear when pf resets */ 3462 if (!(handle->flags & HNAE3_SUPPORT_VF)) 3463 hns3_restore_vlan(netdev); 3464 3465 /* Carrier off reporting is important to ethtool even BEFORE open */ 3466 netif_carrier_off(netdev); 3467 3468 ret = hns3_nic_init_vector_data(priv); 3469 if (ret) 3470 return ret; 3471 3472 ret = hns3_init_all_ring(priv); 3473 if (ret) { 3474 hns3_nic_uninit_vector_data(priv); 3475 priv->ring_data = NULL; 3476 } 3477 3478 return ret; 3479 } 3480 3481 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 3482 { 3483 struct net_device *netdev = handle->kinfo.netdev; 3484 struct hns3_nic_priv *priv = netdev_priv(netdev); 3485 int ret; 3486 3487 hns3_force_clear_all_rx_ring(handle); 3488 3489 ret = hns3_nic_uninit_vector_data(priv); 3490 if (ret) { 3491 netdev_err(netdev, "uninit vector error\n"); 3492 return ret; 3493 } 3494 3495 ret = hns3_uninit_all_ring(priv); 3496 if (ret) 3497 netdev_err(netdev, "uninit ring error\n"); 3498 3499 hns3_uninit_mac_addr(netdev); 3500 3501 return ret; 3502 } 3503 3504 static int hns3_reset_notify(struct hnae3_handle *handle, 3505 enum hnae3_reset_notify_type type) 3506 { 3507 int ret = 0; 3508 3509 switch (type) { 3510 case HNAE3_UP_CLIENT: 3511 ret = hns3_reset_notify_up_enet(handle); 3512 break; 3513 case HNAE3_DOWN_CLIENT: 3514 ret = hns3_reset_notify_down_enet(handle); 3515 break; 3516 case HNAE3_INIT_CLIENT: 3517 ret = hns3_reset_notify_init_enet(handle); 3518 break; 3519 case HNAE3_UNINIT_CLIENT: 3520 ret = hns3_reset_notify_uninit_enet(handle); 3521 break; 3522 default: 3523 break; 3524 } 3525 3526 return ret; 3527 } 3528 3529 static void hns3_restore_coal(struct hns3_nic_priv *priv, 3530 struct hns3_enet_coalesce *tx, 3531 struct hns3_enet_coalesce *rx) 3532 { 3533 u16 vector_num = priv->vector_num; 3534 int i; 3535 3536 for (i = 0; i < vector_num; i++) { 3537 memcpy(&priv->tqp_vector[i].tx_group.coal, tx, 3538 sizeof(struct hns3_enet_coalesce)); 3539 memcpy(&priv->tqp_vector[i].rx_group.coal, rx, 3540 sizeof(struct hns3_enet_coalesce)); 3541 } 3542 } 3543 3544 static int hns3_modify_tqp_num(struct net_device *netdev, u16 new_tqp_num, 3545 struct hns3_enet_coalesce *tx, 3546 struct hns3_enet_coalesce *rx) 3547 { 3548 struct hns3_nic_priv *priv = netdev_priv(netdev); 3549 struct hnae3_handle *h = hns3_get_handle(netdev); 3550 int ret; 3551 3552 ret = h->ae_algo->ops->set_channels(h, new_tqp_num); 3553 if (ret) 3554 return ret; 3555 3556 ret = hns3_get_ring_config(priv); 3557 if (ret) 3558 return ret; 3559 3560 ret = hns3_nic_alloc_vector_data(priv); 3561 if (ret) 3562 goto err_alloc_vector; 3563 3564 hns3_restore_coal(priv, tx, rx); 3565 3566 ret = hns3_nic_init_vector_data(priv); 3567 if (ret) 3568 goto err_uninit_vector; 3569 3570 ret = hns3_init_all_ring(priv); 3571 if (ret) 3572 goto err_put_ring; 3573 3574 return 0; 3575 3576 err_put_ring: 3577 hns3_put_ring_config(priv); 3578 err_uninit_vector: 3579 hns3_nic_uninit_vector_data(priv); 3580 err_alloc_vector: 3581 hns3_nic_dealloc_vector_data(priv); 3582 return ret; 3583 } 3584 3585 static int hns3_adjust_tqps_num(u8 num_tc, u32 new_tqp_num) 3586 { 3587 return (new_tqp_num / num_tc) * num_tc; 3588 } 3589 3590 int hns3_set_channels(struct net_device *netdev, 3591 struct ethtool_channels *ch) 3592 { 3593 struct hns3_nic_priv *priv = netdev_priv(netdev); 3594 struct hnae3_handle *h = hns3_get_handle(netdev); 3595 struct hnae3_knic_private_info *kinfo = &h->kinfo; 3596 struct hns3_enet_coalesce tx_coal, rx_coal; 3597 bool if_running = netif_running(netdev); 3598 u32 new_tqp_num = ch->combined_count; 3599 u16 org_tqp_num; 3600 int ret; 3601 3602 if (ch->rx_count || ch->tx_count) 3603 return -EINVAL; 3604 3605 if (new_tqp_num > hns3_get_max_available_channels(h) || 3606 new_tqp_num < kinfo->num_tc) { 3607 dev_err(&netdev->dev, 3608 "Change tqps fail, the tqp range is from %d to %d", 3609 kinfo->num_tc, 3610 hns3_get_max_available_channels(h)); 3611 return -EINVAL; 3612 } 3613 3614 new_tqp_num = hns3_adjust_tqps_num(kinfo->num_tc, new_tqp_num); 3615 if (kinfo->num_tqps == new_tqp_num) 3616 return 0; 3617 3618 if (if_running) 3619 hns3_nic_net_stop(netdev); 3620 3621 ret = hns3_nic_uninit_vector_data(priv); 3622 if (ret) { 3623 dev_err(&netdev->dev, 3624 "Unbind vector with tqp fail, nothing is changed"); 3625 goto open_netdev; 3626 } 3627 3628 /* Changing the tqp num may also change the vector num, 3629 * ethtool only support setting and querying one coal 3630 * configuation for now, so save the vector 0' coal 3631 * configuation here in order to restore it. 3632 */ 3633 memcpy(&tx_coal, &priv->tqp_vector[0].tx_group.coal, 3634 sizeof(struct hns3_enet_coalesce)); 3635 memcpy(&rx_coal, &priv->tqp_vector[0].rx_group.coal, 3636 sizeof(struct hns3_enet_coalesce)); 3637 3638 hns3_nic_dealloc_vector_data(priv); 3639 3640 hns3_uninit_all_ring(priv); 3641 hns3_put_ring_config(priv); 3642 3643 org_tqp_num = h->kinfo.num_tqps; 3644 ret = hns3_modify_tqp_num(netdev, new_tqp_num, &tx_coal, &rx_coal); 3645 if (ret) { 3646 ret = hns3_modify_tqp_num(netdev, org_tqp_num, 3647 &tx_coal, &rx_coal); 3648 if (ret) { 3649 /* If revert to old tqp failed, fatal error occurred */ 3650 dev_err(&netdev->dev, 3651 "Revert to old tqp num fail, ret=%d", ret); 3652 return ret; 3653 } 3654 dev_info(&netdev->dev, 3655 "Change tqp num fail, Revert to old tqp num"); 3656 } 3657 3658 open_netdev: 3659 if (if_running) 3660 hns3_nic_net_open(netdev); 3661 3662 return ret; 3663 } 3664 3665 static const struct hnae3_client_ops client_ops = { 3666 .init_instance = hns3_client_init, 3667 .uninit_instance = hns3_client_uninit, 3668 .link_status_change = hns3_link_status_change, 3669 .setup_tc = hns3_client_setup_tc, 3670 .reset_notify = hns3_reset_notify, 3671 }; 3672 3673 /* hns3_init_module - Driver registration routine 3674 * hns3_init_module is the first routine called when the driver is 3675 * loaded. All it does is register with the PCI subsystem. 3676 */ 3677 static int __init hns3_init_module(void) 3678 { 3679 int ret; 3680 3681 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 3682 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 3683 3684 client.type = HNAE3_CLIENT_KNIC; 3685 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s", 3686 hns3_driver_name); 3687 3688 client.ops = &client_ops; 3689 3690 INIT_LIST_HEAD(&client.node); 3691 3692 ret = hnae3_register_client(&client); 3693 if (ret) 3694 return ret; 3695 3696 ret = pci_register_driver(&hns3_driver); 3697 if (ret) 3698 hnae3_unregister_client(&client); 3699 3700 return ret; 3701 } 3702 module_init(hns3_init_module); 3703 3704 /* hns3_exit_module - Driver exit cleanup routine 3705 * hns3_exit_module is called just before the driver is removed 3706 * from memory. 3707 */ 3708 static void __exit hns3_exit_module(void) 3709 { 3710 pci_unregister_driver(&hns3_driver); 3711 hnae3_unregister_client(&client); 3712 } 3713 module_exit(hns3_exit_module); 3714 3715 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 3716 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3717 MODULE_LICENSE("GPL"); 3718 MODULE_ALIAS("pci:hns-nic"); 3719 MODULE_VERSION(HNS3_MOD_VERSION); 3720