1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #ifdef CONFIG_RFS_ACCEL 8 #include <linux/cpu_rmap.h> 9 #endif 10 #include <linux/if_vlan.h> 11 #include <linux/irq.h> 12 #include <linux/ip.h> 13 #include <linux/ipv6.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/aer.h> 17 #include <linux/skbuff.h> 18 #include <linux/sctp.h> 19 #include <net/gre.h> 20 #include <net/gro.h> 21 #include <net/ip6_checksum.h> 22 #include <net/pkt_cls.h> 23 #include <net/pkt_sched.h> 24 #include <net/tcp.h> 25 #include <net/vxlan.h> 26 #include <net/geneve.h> 27 28 #include "hnae3.h" 29 #include "hns3_enet.h" 30 /* All hns3 tracepoints are defined by the include below, which 31 * must be included exactly once across the whole kernel with 32 * CREATE_TRACE_POINTS defined 33 */ 34 #define CREATE_TRACE_POINTS 35 #include "hns3_trace.h" 36 37 #define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift)) 38 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE) 39 40 #define hns3_rl_err(fmt, ...) \ 41 do { \ 42 if (net_ratelimit()) \ 43 netdev_err(fmt, ##__VA_ARGS__); \ 44 } while (0) 45 46 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force); 47 48 static const char hns3_driver_name[] = "hns3"; 49 static const char hns3_driver_string[] = 50 "Hisilicon Ethernet Network Driver for Hip08 Family"; 51 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 52 static struct hnae3_client client; 53 54 static int debug = -1; 55 module_param(debug, int, 0); 56 MODULE_PARM_DESC(debug, " Network interface message level setting"); 57 58 static unsigned int tx_sgl = 1; 59 module_param(tx_sgl, uint, 0600); 60 MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping"); 61 62 static bool page_pool_enabled = true; 63 module_param(page_pool_enabled, bool, 0400); 64 65 #define HNS3_SGL_SIZE(nfrag) (sizeof(struct scatterlist) * (nfrag) + \ 66 sizeof(struct sg_table)) 67 #define HNS3_MAX_SGL_SIZE ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \ 68 dma_get_cache_alignment()) 69 70 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 71 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) 72 73 #define HNS3_INNER_VLAN_TAG 1 74 #define HNS3_OUTER_VLAN_TAG 2 75 76 #define HNS3_MIN_TX_LEN 33U 77 #define HNS3_MIN_TUN_PKT_LEN 65U 78 79 /* hns3_pci_tbl - PCI Device ID Table 80 * 81 * Last entry must be all 0s 82 * 83 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 84 * Class, Class Mask, private data (not used) } 85 */ 86 static const struct pci_device_id hns3_pci_tbl[] = { 87 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 88 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 89 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 90 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 91 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 92 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 93 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 94 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 95 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 96 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 97 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 98 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 99 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 100 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 101 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 102 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 103 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 104 /* required last entry */ 105 {0,} 106 }; 107 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 108 109 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t, h) \ 110 { ptype, \ 111 l, \ 112 CHECKSUM_##s, \ 113 HNS3_L3_TYPE_##t, \ 114 1, \ 115 h} 116 117 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \ 118 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0, \ 119 PKT_HASH_TYPE_NONE } 120 121 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = { 122 HNS3_RX_PTYPE_UNUSED_ENTRY(0), 123 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP, PKT_HASH_TYPE_NONE), 124 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP, PKT_HASH_TYPE_NONE), 125 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP, PKT_HASH_TYPE_NONE), 126 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 127 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 128 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 129 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM, PKT_HASH_TYPE_NONE), 130 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 131 HNS3_RX_PTYPE_UNUSED_ENTRY(9), 132 HNS3_RX_PTYPE_UNUSED_ENTRY(10), 133 HNS3_RX_PTYPE_UNUSED_ENTRY(11), 134 HNS3_RX_PTYPE_UNUSED_ENTRY(12), 135 HNS3_RX_PTYPE_UNUSED_ENTRY(13), 136 HNS3_RX_PTYPE_UNUSED_ENTRY(14), 137 HNS3_RX_PTYPE_UNUSED_ENTRY(15), 138 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 139 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE), 140 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE), 141 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 142 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 143 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4, PKT_HASH_TYPE_NONE), 144 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 145 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4, PKT_HASH_TYPE_L3), 146 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4, PKT_HASH_TYPE_L3), 147 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 148 HNS3_RX_PTYPE_UNUSED_ENTRY(26), 149 HNS3_RX_PTYPE_UNUSED_ENTRY(27), 150 HNS3_RX_PTYPE_UNUSED_ENTRY(28), 151 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 152 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 153 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 154 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 155 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 156 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 157 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 158 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 159 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 160 HNS3_RX_PTYPE_UNUSED_ENTRY(38), 161 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 162 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 163 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 164 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 165 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 166 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 167 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 168 HNS3_RX_PTYPE_UNUSED_ENTRY(46), 169 HNS3_RX_PTYPE_UNUSED_ENTRY(47), 170 HNS3_RX_PTYPE_UNUSED_ENTRY(48), 171 HNS3_RX_PTYPE_UNUSED_ENTRY(49), 172 HNS3_RX_PTYPE_UNUSED_ENTRY(50), 173 HNS3_RX_PTYPE_UNUSED_ENTRY(51), 174 HNS3_RX_PTYPE_UNUSED_ENTRY(52), 175 HNS3_RX_PTYPE_UNUSED_ENTRY(53), 176 HNS3_RX_PTYPE_UNUSED_ENTRY(54), 177 HNS3_RX_PTYPE_UNUSED_ENTRY(55), 178 HNS3_RX_PTYPE_UNUSED_ENTRY(56), 179 HNS3_RX_PTYPE_UNUSED_ENTRY(57), 180 HNS3_RX_PTYPE_UNUSED_ENTRY(58), 181 HNS3_RX_PTYPE_UNUSED_ENTRY(59), 182 HNS3_RX_PTYPE_UNUSED_ENTRY(60), 183 HNS3_RX_PTYPE_UNUSED_ENTRY(61), 184 HNS3_RX_PTYPE_UNUSED_ENTRY(62), 185 HNS3_RX_PTYPE_UNUSED_ENTRY(63), 186 HNS3_RX_PTYPE_UNUSED_ENTRY(64), 187 HNS3_RX_PTYPE_UNUSED_ENTRY(65), 188 HNS3_RX_PTYPE_UNUSED_ENTRY(66), 189 HNS3_RX_PTYPE_UNUSED_ENTRY(67), 190 HNS3_RX_PTYPE_UNUSED_ENTRY(68), 191 HNS3_RX_PTYPE_UNUSED_ENTRY(69), 192 HNS3_RX_PTYPE_UNUSED_ENTRY(70), 193 HNS3_RX_PTYPE_UNUSED_ENTRY(71), 194 HNS3_RX_PTYPE_UNUSED_ENTRY(72), 195 HNS3_RX_PTYPE_UNUSED_ENTRY(73), 196 HNS3_RX_PTYPE_UNUSED_ENTRY(74), 197 HNS3_RX_PTYPE_UNUSED_ENTRY(75), 198 HNS3_RX_PTYPE_UNUSED_ENTRY(76), 199 HNS3_RX_PTYPE_UNUSED_ENTRY(77), 200 HNS3_RX_PTYPE_UNUSED_ENTRY(78), 201 HNS3_RX_PTYPE_UNUSED_ENTRY(79), 202 HNS3_RX_PTYPE_UNUSED_ENTRY(80), 203 HNS3_RX_PTYPE_UNUSED_ENTRY(81), 204 HNS3_RX_PTYPE_UNUSED_ENTRY(82), 205 HNS3_RX_PTYPE_UNUSED_ENTRY(83), 206 HNS3_RX_PTYPE_UNUSED_ENTRY(84), 207 HNS3_RX_PTYPE_UNUSED_ENTRY(85), 208 HNS3_RX_PTYPE_UNUSED_ENTRY(86), 209 HNS3_RX_PTYPE_UNUSED_ENTRY(87), 210 HNS3_RX_PTYPE_UNUSED_ENTRY(88), 211 HNS3_RX_PTYPE_UNUSED_ENTRY(89), 212 HNS3_RX_PTYPE_UNUSED_ENTRY(90), 213 HNS3_RX_PTYPE_UNUSED_ENTRY(91), 214 HNS3_RX_PTYPE_UNUSED_ENTRY(92), 215 HNS3_RX_PTYPE_UNUSED_ENTRY(93), 216 HNS3_RX_PTYPE_UNUSED_ENTRY(94), 217 HNS3_RX_PTYPE_UNUSED_ENTRY(95), 218 HNS3_RX_PTYPE_UNUSED_ENTRY(96), 219 HNS3_RX_PTYPE_UNUSED_ENTRY(97), 220 HNS3_RX_PTYPE_UNUSED_ENTRY(98), 221 HNS3_RX_PTYPE_UNUSED_ENTRY(99), 222 HNS3_RX_PTYPE_UNUSED_ENTRY(100), 223 HNS3_RX_PTYPE_UNUSED_ENTRY(101), 224 HNS3_RX_PTYPE_UNUSED_ENTRY(102), 225 HNS3_RX_PTYPE_UNUSED_ENTRY(103), 226 HNS3_RX_PTYPE_UNUSED_ENTRY(104), 227 HNS3_RX_PTYPE_UNUSED_ENTRY(105), 228 HNS3_RX_PTYPE_UNUSED_ENTRY(106), 229 HNS3_RX_PTYPE_UNUSED_ENTRY(107), 230 HNS3_RX_PTYPE_UNUSED_ENTRY(108), 231 HNS3_RX_PTYPE_UNUSED_ENTRY(109), 232 HNS3_RX_PTYPE_UNUSED_ENTRY(110), 233 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 234 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 235 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 236 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 237 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6, PKT_HASH_TYPE_L3), 238 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 239 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6, PKT_HASH_TYPE_L3), 240 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6, PKT_HASH_TYPE_L3), 241 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 242 HNS3_RX_PTYPE_UNUSED_ENTRY(120), 243 HNS3_RX_PTYPE_UNUSED_ENTRY(121), 244 HNS3_RX_PTYPE_UNUSED_ENTRY(122), 245 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 246 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 247 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 248 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 249 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 250 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 251 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 252 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 253 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 254 HNS3_RX_PTYPE_UNUSED_ENTRY(132), 255 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 256 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 257 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 258 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 259 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 260 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 261 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 262 HNS3_RX_PTYPE_UNUSED_ENTRY(140), 263 HNS3_RX_PTYPE_UNUSED_ENTRY(141), 264 HNS3_RX_PTYPE_UNUSED_ENTRY(142), 265 HNS3_RX_PTYPE_UNUSED_ENTRY(143), 266 HNS3_RX_PTYPE_UNUSED_ENTRY(144), 267 HNS3_RX_PTYPE_UNUSED_ENTRY(145), 268 HNS3_RX_PTYPE_UNUSED_ENTRY(146), 269 HNS3_RX_PTYPE_UNUSED_ENTRY(147), 270 HNS3_RX_PTYPE_UNUSED_ENTRY(148), 271 HNS3_RX_PTYPE_UNUSED_ENTRY(149), 272 HNS3_RX_PTYPE_UNUSED_ENTRY(150), 273 HNS3_RX_PTYPE_UNUSED_ENTRY(151), 274 HNS3_RX_PTYPE_UNUSED_ENTRY(152), 275 HNS3_RX_PTYPE_UNUSED_ENTRY(153), 276 HNS3_RX_PTYPE_UNUSED_ENTRY(154), 277 HNS3_RX_PTYPE_UNUSED_ENTRY(155), 278 HNS3_RX_PTYPE_UNUSED_ENTRY(156), 279 HNS3_RX_PTYPE_UNUSED_ENTRY(157), 280 HNS3_RX_PTYPE_UNUSED_ENTRY(158), 281 HNS3_RX_PTYPE_UNUSED_ENTRY(159), 282 HNS3_RX_PTYPE_UNUSED_ENTRY(160), 283 HNS3_RX_PTYPE_UNUSED_ENTRY(161), 284 HNS3_RX_PTYPE_UNUSED_ENTRY(162), 285 HNS3_RX_PTYPE_UNUSED_ENTRY(163), 286 HNS3_RX_PTYPE_UNUSED_ENTRY(164), 287 HNS3_RX_PTYPE_UNUSED_ENTRY(165), 288 HNS3_RX_PTYPE_UNUSED_ENTRY(166), 289 HNS3_RX_PTYPE_UNUSED_ENTRY(167), 290 HNS3_RX_PTYPE_UNUSED_ENTRY(168), 291 HNS3_RX_PTYPE_UNUSED_ENTRY(169), 292 HNS3_RX_PTYPE_UNUSED_ENTRY(170), 293 HNS3_RX_PTYPE_UNUSED_ENTRY(171), 294 HNS3_RX_PTYPE_UNUSED_ENTRY(172), 295 HNS3_RX_PTYPE_UNUSED_ENTRY(173), 296 HNS3_RX_PTYPE_UNUSED_ENTRY(174), 297 HNS3_RX_PTYPE_UNUSED_ENTRY(175), 298 HNS3_RX_PTYPE_UNUSED_ENTRY(176), 299 HNS3_RX_PTYPE_UNUSED_ENTRY(177), 300 HNS3_RX_PTYPE_UNUSED_ENTRY(178), 301 HNS3_RX_PTYPE_UNUSED_ENTRY(179), 302 HNS3_RX_PTYPE_UNUSED_ENTRY(180), 303 HNS3_RX_PTYPE_UNUSED_ENTRY(181), 304 HNS3_RX_PTYPE_UNUSED_ENTRY(182), 305 HNS3_RX_PTYPE_UNUSED_ENTRY(183), 306 HNS3_RX_PTYPE_UNUSED_ENTRY(184), 307 HNS3_RX_PTYPE_UNUSED_ENTRY(185), 308 HNS3_RX_PTYPE_UNUSED_ENTRY(186), 309 HNS3_RX_PTYPE_UNUSED_ENTRY(187), 310 HNS3_RX_PTYPE_UNUSED_ENTRY(188), 311 HNS3_RX_PTYPE_UNUSED_ENTRY(189), 312 HNS3_RX_PTYPE_UNUSED_ENTRY(190), 313 HNS3_RX_PTYPE_UNUSED_ENTRY(191), 314 HNS3_RX_PTYPE_UNUSED_ENTRY(192), 315 HNS3_RX_PTYPE_UNUSED_ENTRY(193), 316 HNS3_RX_PTYPE_UNUSED_ENTRY(194), 317 HNS3_RX_PTYPE_UNUSED_ENTRY(195), 318 HNS3_RX_PTYPE_UNUSED_ENTRY(196), 319 HNS3_RX_PTYPE_UNUSED_ENTRY(197), 320 HNS3_RX_PTYPE_UNUSED_ENTRY(198), 321 HNS3_RX_PTYPE_UNUSED_ENTRY(199), 322 HNS3_RX_PTYPE_UNUSED_ENTRY(200), 323 HNS3_RX_PTYPE_UNUSED_ENTRY(201), 324 HNS3_RX_PTYPE_UNUSED_ENTRY(202), 325 HNS3_RX_PTYPE_UNUSED_ENTRY(203), 326 HNS3_RX_PTYPE_UNUSED_ENTRY(204), 327 HNS3_RX_PTYPE_UNUSED_ENTRY(205), 328 HNS3_RX_PTYPE_UNUSED_ENTRY(206), 329 HNS3_RX_PTYPE_UNUSED_ENTRY(207), 330 HNS3_RX_PTYPE_UNUSED_ENTRY(208), 331 HNS3_RX_PTYPE_UNUSED_ENTRY(209), 332 HNS3_RX_PTYPE_UNUSED_ENTRY(210), 333 HNS3_RX_PTYPE_UNUSED_ENTRY(211), 334 HNS3_RX_PTYPE_UNUSED_ENTRY(212), 335 HNS3_RX_PTYPE_UNUSED_ENTRY(213), 336 HNS3_RX_PTYPE_UNUSED_ENTRY(214), 337 HNS3_RX_PTYPE_UNUSED_ENTRY(215), 338 HNS3_RX_PTYPE_UNUSED_ENTRY(216), 339 HNS3_RX_PTYPE_UNUSED_ENTRY(217), 340 HNS3_RX_PTYPE_UNUSED_ENTRY(218), 341 HNS3_RX_PTYPE_UNUSED_ENTRY(219), 342 HNS3_RX_PTYPE_UNUSED_ENTRY(220), 343 HNS3_RX_PTYPE_UNUSED_ENTRY(221), 344 HNS3_RX_PTYPE_UNUSED_ENTRY(222), 345 HNS3_RX_PTYPE_UNUSED_ENTRY(223), 346 HNS3_RX_PTYPE_UNUSED_ENTRY(224), 347 HNS3_RX_PTYPE_UNUSED_ENTRY(225), 348 HNS3_RX_PTYPE_UNUSED_ENTRY(226), 349 HNS3_RX_PTYPE_UNUSED_ENTRY(227), 350 HNS3_RX_PTYPE_UNUSED_ENTRY(228), 351 HNS3_RX_PTYPE_UNUSED_ENTRY(229), 352 HNS3_RX_PTYPE_UNUSED_ENTRY(230), 353 HNS3_RX_PTYPE_UNUSED_ENTRY(231), 354 HNS3_RX_PTYPE_UNUSED_ENTRY(232), 355 HNS3_RX_PTYPE_UNUSED_ENTRY(233), 356 HNS3_RX_PTYPE_UNUSED_ENTRY(234), 357 HNS3_RX_PTYPE_UNUSED_ENTRY(235), 358 HNS3_RX_PTYPE_UNUSED_ENTRY(236), 359 HNS3_RX_PTYPE_UNUSED_ENTRY(237), 360 HNS3_RX_PTYPE_UNUSED_ENTRY(238), 361 HNS3_RX_PTYPE_UNUSED_ENTRY(239), 362 HNS3_RX_PTYPE_UNUSED_ENTRY(240), 363 HNS3_RX_PTYPE_UNUSED_ENTRY(241), 364 HNS3_RX_PTYPE_UNUSED_ENTRY(242), 365 HNS3_RX_PTYPE_UNUSED_ENTRY(243), 366 HNS3_RX_PTYPE_UNUSED_ENTRY(244), 367 HNS3_RX_PTYPE_UNUSED_ENTRY(245), 368 HNS3_RX_PTYPE_UNUSED_ENTRY(246), 369 HNS3_RX_PTYPE_UNUSED_ENTRY(247), 370 HNS3_RX_PTYPE_UNUSED_ENTRY(248), 371 HNS3_RX_PTYPE_UNUSED_ENTRY(249), 372 HNS3_RX_PTYPE_UNUSED_ENTRY(250), 373 HNS3_RX_PTYPE_UNUSED_ENTRY(251), 374 HNS3_RX_PTYPE_UNUSED_ENTRY(252), 375 HNS3_RX_PTYPE_UNUSED_ENTRY(253), 376 HNS3_RX_PTYPE_UNUSED_ENTRY(254), 377 HNS3_RX_PTYPE_UNUSED_ENTRY(255), 378 }; 379 380 #define HNS3_INVALID_PTYPE \ 381 ARRAY_SIZE(hns3_rx_ptype_tbl) 382 383 static irqreturn_t hns3_irq_handle(int irq, void *vector) 384 { 385 struct hns3_enet_tqp_vector *tqp_vector = vector; 386 387 napi_schedule_irqoff(&tqp_vector->napi); 388 tqp_vector->event_cnt++; 389 390 return IRQ_HANDLED; 391 } 392 393 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 394 { 395 struct hns3_enet_tqp_vector *tqp_vectors; 396 unsigned int i; 397 398 for (i = 0; i < priv->vector_num; i++) { 399 tqp_vectors = &priv->tqp_vector[i]; 400 401 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 402 continue; 403 404 /* clear the affinity mask */ 405 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 406 407 /* release the irq resource */ 408 free_irq(tqp_vectors->vector_irq, tqp_vectors); 409 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 410 } 411 } 412 413 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 414 { 415 struct hns3_enet_tqp_vector *tqp_vectors; 416 int txrx_int_idx = 0; 417 int rx_int_idx = 0; 418 int tx_int_idx = 0; 419 unsigned int i; 420 int ret; 421 422 for (i = 0; i < priv->vector_num; i++) { 423 tqp_vectors = &priv->tqp_vector[i]; 424 425 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 426 continue; 427 428 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 429 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 430 "%s-%s-%s-%d", hns3_driver_name, 431 pci_name(priv->ae_handle->pdev), 432 "TxRx", txrx_int_idx++); 433 txrx_int_idx++; 434 } else if (tqp_vectors->rx_group.ring) { 435 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 436 "%s-%s-%s-%d", hns3_driver_name, 437 pci_name(priv->ae_handle->pdev), 438 "Rx", rx_int_idx++); 439 } else if (tqp_vectors->tx_group.ring) { 440 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 441 "%s-%s-%s-%d", hns3_driver_name, 442 pci_name(priv->ae_handle->pdev), 443 "Tx", tx_int_idx++); 444 } else { 445 /* Skip this unused q_vector */ 446 continue; 447 } 448 449 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 450 451 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN); 452 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 453 tqp_vectors->name, tqp_vectors); 454 if (ret) { 455 netdev_err(priv->netdev, "request irq(%d) fail\n", 456 tqp_vectors->vector_irq); 457 hns3_nic_uninit_irq(priv); 458 return ret; 459 } 460 461 irq_set_affinity_hint(tqp_vectors->vector_irq, 462 &tqp_vectors->affinity_mask); 463 464 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 465 } 466 467 return 0; 468 } 469 470 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 471 u32 mask_en) 472 { 473 writel(mask_en, tqp_vector->mask_addr); 474 } 475 476 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 477 { 478 napi_enable(&tqp_vector->napi); 479 enable_irq(tqp_vector->vector_irq); 480 481 /* enable vector */ 482 hns3_mask_vector_irq(tqp_vector, 1); 483 } 484 485 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 486 { 487 /* disable vector */ 488 hns3_mask_vector_irq(tqp_vector, 0); 489 490 disable_irq(tqp_vector->vector_irq); 491 napi_disable(&tqp_vector->napi); 492 cancel_work_sync(&tqp_vector->rx_group.dim.work); 493 cancel_work_sync(&tqp_vector->tx_group.dim.work); 494 } 495 496 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 497 u32 rl_value) 498 { 499 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 500 501 /* this defines the configuration for RL (Interrupt Rate Limiter). 502 * Rl defines rate of interrupts i.e. number of interrupts-per-second 503 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 504 */ 505 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable && 506 !tqp_vector->rx_group.coal.adapt_enable) 507 /* According to the hardware, the range of rl_reg is 508 * 0-59 and the unit is 4. 509 */ 510 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 511 512 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 513 } 514 515 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 516 u32 gl_value) 517 { 518 u32 new_val; 519 520 if (tqp_vector->rx_group.coal.unit_1us) 521 new_val = gl_value | HNS3_INT_GL_1US; 522 else 523 new_val = hns3_gl_usec_to_reg(gl_value); 524 525 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 526 } 527 528 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 529 u32 gl_value) 530 { 531 u32 new_val; 532 533 if (tqp_vector->tx_group.coal.unit_1us) 534 new_val = gl_value | HNS3_INT_GL_1US; 535 else 536 new_val = hns3_gl_usec_to_reg(gl_value); 537 538 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 539 } 540 541 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector, 542 u32 ql_value) 543 { 544 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET); 545 } 546 547 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector, 548 u32 ql_value) 549 { 550 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET); 551 } 552 553 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector, 554 struct hns3_nic_priv *priv) 555 { 556 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 557 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 558 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 559 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal; 560 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal; 561 562 tx_coal->adapt_enable = ptx_coal->adapt_enable; 563 rx_coal->adapt_enable = prx_coal->adapt_enable; 564 565 tx_coal->int_gl = ptx_coal->int_gl; 566 rx_coal->int_gl = prx_coal->int_gl; 567 568 rx_coal->flow_level = prx_coal->flow_level; 569 tx_coal->flow_level = ptx_coal->flow_level; 570 571 /* device version above V3(include V3), GL can configure 1us 572 * unit, so uses 1us unit. 573 */ 574 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) { 575 tx_coal->unit_1us = 1; 576 rx_coal->unit_1us = 1; 577 } 578 579 if (ae_dev->dev_specs.int_ql_max) { 580 tx_coal->ql_enable = 1; 581 rx_coal->ql_enable = 1; 582 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 583 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 584 tx_coal->int_ql = ptx_coal->int_ql; 585 rx_coal->int_ql = prx_coal->int_ql; 586 } 587 } 588 589 static void 590 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 591 struct hns3_nic_priv *priv) 592 { 593 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 594 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 595 struct hnae3_handle *h = priv->ae_handle; 596 597 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl); 598 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl); 599 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 600 601 if (tx_coal->ql_enable) 602 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql); 603 604 if (rx_coal->ql_enable) 605 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql); 606 } 607 608 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 609 { 610 struct hnae3_handle *h = hns3_get_handle(netdev); 611 struct hnae3_knic_private_info *kinfo = &h->kinfo; 612 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 613 unsigned int queue_size = kinfo->num_tqps; 614 int i, ret; 615 616 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) { 617 netdev_reset_tc(netdev); 618 } else { 619 ret = netdev_set_num_tc(netdev, tc_info->num_tc); 620 if (ret) { 621 netdev_err(netdev, 622 "netdev_set_num_tc fail, ret=%d!\n", ret); 623 return ret; 624 } 625 626 for (i = 0; i < tc_info->num_tc; i++) 627 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i], 628 tc_info->tqp_offset[i]); 629 } 630 631 ret = netif_set_real_num_tx_queues(netdev, queue_size); 632 if (ret) { 633 netdev_err(netdev, 634 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret); 635 return ret; 636 } 637 638 ret = netif_set_real_num_rx_queues(netdev, queue_size); 639 if (ret) { 640 netdev_err(netdev, 641 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 642 return ret; 643 } 644 645 return 0; 646 } 647 648 u16 hns3_get_max_available_channels(struct hnae3_handle *h) 649 { 650 u16 alloc_tqps, max_rss_size, rss_size; 651 652 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 653 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc; 654 655 return min_t(u16, rss_size, max_rss_size); 656 } 657 658 static void hns3_tqp_enable(struct hnae3_queue *tqp) 659 { 660 u32 rcb_reg; 661 662 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 663 rcb_reg |= BIT(HNS3_RING_EN_B); 664 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 665 } 666 667 static void hns3_tqp_disable(struct hnae3_queue *tqp) 668 { 669 u32 rcb_reg; 670 671 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 672 rcb_reg &= ~BIT(HNS3_RING_EN_B); 673 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 674 } 675 676 static void hns3_free_rx_cpu_rmap(struct net_device *netdev) 677 { 678 #ifdef CONFIG_RFS_ACCEL 679 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 680 netdev->rx_cpu_rmap = NULL; 681 #endif 682 } 683 684 static int hns3_set_rx_cpu_rmap(struct net_device *netdev) 685 { 686 #ifdef CONFIG_RFS_ACCEL 687 struct hns3_nic_priv *priv = netdev_priv(netdev); 688 struct hns3_enet_tqp_vector *tqp_vector; 689 int i, ret; 690 691 if (!netdev->rx_cpu_rmap) { 692 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num); 693 if (!netdev->rx_cpu_rmap) 694 return -ENOMEM; 695 } 696 697 for (i = 0; i < priv->vector_num; i++) { 698 tqp_vector = &priv->tqp_vector[i]; 699 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap, 700 tqp_vector->vector_irq); 701 if (ret) { 702 hns3_free_rx_cpu_rmap(netdev); 703 return ret; 704 } 705 } 706 #endif 707 return 0; 708 } 709 710 static int hns3_nic_net_up(struct net_device *netdev) 711 { 712 struct hns3_nic_priv *priv = netdev_priv(netdev); 713 struct hnae3_handle *h = priv->ae_handle; 714 int i, j; 715 int ret; 716 717 ret = hns3_nic_reset_all_ring(h); 718 if (ret) 719 return ret; 720 721 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 722 723 /* enable the vectors */ 724 for (i = 0; i < priv->vector_num; i++) 725 hns3_vector_enable(&priv->tqp_vector[i]); 726 727 /* enable rcb */ 728 for (j = 0; j < h->kinfo.num_tqps; j++) 729 hns3_tqp_enable(h->kinfo.tqp[j]); 730 731 /* start the ae_dev */ 732 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 733 if (ret) { 734 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 735 while (j--) 736 hns3_tqp_disable(h->kinfo.tqp[j]); 737 738 for (j = i - 1; j >= 0; j--) 739 hns3_vector_disable(&priv->tqp_vector[j]); 740 } 741 742 return ret; 743 } 744 745 static void hns3_config_xps(struct hns3_nic_priv *priv) 746 { 747 int i; 748 749 for (i = 0; i < priv->vector_num; i++) { 750 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 751 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 752 753 while (ring) { 754 int ret; 755 756 ret = netif_set_xps_queue(priv->netdev, 757 &tqp_vector->affinity_mask, 758 ring->tqp->tqp_index); 759 if (ret) 760 netdev_warn(priv->netdev, 761 "set xps queue failed: %d", ret); 762 763 ring = ring->next; 764 } 765 } 766 } 767 768 static int hns3_nic_net_open(struct net_device *netdev) 769 { 770 struct hns3_nic_priv *priv = netdev_priv(netdev); 771 struct hnae3_handle *h = hns3_get_handle(netdev); 772 struct hnae3_knic_private_info *kinfo; 773 int i, ret; 774 775 if (hns3_nic_resetting(netdev)) 776 return -EBUSY; 777 778 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 779 netdev_warn(netdev, "net open repeatedly!\n"); 780 return 0; 781 } 782 783 netif_carrier_off(netdev); 784 785 ret = hns3_nic_set_real_num_queue(netdev); 786 if (ret) 787 return ret; 788 789 ret = hns3_nic_net_up(netdev); 790 if (ret) { 791 netdev_err(netdev, "net up fail, ret=%d!\n", ret); 792 return ret; 793 } 794 795 kinfo = &h->kinfo; 796 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 797 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]); 798 799 if (h->ae_algo->ops->set_timer_task) 800 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 801 802 hns3_config_xps(priv); 803 804 netif_dbg(h, drv, netdev, "net open\n"); 805 806 return 0; 807 } 808 809 static void hns3_reset_tx_queue(struct hnae3_handle *h) 810 { 811 struct net_device *ndev = h->kinfo.netdev; 812 struct hns3_nic_priv *priv = netdev_priv(ndev); 813 struct netdev_queue *dev_queue; 814 u32 i; 815 816 for (i = 0; i < h->kinfo.num_tqps; i++) { 817 dev_queue = netdev_get_tx_queue(ndev, 818 priv->ring[i].queue_index); 819 netdev_tx_reset_queue(dev_queue); 820 } 821 } 822 823 static void hns3_nic_net_down(struct net_device *netdev) 824 { 825 struct hns3_nic_priv *priv = netdev_priv(netdev); 826 struct hnae3_handle *h = hns3_get_handle(netdev); 827 const struct hnae3_ae_ops *ops; 828 int i; 829 830 /* disable vectors */ 831 for (i = 0; i < priv->vector_num; i++) 832 hns3_vector_disable(&priv->tqp_vector[i]); 833 834 /* disable rcb */ 835 for (i = 0; i < h->kinfo.num_tqps; i++) 836 hns3_tqp_disable(h->kinfo.tqp[i]); 837 838 /* stop ae_dev */ 839 ops = priv->ae_handle->ae_algo->ops; 840 if (ops->stop) 841 ops->stop(priv->ae_handle); 842 843 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 844 * during reset process, because driver may not be able 845 * to disable the ring through firmware when downing the netdev. 846 */ 847 if (!hns3_nic_resetting(netdev)) 848 hns3_clear_all_ring(priv->ae_handle, false); 849 850 hns3_reset_tx_queue(priv->ae_handle); 851 } 852 853 static int hns3_nic_net_stop(struct net_device *netdev) 854 { 855 struct hns3_nic_priv *priv = netdev_priv(netdev); 856 struct hnae3_handle *h = hns3_get_handle(netdev); 857 858 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 859 return 0; 860 861 netif_dbg(h, drv, netdev, "net stop\n"); 862 863 if (h->ae_algo->ops->set_timer_task) 864 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 865 866 netif_carrier_off(netdev); 867 netif_tx_disable(netdev); 868 869 hns3_nic_net_down(netdev); 870 871 return 0; 872 } 873 874 static int hns3_nic_uc_sync(struct net_device *netdev, 875 const unsigned char *addr) 876 { 877 struct hnae3_handle *h = hns3_get_handle(netdev); 878 879 if (h->ae_algo->ops->add_uc_addr) 880 return h->ae_algo->ops->add_uc_addr(h, addr); 881 882 return 0; 883 } 884 885 static int hns3_nic_uc_unsync(struct net_device *netdev, 886 const unsigned char *addr) 887 { 888 struct hnae3_handle *h = hns3_get_handle(netdev); 889 890 /* need ignore the request of removing device address, because 891 * we store the device address and other addresses of uc list 892 * in the function's mac filter list. 893 */ 894 if (ether_addr_equal(addr, netdev->dev_addr)) 895 return 0; 896 897 if (h->ae_algo->ops->rm_uc_addr) 898 return h->ae_algo->ops->rm_uc_addr(h, addr); 899 900 return 0; 901 } 902 903 static int hns3_nic_mc_sync(struct net_device *netdev, 904 const unsigned char *addr) 905 { 906 struct hnae3_handle *h = hns3_get_handle(netdev); 907 908 if (h->ae_algo->ops->add_mc_addr) 909 return h->ae_algo->ops->add_mc_addr(h, addr); 910 911 return 0; 912 } 913 914 static int hns3_nic_mc_unsync(struct net_device *netdev, 915 const unsigned char *addr) 916 { 917 struct hnae3_handle *h = hns3_get_handle(netdev); 918 919 if (h->ae_algo->ops->rm_mc_addr) 920 return h->ae_algo->ops->rm_mc_addr(h, addr); 921 922 return 0; 923 } 924 925 static u8 hns3_get_netdev_flags(struct net_device *netdev) 926 { 927 u8 flags = 0; 928 929 if (netdev->flags & IFF_PROMISC) 930 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 931 else if (netdev->flags & IFF_ALLMULTI) 932 flags = HNAE3_USER_MPE; 933 934 return flags; 935 } 936 937 static void hns3_nic_set_rx_mode(struct net_device *netdev) 938 { 939 struct hnae3_handle *h = hns3_get_handle(netdev); 940 u8 new_flags; 941 942 new_flags = hns3_get_netdev_flags(netdev); 943 944 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 945 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync); 946 947 /* User mode Promisc mode enable and vlan filtering is disabled to 948 * let all packets in. 949 */ 950 h->netdev_flags = new_flags; 951 hns3_request_update_promisc_mode(h); 952 } 953 954 void hns3_request_update_promisc_mode(struct hnae3_handle *handle) 955 { 956 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 957 958 if (ops->request_update_promisc_mode) 959 ops->request_update_promisc_mode(handle); 960 } 961 962 static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring) 963 { 964 struct hns3_tx_spare *tx_spare = ring->tx_spare; 965 u32 ntc, ntu; 966 967 /* This smp_load_acquire() pairs with smp_store_release() in 968 * hns3_tx_spare_update() called in tx desc cleaning process. 969 */ 970 ntc = smp_load_acquire(&tx_spare->last_to_clean); 971 ntu = tx_spare->next_to_use; 972 973 if (ntc > ntu) 974 return ntc - ntu - 1; 975 976 /* The free tx buffer is divided into two part, so pick the 977 * larger one. 978 */ 979 return max(ntc, tx_spare->len - ntu) - 1; 980 } 981 982 static void hns3_tx_spare_update(struct hns3_enet_ring *ring) 983 { 984 struct hns3_tx_spare *tx_spare = ring->tx_spare; 985 986 if (!tx_spare || 987 tx_spare->last_to_clean == tx_spare->next_to_clean) 988 return; 989 990 /* This smp_store_release() pairs with smp_load_acquire() in 991 * hns3_tx_spare_space() called in xmit process. 992 */ 993 smp_store_release(&tx_spare->last_to_clean, 994 tx_spare->next_to_clean); 995 } 996 997 static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring, 998 struct sk_buff *skb, 999 u32 space) 1000 { 1001 u32 len = skb->len <= ring->tx_copybreak ? skb->len : 1002 skb_headlen(skb); 1003 1004 if (len > ring->tx_copybreak) 1005 return false; 1006 1007 if (ALIGN(len, dma_get_cache_alignment()) > space) { 1008 hns3_ring_stats_update(ring, tx_spare_full); 1009 return false; 1010 } 1011 1012 return true; 1013 } 1014 1015 static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring, 1016 struct sk_buff *skb, 1017 u32 space) 1018 { 1019 if (skb->len <= ring->tx_copybreak || !tx_sgl || 1020 (!skb_has_frag_list(skb) && 1021 skb_shinfo(skb)->nr_frags < tx_sgl)) 1022 return false; 1023 1024 if (space < HNS3_MAX_SGL_SIZE) { 1025 hns3_ring_stats_update(ring, tx_spare_full); 1026 return false; 1027 } 1028 1029 return true; 1030 } 1031 1032 static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring) 1033 { 1034 u32 alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size; 1035 struct hns3_tx_spare *tx_spare; 1036 struct page *page; 1037 dma_addr_t dma; 1038 int order; 1039 1040 if (!alloc_size) 1041 return; 1042 1043 order = get_order(alloc_size); 1044 if (order >= MAX_ORDER) { 1045 if (net_ratelimit()) 1046 dev_warn(ring_to_dev(ring), "failed to allocate tx spare buffer, exceed to max order\n"); 1047 return; 1048 } 1049 1050 tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare), 1051 GFP_KERNEL); 1052 if (!tx_spare) { 1053 /* The driver still work without the tx spare buffer */ 1054 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n"); 1055 goto devm_kzalloc_error; 1056 } 1057 1058 page = alloc_pages_node(dev_to_node(ring_to_dev(ring)), 1059 GFP_KERNEL, order); 1060 if (!page) { 1061 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n"); 1062 goto alloc_pages_error; 1063 } 1064 1065 dma = dma_map_page(ring_to_dev(ring), page, 0, 1066 PAGE_SIZE << order, DMA_TO_DEVICE); 1067 if (dma_mapping_error(ring_to_dev(ring), dma)) { 1068 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n"); 1069 goto dma_mapping_error; 1070 } 1071 1072 tx_spare->dma = dma; 1073 tx_spare->buf = page_address(page); 1074 tx_spare->len = PAGE_SIZE << order; 1075 ring->tx_spare = tx_spare; 1076 return; 1077 1078 dma_mapping_error: 1079 put_page(page); 1080 alloc_pages_error: 1081 devm_kfree(ring_to_dev(ring), tx_spare); 1082 devm_kzalloc_error: 1083 ring->tqp->handle->kinfo.tx_spare_buf_size = 0; 1084 } 1085 1086 /* Use hns3_tx_spare_space() to make sure there is enough buffer 1087 * before calling below function to allocate tx buffer. 1088 */ 1089 static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring, 1090 unsigned int size, dma_addr_t *dma, 1091 u32 *cb_len) 1092 { 1093 struct hns3_tx_spare *tx_spare = ring->tx_spare; 1094 u32 ntu = tx_spare->next_to_use; 1095 1096 size = ALIGN(size, dma_get_cache_alignment()); 1097 *cb_len = size; 1098 1099 /* Tx spare buffer wraps back here because the end of 1100 * freed tx buffer is not enough. 1101 */ 1102 if (ntu + size > tx_spare->len) { 1103 *cb_len += (tx_spare->len - ntu); 1104 ntu = 0; 1105 } 1106 1107 tx_spare->next_to_use = ntu + size; 1108 if (tx_spare->next_to_use == tx_spare->len) 1109 tx_spare->next_to_use = 0; 1110 1111 *dma = tx_spare->dma + ntu; 1112 1113 return tx_spare->buf + ntu; 1114 } 1115 1116 static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len) 1117 { 1118 struct hns3_tx_spare *tx_spare = ring->tx_spare; 1119 1120 if (len > tx_spare->next_to_use) { 1121 len -= tx_spare->next_to_use; 1122 tx_spare->next_to_use = tx_spare->len - len; 1123 } else { 1124 tx_spare->next_to_use -= len; 1125 } 1126 } 1127 1128 static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring, 1129 struct hns3_desc_cb *cb) 1130 { 1131 struct hns3_tx_spare *tx_spare = ring->tx_spare; 1132 u32 ntc = tx_spare->next_to_clean; 1133 u32 len = cb->length; 1134 1135 tx_spare->next_to_clean += len; 1136 1137 if (tx_spare->next_to_clean >= tx_spare->len) { 1138 tx_spare->next_to_clean -= tx_spare->len; 1139 1140 if (tx_spare->next_to_clean) { 1141 ntc = 0; 1142 len = tx_spare->next_to_clean; 1143 } 1144 } 1145 1146 /* This tx spare buffer is only really reclaimed after calling 1147 * hns3_tx_spare_update(), so it is still safe to use the info in 1148 * the tx buffer to do the dma sync or sg unmapping after 1149 * tx_spare->next_to_clean is moved forword. 1150 */ 1151 if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) { 1152 dma_addr_t dma = tx_spare->dma + ntc; 1153 1154 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len, 1155 DMA_TO_DEVICE); 1156 } else { 1157 struct sg_table *sgt = tx_spare->buf + ntc; 1158 1159 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents, 1160 DMA_TO_DEVICE); 1161 } 1162 } 1163 1164 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs, 1165 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes) 1166 { 1167 u32 l4_offset, hdr_len; 1168 union l3_hdr_info l3; 1169 union l4_hdr_info l4; 1170 u32 l4_paylen; 1171 int ret; 1172 1173 if (!skb_is_gso(skb)) 1174 return 0; 1175 1176 ret = skb_cow_head(skb, 0); 1177 if (unlikely(ret < 0)) 1178 return ret; 1179 1180 l3.hdr = skb_network_header(skb); 1181 l4.hdr = skb_transport_header(skb); 1182 1183 /* Software should clear the IPv4's checksum field when tso is 1184 * needed. 1185 */ 1186 if (l3.v4->version == 4) 1187 l3.v4->check = 0; 1188 1189 /* tunnel packet */ 1190 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 1191 SKB_GSO_GRE_CSUM | 1192 SKB_GSO_UDP_TUNNEL | 1193 SKB_GSO_UDP_TUNNEL_CSUM)) { 1194 /* reset l3&l4 pointers from outer to inner headers */ 1195 l3.hdr = skb_inner_network_header(skb); 1196 l4.hdr = skb_inner_transport_header(skb); 1197 1198 /* Software should clear the IPv4's checksum field when 1199 * tso is needed. 1200 */ 1201 if (l3.v4->version == 4) 1202 l3.v4->check = 0; 1203 } 1204 1205 /* normal or tunnel packet */ 1206 l4_offset = l4.hdr - skb->data; 1207 1208 /* remove payload length from inner pseudo checksum when tso */ 1209 l4_paylen = skb->len - l4_offset; 1210 1211 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 1212 hdr_len = sizeof(*l4.udp) + l4_offset; 1213 csum_replace_by_diff(&l4.udp->check, 1214 (__force __wsum)htonl(l4_paylen)); 1215 } else { 1216 hdr_len = (l4.tcp->doff << 2) + l4_offset; 1217 csum_replace_by_diff(&l4.tcp->check, 1218 (__force __wsum)htonl(l4_paylen)); 1219 } 1220 1221 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len; 1222 1223 /* find the txbd field values */ 1224 *paylen_fdop_ol4cs = skb->len - hdr_len; 1225 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 1226 1227 /* offload outer UDP header checksum */ 1228 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM) 1229 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1); 1230 1231 /* get MSS for TSO */ 1232 *mss = skb_shinfo(skb)->gso_size; 1233 1234 trace_hns3_tso(skb); 1235 1236 return 0; 1237 } 1238 1239 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 1240 u8 *il4_proto) 1241 { 1242 union l3_hdr_info l3; 1243 unsigned char *l4_hdr; 1244 unsigned char *exthdr; 1245 u8 l4_proto_tmp; 1246 __be16 frag_off; 1247 1248 /* find outer header point */ 1249 l3.hdr = skb_network_header(skb); 1250 l4_hdr = skb_transport_header(skb); 1251 1252 if (skb->protocol == htons(ETH_P_IPV6)) { 1253 exthdr = l3.hdr + sizeof(*l3.v6); 1254 l4_proto_tmp = l3.v6->nexthdr; 1255 if (l4_hdr != exthdr) 1256 ipv6_skip_exthdr(skb, exthdr - skb->data, 1257 &l4_proto_tmp, &frag_off); 1258 } else if (skb->protocol == htons(ETH_P_IP)) { 1259 l4_proto_tmp = l3.v4->protocol; 1260 } else { 1261 return -EINVAL; 1262 } 1263 1264 *ol4_proto = l4_proto_tmp; 1265 1266 /* tunnel packet */ 1267 if (!skb->encapsulation) { 1268 *il4_proto = 0; 1269 return 0; 1270 } 1271 1272 /* find inner header point */ 1273 l3.hdr = skb_inner_network_header(skb); 1274 l4_hdr = skb_inner_transport_header(skb); 1275 1276 if (l3.v6->version == 6) { 1277 exthdr = l3.hdr + sizeof(*l3.v6); 1278 l4_proto_tmp = l3.v6->nexthdr; 1279 if (l4_hdr != exthdr) 1280 ipv6_skip_exthdr(skb, exthdr - skb->data, 1281 &l4_proto_tmp, &frag_off); 1282 } else if (l3.v4->version == 4) { 1283 l4_proto_tmp = l3.v4->protocol; 1284 } 1285 1286 *il4_proto = l4_proto_tmp; 1287 1288 return 0; 1289 } 1290 1291 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 1292 * and it is udp packet, which has a dest port as the IANA assigned. 1293 * the hardware is expected to do the checksum offload, but the 1294 * hardware will not do the checksum offload when udp dest port is 1295 * 4789, 4790 or 6081. 1296 */ 1297 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 1298 { 1299 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 1300 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 1301 union l4_hdr_info l4; 1302 1303 /* device version above V3(include V3), the hardware can 1304 * do this checksum offload. 1305 */ 1306 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 1307 return false; 1308 1309 l4.hdr = skb_transport_header(skb); 1310 1311 if (!(!skb->encapsulation && 1312 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) || 1313 l4.udp->dest == htons(GENEVE_UDP_PORT) || 1314 l4.udp->dest == htons(IANA_VXLAN_GPE_UDP_PORT)))) 1315 return false; 1316 1317 return true; 1318 } 1319 1320 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 1321 u32 *ol_type_vlan_len_msec) 1322 { 1323 u32 l2_len, l3_len, l4_len; 1324 unsigned char *il2_hdr; 1325 union l3_hdr_info l3; 1326 union l4_hdr_info l4; 1327 1328 l3.hdr = skb_network_header(skb); 1329 l4.hdr = skb_transport_header(skb); 1330 1331 /* compute OL2 header size, defined in 2 Bytes */ 1332 l2_len = l3.hdr - skb->data; 1333 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1); 1334 1335 /* compute OL3 header size, defined in 4 Bytes */ 1336 l3_len = l4.hdr - l3.hdr; 1337 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2); 1338 1339 il2_hdr = skb_inner_mac_header(skb); 1340 /* compute OL4 header size, defined in 4 Bytes */ 1341 l4_len = il2_hdr - l4.hdr; 1342 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2); 1343 1344 /* define outer network header type */ 1345 if (skb->protocol == htons(ETH_P_IP)) { 1346 if (skb_is_gso(skb)) 1347 hns3_set_field(*ol_type_vlan_len_msec, 1348 HNS3_TXD_OL3T_S, 1349 HNS3_OL3T_IPV4_CSUM); 1350 else 1351 hns3_set_field(*ol_type_vlan_len_msec, 1352 HNS3_TXD_OL3T_S, 1353 HNS3_OL3T_IPV4_NO_CSUM); 1354 } else if (skb->protocol == htons(ETH_P_IPV6)) { 1355 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 1356 HNS3_OL3T_IPV6); 1357 } 1358 1359 if (ol4_proto == IPPROTO_UDP) 1360 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 1361 HNS3_TUN_MAC_IN_UDP); 1362 else if (ol4_proto == IPPROTO_GRE) 1363 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 1364 HNS3_TUN_NVGRE); 1365 } 1366 1367 static void hns3_set_l3_type(struct sk_buff *skb, union l3_hdr_info l3, 1368 u32 *type_cs_vlan_tso) 1369 { 1370 if (l3.v4->version == 4) { 1371 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 1372 HNS3_L3T_IPV4); 1373 1374 /* the stack computes the IP header already, the only time we 1375 * need the hardware to recompute it is in the case of TSO. 1376 */ 1377 if (skb_is_gso(skb)) 1378 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 1379 } else if (l3.v6->version == 6) { 1380 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 1381 HNS3_L3T_IPV6); 1382 } 1383 } 1384 1385 static int hns3_set_l4_csum_length(struct sk_buff *skb, union l4_hdr_info l4, 1386 u32 l4_proto, u32 *type_cs_vlan_tso) 1387 { 1388 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 1389 switch (l4_proto) { 1390 case IPPROTO_TCP: 1391 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1392 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1393 HNS3_L4T_TCP); 1394 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1395 l4.tcp->doff); 1396 break; 1397 case IPPROTO_UDP: 1398 if (hns3_tunnel_csum_bug(skb)) { 1399 int ret = skb_put_padto(skb, HNS3_MIN_TUN_PKT_LEN); 1400 1401 return ret ? ret : skb_checksum_help(skb); 1402 } 1403 1404 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1405 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1406 HNS3_L4T_UDP); 1407 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1408 (sizeof(struct udphdr) >> 2)); 1409 break; 1410 case IPPROTO_SCTP: 1411 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1412 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1413 HNS3_L4T_SCTP); 1414 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1415 (sizeof(struct sctphdr) >> 2)); 1416 break; 1417 default: 1418 /* drop the skb tunnel packet if hardware don't support, 1419 * because hardware can't calculate csum when TSO. 1420 */ 1421 if (skb_is_gso(skb)) 1422 return -EDOM; 1423 1424 /* the stack computes the IP header already, 1425 * driver calculate l4 checksum when not TSO. 1426 */ 1427 return skb_checksum_help(skb); 1428 } 1429 1430 return 0; 1431 } 1432 1433 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 1434 u8 il4_proto, u32 *type_cs_vlan_tso, 1435 u32 *ol_type_vlan_len_msec) 1436 { 1437 unsigned char *l2_hdr = skb->data; 1438 u32 l4_proto = ol4_proto; 1439 union l4_hdr_info l4; 1440 union l3_hdr_info l3; 1441 u32 l2_len, l3_len; 1442 1443 l4.hdr = skb_transport_header(skb); 1444 l3.hdr = skb_network_header(skb); 1445 1446 /* handle encapsulation skb */ 1447 if (skb->encapsulation) { 1448 /* If this is a not UDP/GRE encapsulation skb */ 1449 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) { 1450 /* drop the skb tunnel packet if hardware don't support, 1451 * because hardware can't calculate csum when TSO. 1452 */ 1453 if (skb_is_gso(skb)) 1454 return -EDOM; 1455 1456 /* the stack computes the IP header already, 1457 * driver calculate l4 checksum when not TSO. 1458 */ 1459 return skb_checksum_help(skb); 1460 } 1461 1462 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec); 1463 1464 /* switch to inner header */ 1465 l2_hdr = skb_inner_mac_header(skb); 1466 l3.hdr = skb_inner_network_header(skb); 1467 l4.hdr = skb_inner_transport_header(skb); 1468 l4_proto = il4_proto; 1469 } 1470 1471 hns3_set_l3_type(skb, l3, type_cs_vlan_tso); 1472 1473 /* compute inner(/normal) L2 header size, defined in 2 Bytes */ 1474 l2_len = l3.hdr - l2_hdr; 1475 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 1476 1477 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 1478 l3_len = l4.hdr - l3.hdr; 1479 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 1480 1481 return hns3_set_l4_csum_length(skb, l4, l4_proto, type_cs_vlan_tso); 1482 } 1483 1484 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring, 1485 struct sk_buff *skb) 1486 { 1487 struct hnae3_handle *handle = tx_ring->tqp->handle; 1488 struct hnae3_ae_dev *ae_dev; 1489 struct vlan_ethhdr *vhdr; 1490 int rc; 1491 1492 if (!(skb->protocol == htons(ETH_P_8021Q) || 1493 skb_vlan_tag_present(skb))) 1494 return 0; 1495 1496 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert 1497 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it 1498 * will cause RAS error. 1499 */ 1500 ae_dev = pci_get_drvdata(handle->pdev); 1501 if (unlikely(skb_vlan_tagged_multi(skb) && 1502 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 && 1503 handle->port_base_vlan_state == 1504 HNAE3_PORT_BASE_VLAN_ENABLE)) 1505 return -EINVAL; 1506 1507 if (skb->protocol == htons(ETH_P_8021Q) && 1508 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 1509 /* When HW VLAN acceleration is turned off, and the stack 1510 * sets the protocol to 802.1q, the driver just need to 1511 * set the protocol to the encapsulated ethertype. 1512 */ 1513 skb->protocol = vlan_get_protocol(skb); 1514 return 0; 1515 } 1516 1517 if (skb_vlan_tag_present(skb)) { 1518 /* Based on hw strategy, use out_vtag in two layer tag case, 1519 * and use inner_vtag in one tag case. 1520 */ 1521 if (skb->protocol == htons(ETH_P_8021Q) && 1522 handle->port_base_vlan_state == 1523 HNAE3_PORT_BASE_VLAN_DISABLE) 1524 rc = HNS3_OUTER_VLAN_TAG; 1525 else 1526 rc = HNS3_INNER_VLAN_TAG; 1527 1528 skb->protocol = vlan_get_protocol(skb); 1529 return rc; 1530 } 1531 1532 rc = skb_cow_head(skb, 0); 1533 if (unlikely(rc < 0)) 1534 return rc; 1535 1536 vhdr = (struct vlan_ethhdr *)skb->data; 1537 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT) 1538 & VLAN_PRIO_MASK); 1539 1540 skb->protocol = vlan_get_protocol(skb); 1541 return 0; 1542 } 1543 1544 /* check if the hardware is capable of checksum offloading */ 1545 static bool hns3_check_hw_tx_csum(struct sk_buff *skb) 1546 { 1547 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 1548 1549 /* Kindly note, due to backward compatibility of the TX descriptor, 1550 * HW checksum of the non-IP packets and GSO packets is handled at 1551 * different place in the following code 1552 */ 1553 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) || 1554 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state)) 1555 return false; 1556 1557 return true; 1558 } 1559 1560 struct hns3_desc_param { 1561 u32 paylen_ol4cs; 1562 u32 ol_type_vlan_len_msec; 1563 u32 type_cs_vlan_tso; 1564 u16 mss_hw_csum; 1565 u16 inner_vtag; 1566 u16 out_vtag; 1567 }; 1568 1569 static void hns3_init_desc_data(struct sk_buff *skb, struct hns3_desc_param *pa) 1570 { 1571 pa->paylen_ol4cs = skb->len; 1572 pa->ol_type_vlan_len_msec = 0; 1573 pa->type_cs_vlan_tso = 0; 1574 pa->mss_hw_csum = 0; 1575 pa->inner_vtag = 0; 1576 pa->out_vtag = 0; 1577 } 1578 1579 static int hns3_handle_vlan_info(struct hns3_enet_ring *ring, 1580 struct sk_buff *skb, 1581 struct hns3_desc_param *param) 1582 { 1583 int ret; 1584 1585 ret = hns3_handle_vtags(ring, skb); 1586 if (unlikely(ret < 0)) { 1587 hns3_ring_stats_update(ring, tx_vlan_err); 1588 return ret; 1589 } else if (ret == HNS3_INNER_VLAN_TAG) { 1590 param->inner_vtag = skb_vlan_tag_get(skb); 1591 param->inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1592 VLAN_PRIO_MASK; 1593 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1); 1594 } else if (ret == HNS3_OUTER_VLAN_TAG) { 1595 param->out_vtag = skb_vlan_tag_get(skb); 1596 param->out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1597 VLAN_PRIO_MASK; 1598 hns3_set_field(param->ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B, 1599 1); 1600 } 1601 return 0; 1602 } 1603 1604 static int hns3_handle_csum_partial(struct hns3_enet_ring *ring, 1605 struct sk_buff *skb, 1606 struct hns3_desc_cb *desc_cb, 1607 struct hns3_desc_param *param) 1608 { 1609 u8 ol4_proto, il4_proto; 1610 int ret; 1611 1612 if (hns3_check_hw_tx_csum(skb)) { 1613 /* set checksum start and offset, defined in 2 Bytes */ 1614 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_CSUM_START_S, 1615 skb_checksum_start_offset(skb) >> 1); 1616 hns3_set_field(param->ol_type_vlan_len_msec, 1617 HNS3_TXD_CSUM_OFFSET_S, 1618 skb->csum_offset >> 1); 1619 param->mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B); 1620 return 0; 1621 } 1622 1623 skb_reset_mac_len(skb); 1624 1625 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1626 if (unlikely(ret < 0)) { 1627 hns3_ring_stats_update(ring, tx_l4_proto_err); 1628 return ret; 1629 } 1630 1631 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto, 1632 ¶m->type_cs_vlan_tso, 1633 ¶m->ol_type_vlan_len_msec); 1634 if (unlikely(ret < 0)) { 1635 hns3_ring_stats_update(ring, tx_l2l3l4_err); 1636 return ret; 1637 } 1638 1639 ret = hns3_set_tso(skb, ¶m->paylen_ol4cs, ¶m->mss_hw_csum, 1640 ¶m->type_cs_vlan_tso, &desc_cb->send_bytes); 1641 if (unlikely(ret < 0)) { 1642 hns3_ring_stats_update(ring, tx_tso_err); 1643 return ret; 1644 } 1645 return 0; 1646 } 1647 1648 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring, 1649 struct sk_buff *skb, struct hns3_desc *desc, 1650 struct hns3_desc_cb *desc_cb) 1651 { 1652 struct hns3_desc_param param; 1653 int ret; 1654 1655 hns3_init_desc_data(skb, ¶m); 1656 ret = hns3_handle_vlan_info(ring, skb, ¶m); 1657 if (unlikely(ret < 0)) 1658 return ret; 1659 1660 desc_cb->send_bytes = skb->len; 1661 1662 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1663 ret = hns3_handle_csum_partial(ring, skb, desc_cb, ¶m); 1664 if (ret) 1665 return ret; 1666 } 1667 1668 /* Set txbd */ 1669 desc->tx.ol_type_vlan_len_msec = 1670 cpu_to_le32(param.ol_type_vlan_len_msec); 1671 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(param.type_cs_vlan_tso); 1672 desc->tx.paylen_ol4cs = cpu_to_le32(param.paylen_ol4cs); 1673 desc->tx.mss_hw_csum = cpu_to_le16(param.mss_hw_csum); 1674 desc->tx.vlan_tag = cpu_to_le16(param.inner_vtag); 1675 desc->tx.outer_vlan_tag = cpu_to_le16(param.out_vtag); 1676 1677 return 0; 1678 } 1679 1680 static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma, 1681 unsigned int size) 1682 { 1683 #define HNS3_LIKELY_BD_NUM 1 1684 1685 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1686 unsigned int frag_buf_num; 1687 int k, sizeoflast; 1688 1689 if (likely(size <= HNS3_MAX_BD_SIZE)) { 1690 desc->addr = cpu_to_le64(dma); 1691 desc->tx.send_size = cpu_to_le16(size); 1692 desc->tx.bdtp_fe_sc_vld_ra_ri = 1693 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1694 1695 trace_hns3_tx_desc(ring, ring->next_to_use); 1696 ring_ptr_move_fw(ring, next_to_use); 1697 return HNS3_LIKELY_BD_NUM; 1698 } 1699 1700 frag_buf_num = hns3_tx_bd_count(size); 1701 sizeoflast = size % HNS3_MAX_BD_SIZE; 1702 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1703 1704 /* When frag size is bigger than hardware limit, split this frag */ 1705 for (k = 0; k < frag_buf_num; k++) { 1706 /* now, fill the descriptor */ 1707 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1708 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1709 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1710 desc->tx.bdtp_fe_sc_vld_ra_ri = 1711 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1712 1713 trace_hns3_tx_desc(ring, ring->next_to_use); 1714 /* move ring pointer to next */ 1715 ring_ptr_move_fw(ring, next_to_use); 1716 1717 desc = &ring->desc[ring->next_to_use]; 1718 } 1719 1720 return frag_buf_num; 1721 } 1722 1723 static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv, 1724 unsigned int type) 1725 { 1726 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1727 struct device *dev = ring_to_dev(ring); 1728 unsigned int size; 1729 dma_addr_t dma; 1730 1731 if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) { 1732 struct sk_buff *skb = (struct sk_buff *)priv; 1733 1734 size = skb_headlen(skb); 1735 if (!size) 1736 return 0; 1737 1738 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1739 } else if (type & DESC_TYPE_BOUNCE_HEAD) { 1740 /* Head data has been filled in hns3_handle_tx_bounce(), 1741 * just return 0 here. 1742 */ 1743 return 0; 1744 } else { 1745 skb_frag_t *frag = (skb_frag_t *)priv; 1746 1747 size = skb_frag_size(frag); 1748 if (!size) 1749 return 0; 1750 1751 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1752 } 1753 1754 if (unlikely(dma_mapping_error(dev, dma))) { 1755 hns3_ring_stats_update(ring, sw_err_cnt); 1756 return -ENOMEM; 1757 } 1758 1759 desc_cb->priv = priv; 1760 desc_cb->length = size; 1761 desc_cb->dma = dma; 1762 desc_cb->type = type; 1763 1764 return hns3_fill_desc(ring, dma, size); 1765 } 1766 1767 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1768 unsigned int bd_num) 1769 { 1770 unsigned int size; 1771 int i; 1772 1773 size = skb_headlen(skb); 1774 while (size > HNS3_MAX_BD_SIZE) { 1775 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1776 size -= HNS3_MAX_BD_SIZE; 1777 1778 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1779 return bd_num; 1780 } 1781 1782 if (size) { 1783 bd_size[bd_num++] = size; 1784 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1785 return bd_num; 1786 } 1787 1788 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1789 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1790 size = skb_frag_size(frag); 1791 if (!size) 1792 continue; 1793 1794 while (size > HNS3_MAX_BD_SIZE) { 1795 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1796 size -= HNS3_MAX_BD_SIZE; 1797 1798 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1799 return bd_num; 1800 } 1801 1802 bd_size[bd_num++] = size; 1803 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1804 return bd_num; 1805 } 1806 1807 return bd_num; 1808 } 1809 1810 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1811 u8 max_non_tso_bd_num, unsigned int bd_num, 1812 unsigned int recursion_level) 1813 { 1814 #define HNS3_MAX_RECURSION_LEVEL 24 1815 1816 struct sk_buff *frag_skb; 1817 1818 /* If the total len is within the max bd limit */ 1819 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level && 1820 !skb_has_frag_list(skb) && 1821 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num)) 1822 return skb_shinfo(skb)->nr_frags + 1U; 1823 1824 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL)) 1825 return UINT_MAX; 1826 1827 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num); 1828 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM) 1829 return bd_num; 1830 1831 skb_walk_frags(skb, frag_skb) { 1832 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num, 1833 bd_num, recursion_level + 1); 1834 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1835 return bd_num; 1836 } 1837 1838 return bd_num; 1839 } 1840 1841 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb) 1842 { 1843 if (!skb->encapsulation) 1844 return skb_tcp_all_headers(skb); 1845 1846 return skb_inner_tcp_all_headers(skb); 1847 } 1848 1849 /* HW need every continuous max_non_tso_bd_num buffer data to be larger 1850 * than MSS, we simplify it by ensuring skb_headlen + the first continuous 1851 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss, 1852 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger 1853 * than MSS except the last max_non_tso_bd_num - 1 frags. 1854 */ 1855 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size, 1856 unsigned int bd_num, u8 max_non_tso_bd_num) 1857 { 1858 unsigned int tot_len = 0; 1859 int i; 1860 1861 for (i = 0; i < max_non_tso_bd_num - 1U; i++) 1862 tot_len += bd_size[i]; 1863 1864 /* ensure the first max_non_tso_bd_num frags is greater than 1865 * mss + header 1866 */ 1867 if (tot_len + bd_size[max_non_tso_bd_num - 1U] < 1868 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb)) 1869 return true; 1870 1871 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater 1872 * than mss except the last one. 1873 */ 1874 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) { 1875 tot_len -= bd_size[i]; 1876 tot_len += bd_size[i + max_non_tso_bd_num - 1U]; 1877 1878 if (tot_len < skb_shinfo(skb)->gso_size) 1879 return true; 1880 } 1881 1882 return false; 1883 } 1884 1885 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size) 1886 { 1887 int i; 1888 1889 for (i = 0; i < MAX_SKB_FRAGS; i++) 1890 size[i] = skb_frag_size(&shinfo->frags[i]); 1891 } 1892 1893 static int hns3_skb_linearize(struct hns3_enet_ring *ring, 1894 struct sk_buff *skb, 1895 unsigned int bd_num) 1896 { 1897 /* 'bd_num == UINT_MAX' means the skb' fraglist has a 1898 * recursion level of over HNS3_MAX_RECURSION_LEVEL. 1899 */ 1900 if (bd_num == UINT_MAX) { 1901 hns3_ring_stats_update(ring, over_max_recursion); 1902 return -ENOMEM; 1903 } 1904 1905 /* The skb->len has exceeded the hw limitation, linearization 1906 * will not help. 1907 */ 1908 if (skb->len > HNS3_MAX_TSO_SIZE || 1909 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)) { 1910 hns3_ring_stats_update(ring, hw_limitation); 1911 return -ENOMEM; 1912 } 1913 1914 if (__skb_linearize(skb)) { 1915 hns3_ring_stats_update(ring, sw_err_cnt); 1916 return -ENOMEM; 1917 } 1918 1919 return 0; 1920 } 1921 1922 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring, 1923 struct net_device *netdev, 1924 struct sk_buff *skb) 1925 { 1926 struct hns3_nic_priv *priv = netdev_priv(netdev); 1927 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num; 1928 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U]; 1929 unsigned int bd_num; 1930 1931 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0); 1932 if (unlikely(bd_num > max_non_tso_bd_num)) { 1933 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) && 1934 !hns3_skb_need_linearized(skb, bd_size, bd_num, 1935 max_non_tso_bd_num)) { 1936 trace_hns3_over_max_bd(skb); 1937 goto out; 1938 } 1939 1940 if (hns3_skb_linearize(ring, skb, bd_num)) 1941 return -ENOMEM; 1942 1943 bd_num = hns3_tx_bd_count(skb->len); 1944 1945 hns3_ring_stats_update(ring, tx_copy); 1946 } 1947 1948 out: 1949 if (likely(ring_space(ring) >= bd_num)) 1950 return bd_num; 1951 1952 netif_stop_subqueue(netdev, ring->queue_index); 1953 smp_mb(); /* Memory barrier before checking ring_space */ 1954 1955 /* Start queue in case hns3_clean_tx_ring has just made room 1956 * available and has not seen the queue stopped state performed 1957 * by netif_stop_subqueue above. 1958 */ 1959 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) && 1960 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 1961 netif_start_subqueue(netdev, ring->queue_index); 1962 return bd_num; 1963 } 1964 1965 hns3_ring_stats_update(ring, tx_busy); 1966 1967 return -EBUSY; 1968 } 1969 1970 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1971 { 1972 struct device *dev = ring_to_dev(ring); 1973 unsigned int i; 1974 1975 for (i = 0; i < ring->desc_num; i++) { 1976 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1977 struct hns3_desc_cb *desc_cb; 1978 1979 memset(desc, 0, sizeof(*desc)); 1980 1981 /* check if this is where we started */ 1982 if (ring->next_to_use == next_to_use_orig) 1983 break; 1984 1985 /* rollback one */ 1986 ring_ptr_move_bw(ring, next_to_use); 1987 1988 desc_cb = &ring->desc_cb[ring->next_to_use]; 1989 1990 if (!desc_cb->dma) 1991 continue; 1992 1993 /* unmap the descriptor dma address */ 1994 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB)) 1995 dma_unmap_single(dev, desc_cb->dma, desc_cb->length, 1996 DMA_TO_DEVICE); 1997 else if (desc_cb->type & 1998 (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) 1999 hns3_tx_spare_rollback(ring, desc_cb->length); 2000 else if (desc_cb->length) 2001 dma_unmap_page(dev, desc_cb->dma, desc_cb->length, 2002 DMA_TO_DEVICE); 2003 2004 desc_cb->length = 0; 2005 desc_cb->dma = 0; 2006 desc_cb->type = DESC_TYPE_UNKNOWN; 2007 } 2008 } 2009 2010 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring, 2011 struct sk_buff *skb, unsigned int type) 2012 { 2013 struct sk_buff *frag_skb; 2014 int i, ret, bd_num = 0; 2015 2016 ret = hns3_map_and_fill_desc(ring, skb, type); 2017 if (unlikely(ret < 0)) 2018 return ret; 2019 2020 bd_num += ret; 2021 2022 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2023 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2024 2025 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE); 2026 if (unlikely(ret < 0)) 2027 return ret; 2028 2029 bd_num += ret; 2030 } 2031 2032 skb_walk_frags(skb, frag_skb) { 2033 ret = hns3_fill_skb_to_desc(ring, frag_skb, 2034 DESC_TYPE_FRAGLIST_SKB); 2035 if (unlikely(ret < 0)) 2036 return ret; 2037 2038 bd_num += ret; 2039 } 2040 2041 return bd_num; 2042 } 2043 2044 static void hns3_tx_push_bd(struct hns3_enet_ring *ring, int num) 2045 { 2046 #define HNS3_BYTES_PER_64BIT 8 2047 2048 struct hns3_desc desc[HNS3_MAX_PUSH_BD_NUM] = {}; 2049 int offset = 0; 2050 2051 /* make sure everything is visible to device before 2052 * excuting tx push or updating doorbell 2053 */ 2054 dma_wmb(); 2055 2056 do { 2057 int idx = (ring->next_to_use - num + ring->desc_num) % 2058 ring->desc_num; 2059 2060 u64_stats_update_begin(&ring->syncp); 2061 ring->stats.tx_push++; 2062 u64_stats_update_end(&ring->syncp); 2063 memcpy(&desc[offset], &ring->desc[idx], 2064 sizeof(struct hns3_desc)); 2065 offset++; 2066 } while (--num); 2067 2068 __iowrite64_copy(ring->tqp->mem_base, desc, 2069 (sizeof(struct hns3_desc) * HNS3_MAX_PUSH_BD_NUM) / 2070 HNS3_BYTES_PER_64BIT); 2071 2072 io_stop_wc(); 2073 } 2074 2075 static void hns3_tx_mem_doorbell(struct hns3_enet_ring *ring) 2076 { 2077 #define HNS3_MEM_DOORBELL_OFFSET 64 2078 2079 __le64 bd_num = cpu_to_le64((u64)ring->pending_buf); 2080 2081 /* make sure everything is visible to device before 2082 * excuting tx push or updating doorbell 2083 */ 2084 dma_wmb(); 2085 2086 __iowrite64_copy(ring->tqp->mem_base + HNS3_MEM_DOORBELL_OFFSET, 2087 &bd_num, 1); 2088 u64_stats_update_begin(&ring->syncp); 2089 ring->stats.tx_mem_doorbell += ring->pending_buf; 2090 u64_stats_update_end(&ring->syncp); 2091 2092 io_stop_wc(); 2093 } 2094 2095 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num, 2096 bool doorbell) 2097 { 2098 struct net_device *netdev = ring_to_netdev(ring); 2099 struct hns3_nic_priv *priv = netdev_priv(netdev); 2100 2101 /* when tx push is enabled, the packet whose number of BD below 2102 * HNS3_MAX_PUSH_BD_NUM can be pushed directly. 2103 */ 2104 if (test_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state) && num && 2105 !ring->pending_buf && num <= HNS3_MAX_PUSH_BD_NUM && doorbell) { 2106 hns3_tx_push_bd(ring, num); 2107 WRITE_ONCE(ring->last_to_use, ring->next_to_use); 2108 return; 2109 } 2110 2111 ring->pending_buf += num; 2112 2113 if (!doorbell) { 2114 hns3_ring_stats_update(ring, tx_more); 2115 return; 2116 } 2117 2118 if (ring->tqp->mem_base) 2119 hns3_tx_mem_doorbell(ring); 2120 else 2121 writel(ring->pending_buf, 2122 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG); 2123 2124 ring->pending_buf = 0; 2125 WRITE_ONCE(ring->last_to_use, ring->next_to_use); 2126 } 2127 2128 static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb, 2129 struct hns3_desc *desc) 2130 { 2131 struct hnae3_handle *h = hns3_get_handle(netdev); 2132 2133 if (!(h->ae_algo->ops->set_tx_hwts_info && 2134 h->ae_algo->ops->set_tx_hwts_info(h, skb))) 2135 return; 2136 2137 desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B)); 2138 } 2139 2140 static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring, 2141 struct sk_buff *skb) 2142 { 2143 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 2144 unsigned int type = DESC_TYPE_BOUNCE_HEAD; 2145 unsigned int size = skb_headlen(skb); 2146 dma_addr_t dma; 2147 int bd_num = 0; 2148 u32 cb_len; 2149 void *buf; 2150 int ret; 2151 2152 if (skb->len <= ring->tx_copybreak) { 2153 size = skb->len; 2154 type = DESC_TYPE_BOUNCE_ALL; 2155 } 2156 2157 /* hns3_can_use_tx_bounce() is called to ensure the below 2158 * function can always return the tx buffer. 2159 */ 2160 buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len); 2161 2162 ret = skb_copy_bits(skb, 0, buf, size); 2163 if (unlikely(ret < 0)) { 2164 hns3_tx_spare_rollback(ring, cb_len); 2165 hns3_ring_stats_update(ring, copy_bits_err); 2166 return ret; 2167 } 2168 2169 desc_cb->priv = skb; 2170 desc_cb->length = cb_len; 2171 desc_cb->dma = dma; 2172 desc_cb->type = type; 2173 2174 bd_num += hns3_fill_desc(ring, dma, size); 2175 2176 if (type == DESC_TYPE_BOUNCE_HEAD) { 2177 ret = hns3_fill_skb_to_desc(ring, skb, 2178 DESC_TYPE_BOUNCE_HEAD); 2179 if (unlikely(ret < 0)) 2180 return ret; 2181 2182 bd_num += ret; 2183 } 2184 2185 dma_sync_single_for_device(ring_to_dev(ring), dma, size, 2186 DMA_TO_DEVICE); 2187 2188 hns3_ring_stats_update(ring, tx_bounce); 2189 2190 return bd_num; 2191 } 2192 2193 static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring, 2194 struct sk_buff *skb) 2195 { 2196 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 2197 u32 nfrag = skb_shinfo(skb)->nr_frags + 1; 2198 struct sg_table *sgt; 2199 int i, bd_num = 0; 2200 dma_addr_t dma; 2201 u32 cb_len; 2202 int nents; 2203 2204 if (skb_has_frag_list(skb)) 2205 nfrag = HNS3_MAX_TSO_BD_NUM; 2206 2207 /* hns3_can_use_tx_sgl() is called to ensure the below 2208 * function can always return the tx buffer. 2209 */ 2210 sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag), 2211 &dma, &cb_len); 2212 2213 /* scatterlist follows by the sg table */ 2214 sgt->sgl = (struct scatterlist *)(sgt + 1); 2215 sg_init_table(sgt->sgl, nfrag); 2216 nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len); 2217 if (unlikely(nents < 0)) { 2218 hns3_tx_spare_rollback(ring, cb_len); 2219 hns3_ring_stats_update(ring, skb2sgl_err); 2220 return -ENOMEM; 2221 } 2222 2223 sgt->orig_nents = nents; 2224 sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents, 2225 DMA_TO_DEVICE); 2226 if (unlikely(!sgt->nents)) { 2227 hns3_tx_spare_rollback(ring, cb_len); 2228 hns3_ring_stats_update(ring, map_sg_err); 2229 return -ENOMEM; 2230 } 2231 2232 desc_cb->priv = skb; 2233 desc_cb->length = cb_len; 2234 desc_cb->dma = dma; 2235 desc_cb->type = DESC_TYPE_SGL_SKB; 2236 2237 for (i = 0; i < sgt->nents; i++) 2238 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i), 2239 sg_dma_len(sgt->sgl + i)); 2240 hns3_ring_stats_update(ring, tx_sgl); 2241 2242 return bd_num; 2243 } 2244 2245 static int hns3_handle_desc_filling(struct hns3_enet_ring *ring, 2246 struct sk_buff *skb) 2247 { 2248 u32 space; 2249 2250 if (!ring->tx_spare) 2251 goto out; 2252 2253 space = hns3_tx_spare_space(ring); 2254 2255 if (hns3_can_use_tx_sgl(ring, skb, space)) 2256 return hns3_handle_tx_sgl(ring, skb); 2257 2258 if (hns3_can_use_tx_bounce(ring, skb, space)) 2259 return hns3_handle_tx_bounce(ring, skb); 2260 2261 out: 2262 return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB); 2263 } 2264 2265 static int hns3_handle_skb_desc(struct hns3_enet_ring *ring, 2266 struct sk_buff *skb, 2267 struct hns3_desc_cb *desc_cb, 2268 int next_to_use_head) 2269 { 2270 int ret; 2271 2272 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use], 2273 desc_cb); 2274 if (unlikely(ret < 0)) 2275 goto fill_err; 2276 2277 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is 2278 * zero, which is unlikely, and 'ret > 0' means how many tx desc 2279 * need to be notified to the hw. 2280 */ 2281 ret = hns3_handle_desc_filling(ring, skb); 2282 if (likely(ret > 0)) 2283 return ret; 2284 2285 fill_err: 2286 hns3_clear_desc(ring, next_to_use_head); 2287 return ret; 2288 } 2289 2290 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 2291 { 2292 struct hns3_nic_priv *priv = netdev_priv(netdev); 2293 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping]; 2294 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 2295 struct netdev_queue *dev_queue; 2296 int pre_ntu, ret; 2297 bool doorbell; 2298 2299 /* Hardware can only handle short frames above 32 bytes */ 2300 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) { 2301 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 2302 2303 hns3_ring_stats_update(ring, sw_err_cnt); 2304 2305 return NETDEV_TX_OK; 2306 } 2307 2308 /* Prefetch the data used later */ 2309 prefetch(skb->data); 2310 2311 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb); 2312 if (unlikely(ret <= 0)) { 2313 if (ret == -EBUSY) { 2314 hns3_tx_doorbell(ring, 0, true); 2315 return NETDEV_TX_BUSY; 2316 } 2317 2318 hns3_rl_err(netdev, "xmit error: %d!\n", ret); 2319 goto out_err_tx_ok; 2320 } 2321 2322 ret = hns3_handle_skb_desc(ring, skb, desc_cb, ring->next_to_use); 2323 if (unlikely(ret <= 0)) 2324 goto out_err_tx_ok; 2325 2326 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) : 2327 (ring->desc_num - 1); 2328 2329 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 2330 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]); 2331 2332 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |= 2333 cpu_to_le16(BIT(HNS3_TXD_FE_B)); 2334 trace_hns3_tx_desc(ring, pre_ntu); 2335 2336 skb_tx_timestamp(skb); 2337 2338 /* Complete translate all packets */ 2339 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index); 2340 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes, 2341 netdev_xmit_more()); 2342 hns3_tx_doorbell(ring, ret, doorbell); 2343 2344 return NETDEV_TX_OK; 2345 2346 out_err_tx_ok: 2347 dev_kfree_skb_any(skb); 2348 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 2349 return NETDEV_TX_OK; 2350 } 2351 2352 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 2353 { 2354 char format_mac_addr_perm[HNAE3_FORMAT_MAC_ADDR_LEN]; 2355 char format_mac_addr_sa[HNAE3_FORMAT_MAC_ADDR_LEN]; 2356 struct hnae3_handle *h = hns3_get_handle(netdev); 2357 struct sockaddr *mac_addr = p; 2358 int ret; 2359 2360 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 2361 return -EADDRNOTAVAIL; 2362 2363 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 2364 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data); 2365 netdev_info(netdev, "already using mac address %s\n", 2366 format_mac_addr_sa); 2367 return 0; 2368 } 2369 2370 /* For VF device, if there is a perm_addr, then the user will not 2371 * be allowed to change the address. 2372 */ 2373 if (!hns3_is_phys_func(h->pdev) && 2374 !is_zero_ether_addr(netdev->perm_addr)) { 2375 hnae3_format_mac_addr(format_mac_addr_perm, netdev->perm_addr); 2376 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data); 2377 netdev_err(netdev, "has permanent MAC %s, user MAC %s not allow\n", 2378 format_mac_addr_perm, format_mac_addr_sa); 2379 return -EPERM; 2380 } 2381 2382 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 2383 if (ret) { 2384 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 2385 return ret; 2386 } 2387 2388 eth_hw_addr_set(netdev, mac_addr->sa_data); 2389 2390 return 0; 2391 } 2392 2393 static int hns3_nic_do_ioctl(struct net_device *netdev, 2394 struct ifreq *ifr, int cmd) 2395 { 2396 struct hnae3_handle *h = hns3_get_handle(netdev); 2397 2398 if (!netif_running(netdev)) 2399 return -EINVAL; 2400 2401 if (!h->ae_algo->ops->do_ioctl) 2402 return -EOPNOTSUPP; 2403 2404 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 2405 } 2406 2407 static int hns3_nic_set_features(struct net_device *netdev, 2408 netdev_features_t features) 2409 { 2410 netdev_features_t changed = netdev->features ^ features; 2411 struct hns3_nic_priv *priv = netdev_priv(netdev); 2412 struct hnae3_handle *h = priv->ae_handle; 2413 bool enable; 2414 int ret; 2415 2416 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 2417 enable = !!(features & NETIF_F_GRO_HW); 2418 ret = h->ae_algo->ops->set_gro_en(h, enable); 2419 if (ret) 2420 return ret; 2421 } 2422 2423 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 2424 h->ae_algo->ops->enable_hw_strip_rxvtag) { 2425 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 2426 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 2427 if (ret) 2428 return ret; 2429 } 2430 2431 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 2432 enable = !!(features & NETIF_F_NTUPLE); 2433 h->ae_algo->ops->enable_fd(h, enable); 2434 } 2435 2436 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) && 2437 h->ae_algo->ops->cls_flower_active(h)) { 2438 netdev_err(netdev, 2439 "there are offloaded TC filters active, cannot disable HW TC offload"); 2440 return -EINVAL; 2441 } 2442 2443 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 2444 h->ae_algo->ops->enable_vlan_filter) { 2445 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER); 2446 ret = h->ae_algo->ops->enable_vlan_filter(h, enable); 2447 if (ret) 2448 return ret; 2449 } 2450 2451 netdev->features = features; 2452 return 0; 2453 } 2454 2455 static netdev_features_t hns3_features_check(struct sk_buff *skb, 2456 struct net_device *dev, 2457 netdev_features_t features) 2458 { 2459 #define HNS3_MAX_HDR_LEN 480U 2460 #define HNS3_MAX_L4_HDR_LEN 60U 2461 2462 size_t len; 2463 2464 if (skb->ip_summed != CHECKSUM_PARTIAL) 2465 return features; 2466 2467 if (skb->encapsulation) 2468 len = skb_inner_transport_header(skb) - skb->data; 2469 else 2470 len = skb_transport_header(skb) - skb->data; 2471 2472 /* Assume L4 is 60 byte as TCP is the only protocol with a 2473 * a flexible value, and it's max len is 60 bytes. 2474 */ 2475 len += HNS3_MAX_L4_HDR_LEN; 2476 2477 /* Hardware only supports checksum on the skb with a max header 2478 * len of 480 bytes. 2479 */ 2480 if (len > HNS3_MAX_HDR_LEN) 2481 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2482 2483 return features; 2484 } 2485 2486 static void hns3_fetch_stats(struct rtnl_link_stats64 *stats, 2487 struct hns3_enet_ring *ring, bool is_tx) 2488 { 2489 unsigned int start; 2490 2491 do { 2492 start = u64_stats_fetch_begin(&ring->syncp); 2493 if (is_tx) { 2494 stats->tx_bytes += ring->stats.tx_bytes; 2495 stats->tx_packets += ring->stats.tx_pkts; 2496 stats->tx_dropped += ring->stats.sw_err_cnt; 2497 stats->tx_dropped += ring->stats.tx_vlan_err; 2498 stats->tx_dropped += ring->stats.tx_l4_proto_err; 2499 stats->tx_dropped += ring->stats.tx_l2l3l4_err; 2500 stats->tx_dropped += ring->stats.tx_tso_err; 2501 stats->tx_dropped += ring->stats.over_max_recursion; 2502 stats->tx_dropped += ring->stats.hw_limitation; 2503 stats->tx_dropped += ring->stats.copy_bits_err; 2504 stats->tx_dropped += ring->stats.skb2sgl_err; 2505 stats->tx_dropped += ring->stats.map_sg_err; 2506 stats->tx_errors += ring->stats.sw_err_cnt; 2507 stats->tx_errors += ring->stats.tx_vlan_err; 2508 stats->tx_errors += ring->stats.tx_l4_proto_err; 2509 stats->tx_errors += ring->stats.tx_l2l3l4_err; 2510 stats->tx_errors += ring->stats.tx_tso_err; 2511 stats->tx_errors += ring->stats.over_max_recursion; 2512 stats->tx_errors += ring->stats.hw_limitation; 2513 stats->tx_errors += ring->stats.copy_bits_err; 2514 stats->tx_errors += ring->stats.skb2sgl_err; 2515 stats->tx_errors += ring->stats.map_sg_err; 2516 } else { 2517 stats->rx_bytes += ring->stats.rx_bytes; 2518 stats->rx_packets += ring->stats.rx_pkts; 2519 stats->rx_dropped += ring->stats.l2_err; 2520 stats->rx_errors += ring->stats.l2_err; 2521 stats->rx_errors += ring->stats.l3l4_csum_err; 2522 stats->rx_crc_errors += ring->stats.l2_err; 2523 stats->multicast += ring->stats.rx_multicast; 2524 stats->rx_length_errors += ring->stats.err_pkt_len; 2525 } 2526 } while (u64_stats_fetch_retry(&ring->syncp, start)); 2527 } 2528 2529 static void hns3_nic_get_stats64(struct net_device *netdev, 2530 struct rtnl_link_stats64 *stats) 2531 { 2532 struct hns3_nic_priv *priv = netdev_priv(netdev); 2533 int queue_num = priv->ae_handle->kinfo.num_tqps; 2534 struct hnae3_handle *handle = priv->ae_handle; 2535 struct rtnl_link_stats64 ring_total_stats; 2536 struct hns3_enet_ring *ring; 2537 unsigned int idx; 2538 2539 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 2540 return; 2541 2542 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 2543 2544 memset(&ring_total_stats, 0, sizeof(ring_total_stats)); 2545 for (idx = 0; idx < queue_num; idx++) { 2546 /* fetch the tx stats */ 2547 ring = &priv->ring[idx]; 2548 hns3_fetch_stats(&ring_total_stats, ring, true); 2549 2550 /* fetch the rx stats */ 2551 ring = &priv->ring[idx + queue_num]; 2552 hns3_fetch_stats(&ring_total_stats, ring, false); 2553 } 2554 2555 stats->tx_bytes = ring_total_stats.tx_bytes; 2556 stats->tx_packets = ring_total_stats.tx_packets; 2557 stats->rx_bytes = ring_total_stats.rx_bytes; 2558 stats->rx_packets = ring_total_stats.rx_packets; 2559 2560 stats->rx_errors = ring_total_stats.rx_errors; 2561 stats->multicast = ring_total_stats.multicast; 2562 stats->rx_length_errors = ring_total_stats.rx_length_errors; 2563 stats->rx_crc_errors = ring_total_stats.rx_crc_errors; 2564 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 2565 2566 stats->tx_errors = ring_total_stats.tx_errors; 2567 stats->rx_dropped = ring_total_stats.rx_dropped; 2568 stats->tx_dropped = ring_total_stats.tx_dropped; 2569 stats->collisions = netdev->stats.collisions; 2570 stats->rx_over_errors = netdev->stats.rx_over_errors; 2571 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 2572 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 2573 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 2574 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 2575 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 2576 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 2577 stats->tx_window_errors = netdev->stats.tx_window_errors; 2578 stats->rx_compressed = netdev->stats.rx_compressed; 2579 stats->tx_compressed = netdev->stats.tx_compressed; 2580 } 2581 2582 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 2583 { 2584 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 2585 struct hnae3_knic_private_info *kinfo; 2586 u8 tc = mqprio_qopt->qopt.num_tc; 2587 u16 mode = mqprio_qopt->mode; 2588 u8 hw = mqprio_qopt->qopt.hw; 2589 struct hnae3_handle *h; 2590 2591 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 2592 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 2593 return -EOPNOTSUPP; 2594 2595 if (tc > HNAE3_MAX_TC) 2596 return -EINVAL; 2597 2598 if (!netdev) 2599 return -EINVAL; 2600 2601 h = hns3_get_handle(netdev); 2602 kinfo = &h->kinfo; 2603 2604 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc); 2605 2606 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 2607 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP; 2608 } 2609 2610 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv, 2611 struct flow_cls_offload *flow) 2612 { 2613 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid); 2614 struct hnae3_handle *h = hns3_get_handle(priv->netdev); 2615 2616 switch (flow->command) { 2617 case FLOW_CLS_REPLACE: 2618 if (h->ae_algo->ops->add_cls_flower) 2619 return h->ae_algo->ops->add_cls_flower(h, flow, tc); 2620 break; 2621 case FLOW_CLS_DESTROY: 2622 if (h->ae_algo->ops->del_cls_flower) 2623 return h->ae_algo->ops->del_cls_flower(h, flow); 2624 break; 2625 default: 2626 break; 2627 } 2628 2629 return -EOPNOTSUPP; 2630 } 2631 2632 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2633 void *cb_priv) 2634 { 2635 struct hns3_nic_priv *priv = cb_priv; 2636 2637 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data)) 2638 return -EOPNOTSUPP; 2639 2640 switch (type) { 2641 case TC_SETUP_CLSFLOWER: 2642 return hns3_setup_tc_cls_flower(priv, type_data); 2643 default: 2644 return -EOPNOTSUPP; 2645 } 2646 } 2647 2648 static LIST_HEAD(hns3_block_cb_list); 2649 2650 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 2651 void *type_data) 2652 { 2653 struct hns3_nic_priv *priv = netdev_priv(dev); 2654 int ret; 2655 2656 switch (type) { 2657 case TC_SETUP_QDISC_MQPRIO: 2658 ret = hns3_setup_tc(dev, type_data); 2659 break; 2660 case TC_SETUP_BLOCK: 2661 ret = flow_block_cb_setup_simple(type_data, 2662 &hns3_block_cb_list, 2663 hns3_setup_tc_block_cb, 2664 priv, priv, true); 2665 break; 2666 default: 2667 return -EOPNOTSUPP; 2668 } 2669 2670 return ret; 2671 } 2672 2673 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 2674 __be16 proto, u16 vid) 2675 { 2676 struct hnae3_handle *h = hns3_get_handle(netdev); 2677 int ret = -EIO; 2678 2679 if (h->ae_algo->ops->set_vlan_filter) 2680 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 2681 2682 return ret; 2683 } 2684 2685 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 2686 __be16 proto, u16 vid) 2687 { 2688 struct hnae3_handle *h = hns3_get_handle(netdev); 2689 int ret = -EIO; 2690 2691 if (h->ae_algo->ops->set_vlan_filter) 2692 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 2693 2694 return ret; 2695 } 2696 2697 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2698 u8 qos, __be16 vlan_proto) 2699 { 2700 struct hnae3_handle *h = hns3_get_handle(netdev); 2701 int ret = -EIO; 2702 2703 netif_dbg(h, drv, netdev, 2704 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n", 2705 vf, vlan, qos, ntohs(vlan_proto)); 2706 2707 if (h->ae_algo->ops->set_vf_vlan_filter) 2708 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 2709 qos, vlan_proto); 2710 2711 return ret; 2712 } 2713 2714 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable) 2715 { 2716 struct hnae3_handle *handle = hns3_get_handle(netdev); 2717 2718 if (hns3_nic_resetting(netdev)) 2719 return -EBUSY; 2720 2721 if (!handle->ae_algo->ops->set_vf_spoofchk) 2722 return -EOPNOTSUPP; 2723 2724 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable); 2725 } 2726 2727 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable) 2728 { 2729 struct hnae3_handle *handle = hns3_get_handle(netdev); 2730 2731 if (!handle->ae_algo->ops->set_vf_trust) 2732 return -EOPNOTSUPP; 2733 2734 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable); 2735 } 2736 2737 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 2738 { 2739 struct hnae3_handle *h = hns3_get_handle(netdev); 2740 int ret; 2741 2742 if (hns3_nic_resetting(netdev)) 2743 return -EBUSY; 2744 2745 if (!h->ae_algo->ops->set_mtu) 2746 return -EOPNOTSUPP; 2747 2748 netif_dbg(h, drv, netdev, 2749 "change mtu from %u to %d\n", netdev->mtu, new_mtu); 2750 2751 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 2752 if (ret) 2753 netdev_err(netdev, "failed to change MTU in hardware %d\n", 2754 ret); 2755 else 2756 netdev->mtu = new_mtu; 2757 2758 return ret; 2759 } 2760 2761 static int hns3_get_timeout_queue(struct net_device *ndev) 2762 { 2763 int i; 2764 2765 /* Find the stopped queue the same way the stack does */ 2766 for (i = 0; i < ndev->num_tx_queues; i++) { 2767 struct netdev_queue *q; 2768 unsigned long trans_start; 2769 2770 q = netdev_get_tx_queue(ndev, i); 2771 trans_start = READ_ONCE(q->trans_start); 2772 if (netif_xmit_stopped(q) && 2773 time_after(jiffies, 2774 (trans_start + ndev->watchdog_timeo))) { 2775 #ifdef CONFIG_BQL 2776 struct dql *dql = &q->dql; 2777 2778 netdev_info(ndev, "DQL info last_cnt: %u, queued: %u, adj_limit: %u, completed: %u\n", 2779 dql->last_obj_cnt, dql->num_queued, 2780 dql->adj_limit, dql->num_completed); 2781 #endif 2782 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n", 2783 q->state, 2784 jiffies_to_msecs(jiffies - trans_start)); 2785 break; 2786 } 2787 } 2788 2789 return i; 2790 } 2791 2792 static void hns3_dump_queue_stats(struct net_device *ndev, 2793 struct hns3_enet_ring *tx_ring, 2794 int timeout_queue) 2795 { 2796 struct napi_struct *napi = &tx_ring->tqp_vector->napi; 2797 struct hns3_nic_priv *priv = netdev_priv(ndev); 2798 2799 netdev_info(ndev, 2800 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n", 2801 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use, 2802 tx_ring->next_to_clean, napi->state); 2803 2804 netdev_info(ndev, 2805 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n", 2806 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes, 2807 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf); 2808 2809 netdev_info(ndev, 2810 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n", 2811 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more, 2812 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy); 2813 2814 netdev_info(ndev, "tx_push: %llu, tx_mem_doorbell: %llu\n", 2815 tx_ring->stats.tx_push, tx_ring->stats.tx_mem_doorbell); 2816 } 2817 2818 static void hns3_dump_queue_reg(struct net_device *ndev, 2819 struct hns3_enet_ring *tx_ring) 2820 { 2821 netdev_info(ndev, 2822 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n", 2823 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_NUM_REG), 2824 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_HEAD_REG), 2825 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TAIL_REG), 2826 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_ERR_REG), 2827 readl(tx_ring->tqp_vector->mask_addr)); 2828 netdev_info(ndev, 2829 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n", 2830 hns3_tqp_read_reg(tx_ring, HNS3_RING_EN_REG), 2831 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TC_REG), 2832 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_FBDNUM_REG), 2833 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_OFFSET_REG), 2834 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_EBDNUM_REG), 2835 hns3_tqp_read_reg(tx_ring, 2836 HNS3_RING_TX_RING_EBD_OFFSET_REG)); 2837 } 2838 2839 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 2840 { 2841 struct hns3_nic_priv *priv = netdev_priv(ndev); 2842 struct hnae3_handle *h = hns3_get_handle(ndev); 2843 struct hns3_enet_ring *tx_ring; 2844 int timeout_queue; 2845 2846 timeout_queue = hns3_get_timeout_queue(ndev); 2847 if (timeout_queue >= ndev->num_tx_queues) { 2848 netdev_info(ndev, 2849 "no netdev TX timeout queue found, timeout count: %llu\n", 2850 priv->tx_timeout_count); 2851 return false; 2852 } 2853 2854 priv->tx_timeout_count++; 2855 2856 tx_ring = &priv->ring[timeout_queue]; 2857 hns3_dump_queue_stats(ndev, tx_ring, timeout_queue); 2858 2859 /* When mac received many pause frames continuous, it's unable to send 2860 * packets, which may cause tx timeout 2861 */ 2862 if (h->ae_algo->ops->get_mac_stats) { 2863 struct hns3_mac_stats mac_stats; 2864 2865 h->ae_algo->ops->get_mac_stats(h, &mac_stats); 2866 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n", 2867 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt); 2868 } 2869 2870 hns3_dump_queue_reg(ndev, tx_ring); 2871 2872 return true; 2873 } 2874 2875 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue) 2876 { 2877 struct hns3_nic_priv *priv = netdev_priv(ndev); 2878 struct hnae3_handle *h = priv->ae_handle; 2879 2880 if (!hns3_get_tx_timeo_queue_info(ndev)) 2881 return; 2882 2883 /* request the reset, and let the hclge to determine 2884 * which reset level should be done 2885 */ 2886 if (h->ae_algo->ops->reset_event) 2887 h->ae_algo->ops->reset_event(h->pdev, h); 2888 } 2889 2890 #ifdef CONFIG_RFS_ACCEL 2891 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 2892 u16 rxq_index, u32 flow_id) 2893 { 2894 struct hnae3_handle *h = hns3_get_handle(dev); 2895 struct flow_keys fkeys; 2896 2897 if (!h->ae_algo->ops->add_arfs_entry) 2898 return -EOPNOTSUPP; 2899 2900 if (skb->encapsulation) 2901 return -EPROTONOSUPPORT; 2902 2903 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0)) 2904 return -EPROTONOSUPPORT; 2905 2906 if ((fkeys.basic.n_proto != htons(ETH_P_IP) && 2907 fkeys.basic.n_proto != htons(ETH_P_IPV6)) || 2908 (fkeys.basic.ip_proto != IPPROTO_TCP && 2909 fkeys.basic.ip_proto != IPPROTO_UDP)) 2910 return -EPROTONOSUPPORT; 2911 2912 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys); 2913 } 2914 #endif 2915 2916 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf, 2917 struct ifla_vf_info *ivf) 2918 { 2919 struct hnae3_handle *h = hns3_get_handle(ndev); 2920 2921 if (!h->ae_algo->ops->get_vf_config) 2922 return -EOPNOTSUPP; 2923 2924 return h->ae_algo->ops->get_vf_config(h, vf, ivf); 2925 } 2926 2927 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf, 2928 int link_state) 2929 { 2930 struct hnae3_handle *h = hns3_get_handle(ndev); 2931 2932 if (!h->ae_algo->ops->set_vf_link_state) 2933 return -EOPNOTSUPP; 2934 2935 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state); 2936 } 2937 2938 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf, 2939 int min_tx_rate, int max_tx_rate) 2940 { 2941 struct hnae3_handle *h = hns3_get_handle(ndev); 2942 2943 if (!h->ae_algo->ops->set_vf_rate) 2944 return -EOPNOTSUPP; 2945 2946 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate, 2947 false); 2948 } 2949 2950 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) 2951 { 2952 struct hnae3_handle *h = hns3_get_handle(netdev); 2953 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 2954 2955 if (!h->ae_algo->ops->set_vf_mac) 2956 return -EOPNOTSUPP; 2957 2958 if (is_multicast_ether_addr(mac)) { 2959 hnae3_format_mac_addr(format_mac_addr, mac); 2960 netdev_err(netdev, 2961 "Invalid MAC:%s specified. Could not set MAC\n", 2962 format_mac_addr); 2963 return -EINVAL; 2964 } 2965 2966 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac); 2967 } 2968 2969 #define HNS3_INVALID_DSCP 0xff 2970 #define HNS3_DSCP_SHIFT 2 2971 2972 static u8 hns3_get_skb_dscp(struct sk_buff *skb) 2973 { 2974 __be16 protocol = skb->protocol; 2975 u8 dscp = HNS3_INVALID_DSCP; 2976 2977 if (protocol == htons(ETH_P_8021Q)) 2978 protocol = vlan_get_protocol(skb); 2979 2980 if (protocol == htons(ETH_P_IP)) 2981 dscp = ipv4_get_dsfield(ip_hdr(skb)) >> HNS3_DSCP_SHIFT; 2982 else if (protocol == htons(ETH_P_IPV6)) 2983 dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> HNS3_DSCP_SHIFT; 2984 2985 return dscp; 2986 } 2987 2988 static u16 hns3_nic_select_queue(struct net_device *netdev, 2989 struct sk_buff *skb, 2990 struct net_device *sb_dev) 2991 { 2992 struct hnae3_handle *h = hns3_get_handle(netdev); 2993 u8 dscp; 2994 2995 if (h->kinfo.tc_map_mode != HNAE3_TC_MAP_MODE_DSCP || 2996 !h->ae_algo->ops->get_dscp_prio) 2997 goto out; 2998 2999 dscp = hns3_get_skb_dscp(skb); 3000 if (unlikely(dscp >= HNAE3_MAX_DSCP)) 3001 goto out; 3002 3003 skb->priority = h->kinfo.dscp_prio[dscp]; 3004 if (skb->priority == HNAE3_PRIO_ID_INVALID) 3005 skb->priority = 0; 3006 3007 out: 3008 return netdev_pick_tx(netdev, skb, sb_dev); 3009 } 3010 3011 static const struct net_device_ops hns3_nic_netdev_ops = { 3012 .ndo_open = hns3_nic_net_open, 3013 .ndo_stop = hns3_nic_net_stop, 3014 .ndo_start_xmit = hns3_nic_net_xmit, 3015 .ndo_tx_timeout = hns3_nic_net_timeout, 3016 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 3017 .ndo_eth_ioctl = hns3_nic_do_ioctl, 3018 .ndo_change_mtu = hns3_nic_change_mtu, 3019 .ndo_set_features = hns3_nic_set_features, 3020 .ndo_features_check = hns3_features_check, 3021 .ndo_get_stats64 = hns3_nic_get_stats64, 3022 .ndo_setup_tc = hns3_nic_setup_tc, 3023 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 3024 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 3025 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 3026 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 3027 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk, 3028 .ndo_set_vf_trust = hns3_set_vf_trust, 3029 #ifdef CONFIG_RFS_ACCEL 3030 .ndo_rx_flow_steer = hns3_rx_flow_steer, 3031 #endif 3032 .ndo_get_vf_config = hns3_nic_get_vf_config, 3033 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state, 3034 .ndo_set_vf_rate = hns3_nic_set_vf_rate, 3035 .ndo_set_vf_mac = hns3_nic_set_vf_mac, 3036 .ndo_select_queue = hns3_nic_select_queue, 3037 }; 3038 3039 bool hns3_is_phys_func(struct pci_dev *pdev) 3040 { 3041 u32 dev_id = pdev->device; 3042 3043 switch (dev_id) { 3044 case HNAE3_DEV_ID_GE: 3045 case HNAE3_DEV_ID_25GE: 3046 case HNAE3_DEV_ID_25GE_RDMA: 3047 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 3048 case HNAE3_DEV_ID_50GE_RDMA: 3049 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 3050 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 3051 case HNAE3_DEV_ID_200G_RDMA: 3052 return true; 3053 case HNAE3_DEV_ID_VF: 3054 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF: 3055 return false; 3056 default: 3057 dev_warn(&pdev->dev, "un-recognized pci device-id %u", 3058 dev_id); 3059 } 3060 3061 return false; 3062 } 3063 3064 static void hns3_disable_sriov(struct pci_dev *pdev) 3065 { 3066 /* If our VFs are assigned we cannot shut down SR-IOV 3067 * without causing issues, so just leave the hardware 3068 * available but disabled 3069 */ 3070 if (pci_vfs_assigned(pdev)) { 3071 dev_warn(&pdev->dev, 3072 "disabling driver while VFs are assigned\n"); 3073 return; 3074 } 3075 3076 pci_disable_sriov(pdev); 3077 } 3078 3079 /* hns3_probe - Device initialization routine 3080 * @pdev: PCI device information struct 3081 * @ent: entry in hns3_pci_tbl 3082 * 3083 * hns3_probe initializes a PF identified by a pci_dev structure. 3084 * The OS initialization, configuring of the PF private structure, 3085 * and a hardware reset occur. 3086 * 3087 * Returns 0 on success, negative on failure 3088 */ 3089 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3090 { 3091 struct hnae3_ae_dev *ae_dev; 3092 int ret; 3093 3094 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL); 3095 if (!ae_dev) 3096 return -ENOMEM; 3097 3098 ae_dev->pdev = pdev; 3099 ae_dev->flag = ent->driver_data; 3100 pci_set_drvdata(pdev, ae_dev); 3101 3102 ret = hnae3_register_ae_dev(ae_dev); 3103 if (ret) 3104 pci_set_drvdata(pdev, NULL); 3105 3106 return ret; 3107 } 3108 3109 /** 3110 * hns3_clean_vf_config 3111 * @pdev: pointer to a pci_dev structure 3112 * @num_vfs: number of VFs allocated 3113 * 3114 * Clean residual vf config after disable sriov 3115 **/ 3116 static void hns3_clean_vf_config(struct pci_dev *pdev, int num_vfs) 3117 { 3118 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3119 3120 if (ae_dev->ops->clean_vf_config) 3121 ae_dev->ops->clean_vf_config(ae_dev, num_vfs); 3122 } 3123 3124 /* hns3_remove - Device removal routine 3125 * @pdev: PCI device information struct 3126 */ 3127 static void hns3_remove(struct pci_dev *pdev) 3128 { 3129 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3130 3131 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 3132 hns3_disable_sriov(pdev); 3133 3134 hnae3_unregister_ae_dev(ae_dev); 3135 pci_set_drvdata(pdev, NULL); 3136 } 3137 3138 /** 3139 * hns3_pci_sriov_configure 3140 * @pdev: pointer to a pci_dev structure 3141 * @num_vfs: number of VFs to allocate 3142 * 3143 * Enable or change the number of VFs. Called when the user updates the number 3144 * of VFs in sysfs. 3145 **/ 3146 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 3147 { 3148 int ret; 3149 3150 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 3151 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 3152 return -EINVAL; 3153 } 3154 3155 if (num_vfs) { 3156 ret = pci_enable_sriov(pdev, num_vfs); 3157 if (ret) 3158 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 3159 else 3160 return num_vfs; 3161 } else if (!pci_vfs_assigned(pdev)) { 3162 int num_vfs_pre = pci_num_vf(pdev); 3163 3164 pci_disable_sriov(pdev); 3165 hns3_clean_vf_config(pdev, num_vfs_pre); 3166 } else { 3167 dev_warn(&pdev->dev, 3168 "Unable to free VFs because some are assigned to VMs.\n"); 3169 } 3170 3171 return 0; 3172 } 3173 3174 static void hns3_shutdown(struct pci_dev *pdev) 3175 { 3176 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3177 3178 hnae3_unregister_ae_dev(ae_dev); 3179 pci_set_drvdata(pdev, NULL); 3180 3181 if (system_state == SYSTEM_POWER_OFF) 3182 pci_set_power_state(pdev, PCI_D3hot); 3183 } 3184 3185 static int __maybe_unused hns3_suspend(struct device *dev) 3186 { 3187 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev); 3188 3189 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) { 3190 dev_info(dev, "Begin to suspend.\n"); 3191 if (ae_dev->ops && ae_dev->ops->reset_prepare) 3192 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET); 3193 } 3194 3195 return 0; 3196 } 3197 3198 static int __maybe_unused hns3_resume(struct device *dev) 3199 { 3200 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev); 3201 3202 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) { 3203 dev_info(dev, "Begin to resume.\n"); 3204 if (ae_dev->ops && ae_dev->ops->reset_done) 3205 ae_dev->ops->reset_done(ae_dev); 3206 } 3207 3208 return 0; 3209 } 3210 3211 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 3212 pci_channel_state_t state) 3213 { 3214 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3215 pci_ers_result_t ret; 3216 3217 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state); 3218 3219 if (state == pci_channel_io_perm_failure) 3220 return PCI_ERS_RESULT_DISCONNECT; 3221 3222 if (!ae_dev || !ae_dev->ops) { 3223 dev_err(&pdev->dev, 3224 "Can't recover - error happened before device initialized\n"); 3225 return PCI_ERS_RESULT_NONE; 3226 } 3227 3228 if (ae_dev->ops->handle_hw_ras_error) 3229 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 3230 else 3231 return PCI_ERS_RESULT_NONE; 3232 3233 return ret; 3234 } 3235 3236 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 3237 { 3238 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3239 const struct hnae3_ae_ops *ops; 3240 enum hnae3_reset_type reset_type; 3241 struct device *dev = &pdev->dev; 3242 3243 if (!ae_dev || !ae_dev->ops) 3244 return PCI_ERS_RESULT_NONE; 3245 3246 ops = ae_dev->ops; 3247 /* request the reset */ 3248 if (ops->reset_event && ops->get_reset_level && 3249 ops->set_default_reset_request) { 3250 if (ae_dev->hw_err_reset_req) { 3251 reset_type = ops->get_reset_level(ae_dev, 3252 &ae_dev->hw_err_reset_req); 3253 ops->set_default_reset_request(ae_dev, reset_type); 3254 dev_info(dev, "requesting reset due to PCI error\n"); 3255 ops->reset_event(pdev, NULL); 3256 } 3257 3258 return PCI_ERS_RESULT_RECOVERED; 3259 } 3260 3261 return PCI_ERS_RESULT_DISCONNECT; 3262 } 3263 3264 static void hns3_reset_prepare(struct pci_dev *pdev) 3265 { 3266 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3267 3268 dev_info(&pdev->dev, "FLR prepare\n"); 3269 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare) 3270 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET); 3271 } 3272 3273 static void hns3_reset_done(struct pci_dev *pdev) 3274 { 3275 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3276 3277 dev_info(&pdev->dev, "FLR done\n"); 3278 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done) 3279 ae_dev->ops->reset_done(ae_dev); 3280 } 3281 3282 static const struct pci_error_handlers hns3_err_handler = { 3283 .error_detected = hns3_error_detected, 3284 .slot_reset = hns3_slot_reset, 3285 .reset_prepare = hns3_reset_prepare, 3286 .reset_done = hns3_reset_done, 3287 }; 3288 3289 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume); 3290 3291 static struct pci_driver hns3_driver = { 3292 .name = hns3_driver_name, 3293 .id_table = hns3_pci_tbl, 3294 .probe = hns3_probe, 3295 .remove = hns3_remove, 3296 .shutdown = hns3_shutdown, 3297 .driver.pm = &hns3_pm_ops, 3298 .sriov_configure = hns3_pci_sriov_configure, 3299 .err_handler = &hns3_err_handler, 3300 }; 3301 3302 /* set default feature to hns3 */ 3303 static void hns3_set_default_feature(struct net_device *netdev) 3304 { 3305 struct hnae3_handle *h = hns3_get_handle(netdev); 3306 struct pci_dev *pdev = h->pdev; 3307 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3308 3309 netdev->priv_flags |= IFF_UNICAST_FLT; 3310 3311 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 3312 3313 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3314 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 3315 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 3316 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 3317 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 3318 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 3319 3320 if (hnae3_ae_dev_gro_supported(ae_dev)) 3321 netdev->features |= NETIF_F_GRO_HW; 3322 3323 if (hnae3_ae_dev_fd_supported(ae_dev)) 3324 netdev->features |= NETIF_F_NTUPLE; 3325 3326 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps)) 3327 netdev->features |= NETIF_F_GSO_UDP_L4; 3328 3329 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) 3330 netdev->features |= NETIF_F_HW_CSUM; 3331 else 3332 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 3333 3334 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps)) 3335 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 3336 3337 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) 3338 netdev->features |= NETIF_F_HW_TC; 3339 3340 netdev->hw_features |= netdev->features; 3341 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 3342 netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 3343 3344 netdev->vlan_features |= netdev->features & 3345 ~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX | 3346 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE | 3347 NETIF_F_HW_TC); 3348 3349 netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID; 3350 } 3351 3352 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 3353 struct hns3_desc_cb *cb) 3354 { 3355 unsigned int order = hns3_page_order(ring); 3356 struct page *p; 3357 3358 if (ring->page_pool) { 3359 p = page_pool_dev_alloc_frag(ring->page_pool, 3360 &cb->page_offset, 3361 hns3_buf_size(ring)); 3362 if (unlikely(!p)) 3363 return -ENOMEM; 3364 3365 cb->priv = p; 3366 cb->buf = page_address(p); 3367 cb->dma = page_pool_get_dma_addr(p); 3368 cb->type = DESC_TYPE_PP_FRAG; 3369 cb->reuse_flag = 0; 3370 return 0; 3371 } 3372 3373 p = dev_alloc_pages(order); 3374 if (!p) 3375 return -ENOMEM; 3376 3377 cb->priv = p; 3378 cb->page_offset = 0; 3379 cb->reuse_flag = 0; 3380 cb->buf = page_address(p); 3381 cb->length = hns3_page_size(ring); 3382 cb->type = DESC_TYPE_PAGE; 3383 page_ref_add(p, USHRT_MAX - 1); 3384 cb->pagecnt_bias = USHRT_MAX; 3385 3386 return 0; 3387 } 3388 3389 static void hns3_free_buffer(struct hns3_enet_ring *ring, 3390 struct hns3_desc_cb *cb, int budget) 3391 { 3392 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD | 3393 DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB)) 3394 napi_consume_skb(cb->priv, budget); 3395 else if (!HNAE3_IS_TX_RING(ring)) { 3396 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias) 3397 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias); 3398 else if (cb->type & DESC_TYPE_PP_FRAG) 3399 page_pool_put_full_page(ring->page_pool, cb->priv, 3400 false); 3401 } 3402 memset(cb, 0, sizeof(*cb)); 3403 } 3404 3405 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 3406 { 3407 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 3408 cb->length, ring_to_dma_dir(ring)); 3409 3410 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 3411 return -EIO; 3412 3413 return 0; 3414 } 3415 3416 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 3417 struct hns3_desc_cb *cb) 3418 { 3419 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB)) 3420 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 3421 ring_to_dma_dir(ring)); 3422 else if ((cb->type & DESC_TYPE_PAGE) && cb->length) 3423 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 3424 ring_to_dma_dir(ring)); 3425 else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD | 3426 DESC_TYPE_SGL_SKB)) 3427 hns3_tx_spare_reclaim_cb(ring, cb); 3428 } 3429 3430 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 3431 { 3432 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 3433 ring->desc[i].addr = 0; 3434 ring->desc_cb[i].refill = 0; 3435 } 3436 3437 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i, 3438 int budget) 3439 { 3440 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 3441 3442 if (!ring->desc_cb[i].dma) 3443 return; 3444 3445 hns3_buffer_detach(ring, i); 3446 hns3_free_buffer(ring, cb, budget); 3447 } 3448 3449 static void hns3_free_buffers(struct hns3_enet_ring *ring) 3450 { 3451 int i; 3452 3453 for (i = 0; i < ring->desc_num; i++) 3454 hns3_free_buffer_detach(ring, i, 0); 3455 } 3456 3457 /* free desc along with its attached buffer */ 3458 static void hns3_free_desc(struct hns3_enet_ring *ring) 3459 { 3460 int size = ring->desc_num * sizeof(ring->desc[0]); 3461 3462 hns3_free_buffers(ring); 3463 3464 if (ring->desc) { 3465 dma_free_coherent(ring_to_dev(ring), size, 3466 ring->desc, ring->desc_dma_addr); 3467 ring->desc = NULL; 3468 } 3469 } 3470 3471 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 3472 { 3473 int size = ring->desc_num * sizeof(ring->desc[0]); 3474 3475 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 3476 &ring->desc_dma_addr, GFP_KERNEL); 3477 if (!ring->desc) 3478 return -ENOMEM; 3479 3480 return 0; 3481 } 3482 3483 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring, 3484 struct hns3_desc_cb *cb) 3485 { 3486 int ret; 3487 3488 ret = hns3_alloc_buffer(ring, cb); 3489 if (ret || ring->page_pool) 3490 goto out; 3491 3492 ret = hns3_map_buffer(ring, cb); 3493 if (ret) 3494 goto out_with_buf; 3495 3496 return 0; 3497 3498 out_with_buf: 3499 hns3_free_buffer(ring, cb, 0); 3500 out: 3501 return ret; 3502 } 3503 3504 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i) 3505 { 3506 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]); 3507 3508 if (ret) 3509 return ret; 3510 3511 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 3512 ring->desc_cb[i].page_offset); 3513 ring->desc_cb[i].refill = 1; 3514 3515 return 0; 3516 } 3517 3518 /* Allocate memory for raw pkg, and map with dma */ 3519 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 3520 { 3521 int i, j, ret; 3522 3523 for (i = 0; i < ring->desc_num; i++) { 3524 ret = hns3_alloc_and_attach_buffer(ring, i); 3525 if (ret) 3526 goto out_buffer_fail; 3527 } 3528 3529 return 0; 3530 3531 out_buffer_fail: 3532 for (j = i - 1; j >= 0; j--) 3533 hns3_free_buffer_detach(ring, j, 0); 3534 return ret; 3535 } 3536 3537 /* detach a in-used buffer and replace with a reserved one */ 3538 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 3539 struct hns3_desc_cb *res_cb) 3540 { 3541 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 3542 ring->desc_cb[i] = *res_cb; 3543 ring->desc_cb[i].refill = 1; 3544 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 3545 ring->desc_cb[i].page_offset); 3546 ring->desc[i].rx.bd_base_info = 0; 3547 } 3548 3549 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 3550 { 3551 ring->desc_cb[i].reuse_flag = 0; 3552 ring->desc_cb[i].refill = 1; 3553 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 3554 ring->desc_cb[i].page_offset); 3555 ring->desc[i].rx.bd_base_info = 0; 3556 3557 dma_sync_single_for_device(ring_to_dev(ring), 3558 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset, 3559 hns3_buf_size(ring), 3560 DMA_FROM_DEVICE); 3561 } 3562 3563 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, 3564 int *bytes, int *pkts, int budget) 3565 { 3566 /* pair with ring->last_to_use update in hns3_tx_doorbell(), 3567 * smp_store_release() is not used in hns3_tx_doorbell() because 3568 * the doorbell operation already have the needed barrier operation. 3569 */ 3570 int ltu = smp_load_acquire(&ring->last_to_use); 3571 int ntc = ring->next_to_clean; 3572 struct hns3_desc_cb *desc_cb; 3573 bool reclaimed = false; 3574 struct hns3_desc *desc; 3575 3576 while (ltu != ntc) { 3577 desc = &ring->desc[ntc]; 3578 3579 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) & 3580 BIT(HNS3_TXD_VLD_B)) 3581 break; 3582 3583 desc_cb = &ring->desc_cb[ntc]; 3584 3585 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL | 3586 DESC_TYPE_BOUNCE_HEAD | 3587 DESC_TYPE_SGL_SKB)) { 3588 (*pkts)++; 3589 (*bytes) += desc_cb->send_bytes; 3590 } 3591 3592 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */ 3593 hns3_free_buffer_detach(ring, ntc, budget); 3594 3595 if (++ntc == ring->desc_num) 3596 ntc = 0; 3597 3598 /* Issue prefetch for next Tx descriptor */ 3599 prefetch(&ring->desc_cb[ntc]); 3600 reclaimed = true; 3601 } 3602 3603 if (unlikely(!reclaimed)) 3604 return false; 3605 3606 /* This smp_store_release() pairs with smp_load_acquire() in 3607 * ring_space called by hns3_nic_net_xmit. 3608 */ 3609 smp_store_release(&ring->next_to_clean, ntc); 3610 3611 hns3_tx_spare_update(ring); 3612 3613 return true; 3614 } 3615 3616 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget) 3617 { 3618 struct net_device *netdev = ring_to_netdev(ring); 3619 struct hns3_nic_priv *priv = netdev_priv(netdev); 3620 struct netdev_queue *dev_queue; 3621 int bytes, pkts; 3622 3623 bytes = 0; 3624 pkts = 0; 3625 3626 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget))) 3627 return; 3628 3629 ring->tqp_vector->tx_group.total_bytes += bytes; 3630 ring->tqp_vector->tx_group.total_packets += pkts; 3631 3632 u64_stats_update_begin(&ring->syncp); 3633 ring->stats.tx_bytes += bytes; 3634 ring->stats.tx_pkts += pkts; 3635 u64_stats_update_end(&ring->syncp); 3636 3637 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 3638 netdev_tx_completed_queue(dev_queue, pkts, bytes); 3639 3640 if (unlikely(netif_carrier_ok(netdev) && 3641 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) { 3642 /* Make sure that anybody stopping the queue after this 3643 * sees the new next_to_clean. 3644 */ 3645 smp_mb(); 3646 if (netif_tx_queue_stopped(dev_queue) && 3647 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 3648 netif_tx_wake_queue(dev_queue); 3649 ring->stats.restart_queue++; 3650 } 3651 } 3652 } 3653 3654 static int hns3_desc_unused(struct hns3_enet_ring *ring) 3655 { 3656 int ntc = ring->next_to_clean; 3657 int ntu = ring->next_to_use; 3658 3659 if (unlikely(ntc == ntu && !ring->desc_cb[ntc].refill)) 3660 return ring->desc_num; 3661 3662 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 3663 } 3664 3665 /* Return true if there is any allocation failure */ 3666 static bool hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, 3667 int cleand_count) 3668 { 3669 struct hns3_desc_cb *desc_cb; 3670 struct hns3_desc_cb res_cbs; 3671 int i, ret; 3672 3673 for (i = 0; i < cleand_count; i++) { 3674 desc_cb = &ring->desc_cb[ring->next_to_use]; 3675 if (desc_cb->reuse_flag) { 3676 hns3_ring_stats_update(ring, reuse_pg_cnt); 3677 3678 hns3_reuse_buffer(ring, ring->next_to_use); 3679 } else { 3680 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 3681 if (ret) { 3682 hns3_ring_stats_update(ring, sw_err_cnt); 3683 3684 hns3_rl_err(ring_to_netdev(ring), 3685 "alloc rx buffer failed: %d\n", 3686 ret); 3687 3688 writel(i, ring->tqp->io_base + 3689 HNS3_RING_RX_RING_HEAD_REG); 3690 return true; 3691 } 3692 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 3693 3694 hns3_ring_stats_update(ring, non_reuse_pg); 3695 } 3696 3697 ring_ptr_move_fw(ring, next_to_use); 3698 } 3699 3700 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 3701 return false; 3702 } 3703 3704 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb) 3705 { 3706 return page_count(cb->priv) == cb->pagecnt_bias; 3707 } 3708 3709 static int hns3_handle_rx_copybreak(struct sk_buff *skb, int i, 3710 struct hns3_enet_ring *ring, 3711 int pull_len, 3712 struct hns3_desc_cb *desc_cb) 3713 { 3714 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 3715 u32 frag_offset = desc_cb->page_offset + pull_len; 3716 int size = le16_to_cpu(desc->rx.size); 3717 u32 frag_size = size - pull_len; 3718 void *frag = napi_alloc_frag(frag_size); 3719 3720 if (unlikely(!frag)) { 3721 hns3_ring_stats_update(ring, frag_alloc_err); 3722 3723 hns3_rl_err(ring_to_netdev(ring), 3724 "failed to allocate rx frag\n"); 3725 return -ENOMEM; 3726 } 3727 3728 desc_cb->reuse_flag = 1; 3729 memcpy(frag, desc_cb->buf + frag_offset, frag_size); 3730 skb_add_rx_frag(skb, i, virt_to_page(frag), 3731 offset_in_page(frag), frag_size, frag_size); 3732 3733 hns3_ring_stats_update(ring, frag_alloc); 3734 return 0; 3735 } 3736 3737 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 3738 struct hns3_enet_ring *ring, int pull_len, 3739 struct hns3_desc_cb *desc_cb) 3740 { 3741 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 3742 u32 frag_offset = desc_cb->page_offset + pull_len; 3743 int size = le16_to_cpu(desc->rx.size); 3744 u32 truesize = hns3_buf_size(ring); 3745 u32 frag_size = size - pull_len; 3746 int ret = 0; 3747 bool reused; 3748 3749 if (ring->page_pool) { 3750 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset, 3751 frag_size, truesize); 3752 return; 3753 } 3754 3755 /* Avoid re-using remote or pfmem page */ 3756 if (unlikely(!dev_page_is_reusable(desc_cb->priv))) 3757 goto out; 3758 3759 reused = hns3_can_reuse_page(desc_cb); 3760 3761 /* Rx page can be reused when: 3762 * 1. Rx page is only owned by the driver when page_offset 3763 * is zero, which means 0 @ truesize will be used by 3764 * stack after skb_add_rx_frag() is called, and the rest 3765 * of rx page can be reused by driver. 3766 * Or 3767 * 2. Rx page is only owned by the driver when page_offset 3768 * is non-zero, which means page_offset @ truesize will 3769 * be used by stack after skb_add_rx_frag() is called, 3770 * and 0 @ truesize can be reused by driver. 3771 */ 3772 if ((!desc_cb->page_offset && reused) || 3773 ((desc_cb->page_offset + truesize + truesize) <= 3774 hns3_page_size(ring) && desc_cb->page_offset)) { 3775 desc_cb->page_offset += truesize; 3776 desc_cb->reuse_flag = 1; 3777 } else if (desc_cb->page_offset && reused) { 3778 desc_cb->page_offset = 0; 3779 desc_cb->reuse_flag = 1; 3780 } else if (frag_size <= ring->rx_copybreak) { 3781 ret = hns3_handle_rx_copybreak(skb, i, ring, pull_len, desc_cb); 3782 if (!ret) 3783 return; 3784 } 3785 3786 out: 3787 desc_cb->pagecnt_bias--; 3788 3789 if (unlikely(!desc_cb->pagecnt_bias)) { 3790 page_ref_add(desc_cb->priv, USHRT_MAX); 3791 desc_cb->pagecnt_bias = USHRT_MAX; 3792 } 3793 3794 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset, 3795 frag_size, truesize); 3796 3797 if (unlikely(!desc_cb->reuse_flag)) 3798 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias); 3799 } 3800 3801 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) 3802 { 3803 __be16 type = skb->protocol; 3804 struct tcphdr *th; 3805 int depth = 0; 3806 3807 while (eth_type_vlan(type)) { 3808 struct vlan_hdr *vh; 3809 3810 if ((depth + VLAN_HLEN) > skb_headlen(skb)) 3811 return -EFAULT; 3812 3813 vh = (struct vlan_hdr *)(skb->data + depth); 3814 type = vh->h_vlan_encapsulated_proto; 3815 depth += VLAN_HLEN; 3816 } 3817 3818 skb_set_network_header(skb, depth); 3819 3820 if (type == htons(ETH_P_IP)) { 3821 const struct iphdr *iph = ip_hdr(skb); 3822 3823 depth += sizeof(struct iphdr); 3824 skb_set_transport_header(skb, depth); 3825 th = tcp_hdr(skb); 3826 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr, 3827 iph->daddr, 0); 3828 } else if (type == htons(ETH_P_IPV6)) { 3829 const struct ipv6hdr *iph = ipv6_hdr(skb); 3830 3831 depth += sizeof(struct ipv6hdr); 3832 skb_set_transport_header(skb, depth); 3833 th = tcp_hdr(skb); 3834 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr, 3835 &iph->daddr, 0); 3836 } else { 3837 hns3_rl_err(skb->dev, 3838 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n", 3839 be16_to_cpu(type), depth); 3840 return -EFAULT; 3841 } 3842 3843 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 3844 if (th->cwr) 3845 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 3846 3847 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B)) 3848 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID; 3849 3850 skb->csum_start = (unsigned char *)th - skb->head; 3851 skb->csum_offset = offsetof(struct tcphdr, check); 3852 skb->ip_summed = CHECKSUM_PARTIAL; 3853 3854 trace_hns3_gro(skb); 3855 3856 return 0; 3857 } 3858 3859 static void hns3_checksum_complete(struct hns3_enet_ring *ring, 3860 struct sk_buff *skb, u32 ptype, u16 csum) 3861 { 3862 if (ptype == HNS3_INVALID_PTYPE || 3863 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE) 3864 return; 3865 3866 hns3_ring_stats_update(ring, csum_complete); 3867 skb->ip_summed = CHECKSUM_COMPLETE; 3868 skb->csum = csum_unfold((__force __sum16)csum); 3869 } 3870 3871 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info, 3872 u32 ol_info, u32 ptype) 3873 { 3874 int l3_type, l4_type; 3875 int ol4_type; 3876 3877 if (ptype != HNS3_INVALID_PTYPE) { 3878 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level; 3879 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed; 3880 3881 return; 3882 } 3883 3884 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M, 3885 HNS3_RXD_OL4ID_S); 3886 switch (ol4_type) { 3887 case HNS3_OL4_TYPE_MAC_IN_UDP: 3888 case HNS3_OL4_TYPE_NVGRE: 3889 skb->csum_level = 1; 3890 fallthrough; 3891 case HNS3_OL4_TYPE_NO_TUN: 3892 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 3893 HNS3_RXD_L3ID_S); 3894 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 3895 HNS3_RXD_L4ID_S); 3896 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 3897 if ((l3_type == HNS3_L3_TYPE_IPV4 || 3898 l3_type == HNS3_L3_TYPE_IPV6) && 3899 (l4_type == HNS3_L4_TYPE_UDP || 3900 l4_type == HNS3_L4_TYPE_TCP || 3901 l4_type == HNS3_L4_TYPE_SCTP)) 3902 skb->ip_summed = CHECKSUM_UNNECESSARY; 3903 break; 3904 default: 3905 break; 3906 } 3907 } 3908 3909 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 3910 u32 l234info, u32 bd_base_info, u32 ol_info, 3911 u16 csum) 3912 { 3913 struct net_device *netdev = ring_to_netdev(ring); 3914 struct hns3_nic_priv *priv = netdev_priv(netdev); 3915 u32 ptype = HNS3_INVALID_PTYPE; 3916 3917 skb->ip_summed = CHECKSUM_NONE; 3918 3919 skb_checksum_none_assert(skb); 3920 3921 if (!(netdev->features & NETIF_F_RXCSUM)) 3922 return; 3923 3924 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) 3925 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, 3926 HNS3_RXD_PTYPE_S); 3927 3928 hns3_checksum_complete(ring, skb, ptype, csum); 3929 3930 /* check if hardware has done checksum */ 3931 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 3932 return; 3933 3934 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | 3935 BIT(HNS3_RXD_OL3E_B) | 3936 BIT(HNS3_RXD_OL4E_B)))) { 3937 skb->ip_summed = CHECKSUM_NONE; 3938 hns3_ring_stats_update(ring, l3l4_csum_err); 3939 3940 return; 3941 } 3942 3943 hns3_rx_handle_csum(skb, l234info, ol_info, ptype); 3944 } 3945 3946 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 3947 { 3948 if (skb_has_frag_list(skb)) 3949 napi_gro_flush(&ring->tqp_vector->napi, false); 3950 3951 napi_gro_receive(&ring->tqp_vector->napi, skb); 3952 } 3953 3954 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 3955 struct hns3_desc *desc, u32 l234info, 3956 u16 *vlan_tag) 3957 { 3958 struct hnae3_handle *handle = ring->tqp->handle; 3959 struct pci_dev *pdev = ring->tqp->handle->pdev; 3960 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3961 3962 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) { 3963 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3964 if (!(*vlan_tag & VLAN_VID_MASK)) 3965 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3966 3967 return (*vlan_tag != 0); 3968 } 3969 3970 #define HNS3_STRP_OUTER_VLAN 0x1 3971 #define HNS3_STRP_INNER_VLAN 0x2 3972 #define HNS3_STRP_BOTH 0x3 3973 3974 /* Hardware always insert VLAN tag into RX descriptor when 3975 * remove the tag from packet, driver needs to determine 3976 * reporting which tag to stack. 3977 */ 3978 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 3979 HNS3_RXD_STRP_TAGP_S)) { 3980 case HNS3_STRP_OUTER_VLAN: 3981 if (handle->port_base_vlan_state != 3982 HNAE3_PORT_BASE_VLAN_DISABLE) 3983 return false; 3984 3985 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3986 return true; 3987 case HNS3_STRP_INNER_VLAN: 3988 if (handle->port_base_vlan_state != 3989 HNAE3_PORT_BASE_VLAN_DISABLE) 3990 return false; 3991 3992 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3993 return true; 3994 case HNS3_STRP_BOTH: 3995 if (handle->port_base_vlan_state == 3996 HNAE3_PORT_BASE_VLAN_DISABLE) 3997 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3998 else 3999 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 4000 4001 return true; 4002 default: 4003 return false; 4004 } 4005 } 4006 4007 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring) 4008 { 4009 ring->desc[ring->next_to_clean].rx.bd_base_info &= 4010 cpu_to_le32(~BIT(HNS3_RXD_VLD_B)); 4011 ring->desc_cb[ring->next_to_clean].refill = 0; 4012 ring->next_to_clean += 1; 4013 4014 if (unlikely(ring->next_to_clean == ring->desc_num)) 4015 ring->next_to_clean = 0; 4016 } 4017 4018 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length, 4019 unsigned char *va) 4020 { 4021 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 4022 struct net_device *netdev = ring_to_netdev(ring); 4023 struct sk_buff *skb; 4024 4025 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 4026 skb = ring->skb; 4027 if (unlikely(!skb)) { 4028 hns3_rl_err(netdev, "alloc rx skb fail\n"); 4029 hns3_ring_stats_update(ring, sw_err_cnt); 4030 4031 return -ENOMEM; 4032 } 4033 4034 trace_hns3_rx_desc(ring); 4035 prefetchw(skb->data); 4036 4037 ring->pending_buf = 1; 4038 ring->frag_num = 0; 4039 ring->tail_skb = NULL; 4040 if (length <= HNS3_RX_HEAD_SIZE) { 4041 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 4042 4043 /* We can reuse buffer as-is, just make sure it is reusable */ 4044 if (dev_page_is_reusable(desc_cb->priv)) 4045 desc_cb->reuse_flag = 1; 4046 else if (desc_cb->type & DESC_TYPE_PP_FRAG) 4047 page_pool_put_full_page(ring->page_pool, desc_cb->priv, 4048 false); 4049 else /* This page cannot be reused so discard it */ 4050 __page_frag_cache_drain(desc_cb->priv, 4051 desc_cb->pagecnt_bias); 4052 4053 hns3_rx_ring_move_fw(ring); 4054 return 0; 4055 } 4056 4057 if (ring->page_pool) 4058 skb_mark_for_recycle(skb); 4059 4060 hns3_ring_stats_update(ring, seg_pkt_cnt); 4061 4062 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE); 4063 __skb_put(skb, ring->pull_len); 4064 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 4065 desc_cb); 4066 hns3_rx_ring_move_fw(ring); 4067 4068 return 0; 4069 } 4070 4071 static int hns3_add_frag(struct hns3_enet_ring *ring) 4072 { 4073 struct sk_buff *skb = ring->skb; 4074 struct sk_buff *head_skb = skb; 4075 struct sk_buff *new_skb; 4076 struct hns3_desc_cb *desc_cb; 4077 struct hns3_desc *desc; 4078 u32 bd_base_info; 4079 4080 do { 4081 desc = &ring->desc[ring->next_to_clean]; 4082 desc_cb = &ring->desc_cb[ring->next_to_clean]; 4083 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 4084 /* make sure HW write desc complete */ 4085 dma_rmb(); 4086 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 4087 return -ENXIO; 4088 4089 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 4090 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0); 4091 if (unlikely(!new_skb)) { 4092 hns3_rl_err(ring_to_netdev(ring), 4093 "alloc rx fraglist skb fail\n"); 4094 return -ENXIO; 4095 } 4096 4097 if (ring->page_pool) 4098 skb_mark_for_recycle(new_skb); 4099 4100 ring->frag_num = 0; 4101 4102 if (ring->tail_skb) { 4103 ring->tail_skb->next = new_skb; 4104 ring->tail_skb = new_skb; 4105 } else { 4106 skb_shinfo(skb)->frag_list = new_skb; 4107 ring->tail_skb = new_skb; 4108 } 4109 } 4110 4111 if (ring->tail_skb) { 4112 head_skb->truesize += hns3_buf_size(ring); 4113 head_skb->data_len += le16_to_cpu(desc->rx.size); 4114 head_skb->len += le16_to_cpu(desc->rx.size); 4115 skb = ring->tail_skb; 4116 } 4117 4118 dma_sync_single_for_cpu(ring_to_dev(ring), 4119 desc_cb->dma + desc_cb->page_offset, 4120 hns3_buf_size(ring), 4121 DMA_FROM_DEVICE); 4122 4123 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 4124 trace_hns3_rx_desc(ring); 4125 hns3_rx_ring_move_fw(ring); 4126 ring->pending_buf++; 4127 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B))); 4128 4129 return 0; 4130 } 4131 4132 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring, 4133 struct sk_buff *skb, u32 l234info, 4134 u32 bd_base_info, u32 ol_info, u16 csum) 4135 { 4136 struct net_device *netdev = ring_to_netdev(ring); 4137 struct hns3_nic_priv *priv = netdev_priv(netdev); 4138 u32 l3_type; 4139 4140 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 4141 HNS3_RXD_GRO_SIZE_M, 4142 HNS3_RXD_GRO_SIZE_S); 4143 /* if there is no HW GRO, do not set gro params */ 4144 if (!skb_shinfo(skb)->gso_size) { 4145 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info, 4146 csum); 4147 return 0; 4148 } 4149 4150 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info, 4151 HNS3_RXD_GRO_COUNT_M, 4152 HNS3_RXD_GRO_COUNT_S); 4153 4154 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) { 4155 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, 4156 HNS3_RXD_PTYPE_S); 4157 4158 l3_type = hns3_rx_ptype_tbl[ptype].l3_type; 4159 } else { 4160 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 4161 HNS3_RXD_L3ID_S); 4162 } 4163 4164 if (l3_type == HNS3_L3_TYPE_IPV4) 4165 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 4166 else if (l3_type == HNS3_L3_TYPE_IPV6) 4167 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 4168 else 4169 return -EFAULT; 4170 4171 return hns3_gro_complete(skb, l234info); 4172 } 4173 4174 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 4175 struct sk_buff *skb, u32 rss_hash, 4176 u32 l234info, u32 ol_info) 4177 { 4178 enum pkt_hash_types rss_type = PKT_HASH_TYPE_NONE; 4179 struct net_device *netdev = ring_to_netdev(ring); 4180 struct hns3_nic_priv *priv = netdev_priv(netdev); 4181 4182 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) { 4183 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, 4184 HNS3_RXD_PTYPE_S); 4185 4186 rss_type = hns3_rx_ptype_tbl[ptype].hash_type; 4187 } else { 4188 int l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 4189 HNS3_RXD_L3ID_S); 4190 int l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 4191 HNS3_RXD_L4ID_S); 4192 4193 if (l3_type == HNS3_L3_TYPE_IPV4 || 4194 l3_type == HNS3_L3_TYPE_IPV6) { 4195 if (l4_type == HNS3_L4_TYPE_UDP || 4196 l4_type == HNS3_L4_TYPE_TCP || 4197 l4_type == HNS3_L4_TYPE_SCTP) 4198 rss_type = PKT_HASH_TYPE_L4; 4199 else if (l4_type == HNS3_L4_TYPE_IGMP || 4200 l4_type == HNS3_L4_TYPE_ICMP) 4201 rss_type = PKT_HASH_TYPE_L3; 4202 } 4203 } 4204 4205 skb_set_hash(skb, rss_hash, rss_type); 4206 } 4207 4208 static void hns3_handle_rx_ts_info(struct net_device *netdev, 4209 struct hns3_desc *desc, struct sk_buff *skb, 4210 u32 bd_base_info) 4211 { 4212 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) { 4213 struct hnae3_handle *h = hns3_get_handle(netdev); 4214 u32 nsec = le32_to_cpu(desc->ts_nsec); 4215 u32 sec = le32_to_cpu(desc->ts_sec); 4216 4217 if (h->ae_algo->ops->get_rx_hwts) 4218 h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec); 4219 } 4220 } 4221 4222 static void hns3_handle_rx_vlan_tag(struct hns3_enet_ring *ring, 4223 struct hns3_desc *desc, struct sk_buff *skb, 4224 u32 l234info) 4225 { 4226 struct net_device *netdev = ring_to_netdev(ring); 4227 4228 /* Based on hw strategy, the tag offloaded will be stored at 4229 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 4230 * in one layer tag case. 4231 */ 4232 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 4233 u16 vlan_tag; 4234 4235 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 4236 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 4237 vlan_tag); 4238 } 4239 } 4240 4241 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb) 4242 { 4243 struct net_device *netdev = ring_to_netdev(ring); 4244 enum hns3_pkt_l2t_type l2_frame_type; 4245 u32 bd_base_info, l234info, ol_info; 4246 struct hns3_desc *desc; 4247 unsigned int len; 4248 int pre_ntc, ret; 4249 u16 csum; 4250 4251 /* bdinfo handled below is only valid on the last BD of the 4252 * current packet, and ring->next_to_clean indicates the first 4253 * descriptor of next packet, so need - 1 below. 4254 */ 4255 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) : 4256 (ring->desc_num - 1); 4257 desc = &ring->desc[pre_ntc]; 4258 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 4259 l234info = le32_to_cpu(desc->rx.l234_info); 4260 ol_info = le32_to_cpu(desc->rx.ol_info); 4261 csum = le16_to_cpu(desc->csum); 4262 4263 hns3_handle_rx_ts_info(netdev, desc, skb, bd_base_info); 4264 4265 hns3_handle_rx_vlan_tag(ring, desc, skb, l234info); 4266 4267 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 4268 BIT(HNS3_RXD_L2E_B))))) { 4269 u64_stats_update_begin(&ring->syncp); 4270 if (l234info & BIT(HNS3_RXD_L2E_B)) 4271 ring->stats.l2_err++; 4272 else 4273 ring->stats.err_pkt_len++; 4274 u64_stats_update_end(&ring->syncp); 4275 4276 return -EFAULT; 4277 } 4278 4279 len = skb->len; 4280 4281 /* Do update ip stack process */ 4282 skb->protocol = eth_type_trans(skb, netdev); 4283 4284 /* This is needed in order to enable forwarding support */ 4285 ret = hns3_set_gro_and_checksum(ring, skb, l234info, 4286 bd_base_info, ol_info, csum); 4287 if (unlikely(ret)) { 4288 hns3_ring_stats_update(ring, rx_err_cnt); 4289 return ret; 4290 } 4291 4292 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 4293 HNS3_RXD_DMAC_S); 4294 4295 u64_stats_update_begin(&ring->syncp); 4296 ring->stats.rx_pkts++; 4297 ring->stats.rx_bytes += len; 4298 4299 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 4300 ring->stats.rx_multicast++; 4301 4302 u64_stats_update_end(&ring->syncp); 4303 4304 ring->tqp_vector->rx_group.total_bytes += len; 4305 4306 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash), 4307 l234info, ol_info); 4308 return 0; 4309 } 4310 4311 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring) 4312 { 4313 struct sk_buff *skb = ring->skb; 4314 struct hns3_desc_cb *desc_cb; 4315 struct hns3_desc *desc; 4316 unsigned int length; 4317 u32 bd_base_info; 4318 int ret; 4319 4320 desc = &ring->desc[ring->next_to_clean]; 4321 desc_cb = &ring->desc_cb[ring->next_to_clean]; 4322 4323 prefetch(desc); 4324 4325 if (!skb) { 4326 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 4327 /* Check valid BD */ 4328 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 4329 return -ENXIO; 4330 4331 dma_rmb(); 4332 length = le16_to_cpu(desc->rx.size); 4333 4334 ring->va = desc_cb->buf + desc_cb->page_offset; 4335 4336 dma_sync_single_for_cpu(ring_to_dev(ring), 4337 desc_cb->dma + desc_cb->page_offset, 4338 hns3_buf_size(ring), 4339 DMA_FROM_DEVICE); 4340 4341 /* Prefetch first cache line of first page. 4342 * Idea is to cache few bytes of the header of the packet. 4343 * Our L1 Cache line size is 64B so need to prefetch twice to make 4344 * it 128B. But in actual we can have greater size of caches with 4345 * 128B Level 1 cache lines. In such a case, single fetch would 4346 * suffice to cache in the relevant part of the header. 4347 */ 4348 net_prefetch(ring->va); 4349 4350 ret = hns3_alloc_skb(ring, length, ring->va); 4351 skb = ring->skb; 4352 4353 if (ret < 0) /* alloc buffer fail */ 4354 return ret; 4355 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */ 4356 ret = hns3_add_frag(ring); 4357 if (ret) 4358 return ret; 4359 } 4360 } else { 4361 ret = hns3_add_frag(ring); 4362 if (ret) 4363 return ret; 4364 } 4365 4366 /* As the head data may be changed when GRO enable, copy 4367 * the head data in after other data rx completed 4368 */ 4369 if (skb->len > HNS3_RX_HEAD_SIZE) 4370 memcpy(skb->data, ring->va, 4371 ALIGN(ring->pull_len, sizeof(long))); 4372 4373 ret = hns3_handle_bdinfo(ring, skb); 4374 if (unlikely(ret)) { 4375 dev_kfree_skb_any(skb); 4376 return ret; 4377 } 4378 4379 skb_record_rx_queue(skb, ring->tqp->tqp_index); 4380 return 0; 4381 } 4382 4383 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget, 4384 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 4385 { 4386 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 4387 int unused_count = hns3_desc_unused(ring); 4388 bool failure = false; 4389 int recv_pkts = 0; 4390 int err; 4391 4392 unused_count -= ring->pending_buf; 4393 4394 while (recv_pkts < budget) { 4395 /* Reuse or realloc buffers */ 4396 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 4397 failure = failure || 4398 hns3_nic_alloc_rx_buffers(ring, unused_count); 4399 unused_count = 0; 4400 } 4401 4402 /* Poll one pkt */ 4403 err = hns3_handle_rx_bd(ring); 4404 /* Do not get FE for the packet or failed to alloc skb */ 4405 if (unlikely(!ring->skb || err == -ENXIO)) { 4406 goto out; 4407 } else if (likely(!err)) { 4408 rx_fn(ring, ring->skb); 4409 recv_pkts++; 4410 } 4411 4412 unused_count += ring->pending_buf; 4413 ring->skb = NULL; 4414 ring->pending_buf = 0; 4415 } 4416 4417 out: 4418 /* sync head pointer before exiting, since hardware will calculate 4419 * FBD number with head pointer 4420 */ 4421 if (unused_count > 0) 4422 failure = failure || 4423 hns3_nic_alloc_rx_buffers(ring, unused_count); 4424 4425 return failure ? budget : recv_pkts; 4426 } 4427 4428 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector) 4429 { 4430 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 4431 struct dim_sample sample = {}; 4432 4433 if (!rx_group->coal.adapt_enable) 4434 return; 4435 4436 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets, 4437 rx_group->total_bytes, &sample); 4438 net_dim(&rx_group->dim, sample); 4439 } 4440 4441 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector) 4442 { 4443 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 4444 struct dim_sample sample = {}; 4445 4446 if (!tx_group->coal.adapt_enable) 4447 return; 4448 4449 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets, 4450 tx_group->total_bytes, &sample); 4451 net_dim(&tx_group->dim, sample); 4452 } 4453 4454 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 4455 { 4456 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 4457 struct hns3_enet_ring *ring; 4458 int rx_pkt_total = 0; 4459 4460 struct hns3_enet_tqp_vector *tqp_vector = 4461 container_of(napi, struct hns3_enet_tqp_vector, napi); 4462 bool clean_complete = true; 4463 int rx_budget = budget; 4464 4465 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 4466 napi_complete(napi); 4467 return 0; 4468 } 4469 4470 /* Since the actual Tx work is minimal, we can give the Tx a larger 4471 * budget and be more aggressive about cleaning up the Tx descriptors. 4472 */ 4473 hns3_for_each_ring(ring, tqp_vector->tx_group) 4474 hns3_clean_tx_ring(ring, budget); 4475 4476 /* make sure rx ring budget not smaller than 1 */ 4477 if (tqp_vector->num_tqps > 1) 4478 rx_budget = max(budget / tqp_vector->num_tqps, 1); 4479 4480 hns3_for_each_ring(ring, tqp_vector->rx_group) { 4481 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 4482 hns3_rx_skb); 4483 if (rx_cleaned >= rx_budget) 4484 clean_complete = false; 4485 4486 rx_pkt_total += rx_cleaned; 4487 } 4488 4489 tqp_vector->rx_group.total_packets += rx_pkt_total; 4490 4491 if (!clean_complete) 4492 return budget; 4493 4494 if (napi_complete(napi) && 4495 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 4496 hns3_update_rx_int_coalesce(tqp_vector); 4497 hns3_update_tx_int_coalesce(tqp_vector); 4498 4499 hns3_mask_vector_irq(tqp_vector, 1); 4500 } 4501 4502 return rx_pkt_total; 4503 } 4504 4505 static int hns3_create_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 4506 struct hnae3_ring_chain_node **head, 4507 bool is_tx) 4508 { 4509 u32 bit_value = is_tx ? HNAE3_RING_TYPE_TX : HNAE3_RING_TYPE_RX; 4510 u32 field_value = is_tx ? HNAE3_RING_GL_TX : HNAE3_RING_GL_RX; 4511 struct hnae3_ring_chain_node *cur_chain = *head; 4512 struct pci_dev *pdev = tqp_vector->handle->pdev; 4513 struct hnae3_ring_chain_node *chain; 4514 struct hns3_enet_ring *ring; 4515 4516 ring = is_tx ? tqp_vector->tx_group.ring : tqp_vector->rx_group.ring; 4517 4518 if (cur_chain) { 4519 while (cur_chain->next) 4520 cur_chain = cur_chain->next; 4521 } 4522 4523 while (ring) { 4524 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 4525 if (!chain) 4526 return -ENOMEM; 4527 if (cur_chain) 4528 cur_chain->next = chain; 4529 else 4530 *head = chain; 4531 chain->tqp_index = ring->tqp->tqp_index; 4532 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 4533 bit_value); 4534 hnae3_set_field(chain->int_gl_idx, 4535 HNAE3_RING_GL_IDX_M, 4536 HNAE3_RING_GL_IDX_S, field_value); 4537 4538 cur_chain = chain; 4539 4540 ring = ring->next; 4541 } 4542 4543 return 0; 4544 } 4545 4546 static struct hnae3_ring_chain_node * 4547 hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector) 4548 { 4549 struct pci_dev *pdev = tqp_vector->handle->pdev; 4550 struct hnae3_ring_chain_node *cur_chain = NULL; 4551 struct hnae3_ring_chain_node *chain; 4552 4553 if (hns3_create_ring_chain(tqp_vector, &cur_chain, true)) 4554 goto err_free_chain; 4555 4556 if (hns3_create_ring_chain(tqp_vector, &cur_chain, false)) 4557 goto err_free_chain; 4558 4559 return cur_chain; 4560 4561 err_free_chain: 4562 while (cur_chain) { 4563 chain = cur_chain->next; 4564 devm_kfree(&pdev->dev, cur_chain); 4565 cur_chain = chain; 4566 } 4567 4568 return NULL; 4569 } 4570 4571 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 4572 struct hnae3_ring_chain_node *head) 4573 { 4574 struct pci_dev *pdev = tqp_vector->handle->pdev; 4575 struct hnae3_ring_chain_node *chain_tmp, *chain; 4576 4577 chain = head; 4578 4579 while (chain) { 4580 chain_tmp = chain->next; 4581 devm_kfree(&pdev->dev, chain); 4582 chain = chain_tmp; 4583 } 4584 } 4585 4586 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 4587 struct hns3_enet_ring *ring) 4588 { 4589 ring->next = group->ring; 4590 group->ring = ring; 4591 4592 group->count++; 4593 } 4594 4595 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 4596 { 4597 struct pci_dev *pdev = priv->ae_handle->pdev; 4598 struct hns3_enet_tqp_vector *tqp_vector; 4599 int num_vectors = priv->vector_num; 4600 int numa_node; 4601 int vector_i; 4602 4603 numa_node = dev_to_node(&pdev->dev); 4604 4605 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 4606 tqp_vector = &priv->tqp_vector[vector_i]; 4607 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 4608 &tqp_vector->affinity_mask); 4609 } 4610 } 4611 4612 static void hns3_rx_dim_work(struct work_struct *work) 4613 { 4614 struct dim *dim = container_of(work, struct dim, work); 4615 struct hns3_enet_ring_group *group = container_of(dim, 4616 struct hns3_enet_ring_group, dim); 4617 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector; 4618 struct dim_cq_moder cur_moder = 4619 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 4620 4621 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec); 4622 tqp_vector->rx_group.coal.int_gl = cur_moder.usec; 4623 4624 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) { 4625 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts); 4626 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts; 4627 } 4628 4629 dim->state = DIM_START_MEASURE; 4630 } 4631 4632 static void hns3_tx_dim_work(struct work_struct *work) 4633 { 4634 struct dim *dim = container_of(work, struct dim, work); 4635 struct hns3_enet_ring_group *group = container_of(dim, 4636 struct hns3_enet_ring_group, dim); 4637 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector; 4638 struct dim_cq_moder cur_moder = 4639 net_dim_get_tx_moderation(dim->mode, dim->profile_ix); 4640 4641 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec); 4642 tqp_vector->tx_group.coal.int_gl = cur_moder.usec; 4643 4644 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) { 4645 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts); 4646 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts; 4647 } 4648 4649 dim->state = DIM_START_MEASURE; 4650 } 4651 4652 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector) 4653 { 4654 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work); 4655 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work); 4656 } 4657 4658 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 4659 { 4660 struct hnae3_handle *h = priv->ae_handle; 4661 struct hns3_enet_tqp_vector *tqp_vector; 4662 int ret; 4663 int i; 4664 4665 hns3_nic_set_cpumask(priv); 4666 4667 for (i = 0; i < priv->vector_num; i++) { 4668 tqp_vector = &priv->tqp_vector[i]; 4669 hns3_vector_coalesce_init_hw(tqp_vector, priv); 4670 tqp_vector->num_tqps = 0; 4671 hns3_nic_init_dim(tqp_vector); 4672 } 4673 4674 for (i = 0; i < h->kinfo.num_tqps; i++) { 4675 u16 vector_i = i % priv->vector_num; 4676 u16 tqp_num = h->kinfo.num_tqps; 4677 4678 tqp_vector = &priv->tqp_vector[vector_i]; 4679 4680 hns3_add_ring_to_group(&tqp_vector->tx_group, 4681 &priv->ring[i]); 4682 4683 hns3_add_ring_to_group(&tqp_vector->rx_group, 4684 &priv->ring[i + tqp_num]); 4685 4686 priv->ring[i].tqp_vector = tqp_vector; 4687 priv->ring[i + tqp_num].tqp_vector = tqp_vector; 4688 tqp_vector->num_tqps++; 4689 } 4690 4691 for (i = 0; i < priv->vector_num; i++) { 4692 struct hnae3_ring_chain_node *vector_ring_chain; 4693 4694 tqp_vector = &priv->tqp_vector[i]; 4695 4696 tqp_vector->rx_group.total_bytes = 0; 4697 tqp_vector->rx_group.total_packets = 0; 4698 tqp_vector->tx_group.total_bytes = 0; 4699 tqp_vector->tx_group.total_packets = 0; 4700 tqp_vector->handle = h; 4701 4702 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector); 4703 if (!vector_ring_chain) { 4704 ret = -ENOMEM; 4705 goto map_ring_fail; 4706 } 4707 4708 ret = h->ae_algo->ops->map_ring_to_vector(h, 4709 tqp_vector->vector_irq, vector_ring_chain); 4710 4711 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain); 4712 4713 if (ret) 4714 goto map_ring_fail; 4715 4716 netif_napi_add(priv->netdev, &tqp_vector->napi, 4717 hns3_nic_common_poll); 4718 } 4719 4720 return 0; 4721 4722 map_ring_fail: 4723 while (i--) 4724 netif_napi_del(&priv->tqp_vector[i].napi); 4725 4726 return ret; 4727 } 4728 4729 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv) 4730 { 4731 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 4732 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal; 4733 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal; 4734 4735 /* initialize the configuration for interrupt coalescing. 4736 * 1. GL (Interrupt Gap Limiter) 4737 * 2. RL (Interrupt Rate Limiter) 4738 * 3. QL (Interrupt Quantity Limiter) 4739 * 4740 * Default: enable interrupt coalescing self-adaptive and GL 4741 */ 4742 tx_coal->adapt_enable = 1; 4743 rx_coal->adapt_enable = 1; 4744 4745 tx_coal->int_gl = HNS3_INT_GL_50K; 4746 rx_coal->int_gl = HNS3_INT_GL_50K; 4747 4748 rx_coal->flow_level = HNS3_FLOW_LOW; 4749 tx_coal->flow_level = HNS3_FLOW_LOW; 4750 4751 if (ae_dev->dev_specs.int_ql_max) { 4752 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 4753 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 4754 } 4755 } 4756 4757 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 4758 { 4759 struct hnae3_handle *h = priv->ae_handle; 4760 struct hns3_enet_tqp_vector *tqp_vector; 4761 struct hnae3_vector_info *vector; 4762 struct pci_dev *pdev = h->pdev; 4763 u16 tqp_num = h->kinfo.num_tqps; 4764 u16 vector_num; 4765 int ret = 0; 4766 u16 i; 4767 4768 /* RSS size, cpu online and vector_num should be the same */ 4769 /* Should consider 2p/4p later */ 4770 vector_num = min_t(u16, num_online_cpus(), tqp_num); 4771 4772 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 4773 GFP_KERNEL); 4774 if (!vector) 4775 return -ENOMEM; 4776 4777 /* save the actual available vector number */ 4778 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 4779 4780 priv->vector_num = vector_num; 4781 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 4782 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 4783 GFP_KERNEL); 4784 if (!priv->tqp_vector) { 4785 ret = -ENOMEM; 4786 goto out; 4787 } 4788 4789 for (i = 0; i < priv->vector_num; i++) { 4790 tqp_vector = &priv->tqp_vector[i]; 4791 tqp_vector->idx = i; 4792 tqp_vector->mask_addr = vector[i].io_addr; 4793 tqp_vector->vector_irq = vector[i].vector; 4794 hns3_vector_coalesce_init(tqp_vector, priv); 4795 } 4796 4797 out: 4798 devm_kfree(&pdev->dev, vector); 4799 return ret; 4800 } 4801 4802 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 4803 { 4804 group->ring = NULL; 4805 group->count = 0; 4806 } 4807 4808 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 4809 { 4810 struct hnae3_ring_chain_node *vector_ring_chain; 4811 struct hnae3_handle *h = priv->ae_handle; 4812 struct hns3_enet_tqp_vector *tqp_vector; 4813 int i; 4814 4815 for (i = 0; i < priv->vector_num; i++) { 4816 tqp_vector = &priv->tqp_vector[i]; 4817 4818 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 4819 continue; 4820 4821 /* Since the mapping can be overwritten, when fail to get the 4822 * chain between vector and ring, we should go on to deal with 4823 * the remaining options. 4824 */ 4825 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector); 4826 if (!vector_ring_chain) 4827 dev_warn(priv->dev, "failed to get ring chain\n"); 4828 4829 h->ae_algo->ops->unmap_ring_from_vector(h, 4830 tqp_vector->vector_irq, vector_ring_chain); 4831 4832 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain); 4833 4834 hns3_clear_ring_group(&tqp_vector->rx_group); 4835 hns3_clear_ring_group(&tqp_vector->tx_group); 4836 netif_napi_del(&priv->tqp_vector[i].napi); 4837 } 4838 } 4839 4840 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 4841 { 4842 struct hnae3_handle *h = priv->ae_handle; 4843 struct pci_dev *pdev = h->pdev; 4844 int i, ret; 4845 4846 for (i = 0; i < priv->vector_num; i++) { 4847 struct hns3_enet_tqp_vector *tqp_vector; 4848 4849 tqp_vector = &priv->tqp_vector[i]; 4850 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 4851 if (ret) 4852 return; 4853 } 4854 4855 devm_kfree(&pdev->dev, priv->tqp_vector); 4856 } 4857 4858 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 4859 unsigned int ring_type) 4860 { 4861 int queue_num = priv->ae_handle->kinfo.num_tqps; 4862 struct hns3_enet_ring *ring; 4863 int desc_num; 4864 4865 if (ring_type == HNAE3_RING_TYPE_TX) { 4866 ring = &priv->ring[q->tqp_index]; 4867 desc_num = priv->ae_handle->kinfo.num_tx_desc; 4868 ring->queue_index = q->tqp_index; 4869 ring->tx_copybreak = priv->tx_copybreak; 4870 ring->last_to_use = 0; 4871 } else { 4872 ring = &priv->ring[q->tqp_index + queue_num]; 4873 desc_num = priv->ae_handle->kinfo.num_rx_desc; 4874 ring->queue_index = q->tqp_index; 4875 ring->rx_copybreak = priv->rx_copybreak; 4876 } 4877 4878 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 4879 4880 ring->tqp = q; 4881 ring->desc = NULL; 4882 ring->desc_cb = NULL; 4883 ring->dev = priv->dev; 4884 ring->desc_dma_addr = 0; 4885 ring->buf_size = q->buf_size; 4886 ring->desc_num = desc_num; 4887 ring->next_to_use = 0; 4888 ring->next_to_clean = 0; 4889 } 4890 4891 static void hns3_queue_to_ring(struct hnae3_queue *tqp, 4892 struct hns3_nic_priv *priv) 4893 { 4894 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 4895 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 4896 } 4897 4898 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 4899 { 4900 struct hnae3_handle *h = priv->ae_handle; 4901 struct pci_dev *pdev = h->pdev; 4902 int i; 4903 4904 priv->ring = devm_kzalloc(&pdev->dev, 4905 array3_size(h->kinfo.num_tqps, 4906 sizeof(*priv->ring), 2), 4907 GFP_KERNEL); 4908 if (!priv->ring) 4909 return -ENOMEM; 4910 4911 for (i = 0; i < h->kinfo.num_tqps; i++) 4912 hns3_queue_to_ring(h->kinfo.tqp[i], priv); 4913 4914 return 0; 4915 } 4916 4917 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 4918 { 4919 if (!priv->ring) 4920 return; 4921 4922 devm_kfree(priv->dev, priv->ring); 4923 priv->ring = NULL; 4924 } 4925 4926 static void hns3_alloc_page_pool(struct hns3_enet_ring *ring) 4927 { 4928 struct page_pool_params pp_params = { 4929 .flags = PP_FLAG_DMA_MAP | PP_FLAG_PAGE_FRAG | 4930 PP_FLAG_DMA_SYNC_DEV, 4931 .order = hns3_page_order(ring), 4932 .pool_size = ring->desc_num * hns3_buf_size(ring) / 4933 (PAGE_SIZE << hns3_page_order(ring)), 4934 .nid = dev_to_node(ring_to_dev(ring)), 4935 .dev = ring_to_dev(ring), 4936 .dma_dir = DMA_FROM_DEVICE, 4937 .offset = 0, 4938 .max_len = PAGE_SIZE << hns3_page_order(ring), 4939 }; 4940 4941 ring->page_pool = page_pool_create(&pp_params); 4942 if (IS_ERR(ring->page_pool)) { 4943 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n", 4944 PTR_ERR(ring->page_pool)); 4945 ring->page_pool = NULL; 4946 } 4947 } 4948 4949 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 4950 { 4951 int ret; 4952 4953 if (ring->desc_num <= 0 || ring->buf_size <= 0) 4954 return -EINVAL; 4955 4956 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num, 4957 sizeof(ring->desc_cb[0]), GFP_KERNEL); 4958 if (!ring->desc_cb) { 4959 ret = -ENOMEM; 4960 goto out; 4961 } 4962 4963 ret = hns3_alloc_desc(ring); 4964 if (ret) 4965 goto out_with_desc_cb; 4966 4967 if (!HNAE3_IS_TX_RING(ring)) { 4968 if (page_pool_enabled) 4969 hns3_alloc_page_pool(ring); 4970 4971 ret = hns3_alloc_ring_buffers(ring); 4972 if (ret) 4973 goto out_with_desc; 4974 } else { 4975 hns3_init_tx_spare_buffer(ring); 4976 } 4977 4978 return 0; 4979 4980 out_with_desc: 4981 hns3_free_desc(ring); 4982 out_with_desc_cb: 4983 devm_kfree(ring_to_dev(ring), ring->desc_cb); 4984 ring->desc_cb = NULL; 4985 out: 4986 return ret; 4987 } 4988 4989 void hns3_fini_ring(struct hns3_enet_ring *ring) 4990 { 4991 hns3_free_desc(ring); 4992 devm_kfree(ring_to_dev(ring), ring->desc_cb); 4993 ring->desc_cb = NULL; 4994 ring->next_to_clean = 0; 4995 ring->next_to_use = 0; 4996 ring->last_to_use = 0; 4997 ring->pending_buf = 0; 4998 if (!HNAE3_IS_TX_RING(ring) && ring->skb) { 4999 dev_kfree_skb_any(ring->skb); 5000 ring->skb = NULL; 5001 } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) { 5002 struct hns3_tx_spare *tx_spare = ring->tx_spare; 5003 5004 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len, 5005 DMA_TO_DEVICE); 5006 free_pages((unsigned long)tx_spare->buf, 5007 get_order(tx_spare->len)); 5008 devm_kfree(ring_to_dev(ring), tx_spare); 5009 ring->tx_spare = NULL; 5010 } 5011 5012 if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) { 5013 page_pool_destroy(ring->page_pool); 5014 ring->page_pool = NULL; 5015 } 5016 } 5017 5018 static int hns3_buf_size2type(u32 buf_size) 5019 { 5020 int bd_size_type; 5021 5022 switch (buf_size) { 5023 case 512: 5024 bd_size_type = HNS3_BD_SIZE_512_TYPE; 5025 break; 5026 case 1024: 5027 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 5028 break; 5029 case 2048: 5030 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 5031 break; 5032 case 4096: 5033 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 5034 break; 5035 default: 5036 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 5037 } 5038 5039 return bd_size_type; 5040 } 5041 5042 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 5043 { 5044 dma_addr_t dma = ring->desc_dma_addr; 5045 struct hnae3_queue *q = ring->tqp; 5046 5047 if (!HNAE3_IS_TX_RING(ring)) { 5048 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma); 5049 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 5050 (u32)((dma >> 31) >> 1)); 5051 5052 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 5053 hns3_buf_size2type(ring->buf_size)); 5054 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 5055 ring->desc_num / 8 - 1); 5056 } else { 5057 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 5058 (u32)dma); 5059 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 5060 (u32)((dma >> 31) >> 1)); 5061 5062 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 5063 ring->desc_num / 8 - 1); 5064 } 5065 } 5066 5067 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 5068 { 5069 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 5070 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 5071 int i; 5072 5073 for (i = 0; i < tc_info->num_tc; i++) { 5074 int j; 5075 5076 for (j = 0; j < tc_info->tqp_count[i]; j++) { 5077 struct hnae3_queue *q; 5078 5079 q = priv->ring[tc_info->tqp_offset[i] + j].tqp; 5080 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i); 5081 } 5082 } 5083 } 5084 5085 int hns3_init_all_ring(struct hns3_nic_priv *priv) 5086 { 5087 struct hnae3_handle *h = priv->ae_handle; 5088 int ring_num = h->kinfo.num_tqps * 2; 5089 int i, j; 5090 int ret; 5091 5092 for (i = 0; i < ring_num; i++) { 5093 ret = hns3_alloc_ring_memory(&priv->ring[i]); 5094 if (ret) { 5095 dev_err(priv->dev, 5096 "Alloc ring memory fail! ret=%d\n", ret); 5097 goto out_when_alloc_ring_memory; 5098 } 5099 5100 u64_stats_init(&priv->ring[i].syncp); 5101 } 5102 5103 return 0; 5104 5105 out_when_alloc_ring_memory: 5106 for (j = i - 1; j >= 0; j--) 5107 hns3_fini_ring(&priv->ring[j]); 5108 5109 return -ENOMEM; 5110 } 5111 5112 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv) 5113 { 5114 struct hnae3_handle *h = priv->ae_handle; 5115 int i; 5116 5117 for (i = 0; i < h->kinfo.num_tqps; i++) { 5118 hns3_fini_ring(&priv->ring[i]); 5119 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]); 5120 } 5121 } 5122 5123 /* Set mac addr if it is configured. or leave it to the AE driver */ 5124 static int hns3_init_mac_addr(struct net_device *netdev) 5125 { 5126 struct hns3_nic_priv *priv = netdev_priv(netdev); 5127 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 5128 struct hnae3_handle *h = priv->ae_handle; 5129 u8 mac_addr_temp[ETH_ALEN]; 5130 int ret = 0; 5131 5132 if (h->ae_algo->ops->get_mac_addr) 5133 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 5134 5135 /* Check if the MAC address is valid, if not get a random one */ 5136 if (!is_valid_ether_addr(mac_addr_temp)) { 5137 eth_hw_addr_random(netdev); 5138 hnae3_format_mac_addr(format_mac_addr, netdev->dev_addr); 5139 dev_warn(priv->dev, "using random MAC address %s\n", 5140 format_mac_addr); 5141 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) { 5142 eth_hw_addr_set(netdev, mac_addr_temp); 5143 ether_addr_copy(netdev->perm_addr, mac_addr_temp); 5144 } else { 5145 return 0; 5146 } 5147 5148 if (h->ae_algo->ops->set_mac_addr) 5149 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 5150 5151 return ret; 5152 } 5153 5154 static int hns3_init_phy(struct net_device *netdev) 5155 { 5156 struct hnae3_handle *h = hns3_get_handle(netdev); 5157 int ret = 0; 5158 5159 if (h->ae_algo->ops->mac_connect_phy) 5160 ret = h->ae_algo->ops->mac_connect_phy(h); 5161 5162 return ret; 5163 } 5164 5165 static void hns3_uninit_phy(struct net_device *netdev) 5166 { 5167 struct hnae3_handle *h = hns3_get_handle(netdev); 5168 5169 if (h->ae_algo->ops->mac_disconnect_phy) 5170 h->ae_algo->ops->mac_disconnect_phy(h); 5171 } 5172 5173 static int hns3_client_start(struct hnae3_handle *handle) 5174 { 5175 if (!handle->ae_algo->ops->client_start) 5176 return 0; 5177 5178 return handle->ae_algo->ops->client_start(handle); 5179 } 5180 5181 static void hns3_client_stop(struct hnae3_handle *handle) 5182 { 5183 if (!handle->ae_algo->ops->client_stop) 5184 return; 5185 5186 handle->ae_algo->ops->client_stop(handle); 5187 } 5188 5189 static void hns3_info_show(struct hns3_nic_priv *priv) 5190 { 5191 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 5192 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 5193 5194 hnae3_format_mac_addr(format_mac_addr, priv->netdev->dev_addr); 5195 dev_info(priv->dev, "MAC address: %s\n", format_mac_addr); 5196 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps); 5197 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size); 5198 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size); 5199 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len); 5200 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc); 5201 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc); 5202 dev_info(priv->dev, "Total number of enabled TCs: %u\n", 5203 kinfo->tc_info.num_tc); 5204 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu); 5205 } 5206 5207 static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv, 5208 enum dim_cq_period_mode mode, bool is_tx) 5209 { 5210 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 5211 struct hnae3_handle *handle = priv->ae_handle; 5212 int i; 5213 5214 if (is_tx) { 5215 priv->tx_cqe_mode = mode; 5216 5217 for (i = 0; i < priv->vector_num; i++) 5218 priv->tqp_vector[i].tx_group.dim.mode = mode; 5219 } else { 5220 priv->rx_cqe_mode = mode; 5221 5222 for (i = 0; i < priv->vector_num; i++) 5223 priv->tqp_vector[i].rx_group.dim.mode = mode; 5224 } 5225 5226 if (hnae3_ae_dev_cq_supported(ae_dev)) { 5227 u32 new_mode; 5228 u64 reg; 5229 5230 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ? 5231 HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE; 5232 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG; 5233 5234 writel(new_mode, handle->kinfo.io_base + reg); 5235 } 5236 } 5237 5238 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv, 5239 enum dim_cq_period_mode tx_mode, 5240 enum dim_cq_period_mode rx_mode) 5241 { 5242 hns3_set_cq_period_mode(priv, tx_mode, true); 5243 hns3_set_cq_period_mode(priv, rx_mode, false); 5244 } 5245 5246 static void hns3_state_init(struct hnae3_handle *handle) 5247 { 5248 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 5249 struct net_device *netdev = handle->kinfo.netdev; 5250 struct hns3_nic_priv *priv = netdev_priv(netdev); 5251 5252 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 5253 5254 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 5255 set_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state); 5256 5257 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5258 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags); 5259 5260 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) 5261 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state); 5262 5263 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev)) 5264 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state); 5265 } 5266 5267 static void hns3_state_uninit(struct hnae3_handle *handle) 5268 { 5269 struct hns3_nic_priv *priv = handle->priv; 5270 5271 clear_bit(HNS3_NIC_STATE_INITED, &priv->state); 5272 } 5273 5274 static int hns3_client_init(struct hnae3_handle *handle) 5275 { 5276 struct pci_dev *pdev = handle->pdev; 5277 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 5278 u16 alloc_tqps, max_rss_size; 5279 struct hns3_nic_priv *priv; 5280 struct net_device *netdev; 5281 int ret; 5282 5283 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 5284 &max_rss_size); 5285 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 5286 if (!netdev) 5287 return -ENOMEM; 5288 5289 priv = netdev_priv(netdev); 5290 priv->dev = &pdev->dev; 5291 priv->netdev = netdev; 5292 priv->ae_handle = handle; 5293 priv->tx_timeout_count = 0; 5294 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num; 5295 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 5296 5297 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL); 5298 5299 handle->kinfo.netdev = netdev; 5300 handle->priv = (void *)priv; 5301 5302 hns3_init_mac_addr(netdev); 5303 5304 hns3_set_default_feature(netdev); 5305 5306 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 5307 netdev->priv_flags |= IFF_UNICAST_FLT; 5308 netdev->netdev_ops = &hns3_nic_netdev_ops; 5309 SET_NETDEV_DEV(netdev, &pdev->dev); 5310 hns3_ethtool_set_ops(netdev); 5311 5312 /* Carrier off reporting is important to ethtool even BEFORE open */ 5313 netif_carrier_off(netdev); 5314 5315 ret = hns3_get_ring_config(priv); 5316 if (ret) { 5317 ret = -ENOMEM; 5318 goto out_get_ring_cfg; 5319 } 5320 5321 hns3_nic_init_coal_cfg(priv); 5322 5323 ret = hns3_nic_alloc_vector_data(priv); 5324 if (ret) { 5325 ret = -ENOMEM; 5326 goto out_alloc_vector_data; 5327 } 5328 5329 ret = hns3_nic_init_vector_data(priv); 5330 if (ret) { 5331 ret = -ENOMEM; 5332 goto out_init_vector_data; 5333 } 5334 5335 ret = hns3_init_all_ring(priv); 5336 if (ret) { 5337 ret = -ENOMEM; 5338 goto out_init_ring; 5339 } 5340 5341 hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE, 5342 DIM_CQ_PERIOD_MODE_START_FROM_EQE); 5343 5344 ret = hns3_init_phy(netdev); 5345 if (ret) 5346 goto out_init_phy; 5347 5348 /* the device can work without cpu rmap, only aRFS needs it */ 5349 ret = hns3_set_rx_cpu_rmap(netdev); 5350 if (ret) 5351 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 5352 5353 ret = hns3_nic_init_irq(priv); 5354 if (ret) { 5355 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 5356 hns3_free_rx_cpu_rmap(netdev); 5357 goto out_init_irq_fail; 5358 } 5359 5360 ret = hns3_client_start(handle); 5361 if (ret) { 5362 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 5363 goto out_client_start; 5364 } 5365 5366 hns3_dcbnl_setup(handle); 5367 5368 ret = hns3_dbg_init(handle); 5369 if (ret) { 5370 dev_err(priv->dev, "failed to init debugfs, ret = %d\n", 5371 ret); 5372 goto out_client_start; 5373 } 5374 5375 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size); 5376 5377 hns3_state_init(handle); 5378 5379 ret = register_netdev(netdev); 5380 if (ret) { 5381 dev_err(priv->dev, "probe register netdev fail!\n"); 5382 goto out_reg_netdev_fail; 5383 } 5384 5385 if (netif_msg_drv(handle)) 5386 hns3_info_show(priv); 5387 5388 return ret; 5389 5390 out_reg_netdev_fail: 5391 hns3_state_uninit(handle); 5392 hns3_dbg_uninit(handle); 5393 hns3_client_stop(handle); 5394 out_client_start: 5395 hns3_free_rx_cpu_rmap(netdev); 5396 hns3_nic_uninit_irq(priv); 5397 out_init_irq_fail: 5398 hns3_uninit_phy(netdev); 5399 out_init_phy: 5400 hns3_uninit_all_ring(priv); 5401 out_init_ring: 5402 hns3_nic_uninit_vector_data(priv); 5403 out_init_vector_data: 5404 hns3_nic_dealloc_vector_data(priv); 5405 out_alloc_vector_data: 5406 priv->ring = NULL; 5407 out_get_ring_cfg: 5408 priv->ae_handle = NULL; 5409 free_netdev(netdev); 5410 return ret; 5411 } 5412 5413 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 5414 { 5415 struct net_device *netdev = handle->kinfo.netdev; 5416 struct hns3_nic_priv *priv = netdev_priv(netdev); 5417 5418 if (netdev->reg_state != NETREG_UNINITIALIZED) 5419 unregister_netdev(netdev); 5420 5421 hns3_client_stop(handle); 5422 5423 hns3_uninit_phy(netdev); 5424 5425 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 5426 netdev_warn(netdev, "already uninitialized\n"); 5427 goto out_netdev_free; 5428 } 5429 5430 hns3_free_rx_cpu_rmap(netdev); 5431 5432 hns3_nic_uninit_irq(priv); 5433 5434 hns3_clear_all_ring(handle, true); 5435 5436 hns3_nic_uninit_vector_data(priv); 5437 5438 hns3_nic_dealloc_vector_data(priv); 5439 5440 hns3_uninit_all_ring(priv); 5441 5442 hns3_put_ring_config(priv); 5443 5444 out_netdev_free: 5445 hns3_dbg_uninit(handle); 5446 free_netdev(netdev); 5447 } 5448 5449 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 5450 { 5451 struct net_device *netdev = handle->kinfo.netdev; 5452 5453 if (!netdev) 5454 return; 5455 5456 if (linkup) { 5457 netif_tx_wake_all_queues(netdev); 5458 netif_carrier_on(netdev); 5459 if (netif_msg_link(handle)) 5460 netdev_info(netdev, "link up\n"); 5461 } else { 5462 netif_carrier_off(netdev); 5463 netif_tx_stop_all_queues(netdev); 5464 if (netif_msg_link(handle)) 5465 netdev_info(netdev, "link down\n"); 5466 } 5467 } 5468 5469 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 5470 { 5471 while (ring->next_to_clean != ring->next_to_use) { 5472 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 5473 hns3_free_buffer_detach(ring, ring->next_to_clean, 0); 5474 ring_ptr_move_fw(ring, next_to_clean); 5475 } 5476 5477 ring->pending_buf = 0; 5478 } 5479 5480 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 5481 { 5482 struct hns3_desc_cb res_cbs; 5483 int ret; 5484 5485 while (ring->next_to_use != ring->next_to_clean) { 5486 /* When a buffer is not reused, it's memory has been 5487 * freed in hns3_handle_rx_bd or will be freed by 5488 * stack, so we need to replace the buffer here. 5489 */ 5490 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 5491 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 5492 if (ret) { 5493 hns3_ring_stats_update(ring, sw_err_cnt); 5494 /* if alloc new buffer fail, exit directly 5495 * and reclear in up flow. 5496 */ 5497 netdev_warn(ring_to_netdev(ring), 5498 "reserve buffer map failed, ret = %d\n", 5499 ret); 5500 return ret; 5501 } 5502 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 5503 } 5504 ring_ptr_move_fw(ring, next_to_use); 5505 } 5506 5507 /* Free the pending skb in rx ring */ 5508 if (ring->skb) { 5509 dev_kfree_skb_any(ring->skb); 5510 ring->skb = NULL; 5511 ring->pending_buf = 0; 5512 } 5513 5514 return 0; 5515 } 5516 5517 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 5518 { 5519 while (ring->next_to_use != ring->next_to_clean) { 5520 /* When a buffer is not reused, it's memory has been 5521 * freed in hns3_handle_rx_bd or will be freed by 5522 * stack, so only need to unmap the buffer here. 5523 */ 5524 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 5525 hns3_unmap_buffer(ring, 5526 &ring->desc_cb[ring->next_to_use]); 5527 ring->desc_cb[ring->next_to_use].dma = 0; 5528 } 5529 5530 ring_ptr_move_fw(ring, next_to_use); 5531 } 5532 } 5533 5534 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force) 5535 { 5536 struct net_device *ndev = h->kinfo.netdev; 5537 struct hns3_nic_priv *priv = netdev_priv(ndev); 5538 u32 i; 5539 5540 for (i = 0; i < h->kinfo.num_tqps; i++) { 5541 struct hns3_enet_ring *ring; 5542 5543 ring = &priv->ring[i]; 5544 hns3_clear_tx_ring(ring); 5545 5546 ring = &priv->ring[i + h->kinfo.num_tqps]; 5547 /* Continue to clear other rings even if clearing some 5548 * rings failed. 5549 */ 5550 if (force) 5551 hns3_force_clear_rx_ring(ring); 5552 else 5553 hns3_clear_rx_ring(ring); 5554 } 5555 } 5556 5557 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 5558 { 5559 struct net_device *ndev = h->kinfo.netdev; 5560 struct hns3_nic_priv *priv = netdev_priv(ndev); 5561 struct hns3_enet_ring *rx_ring; 5562 int i, j; 5563 int ret; 5564 5565 ret = h->ae_algo->ops->reset_queue(h); 5566 if (ret) 5567 return ret; 5568 5569 for (i = 0; i < h->kinfo.num_tqps; i++) { 5570 hns3_init_ring_hw(&priv->ring[i]); 5571 5572 /* We need to clear tx ring here because self test will 5573 * use the ring and will not run down before up 5574 */ 5575 hns3_clear_tx_ring(&priv->ring[i]); 5576 priv->ring[i].next_to_clean = 0; 5577 priv->ring[i].next_to_use = 0; 5578 priv->ring[i].last_to_use = 0; 5579 5580 rx_ring = &priv->ring[i + h->kinfo.num_tqps]; 5581 hns3_init_ring_hw(rx_ring); 5582 ret = hns3_clear_rx_ring(rx_ring); 5583 if (ret) 5584 return ret; 5585 5586 /* We can not know the hardware head and tail when this 5587 * function is called in reset flow, so we reuse all desc. 5588 */ 5589 for (j = 0; j < rx_ring->desc_num; j++) 5590 hns3_reuse_buffer(rx_ring, j); 5591 5592 rx_ring->next_to_clean = 0; 5593 rx_ring->next_to_use = 0; 5594 } 5595 5596 hns3_init_tx_ring_tc(priv); 5597 5598 return 0; 5599 } 5600 5601 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 5602 { 5603 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 5604 struct net_device *ndev = kinfo->netdev; 5605 struct hns3_nic_priv *priv = netdev_priv(ndev); 5606 5607 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 5608 return 0; 5609 5610 if (!netif_running(ndev)) 5611 return 0; 5612 5613 return hns3_nic_net_stop(ndev); 5614 } 5615 5616 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 5617 { 5618 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 5619 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 5620 int ret = 0; 5621 5622 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 5623 netdev_err(kinfo->netdev, "device is not initialized yet\n"); 5624 return -EFAULT; 5625 } 5626 5627 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 5628 5629 if (netif_running(kinfo->netdev)) { 5630 ret = hns3_nic_net_open(kinfo->netdev); 5631 if (ret) { 5632 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 5633 netdev_err(kinfo->netdev, 5634 "net up fail, ret=%d!\n", ret); 5635 return ret; 5636 } 5637 } 5638 5639 return ret; 5640 } 5641 5642 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 5643 { 5644 struct net_device *netdev = handle->kinfo.netdev; 5645 struct hns3_nic_priv *priv = netdev_priv(netdev); 5646 int ret; 5647 5648 /* Carrier off reporting is important to ethtool even BEFORE open */ 5649 netif_carrier_off(netdev); 5650 5651 ret = hns3_get_ring_config(priv); 5652 if (ret) 5653 return ret; 5654 5655 ret = hns3_nic_alloc_vector_data(priv); 5656 if (ret) 5657 goto err_put_ring; 5658 5659 ret = hns3_nic_init_vector_data(priv); 5660 if (ret) 5661 goto err_dealloc_vector; 5662 5663 ret = hns3_init_all_ring(priv); 5664 if (ret) 5665 goto err_uninit_vector; 5666 5667 hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode); 5668 5669 /* the device can work without cpu rmap, only aRFS needs it */ 5670 ret = hns3_set_rx_cpu_rmap(netdev); 5671 if (ret) 5672 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 5673 5674 ret = hns3_nic_init_irq(priv); 5675 if (ret) { 5676 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 5677 hns3_free_rx_cpu_rmap(netdev); 5678 goto err_init_irq_fail; 5679 } 5680 5681 if (!hns3_is_phys_func(handle->pdev)) 5682 hns3_init_mac_addr(netdev); 5683 5684 ret = hns3_client_start(handle); 5685 if (ret) { 5686 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 5687 goto err_client_start_fail; 5688 } 5689 5690 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 5691 5692 return ret; 5693 5694 err_client_start_fail: 5695 hns3_free_rx_cpu_rmap(netdev); 5696 hns3_nic_uninit_irq(priv); 5697 err_init_irq_fail: 5698 hns3_uninit_all_ring(priv); 5699 err_uninit_vector: 5700 hns3_nic_uninit_vector_data(priv); 5701 err_dealloc_vector: 5702 hns3_nic_dealloc_vector_data(priv); 5703 err_put_ring: 5704 hns3_put_ring_config(priv); 5705 5706 return ret; 5707 } 5708 5709 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 5710 { 5711 struct net_device *netdev = handle->kinfo.netdev; 5712 struct hns3_nic_priv *priv = netdev_priv(netdev); 5713 5714 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 5715 netdev_warn(netdev, "already uninitialized\n"); 5716 return 0; 5717 } 5718 5719 hns3_free_rx_cpu_rmap(netdev); 5720 hns3_nic_uninit_irq(priv); 5721 hns3_clear_all_ring(handle, true); 5722 hns3_reset_tx_queue(priv->ae_handle); 5723 5724 hns3_nic_uninit_vector_data(priv); 5725 5726 hns3_nic_dealloc_vector_data(priv); 5727 5728 hns3_uninit_all_ring(priv); 5729 5730 hns3_put_ring_config(priv); 5731 5732 return 0; 5733 } 5734 5735 int hns3_reset_notify(struct hnae3_handle *handle, 5736 enum hnae3_reset_notify_type type) 5737 { 5738 int ret = 0; 5739 5740 switch (type) { 5741 case HNAE3_UP_CLIENT: 5742 ret = hns3_reset_notify_up_enet(handle); 5743 break; 5744 case HNAE3_DOWN_CLIENT: 5745 ret = hns3_reset_notify_down_enet(handle); 5746 break; 5747 case HNAE3_INIT_CLIENT: 5748 ret = hns3_reset_notify_init_enet(handle); 5749 break; 5750 case HNAE3_UNINIT_CLIENT: 5751 ret = hns3_reset_notify_uninit_enet(handle); 5752 break; 5753 default: 5754 break; 5755 } 5756 5757 return ret; 5758 } 5759 5760 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num, 5761 bool rxfh_configured) 5762 { 5763 int ret; 5764 5765 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num, 5766 rxfh_configured); 5767 if (ret) { 5768 dev_err(&handle->pdev->dev, 5769 "Change tqp num(%u) fail.\n", new_tqp_num); 5770 return ret; 5771 } 5772 5773 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT); 5774 if (ret) 5775 return ret; 5776 5777 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT); 5778 if (ret) 5779 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT); 5780 5781 return ret; 5782 } 5783 5784 int hns3_set_channels(struct net_device *netdev, 5785 struct ethtool_channels *ch) 5786 { 5787 struct hnae3_handle *h = hns3_get_handle(netdev); 5788 struct hnae3_knic_private_info *kinfo = &h->kinfo; 5789 bool rxfh_configured = netif_is_rxfh_configured(netdev); 5790 u32 new_tqp_num = ch->combined_count; 5791 u16 org_tqp_num; 5792 int ret; 5793 5794 if (hns3_nic_resetting(netdev)) 5795 return -EBUSY; 5796 5797 if (ch->rx_count || ch->tx_count) 5798 return -EINVAL; 5799 5800 if (kinfo->tc_info.mqprio_active) { 5801 dev_err(&netdev->dev, 5802 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n"); 5803 return -EINVAL; 5804 } 5805 5806 if (new_tqp_num > hns3_get_max_available_channels(h) || 5807 new_tqp_num < 1) { 5808 dev_err(&netdev->dev, 5809 "Change tqps fail, the tqp range is from 1 to %u", 5810 hns3_get_max_available_channels(h)); 5811 return -EINVAL; 5812 } 5813 5814 if (kinfo->rss_size == new_tqp_num) 5815 return 0; 5816 5817 netif_dbg(h, drv, netdev, 5818 "set channels: tqp_num=%u, rxfh=%d\n", 5819 new_tqp_num, rxfh_configured); 5820 5821 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 5822 if (ret) 5823 return ret; 5824 5825 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 5826 if (ret) 5827 return ret; 5828 5829 org_tqp_num = h->kinfo.num_tqps; 5830 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured); 5831 if (ret) { 5832 int ret1; 5833 5834 netdev_warn(netdev, 5835 "Change channels fail, revert to old value\n"); 5836 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured); 5837 if (ret1) { 5838 netdev_err(netdev, 5839 "revert to old channel fail\n"); 5840 return ret1; 5841 } 5842 5843 return ret; 5844 } 5845 5846 return 0; 5847 } 5848 5849 void hns3_external_lb_prepare(struct net_device *ndev, bool if_running) 5850 { 5851 struct hns3_nic_priv *priv = netdev_priv(ndev); 5852 struct hnae3_handle *h = priv->ae_handle; 5853 int i; 5854 5855 if (!if_running) 5856 return; 5857 5858 netif_carrier_off(ndev); 5859 netif_tx_disable(ndev); 5860 5861 for (i = 0; i < priv->vector_num; i++) 5862 hns3_vector_disable(&priv->tqp_vector[i]); 5863 5864 for (i = 0; i < h->kinfo.num_tqps; i++) 5865 hns3_tqp_disable(h->kinfo.tqp[i]); 5866 5867 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 5868 * during reset process, because driver may not be able 5869 * to disable the ring through firmware when downing the netdev. 5870 */ 5871 if (!hns3_nic_resetting(ndev)) 5872 hns3_nic_reset_all_ring(priv->ae_handle); 5873 5874 hns3_reset_tx_queue(priv->ae_handle); 5875 } 5876 5877 void hns3_external_lb_restore(struct net_device *ndev, bool if_running) 5878 { 5879 struct hns3_nic_priv *priv = netdev_priv(ndev); 5880 struct hnae3_handle *h = priv->ae_handle; 5881 int i; 5882 5883 if (!if_running) 5884 return; 5885 5886 hns3_nic_reset_all_ring(priv->ae_handle); 5887 5888 for (i = 0; i < priv->vector_num; i++) 5889 hns3_vector_enable(&priv->tqp_vector[i]); 5890 5891 for (i = 0; i < h->kinfo.num_tqps; i++) 5892 hns3_tqp_enable(h->kinfo.tqp[i]); 5893 5894 netif_tx_wake_all_queues(ndev); 5895 5896 if (h->ae_algo->ops->get_status(h)) 5897 netif_carrier_on(ndev); 5898 } 5899 5900 static const struct hns3_hw_error_info hns3_hw_err[] = { 5901 { .type = HNAE3_PPU_POISON_ERROR, 5902 .msg = "PPU poison" }, 5903 { .type = HNAE3_CMDQ_ECC_ERROR, 5904 .msg = "IMP CMDQ error" }, 5905 { .type = HNAE3_IMP_RD_POISON_ERROR, 5906 .msg = "IMP RD poison" }, 5907 { .type = HNAE3_ROCEE_AXI_RESP_ERROR, 5908 .msg = "ROCEE AXI RESP error" }, 5909 }; 5910 5911 static void hns3_process_hw_error(struct hnae3_handle *handle, 5912 enum hnae3_hw_error_type type) 5913 { 5914 int i; 5915 5916 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) { 5917 if (hns3_hw_err[i].type == type) { 5918 dev_err(&handle->pdev->dev, "Detected %s!\n", 5919 hns3_hw_err[i].msg); 5920 break; 5921 } 5922 } 5923 } 5924 5925 static const struct hnae3_client_ops client_ops = { 5926 .init_instance = hns3_client_init, 5927 .uninit_instance = hns3_client_uninit, 5928 .link_status_change = hns3_link_status_change, 5929 .reset_notify = hns3_reset_notify, 5930 .process_hw_error = hns3_process_hw_error, 5931 }; 5932 5933 /* hns3_init_module - Driver registration routine 5934 * hns3_init_module is the first routine called when the driver is 5935 * loaded. All it does is register with the PCI subsystem. 5936 */ 5937 static int __init hns3_init_module(void) 5938 { 5939 int ret; 5940 5941 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 5942 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 5943 5944 client.type = HNAE3_CLIENT_KNIC; 5945 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s", 5946 hns3_driver_name); 5947 5948 client.ops = &client_ops; 5949 5950 INIT_LIST_HEAD(&client.node); 5951 5952 hns3_dbg_register_debugfs(hns3_driver_name); 5953 5954 ret = hnae3_register_client(&client); 5955 if (ret) 5956 goto err_reg_client; 5957 5958 ret = pci_register_driver(&hns3_driver); 5959 if (ret) 5960 goto err_reg_driver; 5961 5962 return ret; 5963 5964 err_reg_driver: 5965 hnae3_unregister_client(&client); 5966 err_reg_client: 5967 hns3_dbg_unregister_debugfs(); 5968 return ret; 5969 } 5970 module_init(hns3_init_module); 5971 5972 /* hns3_exit_module - Driver exit cleanup routine 5973 * hns3_exit_module is called just before the driver is removed 5974 * from memory. 5975 */ 5976 static void __exit hns3_exit_module(void) 5977 { 5978 pci_unregister_driver(&hns3_driver); 5979 hnae3_unregister_client(&client); 5980 hns3_dbg_unregister_debugfs(); 5981 } 5982 module_exit(hns3_exit_module); 5983 5984 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 5985 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 5986 MODULE_LICENSE("GPL"); 5987 MODULE_ALIAS("pci:hns-nic"); 5988