1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #ifdef CONFIG_RFS_ACCEL 8 #include <linux/cpu_rmap.h> 9 #endif 10 #include <linux/if_vlan.h> 11 #include <linux/ip.h> 12 #include <linux/ipv6.h> 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/aer.h> 16 #include <linux/skbuff.h> 17 #include <linux/sctp.h> 18 #include <linux/vermagic.h> 19 #include <net/gre.h> 20 #include <net/ip6_checksum.h> 21 #include <net/pkt_cls.h> 22 #include <net/tcp.h> 23 #include <net/vxlan.h> 24 25 #include "hnae3.h" 26 #include "hns3_enet.h" 27 28 #define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift))) 29 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE) 30 31 #define hns3_rl_err(fmt, ...) \ 32 do { \ 33 if (net_ratelimit()) \ 34 netdev_err(fmt, ##__VA_ARGS__); \ 35 } while (0) 36 37 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force); 38 static void hns3_remove_hw_addr(struct net_device *netdev); 39 40 static const char hns3_driver_name[] = "hns3"; 41 const char hns3_driver_version[] = VERMAGIC_STRING; 42 static const char hns3_driver_string[] = 43 "Hisilicon Ethernet Network Driver for Hip08 Family"; 44 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 45 static struct hnae3_client client; 46 47 static int debug = -1; 48 module_param(debug, int, 0); 49 MODULE_PARM_DESC(debug, " Network interface message level setting"); 50 51 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 52 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) 53 54 #define HNS3_INNER_VLAN_TAG 1 55 #define HNS3_OUTER_VLAN_TAG 2 56 57 /* hns3_pci_tbl - PCI Device ID Table 58 * 59 * Last entry must be all 0s 60 * 61 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 62 * Class, Class Mask, private data (not used) } 63 */ 64 static const struct pci_device_id hns3_pci_tbl[] = { 65 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 66 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 67 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 68 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 69 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 70 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 71 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 72 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 74 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 75 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 76 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 77 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 79 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 80 /* required last entry */ 81 {0, } 82 }; 83 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 84 85 static irqreturn_t hns3_irq_handle(int irq, void *vector) 86 { 87 struct hns3_enet_tqp_vector *tqp_vector = vector; 88 89 napi_schedule_irqoff(&tqp_vector->napi); 90 91 return IRQ_HANDLED; 92 } 93 94 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 95 { 96 struct hns3_enet_tqp_vector *tqp_vectors; 97 unsigned int i; 98 99 for (i = 0; i < priv->vector_num; i++) { 100 tqp_vectors = &priv->tqp_vector[i]; 101 102 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 103 continue; 104 105 /* clear the affinity mask */ 106 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 107 108 /* release the irq resource */ 109 free_irq(tqp_vectors->vector_irq, tqp_vectors); 110 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 111 } 112 } 113 114 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 115 { 116 struct hns3_enet_tqp_vector *tqp_vectors; 117 int txrx_int_idx = 0; 118 int rx_int_idx = 0; 119 int tx_int_idx = 0; 120 unsigned int i; 121 int ret; 122 123 for (i = 0; i < priv->vector_num; i++) { 124 tqp_vectors = &priv->tqp_vector[i]; 125 126 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 127 continue; 128 129 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 130 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 131 "%s-%s-%d", priv->netdev->name, "TxRx", 132 txrx_int_idx++); 133 txrx_int_idx++; 134 } else if (tqp_vectors->rx_group.ring) { 135 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 136 "%s-%s-%d", priv->netdev->name, "Rx", 137 rx_int_idx++); 138 } else if (tqp_vectors->tx_group.ring) { 139 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 140 "%s-%s-%d", priv->netdev->name, "Tx", 141 tx_int_idx++); 142 } else { 143 /* Skip this unused q_vector */ 144 continue; 145 } 146 147 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 148 149 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 150 tqp_vectors->name, tqp_vectors); 151 if (ret) { 152 netdev_err(priv->netdev, "request irq(%d) fail\n", 153 tqp_vectors->vector_irq); 154 hns3_nic_uninit_irq(priv); 155 return ret; 156 } 157 158 irq_set_affinity_hint(tqp_vectors->vector_irq, 159 &tqp_vectors->affinity_mask); 160 161 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 162 } 163 164 return 0; 165 } 166 167 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 168 u32 mask_en) 169 { 170 writel(mask_en, tqp_vector->mask_addr); 171 } 172 173 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 174 { 175 napi_enable(&tqp_vector->napi); 176 177 /* enable vector */ 178 hns3_mask_vector_irq(tqp_vector, 1); 179 } 180 181 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 182 { 183 /* disable vector */ 184 hns3_mask_vector_irq(tqp_vector, 0); 185 186 disable_irq(tqp_vector->vector_irq); 187 napi_disable(&tqp_vector->napi); 188 } 189 190 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 191 u32 rl_value) 192 { 193 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 194 195 /* this defines the configuration for RL (Interrupt Rate Limiter). 196 * Rl defines rate of interrupts i.e. number of interrupts-per-second 197 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 198 */ 199 200 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable && 201 !tqp_vector->rx_group.coal.gl_adapt_enable) 202 /* According to the hardware, the range of rl_reg is 203 * 0-59 and the unit is 4. 204 */ 205 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 206 207 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 208 } 209 210 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 211 u32 gl_value) 212 { 213 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value); 214 215 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 216 } 217 218 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 219 u32 gl_value) 220 { 221 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value); 222 223 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 224 } 225 226 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector, 227 struct hns3_nic_priv *priv) 228 { 229 /* initialize the configuration for interrupt coalescing. 230 * 1. GL (Interrupt Gap Limiter) 231 * 2. RL (Interrupt Rate Limiter) 232 * 233 * Default: enable interrupt coalescing self-adaptive and GL 234 */ 235 tqp_vector->tx_group.coal.gl_adapt_enable = 1; 236 tqp_vector->rx_group.coal.gl_adapt_enable = 1; 237 238 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K; 239 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K; 240 241 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW; 242 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW; 243 } 244 245 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 246 struct hns3_nic_priv *priv) 247 { 248 struct hnae3_handle *h = priv->ae_handle; 249 250 hns3_set_vector_coalesce_tx_gl(tqp_vector, 251 tqp_vector->tx_group.coal.int_gl); 252 hns3_set_vector_coalesce_rx_gl(tqp_vector, 253 tqp_vector->rx_group.coal.int_gl); 254 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 255 } 256 257 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 258 { 259 struct hnae3_handle *h = hns3_get_handle(netdev); 260 struct hnae3_knic_private_info *kinfo = &h->kinfo; 261 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc; 262 int i, ret; 263 264 if (kinfo->num_tc <= 1) { 265 netdev_reset_tc(netdev); 266 } else { 267 ret = netdev_set_num_tc(netdev, kinfo->num_tc); 268 if (ret) { 269 netdev_err(netdev, 270 "netdev_set_num_tc fail, ret=%d!\n", ret); 271 return ret; 272 } 273 274 for (i = 0; i < HNAE3_MAX_TC; i++) { 275 if (!kinfo->tc_info[i].enable) 276 continue; 277 278 netdev_set_tc_queue(netdev, 279 kinfo->tc_info[i].tc, 280 kinfo->tc_info[i].tqp_count, 281 kinfo->tc_info[i].tqp_offset); 282 } 283 } 284 285 ret = netif_set_real_num_tx_queues(netdev, queue_size); 286 if (ret) { 287 netdev_err(netdev, 288 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret); 289 return ret; 290 } 291 292 ret = netif_set_real_num_rx_queues(netdev, queue_size); 293 if (ret) { 294 netdev_err(netdev, 295 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 296 return ret; 297 } 298 299 return 0; 300 } 301 302 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 303 { 304 u16 alloc_tqps, max_rss_size, rss_size; 305 306 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 307 rss_size = alloc_tqps / h->kinfo.num_tc; 308 309 return min_t(u16, rss_size, max_rss_size); 310 } 311 312 static void hns3_tqp_enable(struct hnae3_queue *tqp) 313 { 314 u32 rcb_reg; 315 316 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 317 rcb_reg |= BIT(HNS3_RING_EN_B); 318 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 319 } 320 321 static void hns3_tqp_disable(struct hnae3_queue *tqp) 322 { 323 u32 rcb_reg; 324 325 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 326 rcb_reg &= ~BIT(HNS3_RING_EN_B); 327 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 328 } 329 330 static void hns3_free_rx_cpu_rmap(struct net_device *netdev) 331 { 332 #ifdef CONFIG_RFS_ACCEL 333 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 334 netdev->rx_cpu_rmap = NULL; 335 #endif 336 } 337 338 static int hns3_set_rx_cpu_rmap(struct net_device *netdev) 339 { 340 #ifdef CONFIG_RFS_ACCEL 341 struct hns3_nic_priv *priv = netdev_priv(netdev); 342 struct hns3_enet_tqp_vector *tqp_vector; 343 int i, ret; 344 345 if (!netdev->rx_cpu_rmap) { 346 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num); 347 if (!netdev->rx_cpu_rmap) 348 return -ENOMEM; 349 } 350 351 for (i = 0; i < priv->vector_num; i++) { 352 tqp_vector = &priv->tqp_vector[i]; 353 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap, 354 tqp_vector->vector_irq); 355 if (ret) { 356 hns3_free_rx_cpu_rmap(netdev); 357 return ret; 358 } 359 } 360 #endif 361 return 0; 362 } 363 364 static int hns3_nic_net_up(struct net_device *netdev) 365 { 366 struct hns3_nic_priv *priv = netdev_priv(netdev); 367 struct hnae3_handle *h = priv->ae_handle; 368 int i, j; 369 int ret; 370 371 ret = hns3_nic_reset_all_ring(h); 372 if (ret) 373 return ret; 374 375 /* the device can work without cpu rmap, only aRFS needs it */ 376 ret = hns3_set_rx_cpu_rmap(netdev); 377 if (ret) 378 netdev_warn(netdev, "set rx cpu rmap fail, ret=%d!\n", ret); 379 380 /* get irq resource for all vectors */ 381 ret = hns3_nic_init_irq(priv); 382 if (ret) { 383 netdev_err(netdev, "init irq failed! ret=%d\n", ret); 384 goto free_rmap; 385 } 386 387 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 388 389 /* enable the vectors */ 390 for (i = 0; i < priv->vector_num; i++) 391 hns3_vector_enable(&priv->tqp_vector[i]); 392 393 /* enable rcb */ 394 for (j = 0; j < h->kinfo.num_tqps; j++) 395 hns3_tqp_enable(h->kinfo.tqp[j]); 396 397 /* start the ae_dev */ 398 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 399 if (ret) 400 goto out_start_err; 401 402 return 0; 403 404 out_start_err: 405 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 406 while (j--) 407 hns3_tqp_disable(h->kinfo.tqp[j]); 408 409 for (j = i - 1; j >= 0; j--) 410 hns3_vector_disable(&priv->tqp_vector[j]); 411 412 hns3_nic_uninit_irq(priv); 413 free_rmap: 414 hns3_free_rx_cpu_rmap(netdev); 415 return ret; 416 } 417 418 static void hns3_config_xps(struct hns3_nic_priv *priv) 419 { 420 int i; 421 422 for (i = 0; i < priv->vector_num; i++) { 423 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 424 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 425 426 while (ring) { 427 int ret; 428 429 ret = netif_set_xps_queue(priv->netdev, 430 &tqp_vector->affinity_mask, 431 ring->tqp->tqp_index); 432 if (ret) 433 netdev_warn(priv->netdev, 434 "set xps queue failed: %d", ret); 435 436 ring = ring->next; 437 } 438 } 439 } 440 441 static int hns3_nic_net_open(struct net_device *netdev) 442 { 443 struct hns3_nic_priv *priv = netdev_priv(netdev); 444 struct hnae3_handle *h = hns3_get_handle(netdev); 445 struct hnae3_knic_private_info *kinfo; 446 int i, ret; 447 448 if (hns3_nic_resetting(netdev)) 449 return -EBUSY; 450 451 netif_carrier_off(netdev); 452 453 ret = hns3_nic_set_real_num_queue(netdev); 454 if (ret) 455 return ret; 456 457 ret = hns3_nic_net_up(netdev); 458 if (ret) { 459 netdev_err(netdev, "net up fail, ret=%d!\n", ret); 460 return ret; 461 } 462 463 kinfo = &h->kinfo; 464 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 465 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]); 466 467 if (h->ae_algo->ops->set_timer_task) 468 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 469 470 hns3_config_xps(priv); 471 472 netif_dbg(h, drv, netdev, "net open\n"); 473 474 return 0; 475 } 476 477 static void hns3_reset_tx_queue(struct hnae3_handle *h) 478 { 479 struct net_device *ndev = h->kinfo.netdev; 480 struct hns3_nic_priv *priv = netdev_priv(ndev); 481 struct netdev_queue *dev_queue; 482 u32 i; 483 484 for (i = 0; i < h->kinfo.num_tqps; i++) { 485 dev_queue = netdev_get_tx_queue(ndev, 486 priv->ring[i].queue_index); 487 netdev_tx_reset_queue(dev_queue); 488 } 489 } 490 491 static void hns3_nic_net_down(struct net_device *netdev) 492 { 493 struct hns3_nic_priv *priv = netdev_priv(netdev); 494 struct hnae3_handle *h = hns3_get_handle(netdev); 495 const struct hnae3_ae_ops *ops; 496 int i; 497 498 /* disable vectors */ 499 for (i = 0; i < priv->vector_num; i++) 500 hns3_vector_disable(&priv->tqp_vector[i]); 501 502 /* disable rcb */ 503 for (i = 0; i < h->kinfo.num_tqps; i++) 504 hns3_tqp_disable(h->kinfo.tqp[i]); 505 506 /* stop ae_dev */ 507 ops = priv->ae_handle->ae_algo->ops; 508 if (ops->stop) 509 ops->stop(priv->ae_handle); 510 511 hns3_free_rx_cpu_rmap(netdev); 512 513 /* free irq resources */ 514 hns3_nic_uninit_irq(priv); 515 516 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 517 * during reset process, because driver may not be able 518 * to disable the ring through firmware when downing the netdev. 519 */ 520 if (!hns3_nic_resetting(netdev)) 521 hns3_clear_all_ring(priv->ae_handle, false); 522 523 hns3_reset_tx_queue(priv->ae_handle); 524 } 525 526 static int hns3_nic_net_stop(struct net_device *netdev) 527 { 528 struct hns3_nic_priv *priv = netdev_priv(netdev); 529 struct hnae3_handle *h = hns3_get_handle(netdev); 530 531 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 532 return 0; 533 534 netif_dbg(h, drv, netdev, "net stop\n"); 535 536 if (h->ae_algo->ops->set_timer_task) 537 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 538 539 netif_tx_stop_all_queues(netdev); 540 netif_carrier_off(netdev); 541 542 hns3_nic_net_down(netdev); 543 544 return 0; 545 } 546 547 static int hns3_nic_uc_sync(struct net_device *netdev, 548 const unsigned char *addr) 549 { 550 struct hnae3_handle *h = hns3_get_handle(netdev); 551 552 if (h->ae_algo->ops->add_uc_addr) 553 return h->ae_algo->ops->add_uc_addr(h, addr); 554 555 return 0; 556 } 557 558 static int hns3_nic_uc_unsync(struct net_device *netdev, 559 const unsigned char *addr) 560 { 561 struct hnae3_handle *h = hns3_get_handle(netdev); 562 563 if (h->ae_algo->ops->rm_uc_addr) 564 return h->ae_algo->ops->rm_uc_addr(h, addr); 565 566 return 0; 567 } 568 569 static int hns3_nic_mc_sync(struct net_device *netdev, 570 const unsigned char *addr) 571 { 572 struct hnae3_handle *h = hns3_get_handle(netdev); 573 574 if (h->ae_algo->ops->add_mc_addr) 575 return h->ae_algo->ops->add_mc_addr(h, addr); 576 577 return 0; 578 } 579 580 static int hns3_nic_mc_unsync(struct net_device *netdev, 581 const unsigned char *addr) 582 { 583 struct hnae3_handle *h = hns3_get_handle(netdev); 584 585 if (h->ae_algo->ops->rm_mc_addr) 586 return h->ae_algo->ops->rm_mc_addr(h, addr); 587 588 return 0; 589 } 590 591 static u8 hns3_get_netdev_flags(struct net_device *netdev) 592 { 593 u8 flags = 0; 594 595 if (netdev->flags & IFF_PROMISC) { 596 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 597 } else { 598 flags |= HNAE3_VLAN_FLTR; 599 if (netdev->flags & IFF_ALLMULTI) 600 flags |= HNAE3_USER_MPE; 601 } 602 603 return flags; 604 } 605 606 static void hns3_nic_set_rx_mode(struct net_device *netdev) 607 { 608 struct hnae3_handle *h = hns3_get_handle(netdev); 609 u8 new_flags; 610 int ret; 611 612 new_flags = hns3_get_netdev_flags(netdev); 613 614 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 615 if (ret) { 616 netdev_err(netdev, "sync uc address fail\n"); 617 if (ret == -ENOSPC) 618 new_flags |= HNAE3_OVERFLOW_UPE; 619 } 620 621 if (netdev->flags & IFF_MULTICAST) { 622 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync, 623 hns3_nic_mc_unsync); 624 if (ret) { 625 netdev_err(netdev, "sync mc address fail\n"); 626 if (ret == -ENOSPC) 627 new_flags |= HNAE3_OVERFLOW_MPE; 628 } 629 } 630 631 /* User mode Promisc mode enable and vlan filtering is disabled to 632 * let all packets in. MAC-VLAN Table overflow Promisc enabled and 633 * vlan fitering is enabled 634 */ 635 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR); 636 h->netdev_flags = new_flags; 637 hns3_update_promisc_mode(netdev, new_flags); 638 } 639 640 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags) 641 { 642 struct hns3_nic_priv *priv = netdev_priv(netdev); 643 struct hnae3_handle *h = priv->ae_handle; 644 645 if (h->ae_algo->ops->set_promisc_mode) { 646 return h->ae_algo->ops->set_promisc_mode(h, 647 promisc_flags & HNAE3_UPE, 648 promisc_flags & HNAE3_MPE); 649 } 650 651 return 0; 652 } 653 654 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable) 655 { 656 struct hns3_nic_priv *priv = netdev_priv(netdev); 657 struct hnae3_handle *h = priv->ae_handle; 658 bool last_state; 659 660 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) { 661 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false; 662 if (enable != last_state) { 663 netdev_info(netdev, 664 "%s vlan filter\n", 665 enable ? "enable" : "disable"); 666 h->ae_algo->ops->enable_vlan_filter(h, enable); 667 } 668 } 669 } 670 671 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen, 672 u16 *mss, u32 *type_cs_vlan_tso) 673 { 674 u32 l4_offset, hdr_len; 675 union l3_hdr_info l3; 676 union l4_hdr_info l4; 677 u32 l4_paylen; 678 int ret; 679 680 if (!skb_is_gso(skb)) 681 return 0; 682 683 ret = skb_cow_head(skb, 0); 684 if (unlikely(ret < 0)) 685 return ret; 686 687 l3.hdr = skb_network_header(skb); 688 l4.hdr = skb_transport_header(skb); 689 690 /* Software should clear the IPv4's checksum field when tso is 691 * needed. 692 */ 693 if (l3.v4->version == 4) 694 l3.v4->check = 0; 695 696 /* tunnel packet */ 697 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 698 SKB_GSO_GRE_CSUM | 699 SKB_GSO_UDP_TUNNEL | 700 SKB_GSO_UDP_TUNNEL_CSUM)) { 701 if ((!(skb_shinfo(skb)->gso_type & 702 SKB_GSO_PARTIAL)) && 703 (skb_shinfo(skb)->gso_type & 704 SKB_GSO_UDP_TUNNEL_CSUM)) { 705 /* Software should clear the udp's checksum 706 * field when tso is needed. 707 */ 708 l4.udp->check = 0; 709 } 710 /* reset l3&l4 pointers from outer to inner headers */ 711 l3.hdr = skb_inner_network_header(skb); 712 l4.hdr = skb_inner_transport_header(skb); 713 714 /* Software should clear the IPv4's checksum field when 715 * tso is needed. 716 */ 717 if (l3.v4->version == 4) 718 l3.v4->check = 0; 719 } 720 721 /* normal or tunnel packet */ 722 l4_offset = l4.hdr - skb->data; 723 hdr_len = (l4.tcp->doff << 2) + l4_offset; 724 725 /* remove payload length from inner pseudo checksum when tso */ 726 l4_paylen = skb->len - l4_offset; 727 csum_replace_by_diff(&l4.tcp->check, 728 (__force __wsum)htonl(l4_paylen)); 729 730 /* find the txbd field values */ 731 *paylen = skb->len - hdr_len; 732 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 733 734 /* get MSS for TSO */ 735 *mss = skb_shinfo(skb)->gso_size; 736 737 return 0; 738 } 739 740 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 741 u8 *il4_proto) 742 { 743 union l3_hdr_info l3; 744 unsigned char *l4_hdr; 745 unsigned char *exthdr; 746 u8 l4_proto_tmp; 747 __be16 frag_off; 748 749 /* find outer header point */ 750 l3.hdr = skb_network_header(skb); 751 l4_hdr = skb_transport_header(skb); 752 753 if (skb->protocol == htons(ETH_P_IPV6)) { 754 exthdr = l3.hdr + sizeof(*l3.v6); 755 l4_proto_tmp = l3.v6->nexthdr; 756 if (l4_hdr != exthdr) 757 ipv6_skip_exthdr(skb, exthdr - skb->data, 758 &l4_proto_tmp, &frag_off); 759 } else if (skb->protocol == htons(ETH_P_IP)) { 760 l4_proto_tmp = l3.v4->protocol; 761 } else { 762 return -EINVAL; 763 } 764 765 *ol4_proto = l4_proto_tmp; 766 767 /* tunnel packet */ 768 if (!skb->encapsulation) { 769 *il4_proto = 0; 770 return 0; 771 } 772 773 /* find inner header point */ 774 l3.hdr = skb_inner_network_header(skb); 775 l4_hdr = skb_inner_transport_header(skb); 776 777 if (l3.v6->version == 6) { 778 exthdr = l3.hdr + sizeof(*l3.v6); 779 l4_proto_tmp = l3.v6->nexthdr; 780 if (l4_hdr != exthdr) 781 ipv6_skip_exthdr(skb, exthdr - skb->data, 782 &l4_proto_tmp, &frag_off); 783 } else if (l3.v4->version == 4) { 784 l4_proto_tmp = l3.v4->protocol; 785 } 786 787 *il4_proto = l4_proto_tmp; 788 789 return 0; 790 } 791 792 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 793 * and it is udp packet, which has a dest port as the IANA assigned. 794 * the hardware is expected to do the checksum offload, but the 795 * hardware will not do the checksum offload when udp dest port is 796 * 4789. 797 */ 798 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 799 { 800 union l4_hdr_info l4; 801 802 l4.hdr = skb_transport_header(skb); 803 804 if (!(!skb->encapsulation && 805 l4.udp->dest == htons(IANA_VXLAN_UDP_PORT))) 806 return false; 807 808 skb_checksum_help(skb); 809 810 return true; 811 } 812 813 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 814 u32 *ol_type_vlan_len_msec) 815 { 816 u32 l2_len, l3_len, l4_len; 817 unsigned char *il2_hdr; 818 union l3_hdr_info l3; 819 union l4_hdr_info l4; 820 821 l3.hdr = skb_network_header(skb); 822 l4.hdr = skb_transport_header(skb); 823 824 /* compute OL2 header size, defined in 2 Bytes */ 825 l2_len = l3.hdr - skb->data; 826 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1); 827 828 /* compute OL3 header size, defined in 4 Bytes */ 829 l3_len = l4.hdr - l3.hdr; 830 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2); 831 832 il2_hdr = skb_inner_mac_header(skb); 833 /* compute OL4 header size, defined in 4 Bytes */ 834 l4_len = il2_hdr - l4.hdr; 835 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2); 836 837 /* define outer network header type */ 838 if (skb->protocol == htons(ETH_P_IP)) { 839 if (skb_is_gso(skb)) 840 hns3_set_field(*ol_type_vlan_len_msec, 841 HNS3_TXD_OL3T_S, 842 HNS3_OL3T_IPV4_CSUM); 843 else 844 hns3_set_field(*ol_type_vlan_len_msec, 845 HNS3_TXD_OL3T_S, 846 HNS3_OL3T_IPV4_NO_CSUM); 847 848 } else if (skb->protocol == htons(ETH_P_IPV6)) { 849 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 850 HNS3_OL3T_IPV6); 851 } 852 853 if (ol4_proto == IPPROTO_UDP) 854 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 855 HNS3_TUN_MAC_IN_UDP); 856 else if (ol4_proto == IPPROTO_GRE) 857 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 858 HNS3_TUN_NVGRE); 859 } 860 861 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 862 u8 il4_proto, u32 *type_cs_vlan_tso, 863 u32 *ol_type_vlan_len_msec) 864 { 865 unsigned char *l2_hdr = skb->data; 866 u32 l4_proto = ol4_proto; 867 union l4_hdr_info l4; 868 union l3_hdr_info l3; 869 u32 l2_len, l3_len; 870 871 l4.hdr = skb_transport_header(skb); 872 l3.hdr = skb_network_header(skb); 873 874 /* handle encapsulation skb */ 875 if (skb->encapsulation) { 876 /* If this is a not UDP/GRE encapsulation skb */ 877 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) { 878 /* drop the skb tunnel packet if hardware don't support, 879 * because hardware can't calculate csum when TSO. 880 */ 881 if (skb_is_gso(skb)) 882 return -EDOM; 883 884 /* the stack computes the IP header already, 885 * driver calculate l4 checksum when not TSO. 886 */ 887 skb_checksum_help(skb); 888 return 0; 889 } 890 891 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec); 892 893 /* switch to inner header */ 894 l2_hdr = skb_inner_mac_header(skb); 895 l3.hdr = skb_inner_network_header(skb); 896 l4.hdr = skb_inner_transport_header(skb); 897 l4_proto = il4_proto; 898 } 899 900 if (l3.v4->version == 4) { 901 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 902 HNS3_L3T_IPV4); 903 904 /* the stack computes the IP header already, the only time we 905 * need the hardware to recompute it is in the case of TSO. 906 */ 907 if (skb_is_gso(skb)) 908 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 909 } else if (l3.v6->version == 6) { 910 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 911 HNS3_L3T_IPV6); 912 } 913 914 /* compute inner(/normal) L2 header size, defined in 2 Bytes */ 915 l2_len = l3.hdr - l2_hdr; 916 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 917 918 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 919 l3_len = l4.hdr - l3.hdr; 920 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 921 922 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 923 switch (l4_proto) { 924 case IPPROTO_TCP: 925 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 926 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 927 HNS3_L4T_TCP); 928 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 929 l4.tcp->doff); 930 break; 931 case IPPROTO_UDP: 932 if (hns3_tunnel_csum_bug(skb)) 933 break; 934 935 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 936 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 937 HNS3_L4T_UDP); 938 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 939 (sizeof(struct udphdr) >> 2)); 940 break; 941 case IPPROTO_SCTP: 942 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 943 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 944 HNS3_L4T_SCTP); 945 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 946 (sizeof(struct sctphdr) >> 2)); 947 break; 948 default: 949 /* drop the skb tunnel packet if hardware don't support, 950 * because hardware can't calculate csum when TSO. 951 */ 952 if (skb_is_gso(skb)) 953 return -EDOM; 954 955 /* the stack computes the IP header already, 956 * driver calculate l4 checksum when not TSO. 957 */ 958 skb_checksum_help(skb); 959 return 0; 960 } 961 962 return 0; 963 } 964 965 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring, 966 struct sk_buff *skb) 967 { 968 struct hnae3_handle *handle = tx_ring->tqp->handle; 969 struct vlan_ethhdr *vhdr; 970 int rc; 971 972 if (!(skb->protocol == htons(ETH_P_8021Q) || 973 skb_vlan_tag_present(skb))) 974 return 0; 975 976 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN 977 * header is allowed in skb, otherwise it will cause RAS error. 978 */ 979 if (unlikely(skb_vlan_tagged_multi(skb) && 980 handle->port_base_vlan_state == 981 HNAE3_PORT_BASE_VLAN_ENABLE)) 982 return -EINVAL; 983 984 if (skb->protocol == htons(ETH_P_8021Q) && 985 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 986 /* When HW VLAN acceleration is turned off, and the stack 987 * sets the protocol to 802.1q, the driver just need to 988 * set the protocol to the encapsulated ethertype. 989 */ 990 skb->protocol = vlan_get_protocol(skb); 991 return 0; 992 } 993 994 if (skb_vlan_tag_present(skb)) { 995 /* Based on hw strategy, use out_vtag in two layer tag case, 996 * and use inner_vtag in one tag case. 997 */ 998 if (skb->protocol == htons(ETH_P_8021Q) && 999 handle->port_base_vlan_state == 1000 HNAE3_PORT_BASE_VLAN_DISABLE) 1001 rc = HNS3_OUTER_VLAN_TAG; 1002 else 1003 rc = HNS3_INNER_VLAN_TAG; 1004 1005 skb->protocol = vlan_get_protocol(skb); 1006 return rc; 1007 } 1008 1009 rc = skb_cow_head(skb, 0); 1010 if (unlikely(rc < 0)) 1011 return rc; 1012 1013 vhdr = (struct vlan_ethhdr *)skb->data; 1014 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT) 1015 & VLAN_PRIO_MASK); 1016 1017 skb->protocol = vlan_get_protocol(skb); 1018 return 0; 1019 } 1020 1021 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring, 1022 struct sk_buff *skb, struct hns3_desc *desc) 1023 { 1024 u32 ol_type_vlan_len_msec = 0; 1025 u32 type_cs_vlan_tso = 0; 1026 u32 paylen = skb->len; 1027 u16 inner_vtag = 0; 1028 u16 out_vtag = 0; 1029 u16 mss = 0; 1030 int ret; 1031 1032 ret = hns3_handle_vtags(ring, skb); 1033 if (unlikely(ret < 0)) { 1034 u64_stats_update_begin(&ring->syncp); 1035 ring->stats.tx_vlan_err++; 1036 u64_stats_update_end(&ring->syncp); 1037 return ret; 1038 } else if (ret == HNS3_INNER_VLAN_TAG) { 1039 inner_vtag = skb_vlan_tag_get(skb); 1040 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1041 VLAN_PRIO_MASK; 1042 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1); 1043 } else if (ret == HNS3_OUTER_VLAN_TAG) { 1044 out_vtag = skb_vlan_tag_get(skb); 1045 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1046 VLAN_PRIO_MASK; 1047 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B, 1048 1); 1049 } 1050 1051 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1052 u8 ol4_proto, il4_proto; 1053 1054 skb_reset_mac_len(skb); 1055 1056 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1057 if (unlikely(ret < 0)) { 1058 u64_stats_update_begin(&ring->syncp); 1059 ring->stats.tx_l4_proto_err++; 1060 u64_stats_update_end(&ring->syncp); 1061 return ret; 1062 } 1063 1064 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto, 1065 &type_cs_vlan_tso, 1066 &ol_type_vlan_len_msec); 1067 if (unlikely(ret < 0)) { 1068 u64_stats_update_begin(&ring->syncp); 1069 ring->stats.tx_l2l3l4_err++; 1070 u64_stats_update_end(&ring->syncp); 1071 return ret; 1072 } 1073 1074 ret = hns3_set_tso(skb, &paylen, &mss, 1075 &type_cs_vlan_tso); 1076 if (unlikely(ret < 0)) { 1077 u64_stats_update_begin(&ring->syncp); 1078 ring->stats.tx_tso_err++; 1079 u64_stats_update_end(&ring->syncp); 1080 return ret; 1081 } 1082 } 1083 1084 /* Set txbd */ 1085 desc->tx.ol_type_vlan_len_msec = 1086 cpu_to_le32(ol_type_vlan_len_msec); 1087 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso); 1088 desc->tx.paylen = cpu_to_le32(paylen); 1089 desc->tx.mss = cpu_to_le16(mss); 1090 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1091 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1092 1093 return 0; 1094 } 1095 1096 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 1097 unsigned int size, enum hns_desc_type type) 1098 { 1099 #define HNS3_LIKELY_BD_NUM 1 1100 1101 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1102 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1103 struct device *dev = ring_to_dev(ring); 1104 skb_frag_t *frag; 1105 unsigned int frag_buf_num; 1106 int k, sizeoflast; 1107 dma_addr_t dma; 1108 1109 if (type == DESC_TYPE_SKB) { 1110 struct sk_buff *skb = (struct sk_buff *)priv; 1111 int ret; 1112 1113 ret = hns3_fill_skb_desc(ring, skb, desc); 1114 if (unlikely(ret < 0)) 1115 return ret; 1116 1117 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1118 } else { 1119 frag = (skb_frag_t *)priv; 1120 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1121 } 1122 1123 if (unlikely(dma_mapping_error(dev, dma))) { 1124 u64_stats_update_begin(&ring->syncp); 1125 ring->stats.sw_err_cnt++; 1126 u64_stats_update_end(&ring->syncp); 1127 return -ENOMEM; 1128 } 1129 1130 desc_cb->length = size; 1131 1132 if (likely(size <= HNS3_MAX_BD_SIZE)) { 1133 desc_cb->priv = priv; 1134 desc_cb->dma = dma; 1135 desc_cb->type = type; 1136 desc->addr = cpu_to_le64(dma); 1137 desc->tx.send_size = cpu_to_le16(size); 1138 desc->tx.bdtp_fe_sc_vld_ra_ri = 1139 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1140 1141 ring_ptr_move_fw(ring, next_to_use); 1142 return HNS3_LIKELY_BD_NUM; 1143 } 1144 1145 frag_buf_num = hns3_tx_bd_count(size); 1146 sizeoflast = size & HNS3_TX_LAST_SIZE_M; 1147 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1148 1149 /* When frag size is bigger than hardware limit, split this frag */ 1150 for (k = 0; k < frag_buf_num; k++) { 1151 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */ 1152 desc_cb->priv = priv; 1153 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k; 1154 desc_cb->type = (type == DESC_TYPE_SKB && !k) ? 1155 DESC_TYPE_SKB : DESC_TYPE_PAGE; 1156 1157 /* now, fill the descriptor */ 1158 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1159 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1160 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1161 desc->tx.bdtp_fe_sc_vld_ra_ri = 1162 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1163 1164 /* move ring pointer to next */ 1165 ring_ptr_move_fw(ring, next_to_use); 1166 1167 desc_cb = &ring->desc_cb[ring->next_to_use]; 1168 desc = &ring->desc[ring->next_to_use]; 1169 } 1170 1171 return frag_buf_num; 1172 } 1173 1174 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1175 unsigned int bd_num) 1176 { 1177 unsigned int size; 1178 int i; 1179 1180 size = skb_headlen(skb); 1181 while (size > HNS3_MAX_BD_SIZE) { 1182 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1183 size -= HNS3_MAX_BD_SIZE; 1184 1185 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1186 return bd_num; 1187 } 1188 1189 if (size) { 1190 bd_size[bd_num++] = size; 1191 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1192 return bd_num; 1193 } 1194 1195 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1196 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1197 size = skb_frag_size(frag); 1198 if (!size) 1199 continue; 1200 1201 while (size > HNS3_MAX_BD_SIZE) { 1202 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1203 size -= HNS3_MAX_BD_SIZE; 1204 1205 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1206 return bd_num; 1207 } 1208 1209 bd_size[bd_num++] = size; 1210 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1211 return bd_num; 1212 } 1213 1214 return bd_num; 1215 } 1216 1217 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size) 1218 { 1219 struct sk_buff *frag_skb; 1220 unsigned int bd_num = 0; 1221 1222 /* If the total len is within the max bd limit */ 1223 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !skb_has_frag_list(skb) && 1224 skb_shinfo(skb)->nr_frags < HNS3_MAX_NON_TSO_BD_NUM)) 1225 return skb_shinfo(skb)->nr_frags + 1U; 1226 1227 /* The below case will always be linearized, return 1228 * HNS3_MAX_BD_NUM_TSO + 1U to make sure it is linearized. 1229 */ 1230 if (unlikely(skb->len > HNS3_MAX_TSO_SIZE || 1231 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE))) 1232 return HNS3_MAX_TSO_BD_NUM + 1U; 1233 1234 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num); 1235 1236 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM) 1237 return bd_num; 1238 1239 skb_walk_frags(skb, frag_skb) { 1240 bd_num = hns3_skb_bd_num(frag_skb, bd_size, bd_num); 1241 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1242 return bd_num; 1243 } 1244 1245 return bd_num; 1246 } 1247 1248 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb) 1249 { 1250 if (!skb->encapsulation) 1251 return skb_transport_offset(skb) + tcp_hdrlen(skb); 1252 1253 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb); 1254 } 1255 1256 /* HW need every continuous 8 buffer data to be larger than MSS, 1257 * we simplify it by ensuring skb_headlen + the first continuous 1258 * 7 frags to to be larger than gso header len + mss, and the remaining 1259 * continuous 7 frags to be larger than MSS except the last 7 frags. 1260 */ 1261 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size, 1262 unsigned int bd_num) 1263 { 1264 unsigned int tot_len = 0; 1265 int i; 1266 1267 for (i = 0; i < HNS3_MAX_NON_TSO_BD_NUM - 1U; i++) 1268 tot_len += bd_size[i]; 1269 1270 /* ensure the first 8 frags is greater than mss + header */ 1271 if (tot_len + bd_size[HNS3_MAX_NON_TSO_BD_NUM - 1U] < 1272 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb)) 1273 return true; 1274 1275 /* ensure every continuous 7 buffer is greater than mss 1276 * except the last one. 1277 */ 1278 for (i = 0; i < bd_num - HNS3_MAX_NON_TSO_BD_NUM; i++) { 1279 tot_len -= bd_size[i]; 1280 tot_len += bd_size[i + HNS3_MAX_NON_TSO_BD_NUM - 1U]; 1281 1282 if (tot_len < skb_shinfo(skb)->gso_size) 1283 return true; 1284 } 1285 1286 return false; 1287 } 1288 1289 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring, 1290 struct net_device *netdev, 1291 struct sk_buff *skb) 1292 { 1293 struct hns3_nic_priv *priv = netdev_priv(netdev); 1294 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U]; 1295 unsigned int bd_num; 1296 1297 bd_num = hns3_tx_bd_num(skb, bd_size); 1298 if (unlikely(bd_num > HNS3_MAX_NON_TSO_BD_NUM)) { 1299 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) && 1300 !hns3_skb_need_linearized(skb, bd_size, bd_num)) 1301 goto out; 1302 1303 if (__skb_linearize(skb)) 1304 return -ENOMEM; 1305 1306 bd_num = hns3_tx_bd_count(skb->len); 1307 if ((skb_is_gso(skb) && bd_num > HNS3_MAX_TSO_BD_NUM) || 1308 (!skb_is_gso(skb) && 1309 bd_num > HNS3_MAX_NON_TSO_BD_NUM)) 1310 return -ENOMEM; 1311 1312 u64_stats_update_begin(&ring->syncp); 1313 ring->stats.tx_copy++; 1314 u64_stats_update_end(&ring->syncp); 1315 } 1316 1317 out: 1318 if (likely(ring_space(ring) >= bd_num)) 1319 return bd_num; 1320 1321 netif_stop_subqueue(netdev, ring->queue_index); 1322 smp_mb(); /* Memory barrier before checking ring_space */ 1323 1324 /* Start queue in case hns3_clean_tx_ring has just made room 1325 * available and has not seen the queue stopped state performed 1326 * by netif_stop_subqueue above. 1327 */ 1328 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) && 1329 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 1330 netif_start_subqueue(netdev, ring->queue_index); 1331 return bd_num; 1332 } 1333 1334 return -EBUSY; 1335 } 1336 1337 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1338 { 1339 struct device *dev = ring_to_dev(ring); 1340 unsigned int i; 1341 1342 for (i = 0; i < ring->desc_num; i++) { 1343 /* check if this is where we started */ 1344 if (ring->next_to_use == next_to_use_orig) 1345 break; 1346 1347 /* rollback one */ 1348 ring_ptr_move_bw(ring, next_to_use); 1349 1350 /* unmap the descriptor dma address */ 1351 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB) 1352 dma_unmap_single(dev, 1353 ring->desc_cb[ring->next_to_use].dma, 1354 ring->desc_cb[ring->next_to_use].length, 1355 DMA_TO_DEVICE); 1356 else if (ring->desc_cb[ring->next_to_use].length) 1357 dma_unmap_page(dev, 1358 ring->desc_cb[ring->next_to_use].dma, 1359 ring->desc_cb[ring->next_to_use].length, 1360 DMA_TO_DEVICE); 1361 1362 ring->desc_cb[ring->next_to_use].length = 0; 1363 ring->desc_cb[ring->next_to_use].dma = 0; 1364 } 1365 } 1366 1367 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring, 1368 struct sk_buff *skb, enum hns_desc_type type) 1369 { 1370 unsigned int size = skb_headlen(skb); 1371 int i, ret, bd_num = 0; 1372 1373 if (size) { 1374 ret = hns3_fill_desc(ring, skb, size, type); 1375 if (unlikely(ret < 0)) 1376 return ret; 1377 1378 bd_num += ret; 1379 } 1380 1381 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1382 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1383 1384 size = skb_frag_size(frag); 1385 if (!size) 1386 continue; 1387 1388 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE); 1389 if (unlikely(ret < 0)) 1390 return ret; 1391 1392 bd_num += ret; 1393 } 1394 1395 return bd_num; 1396 } 1397 1398 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1399 { 1400 struct hns3_nic_priv *priv = netdev_priv(netdev); 1401 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping]; 1402 struct netdev_queue *dev_queue; 1403 int pre_ntu, next_to_use_head; 1404 struct sk_buff *frag_skb; 1405 int bd_num = 0; 1406 int ret; 1407 1408 /* Prefetch the data used later */ 1409 prefetch(skb->data); 1410 1411 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb); 1412 if (unlikely(ret <= 0)) { 1413 if (ret == -EBUSY) { 1414 u64_stats_update_begin(&ring->syncp); 1415 ring->stats.tx_busy++; 1416 u64_stats_update_end(&ring->syncp); 1417 return NETDEV_TX_BUSY; 1418 } else if (ret == -ENOMEM) { 1419 u64_stats_update_begin(&ring->syncp); 1420 ring->stats.sw_err_cnt++; 1421 u64_stats_update_end(&ring->syncp); 1422 } 1423 1424 hns3_rl_err(netdev, "xmit error: %d!\n", ret); 1425 goto out_err_tx_ok; 1426 } 1427 1428 next_to_use_head = ring->next_to_use; 1429 1430 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB); 1431 if (unlikely(ret < 0)) 1432 goto fill_err; 1433 1434 bd_num += ret; 1435 1436 if (!skb_has_frag_list(skb)) 1437 goto out; 1438 1439 skb_walk_frags(skb, frag_skb) { 1440 ret = hns3_fill_skb_to_desc(ring, frag_skb, DESC_TYPE_PAGE); 1441 if (unlikely(ret < 0)) 1442 goto fill_err; 1443 1444 bd_num += ret; 1445 } 1446 out: 1447 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) : 1448 (ring->desc_num - 1); 1449 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |= 1450 cpu_to_le16(BIT(HNS3_TXD_FE_B)); 1451 1452 /* Complete translate all packets */ 1453 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index); 1454 netdev_tx_sent_queue(dev_queue, skb->len); 1455 1456 wmb(); /* Commit all data before submit */ 1457 1458 hnae3_queue_xmit(ring->tqp, bd_num); 1459 1460 return NETDEV_TX_OK; 1461 1462 fill_err: 1463 hns3_clear_desc(ring, next_to_use_head); 1464 1465 out_err_tx_ok: 1466 dev_kfree_skb_any(skb); 1467 return NETDEV_TX_OK; 1468 } 1469 1470 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1471 { 1472 struct hnae3_handle *h = hns3_get_handle(netdev); 1473 struct sockaddr *mac_addr = p; 1474 int ret; 1475 1476 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1477 return -EADDRNOTAVAIL; 1478 1479 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1480 netdev_info(netdev, "already using mac address %pM\n", 1481 mac_addr->sa_data); 1482 return 0; 1483 } 1484 1485 /* For VF device, if there is a perm_addr, then the user will not 1486 * be allowed to change the address. 1487 */ 1488 if (!hns3_is_phys_func(h->pdev) && 1489 !is_zero_ether_addr(netdev->perm_addr)) { 1490 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n", 1491 netdev->perm_addr, mac_addr->sa_data); 1492 return -EPERM; 1493 } 1494 1495 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1496 if (ret) { 1497 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1498 return ret; 1499 } 1500 1501 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1502 1503 return 0; 1504 } 1505 1506 static int hns3_nic_do_ioctl(struct net_device *netdev, 1507 struct ifreq *ifr, int cmd) 1508 { 1509 struct hnae3_handle *h = hns3_get_handle(netdev); 1510 1511 if (!netif_running(netdev)) 1512 return -EINVAL; 1513 1514 if (!h->ae_algo->ops->do_ioctl) 1515 return -EOPNOTSUPP; 1516 1517 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 1518 } 1519 1520 static int hns3_nic_set_features(struct net_device *netdev, 1521 netdev_features_t features) 1522 { 1523 netdev_features_t changed = netdev->features ^ features; 1524 struct hns3_nic_priv *priv = netdev_priv(netdev); 1525 struct hnae3_handle *h = priv->ae_handle; 1526 bool enable; 1527 int ret; 1528 1529 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 1530 enable = !!(features & NETIF_F_GRO_HW); 1531 ret = h->ae_algo->ops->set_gro_en(h, enable); 1532 if (ret) 1533 return ret; 1534 } 1535 1536 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 1537 h->ae_algo->ops->enable_vlan_filter) { 1538 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER); 1539 h->ae_algo->ops->enable_vlan_filter(h, enable); 1540 } 1541 1542 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1543 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1544 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 1545 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 1546 if (ret) 1547 return ret; 1548 } 1549 1550 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 1551 enable = !!(features & NETIF_F_NTUPLE); 1552 h->ae_algo->ops->enable_fd(h, enable); 1553 } 1554 1555 netdev->features = features; 1556 return 0; 1557 } 1558 1559 static void hns3_nic_get_stats64(struct net_device *netdev, 1560 struct rtnl_link_stats64 *stats) 1561 { 1562 struct hns3_nic_priv *priv = netdev_priv(netdev); 1563 int queue_num = priv->ae_handle->kinfo.num_tqps; 1564 struct hnae3_handle *handle = priv->ae_handle; 1565 struct hns3_enet_ring *ring; 1566 u64 rx_length_errors = 0; 1567 u64 rx_crc_errors = 0; 1568 u64 rx_multicast = 0; 1569 unsigned int start; 1570 u64 tx_errors = 0; 1571 u64 rx_errors = 0; 1572 unsigned int idx; 1573 u64 tx_bytes = 0; 1574 u64 rx_bytes = 0; 1575 u64 tx_pkts = 0; 1576 u64 rx_pkts = 0; 1577 u64 tx_drop = 0; 1578 u64 rx_drop = 0; 1579 1580 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1581 return; 1582 1583 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1584 1585 for (idx = 0; idx < queue_num; idx++) { 1586 /* fetch the tx stats */ 1587 ring = &priv->ring[idx]; 1588 do { 1589 start = u64_stats_fetch_begin_irq(&ring->syncp); 1590 tx_bytes += ring->stats.tx_bytes; 1591 tx_pkts += ring->stats.tx_pkts; 1592 tx_drop += ring->stats.sw_err_cnt; 1593 tx_drop += ring->stats.tx_vlan_err; 1594 tx_drop += ring->stats.tx_l4_proto_err; 1595 tx_drop += ring->stats.tx_l2l3l4_err; 1596 tx_drop += ring->stats.tx_tso_err; 1597 tx_errors += ring->stats.sw_err_cnt; 1598 tx_errors += ring->stats.tx_vlan_err; 1599 tx_errors += ring->stats.tx_l4_proto_err; 1600 tx_errors += ring->stats.tx_l2l3l4_err; 1601 tx_errors += ring->stats.tx_tso_err; 1602 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1603 1604 /* fetch the rx stats */ 1605 ring = &priv->ring[idx + queue_num]; 1606 do { 1607 start = u64_stats_fetch_begin_irq(&ring->syncp); 1608 rx_bytes += ring->stats.rx_bytes; 1609 rx_pkts += ring->stats.rx_pkts; 1610 rx_drop += ring->stats.l2_err; 1611 rx_errors += ring->stats.l2_err; 1612 rx_errors += ring->stats.l3l4_csum_err; 1613 rx_crc_errors += ring->stats.l2_err; 1614 rx_multicast += ring->stats.rx_multicast; 1615 rx_length_errors += ring->stats.err_pkt_len; 1616 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1617 } 1618 1619 stats->tx_bytes = tx_bytes; 1620 stats->tx_packets = tx_pkts; 1621 stats->rx_bytes = rx_bytes; 1622 stats->rx_packets = rx_pkts; 1623 1624 stats->rx_errors = rx_errors; 1625 stats->multicast = rx_multicast; 1626 stats->rx_length_errors = rx_length_errors; 1627 stats->rx_crc_errors = rx_crc_errors; 1628 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1629 1630 stats->tx_errors = tx_errors; 1631 stats->rx_dropped = rx_drop; 1632 stats->tx_dropped = tx_drop; 1633 stats->collisions = netdev->stats.collisions; 1634 stats->rx_over_errors = netdev->stats.rx_over_errors; 1635 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1636 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1637 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1638 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1639 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1640 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1641 stats->tx_window_errors = netdev->stats.tx_window_errors; 1642 stats->rx_compressed = netdev->stats.rx_compressed; 1643 stats->tx_compressed = netdev->stats.tx_compressed; 1644 } 1645 1646 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1647 { 1648 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1649 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map; 1650 struct hnae3_knic_private_info *kinfo; 1651 u8 tc = mqprio_qopt->qopt.num_tc; 1652 u16 mode = mqprio_qopt->mode; 1653 u8 hw = mqprio_qopt->qopt.hw; 1654 struct hnae3_handle *h; 1655 1656 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1657 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1658 return -EOPNOTSUPP; 1659 1660 if (tc > HNAE3_MAX_TC) 1661 return -EINVAL; 1662 1663 if (!netdev) 1664 return -EINVAL; 1665 1666 h = hns3_get_handle(netdev); 1667 kinfo = &h->kinfo; 1668 1669 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc); 1670 1671 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1672 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP; 1673 } 1674 1675 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1676 void *type_data) 1677 { 1678 if (type != TC_SETUP_QDISC_MQPRIO) 1679 return -EOPNOTSUPP; 1680 1681 return hns3_setup_tc(dev, type_data); 1682 } 1683 1684 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1685 __be16 proto, u16 vid) 1686 { 1687 struct hnae3_handle *h = hns3_get_handle(netdev); 1688 int ret = -EIO; 1689 1690 if (h->ae_algo->ops->set_vlan_filter) 1691 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1692 1693 return ret; 1694 } 1695 1696 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1697 __be16 proto, u16 vid) 1698 { 1699 struct hnae3_handle *h = hns3_get_handle(netdev); 1700 int ret = -EIO; 1701 1702 if (h->ae_algo->ops->set_vlan_filter) 1703 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1704 1705 return ret; 1706 } 1707 1708 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1709 u8 qos, __be16 vlan_proto) 1710 { 1711 struct hnae3_handle *h = hns3_get_handle(netdev); 1712 int ret = -EIO; 1713 1714 netif_dbg(h, drv, netdev, 1715 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n", 1716 vf, vlan, qos, ntohs(vlan_proto)); 1717 1718 if (h->ae_algo->ops->set_vf_vlan_filter) 1719 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1720 qos, vlan_proto); 1721 1722 return ret; 1723 } 1724 1725 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable) 1726 { 1727 struct hnae3_handle *handle = hns3_get_handle(netdev); 1728 1729 if (hns3_nic_resetting(netdev)) 1730 return -EBUSY; 1731 1732 if (!handle->ae_algo->ops->set_vf_spoofchk) 1733 return -EOPNOTSUPP; 1734 1735 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable); 1736 } 1737 1738 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable) 1739 { 1740 struct hnae3_handle *handle = hns3_get_handle(netdev); 1741 1742 if (!handle->ae_algo->ops->set_vf_trust) 1743 return -EOPNOTSUPP; 1744 1745 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable); 1746 } 1747 1748 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1749 { 1750 struct hnae3_handle *h = hns3_get_handle(netdev); 1751 int ret; 1752 1753 if (hns3_nic_resetting(netdev)) 1754 return -EBUSY; 1755 1756 if (!h->ae_algo->ops->set_mtu) 1757 return -EOPNOTSUPP; 1758 1759 netif_dbg(h, drv, netdev, 1760 "change mtu from %u to %d\n", netdev->mtu, new_mtu); 1761 1762 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 1763 if (ret) 1764 netdev_err(netdev, "failed to change MTU in hardware %d\n", 1765 ret); 1766 else 1767 netdev->mtu = new_mtu; 1768 1769 return ret; 1770 } 1771 1772 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 1773 { 1774 struct hns3_nic_priv *priv = netdev_priv(ndev); 1775 struct hnae3_handle *h = hns3_get_handle(ndev); 1776 struct hns3_enet_ring *tx_ring; 1777 struct napi_struct *napi; 1778 int timeout_queue = 0; 1779 int hw_head, hw_tail; 1780 int fbd_num, fbd_oft; 1781 int ebd_num, ebd_oft; 1782 int bd_num, bd_err; 1783 int ring_en, tc; 1784 int i; 1785 1786 /* Find the stopped queue the same way the stack does */ 1787 for (i = 0; i < ndev->num_tx_queues; i++) { 1788 struct netdev_queue *q; 1789 unsigned long trans_start; 1790 1791 q = netdev_get_tx_queue(ndev, i); 1792 trans_start = q->trans_start; 1793 if (netif_xmit_stopped(q) && 1794 time_after(jiffies, 1795 (trans_start + ndev->watchdog_timeo))) { 1796 timeout_queue = i; 1797 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n", 1798 q->state, 1799 jiffies_to_msecs(jiffies - trans_start)); 1800 break; 1801 } 1802 } 1803 1804 if (i == ndev->num_tx_queues) { 1805 netdev_info(ndev, 1806 "no netdev TX timeout queue found, timeout count: %llu\n", 1807 priv->tx_timeout_count); 1808 return false; 1809 } 1810 1811 priv->tx_timeout_count++; 1812 1813 tx_ring = &priv->ring[timeout_queue]; 1814 napi = &tx_ring->tqp_vector->napi; 1815 1816 netdev_info(ndev, 1817 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n", 1818 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use, 1819 tx_ring->next_to_clean, napi->state); 1820 1821 netdev_info(ndev, 1822 "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n", 1823 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes, 1824 tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt); 1825 1826 netdev_info(ndev, 1827 "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n", 1828 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt, 1829 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy); 1830 1831 /* When mac received many pause frames continuous, it's unable to send 1832 * packets, which may cause tx timeout 1833 */ 1834 if (h->ae_algo->ops->get_mac_stats) { 1835 struct hns3_mac_stats mac_stats; 1836 1837 h->ae_algo->ops->get_mac_stats(h, &mac_stats); 1838 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n", 1839 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt); 1840 } 1841 1842 hw_head = readl_relaxed(tx_ring->tqp->io_base + 1843 HNS3_RING_TX_RING_HEAD_REG); 1844 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 1845 HNS3_RING_TX_RING_TAIL_REG); 1846 fbd_num = readl_relaxed(tx_ring->tqp->io_base + 1847 HNS3_RING_TX_RING_FBDNUM_REG); 1848 fbd_oft = readl_relaxed(tx_ring->tqp->io_base + 1849 HNS3_RING_TX_RING_OFFSET_REG); 1850 ebd_num = readl_relaxed(tx_ring->tqp->io_base + 1851 HNS3_RING_TX_RING_EBDNUM_REG); 1852 ebd_oft = readl_relaxed(tx_ring->tqp->io_base + 1853 HNS3_RING_TX_RING_EBD_OFFSET_REG); 1854 bd_num = readl_relaxed(tx_ring->tqp->io_base + 1855 HNS3_RING_TX_RING_BD_NUM_REG); 1856 bd_err = readl_relaxed(tx_ring->tqp->io_base + 1857 HNS3_RING_TX_RING_BD_ERR_REG); 1858 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG); 1859 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG); 1860 1861 netdev_info(ndev, 1862 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n", 1863 bd_num, hw_head, hw_tail, bd_err, 1864 readl(tx_ring->tqp_vector->mask_addr)); 1865 netdev_info(ndev, 1866 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n", 1867 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft); 1868 1869 return true; 1870 } 1871 1872 static void hns3_nic_net_timeout(struct net_device *ndev) 1873 { 1874 struct hns3_nic_priv *priv = netdev_priv(ndev); 1875 struct hnae3_handle *h = priv->ae_handle; 1876 1877 if (!hns3_get_tx_timeo_queue_info(ndev)) 1878 return; 1879 1880 /* request the reset, and let the hclge to determine 1881 * which reset level should be done 1882 */ 1883 if (h->ae_algo->ops->reset_event) 1884 h->ae_algo->ops->reset_event(h->pdev, h); 1885 } 1886 1887 #ifdef CONFIG_RFS_ACCEL 1888 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 1889 u16 rxq_index, u32 flow_id) 1890 { 1891 struct hnae3_handle *h = hns3_get_handle(dev); 1892 struct flow_keys fkeys; 1893 1894 if (!h->ae_algo->ops->add_arfs_entry) 1895 return -EOPNOTSUPP; 1896 1897 if (skb->encapsulation) 1898 return -EPROTONOSUPPORT; 1899 1900 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0)) 1901 return -EPROTONOSUPPORT; 1902 1903 if ((fkeys.basic.n_proto != htons(ETH_P_IP) && 1904 fkeys.basic.n_proto != htons(ETH_P_IPV6)) || 1905 (fkeys.basic.ip_proto != IPPROTO_TCP && 1906 fkeys.basic.ip_proto != IPPROTO_UDP)) 1907 return -EPROTONOSUPPORT; 1908 1909 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys); 1910 } 1911 #endif 1912 1913 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf, 1914 struct ifla_vf_info *ivf) 1915 { 1916 struct hnae3_handle *h = hns3_get_handle(ndev); 1917 1918 if (!h->ae_algo->ops->get_vf_config) 1919 return -EOPNOTSUPP; 1920 1921 return h->ae_algo->ops->get_vf_config(h, vf, ivf); 1922 } 1923 1924 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf, 1925 int link_state) 1926 { 1927 struct hnae3_handle *h = hns3_get_handle(ndev); 1928 1929 if (!h->ae_algo->ops->set_vf_link_state) 1930 return -EOPNOTSUPP; 1931 1932 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state); 1933 } 1934 1935 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf, 1936 int min_tx_rate, int max_tx_rate) 1937 { 1938 struct hnae3_handle *h = hns3_get_handle(ndev); 1939 1940 if (!h->ae_algo->ops->set_vf_rate) 1941 return -EOPNOTSUPP; 1942 1943 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate, 1944 false); 1945 } 1946 1947 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) 1948 { 1949 struct hnae3_handle *h = hns3_get_handle(netdev); 1950 1951 if (!h->ae_algo->ops->set_vf_mac) 1952 return -EOPNOTSUPP; 1953 1954 if (is_multicast_ether_addr(mac)) { 1955 netdev_err(netdev, 1956 "Invalid MAC:%pM specified. Could not set MAC\n", 1957 mac); 1958 return -EINVAL; 1959 } 1960 1961 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac); 1962 } 1963 1964 static const struct net_device_ops hns3_nic_netdev_ops = { 1965 .ndo_open = hns3_nic_net_open, 1966 .ndo_stop = hns3_nic_net_stop, 1967 .ndo_start_xmit = hns3_nic_net_xmit, 1968 .ndo_tx_timeout = hns3_nic_net_timeout, 1969 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 1970 .ndo_do_ioctl = hns3_nic_do_ioctl, 1971 .ndo_change_mtu = hns3_nic_change_mtu, 1972 .ndo_set_features = hns3_nic_set_features, 1973 .ndo_get_stats64 = hns3_nic_get_stats64, 1974 .ndo_setup_tc = hns3_nic_setup_tc, 1975 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 1976 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 1977 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 1978 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 1979 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk, 1980 .ndo_set_vf_trust = hns3_set_vf_trust, 1981 #ifdef CONFIG_RFS_ACCEL 1982 .ndo_rx_flow_steer = hns3_rx_flow_steer, 1983 #endif 1984 .ndo_get_vf_config = hns3_nic_get_vf_config, 1985 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state, 1986 .ndo_set_vf_rate = hns3_nic_set_vf_rate, 1987 .ndo_set_vf_mac = hns3_nic_set_vf_mac, 1988 }; 1989 1990 bool hns3_is_phys_func(struct pci_dev *pdev) 1991 { 1992 u32 dev_id = pdev->device; 1993 1994 switch (dev_id) { 1995 case HNAE3_DEV_ID_GE: 1996 case HNAE3_DEV_ID_25GE: 1997 case HNAE3_DEV_ID_25GE_RDMA: 1998 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 1999 case HNAE3_DEV_ID_50GE_RDMA: 2000 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 2001 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 2002 return true; 2003 case HNAE3_DEV_ID_100G_VF: 2004 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF: 2005 return false; 2006 default: 2007 dev_warn(&pdev->dev, "un-recognized pci device-id %u", 2008 dev_id); 2009 } 2010 2011 return false; 2012 } 2013 2014 static void hns3_disable_sriov(struct pci_dev *pdev) 2015 { 2016 /* If our VFs are assigned we cannot shut down SR-IOV 2017 * without causing issues, so just leave the hardware 2018 * available but disabled 2019 */ 2020 if (pci_vfs_assigned(pdev)) { 2021 dev_warn(&pdev->dev, 2022 "disabling driver while VFs are assigned\n"); 2023 return; 2024 } 2025 2026 pci_disable_sriov(pdev); 2027 } 2028 2029 static void hns3_get_dev_capability(struct pci_dev *pdev, 2030 struct hnae3_ae_dev *ae_dev) 2031 { 2032 if (pdev->revision >= 0x21) { 2033 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1); 2034 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1); 2035 } 2036 } 2037 2038 /* hns3_probe - Device initialization routine 2039 * @pdev: PCI device information struct 2040 * @ent: entry in hns3_pci_tbl 2041 * 2042 * hns3_probe initializes a PF identified by a pci_dev structure. 2043 * The OS initialization, configuring of the PF private structure, 2044 * and a hardware reset occur. 2045 * 2046 * Returns 0 on success, negative on failure 2047 */ 2048 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2049 { 2050 struct hnae3_ae_dev *ae_dev; 2051 int ret; 2052 2053 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL); 2054 if (!ae_dev) { 2055 ret = -ENOMEM; 2056 return ret; 2057 } 2058 2059 ae_dev->pdev = pdev; 2060 ae_dev->flag = ent->driver_data; 2061 ae_dev->reset_type = HNAE3_NONE_RESET; 2062 hns3_get_dev_capability(pdev, ae_dev); 2063 pci_set_drvdata(pdev, ae_dev); 2064 2065 ret = hnae3_register_ae_dev(ae_dev); 2066 if (ret) { 2067 devm_kfree(&pdev->dev, ae_dev); 2068 pci_set_drvdata(pdev, NULL); 2069 } 2070 2071 return ret; 2072 } 2073 2074 /* hns3_remove - Device removal routine 2075 * @pdev: PCI device information struct 2076 */ 2077 static void hns3_remove(struct pci_dev *pdev) 2078 { 2079 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2080 2081 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 2082 hns3_disable_sriov(pdev); 2083 2084 hnae3_unregister_ae_dev(ae_dev); 2085 pci_set_drvdata(pdev, NULL); 2086 } 2087 2088 /** 2089 * hns3_pci_sriov_configure 2090 * @pdev: pointer to a pci_dev structure 2091 * @num_vfs: number of VFs to allocate 2092 * 2093 * Enable or change the number of VFs. Called when the user updates the number 2094 * of VFs in sysfs. 2095 **/ 2096 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 2097 { 2098 int ret; 2099 2100 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 2101 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 2102 return -EINVAL; 2103 } 2104 2105 if (num_vfs) { 2106 ret = pci_enable_sriov(pdev, num_vfs); 2107 if (ret) 2108 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 2109 else 2110 return num_vfs; 2111 } else if (!pci_vfs_assigned(pdev)) { 2112 pci_disable_sriov(pdev); 2113 } else { 2114 dev_warn(&pdev->dev, 2115 "Unable to free VFs because some are assigned to VMs.\n"); 2116 } 2117 2118 return 0; 2119 } 2120 2121 static void hns3_shutdown(struct pci_dev *pdev) 2122 { 2123 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2124 2125 hnae3_unregister_ae_dev(ae_dev); 2126 devm_kfree(&pdev->dev, ae_dev); 2127 pci_set_drvdata(pdev, NULL); 2128 2129 if (system_state == SYSTEM_POWER_OFF) 2130 pci_set_power_state(pdev, PCI_D3hot); 2131 } 2132 2133 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 2134 pci_channel_state_t state) 2135 { 2136 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2137 pci_ers_result_t ret; 2138 2139 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state); 2140 2141 if (state == pci_channel_io_perm_failure) 2142 return PCI_ERS_RESULT_DISCONNECT; 2143 2144 if (!ae_dev || !ae_dev->ops) { 2145 dev_err(&pdev->dev, 2146 "Can't recover - error happened before device initialized\n"); 2147 return PCI_ERS_RESULT_NONE; 2148 } 2149 2150 if (ae_dev->ops->handle_hw_ras_error) 2151 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 2152 else 2153 return PCI_ERS_RESULT_NONE; 2154 2155 return ret; 2156 } 2157 2158 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 2159 { 2160 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2161 const struct hnae3_ae_ops *ops; 2162 enum hnae3_reset_type reset_type; 2163 struct device *dev = &pdev->dev; 2164 2165 if (!ae_dev || !ae_dev->ops) 2166 return PCI_ERS_RESULT_NONE; 2167 2168 ops = ae_dev->ops; 2169 /* request the reset */ 2170 if (ops->reset_event && ops->get_reset_level && 2171 ops->set_default_reset_request) { 2172 if (ae_dev->hw_err_reset_req) { 2173 reset_type = ops->get_reset_level(ae_dev, 2174 &ae_dev->hw_err_reset_req); 2175 ops->set_default_reset_request(ae_dev, reset_type); 2176 dev_info(dev, "requesting reset due to PCI error\n"); 2177 ops->reset_event(pdev, NULL); 2178 } 2179 2180 return PCI_ERS_RESULT_RECOVERED; 2181 } 2182 2183 return PCI_ERS_RESULT_DISCONNECT; 2184 } 2185 2186 static void hns3_reset_prepare(struct pci_dev *pdev) 2187 { 2188 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2189 2190 dev_info(&pdev->dev, "hns3 flr prepare\n"); 2191 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare) 2192 ae_dev->ops->flr_prepare(ae_dev); 2193 } 2194 2195 static void hns3_reset_done(struct pci_dev *pdev) 2196 { 2197 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2198 2199 dev_info(&pdev->dev, "hns3 flr done\n"); 2200 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done) 2201 ae_dev->ops->flr_done(ae_dev); 2202 } 2203 2204 static const struct pci_error_handlers hns3_err_handler = { 2205 .error_detected = hns3_error_detected, 2206 .slot_reset = hns3_slot_reset, 2207 .reset_prepare = hns3_reset_prepare, 2208 .reset_done = hns3_reset_done, 2209 }; 2210 2211 static struct pci_driver hns3_driver = { 2212 .name = hns3_driver_name, 2213 .id_table = hns3_pci_tbl, 2214 .probe = hns3_probe, 2215 .remove = hns3_remove, 2216 .shutdown = hns3_shutdown, 2217 .sriov_configure = hns3_pci_sriov_configure, 2218 .err_handler = &hns3_err_handler, 2219 }; 2220 2221 /* set default feature to hns3 */ 2222 static void hns3_set_default_feature(struct net_device *netdev) 2223 { 2224 struct hnae3_handle *h = hns3_get_handle(netdev); 2225 struct pci_dev *pdev = h->pdev; 2226 2227 netdev->priv_flags |= IFF_UNICAST_FLT; 2228 2229 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2230 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2231 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2232 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2233 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2234 NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST; 2235 2236 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 2237 2238 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2239 NETIF_F_HW_VLAN_CTAG_FILTER | 2240 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2241 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2242 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2243 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2244 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2245 NETIF_F_FRAGLIST; 2246 2247 netdev->vlan_features |= 2248 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | 2249 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 2250 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2251 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2252 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2253 NETIF_F_FRAGLIST; 2254 2255 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2256 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 2257 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 2258 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 2259 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 2260 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC | 2261 NETIF_F_FRAGLIST; 2262 2263 if (pdev->revision >= 0x21) { 2264 netdev->hw_features |= NETIF_F_GRO_HW; 2265 netdev->features |= NETIF_F_GRO_HW; 2266 2267 if (!(h->flags & HNAE3_SUPPORT_VF)) { 2268 netdev->hw_features |= NETIF_F_NTUPLE; 2269 netdev->features |= NETIF_F_NTUPLE; 2270 } 2271 } 2272 } 2273 2274 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 2275 struct hns3_desc_cb *cb) 2276 { 2277 unsigned int order = hns3_page_order(ring); 2278 struct page *p; 2279 2280 p = dev_alloc_pages(order); 2281 if (!p) 2282 return -ENOMEM; 2283 2284 cb->priv = p; 2285 cb->page_offset = 0; 2286 cb->reuse_flag = 0; 2287 cb->buf = page_address(p); 2288 cb->length = hns3_page_size(ring); 2289 cb->type = DESC_TYPE_PAGE; 2290 2291 return 0; 2292 } 2293 2294 static void hns3_free_buffer(struct hns3_enet_ring *ring, 2295 struct hns3_desc_cb *cb) 2296 { 2297 if (cb->type == DESC_TYPE_SKB) 2298 dev_kfree_skb_any((struct sk_buff *)cb->priv); 2299 else if (!HNAE3_IS_TX_RING(ring)) 2300 put_page((struct page *)cb->priv); 2301 memset(cb, 0, sizeof(*cb)); 2302 } 2303 2304 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 2305 { 2306 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 2307 cb->length, ring_to_dma_dir(ring)); 2308 2309 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 2310 return -EIO; 2311 2312 return 0; 2313 } 2314 2315 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 2316 struct hns3_desc_cb *cb) 2317 { 2318 if (cb->type == DESC_TYPE_SKB) 2319 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 2320 ring_to_dma_dir(ring)); 2321 else if (cb->length) 2322 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 2323 ring_to_dma_dir(ring)); 2324 } 2325 2326 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 2327 { 2328 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2329 ring->desc[i].addr = 0; 2330 } 2331 2332 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i) 2333 { 2334 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 2335 2336 if (!ring->desc_cb[i].dma) 2337 return; 2338 2339 hns3_buffer_detach(ring, i); 2340 hns3_free_buffer(ring, cb); 2341 } 2342 2343 static void hns3_free_buffers(struct hns3_enet_ring *ring) 2344 { 2345 int i; 2346 2347 for (i = 0; i < ring->desc_num; i++) 2348 hns3_free_buffer_detach(ring, i); 2349 } 2350 2351 /* free desc along with its attached buffer */ 2352 static void hns3_free_desc(struct hns3_enet_ring *ring) 2353 { 2354 int size = ring->desc_num * sizeof(ring->desc[0]); 2355 2356 hns3_free_buffers(ring); 2357 2358 if (ring->desc) { 2359 dma_free_coherent(ring_to_dev(ring), size, 2360 ring->desc, ring->desc_dma_addr); 2361 ring->desc = NULL; 2362 } 2363 } 2364 2365 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 2366 { 2367 int size = ring->desc_num * sizeof(ring->desc[0]); 2368 2369 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 2370 &ring->desc_dma_addr, GFP_KERNEL); 2371 if (!ring->desc) 2372 return -ENOMEM; 2373 2374 return 0; 2375 } 2376 2377 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring, 2378 struct hns3_desc_cb *cb) 2379 { 2380 int ret; 2381 2382 ret = hns3_alloc_buffer(ring, cb); 2383 if (ret) 2384 goto out; 2385 2386 ret = hns3_map_buffer(ring, cb); 2387 if (ret) 2388 goto out_with_buf; 2389 2390 return 0; 2391 2392 out_with_buf: 2393 hns3_free_buffer(ring, cb); 2394 out: 2395 return ret; 2396 } 2397 2398 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i) 2399 { 2400 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]); 2401 2402 if (ret) 2403 return ret; 2404 2405 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2406 2407 return 0; 2408 } 2409 2410 /* Allocate memory for raw pkg, and map with dma */ 2411 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 2412 { 2413 int i, j, ret; 2414 2415 for (i = 0; i < ring->desc_num; i++) { 2416 ret = hns3_alloc_buffer_attach(ring, i); 2417 if (ret) 2418 goto out_buffer_fail; 2419 } 2420 2421 return 0; 2422 2423 out_buffer_fail: 2424 for (j = i - 1; j >= 0; j--) 2425 hns3_free_buffer_detach(ring, j); 2426 return ret; 2427 } 2428 2429 /* detach a in-used buffer and replace with a reserved one */ 2430 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 2431 struct hns3_desc_cb *res_cb) 2432 { 2433 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2434 ring->desc_cb[i] = *res_cb; 2435 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2436 ring->desc[i].rx.bd_base_info = 0; 2437 } 2438 2439 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 2440 { 2441 ring->desc_cb[i].reuse_flag = 0; 2442 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 2443 ring->desc_cb[i].page_offset); 2444 ring->desc[i].rx.bd_base_info = 0; 2445 } 2446 2447 static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head, 2448 int *bytes, int *pkts) 2449 { 2450 int ntc = ring->next_to_clean; 2451 struct hns3_desc_cb *desc_cb; 2452 2453 while (head != ntc) { 2454 desc_cb = &ring->desc_cb[ntc]; 2455 (*pkts) += (desc_cb->type == DESC_TYPE_SKB); 2456 (*bytes) += desc_cb->length; 2457 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */ 2458 hns3_free_buffer_detach(ring, ntc); 2459 2460 if (++ntc == ring->desc_num) 2461 ntc = 0; 2462 2463 /* Issue prefetch for next Tx descriptor */ 2464 prefetch(&ring->desc_cb[ntc]); 2465 } 2466 2467 /* This smp_store_release() pairs with smp_load_acquire() in 2468 * ring_space called by hns3_nic_net_xmit. 2469 */ 2470 smp_store_release(&ring->next_to_clean, ntc); 2471 } 2472 2473 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h) 2474 { 2475 int u = ring->next_to_use; 2476 int c = ring->next_to_clean; 2477 2478 if (unlikely(h > ring->desc_num)) 2479 return 0; 2480 2481 return u > c ? (h > c && h <= u) : (h > c || h <= u); 2482 } 2483 2484 void hns3_clean_tx_ring(struct hns3_enet_ring *ring) 2485 { 2486 struct net_device *netdev = ring_to_netdev(ring); 2487 struct hns3_nic_priv *priv = netdev_priv(netdev); 2488 struct netdev_queue *dev_queue; 2489 int bytes, pkts; 2490 int head; 2491 2492 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG); 2493 2494 if (is_ring_empty(ring) || head == ring->next_to_clean) 2495 return; /* no data to poll */ 2496 2497 rmb(); /* Make sure head is ready before touch any data */ 2498 2499 if (unlikely(!is_valid_clean_head(ring, head))) { 2500 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head, 2501 ring->next_to_use, ring->next_to_clean); 2502 2503 u64_stats_update_begin(&ring->syncp); 2504 ring->stats.io_err_cnt++; 2505 u64_stats_update_end(&ring->syncp); 2506 return; 2507 } 2508 2509 bytes = 0; 2510 pkts = 0; 2511 hns3_nic_reclaim_desc(ring, head, &bytes, &pkts); 2512 2513 ring->tqp_vector->tx_group.total_bytes += bytes; 2514 ring->tqp_vector->tx_group.total_packets += pkts; 2515 2516 u64_stats_update_begin(&ring->syncp); 2517 ring->stats.tx_bytes += bytes; 2518 ring->stats.tx_pkts += pkts; 2519 u64_stats_update_end(&ring->syncp); 2520 2521 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 2522 netdev_tx_completed_queue(dev_queue, pkts, bytes); 2523 2524 if (unlikely(netif_carrier_ok(netdev) && 2525 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) { 2526 /* Make sure that anybody stopping the queue after this 2527 * sees the new next_to_clean. 2528 */ 2529 smp_mb(); 2530 if (netif_tx_queue_stopped(dev_queue) && 2531 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 2532 netif_tx_wake_queue(dev_queue); 2533 ring->stats.restart_queue++; 2534 } 2535 } 2536 } 2537 2538 static int hns3_desc_unused(struct hns3_enet_ring *ring) 2539 { 2540 int ntc = ring->next_to_clean; 2541 int ntu = ring->next_to_use; 2542 2543 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 2544 } 2545 2546 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, 2547 int cleand_count) 2548 { 2549 struct hns3_desc_cb *desc_cb; 2550 struct hns3_desc_cb res_cbs; 2551 int i, ret; 2552 2553 for (i = 0; i < cleand_count; i++) { 2554 desc_cb = &ring->desc_cb[ring->next_to_use]; 2555 if (desc_cb->reuse_flag) { 2556 u64_stats_update_begin(&ring->syncp); 2557 ring->stats.reuse_pg_cnt++; 2558 u64_stats_update_end(&ring->syncp); 2559 2560 hns3_reuse_buffer(ring, ring->next_to_use); 2561 } else { 2562 ret = hns3_reserve_buffer_map(ring, &res_cbs); 2563 if (ret) { 2564 u64_stats_update_begin(&ring->syncp); 2565 ring->stats.sw_err_cnt++; 2566 u64_stats_update_end(&ring->syncp); 2567 2568 hns3_rl_err(ring_to_netdev(ring), 2569 "alloc rx buffer failed: %d\n", 2570 ret); 2571 break; 2572 } 2573 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 2574 2575 u64_stats_update_begin(&ring->syncp); 2576 ring->stats.non_reuse_pg++; 2577 u64_stats_update_end(&ring->syncp); 2578 } 2579 2580 ring_ptr_move_fw(ring, next_to_use); 2581 } 2582 2583 wmb(); /* Make all data has been write before submit */ 2584 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2585 } 2586 2587 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2588 struct hns3_enet_ring *ring, int pull_len, 2589 struct hns3_desc_cb *desc_cb) 2590 { 2591 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 2592 int size = le16_to_cpu(desc->rx.size); 2593 u32 truesize = hns3_buf_size(ring); 2594 2595 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2596 size - pull_len, truesize); 2597 2598 /* Avoid re-using remote pages, or the stack is still using the page 2599 * when page_offset rollback to zero, flag default unreuse 2600 */ 2601 if (unlikely(page_to_nid(desc_cb->priv) != numa_mem_id()) || 2602 (!desc_cb->page_offset && page_count(desc_cb->priv) > 1)) 2603 return; 2604 2605 /* Move offset up to the next cache line */ 2606 desc_cb->page_offset += truesize; 2607 2608 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) { 2609 desc_cb->reuse_flag = 1; 2610 /* Bump ref count on page before it is given */ 2611 get_page(desc_cb->priv); 2612 } else if (page_count(desc_cb->priv) == 1) { 2613 desc_cb->reuse_flag = 1; 2614 desc_cb->page_offset = 0; 2615 get_page(desc_cb->priv); 2616 } 2617 } 2618 2619 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) 2620 { 2621 __be16 type = skb->protocol; 2622 struct tcphdr *th; 2623 int depth = 0; 2624 2625 while (eth_type_vlan(type)) { 2626 struct vlan_hdr *vh; 2627 2628 if ((depth + VLAN_HLEN) > skb_headlen(skb)) 2629 return -EFAULT; 2630 2631 vh = (struct vlan_hdr *)(skb->data + depth); 2632 type = vh->h_vlan_encapsulated_proto; 2633 depth += VLAN_HLEN; 2634 } 2635 2636 skb_set_network_header(skb, depth); 2637 2638 if (type == htons(ETH_P_IP)) { 2639 const struct iphdr *iph = ip_hdr(skb); 2640 2641 depth += sizeof(struct iphdr); 2642 skb_set_transport_header(skb, depth); 2643 th = tcp_hdr(skb); 2644 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr, 2645 iph->daddr, 0); 2646 } else if (type == htons(ETH_P_IPV6)) { 2647 const struct ipv6hdr *iph = ipv6_hdr(skb); 2648 2649 depth += sizeof(struct ipv6hdr); 2650 skb_set_transport_header(skb, depth); 2651 th = tcp_hdr(skb); 2652 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr, 2653 &iph->daddr, 0); 2654 } else { 2655 hns3_rl_err(skb->dev, 2656 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n", 2657 be16_to_cpu(type), depth); 2658 return -EFAULT; 2659 } 2660 2661 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 2662 if (th->cwr) 2663 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 2664 2665 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B)) 2666 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID; 2667 2668 skb->csum_start = (unsigned char *)th - skb->head; 2669 skb->csum_offset = offsetof(struct tcphdr, check); 2670 skb->ip_summed = CHECKSUM_PARTIAL; 2671 return 0; 2672 } 2673 2674 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2675 u32 l234info, u32 bd_base_info, u32 ol_info) 2676 { 2677 struct net_device *netdev = ring_to_netdev(ring); 2678 int l3_type, l4_type; 2679 int ol4_type; 2680 2681 skb->ip_summed = CHECKSUM_NONE; 2682 2683 skb_checksum_none_assert(skb); 2684 2685 if (!(netdev->features & NETIF_F_RXCSUM)) 2686 return; 2687 2688 /* check if hardware has done checksum */ 2689 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 2690 return; 2691 2692 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | 2693 BIT(HNS3_RXD_OL3E_B) | 2694 BIT(HNS3_RXD_OL4E_B)))) { 2695 u64_stats_update_begin(&ring->syncp); 2696 ring->stats.l3l4_csum_err++; 2697 u64_stats_update_end(&ring->syncp); 2698 2699 return; 2700 } 2701 2702 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M, 2703 HNS3_RXD_OL4ID_S); 2704 switch (ol4_type) { 2705 case HNS3_OL4_TYPE_MAC_IN_UDP: 2706 case HNS3_OL4_TYPE_NVGRE: 2707 skb->csum_level = 1; 2708 /* fall through */ 2709 case HNS3_OL4_TYPE_NO_TUN: 2710 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2711 HNS3_RXD_L3ID_S); 2712 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 2713 HNS3_RXD_L4ID_S); 2714 2715 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 2716 if ((l3_type == HNS3_L3_TYPE_IPV4 || 2717 l3_type == HNS3_L3_TYPE_IPV6) && 2718 (l4_type == HNS3_L4_TYPE_UDP || 2719 l4_type == HNS3_L4_TYPE_TCP || 2720 l4_type == HNS3_L4_TYPE_SCTP)) 2721 skb->ip_summed = CHECKSUM_UNNECESSARY; 2722 break; 2723 default: 2724 break; 2725 } 2726 } 2727 2728 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 2729 { 2730 if (skb_has_frag_list(skb)) 2731 napi_gro_flush(&ring->tqp_vector->napi, false); 2732 2733 napi_gro_receive(&ring->tqp_vector->napi, skb); 2734 } 2735 2736 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 2737 struct hns3_desc *desc, u32 l234info, 2738 u16 *vlan_tag) 2739 { 2740 struct hnae3_handle *handle = ring->tqp->handle; 2741 struct pci_dev *pdev = ring->tqp->handle->pdev; 2742 2743 if (pdev->revision == 0x20) { 2744 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2745 if (!(*vlan_tag & VLAN_VID_MASK)) 2746 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2747 2748 return (*vlan_tag != 0); 2749 } 2750 2751 #define HNS3_STRP_OUTER_VLAN 0x1 2752 #define HNS3_STRP_INNER_VLAN 0x2 2753 #define HNS3_STRP_BOTH 0x3 2754 2755 /* Hardware always insert VLAN tag into RX descriptor when 2756 * remove the tag from packet, driver needs to determine 2757 * reporting which tag to stack. 2758 */ 2759 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 2760 HNS3_RXD_STRP_TAGP_S)) { 2761 case HNS3_STRP_OUTER_VLAN: 2762 if (handle->port_base_vlan_state != 2763 HNAE3_PORT_BASE_VLAN_DISABLE) 2764 return false; 2765 2766 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2767 return true; 2768 case HNS3_STRP_INNER_VLAN: 2769 if (handle->port_base_vlan_state != 2770 HNAE3_PORT_BASE_VLAN_DISABLE) 2771 return false; 2772 2773 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2774 return true; 2775 case HNS3_STRP_BOTH: 2776 if (handle->port_base_vlan_state == 2777 HNAE3_PORT_BASE_VLAN_DISABLE) 2778 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2779 else 2780 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2781 2782 return true; 2783 default: 2784 return false; 2785 } 2786 } 2787 2788 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length, 2789 unsigned char *va) 2790 { 2791 #define HNS3_NEED_ADD_FRAG 1 2792 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2793 struct net_device *netdev = ring_to_netdev(ring); 2794 struct sk_buff *skb; 2795 2796 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 2797 skb = ring->skb; 2798 if (unlikely(!skb)) { 2799 hns3_rl_err(netdev, "alloc rx skb fail\n"); 2800 2801 u64_stats_update_begin(&ring->syncp); 2802 ring->stats.sw_err_cnt++; 2803 u64_stats_update_end(&ring->syncp); 2804 2805 return -ENOMEM; 2806 } 2807 2808 prefetchw(skb->data); 2809 2810 ring->pending_buf = 1; 2811 ring->frag_num = 0; 2812 ring->tail_skb = NULL; 2813 if (length <= HNS3_RX_HEAD_SIZE) { 2814 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 2815 2816 /* We can reuse buffer as-is, just make sure it is local */ 2817 if (likely(page_to_nid(desc_cb->priv) == numa_mem_id())) 2818 desc_cb->reuse_flag = 1; 2819 else /* This page cannot be reused so discard it */ 2820 put_page(desc_cb->priv); 2821 2822 ring_ptr_move_fw(ring, next_to_clean); 2823 return 0; 2824 } 2825 u64_stats_update_begin(&ring->syncp); 2826 ring->stats.seg_pkt_cnt++; 2827 u64_stats_update_end(&ring->syncp); 2828 2829 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE); 2830 __skb_put(skb, ring->pull_len); 2831 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 2832 desc_cb); 2833 ring_ptr_move_fw(ring, next_to_clean); 2834 2835 return HNS3_NEED_ADD_FRAG; 2836 } 2837 2838 static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc, 2839 bool pending) 2840 { 2841 struct sk_buff *skb = ring->skb; 2842 struct sk_buff *head_skb = skb; 2843 struct sk_buff *new_skb; 2844 struct hns3_desc_cb *desc_cb; 2845 struct hns3_desc *pre_desc; 2846 u32 bd_base_info; 2847 int pre_bd; 2848 2849 /* if there is pending bd, the SW param next_to_clean has moved 2850 * to next and the next is NULL 2851 */ 2852 if (pending) { 2853 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) % 2854 ring->desc_num; 2855 pre_desc = &ring->desc[pre_bd]; 2856 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info); 2857 } else { 2858 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2859 } 2860 2861 while (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { 2862 desc = &ring->desc[ring->next_to_clean]; 2863 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2864 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2865 /* make sure HW write desc complete */ 2866 dma_rmb(); 2867 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 2868 return -ENXIO; 2869 2870 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 2871 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0); 2872 if (unlikely(!new_skb)) { 2873 hns3_rl_err(ring_to_netdev(ring), 2874 "alloc rx fraglist skb fail\n"); 2875 return -ENXIO; 2876 } 2877 ring->frag_num = 0; 2878 2879 if (ring->tail_skb) { 2880 ring->tail_skb->next = new_skb; 2881 ring->tail_skb = new_skb; 2882 } else { 2883 skb_shinfo(skb)->frag_list = new_skb; 2884 ring->tail_skb = new_skb; 2885 } 2886 } 2887 2888 if (ring->tail_skb) { 2889 head_skb->truesize += hns3_buf_size(ring); 2890 head_skb->data_len += le16_to_cpu(desc->rx.size); 2891 head_skb->len += le16_to_cpu(desc->rx.size); 2892 skb = ring->tail_skb; 2893 } 2894 2895 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 2896 ring_ptr_move_fw(ring, next_to_clean); 2897 ring->pending_buf++; 2898 } 2899 2900 return 0; 2901 } 2902 2903 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring, 2904 struct sk_buff *skb, u32 l234info, 2905 u32 bd_base_info, u32 ol_info) 2906 { 2907 u32 l3_type; 2908 2909 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 2910 HNS3_RXD_GRO_SIZE_M, 2911 HNS3_RXD_GRO_SIZE_S); 2912 /* if there is no HW GRO, do not set gro params */ 2913 if (!skb_shinfo(skb)->gso_size) { 2914 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info); 2915 return 0; 2916 } 2917 2918 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info, 2919 HNS3_RXD_GRO_COUNT_M, 2920 HNS3_RXD_GRO_COUNT_S); 2921 2922 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S); 2923 if (l3_type == HNS3_L3_TYPE_IPV4) 2924 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 2925 else if (l3_type == HNS3_L3_TYPE_IPV6) 2926 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 2927 else 2928 return -EFAULT; 2929 2930 return hns3_gro_complete(skb, l234info); 2931 } 2932 2933 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 2934 struct sk_buff *skb, u32 rss_hash) 2935 { 2936 struct hnae3_handle *handle = ring->tqp->handle; 2937 enum pkt_hash_types rss_type; 2938 2939 if (rss_hash) 2940 rss_type = handle->kinfo.rss_type; 2941 else 2942 rss_type = PKT_HASH_TYPE_NONE; 2943 2944 skb_set_hash(skb, rss_hash, rss_type); 2945 } 2946 2947 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb) 2948 { 2949 struct net_device *netdev = ring_to_netdev(ring); 2950 enum hns3_pkt_l2t_type l2_frame_type; 2951 u32 bd_base_info, l234info, ol_info; 2952 struct hns3_desc *desc; 2953 unsigned int len; 2954 int pre_ntc, ret; 2955 2956 /* bdinfo handled below is only valid on the last BD of the 2957 * current packet, and ring->next_to_clean indicates the first 2958 * descriptor of next packet, so need - 1 below. 2959 */ 2960 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) : 2961 (ring->desc_num - 1); 2962 desc = &ring->desc[pre_ntc]; 2963 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2964 l234info = le32_to_cpu(desc->rx.l234_info); 2965 ol_info = le32_to_cpu(desc->rx.ol_info); 2966 2967 /* Based on hw strategy, the tag offloaded will be stored at 2968 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 2969 * in one layer tag case. 2970 */ 2971 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 2972 u16 vlan_tag; 2973 2974 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 2975 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 2976 vlan_tag); 2977 } 2978 2979 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 2980 BIT(HNS3_RXD_L2E_B))))) { 2981 u64_stats_update_begin(&ring->syncp); 2982 if (l234info & BIT(HNS3_RXD_L2E_B)) 2983 ring->stats.l2_err++; 2984 else 2985 ring->stats.err_pkt_len++; 2986 u64_stats_update_end(&ring->syncp); 2987 2988 return -EFAULT; 2989 } 2990 2991 len = skb->len; 2992 2993 /* Do update ip stack process */ 2994 skb->protocol = eth_type_trans(skb, netdev); 2995 2996 /* This is needed in order to enable forwarding support */ 2997 ret = hns3_set_gro_and_checksum(ring, skb, l234info, 2998 bd_base_info, ol_info); 2999 if (unlikely(ret)) { 3000 u64_stats_update_begin(&ring->syncp); 3001 ring->stats.rx_err_cnt++; 3002 u64_stats_update_end(&ring->syncp); 3003 return ret; 3004 } 3005 3006 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 3007 HNS3_RXD_DMAC_S); 3008 3009 u64_stats_update_begin(&ring->syncp); 3010 ring->stats.rx_pkts++; 3011 ring->stats.rx_bytes += len; 3012 3013 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 3014 ring->stats.rx_multicast++; 3015 3016 u64_stats_update_end(&ring->syncp); 3017 3018 ring->tqp_vector->rx_group.total_bytes += len; 3019 3020 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash)); 3021 return 0; 3022 } 3023 3024 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring) 3025 { 3026 struct sk_buff *skb = ring->skb; 3027 struct hns3_desc_cb *desc_cb; 3028 struct hns3_desc *desc; 3029 unsigned int length; 3030 u32 bd_base_info; 3031 int ret; 3032 3033 desc = &ring->desc[ring->next_to_clean]; 3034 desc_cb = &ring->desc_cb[ring->next_to_clean]; 3035 3036 prefetch(desc); 3037 3038 length = le16_to_cpu(desc->rx.size); 3039 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3040 3041 /* Check valid BD */ 3042 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 3043 return -ENXIO; 3044 3045 if (!skb) 3046 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset; 3047 3048 /* Prefetch first cache line of first page 3049 * Idea is to cache few bytes of the header of the packet. Our L1 Cache 3050 * line size is 64B so need to prefetch twice to make it 128B. But in 3051 * actual we can have greater size of caches with 128B Level 1 cache 3052 * lines. In such a case, single fetch would suffice to cache in the 3053 * relevant part of the header. 3054 */ 3055 prefetch(ring->va); 3056 #if L1_CACHE_BYTES < 128 3057 prefetch(ring->va + L1_CACHE_BYTES); 3058 #endif 3059 3060 if (!skb) { 3061 ret = hns3_alloc_skb(ring, length, ring->va); 3062 skb = ring->skb; 3063 3064 if (ret < 0) /* alloc buffer fail */ 3065 return ret; 3066 if (ret > 0) { /* need add frag */ 3067 ret = hns3_add_frag(ring, desc, false); 3068 if (ret) 3069 return ret; 3070 3071 /* As the head data may be changed when GRO enable, copy 3072 * the head data in after other data rx completed 3073 */ 3074 memcpy(skb->data, ring->va, 3075 ALIGN(ring->pull_len, sizeof(long))); 3076 } 3077 } else { 3078 ret = hns3_add_frag(ring, desc, true); 3079 if (ret) 3080 return ret; 3081 3082 /* As the head data may be changed when GRO enable, copy 3083 * the head data in after other data rx completed 3084 */ 3085 memcpy(skb->data, ring->va, 3086 ALIGN(ring->pull_len, sizeof(long))); 3087 } 3088 3089 ret = hns3_handle_bdinfo(ring, skb); 3090 if (unlikely(ret)) { 3091 dev_kfree_skb_any(skb); 3092 return ret; 3093 } 3094 3095 skb_record_rx_queue(skb, ring->tqp->tqp_index); 3096 return 0; 3097 } 3098 3099 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget, 3100 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 3101 { 3102 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 3103 int unused_count = hns3_desc_unused(ring); 3104 int recv_pkts = 0; 3105 int recv_bds = 0; 3106 int err, num; 3107 3108 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG); 3109 num -= unused_count; 3110 unused_count -= ring->pending_buf; 3111 3112 if (num <= 0) 3113 goto out; 3114 3115 rmb(); /* Make sure num taken effect before the other data is touched */ 3116 3117 while (recv_pkts < budget && recv_bds < num) { 3118 /* Reuse or realloc buffers */ 3119 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 3120 hns3_nic_alloc_rx_buffers(ring, unused_count); 3121 unused_count = hns3_desc_unused(ring) - 3122 ring->pending_buf; 3123 } 3124 3125 /* Poll one pkt */ 3126 err = hns3_handle_rx_bd(ring); 3127 /* Do not get FE for the packet or failed to alloc skb */ 3128 if (unlikely(!ring->skb || err == -ENXIO)) { 3129 goto out; 3130 } else if (likely(!err)) { 3131 rx_fn(ring, ring->skb); 3132 recv_pkts++; 3133 } 3134 3135 recv_bds += ring->pending_buf; 3136 unused_count += ring->pending_buf; 3137 ring->skb = NULL; 3138 ring->pending_buf = 0; 3139 } 3140 3141 out: 3142 /* Make all data has been write before submit */ 3143 if (unused_count > 0) 3144 hns3_nic_alloc_rx_buffers(ring, unused_count); 3145 3146 return recv_pkts; 3147 } 3148 3149 static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group) 3150 { 3151 #define HNS3_RX_LOW_BYTE_RATE 10000 3152 #define HNS3_RX_MID_BYTE_RATE 20000 3153 #define HNS3_RX_ULTRA_PACKET_RATE 40 3154 3155 enum hns3_flow_level_range new_flow_level; 3156 struct hns3_enet_tqp_vector *tqp_vector; 3157 int packets_per_msecs, bytes_per_msecs; 3158 u32 time_passed_ms; 3159 3160 tqp_vector = ring_group->ring->tqp_vector; 3161 time_passed_ms = 3162 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 3163 if (!time_passed_ms) 3164 return false; 3165 3166 do_div(ring_group->total_packets, time_passed_ms); 3167 packets_per_msecs = ring_group->total_packets; 3168 3169 do_div(ring_group->total_bytes, time_passed_ms); 3170 bytes_per_msecs = ring_group->total_bytes; 3171 3172 new_flow_level = ring_group->coal.flow_level; 3173 3174 /* Simple throttlerate management 3175 * 0-10MB/s lower (50000 ints/s) 3176 * 10-20MB/s middle (20000 ints/s) 3177 * 20-1249MB/s high (18000 ints/s) 3178 * > 40000pps ultra (8000 ints/s) 3179 */ 3180 switch (new_flow_level) { 3181 case HNS3_FLOW_LOW: 3182 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 3183 new_flow_level = HNS3_FLOW_MID; 3184 break; 3185 case HNS3_FLOW_MID: 3186 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 3187 new_flow_level = HNS3_FLOW_HIGH; 3188 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 3189 new_flow_level = HNS3_FLOW_LOW; 3190 break; 3191 case HNS3_FLOW_HIGH: 3192 case HNS3_FLOW_ULTRA: 3193 default: 3194 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 3195 new_flow_level = HNS3_FLOW_MID; 3196 break; 3197 } 3198 3199 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 3200 &tqp_vector->rx_group == ring_group) 3201 new_flow_level = HNS3_FLOW_ULTRA; 3202 3203 ring_group->total_bytes = 0; 3204 ring_group->total_packets = 0; 3205 ring_group->coal.flow_level = new_flow_level; 3206 3207 return true; 3208 } 3209 3210 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 3211 { 3212 struct hns3_enet_tqp_vector *tqp_vector; 3213 u16 new_int_gl; 3214 3215 if (!ring_group->ring) 3216 return false; 3217 3218 tqp_vector = ring_group->ring->tqp_vector; 3219 if (!tqp_vector->last_jiffies) 3220 return false; 3221 3222 if (ring_group->total_packets == 0) { 3223 ring_group->coal.int_gl = HNS3_INT_GL_50K; 3224 ring_group->coal.flow_level = HNS3_FLOW_LOW; 3225 return true; 3226 } 3227 3228 if (!hns3_get_new_flow_lvl(ring_group)) 3229 return false; 3230 3231 new_int_gl = ring_group->coal.int_gl; 3232 switch (ring_group->coal.flow_level) { 3233 case HNS3_FLOW_LOW: 3234 new_int_gl = HNS3_INT_GL_50K; 3235 break; 3236 case HNS3_FLOW_MID: 3237 new_int_gl = HNS3_INT_GL_20K; 3238 break; 3239 case HNS3_FLOW_HIGH: 3240 new_int_gl = HNS3_INT_GL_18K; 3241 break; 3242 case HNS3_FLOW_ULTRA: 3243 new_int_gl = HNS3_INT_GL_8K; 3244 break; 3245 default: 3246 break; 3247 } 3248 3249 if (new_int_gl != ring_group->coal.int_gl) { 3250 ring_group->coal.int_gl = new_int_gl; 3251 return true; 3252 } 3253 return false; 3254 } 3255 3256 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 3257 { 3258 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 3259 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 3260 bool rx_update, tx_update; 3261 3262 /* update param every 1000ms */ 3263 if (time_before(jiffies, 3264 tqp_vector->last_jiffies + msecs_to_jiffies(1000))) 3265 return; 3266 3267 if (rx_group->coal.gl_adapt_enable) { 3268 rx_update = hns3_get_new_int_gl(rx_group); 3269 if (rx_update) 3270 hns3_set_vector_coalesce_rx_gl(tqp_vector, 3271 rx_group->coal.int_gl); 3272 } 3273 3274 if (tx_group->coal.gl_adapt_enable) { 3275 tx_update = hns3_get_new_int_gl(tx_group); 3276 if (tx_update) 3277 hns3_set_vector_coalesce_tx_gl(tqp_vector, 3278 tx_group->coal.int_gl); 3279 } 3280 3281 tqp_vector->last_jiffies = jiffies; 3282 } 3283 3284 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 3285 { 3286 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 3287 struct hns3_enet_ring *ring; 3288 int rx_pkt_total = 0; 3289 3290 struct hns3_enet_tqp_vector *tqp_vector = 3291 container_of(napi, struct hns3_enet_tqp_vector, napi); 3292 bool clean_complete = true; 3293 int rx_budget = budget; 3294 3295 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3296 napi_complete(napi); 3297 return 0; 3298 } 3299 3300 /* Since the actual Tx work is minimal, we can give the Tx a larger 3301 * budget and be more aggressive about cleaning up the Tx descriptors. 3302 */ 3303 hns3_for_each_ring(ring, tqp_vector->tx_group) 3304 hns3_clean_tx_ring(ring); 3305 3306 /* make sure rx ring budget not smaller than 1 */ 3307 if (tqp_vector->num_tqps > 1) 3308 rx_budget = max(budget / tqp_vector->num_tqps, 1); 3309 3310 hns3_for_each_ring(ring, tqp_vector->rx_group) { 3311 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 3312 hns3_rx_skb); 3313 3314 if (rx_cleaned >= rx_budget) 3315 clean_complete = false; 3316 3317 rx_pkt_total += rx_cleaned; 3318 } 3319 3320 tqp_vector->rx_group.total_packets += rx_pkt_total; 3321 3322 if (!clean_complete) 3323 return budget; 3324 3325 if (napi_complete(napi) && 3326 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 3327 hns3_update_new_int_gl(tqp_vector); 3328 hns3_mask_vector_irq(tqp_vector, 1); 3329 } 3330 3331 return rx_pkt_total; 3332 } 3333 3334 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3335 struct hnae3_ring_chain_node *head) 3336 { 3337 struct pci_dev *pdev = tqp_vector->handle->pdev; 3338 struct hnae3_ring_chain_node *cur_chain = head; 3339 struct hnae3_ring_chain_node *chain; 3340 struct hns3_enet_ring *tx_ring; 3341 struct hns3_enet_ring *rx_ring; 3342 3343 tx_ring = tqp_vector->tx_group.ring; 3344 if (tx_ring) { 3345 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 3346 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3347 HNAE3_RING_TYPE_TX); 3348 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3349 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 3350 3351 cur_chain->next = NULL; 3352 3353 while (tx_ring->next) { 3354 tx_ring = tx_ring->next; 3355 3356 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 3357 GFP_KERNEL); 3358 if (!chain) 3359 goto err_free_chain; 3360 3361 cur_chain->next = chain; 3362 chain->tqp_index = tx_ring->tqp->tqp_index; 3363 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3364 HNAE3_RING_TYPE_TX); 3365 hnae3_set_field(chain->int_gl_idx, 3366 HNAE3_RING_GL_IDX_M, 3367 HNAE3_RING_GL_IDX_S, 3368 HNAE3_RING_GL_TX); 3369 3370 cur_chain = chain; 3371 } 3372 } 3373 3374 rx_ring = tqp_vector->rx_group.ring; 3375 if (!tx_ring && rx_ring) { 3376 cur_chain->next = NULL; 3377 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 3378 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 3379 HNAE3_RING_TYPE_RX); 3380 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3381 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3382 3383 rx_ring = rx_ring->next; 3384 } 3385 3386 while (rx_ring) { 3387 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 3388 if (!chain) 3389 goto err_free_chain; 3390 3391 cur_chain->next = chain; 3392 chain->tqp_index = rx_ring->tqp->tqp_index; 3393 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 3394 HNAE3_RING_TYPE_RX); 3395 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 3396 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 3397 3398 cur_chain = chain; 3399 3400 rx_ring = rx_ring->next; 3401 } 3402 3403 return 0; 3404 3405 err_free_chain: 3406 cur_chain = head->next; 3407 while (cur_chain) { 3408 chain = cur_chain->next; 3409 devm_kfree(&pdev->dev, cur_chain); 3410 cur_chain = chain; 3411 } 3412 head->next = NULL; 3413 3414 return -ENOMEM; 3415 } 3416 3417 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3418 struct hnae3_ring_chain_node *head) 3419 { 3420 struct pci_dev *pdev = tqp_vector->handle->pdev; 3421 struct hnae3_ring_chain_node *chain_tmp, *chain; 3422 3423 chain = head->next; 3424 3425 while (chain) { 3426 chain_tmp = chain->next; 3427 devm_kfree(&pdev->dev, chain); 3428 chain = chain_tmp; 3429 } 3430 } 3431 3432 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 3433 struct hns3_enet_ring *ring) 3434 { 3435 ring->next = group->ring; 3436 group->ring = ring; 3437 3438 group->count++; 3439 } 3440 3441 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 3442 { 3443 struct pci_dev *pdev = priv->ae_handle->pdev; 3444 struct hns3_enet_tqp_vector *tqp_vector; 3445 int num_vectors = priv->vector_num; 3446 int numa_node; 3447 int vector_i; 3448 3449 numa_node = dev_to_node(&pdev->dev); 3450 3451 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 3452 tqp_vector = &priv->tqp_vector[vector_i]; 3453 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 3454 &tqp_vector->affinity_mask); 3455 } 3456 } 3457 3458 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 3459 { 3460 struct hnae3_ring_chain_node vector_ring_chain; 3461 struct hnae3_handle *h = priv->ae_handle; 3462 struct hns3_enet_tqp_vector *tqp_vector; 3463 int ret = 0; 3464 int i; 3465 3466 hns3_nic_set_cpumask(priv); 3467 3468 for (i = 0; i < priv->vector_num; i++) { 3469 tqp_vector = &priv->tqp_vector[i]; 3470 hns3_vector_gl_rl_init_hw(tqp_vector, priv); 3471 tqp_vector->num_tqps = 0; 3472 } 3473 3474 for (i = 0; i < h->kinfo.num_tqps; i++) { 3475 u16 vector_i = i % priv->vector_num; 3476 u16 tqp_num = h->kinfo.num_tqps; 3477 3478 tqp_vector = &priv->tqp_vector[vector_i]; 3479 3480 hns3_add_ring_to_group(&tqp_vector->tx_group, 3481 &priv->ring[i]); 3482 3483 hns3_add_ring_to_group(&tqp_vector->rx_group, 3484 &priv->ring[i + tqp_num]); 3485 3486 priv->ring[i].tqp_vector = tqp_vector; 3487 priv->ring[i + tqp_num].tqp_vector = tqp_vector; 3488 tqp_vector->num_tqps++; 3489 } 3490 3491 for (i = 0; i < priv->vector_num; i++) { 3492 tqp_vector = &priv->tqp_vector[i]; 3493 3494 tqp_vector->rx_group.total_bytes = 0; 3495 tqp_vector->rx_group.total_packets = 0; 3496 tqp_vector->tx_group.total_bytes = 0; 3497 tqp_vector->tx_group.total_packets = 0; 3498 tqp_vector->handle = h; 3499 3500 ret = hns3_get_vector_ring_chain(tqp_vector, 3501 &vector_ring_chain); 3502 if (ret) 3503 goto map_ring_fail; 3504 3505 ret = h->ae_algo->ops->map_ring_to_vector(h, 3506 tqp_vector->vector_irq, &vector_ring_chain); 3507 3508 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3509 3510 if (ret) 3511 goto map_ring_fail; 3512 3513 netif_napi_add(priv->netdev, &tqp_vector->napi, 3514 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 3515 } 3516 3517 return 0; 3518 3519 map_ring_fail: 3520 while (i--) 3521 netif_napi_del(&priv->tqp_vector[i].napi); 3522 3523 return ret; 3524 } 3525 3526 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 3527 { 3528 #define HNS3_VECTOR_PF_MAX_NUM 64 3529 3530 struct hnae3_handle *h = priv->ae_handle; 3531 struct hns3_enet_tqp_vector *tqp_vector; 3532 struct hnae3_vector_info *vector; 3533 struct pci_dev *pdev = h->pdev; 3534 u16 tqp_num = h->kinfo.num_tqps; 3535 u16 vector_num; 3536 int ret = 0; 3537 u16 i; 3538 3539 /* RSS size, cpu online and vector_num should be the same */ 3540 /* Should consider 2p/4p later */ 3541 vector_num = min_t(u16, num_online_cpus(), tqp_num); 3542 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM); 3543 3544 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 3545 GFP_KERNEL); 3546 if (!vector) 3547 return -ENOMEM; 3548 3549 /* save the actual available vector number */ 3550 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 3551 3552 priv->vector_num = vector_num; 3553 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 3554 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 3555 GFP_KERNEL); 3556 if (!priv->tqp_vector) { 3557 ret = -ENOMEM; 3558 goto out; 3559 } 3560 3561 for (i = 0; i < priv->vector_num; i++) { 3562 tqp_vector = &priv->tqp_vector[i]; 3563 tqp_vector->idx = i; 3564 tqp_vector->mask_addr = vector[i].io_addr; 3565 tqp_vector->vector_irq = vector[i].vector; 3566 hns3_vector_gl_rl_init(tqp_vector, priv); 3567 } 3568 3569 out: 3570 devm_kfree(&pdev->dev, vector); 3571 return ret; 3572 } 3573 3574 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 3575 { 3576 group->ring = NULL; 3577 group->count = 0; 3578 } 3579 3580 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 3581 { 3582 struct hnae3_ring_chain_node vector_ring_chain; 3583 struct hnae3_handle *h = priv->ae_handle; 3584 struct hns3_enet_tqp_vector *tqp_vector; 3585 int i; 3586 3587 for (i = 0; i < priv->vector_num; i++) { 3588 tqp_vector = &priv->tqp_vector[i]; 3589 3590 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 3591 continue; 3592 3593 hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain); 3594 3595 h->ae_algo->ops->unmap_ring_from_vector(h, 3596 tqp_vector->vector_irq, &vector_ring_chain); 3597 3598 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3599 3600 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) { 3601 irq_set_affinity_hint(tqp_vector->vector_irq, NULL); 3602 free_irq(tqp_vector->vector_irq, tqp_vector); 3603 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED; 3604 } 3605 3606 hns3_clear_ring_group(&tqp_vector->rx_group); 3607 hns3_clear_ring_group(&tqp_vector->tx_group); 3608 netif_napi_del(&priv->tqp_vector[i].napi); 3609 } 3610 } 3611 3612 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 3613 { 3614 struct hnae3_handle *h = priv->ae_handle; 3615 struct pci_dev *pdev = h->pdev; 3616 int i, ret; 3617 3618 for (i = 0; i < priv->vector_num; i++) { 3619 struct hns3_enet_tqp_vector *tqp_vector; 3620 3621 tqp_vector = &priv->tqp_vector[i]; 3622 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 3623 if (ret) 3624 return ret; 3625 } 3626 3627 devm_kfree(&pdev->dev, priv->tqp_vector); 3628 return 0; 3629 } 3630 3631 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 3632 unsigned int ring_type) 3633 { 3634 int queue_num = priv->ae_handle->kinfo.num_tqps; 3635 struct hns3_enet_ring *ring; 3636 int desc_num; 3637 3638 if (ring_type == HNAE3_RING_TYPE_TX) { 3639 ring = &priv->ring[q->tqp_index]; 3640 desc_num = priv->ae_handle->kinfo.num_tx_desc; 3641 ring->queue_index = q->tqp_index; 3642 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET; 3643 } else { 3644 ring = &priv->ring[q->tqp_index + queue_num]; 3645 desc_num = priv->ae_handle->kinfo.num_rx_desc; 3646 ring->queue_index = q->tqp_index; 3647 ring->io_base = q->io_base; 3648 } 3649 3650 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 3651 3652 ring->tqp = q; 3653 ring->desc = NULL; 3654 ring->desc_cb = NULL; 3655 ring->dev = priv->dev; 3656 ring->desc_dma_addr = 0; 3657 ring->buf_size = q->buf_size; 3658 ring->desc_num = desc_num; 3659 ring->next_to_use = 0; 3660 ring->next_to_clean = 0; 3661 } 3662 3663 static void hns3_queue_to_ring(struct hnae3_queue *tqp, 3664 struct hns3_nic_priv *priv) 3665 { 3666 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 3667 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 3668 } 3669 3670 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 3671 { 3672 struct hnae3_handle *h = priv->ae_handle; 3673 struct pci_dev *pdev = h->pdev; 3674 int i; 3675 3676 priv->ring = devm_kzalloc(&pdev->dev, 3677 array3_size(h->kinfo.num_tqps, 3678 sizeof(*priv->ring), 2), 3679 GFP_KERNEL); 3680 if (!priv->ring) 3681 return -ENOMEM; 3682 3683 for (i = 0; i < h->kinfo.num_tqps; i++) 3684 hns3_queue_to_ring(h->kinfo.tqp[i], priv); 3685 3686 return 0; 3687 } 3688 3689 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 3690 { 3691 if (!priv->ring) 3692 return; 3693 3694 devm_kfree(priv->dev, priv->ring); 3695 priv->ring = NULL; 3696 } 3697 3698 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 3699 { 3700 int ret; 3701 3702 if (ring->desc_num <= 0 || ring->buf_size <= 0) 3703 return -EINVAL; 3704 3705 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num, 3706 sizeof(ring->desc_cb[0]), GFP_KERNEL); 3707 if (!ring->desc_cb) { 3708 ret = -ENOMEM; 3709 goto out; 3710 } 3711 3712 ret = hns3_alloc_desc(ring); 3713 if (ret) 3714 goto out_with_desc_cb; 3715 3716 if (!HNAE3_IS_TX_RING(ring)) { 3717 ret = hns3_alloc_ring_buffers(ring); 3718 if (ret) 3719 goto out_with_desc; 3720 } 3721 3722 return 0; 3723 3724 out_with_desc: 3725 hns3_free_desc(ring); 3726 out_with_desc_cb: 3727 devm_kfree(ring_to_dev(ring), ring->desc_cb); 3728 ring->desc_cb = NULL; 3729 out: 3730 return ret; 3731 } 3732 3733 void hns3_fini_ring(struct hns3_enet_ring *ring) 3734 { 3735 hns3_free_desc(ring); 3736 devm_kfree(ring_to_dev(ring), ring->desc_cb); 3737 ring->desc_cb = NULL; 3738 ring->next_to_clean = 0; 3739 ring->next_to_use = 0; 3740 ring->pending_buf = 0; 3741 if (ring->skb) { 3742 dev_kfree_skb_any(ring->skb); 3743 ring->skb = NULL; 3744 } 3745 } 3746 3747 static int hns3_buf_size2type(u32 buf_size) 3748 { 3749 int bd_size_type; 3750 3751 switch (buf_size) { 3752 case 512: 3753 bd_size_type = HNS3_BD_SIZE_512_TYPE; 3754 break; 3755 case 1024: 3756 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 3757 break; 3758 case 2048: 3759 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3760 break; 3761 case 4096: 3762 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 3763 break; 3764 default: 3765 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3766 } 3767 3768 return bd_size_type; 3769 } 3770 3771 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 3772 { 3773 dma_addr_t dma = ring->desc_dma_addr; 3774 struct hnae3_queue *q = ring->tqp; 3775 3776 if (!HNAE3_IS_TX_RING(ring)) { 3777 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma); 3778 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 3779 (u32)((dma >> 31) >> 1)); 3780 3781 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 3782 hns3_buf_size2type(ring->buf_size)); 3783 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 3784 ring->desc_num / 8 - 1); 3785 3786 } else { 3787 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 3788 (u32)dma); 3789 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 3790 (u32)((dma >> 31) >> 1)); 3791 3792 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 3793 ring->desc_num / 8 - 1); 3794 } 3795 } 3796 3797 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 3798 { 3799 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3800 int i; 3801 3802 for (i = 0; i < HNAE3_MAX_TC; i++) { 3803 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i]; 3804 int j; 3805 3806 if (!tc_info->enable) 3807 continue; 3808 3809 for (j = 0; j < tc_info->tqp_count; j++) { 3810 struct hnae3_queue *q; 3811 3812 q = priv->ring[tc_info->tqp_offset + j].tqp; 3813 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, 3814 tc_info->tc); 3815 } 3816 } 3817 } 3818 3819 int hns3_init_all_ring(struct hns3_nic_priv *priv) 3820 { 3821 struct hnae3_handle *h = priv->ae_handle; 3822 int ring_num = h->kinfo.num_tqps * 2; 3823 int i, j; 3824 int ret; 3825 3826 for (i = 0; i < ring_num; i++) { 3827 ret = hns3_alloc_ring_memory(&priv->ring[i]); 3828 if (ret) { 3829 dev_err(priv->dev, 3830 "Alloc ring memory fail! ret=%d\n", ret); 3831 goto out_when_alloc_ring_memory; 3832 } 3833 3834 u64_stats_init(&priv->ring[i].syncp); 3835 } 3836 3837 return 0; 3838 3839 out_when_alloc_ring_memory: 3840 for (j = i - 1; j >= 0; j--) 3841 hns3_fini_ring(&priv->ring[j]); 3842 3843 return -ENOMEM; 3844 } 3845 3846 int hns3_uninit_all_ring(struct hns3_nic_priv *priv) 3847 { 3848 struct hnae3_handle *h = priv->ae_handle; 3849 int i; 3850 3851 for (i = 0; i < h->kinfo.num_tqps; i++) { 3852 hns3_fini_ring(&priv->ring[i]); 3853 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]); 3854 } 3855 return 0; 3856 } 3857 3858 /* Set mac addr if it is configured. or leave it to the AE driver */ 3859 static int hns3_init_mac_addr(struct net_device *netdev) 3860 { 3861 struct hns3_nic_priv *priv = netdev_priv(netdev); 3862 struct hnae3_handle *h = priv->ae_handle; 3863 u8 mac_addr_temp[ETH_ALEN]; 3864 int ret = 0; 3865 3866 if (h->ae_algo->ops->get_mac_addr) 3867 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 3868 3869 /* Check if the MAC address is valid, if not get a random one */ 3870 if (!is_valid_ether_addr(mac_addr_temp)) { 3871 eth_hw_addr_random(netdev); 3872 dev_warn(priv->dev, "using random MAC address %pM\n", 3873 netdev->dev_addr); 3874 } else { 3875 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 3876 ether_addr_copy(netdev->perm_addr, mac_addr_temp); 3877 } 3878 3879 if (h->ae_algo->ops->set_mac_addr) 3880 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 3881 3882 return ret; 3883 } 3884 3885 static int hns3_init_phy(struct net_device *netdev) 3886 { 3887 struct hnae3_handle *h = hns3_get_handle(netdev); 3888 int ret = 0; 3889 3890 if (h->ae_algo->ops->mac_connect_phy) 3891 ret = h->ae_algo->ops->mac_connect_phy(h); 3892 3893 return ret; 3894 } 3895 3896 static void hns3_uninit_phy(struct net_device *netdev) 3897 { 3898 struct hnae3_handle *h = hns3_get_handle(netdev); 3899 3900 if (h->ae_algo->ops->mac_disconnect_phy) 3901 h->ae_algo->ops->mac_disconnect_phy(h); 3902 } 3903 3904 static int hns3_restore_fd_rules(struct net_device *netdev) 3905 { 3906 struct hnae3_handle *h = hns3_get_handle(netdev); 3907 int ret = 0; 3908 3909 if (h->ae_algo->ops->restore_fd_rules) 3910 ret = h->ae_algo->ops->restore_fd_rules(h); 3911 3912 return ret; 3913 } 3914 3915 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list) 3916 { 3917 struct hnae3_handle *h = hns3_get_handle(netdev); 3918 3919 if (h->ae_algo->ops->del_all_fd_entries) 3920 h->ae_algo->ops->del_all_fd_entries(h, clear_list); 3921 } 3922 3923 static int hns3_client_start(struct hnae3_handle *handle) 3924 { 3925 if (!handle->ae_algo->ops->client_start) 3926 return 0; 3927 3928 return handle->ae_algo->ops->client_start(handle); 3929 } 3930 3931 static void hns3_client_stop(struct hnae3_handle *handle) 3932 { 3933 if (!handle->ae_algo->ops->client_stop) 3934 return; 3935 3936 handle->ae_algo->ops->client_stop(handle); 3937 } 3938 3939 static void hns3_info_show(struct hns3_nic_priv *priv) 3940 { 3941 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3942 3943 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr); 3944 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps); 3945 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size); 3946 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size); 3947 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len); 3948 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc); 3949 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc); 3950 dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc); 3951 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu); 3952 } 3953 3954 static int hns3_client_init(struct hnae3_handle *handle) 3955 { 3956 struct pci_dev *pdev = handle->pdev; 3957 u16 alloc_tqps, max_rss_size; 3958 struct hns3_nic_priv *priv; 3959 struct net_device *netdev; 3960 int ret; 3961 3962 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 3963 &max_rss_size); 3964 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 3965 if (!netdev) 3966 return -ENOMEM; 3967 3968 priv = netdev_priv(netdev); 3969 priv->dev = &pdev->dev; 3970 priv->netdev = netdev; 3971 priv->ae_handle = handle; 3972 priv->tx_timeout_count = 0; 3973 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 3974 3975 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL); 3976 3977 handle->kinfo.netdev = netdev; 3978 handle->priv = (void *)priv; 3979 3980 hns3_init_mac_addr(netdev); 3981 3982 hns3_set_default_feature(netdev); 3983 3984 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 3985 netdev->priv_flags |= IFF_UNICAST_FLT; 3986 netdev->netdev_ops = &hns3_nic_netdev_ops; 3987 SET_NETDEV_DEV(netdev, &pdev->dev); 3988 hns3_ethtool_set_ops(netdev); 3989 3990 /* Carrier off reporting is important to ethtool even BEFORE open */ 3991 netif_carrier_off(netdev); 3992 3993 ret = hns3_get_ring_config(priv); 3994 if (ret) { 3995 ret = -ENOMEM; 3996 goto out_get_ring_cfg; 3997 } 3998 3999 ret = hns3_nic_alloc_vector_data(priv); 4000 if (ret) { 4001 ret = -ENOMEM; 4002 goto out_alloc_vector_data; 4003 } 4004 4005 ret = hns3_nic_init_vector_data(priv); 4006 if (ret) { 4007 ret = -ENOMEM; 4008 goto out_init_vector_data; 4009 } 4010 4011 ret = hns3_init_all_ring(priv); 4012 if (ret) { 4013 ret = -ENOMEM; 4014 goto out_init_ring; 4015 } 4016 4017 ret = hns3_init_phy(netdev); 4018 if (ret) 4019 goto out_init_phy; 4020 4021 ret = register_netdev(netdev); 4022 if (ret) { 4023 dev_err(priv->dev, "probe register netdev fail!\n"); 4024 goto out_reg_netdev_fail; 4025 } 4026 4027 ret = hns3_client_start(handle); 4028 if (ret) { 4029 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4030 goto out_client_start; 4031 } 4032 4033 hns3_dcbnl_setup(handle); 4034 4035 hns3_dbg_init(handle); 4036 4037 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */ 4038 netdev->max_mtu = HNS3_MAX_MTU; 4039 4040 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4041 4042 if (netif_msg_drv(handle)) 4043 hns3_info_show(priv); 4044 4045 return ret; 4046 4047 out_client_start: 4048 unregister_netdev(netdev); 4049 out_reg_netdev_fail: 4050 hns3_uninit_phy(netdev); 4051 out_init_phy: 4052 hns3_uninit_all_ring(priv); 4053 out_init_ring: 4054 hns3_nic_uninit_vector_data(priv); 4055 out_init_vector_data: 4056 hns3_nic_dealloc_vector_data(priv); 4057 out_alloc_vector_data: 4058 priv->ring = NULL; 4059 out_get_ring_cfg: 4060 priv->ae_handle = NULL; 4061 free_netdev(netdev); 4062 return ret; 4063 } 4064 4065 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 4066 { 4067 struct net_device *netdev = handle->kinfo.netdev; 4068 struct hns3_nic_priv *priv = netdev_priv(netdev); 4069 int ret; 4070 4071 hns3_remove_hw_addr(netdev); 4072 4073 if (netdev->reg_state != NETREG_UNINITIALIZED) 4074 unregister_netdev(netdev); 4075 4076 hns3_client_stop(handle); 4077 4078 hns3_uninit_phy(netdev); 4079 4080 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4081 netdev_warn(netdev, "already uninitialized\n"); 4082 goto out_netdev_free; 4083 } 4084 4085 hns3_del_all_fd_rules(netdev, true); 4086 4087 hns3_clear_all_ring(handle, true); 4088 4089 hns3_nic_uninit_vector_data(priv); 4090 4091 ret = hns3_nic_dealloc_vector_data(priv); 4092 if (ret) 4093 netdev_err(netdev, "dealloc vector error\n"); 4094 4095 ret = hns3_uninit_all_ring(priv); 4096 if (ret) 4097 netdev_err(netdev, "uninit ring error\n"); 4098 4099 hns3_put_ring_config(priv); 4100 4101 hns3_dbg_uninit(handle); 4102 4103 out_netdev_free: 4104 free_netdev(netdev); 4105 } 4106 4107 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 4108 { 4109 struct net_device *netdev = handle->kinfo.netdev; 4110 4111 if (!netdev) 4112 return; 4113 4114 if (linkup) { 4115 netif_carrier_on(netdev); 4116 netif_tx_wake_all_queues(netdev); 4117 if (netif_msg_link(handle)) 4118 netdev_info(netdev, "link up\n"); 4119 } else { 4120 netif_carrier_off(netdev); 4121 netif_tx_stop_all_queues(netdev); 4122 if (netif_msg_link(handle)) 4123 netdev_info(netdev, "link down\n"); 4124 } 4125 } 4126 4127 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc) 4128 { 4129 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4130 struct net_device *ndev = kinfo->netdev; 4131 4132 if (tc > HNAE3_MAX_TC) 4133 return -EINVAL; 4134 4135 if (!ndev) 4136 return -ENODEV; 4137 4138 return hns3_nic_set_real_num_queue(ndev); 4139 } 4140 4141 static int hns3_recover_hw_addr(struct net_device *ndev) 4142 { 4143 struct netdev_hw_addr_list *list; 4144 struct netdev_hw_addr *ha, *tmp; 4145 int ret = 0; 4146 4147 netif_addr_lock_bh(ndev); 4148 /* go through and sync uc_addr entries to the device */ 4149 list = &ndev->uc; 4150 list_for_each_entry_safe(ha, tmp, &list->list, list) { 4151 ret = hns3_nic_uc_sync(ndev, ha->addr); 4152 if (ret) 4153 goto out; 4154 } 4155 4156 /* go through and sync mc_addr entries to the device */ 4157 list = &ndev->mc; 4158 list_for_each_entry_safe(ha, tmp, &list->list, list) { 4159 ret = hns3_nic_mc_sync(ndev, ha->addr); 4160 if (ret) 4161 goto out; 4162 } 4163 4164 out: 4165 netif_addr_unlock_bh(ndev); 4166 return ret; 4167 } 4168 4169 static void hns3_remove_hw_addr(struct net_device *netdev) 4170 { 4171 struct netdev_hw_addr_list *list; 4172 struct netdev_hw_addr *ha, *tmp; 4173 4174 hns3_nic_uc_unsync(netdev, netdev->dev_addr); 4175 4176 netif_addr_lock_bh(netdev); 4177 /* go through and unsync uc_addr entries to the device */ 4178 list = &netdev->uc; 4179 list_for_each_entry_safe(ha, tmp, &list->list, list) 4180 hns3_nic_uc_unsync(netdev, ha->addr); 4181 4182 /* go through and unsync mc_addr entries to the device */ 4183 list = &netdev->mc; 4184 list_for_each_entry_safe(ha, tmp, &list->list, list) 4185 if (ha->refcount > 1) 4186 hns3_nic_mc_unsync(netdev, ha->addr); 4187 4188 netif_addr_unlock_bh(netdev); 4189 } 4190 4191 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 4192 { 4193 while (ring->next_to_clean != ring->next_to_use) { 4194 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 4195 hns3_free_buffer_detach(ring, ring->next_to_clean); 4196 ring_ptr_move_fw(ring, next_to_clean); 4197 } 4198 } 4199 4200 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 4201 { 4202 struct hns3_desc_cb res_cbs; 4203 int ret; 4204 4205 while (ring->next_to_use != ring->next_to_clean) { 4206 /* When a buffer is not reused, it's memory has been 4207 * freed in hns3_handle_rx_bd or will be freed by 4208 * stack, so we need to replace the buffer here. 4209 */ 4210 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4211 ret = hns3_reserve_buffer_map(ring, &res_cbs); 4212 if (ret) { 4213 u64_stats_update_begin(&ring->syncp); 4214 ring->stats.sw_err_cnt++; 4215 u64_stats_update_end(&ring->syncp); 4216 /* if alloc new buffer fail, exit directly 4217 * and reclear in up flow. 4218 */ 4219 netdev_warn(ring_to_netdev(ring), 4220 "reserve buffer map failed, ret = %d\n", 4221 ret); 4222 return ret; 4223 } 4224 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 4225 } 4226 ring_ptr_move_fw(ring, next_to_use); 4227 } 4228 4229 /* Free the pending skb in rx ring */ 4230 if (ring->skb) { 4231 dev_kfree_skb_any(ring->skb); 4232 ring->skb = NULL; 4233 ring->pending_buf = 0; 4234 } 4235 4236 return 0; 4237 } 4238 4239 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 4240 { 4241 while (ring->next_to_use != ring->next_to_clean) { 4242 /* When a buffer is not reused, it's memory has been 4243 * freed in hns3_handle_rx_bd or will be freed by 4244 * stack, so only need to unmap the buffer here. 4245 */ 4246 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 4247 hns3_unmap_buffer(ring, 4248 &ring->desc_cb[ring->next_to_use]); 4249 ring->desc_cb[ring->next_to_use].dma = 0; 4250 } 4251 4252 ring_ptr_move_fw(ring, next_to_use); 4253 } 4254 } 4255 4256 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force) 4257 { 4258 struct net_device *ndev = h->kinfo.netdev; 4259 struct hns3_nic_priv *priv = netdev_priv(ndev); 4260 u32 i; 4261 4262 for (i = 0; i < h->kinfo.num_tqps; i++) { 4263 struct hns3_enet_ring *ring; 4264 4265 ring = &priv->ring[i]; 4266 hns3_clear_tx_ring(ring); 4267 4268 ring = &priv->ring[i + h->kinfo.num_tqps]; 4269 /* Continue to clear other rings even if clearing some 4270 * rings failed. 4271 */ 4272 if (force) 4273 hns3_force_clear_rx_ring(ring); 4274 else 4275 hns3_clear_rx_ring(ring); 4276 } 4277 } 4278 4279 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 4280 { 4281 struct net_device *ndev = h->kinfo.netdev; 4282 struct hns3_nic_priv *priv = netdev_priv(ndev); 4283 struct hns3_enet_ring *rx_ring; 4284 int i, j; 4285 int ret; 4286 4287 for (i = 0; i < h->kinfo.num_tqps; i++) { 4288 ret = h->ae_algo->ops->reset_queue(h, i); 4289 if (ret) 4290 return ret; 4291 4292 hns3_init_ring_hw(&priv->ring[i]); 4293 4294 /* We need to clear tx ring here because self test will 4295 * use the ring and will not run down before up 4296 */ 4297 hns3_clear_tx_ring(&priv->ring[i]); 4298 priv->ring[i].next_to_clean = 0; 4299 priv->ring[i].next_to_use = 0; 4300 4301 rx_ring = &priv->ring[i + h->kinfo.num_tqps]; 4302 hns3_init_ring_hw(rx_ring); 4303 ret = hns3_clear_rx_ring(rx_ring); 4304 if (ret) 4305 return ret; 4306 4307 /* We can not know the hardware head and tail when this 4308 * function is called in reset flow, so we reuse all desc. 4309 */ 4310 for (j = 0; j < rx_ring->desc_num; j++) 4311 hns3_reuse_buffer(rx_ring, j); 4312 4313 rx_ring->next_to_clean = 0; 4314 rx_ring->next_to_use = 0; 4315 } 4316 4317 hns3_init_tx_ring_tc(priv); 4318 4319 return 0; 4320 } 4321 4322 static void hns3_store_coal(struct hns3_nic_priv *priv) 4323 { 4324 /* ethtool only support setting and querying one coal 4325 * configuration for now, so save the vector 0' coal 4326 * configuration here in order to restore it. 4327 */ 4328 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal, 4329 sizeof(struct hns3_enet_coalesce)); 4330 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal, 4331 sizeof(struct hns3_enet_coalesce)); 4332 } 4333 4334 static void hns3_restore_coal(struct hns3_nic_priv *priv) 4335 { 4336 u16 vector_num = priv->vector_num; 4337 int i; 4338 4339 for (i = 0; i < vector_num; i++) { 4340 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal, 4341 sizeof(struct hns3_enet_coalesce)); 4342 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal, 4343 sizeof(struct hns3_enet_coalesce)); 4344 } 4345 } 4346 4347 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 4348 { 4349 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4350 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4351 struct net_device *ndev = kinfo->netdev; 4352 struct hns3_nic_priv *priv = netdev_priv(ndev); 4353 4354 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 4355 return 0; 4356 4357 /* it is cumbersome for hardware to pick-and-choose entries for deletion 4358 * from table space. Hence, for function reset software intervention is 4359 * required to delete the entries 4360 */ 4361 if (hns3_dev_ongoing_func_reset(ae_dev)) { 4362 hns3_remove_hw_addr(ndev); 4363 hns3_del_all_fd_rules(ndev, false); 4364 } 4365 4366 if (!netif_running(ndev)) 4367 return 0; 4368 4369 return hns3_nic_net_stop(ndev); 4370 } 4371 4372 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 4373 { 4374 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4375 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 4376 int ret = 0; 4377 4378 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4379 4380 if (netif_running(kinfo->netdev)) { 4381 ret = hns3_nic_net_open(kinfo->netdev); 4382 if (ret) { 4383 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4384 netdev_err(kinfo->netdev, 4385 "net up fail, ret=%d!\n", ret); 4386 return ret; 4387 } 4388 } 4389 4390 return ret; 4391 } 4392 4393 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 4394 { 4395 struct net_device *netdev = handle->kinfo.netdev; 4396 struct hns3_nic_priv *priv = netdev_priv(netdev); 4397 int ret; 4398 4399 /* Carrier off reporting is important to ethtool even BEFORE open */ 4400 netif_carrier_off(netdev); 4401 4402 ret = hns3_get_ring_config(priv); 4403 if (ret) 4404 return ret; 4405 4406 ret = hns3_nic_alloc_vector_data(priv); 4407 if (ret) 4408 goto err_put_ring; 4409 4410 hns3_restore_coal(priv); 4411 4412 ret = hns3_nic_init_vector_data(priv); 4413 if (ret) 4414 goto err_dealloc_vector; 4415 4416 ret = hns3_init_all_ring(priv); 4417 if (ret) 4418 goto err_uninit_vector; 4419 4420 ret = hns3_client_start(handle); 4421 if (ret) { 4422 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 4423 goto err_uninit_ring; 4424 } 4425 4426 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4427 4428 return ret; 4429 4430 err_uninit_ring: 4431 hns3_uninit_all_ring(priv); 4432 err_uninit_vector: 4433 hns3_nic_uninit_vector_data(priv); 4434 err_dealloc_vector: 4435 hns3_nic_dealloc_vector_data(priv); 4436 err_put_ring: 4437 hns3_put_ring_config(priv); 4438 4439 return ret; 4440 } 4441 4442 static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle) 4443 { 4444 struct net_device *netdev = handle->kinfo.netdev; 4445 bool vlan_filter_enable; 4446 int ret; 4447 4448 ret = hns3_init_mac_addr(netdev); 4449 if (ret) 4450 return ret; 4451 4452 ret = hns3_recover_hw_addr(netdev); 4453 if (ret) 4454 return ret; 4455 4456 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags); 4457 if (ret) 4458 return ret; 4459 4460 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true; 4461 hns3_enable_vlan_filter(netdev, vlan_filter_enable); 4462 4463 if (handle->ae_algo->ops->restore_vlan_table) 4464 handle->ae_algo->ops->restore_vlan_table(handle); 4465 4466 return hns3_restore_fd_rules(netdev); 4467 } 4468 4469 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 4470 { 4471 struct net_device *netdev = handle->kinfo.netdev; 4472 struct hns3_nic_priv *priv = netdev_priv(netdev); 4473 int ret; 4474 4475 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4476 netdev_warn(netdev, "already uninitialized\n"); 4477 return 0; 4478 } 4479 4480 hns3_clear_all_ring(handle, true); 4481 hns3_reset_tx_queue(priv->ae_handle); 4482 4483 hns3_nic_uninit_vector_data(priv); 4484 4485 hns3_store_coal(priv); 4486 4487 ret = hns3_nic_dealloc_vector_data(priv); 4488 if (ret) 4489 netdev_err(netdev, "dealloc vector error\n"); 4490 4491 ret = hns3_uninit_all_ring(priv); 4492 if (ret) 4493 netdev_err(netdev, "uninit ring error\n"); 4494 4495 hns3_put_ring_config(priv); 4496 4497 return ret; 4498 } 4499 4500 static int hns3_reset_notify(struct hnae3_handle *handle, 4501 enum hnae3_reset_notify_type type) 4502 { 4503 int ret = 0; 4504 4505 switch (type) { 4506 case HNAE3_UP_CLIENT: 4507 ret = hns3_reset_notify_up_enet(handle); 4508 break; 4509 case HNAE3_DOWN_CLIENT: 4510 ret = hns3_reset_notify_down_enet(handle); 4511 break; 4512 case HNAE3_INIT_CLIENT: 4513 ret = hns3_reset_notify_init_enet(handle); 4514 break; 4515 case HNAE3_UNINIT_CLIENT: 4516 ret = hns3_reset_notify_uninit_enet(handle); 4517 break; 4518 case HNAE3_RESTORE_CLIENT: 4519 ret = hns3_reset_notify_restore_enet(handle); 4520 break; 4521 default: 4522 break; 4523 } 4524 4525 return ret; 4526 } 4527 4528 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num, 4529 bool rxfh_configured) 4530 { 4531 int ret; 4532 4533 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num, 4534 rxfh_configured); 4535 if (ret) { 4536 dev_err(&handle->pdev->dev, 4537 "Change tqp num(%u) fail.\n", new_tqp_num); 4538 return ret; 4539 } 4540 4541 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT); 4542 if (ret) 4543 return ret; 4544 4545 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT); 4546 if (ret) 4547 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT); 4548 4549 return ret; 4550 } 4551 4552 int hns3_set_channels(struct net_device *netdev, 4553 struct ethtool_channels *ch) 4554 { 4555 struct hnae3_handle *h = hns3_get_handle(netdev); 4556 struct hnae3_knic_private_info *kinfo = &h->kinfo; 4557 bool rxfh_configured = netif_is_rxfh_configured(netdev); 4558 u32 new_tqp_num = ch->combined_count; 4559 u16 org_tqp_num; 4560 int ret; 4561 4562 if (hns3_nic_resetting(netdev)) 4563 return -EBUSY; 4564 4565 if (ch->rx_count || ch->tx_count) 4566 return -EINVAL; 4567 4568 if (new_tqp_num > hns3_get_max_available_channels(h) || 4569 new_tqp_num < 1) { 4570 dev_err(&netdev->dev, 4571 "Change tqps fail, the tqp range is from 1 to %u", 4572 hns3_get_max_available_channels(h)); 4573 return -EINVAL; 4574 } 4575 4576 if (kinfo->rss_size == new_tqp_num) 4577 return 0; 4578 4579 netif_dbg(h, drv, netdev, 4580 "set channels: tqp_num=%u, rxfh=%d\n", 4581 new_tqp_num, rxfh_configured); 4582 4583 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 4584 if (ret) 4585 return ret; 4586 4587 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 4588 if (ret) 4589 return ret; 4590 4591 org_tqp_num = h->kinfo.num_tqps; 4592 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured); 4593 if (ret) { 4594 int ret1; 4595 4596 netdev_warn(netdev, 4597 "Change channels fail, revert to old value\n"); 4598 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured); 4599 if (ret1) { 4600 netdev_err(netdev, 4601 "revert to old channel fail\n"); 4602 return ret1; 4603 } 4604 4605 return ret; 4606 } 4607 4608 return 0; 4609 } 4610 4611 static const struct hns3_hw_error_info hns3_hw_err[] = { 4612 { .type = HNAE3_PPU_POISON_ERROR, 4613 .msg = "PPU poison" }, 4614 { .type = HNAE3_CMDQ_ECC_ERROR, 4615 .msg = "IMP CMDQ error" }, 4616 { .type = HNAE3_IMP_RD_POISON_ERROR, 4617 .msg = "IMP RD poison" }, 4618 }; 4619 4620 static void hns3_process_hw_error(struct hnae3_handle *handle, 4621 enum hnae3_hw_error_type type) 4622 { 4623 int i; 4624 4625 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) { 4626 if (hns3_hw_err[i].type == type) { 4627 dev_err(&handle->pdev->dev, "Detected %s!\n", 4628 hns3_hw_err[i].msg); 4629 break; 4630 } 4631 } 4632 } 4633 4634 static const struct hnae3_client_ops client_ops = { 4635 .init_instance = hns3_client_init, 4636 .uninit_instance = hns3_client_uninit, 4637 .link_status_change = hns3_link_status_change, 4638 .setup_tc = hns3_client_setup_tc, 4639 .reset_notify = hns3_reset_notify, 4640 .process_hw_error = hns3_process_hw_error, 4641 }; 4642 4643 /* hns3_init_module - Driver registration routine 4644 * hns3_init_module is the first routine called when the driver is 4645 * loaded. All it does is register with the PCI subsystem. 4646 */ 4647 static int __init hns3_init_module(void) 4648 { 4649 int ret; 4650 4651 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 4652 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 4653 4654 client.type = HNAE3_CLIENT_KNIC; 4655 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s", 4656 hns3_driver_name); 4657 4658 client.ops = &client_ops; 4659 4660 INIT_LIST_HEAD(&client.node); 4661 4662 hns3_dbg_register_debugfs(hns3_driver_name); 4663 4664 ret = hnae3_register_client(&client); 4665 if (ret) 4666 goto err_reg_client; 4667 4668 ret = pci_register_driver(&hns3_driver); 4669 if (ret) 4670 goto err_reg_driver; 4671 4672 return ret; 4673 4674 err_reg_driver: 4675 hnae3_unregister_client(&client); 4676 err_reg_client: 4677 hns3_dbg_unregister_debugfs(); 4678 return ret; 4679 } 4680 module_init(hns3_init_module); 4681 4682 /* hns3_exit_module - Driver exit cleanup routine 4683 * hns3_exit_module is called just before the driver is removed 4684 * from memory. 4685 */ 4686 static void __exit hns3_exit_module(void) 4687 { 4688 pci_unregister_driver(&hns3_driver); 4689 hnae3_unregister_client(&client); 4690 hns3_dbg_unregister_debugfs(); 4691 } 4692 module_exit(hns3_exit_module); 4693 4694 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 4695 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 4696 MODULE_LICENSE("GPL"); 4697 MODULE_ALIAS("pci:hns-nic"); 4698 MODULE_VERSION(HNS3_MOD_VERSION); 4699