1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #ifdef CONFIG_RFS_ACCEL 8 #include <linux/cpu_rmap.h> 9 #endif 10 #include <linux/if_vlan.h> 11 #include <linux/irq.h> 12 #include <linux/ip.h> 13 #include <linux/ipv6.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/aer.h> 17 #include <linux/skbuff.h> 18 #include <linux/sctp.h> 19 #include <net/gre.h> 20 #include <net/ip6_checksum.h> 21 #include <net/pkt_cls.h> 22 #include <net/tcp.h> 23 #include <net/vxlan.h> 24 #include <net/geneve.h> 25 26 #include "hnae3.h" 27 #include "hns3_enet.h" 28 /* All hns3 tracepoints are defined by the include below, which 29 * must be included exactly once across the whole kernel with 30 * CREATE_TRACE_POINTS defined 31 */ 32 #define CREATE_TRACE_POINTS 33 #include "hns3_trace.h" 34 35 #define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift)) 36 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE) 37 38 #define hns3_rl_err(fmt, ...) \ 39 do { \ 40 if (net_ratelimit()) \ 41 netdev_err(fmt, ##__VA_ARGS__); \ 42 } while (0) 43 44 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force); 45 46 static const char hns3_driver_name[] = "hns3"; 47 static const char hns3_driver_string[] = 48 "Hisilicon Ethernet Network Driver for Hip08 Family"; 49 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 50 static struct hnae3_client client; 51 52 static int debug = -1; 53 module_param(debug, int, 0); 54 MODULE_PARM_DESC(debug, " Network interface message level setting"); 55 56 static unsigned int tx_spare_buf_size; 57 module_param(tx_spare_buf_size, uint, 0400); 58 MODULE_PARM_DESC(tx_spare_buf_size, "Size used to allocate tx spare buffer"); 59 60 static unsigned int tx_sgl = 1; 61 module_param(tx_sgl, uint, 0600); 62 MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping"); 63 64 static bool page_pool_enabled = true; 65 module_param(page_pool_enabled, bool, 0400); 66 67 #define HNS3_SGL_SIZE(nfrag) (sizeof(struct scatterlist) * (nfrag) + \ 68 sizeof(struct sg_table)) 69 #define HNS3_MAX_SGL_SIZE ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \ 70 dma_get_cache_alignment()) 71 72 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 73 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) 74 75 #define HNS3_INNER_VLAN_TAG 1 76 #define HNS3_OUTER_VLAN_TAG 2 77 78 #define HNS3_MIN_TX_LEN 33U 79 #define HNS3_MIN_TUN_PKT_LEN 65U 80 81 /* hns3_pci_tbl - PCI Device ID Table 82 * 83 * Last entry must be all 0s 84 * 85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 86 * Class, Class Mask, private data (not used) } 87 */ 88 static const struct pci_device_id hns3_pci_tbl[] = { 89 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 90 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 91 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 92 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 93 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 94 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 95 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 96 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 97 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 98 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 99 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 100 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 101 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 102 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 103 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 104 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 105 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 106 /* required last entry */ 107 {0,} 108 }; 109 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 110 111 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t) \ 112 { ptype, \ 113 l, \ 114 CHECKSUM_##s, \ 115 HNS3_L3_TYPE_##t, \ 116 1 } 117 118 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \ 119 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0 } 120 121 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = { 122 HNS3_RX_PTYPE_UNUSED_ENTRY(0), 123 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP), 124 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP), 125 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP), 126 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL), 127 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL), 128 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL), 129 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM), 130 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL), 131 HNS3_RX_PTYPE_UNUSED_ENTRY(9), 132 HNS3_RX_PTYPE_UNUSED_ENTRY(10), 133 HNS3_RX_PTYPE_UNUSED_ENTRY(11), 134 HNS3_RX_PTYPE_UNUSED_ENTRY(12), 135 HNS3_RX_PTYPE_UNUSED_ENTRY(13), 136 HNS3_RX_PTYPE_UNUSED_ENTRY(14), 137 HNS3_RX_PTYPE_UNUSED_ENTRY(15), 138 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL), 139 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4), 140 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4), 141 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4), 142 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4), 143 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4), 144 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4), 145 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4), 146 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4), 147 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4), 148 HNS3_RX_PTYPE_UNUSED_ENTRY(26), 149 HNS3_RX_PTYPE_UNUSED_ENTRY(27), 150 HNS3_RX_PTYPE_UNUSED_ENTRY(28), 151 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL), 152 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL), 153 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4), 154 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4), 155 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4), 156 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4), 157 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4), 158 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4), 159 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4), 160 HNS3_RX_PTYPE_UNUSED_ENTRY(38), 161 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6), 162 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6), 163 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6), 164 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6), 165 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6), 166 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6), 167 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6), 168 HNS3_RX_PTYPE_UNUSED_ENTRY(46), 169 HNS3_RX_PTYPE_UNUSED_ENTRY(47), 170 HNS3_RX_PTYPE_UNUSED_ENTRY(48), 171 HNS3_RX_PTYPE_UNUSED_ENTRY(49), 172 HNS3_RX_PTYPE_UNUSED_ENTRY(50), 173 HNS3_RX_PTYPE_UNUSED_ENTRY(51), 174 HNS3_RX_PTYPE_UNUSED_ENTRY(52), 175 HNS3_RX_PTYPE_UNUSED_ENTRY(53), 176 HNS3_RX_PTYPE_UNUSED_ENTRY(54), 177 HNS3_RX_PTYPE_UNUSED_ENTRY(55), 178 HNS3_RX_PTYPE_UNUSED_ENTRY(56), 179 HNS3_RX_PTYPE_UNUSED_ENTRY(57), 180 HNS3_RX_PTYPE_UNUSED_ENTRY(58), 181 HNS3_RX_PTYPE_UNUSED_ENTRY(59), 182 HNS3_RX_PTYPE_UNUSED_ENTRY(60), 183 HNS3_RX_PTYPE_UNUSED_ENTRY(61), 184 HNS3_RX_PTYPE_UNUSED_ENTRY(62), 185 HNS3_RX_PTYPE_UNUSED_ENTRY(63), 186 HNS3_RX_PTYPE_UNUSED_ENTRY(64), 187 HNS3_RX_PTYPE_UNUSED_ENTRY(65), 188 HNS3_RX_PTYPE_UNUSED_ENTRY(66), 189 HNS3_RX_PTYPE_UNUSED_ENTRY(67), 190 HNS3_RX_PTYPE_UNUSED_ENTRY(68), 191 HNS3_RX_PTYPE_UNUSED_ENTRY(69), 192 HNS3_RX_PTYPE_UNUSED_ENTRY(70), 193 HNS3_RX_PTYPE_UNUSED_ENTRY(71), 194 HNS3_RX_PTYPE_UNUSED_ENTRY(72), 195 HNS3_RX_PTYPE_UNUSED_ENTRY(73), 196 HNS3_RX_PTYPE_UNUSED_ENTRY(74), 197 HNS3_RX_PTYPE_UNUSED_ENTRY(75), 198 HNS3_RX_PTYPE_UNUSED_ENTRY(76), 199 HNS3_RX_PTYPE_UNUSED_ENTRY(77), 200 HNS3_RX_PTYPE_UNUSED_ENTRY(78), 201 HNS3_RX_PTYPE_UNUSED_ENTRY(79), 202 HNS3_RX_PTYPE_UNUSED_ENTRY(80), 203 HNS3_RX_PTYPE_UNUSED_ENTRY(81), 204 HNS3_RX_PTYPE_UNUSED_ENTRY(82), 205 HNS3_RX_PTYPE_UNUSED_ENTRY(83), 206 HNS3_RX_PTYPE_UNUSED_ENTRY(84), 207 HNS3_RX_PTYPE_UNUSED_ENTRY(85), 208 HNS3_RX_PTYPE_UNUSED_ENTRY(86), 209 HNS3_RX_PTYPE_UNUSED_ENTRY(87), 210 HNS3_RX_PTYPE_UNUSED_ENTRY(88), 211 HNS3_RX_PTYPE_UNUSED_ENTRY(89), 212 HNS3_RX_PTYPE_UNUSED_ENTRY(90), 213 HNS3_RX_PTYPE_UNUSED_ENTRY(91), 214 HNS3_RX_PTYPE_UNUSED_ENTRY(92), 215 HNS3_RX_PTYPE_UNUSED_ENTRY(93), 216 HNS3_RX_PTYPE_UNUSED_ENTRY(94), 217 HNS3_RX_PTYPE_UNUSED_ENTRY(95), 218 HNS3_RX_PTYPE_UNUSED_ENTRY(96), 219 HNS3_RX_PTYPE_UNUSED_ENTRY(97), 220 HNS3_RX_PTYPE_UNUSED_ENTRY(98), 221 HNS3_RX_PTYPE_UNUSED_ENTRY(99), 222 HNS3_RX_PTYPE_UNUSED_ENTRY(100), 223 HNS3_RX_PTYPE_UNUSED_ENTRY(101), 224 HNS3_RX_PTYPE_UNUSED_ENTRY(102), 225 HNS3_RX_PTYPE_UNUSED_ENTRY(103), 226 HNS3_RX_PTYPE_UNUSED_ENTRY(104), 227 HNS3_RX_PTYPE_UNUSED_ENTRY(105), 228 HNS3_RX_PTYPE_UNUSED_ENTRY(106), 229 HNS3_RX_PTYPE_UNUSED_ENTRY(107), 230 HNS3_RX_PTYPE_UNUSED_ENTRY(108), 231 HNS3_RX_PTYPE_UNUSED_ENTRY(109), 232 HNS3_RX_PTYPE_UNUSED_ENTRY(110), 233 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6), 234 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6), 235 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6), 236 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6), 237 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6), 238 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6), 239 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6), 240 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6), 241 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6), 242 HNS3_RX_PTYPE_UNUSED_ENTRY(120), 243 HNS3_RX_PTYPE_UNUSED_ENTRY(121), 244 HNS3_RX_PTYPE_UNUSED_ENTRY(122), 245 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL), 246 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL), 247 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4), 248 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4), 249 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4), 250 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4), 251 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4), 252 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4), 253 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4), 254 HNS3_RX_PTYPE_UNUSED_ENTRY(132), 255 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6), 256 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6), 257 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6), 258 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6), 259 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6), 260 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6), 261 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6), 262 HNS3_RX_PTYPE_UNUSED_ENTRY(140), 263 HNS3_RX_PTYPE_UNUSED_ENTRY(141), 264 HNS3_RX_PTYPE_UNUSED_ENTRY(142), 265 HNS3_RX_PTYPE_UNUSED_ENTRY(143), 266 HNS3_RX_PTYPE_UNUSED_ENTRY(144), 267 HNS3_RX_PTYPE_UNUSED_ENTRY(145), 268 HNS3_RX_PTYPE_UNUSED_ENTRY(146), 269 HNS3_RX_PTYPE_UNUSED_ENTRY(147), 270 HNS3_RX_PTYPE_UNUSED_ENTRY(148), 271 HNS3_RX_PTYPE_UNUSED_ENTRY(149), 272 HNS3_RX_PTYPE_UNUSED_ENTRY(150), 273 HNS3_RX_PTYPE_UNUSED_ENTRY(151), 274 HNS3_RX_PTYPE_UNUSED_ENTRY(152), 275 HNS3_RX_PTYPE_UNUSED_ENTRY(153), 276 HNS3_RX_PTYPE_UNUSED_ENTRY(154), 277 HNS3_RX_PTYPE_UNUSED_ENTRY(155), 278 HNS3_RX_PTYPE_UNUSED_ENTRY(156), 279 HNS3_RX_PTYPE_UNUSED_ENTRY(157), 280 HNS3_RX_PTYPE_UNUSED_ENTRY(158), 281 HNS3_RX_PTYPE_UNUSED_ENTRY(159), 282 HNS3_RX_PTYPE_UNUSED_ENTRY(160), 283 HNS3_RX_PTYPE_UNUSED_ENTRY(161), 284 HNS3_RX_PTYPE_UNUSED_ENTRY(162), 285 HNS3_RX_PTYPE_UNUSED_ENTRY(163), 286 HNS3_RX_PTYPE_UNUSED_ENTRY(164), 287 HNS3_RX_PTYPE_UNUSED_ENTRY(165), 288 HNS3_RX_PTYPE_UNUSED_ENTRY(166), 289 HNS3_RX_PTYPE_UNUSED_ENTRY(167), 290 HNS3_RX_PTYPE_UNUSED_ENTRY(168), 291 HNS3_RX_PTYPE_UNUSED_ENTRY(169), 292 HNS3_RX_PTYPE_UNUSED_ENTRY(170), 293 HNS3_RX_PTYPE_UNUSED_ENTRY(171), 294 HNS3_RX_PTYPE_UNUSED_ENTRY(172), 295 HNS3_RX_PTYPE_UNUSED_ENTRY(173), 296 HNS3_RX_PTYPE_UNUSED_ENTRY(174), 297 HNS3_RX_PTYPE_UNUSED_ENTRY(175), 298 HNS3_RX_PTYPE_UNUSED_ENTRY(176), 299 HNS3_RX_PTYPE_UNUSED_ENTRY(177), 300 HNS3_RX_PTYPE_UNUSED_ENTRY(178), 301 HNS3_RX_PTYPE_UNUSED_ENTRY(179), 302 HNS3_RX_PTYPE_UNUSED_ENTRY(180), 303 HNS3_RX_PTYPE_UNUSED_ENTRY(181), 304 HNS3_RX_PTYPE_UNUSED_ENTRY(182), 305 HNS3_RX_PTYPE_UNUSED_ENTRY(183), 306 HNS3_RX_PTYPE_UNUSED_ENTRY(184), 307 HNS3_RX_PTYPE_UNUSED_ENTRY(185), 308 HNS3_RX_PTYPE_UNUSED_ENTRY(186), 309 HNS3_RX_PTYPE_UNUSED_ENTRY(187), 310 HNS3_RX_PTYPE_UNUSED_ENTRY(188), 311 HNS3_RX_PTYPE_UNUSED_ENTRY(189), 312 HNS3_RX_PTYPE_UNUSED_ENTRY(190), 313 HNS3_RX_PTYPE_UNUSED_ENTRY(191), 314 HNS3_RX_PTYPE_UNUSED_ENTRY(192), 315 HNS3_RX_PTYPE_UNUSED_ENTRY(193), 316 HNS3_RX_PTYPE_UNUSED_ENTRY(194), 317 HNS3_RX_PTYPE_UNUSED_ENTRY(195), 318 HNS3_RX_PTYPE_UNUSED_ENTRY(196), 319 HNS3_RX_PTYPE_UNUSED_ENTRY(197), 320 HNS3_RX_PTYPE_UNUSED_ENTRY(198), 321 HNS3_RX_PTYPE_UNUSED_ENTRY(199), 322 HNS3_RX_PTYPE_UNUSED_ENTRY(200), 323 HNS3_RX_PTYPE_UNUSED_ENTRY(201), 324 HNS3_RX_PTYPE_UNUSED_ENTRY(202), 325 HNS3_RX_PTYPE_UNUSED_ENTRY(203), 326 HNS3_RX_PTYPE_UNUSED_ENTRY(204), 327 HNS3_RX_PTYPE_UNUSED_ENTRY(205), 328 HNS3_RX_PTYPE_UNUSED_ENTRY(206), 329 HNS3_RX_PTYPE_UNUSED_ENTRY(207), 330 HNS3_RX_PTYPE_UNUSED_ENTRY(208), 331 HNS3_RX_PTYPE_UNUSED_ENTRY(209), 332 HNS3_RX_PTYPE_UNUSED_ENTRY(210), 333 HNS3_RX_PTYPE_UNUSED_ENTRY(211), 334 HNS3_RX_PTYPE_UNUSED_ENTRY(212), 335 HNS3_RX_PTYPE_UNUSED_ENTRY(213), 336 HNS3_RX_PTYPE_UNUSED_ENTRY(214), 337 HNS3_RX_PTYPE_UNUSED_ENTRY(215), 338 HNS3_RX_PTYPE_UNUSED_ENTRY(216), 339 HNS3_RX_PTYPE_UNUSED_ENTRY(217), 340 HNS3_RX_PTYPE_UNUSED_ENTRY(218), 341 HNS3_RX_PTYPE_UNUSED_ENTRY(219), 342 HNS3_RX_PTYPE_UNUSED_ENTRY(220), 343 HNS3_RX_PTYPE_UNUSED_ENTRY(221), 344 HNS3_RX_PTYPE_UNUSED_ENTRY(222), 345 HNS3_RX_PTYPE_UNUSED_ENTRY(223), 346 HNS3_RX_PTYPE_UNUSED_ENTRY(224), 347 HNS3_RX_PTYPE_UNUSED_ENTRY(225), 348 HNS3_RX_PTYPE_UNUSED_ENTRY(226), 349 HNS3_RX_PTYPE_UNUSED_ENTRY(227), 350 HNS3_RX_PTYPE_UNUSED_ENTRY(228), 351 HNS3_RX_PTYPE_UNUSED_ENTRY(229), 352 HNS3_RX_PTYPE_UNUSED_ENTRY(230), 353 HNS3_RX_PTYPE_UNUSED_ENTRY(231), 354 HNS3_RX_PTYPE_UNUSED_ENTRY(232), 355 HNS3_RX_PTYPE_UNUSED_ENTRY(233), 356 HNS3_RX_PTYPE_UNUSED_ENTRY(234), 357 HNS3_RX_PTYPE_UNUSED_ENTRY(235), 358 HNS3_RX_PTYPE_UNUSED_ENTRY(236), 359 HNS3_RX_PTYPE_UNUSED_ENTRY(237), 360 HNS3_RX_PTYPE_UNUSED_ENTRY(238), 361 HNS3_RX_PTYPE_UNUSED_ENTRY(239), 362 HNS3_RX_PTYPE_UNUSED_ENTRY(240), 363 HNS3_RX_PTYPE_UNUSED_ENTRY(241), 364 HNS3_RX_PTYPE_UNUSED_ENTRY(242), 365 HNS3_RX_PTYPE_UNUSED_ENTRY(243), 366 HNS3_RX_PTYPE_UNUSED_ENTRY(244), 367 HNS3_RX_PTYPE_UNUSED_ENTRY(245), 368 HNS3_RX_PTYPE_UNUSED_ENTRY(246), 369 HNS3_RX_PTYPE_UNUSED_ENTRY(247), 370 HNS3_RX_PTYPE_UNUSED_ENTRY(248), 371 HNS3_RX_PTYPE_UNUSED_ENTRY(249), 372 HNS3_RX_PTYPE_UNUSED_ENTRY(250), 373 HNS3_RX_PTYPE_UNUSED_ENTRY(251), 374 HNS3_RX_PTYPE_UNUSED_ENTRY(252), 375 HNS3_RX_PTYPE_UNUSED_ENTRY(253), 376 HNS3_RX_PTYPE_UNUSED_ENTRY(254), 377 HNS3_RX_PTYPE_UNUSED_ENTRY(255), 378 }; 379 380 #define HNS3_INVALID_PTYPE \ 381 ARRAY_SIZE(hns3_rx_ptype_tbl) 382 383 static irqreturn_t hns3_irq_handle(int irq, void *vector) 384 { 385 struct hns3_enet_tqp_vector *tqp_vector = vector; 386 387 napi_schedule_irqoff(&tqp_vector->napi); 388 tqp_vector->event_cnt++; 389 390 return IRQ_HANDLED; 391 } 392 393 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 394 { 395 struct hns3_enet_tqp_vector *tqp_vectors; 396 unsigned int i; 397 398 for (i = 0; i < priv->vector_num; i++) { 399 tqp_vectors = &priv->tqp_vector[i]; 400 401 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 402 continue; 403 404 /* clear the affinity mask */ 405 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 406 407 /* release the irq resource */ 408 free_irq(tqp_vectors->vector_irq, tqp_vectors); 409 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 410 } 411 } 412 413 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 414 { 415 struct hns3_enet_tqp_vector *tqp_vectors; 416 int txrx_int_idx = 0; 417 int rx_int_idx = 0; 418 int tx_int_idx = 0; 419 unsigned int i; 420 int ret; 421 422 for (i = 0; i < priv->vector_num; i++) { 423 tqp_vectors = &priv->tqp_vector[i]; 424 425 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 426 continue; 427 428 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 429 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 430 "%s-%s-%s-%d", hns3_driver_name, 431 pci_name(priv->ae_handle->pdev), 432 "TxRx", txrx_int_idx++); 433 txrx_int_idx++; 434 } else if (tqp_vectors->rx_group.ring) { 435 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 436 "%s-%s-%s-%d", hns3_driver_name, 437 pci_name(priv->ae_handle->pdev), 438 "Rx", rx_int_idx++); 439 } else if (tqp_vectors->tx_group.ring) { 440 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 441 "%s-%s-%s-%d", hns3_driver_name, 442 pci_name(priv->ae_handle->pdev), 443 "Tx", tx_int_idx++); 444 } else { 445 /* Skip this unused q_vector */ 446 continue; 447 } 448 449 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 450 451 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN); 452 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 453 tqp_vectors->name, tqp_vectors); 454 if (ret) { 455 netdev_err(priv->netdev, "request irq(%d) fail\n", 456 tqp_vectors->vector_irq); 457 hns3_nic_uninit_irq(priv); 458 return ret; 459 } 460 461 irq_set_affinity_hint(tqp_vectors->vector_irq, 462 &tqp_vectors->affinity_mask); 463 464 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 465 } 466 467 return 0; 468 } 469 470 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 471 u32 mask_en) 472 { 473 writel(mask_en, tqp_vector->mask_addr); 474 } 475 476 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 477 { 478 napi_enable(&tqp_vector->napi); 479 enable_irq(tqp_vector->vector_irq); 480 481 /* enable vector */ 482 hns3_mask_vector_irq(tqp_vector, 1); 483 } 484 485 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 486 { 487 /* disable vector */ 488 hns3_mask_vector_irq(tqp_vector, 0); 489 490 disable_irq(tqp_vector->vector_irq); 491 napi_disable(&tqp_vector->napi); 492 cancel_work_sync(&tqp_vector->rx_group.dim.work); 493 cancel_work_sync(&tqp_vector->tx_group.dim.work); 494 } 495 496 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 497 u32 rl_value) 498 { 499 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 500 501 /* this defines the configuration for RL (Interrupt Rate Limiter). 502 * Rl defines rate of interrupts i.e. number of interrupts-per-second 503 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 504 */ 505 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable && 506 !tqp_vector->rx_group.coal.adapt_enable) 507 /* According to the hardware, the range of rl_reg is 508 * 0-59 and the unit is 4. 509 */ 510 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 511 512 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 513 } 514 515 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 516 u32 gl_value) 517 { 518 u32 new_val; 519 520 if (tqp_vector->rx_group.coal.unit_1us) 521 new_val = gl_value | HNS3_INT_GL_1US; 522 else 523 new_val = hns3_gl_usec_to_reg(gl_value); 524 525 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 526 } 527 528 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 529 u32 gl_value) 530 { 531 u32 new_val; 532 533 if (tqp_vector->tx_group.coal.unit_1us) 534 new_val = gl_value | HNS3_INT_GL_1US; 535 else 536 new_val = hns3_gl_usec_to_reg(gl_value); 537 538 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 539 } 540 541 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector, 542 u32 ql_value) 543 { 544 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET); 545 } 546 547 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector, 548 u32 ql_value) 549 { 550 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET); 551 } 552 553 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector, 554 struct hns3_nic_priv *priv) 555 { 556 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 557 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 558 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 559 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal; 560 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal; 561 562 tx_coal->adapt_enable = ptx_coal->adapt_enable; 563 rx_coal->adapt_enable = prx_coal->adapt_enable; 564 565 tx_coal->int_gl = ptx_coal->int_gl; 566 rx_coal->int_gl = prx_coal->int_gl; 567 568 rx_coal->flow_level = prx_coal->flow_level; 569 tx_coal->flow_level = ptx_coal->flow_level; 570 571 /* device version above V3(include V3), GL can configure 1us 572 * unit, so uses 1us unit. 573 */ 574 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) { 575 tx_coal->unit_1us = 1; 576 rx_coal->unit_1us = 1; 577 } 578 579 if (ae_dev->dev_specs.int_ql_max) { 580 tx_coal->ql_enable = 1; 581 rx_coal->ql_enable = 1; 582 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 583 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 584 tx_coal->int_ql = ptx_coal->int_ql; 585 rx_coal->int_ql = prx_coal->int_ql; 586 } 587 } 588 589 static void 590 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 591 struct hns3_nic_priv *priv) 592 { 593 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 594 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 595 struct hnae3_handle *h = priv->ae_handle; 596 597 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl); 598 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl); 599 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 600 601 if (tx_coal->ql_enable) 602 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql); 603 604 if (rx_coal->ql_enable) 605 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql); 606 } 607 608 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 609 { 610 struct hnae3_handle *h = hns3_get_handle(netdev); 611 struct hnae3_knic_private_info *kinfo = &h->kinfo; 612 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 613 unsigned int queue_size = kinfo->num_tqps; 614 int i, ret; 615 616 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) { 617 netdev_reset_tc(netdev); 618 } else { 619 ret = netdev_set_num_tc(netdev, tc_info->num_tc); 620 if (ret) { 621 netdev_err(netdev, 622 "netdev_set_num_tc fail, ret=%d!\n", ret); 623 return ret; 624 } 625 626 for (i = 0; i < HNAE3_MAX_TC; i++) { 627 if (!test_bit(i, &tc_info->tc_en)) 628 continue; 629 630 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i], 631 tc_info->tqp_offset[i]); 632 } 633 } 634 635 ret = netif_set_real_num_tx_queues(netdev, queue_size); 636 if (ret) { 637 netdev_err(netdev, 638 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret); 639 return ret; 640 } 641 642 ret = netif_set_real_num_rx_queues(netdev, queue_size); 643 if (ret) { 644 netdev_err(netdev, 645 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 646 return ret; 647 } 648 649 return 0; 650 } 651 652 u16 hns3_get_max_available_channels(struct hnae3_handle *h) 653 { 654 u16 alloc_tqps, max_rss_size, rss_size; 655 656 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 657 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc; 658 659 return min_t(u16, rss_size, max_rss_size); 660 } 661 662 static void hns3_tqp_enable(struct hnae3_queue *tqp) 663 { 664 u32 rcb_reg; 665 666 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 667 rcb_reg |= BIT(HNS3_RING_EN_B); 668 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 669 } 670 671 static void hns3_tqp_disable(struct hnae3_queue *tqp) 672 { 673 u32 rcb_reg; 674 675 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 676 rcb_reg &= ~BIT(HNS3_RING_EN_B); 677 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 678 } 679 680 static void hns3_free_rx_cpu_rmap(struct net_device *netdev) 681 { 682 #ifdef CONFIG_RFS_ACCEL 683 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 684 netdev->rx_cpu_rmap = NULL; 685 #endif 686 } 687 688 static int hns3_set_rx_cpu_rmap(struct net_device *netdev) 689 { 690 #ifdef CONFIG_RFS_ACCEL 691 struct hns3_nic_priv *priv = netdev_priv(netdev); 692 struct hns3_enet_tqp_vector *tqp_vector; 693 int i, ret; 694 695 if (!netdev->rx_cpu_rmap) { 696 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num); 697 if (!netdev->rx_cpu_rmap) 698 return -ENOMEM; 699 } 700 701 for (i = 0; i < priv->vector_num; i++) { 702 tqp_vector = &priv->tqp_vector[i]; 703 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap, 704 tqp_vector->vector_irq); 705 if (ret) { 706 hns3_free_rx_cpu_rmap(netdev); 707 return ret; 708 } 709 } 710 #endif 711 return 0; 712 } 713 714 static int hns3_nic_net_up(struct net_device *netdev) 715 { 716 struct hns3_nic_priv *priv = netdev_priv(netdev); 717 struct hnae3_handle *h = priv->ae_handle; 718 int i, j; 719 int ret; 720 721 ret = hns3_nic_reset_all_ring(h); 722 if (ret) 723 return ret; 724 725 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 726 727 /* enable the vectors */ 728 for (i = 0; i < priv->vector_num; i++) 729 hns3_vector_enable(&priv->tqp_vector[i]); 730 731 /* enable rcb */ 732 for (j = 0; j < h->kinfo.num_tqps; j++) 733 hns3_tqp_enable(h->kinfo.tqp[j]); 734 735 /* start the ae_dev */ 736 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 737 if (ret) { 738 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 739 while (j--) 740 hns3_tqp_disable(h->kinfo.tqp[j]); 741 742 for (j = i - 1; j >= 0; j--) 743 hns3_vector_disable(&priv->tqp_vector[j]); 744 } 745 746 return ret; 747 } 748 749 static void hns3_config_xps(struct hns3_nic_priv *priv) 750 { 751 int i; 752 753 for (i = 0; i < priv->vector_num; i++) { 754 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 755 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 756 757 while (ring) { 758 int ret; 759 760 ret = netif_set_xps_queue(priv->netdev, 761 &tqp_vector->affinity_mask, 762 ring->tqp->tqp_index); 763 if (ret) 764 netdev_warn(priv->netdev, 765 "set xps queue failed: %d", ret); 766 767 ring = ring->next; 768 } 769 } 770 } 771 772 static int hns3_nic_net_open(struct net_device *netdev) 773 { 774 struct hns3_nic_priv *priv = netdev_priv(netdev); 775 struct hnae3_handle *h = hns3_get_handle(netdev); 776 struct hnae3_knic_private_info *kinfo; 777 int i, ret; 778 779 if (hns3_nic_resetting(netdev)) 780 return -EBUSY; 781 782 netif_carrier_off(netdev); 783 784 ret = hns3_nic_set_real_num_queue(netdev); 785 if (ret) 786 return ret; 787 788 ret = hns3_nic_net_up(netdev); 789 if (ret) { 790 netdev_err(netdev, "net up fail, ret=%d!\n", ret); 791 return ret; 792 } 793 794 kinfo = &h->kinfo; 795 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 796 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]); 797 798 if (h->ae_algo->ops->set_timer_task) 799 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 800 801 hns3_config_xps(priv); 802 803 netif_dbg(h, drv, netdev, "net open\n"); 804 805 return 0; 806 } 807 808 static void hns3_reset_tx_queue(struct hnae3_handle *h) 809 { 810 struct net_device *ndev = h->kinfo.netdev; 811 struct hns3_nic_priv *priv = netdev_priv(ndev); 812 struct netdev_queue *dev_queue; 813 u32 i; 814 815 for (i = 0; i < h->kinfo.num_tqps; i++) { 816 dev_queue = netdev_get_tx_queue(ndev, 817 priv->ring[i].queue_index); 818 netdev_tx_reset_queue(dev_queue); 819 } 820 } 821 822 static void hns3_nic_net_down(struct net_device *netdev) 823 { 824 struct hns3_nic_priv *priv = netdev_priv(netdev); 825 struct hnae3_handle *h = hns3_get_handle(netdev); 826 const struct hnae3_ae_ops *ops; 827 int i; 828 829 /* disable vectors */ 830 for (i = 0; i < priv->vector_num; i++) 831 hns3_vector_disable(&priv->tqp_vector[i]); 832 833 /* disable rcb */ 834 for (i = 0; i < h->kinfo.num_tqps; i++) 835 hns3_tqp_disable(h->kinfo.tqp[i]); 836 837 /* stop ae_dev */ 838 ops = priv->ae_handle->ae_algo->ops; 839 if (ops->stop) 840 ops->stop(priv->ae_handle); 841 842 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 843 * during reset process, because driver may not be able 844 * to disable the ring through firmware when downing the netdev. 845 */ 846 if (!hns3_nic_resetting(netdev)) 847 hns3_clear_all_ring(priv->ae_handle, false); 848 849 hns3_reset_tx_queue(priv->ae_handle); 850 } 851 852 static int hns3_nic_net_stop(struct net_device *netdev) 853 { 854 struct hns3_nic_priv *priv = netdev_priv(netdev); 855 struct hnae3_handle *h = hns3_get_handle(netdev); 856 857 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 858 return 0; 859 860 netif_dbg(h, drv, netdev, "net stop\n"); 861 862 if (h->ae_algo->ops->set_timer_task) 863 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 864 865 netif_carrier_off(netdev); 866 netif_tx_disable(netdev); 867 868 hns3_nic_net_down(netdev); 869 870 return 0; 871 } 872 873 static int hns3_nic_uc_sync(struct net_device *netdev, 874 const unsigned char *addr) 875 { 876 struct hnae3_handle *h = hns3_get_handle(netdev); 877 878 if (h->ae_algo->ops->add_uc_addr) 879 return h->ae_algo->ops->add_uc_addr(h, addr); 880 881 return 0; 882 } 883 884 static int hns3_nic_uc_unsync(struct net_device *netdev, 885 const unsigned char *addr) 886 { 887 struct hnae3_handle *h = hns3_get_handle(netdev); 888 889 /* need ignore the request of removing device address, because 890 * we store the device address and other addresses of uc list 891 * in the function's mac filter list. 892 */ 893 if (ether_addr_equal(addr, netdev->dev_addr)) 894 return 0; 895 896 if (h->ae_algo->ops->rm_uc_addr) 897 return h->ae_algo->ops->rm_uc_addr(h, addr); 898 899 return 0; 900 } 901 902 static int hns3_nic_mc_sync(struct net_device *netdev, 903 const unsigned char *addr) 904 { 905 struct hnae3_handle *h = hns3_get_handle(netdev); 906 907 if (h->ae_algo->ops->add_mc_addr) 908 return h->ae_algo->ops->add_mc_addr(h, addr); 909 910 return 0; 911 } 912 913 static int hns3_nic_mc_unsync(struct net_device *netdev, 914 const unsigned char *addr) 915 { 916 struct hnae3_handle *h = hns3_get_handle(netdev); 917 918 if (h->ae_algo->ops->rm_mc_addr) 919 return h->ae_algo->ops->rm_mc_addr(h, addr); 920 921 return 0; 922 } 923 924 static u8 hns3_get_netdev_flags(struct net_device *netdev) 925 { 926 u8 flags = 0; 927 928 if (netdev->flags & IFF_PROMISC) 929 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 930 else if (netdev->flags & IFF_ALLMULTI) 931 flags = HNAE3_USER_MPE; 932 933 return flags; 934 } 935 936 static void hns3_nic_set_rx_mode(struct net_device *netdev) 937 { 938 struct hnae3_handle *h = hns3_get_handle(netdev); 939 u8 new_flags; 940 941 new_flags = hns3_get_netdev_flags(netdev); 942 943 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 944 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync); 945 946 /* User mode Promisc mode enable and vlan filtering is disabled to 947 * let all packets in. 948 */ 949 h->netdev_flags = new_flags; 950 hns3_request_update_promisc_mode(h); 951 } 952 953 void hns3_request_update_promisc_mode(struct hnae3_handle *handle) 954 { 955 const struct hnae3_ae_ops *ops = handle->ae_algo->ops; 956 957 if (ops->request_update_promisc_mode) 958 ops->request_update_promisc_mode(handle); 959 } 960 961 static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring) 962 { 963 struct hns3_tx_spare *tx_spare = ring->tx_spare; 964 u32 ntc, ntu; 965 966 /* This smp_load_acquire() pairs with smp_store_release() in 967 * hns3_tx_spare_update() called in tx desc cleaning process. 968 */ 969 ntc = smp_load_acquire(&tx_spare->last_to_clean); 970 ntu = tx_spare->next_to_use; 971 972 if (ntc > ntu) 973 return ntc - ntu - 1; 974 975 /* The free tx buffer is divided into two part, so pick the 976 * larger one. 977 */ 978 return max(ntc, tx_spare->len - ntu) - 1; 979 } 980 981 static void hns3_tx_spare_update(struct hns3_enet_ring *ring) 982 { 983 struct hns3_tx_spare *tx_spare = ring->tx_spare; 984 985 if (!tx_spare || 986 tx_spare->last_to_clean == tx_spare->next_to_clean) 987 return; 988 989 /* This smp_store_release() pairs with smp_load_acquire() in 990 * hns3_tx_spare_space() called in xmit process. 991 */ 992 smp_store_release(&tx_spare->last_to_clean, 993 tx_spare->next_to_clean); 994 } 995 996 static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring, 997 struct sk_buff *skb, 998 u32 space) 999 { 1000 u32 len = skb->len <= ring->tx_copybreak ? skb->len : 1001 skb_headlen(skb); 1002 1003 if (len > ring->tx_copybreak) 1004 return false; 1005 1006 if (ALIGN(len, dma_get_cache_alignment()) > space) { 1007 u64_stats_update_begin(&ring->syncp); 1008 ring->stats.tx_spare_full++; 1009 u64_stats_update_end(&ring->syncp); 1010 return false; 1011 } 1012 1013 return true; 1014 } 1015 1016 static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring, 1017 struct sk_buff *skb, 1018 u32 space) 1019 { 1020 if (skb->len <= ring->tx_copybreak || !tx_sgl || 1021 (!skb_has_frag_list(skb) && 1022 skb_shinfo(skb)->nr_frags < tx_sgl)) 1023 return false; 1024 1025 if (space < HNS3_MAX_SGL_SIZE) { 1026 u64_stats_update_begin(&ring->syncp); 1027 ring->stats.tx_spare_full++; 1028 u64_stats_update_end(&ring->syncp); 1029 return false; 1030 } 1031 1032 return true; 1033 } 1034 1035 static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring) 1036 { 1037 struct hns3_tx_spare *tx_spare; 1038 struct page *page; 1039 u32 alloc_size; 1040 dma_addr_t dma; 1041 int order; 1042 1043 alloc_size = tx_spare_buf_size ? tx_spare_buf_size : 1044 ring->tqp->handle->kinfo.tx_spare_buf_size; 1045 if (!alloc_size) 1046 return; 1047 1048 order = get_order(alloc_size); 1049 tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare), 1050 GFP_KERNEL); 1051 if (!tx_spare) { 1052 /* The driver still work without the tx spare buffer */ 1053 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n"); 1054 return; 1055 } 1056 1057 page = alloc_pages_node(dev_to_node(ring_to_dev(ring)), 1058 GFP_KERNEL, order); 1059 if (!page) { 1060 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n"); 1061 devm_kfree(ring_to_dev(ring), tx_spare); 1062 return; 1063 } 1064 1065 dma = dma_map_page(ring_to_dev(ring), page, 0, 1066 PAGE_SIZE << order, DMA_TO_DEVICE); 1067 if (dma_mapping_error(ring_to_dev(ring), dma)) { 1068 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n"); 1069 put_page(page); 1070 devm_kfree(ring_to_dev(ring), tx_spare); 1071 return; 1072 } 1073 1074 tx_spare->dma = dma; 1075 tx_spare->buf = page_address(page); 1076 tx_spare->len = PAGE_SIZE << order; 1077 ring->tx_spare = tx_spare; 1078 } 1079 1080 /* Use hns3_tx_spare_space() to make sure there is enough buffer 1081 * before calling below function to allocate tx buffer. 1082 */ 1083 static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring, 1084 unsigned int size, dma_addr_t *dma, 1085 u32 *cb_len) 1086 { 1087 struct hns3_tx_spare *tx_spare = ring->tx_spare; 1088 u32 ntu = tx_spare->next_to_use; 1089 1090 size = ALIGN(size, dma_get_cache_alignment()); 1091 *cb_len = size; 1092 1093 /* Tx spare buffer wraps back here because the end of 1094 * freed tx buffer is not enough. 1095 */ 1096 if (ntu + size > tx_spare->len) { 1097 *cb_len += (tx_spare->len - ntu); 1098 ntu = 0; 1099 } 1100 1101 tx_spare->next_to_use = ntu + size; 1102 if (tx_spare->next_to_use == tx_spare->len) 1103 tx_spare->next_to_use = 0; 1104 1105 *dma = tx_spare->dma + ntu; 1106 1107 return tx_spare->buf + ntu; 1108 } 1109 1110 static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len) 1111 { 1112 struct hns3_tx_spare *tx_spare = ring->tx_spare; 1113 1114 if (len > tx_spare->next_to_use) { 1115 len -= tx_spare->next_to_use; 1116 tx_spare->next_to_use = tx_spare->len - len; 1117 } else { 1118 tx_spare->next_to_use -= len; 1119 } 1120 } 1121 1122 static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring, 1123 struct hns3_desc_cb *cb) 1124 { 1125 struct hns3_tx_spare *tx_spare = ring->tx_spare; 1126 u32 ntc = tx_spare->next_to_clean; 1127 u32 len = cb->length; 1128 1129 tx_spare->next_to_clean += len; 1130 1131 if (tx_spare->next_to_clean >= tx_spare->len) { 1132 tx_spare->next_to_clean -= tx_spare->len; 1133 1134 if (tx_spare->next_to_clean) { 1135 ntc = 0; 1136 len = tx_spare->next_to_clean; 1137 } 1138 } 1139 1140 /* This tx spare buffer is only really reclaimed after calling 1141 * hns3_tx_spare_update(), so it is still safe to use the info in 1142 * the tx buffer to do the dma sync or sg unmapping after 1143 * tx_spare->next_to_clean is moved forword. 1144 */ 1145 if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) { 1146 dma_addr_t dma = tx_spare->dma + ntc; 1147 1148 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len, 1149 DMA_TO_DEVICE); 1150 } else { 1151 struct sg_table *sgt = tx_spare->buf + ntc; 1152 1153 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents, 1154 DMA_TO_DEVICE); 1155 } 1156 } 1157 1158 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs, 1159 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes) 1160 { 1161 u32 l4_offset, hdr_len; 1162 union l3_hdr_info l3; 1163 union l4_hdr_info l4; 1164 u32 l4_paylen; 1165 int ret; 1166 1167 if (!skb_is_gso(skb)) 1168 return 0; 1169 1170 ret = skb_cow_head(skb, 0); 1171 if (unlikely(ret < 0)) 1172 return ret; 1173 1174 l3.hdr = skb_network_header(skb); 1175 l4.hdr = skb_transport_header(skb); 1176 1177 /* Software should clear the IPv4's checksum field when tso is 1178 * needed. 1179 */ 1180 if (l3.v4->version == 4) 1181 l3.v4->check = 0; 1182 1183 /* tunnel packet */ 1184 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 1185 SKB_GSO_GRE_CSUM | 1186 SKB_GSO_UDP_TUNNEL | 1187 SKB_GSO_UDP_TUNNEL_CSUM)) { 1188 /* reset l3&l4 pointers from outer to inner headers */ 1189 l3.hdr = skb_inner_network_header(skb); 1190 l4.hdr = skb_inner_transport_header(skb); 1191 1192 /* Software should clear the IPv4's checksum field when 1193 * tso is needed. 1194 */ 1195 if (l3.v4->version == 4) 1196 l3.v4->check = 0; 1197 } 1198 1199 /* normal or tunnel packet */ 1200 l4_offset = l4.hdr - skb->data; 1201 1202 /* remove payload length from inner pseudo checksum when tso */ 1203 l4_paylen = skb->len - l4_offset; 1204 1205 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 1206 hdr_len = sizeof(*l4.udp) + l4_offset; 1207 csum_replace_by_diff(&l4.udp->check, 1208 (__force __wsum)htonl(l4_paylen)); 1209 } else { 1210 hdr_len = (l4.tcp->doff << 2) + l4_offset; 1211 csum_replace_by_diff(&l4.tcp->check, 1212 (__force __wsum)htonl(l4_paylen)); 1213 } 1214 1215 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len; 1216 1217 /* find the txbd field values */ 1218 *paylen_fdop_ol4cs = skb->len - hdr_len; 1219 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 1220 1221 /* offload outer UDP header checksum */ 1222 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM) 1223 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1); 1224 1225 /* get MSS for TSO */ 1226 *mss = skb_shinfo(skb)->gso_size; 1227 1228 trace_hns3_tso(skb); 1229 1230 return 0; 1231 } 1232 1233 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 1234 u8 *il4_proto) 1235 { 1236 union l3_hdr_info l3; 1237 unsigned char *l4_hdr; 1238 unsigned char *exthdr; 1239 u8 l4_proto_tmp; 1240 __be16 frag_off; 1241 1242 /* find outer header point */ 1243 l3.hdr = skb_network_header(skb); 1244 l4_hdr = skb_transport_header(skb); 1245 1246 if (skb->protocol == htons(ETH_P_IPV6)) { 1247 exthdr = l3.hdr + sizeof(*l3.v6); 1248 l4_proto_tmp = l3.v6->nexthdr; 1249 if (l4_hdr != exthdr) 1250 ipv6_skip_exthdr(skb, exthdr - skb->data, 1251 &l4_proto_tmp, &frag_off); 1252 } else if (skb->protocol == htons(ETH_P_IP)) { 1253 l4_proto_tmp = l3.v4->protocol; 1254 } else { 1255 return -EINVAL; 1256 } 1257 1258 *ol4_proto = l4_proto_tmp; 1259 1260 /* tunnel packet */ 1261 if (!skb->encapsulation) { 1262 *il4_proto = 0; 1263 return 0; 1264 } 1265 1266 /* find inner header point */ 1267 l3.hdr = skb_inner_network_header(skb); 1268 l4_hdr = skb_inner_transport_header(skb); 1269 1270 if (l3.v6->version == 6) { 1271 exthdr = l3.hdr + sizeof(*l3.v6); 1272 l4_proto_tmp = l3.v6->nexthdr; 1273 if (l4_hdr != exthdr) 1274 ipv6_skip_exthdr(skb, exthdr - skb->data, 1275 &l4_proto_tmp, &frag_off); 1276 } else if (l3.v4->version == 4) { 1277 l4_proto_tmp = l3.v4->protocol; 1278 } 1279 1280 *il4_proto = l4_proto_tmp; 1281 1282 return 0; 1283 } 1284 1285 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 1286 * and it is udp packet, which has a dest port as the IANA assigned. 1287 * the hardware is expected to do the checksum offload, but the 1288 * hardware will not do the checksum offload when udp dest port is 1289 * 4789, 4790 or 6081. 1290 */ 1291 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 1292 { 1293 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 1294 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 1295 union l4_hdr_info l4; 1296 1297 /* device version above V3(include V3), the hardware can 1298 * do this checksum offload. 1299 */ 1300 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 1301 return false; 1302 1303 l4.hdr = skb_transport_header(skb); 1304 1305 if (!(!skb->encapsulation && 1306 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) || 1307 l4.udp->dest == htons(GENEVE_UDP_PORT) || 1308 l4.udp->dest == htons(4790)))) 1309 return false; 1310 1311 return true; 1312 } 1313 1314 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 1315 u32 *ol_type_vlan_len_msec) 1316 { 1317 u32 l2_len, l3_len, l4_len; 1318 unsigned char *il2_hdr; 1319 union l3_hdr_info l3; 1320 union l4_hdr_info l4; 1321 1322 l3.hdr = skb_network_header(skb); 1323 l4.hdr = skb_transport_header(skb); 1324 1325 /* compute OL2 header size, defined in 2 Bytes */ 1326 l2_len = l3.hdr - skb->data; 1327 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1); 1328 1329 /* compute OL3 header size, defined in 4 Bytes */ 1330 l3_len = l4.hdr - l3.hdr; 1331 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2); 1332 1333 il2_hdr = skb_inner_mac_header(skb); 1334 /* compute OL4 header size, defined in 4 Bytes */ 1335 l4_len = il2_hdr - l4.hdr; 1336 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2); 1337 1338 /* define outer network header type */ 1339 if (skb->protocol == htons(ETH_P_IP)) { 1340 if (skb_is_gso(skb)) 1341 hns3_set_field(*ol_type_vlan_len_msec, 1342 HNS3_TXD_OL3T_S, 1343 HNS3_OL3T_IPV4_CSUM); 1344 else 1345 hns3_set_field(*ol_type_vlan_len_msec, 1346 HNS3_TXD_OL3T_S, 1347 HNS3_OL3T_IPV4_NO_CSUM); 1348 } else if (skb->protocol == htons(ETH_P_IPV6)) { 1349 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 1350 HNS3_OL3T_IPV6); 1351 } 1352 1353 if (ol4_proto == IPPROTO_UDP) 1354 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 1355 HNS3_TUN_MAC_IN_UDP); 1356 else if (ol4_proto == IPPROTO_GRE) 1357 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 1358 HNS3_TUN_NVGRE); 1359 } 1360 1361 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 1362 u8 il4_proto, u32 *type_cs_vlan_tso, 1363 u32 *ol_type_vlan_len_msec) 1364 { 1365 unsigned char *l2_hdr = skb->data; 1366 u32 l4_proto = ol4_proto; 1367 union l4_hdr_info l4; 1368 union l3_hdr_info l3; 1369 u32 l2_len, l3_len; 1370 1371 l4.hdr = skb_transport_header(skb); 1372 l3.hdr = skb_network_header(skb); 1373 1374 /* handle encapsulation skb */ 1375 if (skb->encapsulation) { 1376 /* If this is a not UDP/GRE encapsulation skb */ 1377 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) { 1378 /* drop the skb tunnel packet if hardware don't support, 1379 * because hardware can't calculate csum when TSO. 1380 */ 1381 if (skb_is_gso(skb)) 1382 return -EDOM; 1383 1384 /* the stack computes the IP header already, 1385 * driver calculate l4 checksum when not TSO. 1386 */ 1387 return skb_checksum_help(skb); 1388 } 1389 1390 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec); 1391 1392 /* switch to inner header */ 1393 l2_hdr = skb_inner_mac_header(skb); 1394 l3.hdr = skb_inner_network_header(skb); 1395 l4.hdr = skb_inner_transport_header(skb); 1396 l4_proto = il4_proto; 1397 } 1398 1399 if (l3.v4->version == 4) { 1400 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 1401 HNS3_L3T_IPV4); 1402 1403 /* the stack computes the IP header already, the only time we 1404 * need the hardware to recompute it is in the case of TSO. 1405 */ 1406 if (skb_is_gso(skb)) 1407 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 1408 } else if (l3.v6->version == 6) { 1409 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 1410 HNS3_L3T_IPV6); 1411 } 1412 1413 /* compute inner(/normal) L2 header size, defined in 2 Bytes */ 1414 l2_len = l3.hdr - l2_hdr; 1415 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 1416 1417 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 1418 l3_len = l4.hdr - l3.hdr; 1419 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 1420 1421 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 1422 switch (l4_proto) { 1423 case IPPROTO_TCP: 1424 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1425 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1426 HNS3_L4T_TCP); 1427 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1428 l4.tcp->doff); 1429 break; 1430 case IPPROTO_UDP: 1431 if (hns3_tunnel_csum_bug(skb)) { 1432 int ret = skb_put_padto(skb, HNS3_MIN_TUN_PKT_LEN); 1433 1434 return ret ? ret : skb_checksum_help(skb); 1435 } 1436 1437 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1438 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1439 HNS3_L4T_UDP); 1440 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1441 (sizeof(struct udphdr) >> 2)); 1442 break; 1443 case IPPROTO_SCTP: 1444 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1445 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1446 HNS3_L4T_SCTP); 1447 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1448 (sizeof(struct sctphdr) >> 2)); 1449 break; 1450 default: 1451 /* drop the skb tunnel packet if hardware don't support, 1452 * because hardware can't calculate csum when TSO. 1453 */ 1454 if (skb_is_gso(skb)) 1455 return -EDOM; 1456 1457 /* the stack computes the IP header already, 1458 * driver calculate l4 checksum when not TSO. 1459 */ 1460 return skb_checksum_help(skb); 1461 } 1462 1463 return 0; 1464 } 1465 1466 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring, 1467 struct sk_buff *skb) 1468 { 1469 struct hnae3_handle *handle = tx_ring->tqp->handle; 1470 struct hnae3_ae_dev *ae_dev; 1471 struct vlan_ethhdr *vhdr; 1472 int rc; 1473 1474 if (!(skb->protocol == htons(ETH_P_8021Q) || 1475 skb_vlan_tag_present(skb))) 1476 return 0; 1477 1478 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert 1479 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it 1480 * will cause RAS error. 1481 */ 1482 ae_dev = pci_get_drvdata(handle->pdev); 1483 if (unlikely(skb_vlan_tagged_multi(skb) && 1484 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 && 1485 handle->port_base_vlan_state == 1486 HNAE3_PORT_BASE_VLAN_ENABLE)) 1487 return -EINVAL; 1488 1489 if (skb->protocol == htons(ETH_P_8021Q) && 1490 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 1491 /* When HW VLAN acceleration is turned off, and the stack 1492 * sets the protocol to 802.1q, the driver just need to 1493 * set the protocol to the encapsulated ethertype. 1494 */ 1495 skb->protocol = vlan_get_protocol(skb); 1496 return 0; 1497 } 1498 1499 if (skb_vlan_tag_present(skb)) { 1500 /* Based on hw strategy, use out_vtag in two layer tag case, 1501 * and use inner_vtag in one tag case. 1502 */ 1503 if (skb->protocol == htons(ETH_P_8021Q) && 1504 handle->port_base_vlan_state == 1505 HNAE3_PORT_BASE_VLAN_DISABLE) 1506 rc = HNS3_OUTER_VLAN_TAG; 1507 else 1508 rc = HNS3_INNER_VLAN_TAG; 1509 1510 skb->protocol = vlan_get_protocol(skb); 1511 return rc; 1512 } 1513 1514 rc = skb_cow_head(skb, 0); 1515 if (unlikely(rc < 0)) 1516 return rc; 1517 1518 vhdr = (struct vlan_ethhdr *)skb->data; 1519 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT) 1520 & VLAN_PRIO_MASK); 1521 1522 skb->protocol = vlan_get_protocol(skb); 1523 return 0; 1524 } 1525 1526 /* check if the hardware is capable of checksum offloading */ 1527 static bool hns3_check_hw_tx_csum(struct sk_buff *skb) 1528 { 1529 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 1530 1531 /* Kindly note, due to backward compatibility of the TX descriptor, 1532 * HW checksum of the non-IP packets and GSO packets is handled at 1533 * different place in the following code 1534 */ 1535 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) || 1536 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state)) 1537 return false; 1538 1539 return true; 1540 } 1541 1542 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring, 1543 struct sk_buff *skb, struct hns3_desc *desc, 1544 struct hns3_desc_cb *desc_cb) 1545 { 1546 u32 ol_type_vlan_len_msec = 0; 1547 u32 paylen_ol4cs = skb->len; 1548 u32 type_cs_vlan_tso = 0; 1549 u16 mss_hw_csum = 0; 1550 u16 inner_vtag = 0; 1551 u16 out_vtag = 0; 1552 int ret; 1553 1554 ret = hns3_handle_vtags(ring, skb); 1555 if (unlikely(ret < 0)) { 1556 u64_stats_update_begin(&ring->syncp); 1557 ring->stats.tx_vlan_err++; 1558 u64_stats_update_end(&ring->syncp); 1559 return ret; 1560 } else if (ret == HNS3_INNER_VLAN_TAG) { 1561 inner_vtag = skb_vlan_tag_get(skb); 1562 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1563 VLAN_PRIO_MASK; 1564 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1); 1565 } else if (ret == HNS3_OUTER_VLAN_TAG) { 1566 out_vtag = skb_vlan_tag_get(skb); 1567 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1568 VLAN_PRIO_MASK; 1569 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B, 1570 1); 1571 } 1572 1573 desc_cb->send_bytes = skb->len; 1574 1575 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1576 u8 ol4_proto, il4_proto; 1577 1578 if (hns3_check_hw_tx_csum(skb)) { 1579 /* set checksum start and offset, defined in 2 Bytes */ 1580 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_CSUM_START_S, 1581 skb_checksum_start_offset(skb) >> 1); 1582 hns3_set_field(ol_type_vlan_len_msec, 1583 HNS3_TXD_CSUM_OFFSET_S, 1584 skb->csum_offset >> 1); 1585 mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B); 1586 goto out_hw_tx_csum; 1587 } 1588 1589 skb_reset_mac_len(skb); 1590 1591 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1592 if (unlikely(ret < 0)) { 1593 u64_stats_update_begin(&ring->syncp); 1594 ring->stats.tx_l4_proto_err++; 1595 u64_stats_update_end(&ring->syncp); 1596 return ret; 1597 } 1598 1599 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto, 1600 &type_cs_vlan_tso, 1601 &ol_type_vlan_len_msec); 1602 if (unlikely(ret < 0)) { 1603 u64_stats_update_begin(&ring->syncp); 1604 ring->stats.tx_l2l3l4_err++; 1605 u64_stats_update_end(&ring->syncp); 1606 return ret; 1607 } 1608 1609 ret = hns3_set_tso(skb, &paylen_ol4cs, &mss_hw_csum, 1610 &type_cs_vlan_tso, &desc_cb->send_bytes); 1611 if (unlikely(ret < 0)) { 1612 u64_stats_update_begin(&ring->syncp); 1613 ring->stats.tx_tso_err++; 1614 u64_stats_update_end(&ring->syncp); 1615 return ret; 1616 } 1617 } 1618 1619 out_hw_tx_csum: 1620 /* Set txbd */ 1621 desc->tx.ol_type_vlan_len_msec = 1622 cpu_to_le32(ol_type_vlan_len_msec); 1623 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso); 1624 desc->tx.paylen_ol4cs = cpu_to_le32(paylen_ol4cs); 1625 desc->tx.mss_hw_csum = cpu_to_le16(mss_hw_csum); 1626 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1627 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1628 1629 return 0; 1630 } 1631 1632 static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma, 1633 unsigned int size) 1634 { 1635 #define HNS3_LIKELY_BD_NUM 1 1636 1637 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1638 unsigned int frag_buf_num; 1639 int k, sizeoflast; 1640 1641 if (likely(size <= HNS3_MAX_BD_SIZE)) { 1642 desc->addr = cpu_to_le64(dma); 1643 desc->tx.send_size = cpu_to_le16(size); 1644 desc->tx.bdtp_fe_sc_vld_ra_ri = 1645 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1646 1647 trace_hns3_tx_desc(ring, ring->next_to_use); 1648 ring_ptr_move_fw(ring, next_to_use); 1649 return HNS3_LIKELY_BD_NUM; 1650 } 1651 1652 frag_buf_num = hns3_tx_bd_count(size); 1653 sizeoflast = size % HNS3_MAX_BD_SIZE; 1654 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1655 1656 /* When frag size is bigger than hardware limit, split this frag */ 1657 for (k = 0; k < frag_buf_num; k++) { 1658 /* now, fill the descriptor */ 1659 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1660 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1661 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1662 desc->tx.bdtp_fe_sc_vld_ra_ri = 1663 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1664 1665 trace_hns3_tx_desc(ring, ring->next_to_use); 1666 /* move ring pointer to next */ 1667 ring_ptr_move_fw(ring, next_to_use); 1668 1669 desc = &ring->desc[ring->next_to_use]; 1670 } 1671 1672 return frag_buf_num; 1673 } 1674 1675 static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv, 1676 unsigned int type) 1677 { 1678 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1679 struct device *dev = ring_to_dev(ring); 1680 unsigned int size; 1681 dma_addr_t dma; 1682 1683 if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) { 1684 struct sk_buff *skb = (struct sk_buff *)priv; 1685 1686 size = skb_headlen(skb); 1687 if (!size) 1688 return 0; 1689 1690 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1691 } else if (type & DESC_TYPE_BOUNCE_HEAD) { 1692 /* Head data has been filled in hns3_handle_tx_bounce(), 1693 * just return 0 here. 1694 */ 1695 return 0; 1696 } else { 1697 skb_frag_t *frag = (skb_frag_t *)priv; 1698 1699 size = skb_frag_size(frag); 1700 if (!size) 1701 return 0; 1702 1703 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1704 } 1705 1706 if (unlikely(dma_mapping_error(dev, dma))) { 1707 u64_stats_update_begin(&ring->syncp); 1708 ring->stats.sw_err_cnt++; 1709 u64_stats_update_end(&ring->syncp); 1710 return -ENOMEM; 1711 } 1712 1713 desc_cb->priv = priv; 1714 desc_cb->length = size; 1715 desc_cb->dma = dma; 1716 desc_cb->type = type; 1717 1718 return hns3_fill_desc(ring, dma, size); 1719 } 1720 1721 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1722 unsigned int bd_num) 1723 { 1724 unsigned int size; 1725 int i; 1726 1727 size = skb_headlen(skb); 1728 while (size > HNS3_MAX_BD_SIZE) { 1729 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1730 size -= HNS3_MAX_BD_SIZE; 1731 1732 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1733 return bd_num; 1734 } 1735 1736 if (size) { 1737 bd_size[bd_num++] = size; 1738 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1739 return bd_num; 1740 } 1741 1742 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1743 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1744 size = skb_frag_size(frag); 1745 if (!size) 1746 continue; 1747 1748 while (size > HNS3_MAX_BD_SIZE) { 1749 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1750 size -= HNS3_MAX_BD_SIZE; 1751 1752 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1753 return bd_num; 1754 } 1755 1756 bd_size[bd_num++] = size; 1757 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1758 return bd_num; 1759 } 1760 1761 return bd_num; 1762 } 1763 1764 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1765 u8 max_non_tso_bd_num, unsigned int bd_num, 1766 unsigned int recursion_level) 1767 { 1768 #define HNS3_MAX_RECURSION_LEVEL 24 1769 1770 struct sk_buff *frag_skb; 1771 1772 /* If the total len is within the max bd limit */ 1773 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level && 1774 !skb_has_frag_list(skb) && 1775 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num)) 1776 return skb_shinfo(skb)->nr_frags + 1U; 1777 1778 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL)) 1779 return UINT_MAX; 1780 1781 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num); 1782 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM) 1783 return bd_num; 1784 1785 skb_walk_frags(skb, frag_skb) { 1786 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num, 1787 bd_num, recursion_level + 1); 1788 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1789 return bd_num; 1790 } 1791 1792 return bd_num; 1793 } 1794 1795 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb) 1796 { 1797 if (!skb->encapsulation) 1798 return skb_transport_offset(skb) + tcp_hdrlen(skb); 1799 1800 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb); 1801 } 1802 1803 /* HW need every continuous max_non_tso_bd_num buffer data to be larger 1804 * than MSS, we simplify it by ensuring skb_headlen + the first continuous 1805 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss, 1806 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger 1807 * than MSS except the last max_non_tso_bd_num - 1 frags. 1808 */ 1809 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size, 1810 unsigned int bd_num, u8 max_non_tso_bd_num) 1811 { 1812 unsigned int tot_len = 0; 1813 int i; 1814 1815 for (i = 0; i < max_non_tso_bd_num - 1U; i++) 1816 tot_len += bd_size[i]; 1817 1818 /* ensure the first max_non_tso_bd_num frags is greater than 1819 * mss + header 1820 */ 1821 if (tot_len + bd_size[max_non_tso_bd_num - 1U] < 1822 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb)) 1823 return true; 1824 1825 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater 1826 * than mss except the last one. 1827 */ 1828 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) { 1829 tot_len -= bd_size[i]; 1830 tot_len += bd_size[i + max_non_tso_bd_num - 1U]; 1831 1832 if (tot_len < skb_shinfo(skb)->gso_size) 1833 return true; 1834 } 1835 1836 return false; 1837 } 1838 1839 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size) 1840 { 1841 int i; 1842 1843 for (i = 0; i < MAX_SKB_FRAGS; i++) 1844 size[i] = skb_frag_size(&shinfo->frags[i]); 1845 } 1846 1847 static int hns3_skb_linearize(struct hns3_enet_ring *ring, 1848 struct sk_buff *skb, 1849 u8 max_non_tso_bd_num, 1850 unsigned int bd_num) 1851 { 1852 /* 'bd_num == UINT_MAX' means the skb' fraglist has a 1853 * recursion level of over HNS3_MAX_RECURSION_LEVEL. 1854 */ 1855 if (bd_num == UINT_MAX) { 1856 u64_stats_update_begin(&ring->syncp); 1857 ring->stats.over_max_recursion++; 1858 u64_stats_update_end(&ring->syncp); 1859 return -ENOMEM; 1860 } 1861 1862 /* The skb->len has exceeded the hw limitation, linearization 1863 * will not help. 1864 */ 1865 if (skb->len > HNS3_MAX_TSO_SIZE || 1866 (!skb_is_gso(skb) && skb->len > 1867 HNS3_MAX_NON_TSO_SIZE(max_non_tso_bd_num))) { 1868 u64_stats_update_begin(&ring->syncp); 1869 ring->stats.hw_limitation++; 1870 u64_stats_update_end(&ring->syncp); 1871 return -ENOMEM; 1872 } 1873 1874 if (__skb_linearize(skb)) { 1875 u64_stats_update_begin(&ring->syncp); 1876 ring->stats.sw_err_cnt++; 1877 u64_stats_update_end(&ring->syncp); 1878 return -ENOMEM; 1879 } 1880 1881 return 0; 1882 } 1883 1884 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring, 1885 struct net_device *netdev, 1886 struct sk_buff *skb) 1887 { 1888 struct hns3_nic_priv *priv = netdev_priv(netdev); 1889 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num; 1890 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U]; 1891 unsigned int bd_num; 1892 1893 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0); 1894 if (unlikely(bd_num > max_non_tso_bd_num)) { 1895 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) && 1896 !hns3_skb_need_linearized(skb, bd_size, bd_num, 1897 max_non_tso_bd_num)) { 1898 trace_hns3_over_max_bd(skb); 1899 goto out; 1900 } 1901 1902 if (hns3_skb_linearize(ring, skb, max_non_tso_bd_num, 1903 bd_num)) 1904 return -ENOMEM; 1905 1906 bd_num = hns3_tx_bd_count(skb->len); 1907 1908 u64_stats_update_begin(&ring->syncp); 1909 ring->stats.tx_copy++; 1910 u64_stats_update_end(&ring->syncp); 1911 } 1912 1913 out: 1914 if (likely(ring_space(ring) >= bd_num)) 1915 return bd_num; 1916 1917 netif_stop_subqueue(netdev, ring->queue_index); 1918 smp_mb(); /* Memory barrier before checking ring_space */ 1919 1920 /* Start queue in case hns3_clean_tx_ring has just made room 1921 * available and has not seen the queue stopped state performed 1922 * by netif_stop_subqueue above. 1923 */ 1924 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) && 1925 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 1926 netif_start_subqueue(netdev, ring->queue_index); 1927 return bd_num; 1928 } 1929 1930 u64_stats_update_begin(&ring->syncp); 1931 ring->stats.tx_busy++; 1932 u64_stats_update_end(&ring->syncp); 1933 1934 return -EBUSY; 1935 } 1936 1937 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1938 { 1939 struct device *dev = ring_to_dev(ring); 1940 unsigned int i; 1941 1942 for (i = 0; i < ring->desc_num; i++) { 1943 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1944 struct hns3_desc_cb *desc_cb; 1945 1946 memset(desc, 0, sizeof(*desc)); 1947 1948 /* check if this is where we started */ 1949 if (ring->next_to_use == next_to_use_orig) 1950 break; 1951 1952 /* rollback one */ 1953 ring_ptr_move_bw(ring, next_to_use); 1954 1955 desc_cb = &ring->desc_cb[ring->next_to_use]; 1956 1957 if (!desc_cb->dma) 1958 continue; 1959 1960 /* unmap the descriptor dma address */ 1961 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB)) 1962 dma_unmap_single(dev, desc_cb->dma, desc_cb->length, 1963 DMA_TO_DEVICE); 1964 else if (desc_cb->type & 1965 (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) 1966 hns3_tx_spare_rollback(ring, desc_cb->length); 1967 else if (desc_cb->length) 1968 dma_unmap_page(dev, desc_cb->dma, desc_cb->length, 1969 DMA_TO_DEVICE); 1970 1971 desc_cb->length = 0; 1972 desc_cb->dma = 0; 1973 desc_cb->type = DESC_TYPE_UNKNOWN; 1974 } 1975 } 1976 1977 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring, 1978 struct sk_buff *skb, unsigned int type) 1979 { 1980 struct sk_buff *frag_skb; 1981 int i, ret, bd_num = 0; 1982 1983 ret = hns3_map_and_fill_desc(ring, skb, type); 1984 if (unlikely(ret < 0)) 1985 return ret; 1986 1987 bd_num += ret; 1988 1989 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1990 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1991 1992 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE); 1993 if (unlikely(ret < 0)) 1994 return ret; 1995 1996 bd_num += ret; 1997 } 1998 1999 skb_walk_frags(skb, frag_skb) { 2000 ret = hns3_fill_skb_to_desc(ring, frag_skb, 2001 DESC_TYPE_FRAGLIST_SKB); 2002 if (unlikely(ret < 0)) 2003 return ret; 2004 2005 bd_num += ret; 2006 } 2007 2008 return bd_num; 2009 } 2010 2011 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num, 2012 bool doorbell) 2013 { 2014 ring->pending_buf += num; 2015 2016 if (!doorbell) { 2017 u64_stats_update_begin(&ring->syncp); 2018 ring->stats.tx_more++; 2019 u64_stats_update_end(&ring->syncp); 2020 return; 2021 } 2022 2023 if (!ring->pending_buf) 2024 return; 2025 2026 writel(ring->pending_buf, 2027 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG); 2028 ring->pending_buf = 0; 2029 WRITE_ONCE(ring->last_to_use, ring->next_to_use); 2030 } 2031 2032 static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb, 2033 struct hns3_desc *desc) 2034 { 2035 struct hnae3_handle *h = hns3_get_handle(netdev); 2036 2037 if (!(h->ae_algo->ops->set_tx_hwts_info && 2038 h->ae_algo->ops->set_tx_hwts_info(h, skb))) 2039 return; 2040 2041 desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B)); 2042 } 2043 2044 static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring, 2045 struct sk_buff *skb) 2046 { 2047 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 2048 unsigned int type = DESC_TYPE_BOUNCE_HEAD; 2049 unsigned int size = skb_headlen(skb); 2050 dma_addr_t dma; 2051 int bd_num = 0; 2052 u32 cb_len; 2053 void *buf; 2054 int ret; 2055 2056 if (skb->len <= ring->tx_copybreak) { 2057 size = skb->len; 2058 type = DESC_TYPE_BOUNCE_ALL; 2059 } 2060 2061 /* hns3_can_use_tx_bounce() is called to ensure the below 2062 * function can always return the tx buffer. 2063 */ 2064 buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len); 2065 2066 ret = skb_copy_bits(skb, 0, buf, size); 2067 if (unlikely(ret < 0)) { 2068 hns3_tx_spare_rollback(ring, cb_len); 2069 u64_stats_update_begin(&ring->syncp); 2070 ring->stats.copy_bits_err++; 2071 u64_stats_update_end(&ring->syncp); 2072 return ret; 2073 } 2074 2075 desc_cb->priv = skb; 2076 desc_cb->length = cb_len; 2077 desc_cb->dma = dma; 2078 desc_cb->type = type; 2079 2080 bd_num += hns3_fill_desc(ring, dma, size); 2081 2082 if (type == DESC_TYPE_BOUNCE_HEAD) { 2083 ret = hns3_fill_skb_to_desc(ring, skb, 2084 DESC_TYPE_BOUNCE_HEAD); 2085 if (unlikely(ret < 0)) 2086 return ret; 2087 2088 bd_num += ret; 2089 } 2090 2091 dma_sync_single_for_device(ring_to_dev(ring), dma, size, 2092 DMA_TO_DEVICE); 2093 2094 u64_stats_update_begin(&ring->syncp); 2095 ring->stats.tx_bounce++; 2096 u64_stats_update_end(&ring->syncp); 2097 return bd_num; 2098 } 2099 2100 static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring, 2101 struct sk_buff *skb) 2102 { 2103 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 2104 u32 nfrag = skb_shinfo(skb)->nr_frags + 1; 2105 struct sg_table *sgt; 2106 int i, bd_num = 0; 2107 dma_addr_t dma; 2108 u32 cb_len; 2109 int nents; 2110 2111 if (skb_has_frag_list(skb)) 2112 nfrag = HNS3_MAX_TSO_BD_NUM; 2113 2114 /* hns3_can_use_tx_sgl() is called to ensure the below 2115 * function can always return the tx buffer. 2116 */ 2117 sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag), 2118 &dma, &cb_len); 2119 2120 /* scatterlist follows by the sg table */ 2121 sgt->sgl = (struct scatterlist *)(sgt + 1); 2122 sg_init_table(sgt->sgl, nfrag); 2123 nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len); 2124 if (unlikely(nents < 0)) { 2125 hns3_tx_spare_rollback(ring, cb_len); 2126 u64_stats_update_begin(&ring->syncp); 2127 ring->stats.skb2sgl_err++; 2128 u64_stats_update_end(&ring->syncp); 2129 return -ENOMEM; 2130 } 2131 2132 sgt->orig_nents = nents; 2133 sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents, 2134 DMA_TO_DEVICE); 2135 if (unlikely(!sgt->nents)) { 2136 hns3_tx_spare_rollback(ring, cb_len); 2137 u64_stats_update_begin(&ring->syncp); 2138 ring->stats.map_sg_err++; 2139 u64_stats_update_end(&ring->syncp); 2140 return -ENOMEM; 2141 } 2142 2143 desc_cb->priv = skb; 2144 desc_cb->length = cb_len; 2145 desc_cb->dma = dma; 2146 desc_cb->type = DESC_TYPE_SGL_SKB; 2147 2148 for (i = 0; i < sgt->nents; i++) 2149 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i), 2150 sg_dma_len(sgt->sgl + i)); 2151 2152 u64_stats_update_begin(&ring->syncp); 2153 ring->stats.tx_sgl++; 2154 u64_stats_update_end(&ring->syncp); 2155 2156 return bd_num; 2157 } 2158 2159 static int hns3_handle_desc_filling(struct hns3_enet_ring *ring, 2160 struct sk_buff *skb) 2161 { 2162 u32 space; 2163 2164 if (!ring->tx_spare) 2165 goto out; 2166 2167 space = hns3_tx_spare_space(ring); 2168 2169 if (hns3_can_use_tx_sgl(ring, skb, space)) 2170 return hns3_handle_tx_sgl(ring, skb); 2171 2172 if (hns3_can_use_tx_bounce(ring, skb, space)) 2173 return hns3_handle_tx_bounce(ring, skb); 2174 2175 out: 2176 return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB); 2177 } 2178 2179 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 2180 { 2181 struct hns3_nic_priv *priv = netdev_priv(netdev); 2182 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping]; 2183 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 2184 struct netdev_queue *dev_queue; 2185 int pre_ntu, next_to_use_head; 2186 bool doorbell; 2187 int ret; 2188 2189 /* Hardware can only handle short frames above 32 bytes */ 2190 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) { 2191 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 2192 2193 u64_stats_update_begin(&ring->syncp); 2194 ring->stats.sw_err_cnt++; 2195 u64_stats_update_end(&ring->syncp); 2196 2197 return NETDEV_TX_OK; 2198 } 2199 2200 /* Prefetch the data used later */ 2201 prefetch(skb->data); 2202 2203 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb); 2204 if (unlikely(ret <= 0)) { 2205 if (ret == -EBUSY) { 2206 hns3_tx_doorbell(ring, 0, true); 2207 return NETDEV_TX_BUSY; 2208 } 2209 2210 hns3_rl_err(netdev, "xmit error: %d!\n", ret); 2211 goto out_err_tx_ok; 2212 } 2213 2214 next_to_use_head = ring->next_to_use; 2215 2216 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use], 2217 desc_cb); 2218 if (unlikely(ret < 0)) 2219 goto fill_err; 2220 2221 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is 2222 * zero, which is unlikely, and 'ret > 0' means how many tx desc 2223 * need to be notified to the hw. 2224 */ 2225 ret = hns3_handle_desc_filling(ring, skb); 2226 if (unlikely(ret <= 0)) 2227 goto fill_err; 2228 2229 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) : 2230 (ring->desc_num - 1); 2231 2232 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 2233 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]); 2234 2235 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |= 2236 cpu_to_le16(BIT(HNS3_TXD_FE_B)); 2237 trace_hns3_tx_desc(ring, pre_ntu); 2238 2239 skb_tx_timestamp(skb); 2240 2241 /* Complete translate all packets */ 2242 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index); 2243 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes, 2244 netdev_xmit_more()); 2245 hns3_tx_doorbell(ring, ret, doorbell); 2246 2247 return NETDEV_TX_OK; 2248 2249 fill_err: 2250 hns3_clear_desc(ring, next_to_use_head); 2251 2252 out_err_tx_ok: 2253 dev_kfree_skb_any(skb); 2254 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 2255 return NETDEV_TX_OK; 2256 } 2257 2258 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 2259 { 2260 struct hnae3_handle *h = hns3_get_handle(netdev); 2261 struct sockaddr *mac_addr = p; 2262 int ret; 2263 2264 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 2265 return -EADDRNOTAVAIL; 2266 2267 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 2268 netdev_info(netdev, "already using mac address %pM\n", 2269 mac_addr->sa_data); 2270 return 0; 2271 } 2272 2273 /* For VF device, if there is a perm_addr, then the user will not 2274 * be allowed to change the address. 2275 */ 2276 if (!hns3_is_phys_func(h->pdev) && 2277 !is_zero_ether_addr(netdev->perm_addr)) { 2278 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n", 2279 netdev->perm_addr, mac_addr->sa_data); 2280 return -EPERM; 2281 } 2282 2283 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 2284 if (ret) { 2285 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 2286 return ret; 2287 } 2288 2289 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 2290 2291 return 0; 2292 } 2293 2294 static int hns3_nic_do_ioctl(struct net_device *netdev, 2295 struct ifreq *ifr, int cmd) 2296 { 2297 struct hnae3_handle *h = hns3_get_handle(netdev); 2298 2299 if (!netif_running(netdev)) 2300 return -EINVAL; 2301 2302 if (!h->ae_algo->ops->do_ioctl) 2303 return -EOPNOTSUPP; 2304 2305 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 2306 } 2307 2308 static int hns3_nic_set_features(struct net_device *netdev, 2309 netdev_features_t features) 2310 { 2311 netdev_features_t changed = netdev->features ^ features; 2312 struct hns3_nic_priv *priv = netdev_priv(netdev); 2313 struct hnae3_handle *h = priv->ae_handle; 2314 bool enable; 2315 int ret; 2316 2317 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 2318 enable = !!(features & NETIF_F_GRO_HW); 2319 ret = h->ae_algo->ops->set_gro_en(h, enable); 2320 if (ret) 2321 return ret; 2322 } 2323 2324 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 2325 h->ae_algo->ops->enable_hw_strip_rxvtag) { 2326 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 2327 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 2328 if (ret) 2329 return ret; 2330 } 2331 2332 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 2333 enable = !!(features & NETIF_F_NTUPLE); 2334 h->ae_algo->ops->enable_fd(h, enable); 2335 } 2336 2337 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) && 2338 h->ae_algo->ops->cls_flower_active(h)) { 2339 netdev_err(netdev, 2340 "there are offloaded TC filters active, cannot disable HW TC offload"); 2341 return -EINVAL; 2342 } 2343 2344 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 2345 h->ae_algo->ops->enable_vlan_filter) { 2346 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER); 2347 ret = h->ae_algo->ops->enable_vlan_filter(h, enable); 2348 if (ret) 2349 return ret; 2350 } 2351 2352 netdev->features = features; 2353 return 0; 2354 } 2355 2356 static netdev_features_t hns3_features_check(struct sk_buff *skb, 2357 struct net_device *dev, 2358 netdev_features_t features) 2359 { 2360 #define HNS3_MAX_HDR_LEN 480U 2361 #define HNS3_MAX_L4_HDR_LEN 60U 2362 2363 size_t len; 2364 2365 if (skb->ip_summed != CHECKSUM_PARTIAL) 2366 return features; 2367 2368 if (skb->encapsulation) 2369 len = skb_inner_transport_header(skb) - skb->data; 2370 else 2371 len = skb_transport_header(skb) - skb->data; 2372 2373 /* Assume L4 is 60 byte as TCP is the only protocol with a 2374 * a flexible value, and it's max len is 60 bytes. 2375 */ 2376 len += HNS3_MAX_L4_HDR_LEN; 2377 2378 /* Hardware only supports checksum on the skb with a max header 2379 * len of 480 bytes. 2380 */ 2381 if (len > HNS3_MAX_HDR_LEN) 2382 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2383 2384 return features; 2385 } 2386 2387 static void hns3_nic_get_stats64(struct net_device *netdev, 2388 struct rtnl_link_stats64 *stats) 2389 { 2390 struct hns3_nic_priv *priv = netdev_priv(netdev); 2391 int queue_num = priv->ae_handle->kinfo.num_tqps; 2392 struct hnae3_handle *handle = priv->ae_handle; 2393 struct hns3_enet_ring *ring; 2394 u64 rx_length_errors = 0; 2395 u64 rx_crc_errors = 0; 2396 u64 rx_multicast = 0; 2397 unsigned int start; 2398 u64 tx_errors = 0; 2399 u64 rx_errors = 0; 2400 unsigned int idx; 2401 u64 tx_bytes = 0; 2402 u64 rx_bytes = 0; 2403 u64 tx_pkts = 0; 2404 u64 rx_pkts = 0; 2405 u64 tx_drop = 0; 2406 u64 rx_drop = 0; 2407 2408 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 2409 return; 2410 2411 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 2412 2413 for (idx = 0; idx < queue_num; idx++) { 2414 /* fetch the tx stats */ 2415 ring = &priv->ring[idx]; 2416 do { 2417 start = u64_stats_fetch_begin_irq(&ring->syncp); 2418 tx_bytes += ring->stats.tx_bytes; 2419 tx_pkts += ring->stats.tx_pkts; 2420 tx_drop += ring->stats.sw_err_cnt; 2421 tx_drop += ring->stats.tx_vlan_err; 2422 tx_drop += ring->stats.tx_l4_proto_err; 2423 tx_drop += ring->stats.tx_l2l3l4_err; 2424 tx_drop += ring->stats.tx_tso_err; 2425 tx_drop += ring->stats.over_max_recursion; 2426 tx_drop += ring->stats.hw_limitation; 2427 tx_drop += ring->stats.copy_bits_err; 2428 tx_drop += ring->stats.skb2sgl_err; 2429 tx_drop += ring->stats.map_sg_err; 2430 tx_errors += ring->stats.sw_err_cnt; 2431 tx_errors += ring->stats.tx_vlan_err; 2432 tx_errors += ring->stats.tx_l4_proto_err; 2433 tx_errors += ring->stats.tx_l2l3l4_err; 2434 tx_errors += ring->stats.tx_tso_err; 2435 tx_errors += ring->stats.over_max_recursion; 2436 tx_errors += ring->stats.hw_limitation; 2437 tx_errors += ring->stats.copy_bits_err; 2438 tx_errors += ring->stats.skb2sgl_err; 2439 tx_errors += ring->stats.map_sg_err; 2440 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 2441 2442 /* fetch the rx stats */ 2443 ring = &priv->ring[idx + queue_num]; 2444 do { 2445 start = u64_stats_fetch_begin_irq(&ring->syncp); 2446 rx_bytes += ring->stats.rx_bytes; 2447 rx_pkts += ring->stats.rx_pkts; 2448 rx_drop += ring->stats.l2_err; 2449 rx_errors += ring->stats.l2_err; 2450 rx_errors += ring->stats.l3l4_csum_err; 2451 rx_crc_errors += ring->stats.l2_err; 2452 rx_multicast += ring->stats.rx_multicast; 2453 rx_length_errors += ring->stats.err_pkt_len; 2454 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 2455 } 2456 2457 stats->tx_bytes = tx_bytes; 2458 stats->tx_packets = tx_pkts; 2459 stats->rx_bytes = rx_bytes; 2460 stats->rx_packets = rx_pkts; 2461 2462 stats->rx_errors = rx_errors; 2463 stats->multicast = rx_multicast; 2464 stats->rx_length_errors = rx_length_errors; 2465 stats->rx_crc_errors = rx_crc_errors; 2466 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 2467 2468 stats->tx_errors = tx_errors; 2469 stats->rx_dropped = rx_drop; 2470 stats->tx_dropped = tx_drop; 2471 stats->collisions = netdev->stats.collisions; 2472 stats->rx_over_errors = netdev->stats.rx_over_errors; 2473 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 2474 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 2475 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 2476 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 2477 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 2478 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 2479 stats->tx_window_errors = netdev->stats.tx_window_errors; 2480 stats->rx_compressed = netdev->stats.rx_compressed; 2481 stats->tx_compressed = netdev->stats.tx_compressed; 2482 } 2483 2484 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 2485 { 2486 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 2487 struct hnae3_knic_private_info *kinfo; 2488 u8 tc = mqprio_qopt->qopt.num_tc; 2489 u16 mode = mqprio_qopt->mode; 2490 u8 hw = mqprio_qopt->qopt.hw; 2491 struct hnae3_handle *h; 2492 2493 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 2494 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 2495 return -EOPNOTSUPP; 2496 2497 if (tc > HNAE3_MAX_TC) 2498 return -EINVAL; 2499 2500 if (!netdev) 2501 return -EINVAL; 2502 2503 h = hns3_get_handle(netdev); 2504 kinfo = &h->kinfo; 2505 2506 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc); 2507 2508 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 2509 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP; 2510 } 2511 2512 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv, 2513 struct flow_cls_offload *flow) 2514 { 2515 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid); 2516 struct hnae3_handle *h = hns3_get_handle(priv->netdev); 2517 2518 switch (flow->command) { 2519 case FLOW_CLS_REPLACE: 2520 if (h->ae_algo->ops->add_cls_flower) 2521 return h->ae_algo->ops->add_cls_flower(h, flow, tc); 2522 break; 2523 case FLOW_CLS_DESTROY: 2524 if (h->ae_algo->ops->del_cls_flower) 2525 return h->ae_algo->ops->del_cls_flower(h, flow); 2526 break; 2527 default: 2528 break; 2529 } 2530 2531 return -EOPNOTSUPP; 2532 } 2533 2534 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2535 void *cb_priv) 2536 { 2537 struct hns3_nic_priv *priv = cb_priv; 2538 2539 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data)) 2540 return -EOPNOTSUPP; 2541 2542 switch (type) { 2543 case TC_SETUP_CLSFLOWER: 2544 return hns3_setup_tc_cls_flower(priv, type_data); 2545 default: 2546 return -EOPNOTSUPP; 2547 } 2548 } 2549 2550 static LIST_HEAD(hns3_block_cb_list); 2551 2552 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 2553 void *type_data) 2554 { 2555 struct hns3_nic_priv *priv = netdev_priv(dev); 2556 int ret; 2557 2558 switch (type) { 2559 case TC_SETUP_QDISC_MQPRIO: 2560 ret = hns3_setup_tc(dev, type_data); 2561 break; 2562 case TC_SETUP_BLOCK: 2563 ret = flow_block_cb_setup_simple(type_data, 2564 &hns3_block_cb_list, 2565 hns3_setup_tc_block_cb, 2566 priv, priv, true); 2567 break; 2568 default: 2569 return -EOPNOTSUPP; 2570 } 2571 2572 return ret; 2573 } 2574 2575 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 2576 __be16 proto, u16 vid) 2577 { 2578 struct hnae3_handle *h = hns3_get_handle(netdev); 2579 int ret = -EIO; 2580 2581 if (h->ae_algo->ops->set_vlan_filter) 2582 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 2583 2584 return ret; 2585 } 2586 2587 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 2588 __be16 proto, u16 vid) 2589 { 2590 struct hnae3_handle *h = hns3_get_handle(netdev); 2591 int ret = -EIO; 2592 2593 if (h->ae_algo->ops->set_vlan_filter) 2594 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 2595 2596 return ret; 2597 } 2598 2599 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2600 u8 qos, __be16 vlan_proto) 2601 { 2602 struct hnae3_handle *h = hns3_get_handle(netdev); 2603 int ret = -EIO; 2604 2605 netif_dbg(h, drv, netdev, 2606 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n", 2607 vf, vlan, qos, ntohs(vlan_proto)); 2608 2609 if (h->ae_algo->ops->set_vf_vlan_filter) 2610 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 2611 qos, vlan_proto); 2612 2613 return ret; 2614 } 2615 2616 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable) 2617 { 2618 struct hnae3_handle *handle = hns3_get_handle(netdev); 2619 2620 if (hns3_nic_resetting(netdev)) 2621 return -EBUSY; 2622 2623 if (!handle->ae_algo->ops->set_vf_spoofchk) 2624 return -EOPNOTSUPP; 2625 2626 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable); 2627 } 2628 2629 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable) 2630 { 2631 struct hnae3_handle *handle = hns3_get_handle(netdev); 2632 2633 if (!handle->ae_algo->ops->set_vf_trust) 2634 return -EOPNOTSUPP; 2635 2636 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable); 2637 } 2638 2639 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 2640 { 2641 struct hnae3_handle *h = hns3_get_handle(netdev); 2642 int ret; 2643 2644 if (hns3_nic_resetting(netdev)) 2645 return -EBUSY; 2646 2647 if (!h->ae_algo->ops->set_mtu) 2648 return -EOPNOTSUPP; 2649 2650 netif_dbg(h, drv, netdev, 2651 "change mtu from %u to %d\n", netdev->mtu, new_mtu); 2652 2653 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 2654 if (ret) 2655 netdev_err(netdev, "failed to change MTU in hardware %d\n", 2656 ret); 2657 else 2658 netdev->mtu = new_mtu; 2659 2660 return ret; 2661 } 2662 2663 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 2664 { 2665 struct hns3_nic_priv *priv = netdev_priv(ndev); 2666 struct hnae3_handle *h = hns3_get_handle(ndev); 2667 struct hns3_enet_ring *tx_ring; 2668 struct napi_struct *napi; 2669 int timeout_queue = 0; 2670 int hw_head, hw_tail; 2671 int fbd_num, fbd_oft; 2672 int ebd_num, ebd_oft; 2673 int bd_num, bd_err; 2674 int ring_en, tc; 2675 int i; 2676 2677 /* Find the stopped queue the same way the stack does */ 2678 for (i = 0; i < ndev->num_tx_queues; i++) { 2679 struct netdev_queue *q; 2680 unsigned long trans_start; 2681 2682 q = netdev_get_tx_queue(ndev, i); 2683 trans_start = q->trans_start; 2684 if (netif_xmit_stopped(q) && 2685 time_after(jiffies, 2686 (trans_start + ndev->watchdog_timeo))) { 2687 timeout_queue = i; 2688 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n", 2689 q->state, 2690 jiffies_to_msecs(jiffies - trans_start)); 2691 break; 2692 } 2693 } 2694 2695 if (i == ndev->num_tx_queues) { 2696 netdev_info(ndev, 2697 "no netdev TX timeout queue found, timeout count: %llu\n", 2698 priv->tx_timeout_count); 2699 return false; 2700 } 2701 2702 priv->tx_timeout_count++; 2703 2704 tx_ring = &priv->ring[timeout_queue]; 2705 napi = &tx_ring->tqp_vector->napi; 2706 2707 netdev_info(ndev, 2708 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n", 2709 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use, 2710 tx_ring->next_to_clean, napi->state); 2711 2712 netdev_info(ndev, 2713 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n", 2714 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes, 2715 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf); 2716 2717 netdev_info(ndev, 2718 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n", 2719 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more, 2720 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy); 2721 2722 /* When mac received many pause frames continuous, it's unable to send 2723 * packets, which may cause tx timeout 2724 */ 2725 if (h->ae_algo->ops->get_mac_stats) { 2726 struct hns3_mac_stats mac_stats; 2727 2728 h->ae_algo->ops->get_mac_stats(h, &mac_stats); 2729 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n", 2730 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt); 2731 } 2732 2733 hw_head = readl_relaxed(tx_ring->tqp->io_base + 2734 HNS3_RING_TX_RING_HEAD_REG); 2735 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 2736 HNS3_RING_TX_RING_TAIL_REG); 2737 fbd_num = readl_relaxed(tx_ring->tqp->io_base + 2738 HNS3_RING_TX_RING_FBDNUM_REG); 2739 fbd_oft = readl_relaxed(tx_ring->tqp->io_base + 2740 HNS3_RING_TX_RING_OFFSET_REG); 2741 ebd_num = readl_relaxed(tx_ring->tqp->io_base + 2742 HNS3_RING_TX_RING_EBDNUM_REG); 2743 ebd_oft = readl_relaxed(tx_ring->tqp->io_base + 2744 HNS3_RING_TX_RING_EBD_OFFSET_REG); 2745 bd_num = readl_relaxed(tx_ring->tqp->io_base + 2746 HNS3_RING_TX_RING_BD_NUM_REG); 2747 bd_err = readl_relaxed(tx_ring->tqp->io_base + 2748 HNS3_RING_TX_RING_BD_ERR_REG); 2749 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG); 2750 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG); 2751 2752 netdev_info(ndev, 2753 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n", 2754 bd_num, hw_head, hw_tail, bd_err, 2755 readl(tx_ring->tqp_vector->mask_addr)); 2756 netdev_info(ndev, 2757 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n", 2758 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft); 2759 2760 return true; 2761 } 2762 2763 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue) 2764 { 2765 struct hns3_nic_priv *priv = netdev_priv(ndev); 2766 struct hnae3_handle *h = priv->ae_handle; 2767 2768 if (!hns3_get_tx_timeo_queue_info(ndev)) 2769 return; 2770 2771 /* request the reset, and let the hclge to determine 2772 * which reset level should be done 2773 */ 2774 if (h->ae_algo->ops->reset_event) 2775 h->ae_algo->ops->reset_event(h->pdev, h); 2776 } 2777 2778 #ifdef CONFIG_RFS_ACCEL 2779 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 2780 u16 rxq_index, u32 flow_id) 2781 { 2782 struct hnae3_handle *h = hns3_get_handle(dev); 2783 struct flow_keys fkeys; 2784 2785 if (!h->ae_algo->ops->add_arfs_entry) 2786 return -EOPNOTSUPP; 2787 2788 if (skb->encapsulation) 2789 return -EPROTONOSUPPORT; 2790 2791 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0)) 2792 return -EPROTONOSUPPORT; 2793 2794 if ((fkeys.basic.n_proto != htons(ETH_P_IP) && 2795 fkeys.basic.n_proto != htons(ETH_P_IPV6)) || 2796 (fkeys.basic.ip_proto != IPPROTO_TCP && 2797 fkeys.basic.ip_proto != IPPROTO_UDP)) 2798 return -EPROTONOSUPPORT; 2799 2800 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys); 2801 } 2802 #endif 2803 2804 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf, 2805 struct ifla_vf_info *ivf) 2806 { 2807 struct hnae3_handle *h = hns3_get_handle(ndev); 2808 2809 if (!h->ae_algo->ops->get_vf_config) 2810 return -EOPNOTSUPP; 2811 2812 return h->ae_algo->ops->get_vf_config(h, vf, ivf); 2813 } 2814 2815 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf, 2816 int link_state) 2817 { 2818 struct hnae3_handle *h = hns3_get_handle(ndev); 2819 2820 if (!h->ae_algo->ops->set_vf_link_state) 2821 return -EOPNOTSUPP; 2822 2823 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state); 2824 } 2825 2826 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf, 2827 int min_tx_rate, int max_tx_rate) 2828 { 2829 struct hnae3_handle *h = hns3_get_handle(ndev); 2830 2831 if (!h->ae_algo->ops->set_vf_rate) 2832 return -EOPNOTSUPP; 2833 2834 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate, 2835 false); 2836 } 2837 2838 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) 2839 { 2840 struct hnae3_handle *h = hns3_get_handle(netdev); 2841 2842 if (!h->ae_algo->ops->set_vf_mac) 2843 return -EOPNOTSUPP; 2844 2845 if (is_multicast_ether_addr(mac)) { 2846 netdev_err(netdev, 2847 "Invalid MAC:%pM specified. Could not set MAC\n", 2848 mac); 2849 return -EINVAL; 2850 } 2851 2852 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac); 2853 } 2854 2855 static const struct net_device_ops hns3_nic_netdev_ops = { 2856 .ndo_open = hns3_nic_net_open, 2857 .ndo_stop = hns3_nic_net_stop, 2858 .ndo_start_xmit = hns3_nic_net_xmit, 2859 .ndo_tx_timeout = hns3_nic_net_timeout, 2860 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 2861 .ndo_eth_ioctl = hns3_nic_do_ioctl, 2862 .ndo_change_mtu = hns3_nic_change_mtu, 2863 .ndo_set_features = hns3_nic_set_features, 2864 .ndo_features_check = hns3_features_check, 2865 .ndo_get_stats64 = hns3_nic_get_stats64, 2866 .ndo_setup_tc = hns3_nic_setup_tc, 2867 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 2868 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 2869 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 2870 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 2871 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk, 2872 .ndo_set_vf_trust = hns3_set_vf_trust, 2873 #ifdef CONFIG_RFS_ACCEL 2874 .ndo_rx_flow_steer = hns3_rx_flow_steer, 2875 #endif 2876 .ndo_get_vf_config = hns3_nic_get_vf_config, 2877 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state, 2878 .ndo_set_vf_rate = hns3_nic_set_vf_rate, 2879 .ndo_set_vf_mac = hns3_nic_set_vf_mac, 2880 }; 2881 2882 bool hns3_is_phys_func(struct pci_dev *pdev) 2883 { 2884 u32 dev_id = pdev->device; 2885 2886 switch (dev_id) { 2887 case HNAE3_DEV_ID_GE: 2888 case HNAE3_DEV_ID_25GE: 2889 case HNAE3_DEV_ID_25GE_RDMA: 2890 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 2891 case HNAE3_DEV_ID_50GE_RDMA: 2892 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 2893 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 2894 case HNAE3_DEV_ID_200G_RDMA: 2895 return true; 2896 case HNAE3_DEV_ID_VF: 2897 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF: 2898 return false; 2899 default: 2900 dev_warn(&pdev->dev, "un-recognized pci device-id %u", 2901 dev_id); 2902 } 2903 2904 return false; 2905 } 2906 2907 static void hns3_disable_sriov(struct pci_dev *pdev) 2908 { 2909 /* If our VFs are assigned we cannot shut down SR-IOV 2910 * without causing issues, so just leave the hardware 2911 * available but disabled 2912 */ 2913 if (pci_vfs_assigned(pdev)) { 2914 dev_warn(&pdev->dev, 2915 "disabling driver while VFs are assigned\n"); 2916 return; 2917 } 2918 2919 pci_disable_sriov(pdev); 2920 } 2921 2922 /* hns3_probe - Device initialization routine 2923 * @pdev: PCI device information struct 2924 * @ent: entry in hns3_pci_tbl 2925 * 2926 * hns3_probe initializes a PF identified by a pci_dev structure. 2927 * The OS initialization, configuring of the PF private structure, 2928 * and a hardware reset occur. 2929 * 2930 * Returns 0 on success, negative on failure 2931 */ 2932 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2933 { 2934 struct hnae3_ae_dev *ae_dev; 2935 int ret; 2936 2937 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL); 2938 if (!ae_dev) 2939 return -ENOMEM; 2940 2941 ae_dev->pdev = pdev; 2942 ae_dev->flag = ent->driver_data; 2943 pci_set_drvdata(pdev, ae_dev); 2944 2945 ret = hnae3_register_ae_dev(ae_dev); 2946 if (ret) 2947 pci_set_drvdata(pdev, NULL); 2948 2949 return ret; 2950 } 2951 2952 /* hns3_remove - Device removal routine 2953 * @pdev: PCI device information struct 2954 */ 2955 static void hns3_remove(struct pci_dev *pdev) 2956 { 2957 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 2958 2959 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 2960 hns3_disable_sriov(pdev); 2961 2962 hnae3_unregister_ae_dev(ae_dev); 2963 pci_set_drvdata(pdev, NULL); 2964 } 2965 2966 /** 2967 * hns3_pci_sriov_configure 2968 * @pdev: pointer to a pci_dev structure 2969 * @num_vfs: number of VFs to allocate 2970 * 2971 * Enable or change the number of VFs. Called when the user updates the number 2972 * of VFs in sysfs. 2973 **/ 2974 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 2975 { 2976 int ret; 2977 2978 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 2979 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 2980 return -EINVAL; 2981 } 2982 2983 if (num_vfs) { 2984 ret = pci_enable_sriov(pdev, num_vfs); 2985 if (ret) 2986 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 2987 else 2988 return num_vfs; 2989 } else if (!pci_vfs_assigned(pdev)) { 2990 pci_disable_sriov(pdev); 2991 } else { 2992 dev_warn(&pdev->dev, 2993 "Unable to free VFs because some are assigned to VMs.\n"); 2994 } 2995 2996 return 0; 2997 } 2998 2999 static void hns3_shutdown(struct pci_dev *pdev) 3000 { 3001 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3002 3003 hnae3_unregister_ae_dev(ae_dev); 3004 pci_set_drvdata(pdev, NULL); 3005 3006 if (system_state == SYSTEM_POWER_OFF) 3007 pci_set_power_state(pdev, PCI_D3hot); 3008 } 3009 3010 static int __maybe_unused hns3_suspend(struct device *dev) 3011 { 3012 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev); 3013 3014 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) { 3015 dev_info(dev, "Begin to suspend.\n"); 3016 if (ae_dev->ops && ae_dev->ops->reset_prepare) 3017 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET); 3018 } 3019 3020 return 0; 3021 } 3022 3023 static int __maybe_unused hns3_resume(struct device *dev) 3024 { 3025 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev); 3026 3027 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) { 3028 dev_info(dev, "Begin to resume.\n"); 3029 if (ae_dev->ops && ae_dev->ops->reset_done) 3030 ae_dev->ops->reset_done(ae_dev); 3031 } 3032 3033 return 0; 3034 } 3035 3036 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 3037 pci_channel_state_t state) 3038 { 3039 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3040 pci_ers_result_t ret; 3041 3042 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state); 3043 3044 if (state == pci_channel_io_perm_failure) 3045 return PCI_ERS_RESULT_DISCONNECT; 3046 3047 if (!ae_dev || !ae_dev->ops) { 3048 dev_err(&pdev->dev, 3049 "Can't recover - error happened before device initialized\n"); 3050 return PCI_ERS_RESULT_NONE; 3051 } 3052 3053 if (ae_dev->ops->handle_hw_ras_error) 3054 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 3055 else 3056 return PCI_ERS_RESULT_NONE; 3057 3058 return ret; 3059 } 3060 3061 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 3062 { 3063 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3064 const struct hnae3_ae_ops *ops; 3065 enum hnae3_reset_type reset_type; 3066 struct device *dev = &pdev->dev; 3067 3068 if (!ae_dev || !ae_dev->ops) 3069 return PCI_ERS_RESULT_NONE; 3070 3071 ops = ae_dev->ops; 3072 /* request the reset */ 3073 if (ops->reset_event && ops->get_reset_level && 3074 ops->set_default_reset_request) { 3075 if (ae_dev->hw_err_reset_req) { 3076 reset_type = ops->get_reset_level(ae_dev, 3077 &ae_dev->hw_err_reset_req); 3078 ops->set_default_reset_request(ae_dev, reset_type); 3079 dev_info(dev, "requesting reset due to PCI error\n"); 3080 ops->reset_event(pdev, NULL); 3081 } 3082 3083 return PCI_ERS_RESULT_RECOVERED; 3084 } 3085 3086 return PCI_ERS_RESULT_DISCONNECT; 3087 } 3088 3089 static void hns3_reset_prepare(struct pci_dev *pdev) 3090 { 3091 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3092 3093 dev_info(&pdev->dev, "FLR prepare\n"); 3094 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare) 3095 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET); 3096 } 3097 3098 static void hns3_reset_done(struct pci_dev *pdev) 3099 { 3100 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3101 3102 dev_info(&pdev->dev, "FLR done\n"); 3103 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done) 3104 ae_dev->ops->reset_done(ae_dev); 3105 } 3106 3107 static const struct pci_error_handlers hns3_err_handler = { 3108 .error_detected = hns3_error_detected, 3109 .slot_reset = hns3_slot_reset, 3110 .reset_prepare = hns3_reset_prepare, 3111 .reset_done = hns3_reset_done, 3112 }; 3113 3114 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume); 3115 3116 static struct pci_driver hns3_driver = { 3117 .name = hns3_driver_name, 3118 .id_table = hns3_pci_tbl, 3119 .probe = hns3_probe, 3120 .remove = hns3_remove, 3121 .shutdown = hns3_shutdown, 3122 .driver.pm = &hns3_pm_ops, 3123 .sriov_configure = hns3_pci_sriov_configure, 3124 .err_handler = &hns3_err_handler, 3125 }; 3126 3127 /* set default feature to hns3 */ 3128 static void hns3_set_default_feature(struct net_device *netdev) 3129 { 3130 struct hnae3_handle *h = hns3_get_handle(netdev); 3131 struct pci_dev *pdev = h->pdev; 3132 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3133 3134 netdev->priv_flags |= IFF_UNICAST_FLT; 3135 3136 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 3137 3138 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3139 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 3140 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 3141 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 3142 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 3143 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 3144 3145 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3146 netdev->features |= NETIF_F_GRO_HW; 3147 3148 if (!(h->flags & HNAE3_SUPPORT_VF)) 3149 netdev->features |= NETIF_F_NTUPLE; 3150 } 3151 3152 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps)) 3153 netdev->features |= NETIF_F_GSO_UDP_L4; 3154 3155 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) 3156 netdev->features |= NETIF_F_HW_CSUM; 3157 else 3158 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 3159 3160 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps)) 3161 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 3162 3163 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) 3164 netdev->features |= NETIF_F_HW_TC; 3165 3166 netdev->hw_features |= netdev->features; 3167 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 3168 netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 3169 3170 netdev->vlan_features |= netdev->features & 3171 ~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX | 3172 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE | 3173 NETIF_F_HW_TC); 3174 3175 netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID; 3176 } 3177 3178 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 3179 struct hns3_desc_cb *cb) 3180 { 3181 unsigned int order = hns3_page_order(ring); 3182 struct page *p; 3183 3184 if (ring->page_pool) { 3185 p = page_pool_dev_alloc_frag(ring->page_pool, 3186 &cb->page_offset, 3187 hns3_buf_size(ring)); 3188 if (unlikely(!p)) 3189 return -ENOMEM; 3190 3191 cb->priv = p; 3192 cb->buf = page_address(p); 3193 cb->dma = page_pool_get_dma_addr(p); 3194 cb->type = DESC_TYPE_PP_FRAG; 3195 cb->reuse_flag = 0; 3196 return 0; 3197 } 3198 3199 p = dev_alloc_pages(order); 3200 if (!p) 3201 return -ENOMEM; 3202 3203 cb->priv = p; 3204 cb->page_offset = 0; 3205 cb->reuse_flag = 0; 3206 cb->buf = page_address(p); 3207 cb->length = hns3_page_size(ring); 3208 cb->type = DESC_TYPE_PAGE; 3209 page_ref_add(p, USHRT_MAX - 1); 3210 cb->pagecnt_bias = USHRT_MAX; 3211 3212 return 0; 3213 } 3214 3215 static void hns3_free_buffer(struct hns3_enet_ring *ring, 3216 struct hns3_desc_cb *cb, int budget) 3217 { 3218 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD | 3219 DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB)) 3220 napi_consume_skb(cb->priv, budget); 3221 else if (!HNAE3_IS_TX_RING(ring)) { 3222 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias) 3223 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias); 3224 else if (cb->type & DESC_TYPE_PP_FRAG) 3225 page_pool_put_full_page(ring->page_pool, cb->priv, 3226 false); 3227 } 3228 memset(cb, 0, sizeof(*cb)); 3229 } 3230 3231 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 3232 { 3233 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 3234 cb->length, ring_to_dma_dir(ring)); 3235 3236 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 3237 return -EIO; 3238 3239 return 0; 3240 } 3241 3242 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 3243 struct hns3_desc_cb *cb) 3244 { 3245 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB)) 3246 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 3247 ring_to_dma_dir(ring)); 3248 else if ((cb->type & DESC_TYPE_PAGE) && cb->length) 3249 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 3250 ring_to_dma_dir(ring)); 3251 else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD | 3252 DESC_TYPE_SGL_SKB)) 3253 hns3_tx_spare_reclaim_cb(ring, cb); 3254 } 3255 3256 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 3257 { 3258 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 3259 ring->desc[i].addr = 0; 3260 } 3261 3262 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i, 3263 int budget) 3264 { 3265 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 3266 3267 if (!ring->desc_cb[i].dma) 3268 return; 3269 3270 hns3_buffer_detach(ring, i); 3271 hns3_free_buffer(ring, cb, budget); 3272 } 3273 3274 static void hns3_free_buffers(struct hns3_enet_ring *ring) 3275 { 3276 int i; 3277 3278 for (i = 0; i < ring->desc_num; i++) 3279 hns3_free_buffer_detach(ring, i, 0); 3280 } 3281 3282 /* free desc along with its attached buffer */ 3283 static void hns3_free_desc(struct hns3_enet_ring *ring) 3284 { 3285 int size = ring->desc_num * sizeof(ring->desc[0]); 3286 3287 hns3_free_buffers(ring); 3288 3289 if (ring->desc) { 3290 dma_free_coherent(ring_to_dev(ring), size, 3291 ring->desc, ring->desc_dma_addr); 3292 ring->desc = NULL; 3293 } 3294 } 3295 3296 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 3297 { 3298 int size = ring->desc_num * sizeof(ring->desc[0]); 3299 3300 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 3301 &ring->desc_dma_addr, GFP_KERNEL); 3302 if (!ring->desc) 3303 return -ENOMEM; 3304 3305 return 0; 3306 } 3307 3308 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring, 3309 struct hns3_desc_cb *cb) 3310 { 3311 int ret; 3312 3313 ret = hns3_alloc_buffer(ring, cb); 3314 if (ret || ring->page_pool) 3315 goto out; 3316 3317 ret = hns3_map_buffer(ring, cb); 3318 if (ret) 3319 goto out_with_buf; 3320 3321 return 0; 3322 3323 out_with_buf: 3324 hns3_free_buffer(ring, cb, 0); 3325 out: 3326 return ret; 3327 } 3328 3329 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i) 3330 { 3331 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]); 3332 3333 if (ret) 3334 return ret; 3335 3336 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 3337 ring->desc_cb[i].page_offset); 3338 3339 return 0; 3340 } 3341 3342 /* Allocate memory for raw pkg, and map with dma */ 3343 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 3344 { 3345 int i, j, ret; 3346 3347 for (i = 0; i < ring->desc_num; i++) { 3348 ret = hns3_alloc_and_attach_buffer(ring, i); 3349 if (ret) 3350 goto out_buffer_fail; 3351 } 3352 3353 return 0; 3354 3355 out_buffer_fail: 3356 for (j = i - 1; j >= 0; j--) 3357 hns3_free_buffer_detach(ring, j, 0); 3358 return ret; 3359 } 3360 3361 /* detach a in-used buffer and replace with a reserved one */ 3362 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 3363 struct hns3_desc_cb *res_cb) 3364 { 3365 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 3366 ring->desc_cb[i] = *res_cb; 3367 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 3368 ring->desc_cb[i].page_offset); 3369 ring->desc[i].rx.bd_base_info = 0; 3370 } 3371 3372 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 3373 { 3374 ring->desc_cb[i].reuse_flag = 0; 3375 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 3376 ring->desc_cb[i].page_offset); 3377 ring->desc[i].rx.bd_base_info = 0; 3378 3379 dma_sync_single_for_device(ring_to_dev(ring), 3380 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset, 3381 hns3_buf_size(ring), 3382 DMA_FROM_DEVICE); 3383 } 3384 3385 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, 3386 int *bytes, int *pkts, int budget) 3387 { 3388 /* pair with ring->last_to_use update in hns3_tx_doorbell(), 3389 * smp_store_release() is not used in hns3_tx_doorbell() because 3390 * the doorbell operation already have the needed barrier operation. 3391 */ 3392 int ltu = smp_load_acquire(&ring->last_to_use); 3393 int ntc = ring->next_to_clean; 3394 struct hns3_desc_cb *desc_cb; 3395 bool reclaimed = false; 3396 struct hns3_desc *desc; 3397 3398 while (ltu != ntc) { 3399 desc = &ring->desc[ntc]; 3400 3401 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) & 3402 BIT(HNS3_TXD_VLD_B)) 3403 break; 3404 3405 desc_cb = &ring->desc_cb[ntc]; 3406 3407 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL | 3408 DESC_TYPE_BOUNCE_HEAD | 3409 DESC_TYPE_SGL_SKB)) { 3410 (*pkts)++; 3411 (*bytes) += desc_cb->send_bytes; 3412 } 3413 3414 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */ 3415 hns3_free_buffer_detach(ring, ntc, budget); 3416 3417 if (++ntc == ring->desc_num) 3418 ntc = 0; 3419 3420 /* Issue prefetch for next Tx descriptor */ 3421 prefetch(&ring->desc_cb[ntc]); 3422 reclaimed = true; 3423 } 3424 3425 if (unlikely(!reclaimed)) 3426 return false; 3427 3428 /* This smp_store_release() pairs with smp_load_acquire() in 3429 * ring_space called by hns3_nic_net_xmit. 3430 */ 3431 smp_store_release(&ring->next_to_clean, ntc); 3432 3433 hns3_tx_spare_update(ring); 3434 3435 return true; 3436 } 3437 3438 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget) 3439 { 3440 struct net_device *netdev = ring_to_netdev(ring); 3441 struct hns3_nic_priv *priv = netdev_priv(netdev); 3442 struct netdev_queue *dev_queue; 3443 int bytes, pkts; 3444 3445 bytes = 0; 3446 pkts = 0; 3447 3448 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget))) 3449 return; 3450 3451 ring->tqp_vector->tx_group.total_bytes += bytes; 3452 ring->tqp_vector->tx_group.total_packets += pkts; 3453 3454 u64_stats_update_begin(&ring->syncp); 3455 ring->stats.tx_bytes += bytes; 3456 ring->stats.tx_pkts += pkts; 3457 u64_stats_update_end(&ring->syncp); 3458 3459 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 3460 netdev_tx_completed_queue(dev_queue, pkts, bytes); 3461 3462 if (unlikely(netif_carrier_ok(netdev) && 3463 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) { 3464 /* Make sure that anybody stopping the queue after this 3465 * sees the new next_to_clean. 3466 */ 3467 smp_mb(); 3468 if (netif_tx_queue_stopped(dev_queue) && 3469 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 3470 netif_tx_wake_queue(dev_queue); 3471 ring->stats.restart_queue++; 3472 } 3473 } 3474 } 3475 3476 static int hns3_desc_unused(struct hns3_enet_ring *ring) 3477 { 3478 int ntc = ring->next_to_clean; 3479 int ntu = ring->next_to_use; 3480 3481 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 3482 } 3483 3484 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, 3485 int cleand_count) 3486 { 3487 struct hns3_desc_cb *desc_cb; 3488 struct hns3_desc_cb res_cbs; 3489 int i, ret; 3490 3491 for (i = 0; i < cleand_count; i++) { 3492 desc_cb = &ring->desc_cb[ring->next_to_use]; 3493 if (desc_cb->reuse_flag) { 3494 u64_stats_update_begin(&ring->syncp); 3495 ring->stats.reuse_pg_cnt++; 3496 u64_stats_update_end(&ring->syncp); 3497 3498 hns3_reuse_buffer(ring, ring->next_to_use); 3499 } else { 3500 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 3501 if (ret) { 3502 u64_stats_update_begin(&ring->syncp); 3503 ring->stats.sw_err_cnt++; 3504 u64_stats_update_end(&ring->syncp); 3505 3506 hns3_rl_err(ring_to_netdev(ring), 3507 "alloc rx buffer failed: %d\n", 3508 ret); 3509 break; 3510 } 3511 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 3512 3513 u64_stats_update_begin(&ring->syncp); 3514 ring->stats.non_reuse_pg++; 3515 u64_stats_update_end(&ring->syncp); 3516 } 3517 3518 ring_ptr_move_fw(ring, next_to_use); 3519 } 3520 3521 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 3522 } 3523 3524 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb) 3525 { 3526 return page_count(cb->priv) == cb->pagecnt_bias; 3527 } 3528 3529 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 3530 struct hns3_enet_ring *ring, int pull_len, 3531 struct hns3_desc_cb *desc_cb) 3532 { 3533 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 3534 u32 frag_offset = desc_cb->page_offset + pull_len; 3535 int size = le16_to_cpu(desc->rx.size); 3536 u32 truesize = hns3_buf_size(ring); 3537 u32 frag_size = size - pull_len; 3538 bool reused; 3539 3540 if (ring->page_pool) { 3541 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset, 3542 frag_size, truesize); 3543 return; 3544 } 3545 3546 /* Avoid re-using remote or pfmem page */ 3547 if (unlikely(!dev_page_is_reusable(desc_cb->priv))) 3548 goto out; 3549 3550 reused = hns3_can_reuse_page(desc_cb); 3551 3552 /* Rx page can be reused when: 3553 * 1. Rx page is only owned by the driver when page_offset 3554 * is zero, which means 0 @ truesize will be used by 3555 * stack after skb_add_rx_frag() is called, and the rest 3556 * of rx page can be reused by driver. 3557 * Or 3558 * 2. Rx page is only owned by the driver when page_offset 3559 * is non-zero, which means page_offset @ truesize will 3560 * be used by stack after skb_add_rx_frag() is called, 3561 * and 0 @ truesize can be reused by driver. 3562 */ 3563 if ((!desc_cb->page_offset && reused) || 3564 ((desc_cb->page_offset + truesize + truesize) <= 3565 hns3_page_size(ring) && desc_cb->page_offset)) { 3566 desc_cb->page_offset += truesize; 3567 desc_cb->reuse_flag = 1; 3568 } else if (desc_cb->page_offset && reused) { 3569 desc_cb->page_offset = 0; 3570 desc_cb->reuse_flag = 1; 3571 } else if (frag_size <= ring->rx_copybreak) { 3572 void *frag = napi_alloc_frag(frag_size); 3573 3574 if (unlikely(!frag)) { 3575 u64_stats_update_begin(&ring->syncp); 3576 ring->stats.frag_alloc_err++; 3577 u64_stats_update_end(&ring->syncp); 3578 3579 hns3_rl_err(ring_to_netdev(ring), 3580 "failed to allocate rx frag\n"); 3581 goto out; 3582 } 3583 3584 desc_cb->reuse_flag = 1; 3585 memcpy(frag, desc_cb->buf + frag_offset, frag_size); 3586 skb_add_rx_frag(skb, i, virt_to_page(frag), 3587 offset_in_page(frag), frag_size, frag_size); 3588 3589 u64_stats_update_begin(&ring->syncp); 3590 ring->stats.frag_alloc++; 3591 u64_stats_update_end(&ring->syncp); 3592 return; 3593 } 3594 3595 out: 3596 desc_cb->pagecnt_bias--; 3597 3598 if (unlikely(!desc_cb->pagecnt_bias)) { 3599 page_ref_add(desc_cb->priv, USHRT_MAX); 3600 desc_cb->pagecnt_bias = USHRT_MAX; 3601 } 3602 3603 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset, 3604 frag_size, truesize); 3605 3606 if (unlikely(!desc_cb->reuse_flag)) 3607 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias); 3608 } 3609 3610 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) 3611 { 3612 __be16 type = skb->protocol; 3613 struct tcphdr *th; 3614 int depth = 0; 3615 3616 while (eth_type_vlan(type)) { 3617 struct vlan_hdr *vh; 3618 3619 if ((depth + VLAN_HLEN) > skb_headlen(skb)) 3620 return -EFAULT; 3621 3622 vh = (struct vlan_hdr *)(skb->data + depth); 3623 type = vh->h_vlan_encapsulated_proto; 3624 depth += VLAN_HLEN; 3625 } 3626 3627 skb_set_network_header(skb, depth); 3628 3629 if (type == htons(ETH_P_IP)) { 3630 const struct iphdr *iph = ip_hdr(skb); 3631 3632 depth += sizeof(struct iphdr); 3633 skb_set_transport_header(skb, depth); 3634 th = tcp_hdr(skb); 3635 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr, 3636 iph->daddr, 0); 3637 } else if (type == htons(ETH_P_IPV6)) { 3638 const struct ipv6hdr *iph = ipv6_hdr(skb); 3639 3640 depth += sizeof(struct ipv6hdr); 3641 skb_set_transport_header(skb, depth); 3642 th = tcp_hdr(skb); 3643 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr, 3644 &iph->daddr, 0); 3645 } else { 3646 hns3_rl_err(skb->dev, 3647 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n", 3648 be16_to_cpu(type), depth); 3649 return -EFAULT; 3650 } 3651 3652 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 3653 if (th->cwr) 3654 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 3655 3656 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B)) 3657 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID; 3658 3659 skb->csum_start = (unsigned char *)th - skb->head; 3660 skb->csum_offset = offsetof(struct tcphdr, check); 3661 skb->ip_summed = CHECKSUM_PARTIAL; 3662 3663 trace_hns3_gro(skb); 3664 3665 return 0; 3666 } 3667 3668 static bool hns3_checksum_complete(struct hns3_enet_ring *ring, 3669 struct sk_buff *skb, u32 ptype, u16 csum) 3670 { 3671 if (ptype == HNS3_INVALID_PTYPE || 3672 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE) 3673 return false; 3674 3675 u64_stats_update_begin(&ring->syncp); 3676 ring->stats.csum_complete++; 3677 u64_stats_update_end(&ring->syncp); 3678 skb->ip_summed = CHECKSUM_COMPLETE; 3679 skb->csum = csum_unfold((__force __sum16)csum); 3680 3681 return true; 3682 } 3683 3684 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info, 3685 u32 ol_info, u32 ptype) 3686 { 3687 int l3_type, l4_type; 3688 int ol4_type; 3689 3690 if (ptype != HNS3_INVALID_PTYPE) { 3691 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level; 3692 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed; 3693 3694 return; 3695 } 3696 3697 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M, 3698 HNS3_RXD_OL4ID_S); 3699 switch (ol4_type) { 3700 case HNS3_OL4_TYPE_MAC_IN_UDP: 3701 case HNS3_OL4_TYPE_NVGRE: 3702 skb->csum_level = 1; 3703 fallthrough; 3704 case HNS3_OL4_TYPE_NO_TUN: 3705 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 3706 HNS3_RXD_L3ID_S); 3707 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 3708 HNS3_RXD_L4ID_S); 3709 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 3710 if ((l3_type == HNS3_L3_TYPE_IPV4 || 3711 l3_type == HNS3_L3_TYPE_IPV6) && 3712 (l4_type == HNS3_L4_TYPE_UDP || 3713 l4_type == HNS3_L4_TYPE_TCP || 3714 l4_type == HNS3_L4_TYPE_SCTP)) 3715 skb->ip_summed = CHECKSUM_UNNECESSARY; 3716 break; 3717 default: 3718 break; 3719 } 3720 } 3721 3722 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 3723 u32 l234info, u32 bd_base_info, u32 ol_info, 3724 u16 csum) 3725 { 3726 struct net_device *netdev = ring_to_netdev(ring); 3727 struct hns3_nic_priv *priv = netdev_priv(netdev); 3728 u32 ptype = HNS3_INVALID_PTYPE; 3729 3730 skb->ip_summed = CHECKSUM_NONE; 3731 3732 skb_checksum_none_assert(skb); 3733 3734 if (!(netdev->features & NETIF_F_RXCSUM)) 3735 return; 3736 3737 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) 3738 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, 3739 HNS3_RXD_PTYPE_S); 3740 3741 if (hns3_checksum_complete(ring, skb, ptype, csum)) 3742 return; 3743 3744 /* check if hardware has done checksum */ 3745 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 3746 return; 3747 3748 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | 3749 BIT(HNS3_RXD_OL3E_B) | 3750 BIT(HNS3_RXD_OL4E_B)))) { 3751 u64_stats_update_begin(&ring->syncp); 3752 ring->stats.l3l4_csum_err++; 3753 u64_stats_update_end(&ring->syncp); 3754 3755 return; 3756 } 3757 3758 hns3_rx_handle_csum(skb, l234info, ol_info, ptype); 3759 } 3760 3761 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 3762 { 3763 if (skb_has_frag_list(skb)) 3764 napi_gro_flush(&ring->tqp_vector->napi, false); 3765 3766 napi_gro_receive(&ring->tqp_vector->napi, skb); 3767 } 3768 3769 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 3770 struct hns3_desc *desc, u32 l234info, 3771 u16 *vlan_tag) 3772 { 3773 struct hnae3_handle *handle = ring->tqp->handle; 3774 struct pci_dev *pdev = ring->tqp->handle->pdev; 3775 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3776 3777 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) { 3778 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3779 if (!(*vlan_tag & VLAN_VID_MASK)) 3780 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3781 3782 return (*vlan_tag != 0); 3783 } 3784 3785 #define HNS3_STRP_OUTER_VLAN 0x1 3786 #define HNS3_STRP_INNER_VLAN 0x2 3787 #define HNS3_STRP_BOTH 0x3 3788 3789 /* Hardware always insert VLAN tag into RX descriptor when 3790 * remove the tag from packet, driver needs to determine 3791 * reporting which tag to stack. 3792 */ 3793 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 3794 HNS3_RXD_STRP_TAGP_S)) { 3795 case HNS3_STRP_OUTER_VLAN: 3796 if (handle->port_base_vlan_state != 3797 HNAE3_PORT_BASE_VLAN_DISABLE) 3798 return false; 3799 3800 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3801 return true; 3802 case HNS3_STRP_INNER_VLAN: 3803 if (handle->port_base_vlan_state != 3804 HNAE3_PORT_BASE_VLAN_DISABLE) 3805 return false; 3806 3807 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3808 return true; 3809 case HNS3_STRP_BOTH: 3810 if (handle->port_base_vlan_state == 3811 HNAE3_PORT_BASE_VLAN_DISABLE) 3812 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 3813 else 3814 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 3815 3816 return true; 3817 default: 3818 return false; 3819 } 3820 } 3821 3822 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring) 3823 { 3824 ring->desc[ring->next_to_clean].rx.bd_base_info &= 3825 cpu_to_le32(~BIT(HNS3_RXD_VLD_B)); 3826 ring->next_to_clean += 1; 3827 3828 if (unlikely(ring->next_to_clean == ring->desc_num)) 3829 ring->next_to_clean = 0; 3830 } 3831 3832 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length, 3833 unsigned char *va) 3834 { 3835 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 3836 struct net_device *netdev = ring_to_netdev(ring); 3837 struct sk_buff *skb; 3838 3839 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 3840 skb = ring->skb; 3841 if (unlikely(!skb)) { 3842 hns3_rl_err(netdev, "alloc rx skb fail\n"); 3843 3844 u64_stats_update_begin(&ring->syncp); 3845 ring->stats.sw_err_cnt++; 3846 u64_stats_update_end(&ring->syncp); 3847 3848 return -ENOMEM; 3849 } 3850 3851 trace_hns3_rx_desc(ring); 3852 prefetchw(skb->data); 3853 3854 ring->pending_buf = 1; 3855 ring->frag_num = 0; 3856 ring->tail_skb = NULL; 3857 if (length <= HNS3_RX_HEAD_SIZE) { 3858 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 3859 3860 /* We can reuse buffer as-is, just make sure it is reusable */ 3861 if (dev_page_is_reusable(desc_cb->priv)) 3862 desc_cb->reuse_flag = 1; 3863 else if (desc_cb->type & DESC_TYPE_PP_FRAG) 3864 page_pool_put_full_page(ring->page_pool, desc_cb->priv, 3865 false); 3866 else /* This page cannot be reused so discard it */ 3867 __page_frag_cache_drain(desc_cb->priv, 3868 desc_cb->pagecnt_bias); 3869 3870 hns3_rx_ring_move_fw(ring); 3871 return 0; 3872 } 3873 3874 if (ring->page_pool) 3875 skb_mark_for_recycle(skb); 3876 3877 u64_stats_update_begin(&ring->syncp); 3878 ring->stats.seg_pkt_cnt++; 3879 u64_stats_update_end(&ring->syncp); 3880 3881 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE); 3882 __skb_put(skb, ring->pull_len); 3883 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 3884 desc_cb); 3885 hns3_rx_ring_move_fw(ring); 3886 3887 return 0; 3888 } 3889 3890 static int hns3_add_frag(struct hns3_enet_ring *ring) 3891 { 3892 struct sk_buff *skb = ring->skb; 3893 struct sk_buff *head_skb = skb; 3894 struct sk_buff *new_skb; 3895 struct hns3_desc_cb *desc_cb; 3896 struct hns3_desc *desc; 3897 u32 bd_base_info; 3898 3899 do { 3900 desc = &ring->desc[ring->next_to_clean]; 3901 desc_cb = &ring->desc_cb[ring->next_to_clean]; 3902 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 3903 /* make sure HW write desc complete */ 3904 dma_rmb(); 3905 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 3906 return -ENXIO; 3907 3908 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 3909 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0); 3910 if (unlikely(!new_skb)) { 3911 hns3_rl_err(ring_to_netdev(ring), 3912 "alloc rx fraglist skb fail\n"); 3913 return -ENXIO; 3914 } 3915 3916 if (ring->page_pool) 3917 skb_mark_for_recycle(new_skb); 3918 3919 ring->frag_num = 0; 3920 3921 if (ring->tail_skb) { 3922 ring->tail_skb->next = new_skb; 3923 ring->tail_skb = new_skb; 3924 } else { 3925 skb_shinfo(skb)->frag_list = new_skb; 3926 ring->tail_skb = new_skb; 3927 } 3928 } 3929 3930 if (ring->tail_skb) { 3931 head_skb->truesize += hns3_buf_size(ring); 3932 head_skb->data_len += le16_to_cpu(desc->rx.size); 3933 head_skb->len += le16_to_cpu(desc->rx.size); 3934 skb = ring->tail_skb; 3935 } 3936 3937 dma_sync_single_for_cpu(ring_to_dev(ring), 3938 desc_cb->dma + desc_cb->page_offset, 3939 hns3_buf_size(ring), 3940 DMA_FROM_DEVICE); 3941 3942 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 3943 trace_hns3_rx_desc(ring); 3944 hns3_rx_ring_move_fw(ring); 3945 ring->pending_buf++; 3946 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B))); 3947 3948 return 0; 3949 } 3950 3951 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring, 3952 struct sk_buff *skb, u32 l234info, 3953 u32 bd_base_info, u32 ol_info, u16 csum) 3954 { 3955 struct net_device *netdev = ring_to_netdev(ring); 3956 struct hns3_nic_priv *priv = netdev_priv(netdev); 3957 u32 l3_type; 3958 3959 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 3960 HNS3_RXD_GRO_SIZE_M, 3961 HNS3_RXD_GRO_SIZE_S); 3962 /* if there is no HW GRO, do not set gro params */ 3963 if (!skb_shinfo(skb)->gso_size) { 3964 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info, 3965 csum); 3966 return 0; 3967 } 3968 3969 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info, 3970 HNS3_RXD_GRO_COUNT_M, 3971 HNS3_RXD_GRO_COUNT_S); 3972 3973 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) { 3974 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, 3975 HNS3_RXD_PTYPE_S); 3976 3977 l3_type = hns3_rx_ptype_tbl[ptype].l3_type; 3978 } else { 3979 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 3980 HNS3_RXD_L3ID_S); 3981 } 3982 3983 if (l3_type == HNS3_L3_TYPE_IPV4) 3984 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 3985 else if (l3_type == HNS3_L3_TYPE_IPV6) 3986 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 3987 else 3988 return -EFAULT; 3989 3990 return hns3_gro_complete(skb, l234info); 3991 } 3992 3993 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 3994 struct sk_buff *skb, u32 rss_hash) 3995 { 3996 struct hnae3_handle *handle = ring->tqp->handle; 3997 enum pkt_hash_types rss_type; 3998 3999 if (rss_hash) 4000 rss_type = handle->kinfo.rss_type; 4001 else 4002 rss_type = PKT_HASH_TYPE_NONE; 4003 4004 skb_set_hash(skb, rss_hash, rss_type); 4005 } 4006 4007 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb) 4008 { 4009 struct net_device *netdev = ring_to_netdev(ring); 4010 enum hns3_pkt_l2t_type l2_frame_type; 4011 u32 bd_base_info, l234info, ol_info; 4012 struct hns3_desc *desc; 4013 unsigned int len; 4014 int pre_ntc, ret; 4015 u16 csum; 4016 4017 /* bdinfo handled below is only valid on the last BD of the 4018 * current packet, and ring->next_to_clean indicates the first 4019 * descriptor of next packet, so need - 1 below. 4020 */ 4021 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) : 4022 (ring->desc_num - 1); 4023 desc = &ring->desc[pre_ntc]; 4024 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 4025 l234info = le32_to_cpu(desc->rx.l234_info); 4026 ol_info = le32_to_cpu(desc->rx.ol_info); 4027 csum = le16_to_cpu(desc->csum); 4028 4029 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) { 4030 struct hnae3_handle *h = hns3_get_handle(netdev); 4031 u32 nsec = le32_to_cpu(desc->ts_nsec); 4032 u32 sec = le32_to_cpu(desc->ts_sec); 4033 4034 if (h->ae_algo->ops->get_rx_hwts) 4035 h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec); 4036 } 4037 4038 /* Based on hw strategy, the tag offloaded will be stored at 4039 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 4040 * in one layer tag case. 4041 */ 4042 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 4043 u16 vlan_tag; 4044 4045 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 4046 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 4047 vlan_tag); 4048 } 4049 4050 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 4051 BIT(HNS3_RXD_L2E_B))))) { 4052 u64_stats_update_begin(&ring->syncp); 4053 if (l234info & BIT(HNS3_RXD_L2E_B)) 4054 ring->stats.l2_err++; 4055 else 4056 ring->stats.err_pkt_len++; 4057 u64_stats_update_end(&ring->syncp); 4058 4059 return -EFAULT; 4060 } 4061 4062 len = skb->len; 4063 4064 /* Do update ip stack process */ 4065 skb->protocol = eth_type_trans(skb, netdev); 4066 4067 /* This is needed in order to enable forwarding support */ 4068 ret = hns3_set_gro_and_checksum(ring, skb, l234info, 4069 bd_base_info, ol_info, csum); 4070 if (unlikely(ret)) { 4071 u64_stats_update_begin(&ring->syncp); 4072 ring->stats.rx_err_cnt++; 4073 u64_stats_update_end(&ring->syncp); 4074 return ret; 4075 } 4076 4077 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 4078 HNS3_RXD_DMAC_S); 4079 4080 u64_stats_update_begin(&ring->syncp); 4081 ring->stats.rx_pkts++; 4082 ring->stats.rx_bytes += len; 4083 4084 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 4085 ring->stats.rx_multicast++; 4086 4087 u64_stats_update_end(&ring->syncp); 4088 4089 ring->tqp_vector->rx_group.total_bytes += len; 4090 4091 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash)); 4092 return 0; 4093 } 4094 4095 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring) 4096 { 4097 struct sk_buff *skb = ring->skb; 4098 struct hns3_desc_cb *desc_cb; 4099 struct hns3_desc *desc; 4100 unsigned int length; 4101 u32 bd_base_info; 4102 int ret; 4103 4104 desc = &ring->desc[ring->next_to_clean]; 4105 desc_cb = &ring->desc_cb[ring->next_to_clean]; 4106 4107 prefetch(desc); 4108 4109 if (!skb) { 4110 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 4111 /* Check valid BD */ 4112 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 4113 return -ENXIO; 4114 4115 dma_rmb(); 4116 length = le16_to_cpu(desc->rx.size); 4117 4118 ring->va = desc_cb->buf + desc_cb->page_offset; 4119 4120 dma_sync_single_for_cpu(ring_to_dev(ring), 4121 desc_cb->dma + desc_cb->page_offset, 4122 hns3_buf_size(ring), 4123 DMA_FROM_DEVICE); 4124 4125 /* Prefetch first cache line of first page. 4126 * Idea is to cache few bytes of the header of the packet. 4127 * Our L1 Cache line size is 64B so need to prefetch twice to make 4128 * it 128B. But in actual we can have greater size of caches with 4129 * 128B Level 1 cache lines. In such a case, single fetch would 4130 * suffice to cache in the relevant part of the header. 4131 */ 4132 net_prefetch(ring->va); 4133 4134 ret = hns3_alloc_skb(ring, length, ring->va); 4135 skb = ring->skb; 4136 4137 if (ret < 0) /* alloc buffer fail */ 4138 return ret; 4139 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */ 4140 ret = hns3_add_frag(ring); 4141 if (ret) 4142 return ret; 4143 } 4144 } else { 4145 ret = hns3_add_frag(ring); 4146 if (ret) 4147 return ret; 4148 } 4149 4150 /* As the head data may be changed when GRO enable, copy 4151 * the head data in after other data rx completed 4152 */ 4153 if (skb->len > HNS3_RX_HEAD_SIZE) 4154 memcpy(skb->data, ring->va, 4155 ALIGN(ring->pull_len, sizeof(long))); 4156 4157 ret = hns3_handle_bdinfo(ring, skb); 4158 if (unlikely(ret)) { 4159 dev_kfree_skb_any(skb); 4160 return ret; 4161 } 4162 4163 skb_record_rx_queue(skb, ring->tqp->tqp_index); 4164 return 0; 4165 } 4166 4167 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget, 4168 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 4169 { 4170 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 4171 int unused_count = hns3_desc_unused(ring); 4172 int recv_pkts = 0; 4173 int err; 4174 4175 unused_count -= ring->pending_buf; 4176 4177 while (recv_pkts < budget) { 4178 /* Reuse or realloc buffers */ 4179 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 4180 hns3_nic_alloc_rx_buffers(ring, unused_count); 4181 unused_count = hns3_desc_unused(ring) - 4182 ring->pending_buf; 4183 } 4184 4185 /* Poll one pkt */ 4186 err = hns3_handle_rx_bd(ring); 4187 /* Do not get FE for the packet or failed to alloc skb */ 4188 if (unlikely(!ring->skb || err == -ENXIO)) { 4189 goto out; 4190 } else if (likely(!err)) { 4191 rx_fn(ring, ring->skb); 4192 recv_pkts++; 4193 } 4194 4195 unused_count += ring->pending_buf; 4196 ring->skb = NULL; 4197 ring->pending_buf = 0; 4198 } 4199 4200 out: 4201 /* Make all data has been write before submit */ 4202 if (unused_count > 0) 4203 hns3_nic_alloc_rx_buffers(ring, unused_count); 4204 4205 return recv_pkts; 4206 } 4207 4208 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector) 4209 { 4210 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 4211 struct dim_sample sample = {}; 4212 4213 if (!rx_group->coal.adapt_enable) 4214 return; 4215 4216 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets, 4217 rx_group->total_bytes, &sample); 4218 net_dim(&rx_group->dim, sample); 4219 } 4220 4221 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector) 4222 { 4223 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 4224 struct dim_sample sample = {}; 4225 4226 if (!tx_group->coal.adapt_enable) 4227 return; 4228 4229 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets, 4230 tx_group->total_bytes, &sample); 4231 net_dim(&tx_group->dim, sample); 4232 } 4233 4234 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 4235 { 4236 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 4237 struct hns3_enet_ring *ring; 4238 int rx_pkt_total = 0; 4239 4240 struct hns3_enet_tqp_vector *tqp_vector = 4241 container_of(napi, struct hns3_enet_tqp_vector, napi); 4242 bool clean_complete = true; 4243 int rx_budget = budget; 4244 4245 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 4246 napi_complete(napi); 4247 return 0; 4248 } 4249 4250 /* Since the actual Tx work is minimal, we can give the Tx a larger 4251 * budget and be more aggressive about cleaning up the Tx descriptors. 4252 */ 4253 hns3_for_each_ring(ring, tqp_vector->tx_group) 4254 hns3_clean_tx_ring(ring, budget); 4255 4256 /* make sure rx ring budget not smaller than 1 */ 4257 if (tqp_vector->num_tqps > 1) 4258 rx_budget = max(budget / tqp_vector->num_tqps, 1); 4259 4260 hns3_for_each_ring(ring, tqp_vector->rx_group) { 4261 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 4262 hns3_rx_skb); 4263 if (rx_cleaned >= rx_budget) 4264 clean_complete = false; 4265 4266 rx_pkt_total += rx_cleaned; 4267 } 4268 4269 tqp_vector->rx_group.total_packets += rx_pkt_total; 4270 4271 if (!clean_complete) 4272 return budget; 4273 4274 if (napi_complete(napi) && 4275 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 4276 hns3_update_rx_int_coalesce(tqp_vector); 4277 hns3_update_tx_int_coalesce(tqp_vector); 4278 4279 hns3_mask_vector_irq(tqp_vector, 1); 4280 } 4281 4282 return rx_pkt_total; 4283 } 4284 4285 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 4286 struct hnae3_ring_chain_node *head) 4287 { 4288 struct pci_dev *pdev = tqp_vector->handle->pdev; 4289 struct hnae3_ring_chain_node *cur_chain = head; 4290 struct hnae3_ring_chain_node *chain; 4291 struct hns3_enet_ring *tx_ring; 4292 struct hns3_enet_ring *rx_ring; 4293 4294 tx_ring = tqp_vector->tx_group.ring; 4295 if (tx_ring) { 4296 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 4297 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 4298 HNAE3_RING_TYPE_TX); 4299 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 4300 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 4301 4302 cur_chain->next = NULL; 4303 4304 while (tx_ring->next) { 4305 tx_ring = tx_ring->next; 4306 4307 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 4308 GFP_KERNEL); 4309 if (!chain) 4310 goto err_free_chain; 4311 4312 cur_chain->next = chain; 4313 chain->tqp_index = tx_ring->tqp->tqp_index; 4314 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 4315 HNAE3_RING_TYPE_TX); 4316 hnae3_set_field(chain->int_gl_idx, 4317 HNAE3_RING_GL_IDX_M, 4318 HNAE3_RING_GL_IDX_S, 4319 HNAE3_RING_GL_TX); 4320 4321 cur_chain = chain; 4322 } 4323 } 4324 4325 rx_ring = tqp_vector->rx_group.ring; 4326 if (!tx_ring && rx_ring) { 4327 cur_chain->next = NULL; 4328 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 4329 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 4330 HNAE3_RING_TYPE_RX); 4331 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 4332 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 4333 4334 rx_ring = rx_ring->next; 4335 } 4336 4337 while (rx_ring) { 4338 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 4339 if (!chain) 4340 goto err_free_chain; 4341 4342 cur_chain->next = chain; 4343 chain->tqp_index = rx_ring->tqp->tqp_index; 4344 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 4345 HNAE3_RING_TYPE_RX); 4346 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 4347 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 4348 4349 cur_chain = chain; 4350 4351 rx_ring = rx_ring->next; 4352 } 4353 4354 return 0; 4355 4356 err_free_chain: 4357 cur_chain = head->next; 4358 while (cur_chain) { 4359 chain = cur_chain->next; 4360 devm_kfree(&pdev->dev, cur_chain); 4361 cur_chain = chain; 4362 } 4363 head->next = NULL; 4364 4365 return -ENOMEM; 4366 } 4367 4368 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 4369 struct hnae3_ring_chain_node *head) 4370 { 4371 struct pci_dev *pdev = tqp_vector->handle->pdev; 4372 struct hnae3_ring_chain_node *chain_tmp, *chain; 4373 4374 chain = head->next; 4375 4376 while (chain) { 4377 chain_tmp = chain->next; 4378 devm_kfree(&pdev->dev, chain); 4379 chain = chain_tmp; 4380 } 4381 } 4382 4383 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 4384 struct hns3_enet_ring *ring) 4385 { 4386 ring->next = group->ring; 4387 group->ring = ring; 4388 4389 group->count++; 4390 } 4391 4392 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 4393 { 4394 struct pci_dev *pdev = priv->ae_handle->pdev; 4395 struct hns3_enet_tqp_vector *tqp_vector; 4396 int num_vectors = priv->vector_num; 4397 int numa_node; 4398 int vector_i; 4399 4400 numa_node = dev_to_node(&pdev->dev); 4401 4402 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 4403 tqp_vector = &priv->tqp_vector[vector_i]; 4404 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 4405 &tqp_vector->affinity_mask); 4406 } 4407 } 4408 4409 static void hns3_rx_dim_work(struct work_struct *work) 4410 { 4411 struct dim *dim = container_of(work, struct dim, work); 4412 struct hns3_enet_ring_group *group = container_of(dim, 4413 struct hns3_enet_ring_group, dim); 4414 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector; 4415 struct dim_cq_moder cur_moder = 4416 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 4417 4418 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec); 4419 tqp_vector->rx_group.coal.int_gl = cur_moder.usec; 4420 4421 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) { 4422 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts); 4423 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts; 4424 } 4425 4426 dim->state = DIM_START_MEASURE; 4427 } 4428 4429 static void hns3_tx_dim_work(struct work_struct *work) 4430 { 4431 struct dim *dim = container_of(work, struct dim, work); 4432 struct hns3_enet_ring_group *group = container_of(dim, 4433 struct hns3_enet_ring_group, dim); 4434 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector; 4435 struct dim_cq_moder cur_moder = 4436 net_dim_get_tx_moderation(dim->mode, dim->profile_ix); 4437 4438 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec); 4439 tqp_vector->tx_group.coal.int_gl = cur_moder.usec; 4440 4441 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) { 4442 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts); 4443 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts; 4444 } 4445 4446 dim->state = DIM_START_MEASURE; 4447 } 4448 4449 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector) 4450 { 4451 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work); 4452 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work); 4453 } 4454 4455 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 4456 { 4457 struct hnae3_handle *h = priv->ae_handle; 4458 struct hns3_enet_tqp_vector *tqp_vector; 4459 int ret; 4460 int i; 4461 4462 hns3_nic_set_cpumask(priv); 4463 4464 for (i = 0; i < priv->vector_num; i++) { 4465 tqp_vector = &priv->tqp_vector[i]; 4466 hns3_vector_coalesce_init_hw(tqp_vector, priv); 4467 tqp_vector->num_tqps = 0; 4468 hns3_nic_init_dim(tqp_vector); 4469 } 4470 4471 for (i = 0; i < h->kinfo.num_tqps; i++) { 4472 u16 vector_i = i % priv->vector_num; 4473 u16 tqp_num = h->kinfo.num_tqps; 4474 4475 tqp_vector = &priv->tqp_vector[vector_i]; 4476 4477 hns3_add_ring_to_group(&tqp_vector->tx_group, 4478 &priv->ring[i]); 4479 4480 hns3_add_ring_to_group(&tqp_vector->rx_group, 4481 &priv->ring[i + tqp_num]); 4482 4483 priv->ring[i].tqp_vector = tqp_vector; 4484 priv->ring[i + tqp_num].tqp_vector = tqp_vector; 4485 tqp_vector->num_tqps++; 4486 } 4487 4488 for (i = 0; i < priv->vector_num; i++) { 4489 struct hnae3_ring_chain_node vector_ring_chain; 4490 4491 tqp_vector = &priv->tqp_vector[i]; 4492 4493 tqp_vector->rx_group.total_bytes = 0; 4494 tqp_vector->rx_group.total_packets = 0; 4495 tqp_vector->tx_group.total_bytes = 0; 4496 tqp_vector->tx_group.total_packets = 0; 4497 tqp_vector->handle = h; 4498 4499 ret = hns3_get_vector_ring_chain(tqp_vector, 4500 &vector_ring_chain); 4501 if (ret) 4502 goto map_ring_fail; 4503 4504 ret = h->ae_algo->ops->map_ring_to_vector(h, 4505 tqp_vector->vector_irq, &vector_ring_chain); 4506 4507 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 4508 4509 if (ret) 4510 goto map_ring_fail; 4511 4512 netif_napi_add(priv->netdev, &tqp_vector->napi, 4513 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 4514 } 4515 4516 return 0; 4517 4518 map_ring_fail: 4519 while (i--) 4520 netif_napi_del(&priv->tqp_vector[i].napi); 4521 4522 return ret; 4523 } 4524 4525 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv) 4526 { 4527 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 4528 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal; 4529 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal; 4530 4531 /* initialize the configuration for interrupt coalescing. 4532 * 1. GL (Interrupt Gap Limiter) 4533 * 2. RL (Interrupt Rate Limiter) 4534 * 3. QL (Interrupt Quantity Limiter) 4535 * 4536 * Default: enable interrupt coalescing self-adaptive and GL 4537 */ 4538 tx_coal->adapt_enable = 1; 4539 rx_coal->adapt_enable = 1; 4540 4541 tx_coal->int_gl = HNS3_INT_GL_50K; 4542 rx_coal->int_gl = HNS3_INT_GL_50K; 4543 4544 rx_coal->flow_level = HNS3_FLOW_LOW; 4545 tx_coal->flow_level = HNS3_FLOW_LOW; 4546 4547 if (ae_dev->dev_specs.int_ql_max) { 4548 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 4549 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 4550 } 4551 } 4552 4553 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 4554 { 4555 struct hnae3_handle *h = priv->ae_handle; 4556 struct hns3_enet_tqp_vector *tqp_vector; 4557 struct hnae3_vector_info *vector; 4558 struct pci_dev *pdev = h->pdev; 4559 u16 tqp_num = h->kinfo.num_tqps; 4560 u16 vector_num; 4561 int ret = 0; 4562 u16 i; 4563 4564 /* RSS size, cpu online and vector_num should be the same */ 4565 /* Should consider 2p/4p later */ 4566 vector_num = min_t(u16, num_online_cpus(), tqp_num); 4567 4568 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 4569 GFP_KERNEL); 4570 if (!vector) 4571 return -ENOMEM; 4572 4573 /* save the actual available vector number */ 4574 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 4575 4576 priv->vector_num = vector_num; 4577 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 4578 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 4579 GFP_KERNEL); 4580 if (!priv->tqp_vector) { 4581 ret = -ENOMEM; 4582 goto out; 4583 } 4584 4585 for (i = 0; i < priv->vector_num; i++) { 4586 tqp_vector = &priv->tqp_vector[i]; 4587 tqp_vector->idx = i; 4588 tqp_vector->mask_addr = vector[i].io_addr; 4589 tqp_vector->vector_irq = vector[i].vector; 4590 hns3_vector_coalesce_init(tqp_vector, priv); 4591 } 4592 4593 out: 4594 devm_kfree(&pdev->dev, vector); 4595 return ret; 4596 } 4597 4598 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 4599 { 4600 group->ring = NULL; 4601 group->count = 0; 4602 } 4603 4604 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 4605 { 4606 struct hnae3_ring_chain_node vector_ring_chain; 4607 struct hnae3_handle *h = priv->ae_handle; 4608 struct hns3_enet_tqp_vector *tqp_vector; 4609 int i; 4610 4611 for (i = 0; i < priv->vector_num; i++) { 4612 tqp_vector = &priv->tqp_vector[i]; 4613 4614 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 4615 continue; 4616 4617 /* Since the mapping can be overwritten, when fail to get the 4618 * chain between vector and ring, we should go on to deal with 4619 * the remaining options. 4620 */ 4621 if (hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain)) 4622 dev_warn(priv->dev, "failed to get ring chain\n"); 4623 4624 h->ae_algo->ops->unmap_ring_from_vector(h, 4625 tqp_vector->vector_irq, &vector_ring_chain); 4626 4627 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 4628 4629 hns3_clear_ring_group(&tqp_vector->rx_group); 4630 hns3_clear_ring_group(&tqp_vector->tx_group); 4631 netif_napi_del(&priv->tqp_vector[i].napi); 4632 } 4633 } 4634 4635 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 4636 { 4637 struct hnae3_handle *h = priv->ae_handle; 4638 struct pci_dev *pdev = h->pdev; 4639 int i, ret; 4640 4641 for (i = 0; i < priv->vector_num; i++) { 4642 struct hns3_enet_tqp_vector *tqp_vector; 4643 4644 tqp_vector = &priv->tqp_vector[i]; 4645 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 4646 if (ret) 4647 return; 4648 } 4649 4650 devm_kfree(&pdev->dev, priv->tqp_vector); 4651 } 4652 4653 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 4654 unsigned int ring_type) 4655 { 4656 int queue_num = priv->ae_handle->kinfo.num_tqps; 4657 struct hns3_enet_ring *ring; 4658 int desc_num; 4659 4660 if (ring_type == HNAE3_RING_TYPE_TX) { 4661 ring = &priv->ring[q->tqp_index]; 4662 desc_num = priv->ae_handle->kinfo.num_tx_desc; 4663 ring->queue_index = q->tqp_index; 4664 ring->tx_copybreak = priv->tx_copybreak; 4665 ring->last_to_use = 0; 4666 } else { 4667 ring = &priv->ring[q->tqp_index + queue_num]; 4668 desc_num = priv->ae_handle->kinfo.num_rx_desc; 4669 ring->queue_index = q->tqp_index; 4670 ring->rx_copybreak = priv->rx_copybreak; 4671 } 4672 4673 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 4674 4675 ring->tqp = q; 4676 ring->desc = NULL; 4677 ring->desc_cb = NULL; 4678 ring->dev = priv->dev; 4679 ring->desc_dma_addr = 0; 4680 ring->buf_size = q->buf_size; 4681 ring->desc_num = desc_num; 4682 ring->next_to_use = 0; 4683 ring->next_to_clean = 0; 4684 } 4685 4686 static void hns3_queue_to_ring(struct hnae3_queue *tqp, 4687 struct hns3_nic_priv *priv) 4688 { 4689 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 4690 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 4691 } 4692 4693 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 4694 { 4695 struct hnae3_handle *h = priv->ae_handle; 4696 struct pci_dev *pdev = h->pdev; 4697 int i; 4698 4699 priv->ring = devm_kzalloc(&pdev->dev, 4700 array3_size(h->kinfo.num_tqps, 4701 sizeof(*priv->ring), 2), 4702 GFP_KERNEL); 4703 if (!priv->ring) 4704 return -ENOMEM; 4705 4706 for (i = 0; i < h->kinfo.num_tqps; i++) 4707 hns3_queue_to_ring(h->kinfo.tqp[i], priv); 4708 4709 return 0; 4710 } 4711 4712 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 4713 { 4714 if (!priv->ring) 4715 return; 4716 4717 devm_kfree(priv->dev, priv->ring); 4718 priv->ring = NULL; 4719 } 4720 4721 static void hns3_alloc_page_pool(struct hns3_enet_ring *ring) 4722 { 4723 struct page_pool_params pp_params = { 4724 .flags = PP_FLAG_DMA_MAP | PP_FLAG_PAGE_FRAG | 4725 PP_FLAG_DMA_SYNC_DEV, 4726 .order = hns3_page_order(ring), 4727 .pool_size = ring->desc_num * hns3_buf_size(ring) / 4728 (PAGE_SIZE << hns3_page_order(ring)), 4729 .nid = dev_to_node(ring_to_dev(ring)), 4730 .dev = ring_to_dev(ring), 4731 .dma_dir = DMA_FROM_DEVICE, 4732 .offset = 0, 4733 .max_len = PAGE_SIZE << hns3_page_order(ring), 4734 }; 4735 4736 ring->page_pool = page_pool_create(&pp_params); 4737 if (IS_ERR(ring->page_pool)) { 4738 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n", 4739 PTR_ERR(ring->page_pool)); 4740 ring->page_pool = NULL; 4741 } 4742 } 4743 4744 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 4745 { 4746 int ret; 4747 4748 if (ring->desc_num <= 0 || ring->buf_size <= 0) 4749 return -EINVAL; 4750 4751 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num, 4752 sizeof(ring->desc_cb[0]), GFP_KERNEL); 4753 if (!ring->desc_cb) { 4754 ret = -ENOMEM; 4755 goto out; 4756 } 4757 4758 ret = hns3_alloc_desc(ring); 4759 if (ret) 4760 goto out_with_desc_cb; 4761 4762 if (!HNAE3_IS_TX_RING(ring)) { 4763 if (page_pool_enabled) 4764 hns3_alloc_page_pool(ring); 4765 4766 ret = hns3_alloc_ring_buffers(ring); 4767 if (ret) 4768 goto out_with_desc; 4769 } else { 4770 hns3_init_tx_spare_buffer(ring); 4771 } 4772 4773 return 0; 4774 4775 out_with_desc: 4776 hns3_free_desc(ring); 4777 out_with_desc_cb: 4778 devm_kfree(ring_to_dev(ring), ring->desc_cb); 4779 ring->desc_cb = NULL; 4780 out: 4781 return ret; 4782 } 4783 4784 void hns3_fini_ring(struct hns3_enet_ring *ring) 4785 { 4786 hns3_free_desc(ring); 4787 devm_kfree(ring_to_dev(ring), ring->desc_cb); 4788 ring->desc_cb = NULL; 4789 ring->next_to_clean = 0; 4790 ring->next_to_use = 0; 4791 ring->last_to_use = 0; 4792 ring->pending_buf = 0; 4793 if (!HNAE3_IS_TX_RING(ring) && ring->skb) { 4794 dev_kfree_skb_any(ring->skb); 4795 ring->skb = NULL; 4796 } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) { 4797 struct hns3_tx_spare *tx_spare = ring->tx_spare; 4798 4799 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len, 4800 DMA_TO_DEVICE); 4801 free_pages((unsigned long)tx_spare->buf, 4802 get_order(tx_spare->len)); 4803 devm_kfree(ring_to_dev(ring), tx_spare); 4804 ring->tx_spare = NULL; 4805 } 4806 4807 if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) { 4808 page_pool_destroy(ring->page_pool); 4809 ring->page_pool = NULL; 4810 } 4811 } 4812 4813 static int hns3_buf_size2type(u32 buf_size) 4814 { 4815 int bd_size_type; 4816 4817 switch (buf_size) { 4818 case 512: 4819 bd_size_type = HNS3_BD_SIZE_512_TYPE; 4820 break; 4821 case 1024: 4822 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 4823 break; 4824 case 2048: 4825 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 4826 break; 4827 case 4096: 4828 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 4829 break; 4830 default: 4831 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 4832 } 4833 4834 return bd_size_type; 4835 } 4836 4837 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 4838 { 4839 dma_addr_t dma = ring->desc_dma_addr; 4840 struct hnae3_queue *q = ring->tqp; 4841 4842 if (!HNAE3_IS_TX_RING(ring)) { 4843 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma); 4844 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 4845 (u32)((dma >> 31) >> 1)); 4846 4847 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 4848 hns3_buf_size2type(ring->buf_size)); 4849 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 4850 ring->desc_num / 8 - 1); 4851 } else { 4852 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 4853 (u32)dma); 4854 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 4855 (u32)((dma >> 31) >> 1)); 4856 4857 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 4858 ring->desc_num / 8 - 1); 4859 } 4860 } 4861 4862 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 4863 { 4864 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 4865 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 4866 int i; 4867 4868 for (i = 0; i < HNAE3_MAX_TC; i++) { 4869 int j; 4870 4871 if (!test_bit(i, &tc_info->tc_en)) 4872 continue; 4873 4874 for (j = 0; j < tc_info->tqp_count[i]; j++) { 4875 struct hnae3_queue *q; 4876 4877 q = priv->ring[tc_info->tqp_offset[i] + j].tqp; 4878 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i); 4879 } 4880 } 4881 } 4882 4883 int hns3_init_all_ring(struct hns3_nic_priv *priv) 4884 { 4885 struct hnae3_handle *h = priv->ae_handle; 4886 int ring_num = h->kinfo.num_tqps * 2; 4887 int i, j; 4888 int ret; 4889 4890 for (i = 0; i < ring_num; i++) { 4891 ret = hns3_alloc_ring_memory(&priv->ring[i]); 4892 if (ret) { 4893 dev_err(priv->dev, 4894 "Alloc ring memory fail! ret=%d\n", ret); 4895 goto out_when_alloc_ring_memory; 4896 } 4897 4898 u64_stats_init(&priv->ring[i].syncp); 4899 } 4900 4901 return 0; 4902 4903 out_when_alloc_ring_memory: 4904 for (j = i - 1; j >= 0; j--) 4905 hns3_fini_ring(&priv->ring[j]); 4906 4907 return -ENOMEM; 4908 } 4909 4910 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv) 4911 { 4912 struct hnae3_handle *h = priv->ae_handle; 4913 int i; 4914 4915 for (i = 0; i < h->kinfo.num_tqps; i++) { 4916 hns3_fini_ring(&priv->ring[i]); 4917 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]); 4918 } 4919 } 4920 4921 /* Set mac addr if it is configured. or leave it to the AE driver */ 4922 static int hns3_init_mac_addr(struct net_device *netdev) 4923 { 4924 struct hns3_nic_priv *priv = netdev_priv(netdev); 4925 struct hnae3_handle *h = priv->ae_handle; 4926 u8 mac_addr_temp[ETH_ALEN]; 4927 int ret = 0; 4928 4929 if (h->ae_algo->ops->get_mac_addr) 4930 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 4931 4932 /* Check if the MAC address is valid, if not get a random one */ 4933 if (!is_valid_ether_addr(mac_addr_temp)) { 4934 eth_hw_addr_random(netdev); 4935 dev_warn(priv->dev, "using random MAC address %pM\n", 4936 netdev->dev_addr); 4937 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) { 4938 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 4939 ether_addr_copy(netdev->perm_addr, mac_addr_temp); 4940 } else { 4941 return 0; 4942 } 4943 4944 if (h->ae_algo->ops->set_mac_addr) 4945 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 4946 4947 return ret; 4948 } 4949 4950 static int hns3_init_phy(struct net_device *netdev) 4951 { 4952 struct hnae3_handle *h = hns3_get_handle(netdev); 4953 int ret = 0; 4954 4955 if (h->ae_algo->ops->mac_connect_phy) 4956 ret = h->ae_algo->ops->mac_connect_phy(h); 4957 4958 return ret; 4959 } 4960 4961 static void hns3_uninit_phy(struct net_device *netdev) 4962 { 4963 struct hnae3_handle *h = hns3_get_handle(netdev); 4964 4965 if (h->ae_algo->ops->mac_disconnect_phy) 4966 h->ae_algo->ops->mac_disconnect_phy(h); 4967 } 4968 4969 static int hns3_client_start(struct hnae3_handle *handle) 4970 { 4971 if (!handle->ae_algo->ops->client_start) 4972 return 0; 4973 4974 return handle->ae_algo->ops->client_start(handle); 4975 } 4976 4977 static void hns3_client_stop(struct hnae3_handle *handle) 4978 { 4979 if (!handle->ae_algo->ops->client_stop) 4980 return; 4981 4982 handle->ae_algo->ops->client_stop(handle); 4983 } 4984 4985 static void hns3_info_show(struct hns3_nic_priv *priv) 4986 { 4987 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 4988 4989 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr); 4990 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps); 4991 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size); 4992 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size); 4993 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len); 4994 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc); 4995 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc); 4996 dev_info(priv->dev, "Total number of enabled TCs: %u\n", 4997 kinfo->tc_info.num_tc); 4998 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu); 4999 } 5000 5001 static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv, 5002 enum dim_cq_period_mode mode, bool is_tx) 5003 { 5004 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev); 5005 struct hnae3_handle *handle = priv->ae_handle; 5006 int i; 5007 5008 if (is_tx) { 5009 priv->tx_cqe_mode = mode; 5010 5011 for (i = 0; i < priv->vector_num; i++) 5012 priv->tqp_vector[i].tx_group.dim.mode = mode; 5013 } else { 5014 priv->rx_cqe_mode = mode; 5015 5016 for (i = 0; i < priv->vector_num; i++) 5017 priv->tqp_vector[i].rx_group.dim.mode = mode; 5018 } 5019 5020 /* only device version above V3(include V3), GL can switch CQ/EQ 5021 * period mode. 5022 */ 5023 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) { 5024 u32 new_mode; 5025 u64 reg; 5026 5027 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ? 5028 HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE; 5029 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG; 5030 5031 writel(new_mode, handle->kinfo.io_base + reg); 5032 } 5033 } 5034 5035 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv, 5036 enum dim_cq_period_mode tx_mode, 5037 enum dim_cq_period_mode rx_mode) 5038 { 5039 hns3_set_cq_period_mode(priv, tx_mode, true); 5040 hns3_set_cq_period_mode(priv, rx_mode, false); 5041 } 5042 5043 static void hns3_state_init(struct hnae3_handle *handle) 5044 { 5045 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 5046 struct net_device *netdev = handle->kinfo.netdev; 5047 struct hns3_nic_priv *priv = netdev_priv(netdev); 5048 5049 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 5050 5051 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5052 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags); 5053 5054 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) 5055 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state); 5056 5057 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev)) 5058 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state); 5059 } 5060 5061 static int hns3_client_init(struct hnae3_handle *handle) 5062 { 5063 struct pci_dev *pdev = handle->pdev; 5064 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 5065 u16 alloc_tqps, max_rss_size; 5066 struct hns3_nic_priv *priv; 5067 struct net_device *netdev; 5068 int ret; 5069 5070 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 5071 &max_rss_size); 5072 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 5073 if (!netdev) 5074 return -ENOMEM; 5075 5076 priv = netdev_priv(netdev); 5077 priv->dev = &pdev->dev; 5078 priv->netdev = netdev; 5079 priv->ae_handle = handle; 5080 priv->tx_timeout_count = 0; 5081 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num; 5082 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 5083 5084 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL); 5085 5086 handle->kinfo.netdev = netdev; 5087 handle->priv = (void *)priv; 5088 5089 hns3_init_mac_addr(netdev); 5090 5091 hns3_set_default_feature(netdev); 5092 5093 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 5094 netdev->priv_flags |= IFF_UNICAST_FLT; 5095 netdev->netdev_ops = &hns3_nic_netdev_ops; 5096 SET_NETDEV_DEV(netdev, &pdev->dev); 5097 hns3_ethtool_set_ops(netdev); 5098 5099 /* Carrier off reporting is important to ethtool even BEFORE open */ 5100 netif_carrier_off(netdev); 5101 5102 ret = hns3_get_ring_config(priv); 5103 if (ret) { 5104 ret = -ENOMEM; 5105 goto out_get_ring_cfg; 5106 } 5107 5108 hns3_nic_init_coal_cfg(priv); 5109 5110 ret = hns3_nic_alloc_vector_data(priv); 5111 if (ret) { 5112 ret = -ENOMEM; 5113 goto out_alloc_vector_data; 5114 } 5115 5116 ret = hns3_nic_init_vector_data(priv); 5117 if (ret) { 5118 ret = -ENOMEM; 5119 goto out_init_vector_data; 5120 } 5121 5122 ret = hns3_init_all_ring(priv); 5123 if (ret) { 5124 ret = -ENOMEM; 5125 goto out_init_ring; 5126 } 5127 5128 hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE, 5129 DIM_CQ_PERIOD_MODE_START_FROM_EQE); 5130 5131 ret = hns3_init_phy(netdev); 5132 if (ret) 5133 goto out_init_phy; 5134 5135 /* the device can work without cpu rmap, only aRFS needs it */ 5136 ret = hns3_set_rx_cpu_rmap(netdev); 5137 if (ret) 5138 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 5139 5140 ret = hns3_nic_init_irq(priv); 5141 if (ret) { 5142 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 5143 hns3_free_rx_cpu_rmap(netdev); 5144 goto out_init_irq_fail; 5145 } 5146 5147 ret = hns3_client_start(handle); 5148 if (ret) { 5149 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 5150 goto out_client_start; 5151 } 5152 5153 hns3_dcbnl_setup(handle); 5154 5155 ret = hns3_dbg_init(handle); 5156 if (ret) { 5157 dev_err(priv->dev, "failed to init debugfs, ret = %d\n", 5158 ret); 5159 goto out_client_start; 5160 } 5161 5162 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size); 5163 5164 hns3_state_init(handle); 5165 5166 ret = register_netdev(netdev); 5167 if (ret) { 5168 dev_err(priv->dev, "probe register netdev fail!\n"); 5169 goto out_reg_netdev_fail; 5170 } 5171 5172 if (netif_msg_drv(handle)) 5173 hns3_info_show(priv); 5174 5175 return ret; 5176 5177 out_reg_netdev_fail: 5178 hns3_dbg_uninit(handle); 5179 out_client_start: 5180 hns3_free_rx_cpu_rmap(netdev); 5181 hns3_nic_uninit_irq(priv); 5182 out_init_irq_fail: 5183 hns3_uninit_phy(netdev); 5184 out_init_phy: 5185 hns3_uninit_all_ring(priv); 5186 out_init_ring: 5187 hns3_nic_uninit_vector_data(priv); 5188 out_init_vector_data: 5189 hns3_nic_dealloc_vector_data(priv); 5190 out_alloc_vector_data: 5191 priv->ring = NULL; 5192 out_get_ring_cfg: 5193 priv->ae_handle = NULL; 5194 free_netdev(netdev); 5195 return ret; 5196 } 5197 5198 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 5199 { 5200 struct net_device *netdev = handle->kinfo.netdev; 5201 struct hns3_nic_priv *priv = netdev_priv(netdev); 5202 5203 if (netdev->reg_state != NETREG_UNINITIALIZED) 5204 unregister_netdev(netdev); 5205 5206 hns3_client_stop(handle); 5207 5208 hns3_uninit_phy(netdev); 5209 5210 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 5211 netdev_warn(netdev, "already uninitialized\n"); 5212 goto out_netdev_free; 5213 } 5214 5215 hns3_free_rx_cpu_rmap(netdev); 5216 5217 hns3_nic_uninit_irq(priv); 5218 5219 hns3_clear_all_ring(handle, true); 5220 5221 hns3_nic_uninit_vector_data(priv); 5222 5223 hns3_nic_dealloc_vector_data(priv); 5224 5225 hns3_uninit_all_ring(priv); 5226 5227 hns3_put_ring_config(priv); 5228 5229 out_netdev_free: 5230 hns3_dbg_uninit(handle); 5231 free_netdev(netdev); 5232 } 5233 5234 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 5235 { 5236 struct net_device *netdev = handle->kinfo.netdev; 5237 5238 if (!netdev) 5239 return; 5240 5241 if (linkup) { 5242 netif_tx_wake_all_queues(netdev); 5243 netif_carrier_on(netdev); 5244 if (netif_msg_link(handle)) 5245 netdev_info(netdev, "link up\n"); 5246 } else { 5247 netif_carrier_off(netdev); 5248 netif_tx_stop_all_queues(netdev); 5249 if (netif_msg_link(handle)) 5250 netdev_info(netdev, "link down\n"); 5251 } 5252 } 5253 5254 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 5255 { 5256 while (ring->next_to_clean != ring->next_to_use) { 5257 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 5258 hns3_free_buffer_detach(ring, ring->next_to_clean, 0); 5259 ring_ptr_move_fw(ring, next_to_clean); 5260 } 5261 5262 ring->pending_buf = 0; 5263 } 5264 5265 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 5266 { 5267 struct hns3_desc_cb res_cbs; 5268 int ret; 5269 5270 while (ring->next_to_use != ring->next_to_clean) { 5271 /* When a buffer is not reused, it's memory has been 5272 * freed in hns3_handle_rx_bd or will be freed by 5273 * stack, so we need to replace the buffer here. 5274 */ 5275 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 5276 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 5277 if (ret) { 5278 u64_stats_update_begin(&ring->syncp); 5279 ring->stats.sw_err_cnt++; 5280 u64_stats_update_end(&ring->syncp); 5281 /* if alloc new buffer fail, exit directly 5282 * and reclear in up flow. 5283 */ 5284 netdev_warn(ring_to_netdev(ring), 5285 "reserve buffer map failed, ret = %d\n", 5286 ret); 5287 return ret; 5288 } 5289 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 5290 } 5291 ring_ptr_move_fw(ring, next_to_use); 5292 } 5293 5294 /* Free the pending skb in rx ring */ 5295 if (ring->skb) { 5296 dev_kfree_skb_any(ring->skb); 5297 ring->skb = NULL; 5298 ring->pending_buf = 0; 5299 } 5300 5301 return 0; 5302 } 5303 5304 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 5305 { 5306 while (ring->next_to_use != ring->next_to_clean) { 5307 /* When a buffer is not reused, it's memory has been 5308 * freed in hns3_handle_rx_bd or will be freed by 5309 * stack, so only need to unmap the buffer here. 5310 */ 5311 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 5312 hns3_unmap_buffer(ring, 5313 &ring->desc_cb[ring->next_to_use]); 5314 ring->desc_cb[ring->next_to_use].dma = 0; 5315 } 5316 5317 ring_ptr_move_fw(ring, next_to_use); 5318 } 5319 } 5320 5321 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force) 5322 { 5323 struct net_device *ndev = h->kinfo.netdev; 5324 struct hns3_nic_priv *priv = netdev_priv(ndev); 5325 u32 i; 5326 5327 for (i = 0; i < h->kinfo.num_tqps; i++) { 5328 struct hns3_enet_ring *ring; 5329 5330 ring = &priv->ring[i]; 5331 hns3_clear_tx_ring(ring); 5332 5333 ring = &priv->ring[i + h->kinfo.num_tqps]; 5334 /* Continue to clear other rings even if clearing some 5335 * rings failed. 5336 */ 5337 if (force) 5338 hns3_force_clear_rx_ring(ring); 5339 else 5340 hns3_clear_rx_ring(ring); 5341 } 5342 } 5343 5344 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 5345 { 5346 struct net_device *ndev = h->kinfo.netdev; 5347 struct hns3_nic_priv *priv = netdev_priv(ndev); 5348 struct hns3_enet_ring *rx_ring; 5349 int i, j; 5350 int ret; 5351 5352 ret = h->ae_algo->ops->reset_queue(h); 5353 if (ret) 5354 return ret; 5355 5356 for (i = 0; i < h->kinfo.num_tqps; i++) { 5357 hns3_init_ring_hw(&priv->ring[i]); 5358 5359 /* We need to clear tx ring here because self test will 5360 * use the ring and will not run down before up 5361 */ 5362 hns3_clear_tx_ring(&priv->ring[i]); 5363 priv->ring[i].next_to_clean = 0; 5364 priv->ring[i].next_to_use = 0; 5365 priv->ring[i].last_to_use = 0; 5366 5367 rx_ring = &priv->ring[i + h->kinfo.num_tqps]; 5368 hns3_init_ring_hw(rx_ring); 5369 ret = hns3_clear_rx_ring(rx_ring); 5370 if (ret) 5371 return ret; 5372 5373 /* We can not know the hardware head and tail when this 5374 * function is called in reset flow, so we reuse all desc. 5375 */ 5376 for (j = 0; j < rx_ring->desc_num; j++) 5377 hns3_reuse_buffer(rx_ring, j); 5378 5379 rx_ring->next_to_clean = 0; 5380 rx_ring->next_to_use = 0; 5381 } 5382 5383 hns3_init_tx_ring_tc(priv); 5384 5385 return 0; 5386 } 5387 5388 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 5389 { 5390 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 5391 struct net_device *ndev = kinfo->netdev; 5392 struct hns3_nic_priv *priv = netdev_priv(ndev); 5393 5394 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 5395 return 0; 5396 5397 if (!netif_running(ndev)) 5398 return 0; 5399 5400 return hns3_nic_net_stop(ndev); 5401 } 5402 5403 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 5404 { 5405 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 5406 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 5407 int ret = 0; 5408 5409 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 5410 netdev_err(kinfo->netdev, "device is not initialized yet\n"); 5411 return -EFAULT; 5412 } 5413 5414 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 5415 5416 if (netif_running(kinfo->netdev)) { 5417 ret = hns3_nic_net_open(kinfo->netdev); 5418 if (ret) { 5419 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 5420 netdev_err(kinfo->netdev, 5421 "net up fail, ret=%d!\n", ret); 5422 return ret; 5423 } 5424 } 5425 5426 return ret; 5427 } 5428 5429 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 5430 { 5431 struct net_device *netdev = handle->kinfo.netdev; 5432 struct hns3_nic_priv *priv = netdev_priv(netdev); 5433 int ret; 5434 5435 /* Carrier off reporting is important to ethtool even BEFORE open */ 5436 netif_carrier_off(netdev); 5437 5438 ret = hns3_get_ring_config(priv); 5439 if (ret) 5440 return ret; 5441 5442 ret = hns3_nic_alloc_vector_data(priv); 5443 if (ret) 5444 goto err_put_ring; 5445 5446 ret = hns3_nic_init_vector_data(priv); 5447 if (ret) 5448 goto err_dealloc_vector; 5449 5450 ret = hns3_init_all_ring(priv); 5451 if (ret) 5452 goto err_uninit_vector; 5453 5454 hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode); 5455 5456 /* the device can work without cpu rmap, only aRFS needs it */ 5457 ret = hns3_set_rx_cpu_rmap(netdev); 5458 if (ret) 5459 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 5460 5461 ret = hns3_nic_init_irq(priv); 5462 if (ret) { 5463 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 5464 hns3_free_rx_cpu_rmap(netdev); 5465 goto err_init_irq_fail; 5466 } 5467 5468 if (!hns3_is_phys_func(handle->pdev)) 5469 hns3_init_mac_addr(netdev); 5470 5471 ret = hns3_client_start(handle); 5472 if (ret) { 5473 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 5474 goto err_client_start_fail; 5475 } 5476 5477 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 5478 5479 return ret; 5480 5481 err_client_start_fail: 5482 hns3_free_rx_cpu_rmap(netdev); 5483 hns3_nic_uninit_irq(priv); 5484 err_init_irq_fail: 5485 hns3_uninit_all_ring(priv); 5486 err_uninit_vector: 5487 hns3_nic_uninit_vector_data(priv); 5488 err_dealloc_vector: 5489 hns3_nic_dealloc_vector_data(priv); 5490 err_put_ring: 5491 hns3_put_ring_config(priv); 5492 5493 return ret; 5494 } 5495 5496 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 5497 { 5498 struct net_device *netdev = handle->kinfo.netdev; 5499 struct hns3_nic_priv *priv = netdev_priv(netdev); 5500 5501 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 5502 netdev_warn(netdev, "already uninitialized\n"); 5503 return 0; 5504 } 5505 5506 hns3_free_rx_cpu_rmap(netdev); 5507 hns3_nic_uninit_irq(priv); 5508 hns3_clear_all_ring(handle, true); 5509 hns3_reset_tx_queue(priv->ae_handle); 5510 5511 hns3_nic_uninit_vector_data(priv); 5512 5513 hns3_nic_dealloc_vector_data(priv); 5514 5515 hns3_uninit_all_ring(priv); 5516 5517 hns3_put_ring_config(priv); 5518 5519 return 0; 5520 } 5521 5522 static int hns3_reset_notify(struct hnae3_handle *handle, 5523 enum hnae3_reset_notify_type type) 5524 { 5525 int ret = 0; 5526 5527 switch (type) { 5528 case HNAE3_UP_CLIENT: 5529 ret = hns3_reset_notify_up_enet(handle); 5530 break; 5531 case HNAE3_DOWN_CLIENT: 5532 ret = hns3_reset_notify_down_enet(handle); 5533 break; 5534 case HNAE3_INIT_CLIENT: 5535 ret = hns3_reset_notify_init_enet(handle); 5536 break; 5537 case HNAE3_UNINIT_CLIENT: 5538 ret = hns3_reset_notify_uninit_enet(handle); 5539 break; 5540 default: 5541 break; 5542 } 5543 5544 return ret; 5545 } 5546 5547 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num, 5548 bool rxfh_configured) 5549 { 5550 int ret; 5551 5552 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num, 5553 rxfh_configured); 5554 if (ret) { 5555 dev_err(&handle->pdev->dev, 5556 "Change tqp num(%u) fail.\n", new_tqp_num); 5557 return ret; 5558 } 5559 5560 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT); 5561 if (ret) 5562 return ret; 5563 5564 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT); 5565 if (ret) 5566 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT); 5567 5568 return ret; 5569 } 5570 5571 int hns3_set_channels(struct net_device *netdev, 5572 struct ethtool_channels *ch) 5573 { 5574 struct hnae3_handle *h = hns3_get_handle(netdev); 5575 struct hnae3_knic_private_info *kinfo = &h->kinfo; 5576 bool rxfh_configured = netif_is_rxfh_configured(netdev); 5577 u32 new_tqp_num = ch->combined_count; 5578 u16 org_tqp_num; 5579 int ret; 5580 5581 if (hns3_nic_resetting(netdev)) 5582 return -EBUSY; 5583 5584 if (ch->rx_count || ch->tx_count) 5585 return -EINVAL; 5586 5587 if (kinfo->tc_info.mqprio_active) { 5588 dev_err(&netdev->dev, 5589 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n"); 5590 return -EINVAL; 5591 } 5592 5593 if (new_tqp_num > hns3_get_max_available_channels(h) || 5594 new_tqp_num < 1) { 5595 dev_err(&netdev->dev, 5596 "Change tqps fail, the tqp range is from 1 to %u", 5597 hns3_get_max_available_channels(h)); 5598 return -EINVAL; 5599 } 5600 5601 if (kinfo->rss_size == new_tqp_num) 5602 return 0; 5603 5604 netif_dbg(h, drv, netdev, 5605 "set channels: tqp_num=%u, rxfh=%d\n", 5606 new_tqp_num, rxfh_configured); 5607 5608 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 5609 if (ret) 5610 return ret; 5611 5612 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 5613 if (ret) 5614 return ret; 5615 5616 org_tqp_num = h->kinfo.num_tqps; 5617 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured); 5618 if (ret) { 5619 int ret1; 5620 5621 netdev_warn(netdev, 5622 "Change channels fail, revert to old value\n"); 5623 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured); 5624 if (ret1) { 5625 netdev_err(netdev, 5626 "revert to old channel fail\n"); 5627 return ret1; 5628 } 5629 5630 return ret; 5631 } 5632 5633 return 0; 5634 } 5635 5636 static const struct hns3_hw_error_info hns3_hw_err[] = { 5637 { .type = HNAE3_PPU_POISON_ERROR, 5638 .msg = "PPU poison" }, 5639 { .type = HNAE3_CMDQ_ECC_ERROR, 5640 .msg = "IMP CMDQ error" }, 5641 { .type = HNAE3_IMP_RD_POISON_ERROR, 5642 .msg = "IMP RD poison" }, 5643 { .type = HNAE3_ROCEE_AXI_RESP_ERROR, 5644 .msg = "ROCEE AXI RESP error" }, 5645 }; 5646 5647 static void hns3_process_hw_error(struct hnae3_handle *handle, 5648 enum hnae3_hw_error_type type) 5649 { 5650 int i; 5651 5652 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) { 5653 if (hns3_hw_err[i].type == type) { 5654 dev_err(&handle->pdev->dev, "Detected %s!\n", 5655 hns3_hw_err[i].msg); 5656 break; 5657 } 5658 } 5659 } 5660 5661 static const struct hnae3_client_ops client_ops = { 5662 .init_instance = hns3_client_init, 5663 .uninit_instance = hns3_client_uninit, 5664 .link_status_change = hns3_link_status_change, 5665 .reset_notify = hns3_reset_notify, 5666 .process_hw_error = hns3_process_hw_error, 5667 }; 5668 5669 /* hns3_init_module - Driver registration routine 5670 * hns3_init_module is the first routine called when the driver is 5671 * loaded. All it does is register with the PCI subsystem. 5672 */ 5673 static int __init hns3_init_module(void) 5674 { 5675 int ret; 5676 5677 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 5678 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 5679 5680 client.type = HNAE3_CLIENT_KNIC; 5681 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s", 5682 hns3_driver_name); 5683 5684 client.ops = &client_ops; 5685 5686 INIT_LIST_HEAD(&client.node); 5687 5688 hns3_dbg_register_debugfs(hns3_driver_name); 5689 5690 ret = hnae3_register_client(&client); 5691 if (ret) 5692 goto err_reg_client; 5693 5694 ret = pci_register_driver(&hns3_driver); 5695 if (ret) 5696 goto err_reg_driver; 5697 5698 return ret; 5699 5700 err_reg_driver: 5701 hnae3_unregister_client(&client); 5702 err_reg_client: 5703 hns3_dbg_unregister_debugfs(); 5704 return ret; 5705 } 5706 module_init(hns3_init_module); 5707 5708 /* hns3_exit_module - Driver exit cleanup routine 5709 * hns3_exit_module is called just before the driver is removed 5710 * from memory. 5711 */ 5712 static void __exit hns3_exit_module(void) 5713 { 5714 pci_unregister_driver(&hns3_driver); 5715 hnae3_unregister_client(&client); 5716 hns3_dbg_unregister_debugfs(); 5717 } 5718 module_exit(hns3_exit_module); 5719 5720 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 5721 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 5722 MODULE_LICENSE("GPL"); 5723 MODULE_ALIAS("pci:hns-nic"); 5724