1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #include <linux/if_vlan.h> 8 #include <linux/ip.h> 9 #include <linux/ipv6.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/skbuff.h> 13 #include <linux/sctp.h> 14 #include <linux/vermagic.h> 15 #include <net/gre.h> 16 #include <net/pkt_cls.h> 17 #include <net/vxlan.h> 18 19 #include "hnae3.h" 20 #include "hns3_enet.h" 21 22 static void hns3_clear_all_ring(struct hnae3_handle *h); 23 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h); 24 25 static const char hns3_driver_name[] = "hns3"; 26 const char hns3_driver_version[] = VERMAGIC_STRING; 27 static const char hns3_driver_string[] = 28 "Hisilicon Ethernet Network Driver for Hip08 Family"; 29 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 30 static struct hnae3_client client; 31 32 /* hns3_pci_tbl - PCI Device ID Table 33 * 34 * Last entry must be all 0s 35 * 36 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 37 * Class, Class Mask, private data (not used) } 38 */ 39 static const struct pci_device_id hns3_pci_tbl[] = { 40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 43 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 45 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 47 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 49 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 51 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 52 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0}, 54 /* required last entry */ 55 {0, } 56 }; 57 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 58 59 static irqreturn_t hns3_irq_handle(int irq, void *vector) 60 { 61 struct hns3_enet_tqp_vector *tqp_vector = vector; 62 63 napi_schedule(&tqp_vector->napi); 64 65 return IRQ_HANDLED; 66 } 67 68 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 69 { 70 struct hns3_enet_tqp_vector *tqp_vectors; 71 unsigned int i; 72 73 for (i = 0; i < priv->vector_num; i++) { 74 tqp_vectors = &priv->tqp_vector[i]; 75 76 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 77 continue; 78 79 /* release the irq resource */ 80 free_irq(tqp_vectors->vector_irq, tqp_vectors); 81 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 82 } 83 } 84 85 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 86 { 87 struct hns3_enet_tqp_vector *tqp_vectors; 88 int txrx_int_idx = 0; 89 int rx_int_idx = 0; 90 int tx_int_idx = 0; 91 unsigned int i; 92 int ret; 93 94 for (i = 0; i < priv->vector_num; i++) { 95 tqp_vectors = &priv->tqp_vector[i]; 96 97 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 98 continue; 99 100 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 101 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 102 "%s-%s-%d", priv->netdev->name, "TxRx", 103 txrx_int_idx++); 104 txrx_int_idx++; 105 } else if (tqp_vectors->rx_group.ring) { 106 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 107 "%s-%s-%d", priv->netdev->name, "Rx", 108 rx_int_idx++); 109 } else if (tqp_vectors->tx_group.ring) { 110 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 111 "%s-%s-%d", priv->netdev->name, "Tx", 112 tx_int_idx++); 113 } else { 114 /* Skip this unused q_vector */ 115 continue; 116 } 117 118 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 119 120 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 121 tqp_vectors->name, 122 tqp_vectors); 123 if (ret) { 124 netdev_err(priv->netdev, "request irq(%d) fail\n", 125 tqp_vectors->vector_irq); 126 return ret; 127 } 128 129 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 130 } 131 132 return 0; 133 } 134 135 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 136 u32 mask_en) 137 { 138 writel(mask_en, tqp_vector->mask_addr); 139 } 140 141 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 142 { 143 napi_enable(&tqp_vector->napi); 144 145 /* enable vector */ 146 hns3_mask_vector_irq(tqp_vector, 1); 147 } 148 149 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 150 { 151 /* disable vector */ 152 hns3_mask_vector_irq(tqp_vector, 0); 153 154 disable_irq(tqp_vector->vector_irq); 155 napi_disable(&tqp_vector->napi); 156 } 157 158 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 159 u32 rl_value) 160 { 161 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 162 163 /* this defines the configuration for RL (Interrupt Rate Limiter). 164 * Rl defines rate of interrupts i.e. number of interrupts-per-second 165 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 166 */ 167 168 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable && 169 !tqp_vector->rx_group.coal.gl_adapt_enable) 170 /* According to the hardware, the range of rl_reg is 171 * 0-59 and the unit is 4. 172 */ 173 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 174 175 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 176 } 177 178 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 179 u32 gl_value) 180 { 181 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value); 182 183 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 184 } 185 186 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 187 u32 gl_value) 188 { 189 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value); 190 191 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 192 } 193 194 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector, 195 struct hns3_nic_priv *priv) 196 { 197 struct hnae3_handle *h = priv->ae_handle; 198 199 /* initialize the configuration for interrupt coalescing. 200 * 1. GL (Interrupt Gap Limiter) 201 * 2. RL (Interrupt Rate Limiter) 202 */ 203 204 /* Default: enable interrupt coalescing self-adaptive and GL */ 205 tqp_vector->tx_group.coal.gl_adapt_enable = 1; 206 tqp_vector->rx_group.coal.gl_adapt_enable = 1; 207 208 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K; 209 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K; 210 211 /* Default: disable RL */ 212 h->kinfo.int_rl_setting = 0; 213 214 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START; 215 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW; 216 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW; 217 } 218 219 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 220 struct hns3_nic_priv *priv) 221 { 222 struct hnae3_handle *h = priv->ae_handle; 223 224 hns3_set_vector_coalesce_tx_gl(tqp_vector, 225 tqp_vector->tx_group.coal.int_gl); 226 hns3_set_vector_coalesce_rx_gl(tqp_vector, 227 tqp_vector->rx_group.coal.int_gl); 228 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 229 } 230 231 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 232 { 233 struct hnae3_handle *h = hns3_get_handle(netdev); 234 struct hnae3_knic_private_info *kinfo = &h->kinfo; 235 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc; 236 int i, ret; 237 238 if (kinfo->num_tc <= 1) { 239 netdev_reset_tc(netdev); 240 } else { 241 ret = netdev_set_num_tc(netdev, kinfo->num_tc); 242 if (ret) { 243 netdev_err(netdev, 244 "netdev_set_num_tc fail, ret=%d!\n", ret); 245 return ret; 246 } 247 248 for (i = 0; i < HNAE3_MAX_TC; i++) { 249 if (!kinfo->tc_info[i].enable) 250 continue; 251 252 netdev_set_tc_queue(netdev, 253 kinfo->tc_info[i].tc, 254 kinfo->tc_info[i].tqp_count, 255 kinfo->tc_info[i].tqp_offset); 256 } 257 } 258 259 ret = netif_set_real_num_tx_queues(netdev, queue_size); 260 if (ret) { 261 netdev_err(netdev, 262 "netif_set_real_num_tx_queues fail, ret=%d!\n", 263 ret); 264 return ret; 265 } 266 267 ret = netif_set_real_num_rx_queues(netdev, queue_size); 268 if (ret) { 269 netdev_err(netdev, 270 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 271 return ret; 272 } 273 274 return 0; 275 } 276 277 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 278 { 279 u16 free_tqps, max_rss_size, max_tqps; 280 281 h->ae_algo->ops->get_tqps_and_rss_info(h, &free_tqps, &max_rss_size); 282 max_tqps = h->kinfo.num_tc * max_rss_size; 283 284 return min_t(u16, max_tqps, (free_tqps + h->kinfo.num_tqps)); 285 } 286 287 static int hns3_nic_net_up(struct net_device *netdev) 288 { 289 struct hns3_nic_priv *priv = netdev_priv(netdev); 290 struct hnae3_handle *h = priv->ae_handle; 291 int i, j; 292 int ret; 293 294 ret = hns3_nic_reset_all_ring(h); 295 if (ret) 296 return ret; 297 298 /* get irq resource for all vectors */ 299 ret = hns3_nic_init_irq(priv); 300 if (ret) { 301 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret); 302 return ret; 303 } 304 305 /* enable the vectors */ 306 for (i = 0; i < priv->vector_num; i++) 307 hns3_vector_enable(&priv->tqp_vector[i]); 308 309 /* start the ae_dev */ 310 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 311 if (ret) 312 goto out_start_err; 313 314 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 315 316 return 0; 317 318 out_start_err: 319 for (j = i - 1; j >= 0; j--) 320 hns3_vector_disable(&priv->tqp_vector[j]); 321 322 hns3_nic_uninit_irq(priv); 323 324 return ret; 325 } 326 327 static int hns3_nic_net_open(struct net_device *netdev) 328 { 329 struct hns3_nic_priv *priv = netdev_priv(netdev); 330 struct hnae3_handle *h = hns3_get_handle(netdev); 331 struct hnae3_knic_private_info *kinfo; 332 int i, ret; 333 334 netif_carrier_off(netdev); 335 336 ret = hns3_nic_set_real_num_queue(netdev); 337 if (ret) 338 return ret; 339 340 ret = hns3_nic_net_up(netdev); 341 if (ret) { 342 netdev_err(netdev, 343 "hns net up fail, ret=%d!\n", ret); 344 return ret; 345 } 346 347 kinfo = &h->kinfo; 348 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { 349 netdev_set_prio_tc_map(netdev, i, 350 kinfo->prio_tc[i]); 351 } 352 353 priv->ae_handle->last_reset_time = jiffies; 354 return 0; 355 } 356 357 static void hns3_nic_net_down(struct net_device *netdev) 358 { 359 struct hns3_nic_priv *priv = netdev_priv(netdev); 360 const struct hnae3_ae_ops *ops; 361 int i; 362 363 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 364 return; 365 366 /* disable vectors */ 367 for (i = 0; i < priv->vector_num; i++) 368 hns3_vector_disable(&priv->tqp_vector[i]); 369 370 /* stop ae_dev */ 371 ops = priv->ae_handle->ae_algo->ops; 372 if (ops->stop) 373 ops->stop(priv->ae_handle); 374 375 /* free irq resources */ 376 hns3_nic_uninit_irq(priv); 377 378 hns3_clear_all_ring(priv->ae_handle); 379 } 380 381 static int hns3_nic_net_stop(struct net_device *netdev) 382 { 383 netif_tx_stop_all_queues(netdev); 384 netif_carrier_off(netdev); 385 386 hns3_nic_net_down(netdev); 387 388 return 0; 389 } 390 391 static int hns3_nic_uc_sync(struct net_device *netdev, 392 const unsigned char *addr) 393 { 394 struct hnae3_handle *h = hns3_get_handle(netdev); 395 396 if (h->ae_algo->ops->add_uc_addr) 397 return h->ae_algo->ops->add_uc_addr(h, addr); 398 399 return 0; 400 } 401 402 static int hns3_nic_uc_unsync(struct net_device *netdev, 403 const unsigned char *addr) 404 { 405 struct hnae3_handle *h = hns3_get_handle(netdev); 406 407 if (h->ae_algo->ops->rm_uc_addr) 408 return h->ae_algo->ops->rm_uc_addr(h, addr); 409 410 return 0; 411 } 412 413 static int hns3_nic_mc_sync(struct net_device *netdev, 414 const unsigned char *addr) 415 { 416 struct hnae3_handle *h = hns3_get_handle(netdev); 417 418 if (h->ae_algo->ops->add_mc_addr) 419 return h->ae_algo->ops->add_mc_addr(h, addr); 420 421 return 0; 422 } 423 424 static int hns3_nic_mc_unsync(struct net_device *netdev, 425 const unsigned char *addr) 426 { 427 struct hnae3_handle *h = hns3_get_handle(netdev); 428 429 if (h->ae_algo->ops->rm_mc_addr) 430 return h->ae_algo->ops->rm_mc_addr(h, addr); 431 432 return 0; 433 } 434 435 static void hns3_nic_set_rx_mode(struct net_device *netdev) 436 { 437 struct hnae3_handle *h = hns3_get_handle(netdev); 438 439 if (h->ae_algo->ops->set_promisc_mode) { 440 if (netdev->flags & IFF_PROMISC) 441 h->ae_algo->ops->set_promisc_mode(h, true, true); 442 else if (netdev->flags & IFF_ALLMULTI) 443 h->ae_algo->ops->set_promisc_mode(h, false, true); 444 else 445 h->ae_algo->ops->set_promisc_mode(h, false, false); 446 } 447 if (__dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync)) 448 netdev_err(netdev, "sync uc address fail\n"); 449 if (netdev->flags & IFF_MULTICAST) { 450 if (__dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync)) 451 netdev_err(netdev, "sync mc address fail\n"); 452 453 if (h->ae_algo->ops->update_mta_status) 454 h->ae_algo->ops->update_mta_status(h); 455 } 456 } 457 458 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen, 459 u16 *mss, u32 *type_cs_vlan_tso) 460 { 461 u32 l4_offset, hdr_len; 462 union l3_hdr_info l3; 463 union l4_hdr_info l4; 464 u32 l4_paylen; 465 int ret; 466 467 if (!skb_is_gso(skb)) 468 return 0; 469 470 ret = skb_cow_head(skb, 0); 471 if (ret) 472 return ret; 473 474 l3.hdr = skb_network_header(skb); 475 l4.hdr = skb_transport_header(skb); 476 477 /* Software should clear the IPv4's checksum field when tso is 478 * needed. 479 */ 480 if (l3.v4->version == 4) 481 l3.v4->check = 0; 482 483 /* tunnel packet.*/ 484 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 485 SKB_GSO_GRE_CSUM | 486 SKB_GSO_UDP_TUNNEL | 487 SKB_GSO_UDP_TUNNEL_CSUM)) { 488 if ((!(skb_shinfo(skb)->gso_type & 489 SKB_GSO_PARTIAL)) && 490 (skb_shinfo(skb)->gso_type & 491 SKB_GSO_UDP_TUNNEL_CSUM)) { 492 /* Software should clear the udp's checksum 493 * field when tso is needed. 494 */ 495 l4.udp->check = 0; 496 } 497 /* reset l3&l4 pointers from outer to inner headers */ 498 l3.hdr = skb_inner_network_header(skb); 499 l4.hdr = skb_inner_transport_header(skb); 500 501 /* Software should clear the IPv4's checksum field when 502 * tso is needed. 503 */ 504 if (l3.v4->version == 4) 505 l3.v4->check = 0; 506 } 507 508 /* normal or tunnel packet*/ 509 l4_offset = l4.hdr - skb->data; 510 hdr_len = (l4.tcp->doff * 4) + l4_offset; 511 512 /* remove payload length from inner pseudo checksum when tso*/ 513 l4_paylen = skb->len - l4_offset; 514 csum_replace_by_diff(&l4.tcp->check, 515 (__force __wsum)htonl(l4_paylen)); 516 517 /* find the txbd field values */ 518 *paylen = skb->len - hdr_len; 519 hnae3_set_bit(*type_cs_vlan_tso, 520 HNS3_TXD_TSO_B, 1); 521 522 /* get MSS for TSO */ 523 *mss = skb_shinfo(skb)->gso_size; 524 525 return 0; 526 } 527 528 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 529 u8 *il4_proto) 530 { 531 union { 532 struct iphdr *v4; 533 struct ipv6hdr *v6; 534 unsigned char *hdr; 535 } l3; 536 unsigned char *l4_hdr; 537 unsigned char *exthdr; 538 u8 l4_proto_tmp; 539 __be16 frag_off; 540 541 /* find outer header point */ 542 l3.hdr = skb_network_header(skb); 543 l4_hdr = skb_transport_header(skb); 544 545 if (skb->protocol == htons(ETH_P_IPV6)) { 546 exthdr = l3.hdr + sizeof(*l3.v6); 547 l4_proto_tmp = l3.v6->nexthdr; 548 if (l4_hdr != exthdr) 549 ipv6_skip_exthdr(skb, exthdr - skb->data, 550 &l4_proto_tmp, &frag_off); 551 } else if (skb->protocol == htons(ETH_P_IP)) { 552 l4_proto_tmp = l3.v4->protocol; 553 } else { 554 return -EINVAL; 555 } 556 557 *ol4_proto = l4_proto_tmp; 558 559 /* tunnel packet */ 560 if (!skb->encapsulation) { 561 *il4_proto = 0; 562 return 0; 563 } 564 565 /* find inner header point */ 566 l3.hdr = skb_inner_network_header(skb); 567 l4_hdr = skb_inner_transport_header(skb); 568 569 if (l3.v6->version == 6) { 570 exthdr = l3.hdr + sizeof(*l3.v6); 571 l4_proto_tmp = l3.v6->nexthdr; 572 if (l4_hdr != exthdr) 573 ipv6_skip_exthdr(skb, exthdr - skb->data, 574 &l4_proto_tmp, &frag_off); 575 } else if (l3.v4->version == 4) { 576 l4_proto_tmp = l3.v4->protocol; 577 } 578 579 *il4_proto = l4_proto_tmp; 580 581 return 0; 582 } 583 584 static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto, 585 u8 il4_proto, u32 *type_cs_vlan_tso, 586 u32 *ol_type_vlan_len_msec) 587 { 588 union { 589 struct iphdr *v4; 590 struct ipv6hdr *v6; 591 unsigned char *hdr; 592 } l3; 593 union { 594 struct tcphdr *tcp; 595 struct udphdr *udp; 596 struct gre_base_hdr *gre; 597 unsigned char *hdr; 598 } l4; 599 unsigned char *l2_hdr; 600 u8 l4_proto = ol4_proto; 601 u32 ol2_len; 602 u32 ol3_len; 603 u32 ol4_len; 604 u32 l2_len; 605 u32 l3_len; 606 607 l3.hdr = skb_network_header(skb); 608 l4.hdr = skb_transport_header(skb); 609 610 /* compute L2 header size for normal packet, defined in 2 Bytes */ 611 l2_len = l3.hdr - skb->data; 612 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M, 613 HNS3_TXD_L2LEN_S, l2_len >> 1); 614 615 /* tunnel packet*/ 616 if (skb->encapsulation) { 617 /* compute OL2 header size, defined in 2 Bytes */ 618 ol2_len = l2_len; 619 hnae3_set_field(*ol_type_vlan_len_msec, 620 HNS3_TXD_L2LEN_M, 621 HNS3_TXD_L2LEN_S, ol2_len >> 1); 622 623 /* compute OL3 header size, defined in 4 Bytes */ 624 ol3_len = l4.hdr - l3.hdr; 625 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M, 626 HNS3_TXD_L3LEN_S, ol3_len >> 2); 627 628 /* MAC in UDP, MAC in GRE (0x6558)*/ 629 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) { 630 /* switch MAC header ptr from outer to inner header.*/ 631 l2_hdr = skb_inner_mac_header(skb); 632 633 /* compute OL4 header size, defined in 4 Bytes. */ 634 ol4_len = l2_hdr - l4.hdr; 635 hnae3_set_field(*ol_type_vlan_len_msec, 636 HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S, 637 ol4_len >> 2); 638 639 /* switch IP header ptr from outer to inner header */ 640 l3.hdr = skb_inner_network_header(skb); 641 642 /* compute inner l2 header size, defined in 2 Bytes. */ 643 l2_len = l3.hdr - l2_hdr; 644 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M, 645 HNS3_TXD_L2LEN_S, l2_len >> 1); 646 } else { 647 /* skb packet types not supported by hardware, 648 * txbd len fild doesn't be filled. 649 */ 650 return; 651 } 652 653 /* switch L4 header pointer from outer to inner */ 654 l4.hdr = skb_inner_transport_header(skb); 655 656 l4_proto = il4_proto; 657 } 658 659 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 660 l3_len = l4.hdr - l3.hdr; 661 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M, 662 HNS3_TXD_L3LEN_S, l3_len >> 2); 663 664 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 665 switch (l4_proto) { 666 case IPPROTO_TCP: 667 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 668 HNS3_TXD_L4LEN_S, l4.tcp->doff); 669 break; 670 case IPPROTO_SCTP: 671 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 672 HNS3_TXD_L4LEN_S, 673 (sizeof(struct sctphdr) >> 2)); 674 break; 675 case IPPROTO_UDP: 676 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M, 677 HNS3_TXD_L4LEN_S, 678 (sizeof(struct udphdr) >> 2)); 679 break; 680 default: 681 /* skb packet types not supported by hardware, 682 * txbd len fild doesn't be filled. 683 */ 684 return; 685 } 686 } 687 688 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 689 * and it is udp packet, which has a dest port as the IANA assigned. 690 * the hardware is expected to do the checksum offload, but the 691 * hardware will not do the checksum offload when udp dest port is 692 * 4789. 693 */ 694 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 695 { 696 #define IANA_VXLAN_PORT 4789 697 union { 698 struct tcphdr *tcp; 699 struct udphdr *udp; 700 struct gre_base_hdr *gre; 701 unsigned char *hdr; 702 } l4; 703 704 l4.hdr = skb_transport_header(skb); 705 706 if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT))) 707 return false; 708 709 skb_checksum_help(skb); 710 711 return true; 712 } 713 714 static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto, 715 u8 il4_proto, u32 *type_cs_vlan_tso, 716 u32 *ol_type_vlan_len_msec) 717 { 718 union { 719 struct iphdr *v4; 720 struct ipv6hdr *v6; 721 unsigned char *hdr; 722 } l3; 723 u32 l4_proto = ol4_proto; 724 725 l3.hdr = skb_network_header(skb); 726 727 /* define OL3 type and tunnel type(OL4).*/ 728 if (skb->encapsulation) { 729 /* define outer network header type.*/ 730 if (skb->protocol == htons(ETH_P_IP)) { 731 if (skb_is_gso(skb)) 732 hnae3_set_field(*ol_type_vlan_len_msec, 733 HNS3_TXD_OL3T_M, 734 HNS3_TXD_OL3T_S, 735 HNS3_OL3T_IPV4_CSUM); 736 else 737 hnae3_set_field(*ol_type_vlan_len_msec, 738 HNS3_TXD_OL3T_M, 739 HNS3_TXD_OL3T_S, 740 HNS3_OL3T_IPV4_NO_CSUM); 741 742 } else if (skb->protocol == htons(ETH_P_IPV6)) { 743 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M, 744 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6); 745 } 746 747 /* define tunnel type(OL4).*/ 748 switch (l4_proto) { 749 case IPPROTO_UDP: 750 hnae3_set_field(*ol_type_vlan_len_msec, 751 HNS3_TXD_TUNTYPE_M, 752 HNS3_TXD_TUNTYPE_S, 753 HNS3_TUN_MAC_IN_UDP); 754 break; 755 case IPPROTO_GRE: 756 hnae3_set_field(*ol_type_vlan_len_msec, 757 HNS3_TXD_TUNTYPE_M, 758 HNS3_TXD_TUNTYPE_S, 759 HNS3_TUN_NVGRE); 760 break; 761 default: 762 /* drop the skb tunnel packet if hardware don't support, 763 * because hardware can't calculate csum when TSO. 764 */ 765 if (skb_is_gso(skb)) 766 return -EDOM; 767 768 /* the stack computes the IP header already, 769 * driver calculate l4 checksum when not TSO. 770 */ 771 skb_checksum_help(skb); 772 return 0; 773 } 774 775 l3.hdr = skb_inner_network_header(skb); 776 l4_proto = il4_proto; 777 } 778 779 if (l3.v4->version == 4) { 780 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M, 781 HNS3_TXD_L3T_S, HNS3_L3T_IPV4); 782 783 /* the stack computes the IP header already, the only time we 784 * need the hardware to recompute it is in the case of TSO. 785 */ 786 if (skb_is_gso(skb)) 787 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 788 } else if (l3.v6->version == 6) { 789 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M, 790 HNS3_TXD_L3T_S, HNS3_L3T_IPV6); 791 } 792 793 switch (l4_proto) { 794 case IPPROTO_TCP: 795 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 796 hnae3_set_field(*type_cs_vlan_tso, 797 HNS3_TXD_L4T_M, 798 HNS3_TXD_L4T_S, 799 HNS3_L4T_TCP); 800 break; 801 case IPPROTO_UDP: 802 if (hns3_tunnel_csum_bug(skb)) 803 break; 804 805 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 806 hnae3_set_field(*type_cs_vlan_tso, 807 HNS3_TXD_L4T_M, 808 HNS3_TXD_L4T_S, 809 HNS3_L4T_UDP); 810 break; 811 case IPPROTO_SCTP: 812 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 813 hnae3_set_field(*type_cs_vlan_tso, 814 HNS3_TXD_L4T_M, 815 HNS3_TXD_L4T_S, 816 HNS3_L4T_SCTP); 817 break; 818 default: 819 /* drop the skb tunnel packet if hardware don't support, 820 * because hardware can't calculate csum when TSO. 821 */ 822 if (skb_is_gso(skb)) 823 return -EDOM; 824 825 /* the stack computes the IP header already, 826 * driver calculate l4 checksum when not TSO. 827 */ 828 skb_checksum_help(skb); 829 return 0; 830 } 831 832 return 0; 833 } 834 835 static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end) 836 { 837 /* Config bd buffer end */ 838 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M, 839 HNS3_TXD_BDTYPE_S, 0); 840 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end); 841 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1); 842 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0); 843 } 844 845 static int hns3_fill_desc_vtags(struct sk_buff *skb, 846 struct hns3_enet_ring *tx_ring, 847 u32 *inner_vlan_flag, 848 u32 *out_vlan_flag, 849 u16 *inner_vtag, 850 u16 *out_vtag) 851 { 852 #define HNS3_TX_VLAN_PRIO_SHIFT 13 853 854 if (skb->protocol == htons(ETH_P_8021Q) && 855 !(tx_ring->tqp->handle->kinfo.netdev->features & 856 NETIF_F_HW_VLAN_CTAG_TX)) { 857 /* When HW VLAN acceleration is turned off, and the stack 858 * sets the protocol to 802.1q, the driver just need to 859 * set the protocol to the encapsulated ethertype. 860 */ 861 skb->protocol = vlan_get_protocol(skb); 862 return 0; 863 } 864 865 if (skb_vlan_tag_present(skb)) { 866 u16 vlan_tag; 867 868 vlan_tag = skb_vlan_tag_get(skb); 869 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT; 870 871 /* Based on hw strategy, use out_vtag in two layer tag case, 872 * and use inner_vtag in one tag case. 873 */ 874 if (skb->protocol == htons(ETH_P_8021Q)) { 875 hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1); 876 *out_vtag = vlan_tag; 877 } else { 878 hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1); 879 *inner_vtag = vlan_tag; 880 } 881 } else if (skb->protocol == htons(ETH_P_8021Q)) { 882 struct vlan_ethhdr *vhdr; 883 int rc; 884 885 rc = skb_cow_head(skb, 0); 886 if (rc < 0) 887 return rc; 888 vhdr = (struct vlan_ethhdr *)skb->data; 889 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7) 890 << HNS3_TX_VLAN_PRIO_SHIFT); 891 } 892 893 skb->protocol = vlan_get_protocol(skb); 894 return 0; 895 } 896 897 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 898 int size, dma_addr_t dma, int frag_end, 899 enum hns_desc_type type) 900 { 901 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 902 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 903 u32 ol_type_vlan_len_msec = 0; 904 u16 bdtp_fe_sc_vld_ra_ri = 0; 905 u32 type_cs_vlan_tso = 0; 906 struct sk_buff *skb; 907 u16 inner_vtag = 0; 908 u16 out_vtag = 0; 909 u32 paylen = 0; 910 u16 mss = 0; 911 u8 ol4_proto; 912 u8 il4_proto; 913 int ret; 914 915 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */ 916 desc_cb->priv = priv; 917 desc_cb->length = size; 918 desc_cb->dma = dma; 919 desc_cb->type = type; 920 921 /* now, fill the descriptor */ 922 desc->addr = cpu_to_le64(dma); 923 desc->tx.send_size = cpu_to_le16((u16)size); 924 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, frag_end); 925 desc->tx.bdtp_fe_sc_vld_ra_ri = cpu_to_le16(bdtp_fe_sc_vld_ra_ri); 926 927 if (type == DESC_TYPE_SKB) { 928 skb = (struct sk_buff *)priv; 929 paylen = skb->len; 930 931 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso, 932 &ol_type_vlan_len_msec, 933 &inner_vtag, &out_vtag); 934 if (unlikely(ret)) 935 return ret; 936 937 if (skb->ip_summed == CHECKSUM_PARTIAL) { 938 skb_reset_mac_len(skb); 939 940 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 941 if (ret) 942 return ret; 943 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto, 944 &type_cs_vlan_tso, 945 &ol_type_vlan_len_msec); 946 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto, 947 &type_cs_vlan_tso, 948 &ol_type_vlan_len_msec); 949 if (ret) 950 return ret; 951 952 ret = hns3_set_tso(skb, &paylen, &mss, 953 &type_cs_vlan_tso); 954 if (ret) 955 return ret; 956 } 957 958 /* Set txbd */ 959 desc->tx.ol_type_vlan_len_msec = 960 cpu_to_le32(ol_type_vlan_len_msec); 961 desc->tx.type_cs_vlan_tso_len = 962 cpu_to_le32(type_cs_vlan_tso); 963 desc->tx.paylen = cpu_to_le32(paylen); 964 desc->tx.mss = cpu_to_le16(mss); 965 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 966 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 967 } 968 969 /* move ring pointer to next.*/ 970 ring_ptr_move_fw(ring, next_to_use); 971 972 return 0; 973 } 974 975 static int hns3_fill_desc_tso(struct hns3_enet_ring *ring, void *priv, 976 int size, dma_addr_t dma, int frag_end, 977 enum hns_desc_type type) 978 { 979 unsigned int frag_buf_num; 980 unsigned int k; 981 int sizeoflast; 982 int ret; 983 984 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 985 sizeoflast = size % HNS3_MAX_BD_SIZE; 986 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 987 988 /* When the frag size is bigger than hardware, split this frag */ 989 for (k = 0; k < frag_buf_num; k++) { 990 ret = hns3_fill_desc(ring, priv, 991 (k == frag_buf_num - 1) ? 992 sizeoflast : HNS3_MAX_BD_SIZE, 993 dma + HNS3_MAX_BD_SIZE * k, 994 frag_end && (k == frag_buf_num - 1) ? 1 : 0, 995 (type == DESC_TYPE_SKB && !k) ? 996 DESC_TYPE_SKB : DESC_TYPE_PAGE); 997 if (ret) 998 return ret; 999 } 1000 1001 return 0; 1002 } 1003 1004 static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum, 1005 struct hns3_enet_ring *ring) 1006 { 1007 struct sk_buff *skb = *out_skb; 1008 struct skb_frag_struct *frag; 1009 int bdnum_for_frag; 1010 int frag_num; 1011 int buf_num; 1012 int size; 1013 int i; 1014 1015 size = skb_headlen(skb); 1016 buf_num = (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1017 1018 frag_num = skb_shinfo(skb)->nr_frags; 1019 for (i = 0; i < frag_num; i++) { 1020 frag = &skb_shinfo(skb)->frags[i]; 1021 size = skb_frag_size(frag); 1022 bdnum_for_frag = 1023 (size + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1024 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG) 1025 return -ENOMEM; 1026 1027 buf_num += bdnum_for_frag; 1028 } 1029 1030 if (buf_num > ring_space(ring)) 1031 return -EBUSY; 1032 1033 *bnum = buf_num; 1034 return 0; 1035 } 1036 1037 static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum, 1038 struct hns3_enet_ring *ring) 1039 { 1040 struct sk_buff *skb = *out_skb; 1041 int buf_num; 1042 1043 /* No. of segments (plus a header) */ 1044 buf_num = skb_shinfo(skb)->nr_frags + 1; 1045 1046 if (buf_num > ring_space(ring)) 1047 return -EBUSY; 1048 1049 *bnum = buf_num; 1050 1051 return 0; 1052 } 1053 1054 static void hns_nic_dma_unmap(struct hns3_enet_ring *ring, int next_to_use_orig) 1055 { 1056 struct device *dev = ring_to_dev(ring); 1057 unsigned int i; 1058 1059 for (i = 0; i < ring->desc_num; i++) { 1060 /* check if this is where we started */ 1061 if (ring->next_to_use == next_to_use_orig) 1062 break; 1063 1064 /* unmap the descriptor dma address */ 1065 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB) 1066 dma_unmap_single(dev, 1067 ring->desc_cb[ring->next_to_use].dma, 1068 ring->desc_cb[ring->next_to_use].length, 1069 DMA_TO_DEVICE); 1070 else 1071 dma_unmap_page(dev, 1072 ring->desc_cb[ring->next_to_use].dma, 1073 ring->desc_cb[ring->next_to_use].length, 1074 DMA_TO_DEVICE); 1075 1076 /* rollback one */ 1077 ring_ptr_move_bw(ring, next_to_use); 1078 } 1079 } 1080 1081 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1082 { 1083 struct hns3_nic_priv *priv = netdev_priv(netdev); 1084 struct hns3_nic_ring_data *ring_data = 1085 &tx_ring_data(priv, skb->queue_mapping); 1086 struct hns3_enet_ring *ring = ring_data->ring; 1087 struct device *dev = priv->dev; 1088 struct netdev_queue *dev_queue; 1089 struct skb_frag_struct *frag; 1090 int next_to_use_head; 1091 int next_to_use_frag; 1092 dma_addr_t dma; 1093 int buf_num; 1094 int seg_num; 1095 int size; 1096 int ret; 1097 int i; 1098 1099 /* Prefetch the data used later */ 1100 prefetch(skb->data); 1101 1102 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) { 1103 case -EBUSY: 1104 u64_stats_update_begin(&ring->syncp); 1105 ring->stats.tx_busy++; 1106 u64_stats_update_end(&ring->syncp); 1107 1108 goto out_net_tx_busy; 1109 case -ENOMEM: 1110 u64_stats_update_begin(&ring->syncp); 1111 ring->stats.sw_err_cnt++; 1112 u64_stats_update_end(&ring->syncp); 1113 netdev_err(netdev, "no memory to xmit!\n"); 1114 1115 goto out_err_tx_ok; 1116 default: 1117 break; 1118 } 1119 1120 /* No. of segments (plus a header) */ 1121 seg_num = skb_shinfo(skb)->nr_frags + 1; 1122 /* Fill the first part */ 1123 size = skb_headlen(skb); 1124 1125 next_to_use_head = ring->next_to_use; 1126 1127 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1128 if (dma_mapping_error(dev, dma)) { 1129 netdev_err(netdev, "TX head DMA map failed\n"); 1130 ring->stats.sw_err_cnt++; 1131 goto out_err_tx_ok; 1132 } 1133 1134 ret = priv->ops.fill_desc(ring, skb, size, dma, seg_num == 1 ? 1 : 0, 1135 DESC_TYPE_SKB); 1136 if (ret) 1137 goto head_dma_map_err; 1138 1139 next_to_use_frag = ring->next_to_use; 1140 /* Fill the fragments */ 1141 for (i = 1; i < seg_num; i++) { 1142 frag = &skb_shinfo(skb)->frags[i - 1]; 1143 size = skb_frag_size(frag); 1144 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1145 if (dma_mapping_error(dev, dma)) { 1146 netdev_err(netdev, "TX frag(%d) DMA map failed\n", i); 1147 ring->stats.sw_err_cnt++; 1148 goto frag_dma_map_err; 1149 } 1150 ret = priv->ops.fill_desc(ring, skb_frag_page(frag), size, dma, 1151 seg_num - 1 == i ? 1 : 0, 1152 DESC_TYPE_PAGE); 1153 1154 if (ret) 1155 goto frag_dma_map_err; 1156 } 1157 1158 /* Complete translate all packets */ 1159 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index); 1160 netdev_tx_sent_queue(dev_queue, skb->len); 1161 1162 wmb(); /* Commit all data before submit */ 1163 1164 hnae3_queue_xmit(ring->tqp, buf_num); 1165 1166 return NETDEV_TX_OK; 1167 1168 frag_dma_map_err: 1169 hns_nic_dma_unmap(ring, next_to_use_frag); 1170 1171 head_dma_map_err: 1172 hns_nic_dma_unmap(ring, next_to_use_head); 1173 1174 out_err_tx_ok: 1175 dev_kfree_skb_any(skb); 1176 return NETDEV_TX_OK; 1177 1178 out_net_tx_busy: 1179 netif_stop_subqueue(netdev, ring_data->queue_index); 1180 smp_mb(); /* Commit all data before submit */ 1181 1182 return NETDEV_TX_BUSY; 1183 } 1184 1185 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1186 { 1187 struct hnae3_handle *h = hns3_get_handle(netdev); 1188 struct sockaddr *mac_addr = p; 1189 int ret; 1190 1191 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1192 return -EADDRNOTAVAIL; 1193 1194 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1195 netdev_info(netdev, "already using mac address %pM\n", 1196 mac_addr->sa_data); 1197 return 0; 1198 } 1199 1200 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1201 if (ret) { 1202 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1203 return ret; 1204 } 1205 1206 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1207 1208 return 0; 1209 } 1210 1211 static int hns3_nic_set_features(struct net_device *netdev, 1212 netdev_features_t features) 1213 { 1214 netdev_features_t changed = netdev->features ^ features; 1215 struct hns3_nic_priv *priv = netdev_priv(netdev); 1216 struct hnae3_handle *h = priv->ae_handle; 1217 int ret; 1218 1219 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) { 1220 if (features & (NETIF_F_TSO | NETIF_F_TSO6)) { 1221 priv->ops.fill_desc = hns3_fill_desc_tso; 1222 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 1223 } else { 1224 priv->ops.fill_desc = hns3_fill_desc; 1225 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 1226 } 1227 } 1228 1229 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 1230 h->ae_algo->ops->enable_vlan_filter) { 1231 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1232 h->ae_algo->ops->enable_vlan_filter(h, true); 1233 else 1234 h->ae_algo->ops->enable_vlan_filter(h, false); 1235 } 1236 1237 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1238 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1239 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1240 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, true); 1241 else 1242 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, false); 1243 1244 if (ret) 1245 return ret; 1246 } 1247 1248 netdev->features = features; 1249 return 0; 1250 } 1251 1252 static void hns3_nic_get_stats64(struct net_device *netdev, 1253 struct rtnl_link_stats64 *stats) 1254 { 1255 struct hns3_nic_priv *priv = netdev_priv(netdev); 1256 int queue_num = priv->ae_handle->kinfo.num_tqps; 1257 struct hnae3_handle *handle = priv->ae_handle; 1258 struct hns3_enet_ring *ring; 1259 unsigned int start; 1260 unsigned int idx; 1261 u64 tx_bytes = 0; 1262 u64 rx_bytes = 0; 1263 u64 tx_pkts = 0; 1264 u64 rx_pkts = 0; 1265 u64 tx_drop = 0; 1266 u64 rx_drop = 0; 1267 1268 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1269 return; 1270 1271 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1272 1273 for (idx = 0; idx < queue_num; idx++) { 1274 /* fetch the tx stats */ 1275 ring = priv->ring_data[idx].ring; 1276 do { 1277 start = u64_stats_fetch_begin_irq(&ring->syncp); 1278 tx_bytes += ring->stats.tx_bytes; 1279 tx_pkts += ring->stats.tx_pkts; 1280 tx_drop += ring->stats.tx_busy; 1281 tx_drop += ring->stats.sw_err_cnt; 1282 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1283 1284 /* fetch the rx stats */ 1285 ring = priv->ring_data[idx + queue_num].ring; 1286 do { 1287 start = u64_stats_fetch_begin_irq(&ring->syncp); 1288 rx_bytes += ring->stats.rx_bytes; 1289 rx_pkts += ring->stats.rx_pkts; 1290 rx_drop += ring->stats.non_vld_descs; 1291 rx_drop += ring->stats.err_pkt_len; 1292 rx_drop += ring->stats.l2_err; 1293 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1294 } 1295 1296 stats->tx_bytes = tx_bytes; 1297 stats->tx_packets = tx_pkts; 1298 stats->rx_bytes = rx_bytes; 1299 stats->rx_packets = rx_pkts; 1300 1301 stats->rx_errors = netdev->stats.rx_errors; 1302 stats->multicast = netdev->stats.multicast; 1303 stats->rx_length_errors = netdev->stats.rx_length_errors; 1304 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 1305 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1306 1307 stats->tx_errors = netdev->stats.tx_errors; 1308 stats->rx_dropped = rx_drop + netdev->stats.rx_dropped; 1309 stats->tx_dropped = tx_drop + netdev->stats.tx_dropped; 1310 stats->collisions = netdev->stats.collisions; 1311 stats->rx_over_errors = netdev->stats.rx_over_errors; 1312 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1313 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1314 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1315 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1316 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1317 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1318 stats->tx_window_errors = netdev->stats.tx_window_errors; 1319 stats->rx_compressed = netdev->stats.rx_compressed; 1320 stats->tx_compressed = netdev->stats.tx_compressed; 1321 } 1322 1323 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1324 { 1325 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1326 struct hnae3_handle *h = hns3_get_handle(netdev); 1327 struct hnae3_knic_private_info *kinfo = &h->kinfo; 1328 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map; 1329 u8 tc = mqprio_qopt->qopt.num_tc; 1330 u16 mode = mqprio_qopt->mode; 1331 u8 hw = mqprio_qopt->qopt.hw; 1332 bool if_running; 1333 int ret; 1334 1335 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1336 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1337 return -EOPNOTSUPP; 1338 1339 if (tc > HNAE3_MAX_TC) 1340 return -EINVAL; 1341 1342 if (!netdev) 1343 return -EINVAL; 1344 1345 if_running = netif_running(netdev); 1346 if (if_running) { 1347 hns3_nic_net_stop(netdev); 1348 msleep(100); 1349 } 1350 1351 ret = (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1352 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP; 1353 if (ret) 1354 goto out; 1355 1356 ret = hns3_nic_set_real_num_queue(netdev); 1357 1358 out: 1359 if (if_running) 1360 hns3_nic_net_open(netdev); 1361 1362 return ret; 1363 } 1364 1365 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1366 void *type_data) 1367 { 1368 if (type != TC_SETUP_QDISC_MQPRIO) 1369 return -EOPNOTSUPP; 1370 1371 return hns3_setup_tc(dev, type_data); 1372 } 1373 1374 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1375 __be16 proto, u16 vid) 1376 { 1377 struct hnae3_handle *h = hns3_get_handle(netdev); 1378 struct hns3_nic_priv *priv = netdev_priv(netdev); 1379 int ret = -EIO; 1380 1381 if (h->ae_algo->ops->set_vlan_filter) 1382 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1383 1384 if (!ret) 1385 set_bit(vid, priv->active_vlans); 1386 1387 return ret; 1388 } 1389 1390 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1391 __be16 proto, u16 vid) 1392 { 1393 struct hnae3_handle *h = hns3_get_handle(netdev); 1394 struct hns3_nic_priv *priv = netdev_priv(netdev); 1395 int ret = -EIO; 1396 1397 if (h->ae_algo->ops->set_vlan_filter) 1398 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1399 1400 if (!ret) 1401 clear_bit(vid, priv->active_vlans); 1402 1403 return ret; 1404 } 1405 1406 static void hns3_restore_vlan(struct net_device *netdev) 1407 { 1408 struct hns3_nic_priv *priv = netdev_priv(netdev); 1409 u16 vid; 1410 int ret; 1411 1412 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 1413 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 1414 if (ret) 1415 netdev_warn(netdev, "Restore vlan: %d filter, ret:%d\n", 1416 vid, ret); 1417 } 1418 } 1419 1420 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1421 u8 qos, __be16 vlan_proto) 1422 { 1423 struct hnae3_handle *h = hns3_get_handle(netdev); 1424 int ret = -EIO; 1425 1426 if (h->ae_algo->ops->set_vf_vlan_filter) 1427 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1428 qos, vlan_proto); 1429 1430 return ret; 1431 } 1432 1433 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1434 { 1435 struct hnae3_handle *h = hns3_get_handle(netdev); 1436 bool if_running = netif_running(netdev); 1437 int ret; 1438 1439 if (!h->ae_algo->ops->set_mtu) 1440 return -EOPNOTSUPP; 1441 1442 /* if this was called with netdev up then bring netdevice down */ 1443 if (if_running) { 1444 (void)hns3_nic_net_stop(netdev); 1445 msleep(100); 1446 } 1447 1448 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 1449 if (ret) { 1450 netdev_err(netdev, "failed to change MTU in hardware %d\n", 1451 ret); 1452 return ret; 1453 } 1454 1455 netdev->mtu = new_mtu; 1456 1457 /* if the netdev was running earlier, bring it up again */ 1458 if (if_running && hns3_nic_net_open(netdev)) 1459 ret = -EINVAL; 1460 1461 return ret; 1462 } 1463 1464 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 1465 { 1466 struct hns3_nic_priv *priv = netdev_priv(ndev); 1467 struct hns3_enet_ring *tx_ring = NULL; 1468 int timeout_queue = 0; 1469 int hw_head, hw_tail; 1470 int i; 1471 1472 /* Find the stopped queue the same way the stack does */ 1473 for (i = 0; i < ndev->real_num_tx_queues; i++) { 1474 struct netdev_queue *q; 1475 unsigned long trans_start; 1476 1477 q = netdev_get_tx_queue(ndev, i); 1478 trans_start = q->trans_start; 1479 if (netif_xmit_stopped(q) && 1480 time_after(jiffies, 1481 (trans_start + ndev->watchdog_timeo))) { 1482 timeout_queue = i; 1483 break; 1484 } 1485 } 1486 1487 if (i == ndev->num_tx_queues) { 1488 netdev_info(ndev, 1489 "no netdev TX timeout queue found, timeout count: %llu\n", 1490 priv->tx_timeout_count); 1491 return false; 1492 } 1493 1494 tx_ring = priv->ring_data[timeout_queue].ring; 1495 1496 hw_head = readl_relaxed(tx_ring->tqp->io_base + 1497 HNS3_RING_TX_RING_HEAD_REG); 1498 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 1499 HNS3_RING_TX_RING_TAIL_REG); 1500 netdev_info(ndev, 1501 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n", 1502 priv->tx_timeout_count, 1503 timeout_queue, 1504 tx_ring->next_to_use, 1505 tx_ring->next_to_clean, 1506 hw_head, 1507 hw_tail, 1508 readl(tx_ring->tqp_vector->mask_addr)); 1509 1510 return true; 1511 } 1512 1513 static void hns3_nic_net_timeout(struct net_device *ndev) 1514 { 1515 struct hns3_nic_priv *priv = netdev_priv(ndev); 1516 struct hnae3_handle *h = priv->ae_handle; 1517 1518 if (!hns3_get_tx_timeo_queue_info(ndev)) 1519 return; 1520 1521 priv->tx_timeout_count++; 1522 1523 if (time_before(jiffies, (h->last_reset_time + ndev->watchdog_timeo))) 1524 return; 1525 1526 /* request the reset */ 1527 if (h->ae_algo->ops->reset_event) 1528 h->ae_algo->ops->reset_event(h); 1529 } 1530 1531 static const struct net_device_ops hns3_nic_netdev_ops = { 1532 .ndo_open = hns3_nic_net_open, 1533 .ndo_stop = hns3_nic_net_stop, 1534 .ndo_start_xmit = hns3_nic_net_xmit, 1535 .ndo_tx_timeout = hns3_nic_net_timeout, 1536 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 1537 .ndo_change_mtu = hns3_nic_change_mtu, 1538 .ndo_set_features = hns3_nic_set_features, 1539 .ndo_get_stats64 = hns3_nic_get_stats64, 1540 .ndo_setup_tc = hns3_nic_setup_tc, 1541 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 1542 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 1543 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 1544 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 1545 }; 1546 1547 static bool hns3_is_phys_func(struct pci_dev *pdev) 1548 { 1549 u32 dev_id = pdev->device; 1550 1551 switch (dev_id) { 1552 case HNAE3_DEV_ID_GE: 1553 case HNAE3_DEV_ID_25GE: 1554 case HNAE3_DEV_ID_25GE_RDMA: 1555 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 1556 case HNAE3_DEV_ID_50GE_RDMA: 1557 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 1558 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 1559 return true; 1560 case HNAE3_DEV_ID_100G_VF: 1561 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF: 1562 return false; 1563 default: 1564 dev_warn(&pdev->dev, "un-recognized pci device-id %d", 1565 dev_id); 1566 } 1567 1568 return false; 1569 } 1570 1571 static void hns3_disable_sriov(struct pci_dev *pdev) 1572 { 1573 /* If our VFs are assigned we cannot shut down SR-IOV 1574 * without causing issues, so just leave the hardware 1575 * available but disabled 1576 */ 1577 if (pci_vfs_assigned(pdev)) { 1578 dev_warn(&pdev->dev, 1579 "disabling driver while VFs are assigned\n"); 1580 return; 1581 } 1582 1583 pci_disable_sriov(pdev); 1584 } 1585 1586 /* hns3_probe - Device initialization routine 1587 * @pdev: PCI device information struct 1588 * @ent: entry in hns3_pci_tbl 1589 * 1590 * hns3_probe initializes a PF identified by a pci_dev structure. 1591 * The OS initialization, configuring of the PF private structure, 1592 * and a hardware reset occur. 1593 * 1594 * Returns 0 on success, negative on failure 1595 */ 1596 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1597 { 1598 struct hnae3_ae_dev *ae_dev; 1599 int ret; 1600 1601 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), 1602 GFP_KERNEL); 1603 if (!ae_dev) { 1604 ret = -ENOMEM; 1605 return ret; 1606 } 1607 1608 ae_dev->pdev = pdev; 1609 ae_dev->flag = ent->driver_data; 1610 ae_dev->dev_type = HNAE3_DEV_KNIC; 1611 pci_set_drvdata(pdev, ae_dev); 1612 1613 hnae3_register_ae_dev(ae_dev); 1614 1615 return 0; 1616 } 1617 1618 /* hns3_remove - Device removal routine 1619 * @pdev: PCI device information struct 1620 */ 1621 static void hns3_remove(struct pci_dev *pdev) 1622 { 1623 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1624 1625 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 1626 hns3_disable_sriov(pdev); 1627 1628 hnae3_unregister_ae_dev(ae_dev); 1629 } 1630 1631 /** 1632 * hns3_pci_sriov_configure 1633 * @pdev: pointer to a pci_dev structure 1634 * @num_vfs: number of VFs to allocate 1635 * 1636 * Enable or change the number of VFs. Called when the user updates the number 1637 * of VFs in sysfs. 1638 **/ 1639 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 1640 { 1641 int ret; 1642 1643 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 1644 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 1645 return -EINVAL; 1646 } 1647 1648 if (num_vfs) { 1649 ret = pci_enable_sriov(pdev, num_vfs); 1650 if (ret) 1651 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 1652 else 1653 return num_vfs; 1654 } else if (!pci_vfs_assigned(pdev)) { 1655 pci_disable_sriov(pdev); 1656 } else { 1657 dev_warn(&pdev->dev, 1658 "Unable to free VFs because some are assigned to VMs.\n"); 1659 } 1660 1661 return 0; 1662 } 1663 1664 static struct pci_driver hns3_driver = { 1665 .name = hns3_driver_name, 1666 .id_table = hns3_pci_tbl, 1667 .probe = hns3_probe, 1668 .remove = hns3_remove, 1669 .sriov_configure = hns3_pci_sriov_configure, 1670 }; 1671 1672 /* set default feature to hns3 */ 1673 static void hns3_set_default_feature(struct net_device *netdev) 1674 { 1675 netdev->priv_flags |= IFF_UNICAST_FLT; 1676 1677 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1678 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1679 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1680 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1681 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1682 1683 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID; 1684 1685 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 1686 1687 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1688 NETIF_F_HW_VLAN_CTAG_FILTER | 1689 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1690 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1691 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1692 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1693 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1694 1695 netdev->vlan_features |= 1696 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | 1697 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 1698 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1699 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1700 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1701 1702 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1703 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1704 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1705 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1706 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1707 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1708 } 1709 1710 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 1711 struct hns3_desc_cb *cb) 1712 { 1713 unsigned int order = hnae3_page_order(ring); 1714 struct page *p; 1715 1716 p = dev_alloc_pages(order); 1717 if (!p) 1718 return -ENOMEM; 1719 1720 cb->priv = p; 1721 cb->page_offset = 0; 1722 cb->reuse_flag = 0; 1723 cb->buf = page_address(p); 1724 cb->length = hnae3_page_size(ring); 1725 cb->type = DESC_TYPE_PAGE; 1726 1727 return 0; 1728 } 1729 1730 static void hns3_free_buffer(struct hns3_enet_ring *ring, 1731 struct hns3_desc_cb *cb) 1732 { 1733 if (cb->type == DESC_TYPE_SKB) 1734 dev_kfree_skb_any((struct sk_buff *)cb->priv); 1735 else if (!HNAE3_IS_TX_RING(ring)) 1736 put_page((struct page *)cb->priv); 1737 memset(cb, 0, sizeof(*cb)); 1738 } 1739 1740 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 1741 { 1742 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 1743 cb->length, ring_to_dma_dir(ring)); 1744 1745 if (dma_mapping_error(ring_to_dev(ring), cb->dma)) 1746 return -EIO; 1747 1748 return 0; 1749 } 1750 1751 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 1752 struct hns3_desc_cb *cb) 1753 { 1754 if (cb->type == DESC_TYPE_SKB) 1755 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 1756 ring_to_dma_dir(ring)); 1757 else 1758 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 1759 ring_to_dma_dir(ring)); 1760 } 1761 1762 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 1763 { 1764 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 1765 ring->desc[i].addr = 0; 1766 } 1767 1768 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i) 1769 { 1770 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 1771 1772 if (!ring->desc_cb[i].dma) 1773 return; 1774 1775 hns3_buffer_detach(ring, i); 1776 hns3_free_buffer(ring, cb); 1777 } 1778 1779 static void hns3_free_buffers(struct hns3_enet_ring *ring) 1780 { 1781 int i; 1782 1783 for (i = 0; i < ring->desc_num; i++) 1784 hns3_free_buffer_detach(ring, i); 1785 } 1786 1787 /* free desc along with its attached buffer */ 1788 static void hns3_free_desc(struct hns3_enet_ring *ring) 1789 { 1790 int size = ring->desc_num * sizeof(ring->desc[0]); 1791 1792 hns3_free_buffers(ring); 1793 1794 if (ring->desc) { 1795 dma_free_coherent(ring_to_dev(ring), size, 1796 ring->desc, ring->desc_dma_addr); 1797 ring->desc = NULL; 1798 } 1799 } 1800 1801 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 1802 { 1803 int size = ring->desc_num * sizeof(ring->desc[0]); 1804 1805 ring->desc = dma_zalloc_coherent(ring_to_dev(ring), size, 1806 &ring->desc_dma_addr, 1807 GFP_KERNEL); 1808 if (!ring->desc) 1809 return -ENOMEM; 1810 1811 return 0; 1812 } 1813 1814 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring, 1815 struct hns3_desc_cb *cb) 1816 { 1817 int ret; 1818 1819 ret = hns3_alloc_buffer(ring, cb); 1820 if (ret) 1821 goto out; 1822 1823 ret = hns3_map_buffer(ring, cb); 1824 if (ret) 1825 goto out_with_buf; 1826 1827 return 0; 1828 1829 out_with_buf: 1830 hns3_free_buffer(ring, cb); 1831 out: 1832 return ret; 1833 } 1834 1835 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i) 1836 { 1837 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]); 1838 1839 if (ret) 1840 return ret; 1841 1842 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 1843 1844 return 0; 1845 } 1846 1847 /* Allocate memory for raw pkg, and map with dma */ 1848 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 1849 { 1850 int i, j, ret; 1851 1852 for (i = 0; i < ring->desc_num; i++) { 1853 ret = hns3_alloc_buffer_attach(ring, i); 1854 if (ret) 1855 goto out_buffer_fail; 1856 } 1857 1858 return 0; 1859 1860 out_buffer_fail: 1861 for (j = i - 1; j >= 0; j--) 1862 hns3_free_buffer_detach(ring, j); 1863 return ret; 1864 } 1865 1866 /* detach a in-used buffer and replace with a reserved one */ 1867 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 1868 struct hns3_desc_cb *res_cb) 1869 { 1870 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 1871 ring->desc_cb[i] = *res_cb; 1872 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 1873 ring->desc[i].rx.bd_base_info = 0; 1874 } 1875 1876 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 1877 { 1878 ring->desc_cb[i].reuse_flag = 0; 1879 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma 1880 + ring->desc_cb[i].page_offset); 1881 ring->desc[i].rx.bd_base_info = 0; 1882 } 1883 1884 static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes, 1885 int *pkts) 1886 { 1887 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 1888 1889 (*pkts) += (desc_cb->type == DESC_TYPE_SKB); 1890 (*bytes) += desc_cb->length; 1891 /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/ 1892 hns3_free_buffer_detach(ring, ring->next_to_clean); 1893 1894 ring_ptr_move_fw(ring, next_to_clean); 1895 } 1896 1897 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h) 1898 { 1899 int u = ring->next_to_use; 1900 int c = ring->next_to_clean; 1901 1902 if (unlikely(h > ring->desc_num)) 1903 return 0; 1904 1905 return u > c ? (h > c && h <= u) : (h > c || h <= u); 1906 } 1907 1908 bool hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget) 1909 { 1910 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 1911 struct netdev_queue *dev_queue; 1912 int bytes, pkts; 1913 int head; 1914 1915 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG); 1916 rmb(); /* Make sure head is ready before touch any data */ 1917 1918 if (is_ring_empty(ring) || head == ring->next_to_clean) 1919 return true; /* no data to poll */ 1920 1921 if (unlikely(!is_valid_clean_head(ring, head))) { 1922 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head, 1923 ring->next_to_use, ring->next_to_clean); 1924 1925 u64_stats_update_begin(&ring->syncp); 1926 ring->stats.io_err_cnt++; 1927 u64_stats_update_end(&ring->syncp); 1928 return true; 1929 } 1930 1931 bytes = 0; 1932 pkts = 0; 1933 while (head != ring->next_to_clean && budget) { 1934 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts); 1935 /* Issue prefetch for next Tx descriptor */ 1936 prefetch(&ring->desc_cb[ring->next_to_clean]); 1937 budget--; 1938 } 1939 1940 ring->tqp_vector->tx_group.total_bytes += bytes; 1941 ring->tqp_vector->tx_group.total_packets += pkts; 1942 1943 u64_stats_update_begin(&ring->syncp); 1944 ring->stats.tx_bytes += bytes; 1945 ring->stats.tx_pkts += pkts; 1946 u64_stats_update_end(&ring->syncp); 1947 1948 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 1949 netdev_tx_completed_queue(dev_queue, pkts, bytes); 1950 1951 if (unlikely(pkts && netif_carrier_ok(netdev) && 1952 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) { 1953 /* Make sure that anybody stopping the queue after this 1954 * sees the new next_to_clean. 1955 */ 1956 smp_mb(); 1957 if (netif_tx_queue_stopped(dev_queue)) { 1958 netif_tx_wake_queue(dev_queue); 1959 ring->stats.restart_queue++; 1960 } 1961 } 1962 1963 return !!budget; 1964 } 1965 1966 static int hns3_desc_unused(struct hns3_enet_ring *ring) 1967 { 1968 int ntc = ring->next_to_clean; 1969 int ntu = ring->next_to_use; 1970 1971 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 1972 } 1973 1974 static void 1975 hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count) 1976 { 1977 struct hns3_desc_cb *desc_cb; 1978 struct hns3_desc_cb res_cbs; 1979 int i, ret; 1980 1981 for (i = 0; i < cleand_count; i++) { 1982 desc_cb = &ring->desc_cb[ring->next_to_use]; 1983 if (desc_cb->reuse_flag) { 1984 u64_stats_update_begin(&ring->syncp); 1985 ring->stats.reuse_pg_cnt++; 1986 u64_stats_update_end(&ring->syncp); 1987 1988 hns3_reuse_buffer(ring, ring->next_to_use); 1989 } else { 1990 ret = hns3_reserve_buffer_map(ring, &res_cbs); 1991 if (ret) { 1992 u64_stats_update_begin(&ring->syncp); 1993 ring->stats.sw_err_cnt++; 1994 u64_stats_update_end(&ring->syncp); 1995 1996 netdev_err(ring->tqp->handle->kinfo.netdev, 1997 "hnae reserve buffer map failed.\n"); 1998 break; 1999 } 2000 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 2001 } 2002 2003 ring_ptr_move_fw(ring, next_to_use); 2004 } 2005 2006 wmb(); /* Make all data has been write before submit */ 2007 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2008 } 2009 2010 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2011 struct hns3_enet_ring *ring, int pull_len, 2012 struct hns3_desc_cb *desc_cb) 2013 { 2014 struct hns3_desc *desc; 2015 int truesize, size; 2016 int last_offset; 2017 bool twobufs; 2018 2019 twobufs = ((PAGE_SIZE < 8192) && 2020 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048); 2021 2022 desc = &ring->desc[ring->next_to_clean]; 2023 size = le16_to_cpu(desc->rx.size); 2024 2025 truesize = hnae3_buf_size(ring); 2026 2027 if (!twobufs) 2028 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring); 2029 2030 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2031 size - pull_len, truesize); 2032 2033 /* Avoid re-using remote pages,flag default unreuse */ 2034 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id())) 2035 return; 2036 2037 if (twobufs) { 2038 /* If we are only owner of page we can reuse it */ 2039 if (likely(page_count(desc_cb->priv) == 1)) { 2040 /* Flip page offset to other buffer */ 2041 desc_cb->page_offset ^= truesize; 2042 2043 desc_cb->reuse_flag = 1; 2044 /* bump ref count on page before it is given*/ 2045 get_page(desc_cb->priv); 2046 } 2047 return; 2048 } 2049 2050 /* Move offset up to the next cache line */ 2051 desc_cb->page_offset += truesize; 2052 2053 if (desc_cb->page_offset <= last_offset) { 2054 desc_cb->reuse_flag = 1; 2055 /* Bump ref count on page before it is given*/ 2056 get_page(desc_cb->priv); 2057 } 2058 } 2059 2060 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2061 struct hns3_desc *desc) 2062 { 2063 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2064 int l3_type, l4_type; 2065 u32 bd_base_info; 2066 int ol4_type; 2067 u32 l234info; 2068 2069 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2070 l234info = le32_to_cpu(desc->rx.l234_info); 2071 2072 skb->ip_summed = CHECKSUM_NONE; 2073 2074 skb_checksum_none_assert(skb); 2075 2076 if (!(netdev->features & NETIF_F_RXCSUM)) 2077 return; 2078 2079 /* check if hardware has done checksum */ 2080 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B)) 2081 return; 2082 2083 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) || 2084 hnae3_get_bit(l234info, HNS3_RXD_L4E_B) || 2085 hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) || 2086 hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) { 2087 netdev_err(netdev, "L3/L4 error pkt\n"); 2088 u64_stats_update_begin(&ring->syncp); 2089 ring->stats.l3l4_csum_err++; 2090 u64_stats_update_end(&ring->syncp); 2091 2092 return; 2093 } 2094 2095 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2096 HNS3_RXD_L3ID_S); 2097 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 2098 HNS3_RXD_L4ID_S); 2099 2100 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M, 2101 HNS3_RXD_OL4ID_S); 2102 switch (ol4_type) { 2103 case HNS3_OL4_TYPE_MAC_IN_UDP: 2104 case HNS3_OL4_TYPE_NVGRE: 2105 skb->csum_level = 1; 2106 case HNS3_OL4_TYPE_NO_TUN: 2107 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 2108 if ((l3_type == HNS3_L3_TYPE_IPV4 || 2109 l3_type == HNS3_L3_TYPE_IPV6) && 2110 (l4_type == HNS3_L4_TYPE_UDP || 2111 l4_type == HNS3_L4_TYPE_TCP || 2112 l4_type == HNS3_L4_TYPE_SCTP)) 2113 skb->ip_summed = CHECKSUM_UNNECESSARY; 2114 break; 2115 } 2116 } 2117 2118 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 2119 { 2120 napi_gro_receive(&ring->tqp_vector->napi, skb); 2121 } 2122 2123 static u16 hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 2124 struct hns3_desc *desc, u32 l234info) 2125 { 2126 struct pci_dev *pdev = ring->tqp->handle->pdev; 2127 u16 vlan_tag; 2128 2129 if (pdev->revision == 0x20) { 2130 vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2131 if (!(vlan_tag & VLAN_VID_MASK)) 2132 vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2133 2134 return vlan_tag; 2135 } 2136 2137 #define HNS3_STRP_OUTER_VLAN 0x1 2138 #define HNS3_STRP_INNER_VLAN 0x2 2139 2140 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 2141 HNS3_RXD_STRP_TAGP_S)) { 2142 case HNS3_STRP_OUTER_VLAN: 2143 vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2144 break; 2145 case HNS3_STRP_INNER_VLAN: 2146 vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2147 break; 2148 default: 2149 vlan_tag = 0; 2150 break; 2151 } 2152 2153 return vlan_tag; 2154 } 2155 2156 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring, 2157 struct sk_buff **out_skb, int *out_bnum) 2158 { 2159 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2160 struct hns3_desc_cb *desc_cb; 2161 struct hns3_desc *desc; 2162 struct sk_buff *skb; 2163 unsigned char *va; 2164 u32 bd_base_info; 2165 int pull_len; 2166 u32 l234info; 2167 int length; 2168 int bnum; 2169 2170 desc = &ring->desc[ring->next_to_clean]; 2171 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2172 2173 prefetch(desc); 2174 2175 length = le16_to_cpu(desc->rx.size); 2176 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2177 2178 /* Check valid BD */ 2179 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) 2180 return -EFAULT; 2181 2182 va = (unsigned char *)desc_cb->buf + desc_cb->page_offset; 2183 2184 /* Prefetch first cache line of first page 2185 * Idea is to cache few bytes of the header of the packet. Our L1 Cache 2186 * line size is 64B so need to prefetch twice to make it 128B. But in 2187 * actual we can have greater size of caches with 128B Level 1 cache 2188 * lines. In such a case, single fetch would suffice to cache in the 2189 * relevant part of the header. 2190 */ 2191 prefetch(va); 2192 #if L1_CACHE_BYTES < 128 2193 prefetch(va + L1_CACHE_BYTES); 2194 #endif 2195 2196 skb = *out_skb = napi_alloc_skb(&ring->tqp_vector->napi, 2197 HNS3_RX_HEAD_SIZE); 2198 if (unlikely(!skb)) { 2199 netdev_err(netdev, "alloc rx skb fail\n"); 2200 2201 u64_stats_update_begin(&ring->syncp); 2202 ring->stats.sw_err_cnt++; 2203 u64_stats_update_end(&ring->syncp); 2204 2205 return -ENOMEM; 2206 } 2207 2208 prefetchw(skb->data); 2209 2210 bnum = 1; 2211 if (length <= HNS3_RX_HEAD_SIZE) { 2212 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 2213 2214 /* We can reuse buffer as-is, just make sure it is local */ 2215 if (likely(page_to_nid(desc_cb->priv) == numa_node_id())) 2216 desc_cb->reuse_flag = 1; 2217 else /* This page cannot be reused so discard it */ 2218 put_page(desc_cb->priv); 2219 2220 ring_ptr_move_fw(ring, next_to_clean); 2221 } else { 2222 u64_stats_update_begin(&ring->syncp); 2223 ring->stats.seg_pkt_cnt++; 2224 u64_stats_update_end(&ring->syncp); 2225 2226 pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE); 2227 2228 memcpy(__skb_put(skb, pull_len), va, 2229 ALIGN(pull_len, sizeof(long))); 2230 2231 hns3_nic_reuse_page(skb, 0, ring, pull_len, desc_cb); 2232 ring_ptr_move_fw(ring, next_to_clean); 2233 2234 while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) { 2235 desc = &ring->desc[ring->next_to_clean]; 2236 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2237 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2238 hns3_nic_reuse_page(skb, bnum, ring, 0, desc_cb); 2239 ring_ptr_move_fw(ring, next_to_clean); 2240 bnum++; 2241 } 2242 } 2243 2244 *out_bnum = bnum; 2245 2246 l234info = le32_to_cpu(desc->rx.l234_info); 2247 2248 /* Based on hw strategy, the tag offloaded will be stored at 2249 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 2250 * in one layer tag case. 2251 */ 2252 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 2253 u16 vlan_tag; 2254 2255 vlan_tag = hns3_parse_vlan_tag(ring, desc, l234info); 2256 if (vlan_tag & VLAN_VID_MASK) 2257 __vlan_hwaccel_put_tag(skb, 2258 htons(ETH_P_8021Q), 2259 vlan_tag); 2260 } 2261 2262 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) { 2263 netdev_err(netdev, "no valid bd,%016llx,%016llx\n", 2264 ((u64 *)desc)[0], ((u64 *)desc)[1]); 2265 u64_stats_update_begin(&ring->syncp); 2266 ring->stats.non_vld_descs++; 2267 u64_stats_update_end(&ring->syncp); 2268 2269 dev_kfree_skb_any(skb); 2270 return -EINVAL; 2271 } 2272 2273 if (unlikely((!desc->rx.pkt_len) || 2274 hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) { 2275 netdev_err(netdev, "truncated pkt\n"); 2276 u64_stats_update_begin(&ring->syncp); 2277 ring->stats.err_pkt_len++; 2278 u64_stats_update_end(&ring->syncp); 2279 2280 dev_kfree_skb_any(skb); 2281 return -EFAULT; 2282 } 2283 2284 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) { 2285 netdev_err(netdev, "L2 error pkt\n"); 2286 u64_stats_update_begin(&ring->syncp); 2287 ring->stats.l2_err++; 2288 u64_stats_update_end(&ring->syncp); 2289 2290 dev_kfree_skb_any(skb); 2291 return -EFAULT; 2292 } 2293 2294 u64_stats_update_begin(&ring->syncp); 2295 ring->stats.rx_pkts++; 2296 ring->stats.rx_bytes += skb->len; 2297 u64_stats_update_end(&ring->syncp); 2298 2299 ring->tqp_vector->rx_group.total_bytes += skb->len; 2300 2301 hns3_rx_checksum(ring, skb, desc); 2302 return 0; 2303 } 2304 2305 int hns3_clean_rx_ring( 2306 struct hns3_enet_ring *ring, int budget, 2307 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 2308 { 2309 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 2310 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2311 int recv_pkts, recv_bds, clean_count, err; 2312 int unused_count = hns3_desc_unused(ring); 2313 struct sk_buff *skb = NULL; 2314 int num, bnum = 0; 2315 2316 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG); 2317 rmb(); /* Make sure num taken effect before the other data is touched */ 2318 2319 recv_pkts = 0, recv_bds = 0, clean_count = 0; 2320 num -= unused_count; 2321 2322 while (recv_pkts < budget && recv_bds < num) { 2323 /* Reuse or realloc buffers */ 2324 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 2325 hns3_nic_alloc_rx_buffers(ring, 2326 clean_count + unused_count); 2327 clean_count = 0; 2328 unused_count = hns3_desc_unused(ring); 2329 } 2330 2331 /* Poll one pkt */ 2332 err = hns3_handle_rx_bd(ring, &skb, &bnum); 2333 if (unlikely(!skb)) /* This fault cannot be repaired */ 2334 goto out; 2335 2336 recv_bds += bnum; 2337 clean_count += bnum; 2338 if (unlikely(err)) { /* Do jump the err */ 2339 recv_pkts++; 2340 continue; 2341 } 2342 2343 /* Do update ip stack process */ 2344 skb->protocol = eth_type_trans(skb, netdev); 2345 rx_fn(ring, skb); 2346 2347 recv_pkts++; 2348 } 2349 2350 out: 2351 /* Make all data has been write before submit */ 2352 if (clean_count + unused_count > 0) 2353 hns3_nic_alloc_rx_buffers(ring, 2354 clean_count + unused_count); 2355 2356 return recv_pkts; 2357 } 2358 2359 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 2360 { 2361 struct hns3_enet_tqp_vector *tqp_vector = 2362 ring_group->ring->tqp_vector; 2363 enum hns3_flow_level_range new_flow_level; 2364 int packets_per_msecs; 2365 int bytes_per_msecs; 2366 u32 time_passed_ms; 2367 u16 new_int_gl; 2368 2369 if (!ring_group->coal.int_gl || !tqp_vector->last_jiffies) 2370 return false; 2371 2372 if (ring_group->total_packets == 0) { 2373 ring_group->coal.int_gl = HNS3_INT_GL_50K; 2374 ring_group->coal.flow_level = HNS3_FLOW_LOW; 2375 return true; 2376 } 2377 2378 /* Simple throttlerate management 2379 * 0-10MB/s lower (50000 ints/s) 2380 * 10-20MB/s middle (20000 ints/s) 2381 * 20-1249MB/s high (18000 ints/s) 2382 * > 40000pps ultra (8000 ints/s) 2383 */ 2384 new_flow_level = ring_group->coal.flow_level; 2385 new_int_gl = ring_group->coal.int_gl; 2386 time_passed_ms = 2387 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 2388 2389 if (!time_passed_ms) 2390 return false; 2391 2392 do_div(ring_group->total_packets, time_passed_ms); 2393 packets_per_msecs = ring_group->total_packets; 2394 2395 do_div(ring_group->total_bytes, time_passed_ms); 2396 bytes_per_msecs = ring_group->total_bytes; 2397 2398 #define HNS3_RX_LOW_BYTE_RATE 10000 2399 #define HNS3_RX_MID_BYTE_RATE 20000 2400 2401 switch (new_flow_level) { 2402 case HNS3_FLOW_LOW: 2403 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 2404 new_flow_level = HNS3_FLOW_MID; 2405 break; 2406 case HNS3_FLOW_MID: 2407 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 2408 new_flow_level = HNS3_FLOW_HIGH; 2409 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 2410 new_flow_level = HNS3_FLOW_LOW; 2411 break; 2412 case HNS3_FLOW_HIGH: 2413 case HNS3_FLOW_ULTRA: 2414 default: 2415 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 2416 new_flow_level = HNS3_FLOW_MID; 2417 break; 2418 } 2419 2420 #define HNS3_RX_ULTRA_PACKET_RATE 40 2421 2422 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 2423 &tqp_vector->rx_group == ring_group) 2424 new_flow_level = HNS3_FLOW_ULTRA; 2425 2426 switch (new_flow_level) { 2427 case HNS3_FLOW_LOW: 2428 new_int_gl = HNS3_INT_GL_50K; 2429 break; 2430 case HNS3_FLOW_MID: 2431 new_int_gl = HNS3_INT_GL_20K; 2432 break; 2433 case HNS3_FLOW_HIGH: 2434 new_int_gl = HNS3_INT_GL_18K; 2435 break; 2436 case HNS3_FLOW_ULTRA: 2437 new_int_gl = HNS3_INT_GL_8K; 2438 break; 2439 default: 2440 break; 2441 } 2442 2443 ring_group->total_bytes = 0; 2444 ring_group->total_packets = 0; 2445 ring_group->coal.flow_level = new_flow_level; 2446 if (new_int_gl != ring_group->coal.int_gl) { 2447 ring_group->coal.int_gl = new_int_gl; 2448 return true; 2449 } 2450 return false; 2451 } 2452 2453 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 2454 { 2455 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 2456 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 2457 bool rx_update, tx_update; 2458 2459 if (tqp_vector->int_adapt_down > 0) { 2460 tqp_vector->int_adapt_down--; 2461 return; 2462 } 2463 2464 if (rx_group->coal.gl_adapt_enable) { 2465 rx_update = hns3_get_new_int_gl(rx_group); 2466 if (rx_update) 2467 hns3_set_vector_coalesce_rx_gl(tqp_vector, 2468 rx_group->coal.int_gl); 2469 } 2470 2471 if (tx_group->coal.gl_adapt_enable) { 2472 tx_update = hns3_get_new_int_gl(&tqp_vector->tx_group); 2473 if (tx_update) 2474 hns3_set_vector_coalesce_tx_gl(tqp_vector, 2475 tx_group->coal.int_gl); 2476 } 2477 2478 tqp_vector->last_jiffies = jiffies; 2479 tqp_vector->int_adapt_down = HNS3_INT_ADAPT_DOWN_START; 2480 } 2481 2482 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 2483 { 2484 struct hns3_enet_ring *ring; 2485 int rx_pkt_total = 0; 2486 2487 struct hns3_enet_tqp_vector *tqp_vector = 2488 container_of(napi, struct hns3_enet_tqp_vector, napi); 2489 bool clean_complete = true; 2490 int rx_budget; 2491 2492 /* Since the actual Tx work is minimal, we can give the Tx a larger 2493 * budget and be more aggressive about cleaning up the Tx descriptors. 2494 */ 2495 hns3_for_each_ring(ring, tqp_vector->tx_group) { 2496 if (!hns3_clean_tx_ring(ring, budget)) 2497 clean_complete = false; 2498 } 2499 2500 /* make sure rx ring budget not smaller than 1 */ 2501 rx_budget = max(budget / tqp_vector->num_tqps, 1); 2502 2503 hns3_for_each_ring(ring, tqp_vector->rx_group) { 2504 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 2505 hns3_rx_skb); 2506 2507 if (rx_cleaned >= rx_budget) 2508 clean_complete = false; 2509 2510 rx_pkt_total += rx_cleaned; 2511 } 2512 2513 tqp_vector->rx_group.total_packets += rx_pkt_total; 2514 2515 if (!clean_complete) 2516 return budget; 2517 2518 napi_complete(napi); 2519 hns3_update_new_int_gl(tqp_vector); 2520 hns3_mask_vector_irq(tqp_vector, 1); 2521 2522 return rx_pkt_total; 2523 } 2524 2525 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 2526 struct hnae3_ring_chain_node *head) 2527 { 2528 struct pci_dev *pdev = tqp_vector->handle->pdev; 2529 struct hnae3_ring_chain_node *cur_chain = head; 2530 struct hnae3_ring_chain_node *chain; 2531 struct hns3_enet_ring *tx_ring; 2532 struct hns3_enet_ring *rx_ring; 2533 2534 tx_ring = tqp_vector->tx_group.ring; 2535 if (tx_ring) { 2536 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 2537 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 2538 HNAE3_RING_TYPE_TX); 2539 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2540 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 2541 2542 cur_chain->next = NULL; 2543 2544 while (tx_ring->next) { 2545 tx_ring = tx_ring->next; 2546 2547 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 2548 GFP_KERNEL); 2549 if (!chain) 2550 return -ENOMEM; 2551 2552 cur_chain->next = chain; 2553 chain->tqp_index = tx_ring->tqp->tqp_index; 2554 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 2555 HNAE3_RING_TYPE_TX); 2556 hnae3_set_field(chain->int_gl_idx, 2557 HNAE3_RING_GL_IDX_M, 2558 HNAE3_RING_GL_IDX_S, 2559 HNAE3_RING_GL_TX); 2560 2561 cur_chain = chain; 2562 } 2563 } 2564 2565 rx_ring = tqp_vector->rx_group.ring; 2566 if (!tx_ring && rx_ring) { 2567 cur_chain->next = NULL; 2568 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 2569 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 2570 HNAE3_RING_TYPE_RX); 2571 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2572 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 2573 2574 rx_ring = rx_ring->next; 2575 } 2576 2577 while (rx_ring) { 2578 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 2579 if (!chain) 2580 return -ENOMEM; 2581 2582 cur_chain->next = chain; 2583 chain->tqp_index = rx_ring->tqp->tqp_index; 2584 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 2585 HNAE3_RING_TYPE_RX); 2586 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2587 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 2588 2589 cur_chain = chain; 2590 2591 rx_ring = rx_ring->next; 2592 } 2593 2594 return 0; 2595 } 2596 2597 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 2598 struct hnae3_ring_chain_node *head) 2599 { 2600 struct pci_dev *pdev = tqp_vector->handle->pdev; 2601 struct hnae3_ring_chain_node *chain_tmp, *chain; 2602 2603 chain = head->next; 2604 2605 while (chain) { 2606 chain_tmp = chain->next; 2607 devm_kfree(&pdev->dev, chain); 2608 chain = chain_tmp; 2609 } 2610 } 2611 2612 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 2613 struct hns3_enet_ring *ring) 2614 { 2615 ring->next = group->ring; 2616 group->ring = ring; 2617 2618 group->count++; 2619 } 2620 2621 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 2622 { 2623 struct hnae3_ring_chain_node vector_ring_chain; 2624 struct hnae3_handle *h = priv->ae_handle; 2625 struct hns3_enet_tqp_vector *tqp_vector; 2626 int ret = 0; 2627 u16 i; 2628 2629 for (i = 0; i < priv->vector_num; i++) { 2630 tqp_vector = &priv->tqp_vector[i]; 2631 hns3_vector_gl_rl_init_hw(tqp_vector, priv); 2632 tqp_vector->num_tqps = 0; 2633 } 2634 2635 for (i = 0; i < h->kinfo.num_tqps; i++) { 2636 u16 vector_i = i % priv->vector_num; 2637 u16 tqp_num = h->kinfo.num_tqps; 2638 2639 tqp_vector = &priv->tqp_vector[vector_i]; 2640 2641 hns3_add_ring_to_group(&tqp_vector->tx_group, 2642 priv->ring_data[i].ring); 2643 2644 hns3_add_ring_to_group(&tqp_vector->rx_group, 2645 priv->ring_data[i + tqp_num].ring); 2646 2647 priv->ring_data[i].ring->tqp_vector = tqp_vector; 2648 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector; 2649 tqp_vector->num_tqps++; 2650 } 2651 2652 for (i = 0; i < priv->vector_num; i++) { 2653 tqp_vector = &priv->tqp_vector[i]; 2654 2655 tqp_vector->rx_group.total_bytes = 0; 2656 tqp_vector->rx_group.total_packets = 0; 2657 tqp_vector->tx_group.total_bytes = 0; 2658 tqp_vector->tx_group.total_packets = 0; 2659 tqp_vector->handle = h; 2660 2661 ret = hns3_get_vector_ring_chain(tqp_vector, 2662 &vector_ring_chain); 2663 if (ret) 2664 return ret; 2665 2666 ret = h->ae_algo->ops->map_ring_to_vector(h, 2667 tqp_vector->vector_irq, &vector_ring_chain); 2668 2669 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 2670 2671 if (ret) 2672 return ret; 2673 2674 netif_napi_add(priv->netdev, &tqp_vector->napi, 2675 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 2676 } 2677 2678 return 0; 2679 } 2680 2681 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 2682 { 2683 struct hnae3_handle *h = priv->ae_handle; 2684 struct hns3_enet_tqp_vector *tqp_vector; 2685 struct hnae3_vector_info *vector; 2686 struct pci_dev *pdev = h->pdev; 2687 u16 tqp_num = h->kinfo.num_tqps; 2688 u16 vector_num; 2689 int ret = 0; 2690 u16 i; 2691 2692 /* RSS size, cpu online and vector_num should be the same */ 2693 /* Should consider 2p/4p later */ 2694 vector_num = min_t(u16, num_online_cpus(), tqp_num); 2695 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 2696 GFP_KERNEL); 2697 if (!vector) 2698 return -ENOMEM; 2699 2700 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 2701 2702 priv->vector_num = vector_num; 2703 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 2704 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 2705 GFP_KERNEL); 2706 if (!priv->tqp_vector) { 2707 ret = -ENOMEM; 2708 goto out; 2709 } 2710 2711 for (i = 0; i < priv->vector_num; i++) { 2712 tqp_vector = &priv->tqp_vector[i]; 2713 tqp_vector->idx = i; 2714 tqp_vector->mask_addr = vector[i].io_addr; 2715 tqp_vector->vector_irq = vector[i].vector; 2716 hns3_vector_gl_rl_init(tqp_vector, priv); 2717 } 2718 2719 out: 2720 devm_kfree(&pdev->dev, vector); 2721 return ret; 2722 } 2723 2724 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 2725 { 2726 group->ring = NULL; 2727 group->count = 0; 2728 } 2729 2730 static int hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 2731 { 2732 struct hnae3_ring_chain_node vector_ring_chain; 2733 struct hnae3_handle *h = priv->ae_handle; 2734 struct hns3_enet_tqp_vector *tqp_vector; 2735 int i, ret; 2736 2737 for (i = 0; i < priv->vector_num; i++) { 2738 tqp_vector = &priv->tqp_vector[i]; 2739 2740 ret = hns3_get_vector_ring_chain(tqp_vector, 2741 &vector_ring_chain); 2742 if (ret) 2743 return ret; 2744 2745 ret = h->ae_algo->ops->unmap_ring_from_vector(h, 2746 tqp_vector->vector_irq, &vector_ring_chain); 2747 if (ret) 2748 return ret; 2749 2750 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 2751 2752 if (priv->tqp_vector[i].irq_init_flag == HNS3_VECTOR_INITED) { 2753 (void)irq_set_affinity_hint( 2754 priv->tqp_vector[i].vector_irq, 2755 NULL); 2756 free_irq(priv->tqp_vector[i].vector_irq, 2757 &priv->tqp_vector[i]); 2758 } 2759 2760 priv->ring_data[i].ring->irq_init_flag = HNS3_VECTOR_NOT_INITED; 2761 hns3_clear_ring_group(&tqp_vector->rx_group); 2762 hns3_clear_ring_group(&tqp_vector->tx_group); 2763 netif_napi_del(&priv->tqp_vector[i].napi); 2764 } 2765 2766 return 0; 2767 } 2768 2769 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 2770 { 2771 struct hnae3_handle *h = priv->ae_handle; 2772 struct pci_dev *pdev = h->pdev; 2773 int i, ret; 2774 2775 for (i = 0; i < priv->vector_num; i++) { 2776 struct hns3_enet_tqp_vector *tqp_vector; 2777 2778 tqp_vector = &priv->tqp_vector[i]; 2779 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 2780 if (ret) 2781 return ret; 2782 } 2783 2784 devm_kfree(&pdev->dev, priv->tqp_vector); 2785 return 0; 2786 } 2787 2788 static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 2789 int ring_type) 2790 { 2791 struct hns3_nic_ring_data *ring_data = priv->ring_data; 2792 int queue_num = priv->ae_handle->kinfo.num_tqps; 2793 struct pci_dev *pdev = priv->ae_handle->pdev; 2794 struct hns3_enet_ring *ring; 2795 2796 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL); 2797 if (!ring) 2798 return -ENOMEM; 2799 2800 if (ring_type == HNAE3_RING_TYPE_TX) { 2801 ring_data[q->tqp_index].ring = ring; 2802 ring_data[q->tqp_index].queue_index = q->tqp_index; 2803 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET; 2804 } else { 2805 ring_data[q->tqp_index + queue_num].ring = ring; 2806 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index; 2807 ring->io_base = q->io_base; 2808 } 2809 2810 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 2811 2812 ring->tqp = q; 2813 ring->desc = NULL; 2814 ring->desc_cb = NULL; 2815 ring->dev = priv->dev; 2816 ring->desc_dma_addr = 0; 2817 ring->buf_size = q->buf_size; 2818 ring->desc_num = q->desc_num; 2819 ring->next_to_use = 0; 2820 ring->next_to_clean = 0; 2821 2822 return 0; 2823 } 2824 2825 static int hns3_queue_to_ring(struct hnae3_queue *tqp, 2826 struct hns3_nic_priv *priv) 2827 { 2828 int ret; 2829 2830 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 2831 if (ret) 2832 return ret; 2833 2834 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 2835 if (ret) 2836 return ret; 2837 2838 return 0; 2839 } 2840 2841 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 2842 { 2843 struct hnae3_handle *h = priv->ae_handle; 2844 struct pci_dev *pdev = h->pdev; 2845 int i, ret; 2846 2847 priv->ring_data = devm_kzalloc(&pdev->dev, 2848 array3_size(h->kinfo.num_tqps, 2849 sizeof(*priv->ring_data), 2850 2), 2851 GFP_KERNEL); 2852 if (!priv->ring_data) 2853 return -ENOMEM; 2854 2855 for (i = 0; i < h->kinfo.num_tqps; i++) { 2856 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv); 2857 if (ret) 2858 goto err; 2859 } 2860 2861 return 0; 2862 err: 2863 devm_kfree(&pdev->dev, priv->ring_data); 2864 return ret; 2865 } 2866 2867 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 2868 { 2869 struct hnae3_handle *h = priv->ae_handle; 2870 int i; 2871 2872 for (i = 0; i < h->kinfo.num_tqps; i++) { 2873 devm_kfree(priv->dev, priv->ring_data[i].ring); 2874 devm_kfree(priv->dev, 2875 priv->ring_data[i + h->kinfo.num_tqps].ring); 2876 } 2877 devm_kfree(priv->dev, priv->ring_data); 2878 } 2879 2880 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 2881 { 2882 int ret; 2883 2884 if (ring->desc_num <= 0 || ring->buf_size <= 0) 2885 return -EINVAL; 2886 2887 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]), 2888 GFP_KERNEL); 2889 if (!ring->desc_cb) { 2890 ret = -ENOMEM; 2891 goto out; 2892 } 2893 2894 ret = hns3_alloc_desc(ring); 2895 if (ret) 2896 goto out_with_desc_cb; 2897 2898 if (!HNAE3_IS_TX_RING(ring)) { 2899 ret = hns3_alloc_ring_buffers(ring); 2900 if (ret) 2901 goto out_with_desc; 2902 } 2903 2904 return 0; 2905 2906 out_with_desc: 2907 hns3_free_desc(ring); 2908 out_with_desc_cb: 2909 kfree(ring->desc_cb); 2910 ring->desc_cb = NULL; 2911 out: 2912 return ret; 2913 } 2914 2915 static void hns3_fini_ring(struct hns3_enet_ring *ring) 2916 { 2917 hns3_free_desc(ring); 2918 kfree(ring->desc_cb); 2919 ring->desc_cb = NULL; 2920 ring->next_to_clean = 0; 2921 ring->next_to_use = 0; 2922 } 2923 2924 static int hns3_buf_size2type(u32 buf_size) 2925 { 2926 int bd_size_type; 2927 2928 switch (buf_size) { 2929 case 512: 2930 bd_size_type = HNS3_BD_SIZE_512_TYPE; 2931 break; 2932 case 1024: 2933 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 2934 break; 2935 case 2048: 2936 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 2937 break; 2938 case 4096: 2939 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 2940 break; 2941 default: 2942 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 2943 } 2944 2945 return bd_size_type; 2946 } 2947 2948 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 2949 { 2950 dma_addr_t dma = ring->desc_dma_addr; 2951 struct hnae3_queue *q = ring->tqp; 2952 2953 if (!HNAE3_IS_TX_RING(ring)) { 2954 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, 2955 (u32)dma); 2956 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 2957 (u32)((dma >> 31) >> 1)); 2958 2959 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 2960 hns3_buf_size2type(ring->buf_size)); 2961 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 2962 ring->desc_num / 8 - 1); 2963 2964 } else { 2965 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 2966 (u32)dma); 2967 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 2968 (u32)((dma >> 31) >> 1)); 2969 2970 hns3_write_dev(q, HNS3_RING_TX_RING_BD_LEN_REG, 2971 hns3_buf_size2type(ring->buf_size)); 2972 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 2973 ring->desc_num / 8 - 1); 2974 } 2975 } 2976 2977 int hns3_init_all_ring(struct hns3_nic_priv *priv) 2978 { 2979 struct hnae3_handle *h = priv->ae_handle; 2980 int ring_num = h->kinfo.num_tqps * 2; 2981 int i, j; 2982 int ret; 2983 2984 for (i = 0; i < ring_num; i++) { 2985 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring); 2986 if (ret) { 2987 dev_err(priv->dev, 2988 "Alloc ring memory fail! ret=%d\n", ret); 2989 goto out_when_alloc_ring_memory; 2990 } 2991 2992 u64_stats_init(&priv->ring_data[i].ring->syncp); 2993 } 2994 2995 return 0; 2996 2997 out_when_alloc_ring_memory: 2998 for (j = i - 1; j >= 0; j--) 2999 hns3_fini_ring(priv->ring_data[j].ring); 3000 3001 return -ENOMEM; 3002 } 3003 3004 int hns3_uninit_all_ring(struct hns3_nic_priv *priv) 3005 { 3006 struct hnae3_handle *h = priv->ae_handle; 3007 int i; 3008 3009 for (i = 0; i < h->kinfo.num_tqps; i++) { 3010 if (h->ae_algo->ops->reset_queue) 3011 h->ae_algo->ops->reset_queue(h, i); 3012 3013 hns3_fini_ring(priv->ring_data[i].ring); 3014 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring); 3015 } 3016 return 0; 3017 } 3018 3019 /* Set mac addr if it is configured. or leave it to the AE driver */ 3020 static void hns3_init_mac_addr(struct net_device *netdev, bool init) 3021 { 3022 struct hns3_nic_priv *priv = netdev_priv(netdev); 3023 struct hnae3_handle *h = priv->ae_handle; 3024 u8 mac_addr_temp[ETH_ALEN]; 3025 3026 if (h->ae_algo->ops->get_mac_addr && init) { 3027 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 3028 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 3029 } 3030 3031 /* Check if the MAC address is valid, if not get a random one */ 3032 if (!is_valid_ether_addr(netdev->dev_addr)) { 3033 eth_hw_addr_random(netdev); 3034 dev_warn(priv->dev, "using random MAC address %pM\n", 3035 netdev->dev_addr); 3036 } 3037 3038 if (h->ae_algo->ops->set_mac_addr) 3039 h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 3040 3041 } 3042 3043 static void hns3_uninit_mac_addr(struct net_device *netdev) 3044 { 3045 struct hns3_nic_priv *priv = netdev_priv(netdev); 3046 struct hnae3_handle *h = priv->ae_handle; 3047 3048 if (h->ae_algo->ops->rm_uc_addr) 3049 h->ae_algo->ops->rm_uc_addr(h, netdev->dev_addr); 3050 } 3051 3052 static void hns3_nic_set_priv_ops(struct net_device *netdev) 3053 { 3054 struct hns3_nic_priv *priv = netdev_priv(netdev); 3055 3056 if ((netdev->features & NETIF_F_TSO) || 3057 (netdev->features & NETIF_F_TSO6)) { 3058 priv->ops.fill_desc = hns3_fill_desc_tso; 3059 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 3060 } else { 3061 priv->ops.fill_desc = hns3_fill_desc; 3062 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 3063 } 3064 } 3065 3066 static int hns3_client_init(struct hnae3_handle *handle) 3067 { 3068 struct pci_dev *pdev = handle->pdev; 3069 struct hns3_nic_priv *priv; 3070 struct net_device *netdev; 3071 int ret; 3072 3073 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), 3074 hns3_get_max_available_channels(handle)); 3075 if (!netdev) 3076 return -ENOMEM; 3077 3078 priv = netdev_priv(netdev); 3079 priv->dev = &pdev->dev; 3080 priv->netdev = netdev; 3081 priv->ae_handle = handle; 3082 priv->ae_handle->last_reset_time = jiffies; 3083 priv->tx_timeout_count = 0; 3084 3085 handle->kinfo.netdev = netdev; 3086 handle->priv = (void *)priv; 3087 3088 hns3_init_mac_addr(netdev, true); 3089 3090 hns3_set_default_feature(netdev); 3091 3092 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 3093 netdev->priv_flags |= IFF_UNICAST_FLT; 3094 netdev->netdev_ops = &hns3_nic_netdev_ops; 3095 SET_NETDEV_DEV(netdev, &pdev->dev); 3096 hns3_ethtool_set_ops(netdev); 3097 hns3_nic_set_priv_ops(netdev); 3098 3099 /* Carrier off reporting is important to ethtool even BEFORE open */ 3100 netif_carrier_off(netdev); 3101 3102 if (handle->flags & HNAE3_SUPPORT_VF) 3103 handle->reset_level = HNAE3_VF_RESET; 3104 else 3105 handle->reset_level = HNAE3_FUNC_RESET; 3106 3107 ret = hns3_get_ring_config(priv); 3108 if (ret) { 3109 ret = -ENOMEM; 3110 goto out_get_ring_cfg; 3111 } 3112 3113 ret = hns3_nic_alloc_vector_data(priv); 3114 if (ret) { 3115 ret = -ENOMEM; 3116 goto out_alloc_vector_data; 3117 } 3118 3119 ret = hns3_nic_init_vector_data(priv); 3120 if (ret) { 3121 ret = -ENOMEM; 3122 goto out_init_vector_data; 3123 } 3124 3125 ret = hns3_init_all_ring(priv); 3126 if (ret) { 3127 ret = -ENOMEM; 3128 goto out_init_ring_data; 3129 } 3130 3131 ret = register_netdev(netdev); 3132 if (ret) { 3133 dev_err(priv->dev, "probe register netdev fail!\n"); 3134 goto out_reg_netdev_fail; 3135 } 3136 3137 hns3_dcbnl_setup(handle); 3138 3139 /* MTU range: (ETH_MIN_MTU(kernel default) - 9706) */ 3140 netdev->max_mtu = HNS3_MAX_MTU - (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); 3141 3142 return ret; 3143 3144 out_reg_netdev_fail: 3145 out_init_ring_data: 3146 (void)hns3_nic_uninit_vector_data(priv); 3147 out_init_vector_data: 3148 hns3_nic_dealloc_vector_data(priv); 3149 out_alloc_vector_data: 3150 priv->ring_data = NULL; 3151 out_get_ring_cfg: 3152 priv->ae_handle = NULL; 3153 free_netdev(netdev); 3154 return ret; 3155 } 3156 3157 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 3158 { 3159 struct net_device *netdev = handle->kinfo.netdev; 3160 struct hns3_nic_priv *priv = netdev_priv(netdev); 3161 int ret; 3162 3163 if (netdev->reg_state != NETREG_UNINITIALIZED) 3164 unregister_netdev(netdev); 3165 3166 hns3_force_clear_all_rx_ring(handle); 3167 3168 ret = hns3_nic_uninit_vector_data(priv); 3169 if (ret) 3170 netdev_err(netdev, "uninit vector error\n"); 3171 3172 ret = hns3_nic_dealloc_vector_data(priv); 3173 if (ret) 3174 netdev_err(netdev, "dealloc vector error\n"); 3175 3176 ret = hns3_uninit_all_ring(priv); 3177 if (ret) 3178 netdev_err(netdev, "uninit ring error\n"); 3179 3180 hns3_put_ring_config(priv); 3181 3182 priv->ring_data = NULL; 3183 3184 hns3_uninit_mac_addr(netdev); 3185 3186 free_netdev(netdev); 3187 } 3188 3189 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 3190 { 3191 struct net_device *netdev = handle->kinfo.netdev; 3192 3193 if (!netdev) 3194 return; 3195 3196 if (linkup) { 3197 netif_carrier_on(netdev); 3198 netif_tx_wake_all_queues(netdev); 3199 netdev_info(netdev, "link up\n"); 3200 } else { 3201 netif_carrier_off(netdev); 3202 netif_tx_stop_all_queues(netdev); 3203 netdev_info(netdev, "link down\n"); 3204 } 3205 } 3206 3207 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc) 3208 { 3209 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3210 struct net_device *ndev = kinfo->netdev; 3211 bool if_running; 3212 int ret; 3213 3214 if (tc > HNAE3_MAX_TC) 3215 return -EINVAL; 3216 3217 if (!ndev) 3218 return -ENODEV; 3219 3220 if_running = netif_running(ndev); 3221 3222 if (if_running) { 3223 (void)hns3_nic_net_stop(ndev); 3224 msleep(100); 3225 } 3226 3227 ret = (kinfo->dcb_ops && kinfo->dcb_ops->map_update) ? 3228 kinfo->dcb_ops->map_update(handle) : -EOPNOTSUPP; 3229 if (ret) 3230 goto err_out; 3231 3232 ret = hns3_nic_set_real_num_queue(ndev); 3233 3234 err_out: 3235 if (if_running) 3236 (void)hns3_nic_net_open(ndev); 3237 3238 return ret; 3239 } 3240 3241 static void hns3_recover_hw_addr(struct net_device *ndev) 3242 { 3243 struct netdev_hw_addr_list *list; 3244 struct netdev_hw_addr *ha, *tmp; 3245 3246 /* go through and sync uc_addr entries to the device */ 3247 list = &ndev->uc; 3248 list_for_each_entry_safe(ha, tmp, &list->list, list) 3249 hns3_nic_uc_sync(ndev, ha->addr); 3250 3251 /* go through and sync mc_addr entries to the device */ 3252 list = &ndev->mc; 3253 list_for_each_entry_safe(ha, tmp, &list->list, list) 3254 hns3_nic_mc_sync(ndev, ha->addr); 3255 } 3256 3257 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 3258 { 3259 while (ring->next_to_clean != ring->next_to_use) { 3260 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 3261 hns3_free_buffer_detach(ring, ring->next_to_clean); 3262 ring_ptr_move_fw(ring, next_to_clean); 3263 } 3264 } 3265 3266 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 3267 { 3268 struct hns3_desc_cb res_cbs; 3269 int ret; 3270 3271 while (ring->next_to_use != ring->next_to_clean) { 3272 /* When a buffer is not reused, it's memory has been 3273 * freed in hns3_handle_rx_bd or will be freed by 3274 * stack, so we need to replace the buffer here. 3275 */ 3276 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3277 ret = hns3_reserve_buffer_map(ring, &res_cbs); 3278 if (ret) { 3279 u64_stats_update_begin(&ring->syncp); 3280 ring->stats.sw_err_cnt++; 3281 u64_stats_update_end(&ring->syncp); 3282 /* if alloc new buffer fail, exit directly 3283 * and reclear in up flow. 3284 */ 3285 netdev_warn(ring->tqp->handle->kinfo.netdev, 3286 "reserve buffer map failed, ret = %d\n", 3287 ret); 3288 return ret; 3289 } 3290 hns3_replace_buffer(ring, ring->next_to_use, 3291 &res_cbs); 3292 } 3293 ring_ptr_move_fw(ring, next_to_use); 3294 } 3295 3296 return 0; 3297 } 3298 3299 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 3300 { 3301 while (ring->next_to_use != ring->next_to_clean) { 3302 /* When a buffer is not reused, it's memory has been 3303 * freed in hns3_handle_rx_bd or will be freed by 3304 * stack, so only need to unmap the buffer here. 3305 */ 3306 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3307 hns3_unmap_buffer(ring, 3308 &ring->desc_cb[ring->next_to_use]); 3309 ring->desc_cb[ring->next_to_use].dma = 0; 3310 } 3311 3312 ring_ptr_move_fw(ring, next_to_use); 3313 } 3314 } 3315 3316 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h) 3317 { 3318 struct net_device *ndev = h->kinfo.netdev; 3319 struct hns3_nic_priv *priv = netdev_priv(ndev); 3320 struct hns3_enet_ring *ring; 3321 u32 i; 3322 3323 for (i = 0; i < h->kinfo.num_tqps; i++) { 3324 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3325 hns3_force_clear_rx_ring(ring); 3326 } 3327 } 3328 3329 static void hns3_clear_all_ring(struct hnae3_handle *h) 3330 { 3331 struct net_device *ndev = h->kinfo.netdev; 3332 struct hns3_nic_priv *priv = netdev_priv(ndev); 3333 u32 i; 3334 3335 for (i = 0; i < h->kinfo.num_tqps; i++) { 3336 struct netdev_queue *dev_queue; 3337 struct hns3_enet_ring *ring; 3338 3339 ring = priv->ring_data[i].ring; 3340 hns3_clear_tx_ring(ring); 3341 dev_queue = netdev_get_tx_queue(ndev, 3342 priv->ring_data[i].queue_index); 3343 netdev_tx_reset_queue(dev_queue); 3344 3345 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3346 /* Continue to clear other rings even if clearing some 3347 * rings failed. 3348 */ 3349 hns3_clear_rx_ring(ring); 3350 } 3351 } 3352 3353 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 3354 { 3355 struct net_device *ndev = h->kinfo.netdev; 3356 struct hns3_nic_priv *priv = netdev_priv(ndev); 3357 struct hns3_enet_ring *rx_ring; 3358 int i, j; 3359 int ret; 3360 3361 for (i = 0; i < h->kinfo.num_tqps; i++) { 3362 h->ae_algo->ops->reset_queue(h, i); 3363 hns3_init_ring_hw(priv->ring_data[i].ring); 3364 3365 /* We need to clear tx ring here because self test will 3366 * use the ring and will not run down before up 3367 */ 3368 hns3_clear_tx_ring(priv->ring_data[i].ring); 3369 priv->ring_data[i].ring->next_to_clean = 0; 3370 priv->ring_data[i].ring->next_to_use = 0; 3371 3372 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3373 hns3_init_ring_hw(rx_ring); 3374 ret = hns3_clear_rx_ring(rx_ring); 3375 if (ret) 3376 return ret; 3377 3378 /* We can not know the hardware head and tail when this 3379 * function is called in reset flow, so we reuse all desc. 3380 */ 3381 for (j = 0; j < rx_ring->desc_num; j++) 3382 hns3_reuse_buffer(rx_ring, j); 3383 3384 rx_ring->next_to_clean = 0; 3385 rx_ring->next_to_use = 0; 3386 } 3387 3388 return 0; 3389 } 3390 3391 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 3392 { 3393 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3394 struct net_device *ndev = kinfo->netdev; 3395 3396 if (!netif_running(ndev)) 3397 return 0; 3398 3399 return hns3_nic_net_stop(ndev); 3400 } 3401 3402 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 3403 { 3404 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3405 int ret = 0; 3406 3407 if (netif_running(kinfo->netdev)) { 3408 ret = hns3_nic_net_up(kinfo->netdev); 3409 if (ret) { 3410 netdev_err(kinfo->netdev, 3411 "hns net up fail, ret=%d!\n", ret); 3412 return ret; 3413 } 3414 handle->last_reset_time = jiffies; 3415 } 3416 3417 return ret; 3418 } 3419 3420 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 3421 { 3422 struct net_device *netdev = handle->kinfo.netdev; 3423 struct hns3_nic_priv *priv = netdev_priv(netdev); 3424 int ret; 3425 3426 hns3_init_mac_addr(netdev, false); 3427 hns3_nic_set_rx_mode(netdev); 3428 hns3_recover_hw_addr(netdev); 3429 3430 /* Hardware table is only clear when pf resets */ 3431 if (!(handle->flags & HNAE3_SUPPORT_VF)) 3432 hns3_restore_vlan(netdev); 3433 3434 /* Carrier off reporting is important to ethtool even BEFORE open */ 3435 netif_carrier_off(netdev); 3436 3437 ret = hns3_nic_init_vector_data(priv); 3438 if (ret) 3439 return ret; 3440 3441 ret = hns3_init_all_ring(priv); 3442 if (ret) { 3443 hns3_nic_uninit_vector_data(priv); 3444 priv->ring_data = NULL; 3445 } 3446 3447 return ret; 3448 } 3449 3450 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 3451 { 3452 struct net_device *netdev = handle->kinfo.netdev; 3453 struct hns3_nic_priv *priv = netdev_priv(netdev); 3454 int ret; 3455 3456 hns3_force_clear_all_rx_ring(handle); 3457 3458 ret = hns3_nic_uninit_vector_data(priv); 3459 if (ret) { 3460 netdev_err(netdev, "uninit vector error\n"); 3461 return ret; 3462 } 3463 3464 ret = hns3_uninit_all_ring(priv); 3465 if (ret) 3466 netdev_err(netdev, "uninit ring error\n"); 3467 3468 hns3_uninit_mac_addr(netdev); 3469 3470 return ret; 3471 } 3472 3473 static int hns3_reset_notify(struct hnae3_handle *handle, 3474 enum hnae3_reset_notify_type type) 3475 { 3476 int ret = 0; 3477 3478 switch (type) { 3479 case HNAE3_UP_CLIENT: 3480 ret = hns3_reset_notify_up_enet(handle); 3481 break; 3482 case HNAE3_DOWN_CLIENT: 3483 ret = hns3_reset_notify_down_enet(handle); 3484 break; 3485 case HNAE3_INIT_CLIENT: 3486 ret = hns3_reset_notify_init_enet(handle); 3487 break; 3488 case HNAE3_UNINIT_CLIENT: 3489 ret = hns3_reset_notify_uninit_enet(handle); 3490 break; 3491 default: 3492 break; 3493 } 3494 3495 return ret; 3496 } 3497 3498 static void hns3_restore_coal(struct hns3_nic_priv *priv, 3499 struct hns3_enet_coalesce *tx, 3500 struct hns3_enet_coalesce *rx) 3501 { 3502 u16 vector_num = priv->vector_num; 3503 int i; 3504 3505 for (i = 0; i < vector_num; i++) { 3506 memcpy(&priv->tqp_vector[i].tx_group.coal, tx, 3507 sizeof(struct hns3_enet_coalesce)); 3508 memcpy(&priv->tqp_vector[i].rx_group.coal, rx, 3509 sizeof(struct hns3_enet_coalesce)); 3510 } 3511 } 3512 3513 static int hns3_modify_tqp_num(struct net_device *netdev, u16 new_tqp_num, 3514 struct hns3_enet_coalesce *tx, 3515 struct hns3_enet_coalesce *rx) 3516 { 3517 struct hns3_nic_priv *priv = netdev_priv(netdev); 3518 struct hnae3_handle *h = hns3_get_handle(netdev); 3519 int ret; 3520 3521 ret = h->ae_algo->ops->set_channels(h, new_tqp_num); 3522 if (ret) 3523 return ret; 3524 3525 ret = hns3_get_ring_config(priv); 3526 if (ret) 3527 return ret; 3528 3529 ret = hns3_nic_alloc_vector_data(priv); 3530 if (ret) 3531 goto err_alloc_vector; 3532 3533 hns3_restore_coal(priv, tx, rx); 3534 3535 ret = hns3_nic_init_vector_data(priv); 3536 if (ret) 3537 goto err_uninit_vector; 3538 3539 ret = hns3_init_all_ring(priv); 3540 if (ret) 3541 goto err_put_ring; 3542 3543 return 0; 3544 3545 err_put_ring: 3546 hns3_put_ring_config(priv); 3547 err_uninit_vector: 3548 hns3_nic_uninit_vector_data(priv); 3549 err_alloc_vector: 3550 hns3_nic_dealloc_vector_data(priv); 3551 return ret; 3552 } 3553 3554 static int hns3_adjust_tqps_num(u8 num_tc, u32 new_tqp_num) 3555 { 3556 return (new_tqp_num / num_tc) * num_tc; 3557 } 3558 3559 int hns3_set_channels(struct net_device *netdev, 3560 struct ethtool_channels *ch) 3561 { 3562 struct hns3_nic_priv *priv = netdev_priv(netdev); 3563 struct hnae3_handle *h = hns3_get_handle(netdev); 3564 struct hnae3_knic_private_info *kinfo = &h->kinfo; 3565 struct hns3_enet_coalesce tx_coal, rx_coal; 3566 bool if_running = netif_running(netdev); 3567 u32 new_tqp_num = ch->combined_count; 3568 u16 org_tqp_num; 3569 int ret; 3570 3571 if (ch->rx_count || ch->tx_count) 3572 return -EINVAL; 3573 3574 if (new_tqp_num > hns3_get_max_available_channels(h) || 3575 new_tqp_num < kinfo->num_tc) { 3576 dev_err(&netdev->dev, 3577 "Change tqps fail, the tqp range is from %d to %d", 3578 kinfo->num_tc, 3579 hns3_get_max_available_channels(h)); 3580 return -EINVAL; 3581 } 3582 3583 new_tqp_num = hns3_adjust_tqps_num(kinfo->num_tc, new_tqp_num); 3584 if (kinfo->num_tqps == new_tqp_num) 3585 return 0; 3586 3587 if (if_running) 3588 hns3_nic_net_stop(netdev); 3589 3590 ret = hns3_nic_uninit_vector_data(priv); 3591 if (ret) { 3592 dev_err(&netdev->dev, 3593 "Unbind vector with tqp fail, nothing is changed"); 3594 goto open_netdev; 3595 } 3596 3597 /* Changing the tqp num may also change the vector num, 3598 * ethtool only support setting and querying one coal 3599 * configuation for now, so save the vector 0' coal 3600 * configuation here in order to restore it. 3601 */ 3602 memcpy(&tx_coal, &priv->tqp_vector[0].tx_group.coal, 3603 sizeof(struct hns3_enet_coalesce)); 3604 memcpy(&rx_coal, &priv->tqp_vector[0].rx_group.coal, 3605 sizeof(struct hns3_enet_coalesce)); 3606 3607 hns3_nic_dealloc_vector_data(priv); 3608 3609 hns3_uninit_all_ring(priv); 3610 hns3_put_ring_config(priv); 3611 3612 org_tqp_num = h->kinfo.num_tqps; 3613 ret = hns3_modify_tqp_num(netdev, new_tqp_num, &tx_coal, &rx_coal); 3614 if (ret) { 3615 ret = hns3_modify_tqp_num(netdev, org_tqp_num, 3616 &tx_coal, &rx_coal); 3617 if (ret) { 3618 /* If revert to old tqp failed, fatal error occurred */ 3619 dev_err(&netdev->dev, 3620 "Revert to old tqp num fail, ret=%d", ret); 3621 return ret; 3622 } 3623 dev_info(&netdev->dev, 3624 "Change tqp num fail, Revert to old tqp num"); 3625 } 3626 3627 open_netdev: 3628 if (if_running) 3629 hns3_nic_net_open(netdev); 3630 3631 return ret; 3632 } 3633 3634 static const struct hnae3_client_ops client_ops = { 3635 .init_instance = hns3_client_init, 3636 .uninit_instance = hns3_client_uninit, 3637 .link_status_change = hns3_link_status_change, 3638 .setup_tc = hns3_client_setup_tc, 3639 .reset_notify = hns3_reset_notify, 3640 }; 3641 3642 /* hns3_init_module - Driver registration routine 3643 * hns3_init_module is the first routine called when the driver is 3644 * loaded. All it does is register with the PCI subsystem. 3645 */ 3646 static int __init hns3_init_module(void) 3647 { 3648 int ret; 3649 3650 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 3651 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 3652 3653 client.type = HNAE3_CLIENT_KNIC; 3654 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s", 3655 hns3_driver_name); 3656 3657 client.ops = &client_ops; 3658 3659 INIT_LIST_HEAD(&client.node); 3660 3661 ret = hnae3_register_client(&client); 3662 if (ret) 3663 return ret; 3664 3665 ret = pci_register_driver(&hns3_driver); 3666 if (ret) 3667 hnae3_unregister_client(&client); 3668 3669 return ret; 3670 } 3671 module_init(hns3_init_module); 3672 3673 /* hns3_exit_module - Driver exit cleanup routine 3674 * hns3_exit_module is called just before the driver is removed 3675 * from memory. 3676 */ 3677 static void __exit hns3_exit_module(void) 3678 { 3679 pci_unregister_driver(&hns3_driver); 3680 hnae3_unregister_client(&client); 3681 } 3682 module_exit(hns3_exit_module); 3683 3684 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 3685 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3686 MODULE_LICENSE("GPL"); 3687 MODULE_ALIAS("pci:hns-nic"); 3688 MODULE_VERSION(HNS3_MOD_VERSION); 3689