1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #include <linux/if_vlan.h> 8 #include <linux/ip.h> 9 #include <linux/ipv6.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/aer.h> 13 #include <linux/skbuff.h> 14 #include <linux/sctp.h> 15 #include <linux/vermagic.h> 16 #include <net/gre.h> 17 #include <net/pkt_cls.h> 18 #include <net/tcp.h> 19 #include <net/vxlan.h> 20 21 #include "hnae3.h" 22 #include "hns3_enet.h" 23 24 #define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift))) 25 26 static void hns3_clear_all_ring(struct hnae3_handle *h); 27 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h); 28 static void hns3_remove_hw_addr(struct net_device *netdev); 29 30 static const char hns3_driver_name[] = "hns3"; 31 const char hns3_driver_version[] = VERMAGIC_STRING; 32 static const char hns3_driver_string[] = 33 "Hisilicon Ethernet Network Driver for Hip08 Family"; 34 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 35 static struct hnae3_client client; 36 37 /* hns3_pci_tbl - PCI Device ID Table 38 * 39 * Last entry must be all 0s 40 * 41 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 42 * Class, Class Mask, private data (not used) } 43 */ 44 static const struct pci_device_id hns3_pci_tbl[] = { 45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 48 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 50 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 52 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 54 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 55 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 56 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 57 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0}, 58 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 59 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 60 /* required last entry */ 61 {0, } 62 }; 63 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 64 65 static irqreturn_t hns3_irq_handle(int irq, void *vector) 66 { 67 struct hns3_enet_tqp_vector *tqp_vector = vector; 68 69 napi_schedule(&tqp_vector->napi); 70 71 return IRQ_HANDLED; 72 } 73 74 /* This callback function is used to set affinity changes to the irq affinity 75 * masks when the irq_set_affinity_notifier function is used. 76 */ 77 static void hns3_nic_irq_affinity_notify(struct irq_affinity_notify *notify, 78 const cpumask_t *mask) 79 { 80 struct hns3_enet_tqp_vector *tqp_vectors = 81 container_of(notify, struct hns3_enet_tqp_vector, 82 affinity_notify); 83 84 tqp_vectors->affinity_mask = *mask; 85 } 86 87 static void hns3_nic_irq_affinity_release(struct kref *ref) 88 { 89 } 90 91 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 92 { 93 struct hns3_enet_tqp_vector *tqp_vectors; 94 unsigned int i; 95 96 for (i = 0; i < priv->vector_num; i++) { 97 tqp_vectors = &priv->tqp_vector[i]; 98 99 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 100 continue; 101 102 /* clear the affinity notifier and affinity mask */ 103 irq_set_affinity_notifier(tqp_vectors->vector_irq, NULL); 104 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 105 106 /* release the irq resource */ 107 free_irq(tqp_vectors->vector_irq, tqp_vectors); 108 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 109 } 110 } 111 112 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 113 { 114 struct hns3_enet_tqp_vector *tqp_vectors; 115 int txrx_int_idx = 0; 116 int rx_int_idx = 0; 117 int tx_int_idx = 0; 118 unsigned int i; 119 int ret; 120 121 for (i = 0; i < priv->vector_num; i++) { 122 tqp_vectors = &priv->tqp_vector[i]; 123 124 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 125 continue; 126 127 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 128 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 129 "%s-%s-%d", priv->netdev->name, "TxRx", 130 txrx_int_idx++); 131 txrx_int_idx++; 132 } else if (tqp_vectors->rx_group.ring) { 133 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 134 "%s-%s-%d", priv->netdev->name, "Rx", 135 rx_int_idx++); 136 } else if (tqp_vectors->tx_group.ring) { 137 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1, 138 "%s-%s-%d", priv->netdev->name, "Tx", 139 tx_int_idx++); 140 } else { 141 /* Skip this unused q_vector */ 142 continue; 143 } 144 145 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 146 147 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 148 tqp_vectors->name, 149 tqp_vectors); 150 if (ret) { 151 netdev_err(priv->netdev, "request irq(%d) fail\n", 152 tqp_vectors->vector_irq); 153 return ret; 154 } 155 156 tqp_vectors->affinity_notify.notify = 157 hns3_nic_irq_affinity_notify; 158 tqp_vectors->affinity_notify.release = 159 hns3_nic_irq_affinity_release; 160 irq_set_affinity_notifier(tqp_vectors->vector_irq, 161 &tqp_vectors->affinity_notify); 162 irq_set_affinity_hint(tqp_vectors->vector_irq, 163 &tqp_vectors->affinity_mask); 164 165 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 166 } 167 168 return 0; 169 } 170 171 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 172 u32 mask_en) 173 { 174 writel(mask_en, tqp_vector->mask_addr); 175 } 176 177 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector) 178 { 179 napi_enable(&tqp_vector->napi); 180 181 /* enable vector */ 182 hns3_mask_vector_irq(tqp_vector, 1); 183 } 184 185 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector) 186 { 187 /* disable vector */ 188 hns3_mask_vector_irq(tqp_vector, 0); 189 190 disable_irq(tqp_vector->vector_irq); 191 napi_disable(&tqp_vector->napi); 192 } 193 194 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 195 u32 rl_value) 196 { 197 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 198 199 /* this defines the configuration for RL (Interrupt Rate Limiter). 200 * Rl defines rate of interrupts i.e. number of interrupts-per-second 201 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 202 */ 203 204 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable && 205 !tqp_vector->rx_group.coal.gl_adapt_enable) 206 /* According to the hardware, the range of rl_reg is 207 * 0-59 and the unit is 4. 208 */ 209 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 210 211 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 212 } 213 214 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 215 u32 gl_value) 216 { 217 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value); 218 219 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 220 } 221 222 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 223 u32 gl_value) 224 { 225 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value); 226 227 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 228 } 229 230 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector, 231 struct hns3_nic_priv *priv) 232 { 233 /* initialize the configuration for interrupt coalescing. 234 * 1. GL (Interrupt Gap Limiter) 235 * 2. RL (Interrupt Rate Limiter) 236 */ 237 238 /* Default: enable interrupt coalescing self-adaptive and GL */ 239 tqp_vector->tx_group.coal.gl_adapt_enable = 1; 240 tqp_vector->rx_group.coal.gl_adapt_enable = 1; 241 242 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K; 243 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K; 244 245 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW; 246 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW; 247 } 248 249 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 250 struct hns3_nic_priv *priv) 251 { 252 struct hnae3_handle *h = priv->ae_handle; 253 254 hns3_set_vector_coalesce_tx_gl(tqp_vector, 255 tqp_vector->tx_group.coal.int_gl); 256 hns3_set_vector_coalesce_rx_gl(tqp_vector, 257 tqp_vector->rx_group.coal.int_gl); 258 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 259 } 260 261 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 262 { 263 struct hnae3_handle *h = hns3_get_handle(netdev); 264 struct hnae3_knic_private_info *kinfo = &h->kinfo; 265 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc; 266 int i, ret; 267 268 if (kinfo->num_tc <= 1) { 269 netdev_reset_tc(netdev); 270 } else { 271 ret = netdev_set_num_tc(netdev, kinfo->num_tc); 272 if (ret) { 273 netdev_err(netdev, 274 "netdev_set_num_tc fail, ret=%d!\n", ret); 275 return ret; 276 } 277 278 for (i = 0; i < HNAE3_MAX_TC; i++) { 279 if (!kinfo->tc_info[i].enable) 280 continue; 281 282 netdev_set_tc_queue(netdev, 283 kinfo->tc_info[i].tc, 284 kinfo->tc_info[i].tqp_count, 285 kinfo->tc_info[i].tqp_offset); 286 } 287 } 288 289 ret = netif_set_real_num_tx_queues(netdev, queue_size); 290 if (ret) { 291 netdev_err(netdev, 292 "netif_set_real_num_tx_queues fail, ret=%d!\n", 293 ret); 294 return ret; 295 } 296 297 ret = netif_set_real_num_rx_queues(netdev, queue_size); 298 if (ret) { 299 netdev_err(netdev, 300 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 301 return ret; 302 } 303 304 return 0; 305 } 306 307 static u16 hns3_get_max_available_channels(struct hnae3_handle *h) 308 { 309 u16 alloc_tqps, max_rss_size, rss_size; 310 311 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 312 rss_size = alloc_tqps / h->kinfo.num_tc; 313 314 return min_t(u16, rss_size, max_rss_size); 315 } 316 317 static void hns3_tqp_enable(struct hnae3_queue *tqp) 318 { 319 u32 rcb_reg; 320 321 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 322 rcb_reg |= BIT(HNS3_RING_EN_B); 323 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 324 } 325 326 static void hns3_tqp_disable(struct hnae3_queue *tqp) 327 { 328 u32 rcb_reg; 329 330 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 331 rcb_reg &= ~BIT(HNS3_RING_EN_B); 332 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 333 } 334 335 static int hns3_nic_net_up(struct net_device *netdev) 336 { 337 struct hns3_nic_priv *priv = netdev_priv(netdev); 338 struct hnae3_handle *h = priv->ae_handle; 339 int i, j; 340 int ret; 341 342 ret = hns3_nic_reset_all_ring(h); 343 if (ret) 344 return ret; 345 346 /* get irq resource for all vectors */ 347 ret = hns3_nic_init_irq(priv); 348 if (ret) { 349 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret); 350 return ret; 351 } 352 353 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 354 355 /* enable the vectors */ 356 for (i = 0; i < priv->vector_num; i++) 357 hns3_vector_enable(&priv->tqp_vector[i]); 358 359 /* enable rcb */ 360 for (j = 0; j < h->kinfo.num_tqps; j++) 361 hns3_tqp_enable(h->kinfo.tqp[j]); 362 363 /* start the ae_dev */ 364 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 365 if (ret) 366 goto out_start_err; 367 368 return 0; 369 370 out_start_err: 371 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 372 while (j--) 373 hns3_tqp_disable(h->kinfo.tqp[j]); 374 375 for (j = i - 1; j >= 0; j--) 376 hns3_vector_disable(&priv->tqp_vector[j]); 377 378 hns3_nic_uninit_irq(priv); 379 380 return ret; 381 } 382 383 static void hns3_config_xps(struct hns3_nic_priv *priv) 384 { 385 int i; 386 387 for (i = 0; i < priv->vector_num; i++) { 388 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 389 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 390 391 while (ring) { 392 int ret; 393 394 ret = netif_set_xps_queue(priv->netdev, 395 &tqp_vector->affinity_mask, 396 ring->tqp->tqp_index); 397 if (ret) 398 netdev_warn(priv->netdev, 399 "set xps queue failed: %d", ret); 400 401 ring = ring->next; 402 } 403 } 404 } 405 406 static int hns3_nic_net_open(struct net_device *netdev) 407 { 408 struct hns3_nic_priv *priv = netdev_priv(netdev); 409 struct hnae3_handle *h = hns3_get_handle(netdev); 410 struct hnae3_knic_private_info *kinfo; 411 int i, ret; 412 413 if (hns3_nic_resetting(netdev)) 414 return -EBUSY; 415 416 netif_carrier_off(netdev); 417 418 ret = hns3_nic_set_real_num_queue(netdev); 419 if (ret) 420 return ret; 421 422 ret = hns3_nic_net_up(netdev); 423 if (ret) { 424 netdev_err(netdev, 425 "hns net up fail, ret=%d!\n", ret); 426 return ret; 427 } 428 429 kinfo = &h->kinfo; 430 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { 431 netdev_set_prio_tc_map(netdev, i, 432 kinfo->prio_tc[i]); 433 } 434 435 if (h->ae_algo->ops->set_timer_task) 436 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 437 438 hns3_config_xps(priv); 439 return 0; 440 } 441 442 static void hns3_nic_net_down(struct net_device *netdev) 443 { 444 struct hns3_nic_priv *priv = netdev_priv(netdev); 445 struct hnae3_handle *h = hns3_get_handle(netdev); 446 const struct hnae3_ae_ops *ops; 447 int i; 448 449 /* disable vectors */ 450 for (i = 0; i < priv->vector_num; i++) 451 hns3_vector_disable(&priv->tqp_vector[i]); 452 453 /* disable rcb */ 454 for (i = 0; i < h->kinfo.num_tqps; i++) 455 hns3_tqp_disable(h->kinfo.tqp[i]); 456 457 /* stop ae_dev */ 458 ops = priv->ae_handle->ae_algo->ops; 459 if (ops->stop) 460 ops->stop(priv->ae_handle); 461 462 /* free irq resources */ 463 hns3_nic_uninit_irq(priv); 464 465 hns3_clear_all_ring(priv->ae_handle); 466 } 467 468 static int hns3_nic_net_stop(struct net_device *netdev) 469 { 470 struct hns3_nic_priv *priv = netdev_priv(netdev); 471 struct hnae3_handle *h = hns3_get_handle(netdev); 472 473 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 474 return 0; 475 476 if (h->ae_algo->ops->set_timer_task) 477 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 478 479 netif_tx_stop_all_queues(netdev); 480 netif_carrier_off(netdev); 481 482 hns3_nic_net_down(netdev); 483 484 return 0; 485 } 486 487 static int hns3_nic_uc_sync(struct net_device *netdev, 488 const unsigned char *addr) 489 { 490 struct hnae3_handle *h = hns3_get_handle(netdev); 491 492 if (h->ae_algo->ops->add_uc_addr) 493 return h->ae_algo->ops->add_uc_addr(h, addr); 494 495 return 0; 496 } 497 498 static int hns3_nic_uc_unsync(struct net_device *netdev, 499 const unsigned char *addr) 500 { 501 struct hnae3_handle *h = hns3_get_handle(netdev); 502 503 if (h->ae_algo->ops->rm_uc_addr) 504 return h->ae_algo->ops->rm_uc_addr(h, addr); 505 506 return 0; 507 } 508 509 static int hns3_nic_mc_sync(struct net_device *netdev, 510 const unsigned char *addr) 511 { 512 struct hnae3_handle *h = hns3_get_handle(netdev); 513 514 if (h->ae_algo->ops->add_mc_addr) 515 return h->ae_algo->ops->add_mc_addr(h, addr); 516 517 return 0; 518 } 519 520 static int hns3_nic_mc_unsync(struct net_device *netdev, 521 const unsigned char *addr) 522 { 523 struct hnae3_handle *h = hns3_get_handle(netdev); 524 525 if (h->ae_algo->ops->rm_mc_addr) 526 return h->ae_algo->ops->rm_mc_addr(h, addr); 527 528 return 0; 529 } 530 531 static u8 hns3_get_netdev_flags(struct net_device *netdev) 532 { 533 u8 flags = 0; 534 535 if (netdev->flags & IFF_PROMISC) { 536 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 537 } else { 538 flags |= HNAE3_VLAN_FLTR; 539 if (netdev->flags & IFF_ALLMULTI) 540 flags |= HNAE3_USER_MPE; 541 } 542 543 return flags; 544 } 545 546 static void hns3_nic_set_rx_mode(struct net_device *netdev) 547 { 548 struct hnae3_handle *h = hns3_get_handle(netdev); 549 u8 new_flags; 550 int ret; 551 552 new_flags = hns3_get_netdev_flags(netdev); 553 554 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 555 if (ret) { 556 netdev_err(netdev, "sync uc address fail\n"); 557 if (ret == -ENOSPC) 558 new_flags |= HNAE3_OVERFLOW_UPE; 559 } 560 561 if (netdev->flags & IFF_MULTICAST) { 562 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync, 563 hns3_nic_mc_unsync); 564 if (ret) { 565 netdev_err(netdev, "sync mc address fail\n"); 566 if (ret == -ENOSPC) 567 new_flags |= HNAE3_OVERFLOW_MPE; 568 } 569 } 570 571 /* User mode Promisc mode enable and vlan filtering is disabled to 572 * let all packets in. MAC-VLAN Table overflow Promisc enabled and 573 * vlan fitering is enabled 574 */ 575 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR); 576 h->netdev_flags = new_flags; 577 hns3_update_promisc_mode(netdev, new_flags); 578 } 579 580 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags) 581 { 582 struct hns3_nic_priv *priv = netdev_priv(netdev); 583 struct hnae3_handle *h = priv->ae_handle; 584 585 if (h->ae_algo->ops->set_promisc_mode) { 586 return h->ae_algo->ops->set_promisc_mode(h, 587 promisc_flags & HNAE3_UPE, 588 promisc_flags & HNAE3_MPE); 589 } 590 591 return 0; 592 } 593 594 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable) 595 { 596 struct hns3_nic_priv *priv = netdev_priv(netdev); 597 struct hnae3_handle *h = priv->ae_handle; 598 bool last_state; 599 600 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) { 601 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false; 602 if (enable != last_state) { 603 netdev_info(netdev, 604 "%s vlan filter\n", 605 enable ? "enable" : "disable"); 606 h->ae_algo->ops->enable_vlan_filter(h, enable); 607 } 608 } 609 } 610 611 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen, 612 u16 *mss, u32 *type_cs_vlan_tso) 613 { 614 u32 l4_offset, hdr_len; 615 union l3_hdr_info l3; 616 union l4_hdr_info l4; 617 u32 l4_paylen; 618 int ret; 619 620 if (!skb_is_gso(skb)) 621 return 0; 622 623 ret = skb_cow_head(skb, 0); 624 if (unlikely(ret)) 625 return ret; 626 627 l3.hdr = skb_network_header(skb); 628 l4.hdr = skb_transport_header(skb); 629 630 /* Software should clear the IPv4's checksum field when tso is 631 * needed. 632 */ 633 if (l3.v4->version == 4) 634 l3.v4->check = 0; 635 636 /* tunnel packet.*/ 637 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 638 SKB_GSO_GRE_CSUM | 639 SKB_GSO_UDP_TUNNEL | 640 SKB_GSO_UDP_TUNNEL_CSUM)) { 641 if ((!(skb_shinfo(skb)->gso_type & 642 SKB_GSO_PARTIAL)) && 643 (skb_shinfo(skb)->gso_type & 644 SKB_GSO_UDP_TUNNEL_CSUM)) { 645 /* Software should clear the udp's checksum 646 * field when tso is needed. 647 */ 648 l4.udp->check = 0; 649 } 650 /* reset l3&l4 pointers from outer to inner headers */ 651 l3.hdr = skb_inner_network_header(skb); 652 l4.hdr = skb_inner_transport_header(skb); 653 654 /* Software should clear the IPv4's checksum field when 655 * tso is needed. 656 */ 657 if (l3.v4->version == 4) 658 l3.v4->check = 0; 659 } 660 661 /* normal or tunnel packet*/ 662 l4_offset = l4.hdr - skb->data; 663 hdr_len = (l4.tcp->doff << 2) + l4_offset; 664 665 /* remove payload length from inner pseudo checksum when tso*/ 666 l4_paylen = skb->len - l4_offset; 667 csum_replace_by_diff(&l4.tcp->check, 668 (__force __wsum)htonl(l4_paylen)); 669 670 /* find the txbd field values */ 671 *paylen = skb->len - hdr_len; 672 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 673 674 /* get MSS for TSO */ 675 *mss = skb_shinfo(skb)->gso_size; 676 677 return 0; 678 } 679 680 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 681 u8 *il4_proto) 682 { 683 union l3_hdr_info l3; 684 unsigned char *l4_hdr; 685 unsigned char *exthdr; 686 u8 l4_proto_tmp; 687 __be16 frag_off; 688 689 /* find outer header point */ 690 l3.hdr = skb_network_header(skb); 691 l4_hdr = skb_transport_header(skb); 692 693 if (skb->protocol == htons(ETH_P_IPV6)) { 694 exthdr = l3.hdr + sizeof(*l3.v6); 695 l4_proto_tmp = l3.v6->nexthdr; 696 if (l4_hdr != exthdr) 697 ipv6_skip_exthdr(skb, exthdr - skb->data, 698 &l4_proto_tmp, &frag_off); 699 } else if (skb->protocol == htons(ETH_P_IP)) { 700 l4_proto_tmp = l3.v4->protocol; 701 } else { 702 return -EINVAL; 703 } 704 705 *ol4_proto = l4_proto_tmp; 706 707 /* tunnel packet */ 708 if (!skb->encapsulation) { 709 *il4_proto = 0; 710 return 0; 711 } 712 713 /* find inner header point */ 714 l3.hdr = skb_inner_network_header(skb); 715 l4_hdr = skb_inner_transport_header(skb); 716 717 if (l3.v6->version == 6) { 718 exthdr = l3.hdr + sizeof(*l3.v6); 719 l4_proto_tmp = l3.v6->nexthdr; 720 if (l4_hdr != exthdr) 721 ipv6_skip_exthdr(skb, exthdr - skb->data, 722 &l4_proto_tmp, &frag_off); 723 } else if (l3.v4->version == 4) { 724 l4_proto_tmp = l3.v4->protocol; 725 } 726 727 *il4_proto = l4_proto_tmp; 728 729 return 0; 730 } 731 732 static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto, 733 u8 il4_proto, u32 *type_cs_vlan_tso, 734 u32 *ol_type_vlan_len_msec) 735 { 736 union l3_hdr_info l3; 737 union l4_hdr_info l4; 738 unsigned char *l2_hdr; 739 u8 l4_proto = ol4_proto; 740 u32 ol2_len; 741 u32 ol3_len; 742 u32 ol4_len; 743 u32 l2_len; 744 u32 l3_len; 745 746 l3.hdr = skb_network_header(skb); 747 l4.hdr = skb_transport_header(skb); 748 749 /* compute L2 header size for normal packet, defined in 2 Bytes */ 750 l2_len = l3.hdr - skb->data; 751 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 752 753 /* tunnel packet*/ 754 if (skb->encapsulation) { 755 /* compute OL2 header size, defined in 2 Bytes */ 756 ol2_len = l2_len; 757 hns3_set_field(*ol_type_vlan_len_msec, 758 HNS3_TXD_L2LEN_S, ol2_len >> 1); 759 760 /* compute OL3 header size, defined in 4 Bytes */ 761 ol3_len = l4.hdr - l3.hdr; 762 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, 763 ol3_len >> 2); 764 765 /* MAC in UDP, MAC in GRE (0x6558)*/ 766 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) { 767 /* switch MAC header ptr from outer to inner header.*/ 768 l2_hdr = skb_inner_mac_header(skb); 769 770 /* compute OL4 header size, defined in 4 Bytes. */ 771 ol4_len = l2_hdr - l4.hdr; 772 hns3_set_field(*ol_type_vlan_len_msec, 773 HNS3_TXD_L4LEN_S, ol4_len >> 2); 774 775 /* switch IP header ptr from outer to inner header */ 776 l3.hdr = skb_inner_network_header(skb); 777 778 /* compute inner l2 header size, defined in 2 Bytes. */ 779 l2_len = l3.hdr - l2_hdr; 780 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, 781 l2_len >> 1); 782 } else { 783 /* skb packet types not supported by hardware, 784 * txbd len fild doesn't be filled. 785 */ 786 return; 787 } 788 789 /* switch L4 header pointer from outer to inner */ 790 l4.hdr = skb_inner_transport_header(skb); 791 792 l4_proto = il4_proto; 793 } 794 795 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 796 l3_len = l4.hdr - l3.hdr; 797 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 798 799 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 800 switch (l4_proto) { 801 case IPPROTO_TCP: 802 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 803 l4.tcp->doff); 804 break; 805 case IPPROTO_SCTP: 806 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 807 (sizeof(struct sctphdr) >> 2)); 808 break; 809 case IPPROTO_UDP: 810 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 811 (sizeof(struct udphdr) >> 2)); 812 break; 813 default: 814 /* skb packet types not supported by hardware, 815 * txbd len fild doesn't be filled. 816 */ 817 return; 818 } 819 } 820 821 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 822 * and it is udp packet, which has a dest port as the IANA assigned. 823 * the hardware is expected to do the checksum offload, but the 824 * hardware will not do the checksum offload when udp dest port is 825 * 4789. 826 */ 827 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 828 { 829 #define IANA_VXLAN_PORT 4789 830 union l4_hdr_info l4; 831 832 l4.hdr = skb_transport_header(skb); 833 834 if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT))) 835 return false; 836 837 skb_checksum_help(skb); 838 839 return true; 840 } 841 842 static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto, 843 u8 il4_proto, u32 *type_cs_vlan_tso, 844 u32 *ol_type_vlan_len_msec) 845 { 846 union l3_hdr_info l3; 847 u32 l4_proto = ol4_proto; 848 849 l3.hdr = skb_network_header(skb); 850 851 /* define OL3 type and tunnel type(OL4).*/ 852 if (skb->encapsulation) { 853 /* define outer network header type.*/ 854 if (skb->protocol == htons(ETH_P_IP)) { 855 if (skb_is_gso(skb)) 856 hns3_set_field(*ol_type_vlan_len_msec, 857 HNS3_TXD_OL3T_S, 858 HNS3_OL3T_IPV4_CSUM); 859 else 860 hns3_set_field(*ol_type_vlan_len_msec, 861 HNS3_TXD_OL3T_S, 862 HNS3_OL3T_IPV4_NO_CSUM); 863 864 } else if (skb->protocol == htons(ETH_P_IPV6)) { 865 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 866 HNS3_OL3T_IPV6); 867 } 868 869 /* define tunnel type(OL4).*/ 870 switch (l4_proto) { 871 case IPPROTO_UDP: 872 hns3_set_field(*ol_type_vlan_len_msec, 873 HNS3_TXD_TUNTYPE_S, 874 HNS3_TUN_MAC_IN_UDP); 875 break; 876 case IPPROTO_GRE: 877 hns3_set_field(*ol_type_vlan_len_msec, 878 HNS3_TXD_TUNTYPE_S, 879 HNS3_TUN_NVGRE); 880 break; 881 default: 882 /* drop the skb tunnel packet if hardware don't support, 883 * because hardware can't calculate csum when TSO. 884 */ 885 if (skb_is_gso(skb)) 886 return -EDOM; 887 888 /* the stack computes the IP header already, 889 * driver calculate l4 checksum when not TSO. 890 */ 891 skb_checksum_help(skb); 892 return 0; 893 } 894 895 l3.hdr = skb_inner_network_header(skb); 896 l4_proto = il4_proto; 897 } 898 899 if (l3.v4->version == 4) { 900 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 901 HNS3_L3T_IPV4); 902 903 /* the stack computes the IP header already, the only time we 904 * need the hardware to recompute it is in the case of TSO. 905 */ 906 if (skb_is_gso(skb)) 907 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 908 } else if (l3.v6->version == 6) { 909 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 910 HNS3_L3T_IPV6); 911 } 912 913 switch (l4_proto) { 914 case IPPROTO_TCP: 915 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 916 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 917 HNS3_L4T_TCP); 918 break; 919 case IPPROTO_UDP: 920 if (hns3_tunnel_csum_bug(skb)) 921 break; 922 923 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 924 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 925 HNS3_L4T_UDP); 926 break; 927 case IPPROTO_SCTP: 928 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 929 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 930 HNS3_L4T_SCTP); 931 break; 932 default: 933 /* drop the skb tunnel packet if hardware don't support, 934 * because hardware can't calculate csum when TSO. 935 */ 936 if (skb_is_gso(skb)) 937 return -EDOM; 938 939 /* the stack computes the IP header already, 940 * driver calculate l4 checksum when not TSO. 941 */ 942 skb_checksum_help(skb); 943 return 0; 944 } 945 946 return 0; 947 } 948 949 static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end) 950 { 951 /* Config bd buffer end */ 952 hns3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end); 953 hns3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1); 954 } 955 956 static int hns3_fill_desc_vtags(struct sk_buff *skb, 957 struct hns3_enet_ring *tx_ring, 958 u32 *inner_vlan_flag, 959 u32 *out_vlan_flag, 960 u16 *inner_vtag, 961 u16 *out_vtag) 962 { 963 #define HNS3_TX_VLAN_PRIO_SHIFT 13 964 965 if (skb->protocol == htons(ETH_P_8021Q) && 966 !(tx_ring->tqp->handle->kinfo.netdev->features & 967 NETIF_F_HW_VLAN_CTAG_TX)) { 968 /* When HW VLAN acceleration is turned off, and the stack 969 * sets the protocol to 802.1q, the driver just need to 970 * set the protocol to the encapsulated ethertype. 971 */ 972 skb->protocol = vlan_get_protocol(skb); 973 return 0; 974 } 975 976 if (skb_vlan_tag_present(skb)) { 977 u16 vlan_tag; 978 979 vlan_tag = skb_vlan_tag_get(skb); 980 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT; 981 982 /* Based on hw strategy, use out_vtag in two layer tag case, 983 * and use inner_vtag in one tag case. 984 */ 985 if (skb->protocol == htons(ETH_P_8021Q)) { 986 hns3_set_field(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1); 987 *out_vtag = vlan_tag; 988 } else { 989 hns3_set_field(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1); 990 *inner_vtag = vlan_tag; 991 } 992 } else if (skb->protocol == htons(ETH_P_8021Q)) { 993 struct vlan_ethhdr *vhdr; 994 int rc; 995 996 rc = skb_cow_head(skb, 0); 997 if (unlikely(rc < 0)) 998 return rc; 999 vhdr = (struct vlan_ethhdr *)skb->data; 1000 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7) 1001 << HNS3_TX_VLAN_PRIO_SHIFT); 1002 } 1003 1004 skb->protocol = vlan_get_protocol(skb); 1005 return 0; 1006 } 1007 1008 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv, 1009 int size, int frag_end, enum hns_desc_type type) 1010 { 1011 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1012 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1013 struct device *dev = ring_to_dev(ring); 1014 u16 bdtp_fe_sc_vld_ra_ri = 0; 1015 struct skb_frag_struct *frag; 1016 unsigned int frag_buf_num; 1017 int k, sizeoflast; 1018 dma_addr_t dma; 1019 1020 if (type == DESC_TYPE_SKB) { 1021 struct sk_buff *skb = (struct sk_buff *)priv; 1022 u32 ol_type_vlan_len_msec = 0; 1023 u32 type_cs_vlan_tso = 0; 1024 u32 paylen = skb->len; 1025 u16 inner_vtag = 0; 1026 u16 out_vtag = 0; 1027 u16 mss = 0; 1028 int ret; 1029 1030 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso, 1031 &ol_type_vlan_len_msec, 1032 &inner_vtag, &out_vtag); 1033 if (unlikely(ret)) 1034 return ret; 1035 1036 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1037 u8 ol4_proto, il4_proto; 1038 1039 skb_reset_mac_len(skb); 1040 1041 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1042 if (unlikely(ret)) 1043 return ret; 1044 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto, 1045 &type_cs_vlan_tso, 1046 &ol_type_vlan_len_msec); 1047 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto, 1048 &type_cs_vlan_tso, 1049 &ol_type_vlan_len_msec); 1050 if (unlikely(ret)) 1051 return ret; 1052 1053 ret = hns3_set_tso(skb, &paylen, &mss, 1054 &type_cs_vlan_tso); 1055 if (unlikely(ret)) 1056 return ret; 1057 } 1058 1059 /* Set txbd */ 1060 desc->tx.ol_type_vlan_len_msec = 1061 cpu_to_le32(ol_type_vlan_len_msec); 1062 desc->tx.type_cs_vlan_tso_len = 1063 cpu_to_le32(type_cs_vlan_tso); 1064 desc->tx.paylen = cpu_to_le32(paylen); 1065 desc->tx.mss = cpu_to_le16(mss); 1066 desc->tx.vlan_tag = cpu_to_le16(inner_vtag); 1067 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag); 1068 1069 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1070 } else { 1071 frag = (struct skb_frag_struct *)priv; 1072 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1073 } 1074 1075 if (unlikely(dma_mapping_error(ring->dev, dma))) { 1076 ring->stats.sw_err_cnt++; 1077 return -ENOMEM; 1078 } 1079 1080 desc_cb->length = size; 1081 1082 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) >> HNS3_MAX_BD_SIZE_OFFSET; 1083 sizeoflast = size & HNS3_TX_LAST_SIZE_M; 1084 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1085 1086 /* When frag size is bigger than hardware limit, split this frag */ 1087 for (k = 0; k < frag_buf_num; k++) { 1088 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */ 1089 desc_cb->priv = priv; 1090 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k; 1091 desc_cb->type = (type == DESC_TYPE_SKB && !k) ? 1092 DESC_TYPE_SKB : DESC_TYPE_PAGE; 1093 1094 /* now, fill the descriptor */ 1095 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1096 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1097 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1098 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri, 1099 frag_end && (k == frag_buf_num - 1) ? 1100 1 : 0); 1101 desc->tx.bdtp_fe_sc_vld_ra_ri = 1102 cpu_to_le16(bdtp_fe_sc_vld_ra_ri); 1103 1104 /* move ring pointer to next.*/ 1105 ring_ptr_move_fw(ring, next_to_use); 1106 1107 desc_cb = &ring->desc_cb[ring->next_to_use]; 1108 desc = &ring->desc[ring->next_to_use]; 1109 } 1110 1111 return 0; 1112 } 1113 1114 static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum, 1115 struct hns3_enet_ring *ring) 1116 { 1117 struct sk_buff *skb = *out_skb; 1118 struct sk_buff *new_skb = NULL; 1119 struct skb_frag_struct *frag; 1120 int bdnum_for_frag; 1121 int frag_num; 1122 int buf_num; 1123 int size; 1124 int i; 1125 1126 size = skb_headlen(skb); 1127 buf_num = (size + HNS3_MAX_BD_SIZE - 1) >> HNS3_MAX_BD_SIZE_OFFSET; 1128 1129 frag_num = skb_shinfo(skb)->nr_frags; 1130 for (i = 0; i < frag_num; i++) { 1131 frag = &skb_shinfo(skb)->frags[i]; 1132 size = skb_frag_size(frag); 1133 bdnum_for_frag = (size + HNS3_MAX_BD_SIZE - 1) >> 1134 HNS3_MAX_BD_SIZE_OFFSET; 1135 if (unlikely(bdnum_for_frag > HNS3_MAX_BD_PER_FRAG)) 1136 return -ENOMEM; 1137 1138 buf_num += bdnum_for_frag; 1139 } 1140 1141 if (unlikely(buf_num > HNS3_MAX_BD_PER_FRAG)) { 1142 buf_num = (skb->len + HNS3_MAX_BD_SIZE - 1) >> 1143 HNS3_MAX_BD_SIZE_OFFSET; 1144 if (ring_space(ring) < buf_num) 1145 return -EBUSY; 1146 /* manual split the send packet */ 1147 new_skb = skb_copy(skb, GFP_ATOMIC); 1148 if (!new_skb) 1149 return -ENOMEM; 1150 dev_kfree_skb_any(skb); 1151 *out_skb = new_skb; 1152 } 1153 1154 if (unlikely(ring_space(ring) < buf_num)) 1155 return -EBUSY; 1156 1157 *bnum = buf_num; 1158 return 0; 1159 } 1160 1161 static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum, 1162 struct hns3_enet_ring *ring) 1163 { 1164 struct sk_buff *skb = *out_skb; 1165 struct sk_buff *new_skb = NULL; 1166 int buf_num; 1167 1168 /* No. of segments (plus a header) */ 1169 buf_num = skb_shinfo(skb)->nr_frags + 1; 1170 1171 if (unlikely(buf_num > HNS3_MAX_BD_PER_FRAG)) { 1172 buf_num = (skb->len + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE; 1173 if (ring_space(ring) < buf_num) 1174 return -EBUSY; 1175 /* manual split the send packet */ 1176 new_skb = skb_copy(skb, GFP_ATOMIC); 1177 if (!new_skb) 1178 return -ENOMEM; 1179 dev_kfree_skb_any(skb); 1180 *out_skb = new_skb; 1181 } 1182 1183 if (unlikely(ring_space(ring) < buf_num)) 1184 return -EBUSY; 1185 1186 *bnum = buf_num; 1187 1188 return 0; 1189 } 1190 1191 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1192 { 1193 struct device *dev = ring_to_dev(ring); 1194 unsigned int i; 1195 1196 for (i = 0; i < ring->desc_num; i++) { 1197 /* check if this is where we started */ 1198 if (ring->next_to_use == next_to_use_orig) 1199 break; 1200 1201 /* unmap the descriptor dma address */ 1202 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB) 1203 dma_unmap_single(dev, 1204 ring->desc_cb[ring->next_to_use].dma, 1205 ring->desc_cb[ring->next_to_use].length, 1206 DMA_TO_DEVICE); 1207 else if (ring->desc_cb[ring->next_to_use].length) 1208 dma_unmap_page(dev, 1209 ring->desc_cb[ring->next_to_use].dma, 1210 ring->desc_cb[ring->next_to_use].length, 1211 DMA_TO_DEVICE); 1212 1213 ring->desc_cb[ring->next_to_use].length = 0; 1214 1215 /* rollback one */ 1216 ring_ptr_move_bw(ring, next_to_use); 1217 } 1218 } 1219 1220 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 1221 { 1222 struct hns3_nic_priv *priv = netdev_priv(netdev); 1223 struct hns3_nic_ring_data *ring_data = 1224 &tx_ring_data(priv, skb->queue_mapping); 1225 struct hns3_enet_ring *ring = ring_data->ring; 1226 struct netdev_queue *dev_queue; 1227 struct skb_frag_struct *frag; 1228 int next_to_use_head; 1229 int next_to_use_frag; 1230 int buf_num; 1231 int seg_num; 1232 int size; 1233 int ret; 1234 int i; 1235 1236 /* Prefetch the data used later */ 1237 prefetch(skb->data); 1238 1239 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) { 1240 case -EBUSY: 1241 u64_stats_update_begin(&ring->syncp); 1242 ring->stats.tx_busy++; 1243 u64_stats_update_end(&ring->syncp); 1244 1245 goto out_net_tx_busy; 1246 case -ENOMEM: 1247 u64_stats_update_begin(&ring->syncp); 1248 ring->stats.sw_err_cnt++; 1249 u64_stats_update_end(&ring->syncp); 1250 netdev_err(netdev, "no memory to xmit!\n"); 1251 1252 goto out_err_tx_ok; 1253 default: 1254 break; 1255 } 1256 1257 /* No. of segments (plus a header) */ 1258 seg_num = skb_shinfo(skb)->nr_frags + 1; 1259 /* Fill the first part */ 1260 size = skb_headlen(skb); 1261 1262 next_to_use_head = ring->next_to_use; 1263 1264 ret = hns3_fill_desc(ring, skb, size, seg_num == 1 ? 1 : 0, 1265 DESC_TYPE_SKB); 1266 if (unlikely(ret)) 1267 goto head_fill_err; 1268 1269 next_to_use_frag = ring->next_to_use; 1270 /* Fill the fragments */ 1271 for (i = 1; i < seg_num; i++) { 1272 frag = &skb_shinfo(skb)->frags[i - 1]; 1273 size = skb_frag_size(frag); 1274 1275 ret = hns3_fill_desc(ring, frag, size, 1276 seg_num - 1 == i ? 1 : 0, 1277 DESC_TYPE_PAGE); 1278 1279 if (unlikely(ret)) 1280 goto frag_fill_err; 1281 } 1282 1283 /* Complete translate all packets */ 1284 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index); 1285 netdev_tx_sent_queue(dev_queue, skb->len); 1286 1287 wmb(); /* Commit all data before submit */ 1288 1289 hnae3_queue_xmit(ring->tqp, buf_num); 1290 1291 return NETDEV_TX_OK; 1292 1293 frag_fill_err: 1294 hns3_clear_desc(ring, next_to_use_frag); 1295 1296 head_fill_err: 1297 hns3_clear_desc(ring, next_to_use_head); 1298 1299 out_err_tx_ok: 1300 dev_kfree_skb_any(skb); 1301 return NETDEV_TX_OK; 1302 1303 out_net_tx_busy: 1304 netif_stop_subqueue(netdev, ring_data->queue_index); 1305 smp_mb(); /* Commit all data before submit */ 1306 1307 return NETDEV_TX_BUSY; 1308 } 1309 1310 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 1311 { 1312 struct hnae3_handle *h = hns3_get_handle(netdev); 1313 struct sockaddr *mac_addr = p; 1314 int ret; 1315 1316 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 1317 return -EADDRNOTAVAIL; 1318 1319 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 1320 netdev_info(netdev, "already using mac address %pM\n", 1321 mac_addr->sa_data); 1322 return 0; 1323 } 1324 1325 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 1326 if (ret) { 1327 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 1328 return ret; 1329 } 1330 1331 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data); 1332 1333 return 0; 1334 } 1335 1336 static int hns3_nic_do_ioctl(struct net_device *netdev, 1337 struct ifreq *ifr, int cmd) 1338 { 1339 struct hnae3_handle *h = hns3_get_handle(netdev); 1340 1341 if (!netif_running(netdev)) 1342 return -EINVAL; 1343 1344 if (!h->ae_algo->ops->do_ioctl) 1345 return -EOPNOTSUPP; 1346 1347 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 1348 } 1349 1350 static int hns3_nic_set_features(struct net_device *netdev, 1351 netdev_features_t features) 1352 { 1353 netdev_features_t changed = netdev->features ^ features; 1354 struct hns3_nic_priv *priv = netdev_priv(netdev); 1355 struct hnae3_handle *h = priv->ae_handle; 1356 bool enable; 1357 int ret; 1358 1359 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) { 1360 if (features & (NETIF_F_TSO | NETIF_F_TSO6)) 1361 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 1362 else 1363 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 1364 } 1365 1366 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 1367 enable = !!(features & NETIF_F_GRO_HW); 1368 ret = h->ae_algo->ops->set_gro_en(h, enable); 1369 if (ret) 1370 return ret; 1371 } 1372 1373 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 1374 h->ae_algo->ops->enable_vlan_filter) { 1375 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER); 1376 h->ae_algo->ops->enable_vlan_filter(h, enable); 1377 } 1378 1379 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 1380 h->ae_algo->ops->enable_hw_strip_rxvtag) { 1381 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 1382 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 1383 if (ret) 1384 return ret; 1385 } 1386 1387 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 1388 enable = !!(features & NETIF_F_NTUPLE); 1389 h->ae_algo->ops->enable_fd(h, enable); 1390 } 1391 1392 netdev->features = features; 1393 return 0; 1394 } 1395 1396 static void hns3_nic_get_stats64(struct net_device *netdev, 1397 struct rtnl_link_stats64 *stats) 1398 { 1399 struct hns3_nic_priv *priv = netdev_priv(netdev); 1400 int queue_num = priv->ae_handle->kinfo.num_tqps; 1401 struct hnae3_handle *handle = priv->ae_handle; 1402 struct hns3_enet_ring *ring; 1403 u64 rx_length_errors = 0; 1404 u64 rx_crc_errors = 0; 1405 u64 rx_multicast = 0; 1406 unsigned int start; 1407 u64 tx_errors = 0; 1408 u64 rx_errors = 0; 1409 unsigned int idx; 1410 u64 tx_bytes = 0; 1411 u64 rx_bytes = 0; 1412 u64 tx_pkts = 0; 1413 u64 rx_pkts = 0; 1414 u64 tx_drop = 0; 1415 u64 rx_drop = 0; 1416 1417 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 1418 return; 1419 1420 handle->ae_algo->ops->update_stats(handle, &netdev->stats); 1421 1422 for (idx = 0; idx < queue_num; idx++) { 1423 /* fetch the tx stats */ 1424 ring = priv->ring_data[idx].ring; 1425 do { 1426 start = u64_stats_fetch_begin_irq(&ring->syncp); 1427 tx_bytes += ring->stats.tx_bytes; 1428 tx_pkts += ring->stats.tx_pkts; 1429 tx_drop += ring->stats.sw_err_cnt; 1430 tx_errors += ring->stats.sw_err_cnt; 1431 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1432 1433 /* fetch the rx stats */ 1434 ring = priv->ring_data[idx + queue_num].ring; 1435 do { 1436 start = u64_stats_fetch_begin_irq(&ring->syncp); 1437 rx_bytes += ring->stats.rx_bytes; 1438 rx_pkts += ring->stats.rx_pkts; 1439 rx_drop += ring->stats.non_vld_descs; 1440 rx_drop += ring->stats.l2_err; 1441 rx_errors += ring->stats.non_vld_descs; 1442 rx_errors += ring->stats.l2_err; 1443 rx_crc_errors += ring->stats.l2_err; 1444 rx_crc_errors += ring->stats.l3l4_csum_err; 1445 rx_multicast += ring->stats.rx_multicast; 1446 rx_length_errors += ring->stats.err_pkt_len; 1447 } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); 1448 } 1449 1450 stats->tx_bytes = tx_bytes; 1451 stats->tx_packets = tx_pkts; 1452 stats->rx_bytes = rx_bytes; 1453 stats->rx_packets = rx_pkts; 1454 1455 stats->rx_errors = rx_errors; 1456 stats->multicast = rx_multicast; 1457 stats->rx_length_errors = rx_length_errors; 1458 stats->rx_crc_errors = rx_crc_errors; 1459 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 1460 1461 stats->tx_errors = tx_errors; 1462 stats->rx_dropped = rx_drop; 1463 stats->tx_dropped = tx_drop; 1464 stats->collisions = netdev->stats.collisions; 1465 stats->rx_over_errors = netdev->stats.rx_over_errors; 1466 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 1467 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 1468 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 1469 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 1470 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 1471 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 1472 stats->tx_window_errors = netdev->stats.tx_window_errors; 1473 stats->rx_compressed = netdev->stats.rx_compressed; 1474 stats->tx_compressed = netdev->stats.tx_compressed; 1475 } 1476 1477 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 1478 { 1479 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 1480 struct hnae3_handle *h = hns3_get_handle(netdev); 1481 struct hnae3_knic_private_info *kinfo = &h->kinfo; 1482 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map; 1483 u8 tc = mqprio_qopt->qopt.num_tc; 1484 u16 mode = mqprio_qopt->mode; 1485 u8 hw = mqprio_qopt->qopt.hw; 1486 1487 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 1488 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 1489 return -EOPNOTSUPP; 1490 1491 if (tc > HNAE3_MAX_TC) 1492 return -EINVAL; 1493 1494 if (!netdev) 1495 return -EINVAL; 1496 1497 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 1498 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP; 1499 } 1500 1501 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 1502 void *type_data) 1503 { 1504 if (type != TC_SETUP_QDISC_MQPRIO) 1505 return -EOPNOTSUPP; 1506 1507 return hns3_setup_tc(dev, type_data); 1508 } 1509 1510 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 1511 __be16 proto, u16 vid) 1512 { 1513 struct hnae3_handle *h = hns3_get_handle(netdev); 1514 struct hns3_nic_priv *priv = netdev_priv(netdev); 1515 int ret = -EIO; 1516 1517 if (h->ae_algo->ops->set_vlan_filter) 1518 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 1519 1520 if (!ret) 1521 set_bit(vid, priv->active_vlans); 1522 1523 return ret; 1524 } 1525 1526 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 1527 __be16 proto, u16 vid) 1528 { 1529 struct hnae3_handle *h = hns3_get_handle(netdev); 1530 struct hns3_nic_priv *priv = netdev_priv(netdev); 1531 int ret = -EIO; 1532 1533 if (h->ae_algo->ops->set_vlan_filter) 1534 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 1535 1536 if (!ret) 1537 clear_bit(vid, priv->active_vlans); 1538 1539 return ret; 1540 } 1541 1542 static int hns3_restore_vlan(struct net_device *netdev) 1543 { 1544 struct hns3_nic_priv *priv = netdev_priv(netdev); 1545 int ret = 0; 1546 u16 vid; 1547 1548 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 1549 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); 1550 if (ret) { 1551 netdev_err(netdev, "Restore vlan: %d filter, ret:%d\n", 1552 vid, ret); 1553 return ret; 1554 } 1555 } 1556 1557 return ret; 1558 } 1559 1560 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1561 u8 qos, __be16 vlan_proto) 1562 { 1563 struct hnae3_handle *h = hns3_get_handle(netdev); 1564 int ret = -EIO; 1565 1566 if (h->ae_algo->ops->set_vf_vlan_filter) 1567 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 1568 qos, vlan_proto); 1569 1570 return ret; 1571 } 1572 1573 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 1574 { 1575 struct hnae3_handle *h = hns3_get_handle(netdev); 1576 int ret; 1577 1578 if (!h->ae_algo->ops->set_mtu) 1579 return -EOPNOTSUPP; 1580 1581 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 1582 if (ret) 1583 netdev_err(netdev, "failed to change MTU in hardware %d\n", 1584 ret); 1585 else 1586 netdev->mtu = new_mtu; 1587 1588 return ret; 1589 } 1590 1591 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 1592 { 1593 struct hns3_nic_priv *priv = netdev_priv(ndev); 1594 struct hns3_enet_ring *tx_ring = NULL; 1595 int timeout_queue = 0; 1596 int hw_head, hw_tail; 1597 int i; 1598 1599 /* Find the stopped queue the same way the stack does */ 1600 for (i = 0; i < ndev->real_num_tx_queues; i++) { 1601 struct netdev_queue *q; 1602 unsigned long trans_start; 1603 1604 q = netdev_get_tx_queue(ndev, i); 1605 trans_start = q->trans_start; 1606 if (netif_xmit_stopped(q) && 1607 time_after(jiffies, 1608 (trans_start + ndev->watchdog_timeo))) { 1609 timeout_queue = i; 1610 break; 1611 } 1612 } 1613 1614 if (i == ndev->num_tx_queues) { 1615 netdev_info(ndev, 1616 "no netdev TX timeout queue found, timeout count: %llu\n", 1617 priv->tx_timeout_count); 1618 return false; 1619 } 1620 1621 tx_ring = priv->ring_data[timeout_queue].ring; 1622 1623 hw_head = readl_relaxed(tx_ring->tqp->io_base + 1624 HNS3_RING_TX_RING_HEAD_REG); 1625 hw_tail = readl_relaxed(tx_ring->tqp->io_base + 1626 HNS3_RING_TX_RING_TAIL_REG); 1627 netdev_info(ndev, 1628 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n", 1629 priv->tx_timeout_count, 1630 timeout_queue, 1631 tx_ring->next_to_use, 1632 tx_ring->next_to_clean, 1633 hw_head, 1634 hw_tail, 1635 readl(tx_ring->tqp_vector->mask_addr)); 1636 1637 return true; 1638 } 1639 1640 static void hns3_nic_net_timeout(struct net_device *ndev) 1641 { 1642 struct hns3_nic_priv *priv = netdev_priv(ndev); 1643 struct hnae3_handle *h = priv->ae_handle; 1644 1645 if (!hns3_get_tx_timeo_queue_info(ndev)) 1646 return; 1647 1648 priv->tx_timeout_count++; 1649 1650 /* request the reset, and let the hclge to determine 1651 * which reset level should be done 1652 */ 1653 if (h->ae_algo->ops->reset_event) 1654 h->ae_algo->ops->reset_event(h->pdev, h); 1655 } 1656 1657 static const struct net_device_ops hns3_nic_netdev_ops = { 1658 .ndo_open = hns3_nic_net_open, 1659 .ndo_stop = hns3_nic_net_stop, 1660 .ndo_start_xmit = hns3_nic_net_xmit, 1661 .ndo_tx_timeout = hns3_nic_net_timeout, 1662 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 1663 .ndo_do_ioctl = hns3_nic_do_ioctl, 1664 .ndo_change_mtu = hns3_nic_change_mtu, 1665 .ndo_set_features = hns3_nic_set_features, 1666 .ndo_get_stats64 = hns3_nic_get_stats64, 1667 .ndo_setup_tc = hns3_nic_setup_tc, 1668 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 1669 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 1670 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 1671 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 1672 }; 1673 1674 static bool hns3_is_phys_func(struct pci_dev *pdev) 1675 { 1676 u32 dev_id = pdev->device; 1677 1678 switch (dev_id) { 1679 case HNAE3_DEV_ID_GE: 1680 case HNAE3_DEV_ID_25GE: 1681 case HNAE3_DEV_ID_25GE_RDMA: 1682 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 1683 case HNAE3_DEV_ID_50GE_RDMA: 1684 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 1685 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 1686 return true; 1687 case HNAE3_DEV_ID_100G_VF: 1688 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF: 1689 return false; 1690 default: 1691 dev_warn(&pdev->dev, "un-recognized pci device-id %d", 1692 dev_id); 1693 } 1694 1695 return false; 1696 } 1697 1698 static void hns3_disable_sriov(struct pci_dev *pdev) 1699 { 1700 /* If our VFs are assigned we cannot shut down SR-IOV 1701 * without causing issues, so just leave the hardware 1702 * available but disabled 1703 */ 1704 if (pci_vfs_assigned(pdev)) { 1705 dev_warn(&pdev->dev, 1706 "disabling driver while VFs are assigned\n"); 1707 return; 1708 } 1709 1710 pci_disable_sriov(pdev); 1711 } 1712 1713 static void hns3_get_dev_capability(struct pci_dev *pdev, 1714 struct hnae3_ae_dev *ae_dev) 1715 { 1716 if (pdev->revision >= 0x21) { 1717 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1); 1718 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1); 1719 } 1720 } 1721 1722 /* hns3_probe - Device initialization routine 1723 * @pdev: PCI device information struct 1724 * @ent: entry in hns3_pci_tbl 1725 * 1726 * hns3_probe initializes a PF identified by a pci_dev structure. 1727 * The OS initialization, configuring of the PF private structure, 1728 * and a hardware reset occur. 1729 * 1730 * Returns 0 on success, negative on failure 1731 */ 1732 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1733 { 1734 struct hnae3_ae_dev *ae_dev; 1735 int ret; 1736 1737 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), 1738 GFP_KERNEL); 1739 if (!ae_dev) { 1740 ret = -ENOMEM; 1741 return ret; 1742 } 1743 1744 ae_dev->pdev = pdev; 1745 ae_dev->flag = ent->driver_data; 1746 ae_dev->dev_type = HNAE3_DEV_KNIC; 1747 ae_dev->reset_type = HNAE3_NONE_RESET; 1748 hns3_get_dev_capability(pdev, ae_dev); 1749 pci_set_drvdata(pdev, ae_dev); 1750 1751 ret = hnae3_register_ae_dev(ae_dev); 1752 if (ret) { 1753 devm_kfree(&pdev->dev, ae_dev); 1754 pci_set_drvdata(pdev, NULL); 1755 } 1756 1757 return ret; 1758 } 1759 1760 /* hns3_remove - Device removal routine 1761 * @pdev: PCI device information struct 1762 */ 1763 static void hns3_remove(struct pci_dev *pdev) 1764 { 1765 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1766 1767 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 1768 hns3_disable_sriov(pdev); 1769 1770 hnae3_unregister_ae_dev(ae_dev); 1771 pci_set_drvdata(pdev, NULL); 1772 } 1773 1774 /** 1775 * hns3_pci_sriov_configure 1776 * @pdev: pointer to a pci_dev structure 1777 * @num_vfs: number of VFs to allocate 1778 * 1779 * Enable or change the number of VFs. Called when the user updates the number 1780 * of VFs in sysfs. 1781 **/ 1782 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 1783 { 1784 int ret; 1785 1786 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 1787 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 1788 return -EINVAL; 1789 } 1790 1791 if (num_vfs) { 1792 ret = pci_enable_sriov(pdev, num_vfs); 1793 if (ret) 1794 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 1795 else 1796 return num_vfs; 1797 } else if (!pci_vfs_assigned(pdev)) { 1798 pci_disable_sriov(pdev); 1799 } else { 1800 dev_warn(&pdev->dev, 1801 "Unable to free VFs because some are assigned to VMs.\n"); 1802 } 1803 1804 return 0; 1805 } 1806 1807 static void hns3_shutdown(struct pci_dev *pdev) 1808 { 1809 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1810 1811 hnae3_unregister_ae_dev(ae_dev); 1812 devm_kfree(&pdev->dev, ae_dev); 1813 pci_set_drvdata(pdev, NULL); 1814 1815 if (system_state == SYSTEM_POWER_OFF) 1816 pci_set_power_state(pdev, PCI_D3hot); 1817 } 1818 1819 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 1820 pci_channel_state_t state) 1821 { 1822 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1823 pci_ers_result_t ret; 1824 1825 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state); 1826 1827 if (state == pci_channel_io_perm_failure) 1828 return PCI_ERS_RESULT_DISCONNECT; 1829 1830 if (!ae_dev) { 1831 dev_err(&pdev->dev, 1832 "Can't recover - error happened during device init\n"); 1833 return PCI_ERS_RESULT_NONE; 1834 } 1835 1836 if (ae_dev->ops->handle_hw_ras_error) 1837 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 1838 else 1839 return PCI_ERS_RESULT_NONE; 1840 1841 return ret; 1842 } 1843 1844 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 1845 { 1846 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1847 struct device *dev = &pdev->dev; 1848 1849 dev_info(dev, "requesting reset due to PCI error\n"); 1850 1851 /* request the reset */ 1852 if (ae_dev->ops->reset_event) { 1853 ae_dev->ops->reset_event(pdev, NULL); 1854 return PCI_ERS_RESULT_RECOVERED; 1855 } 1856 1857 return PCI_ERS_RESULT_DISCONNECT; 1858 } 1859 1860 static void hns3_reset_prepare(struct pci_dev *pdev) 1861 { 1862 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1863 1864 dev_info(&pdev->dev, "hns3 flr prepare\n"); 1865 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare) 1866 ae_dev->ops->flr_prepare(ae_dev); 1867 } 1868 1869 static void hns3_reset_done(struct pci_dev *pdev) 1870 { 1871 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 1872 1873 dev_info(&pdev->dev, "hns3 flr done\n"); 1874 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done) 1875 ae_dev->ops->flr_done(ae_dev); 1876 } 1877 1878 static const struct pci_error_handlers hns3_err_handler = { 1879 .error_detected = hns3_error_detected, 1880 .slot_reset = hns3_slot_reset, 1881 .reset_prepare = hns3_reset_prepare, 1882 .reset_done = hns3_reset_done, 1883 }; 1884 1885 static struct pci_driver hns3_driver = { 1886 .name = hns3_driver_name, 1887 .id_table = hns3_pci_tbl, 1888 .probe = hns3_probe, 1889 .remove = hns3_remove, 1890 .shutdown = hns3_shutdown, 1891 .sriov_configure = hns3_pci_sriov_configure, 1892 .err_handler = &hns3_err_handler, 1893 }; 1894 1895 /* set default feature to hns3 */ 1896 static void hns3_set_default_feature(struct net_device *netdev) 1897 { 1898 struct hnae3_handle *h = hns3_get_handle(netdev); 1899 struct pci_dev *pdev = h->pdev; 1900 1901 netdev->priv_flags |= IFF_UNICAST_FLT; 1902 1903 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1904 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1905 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1906 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1907 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1908 1909 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID; 1910 1911 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 1912 1913 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1914 NETIF_F_HW_VLAN_CTAG_FILTER | 1915 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1916 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1917 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1918 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1919 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1920 1921 netdev->vlan_features |= 1922 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | 1923 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO | 1924 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1925 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1926 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1927 1928 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1929 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 1930 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 1931 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 1932 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 1933 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC; 1934 1935 if (pdev->revision >= 0x21) { 1936 netdev->hw_features |= NETIF_F_GRO_HW; 1937 netdev->features |= NETIF_F_GRO_HW; 1938 1939 if (!(h->flags & HNAE3_SUPPORT_VF)) { 1940 netdev->hw_features |= NETIF_F_NTUPLE; 1941 netdev->features |= NETIF_F_NTUPLE; 1942 } 1943 } 1944 } 1945 1946 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 1947 struct hns3_desc_cb *cb) 1948 { 1949 unsigned int order = hnae3_page_order(ring); 1950 struct page *p; 1951 1952 p = dev_alloc_pages(order); 1953 if (!p) 1954 return -ENOMEM; 1955 1956 cb->priv = p; 1957 cb->page_offset = 0; 1958 cb->reuse_flag = 0; 1959 cb->buf = page_address(p); 1960 cb->length = hnae3_page_size(ring); 1961 cb->type = DESC_TYPE_PAGE; 1962 1963 return 0; 1964 } 1965 1966 static void hns3_free_buffer(struct hns3_enet_ring *ring, 1967 struct hns3_desc_cb *cb) 1968 { 1969 if (cb->type == DESC_TYPE_SKB) 1970 dev_kfree_skb_any((struct sk_buff *)cb->priv); 1971 else if (!HNAE3_IS_TX_RING(ring)) 1972 put_page((struct page *)cb->priv); 1973 memset(cb, 0, sizeof(*cb)); 1974 } 1975 1976 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 1977 { 1978 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 1979 cb->length, ring_to_dma_dir(ring)); 1980 1981 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 1982 return -EIO; 1983 1984 return 0; 1985 } 1986 1987 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 1988 struct hns3_desc_cb *cb) 1989 { 1990 if (cb->type == DESC_TYPE_SKB) 1991 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 1992 ring_to_dma_dir(ring)); 1993 else if (cb->length) 1994 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 1995 ring_to_dma_dir(ring)); 1996 } 1997 1998 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 1999 { 2000 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2001 ring->desc[i].addr = 0; 2002 } 2003 2004 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i) 2005 { 2006 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 2007 2008 if (!ring->desc_cb[i].dma) 2009 return; 2010 2011 hns3_buffer_detach(ring, i); 2012 hns3_free_buffer(ring, cb); 2013 } 2014 2015 static void hns3_free_buffers(struct hns3_enet_ring *ring) 2016 { 2017 int i; 2018 2019 for (i = 0; i < ring->desc_num; i++) 2020 hns3_free_buffer_detach(ring, i); 2021 } 2022 2023 /* free desc along with its attached buffer */ 2024 static void hns3_free_desc(struct hns3_enet_ring *ring) 2025 { 2026 int size = ring->desc_num * sizeof(ring->desc[0]); 2027 2028 hns3_free_buffers(ring); 2029 2030 if (ring->desc) { 2031 dma_free_coherent(ring_to_dev(ring), size, 2032 ring->desc, ring->desc_dma_addr); 2033 ring->desc = NULL; 2034 } 2035 } 2036 2037 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 2038 { 2039 int size = ring->desc_num * sizeof(ring->desc[0]); 2040 2041 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 2042 &ring->desc_dma_addr, GFP_KERNEL); 2043 if (!ring->desc) 2044 return -ENOMEM; 2045 2046 return 0; 2047 } 2048 2049 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring, 2050 struct hns3_desc_cb *cb) 2051 { 2052 int ret; 2053 2054 ret = hns3_alloc_buffer(ring, cb); 2055 if (ret) 2056 goto out; 2057 2058 ret = hns3_map_buffer(ring, cb); 2059 if (ret) 2060 goto out_with_buf; 2061 2062 return 0; 2063 2064 out_with_buf: 2065 hns3_free_buffer(ring, cb); 2066 out: 2067 return ret; 2068 } 2069 2070 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i) 2071 { 2072 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]); 2073 2074 if (ret) 2075 return ret; 2076 2077 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2078 2079 return 0; 2080 } 2081 2082 /* Allocate memory for raw pkg, and map with dma */ 2083 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 2084 { 2085 int i, j, ret; 2086 2087 for (i = 0; i < ring->desc_num; i++) { 2088 ret = hns3_alloc_buffer_attach(ring, i); 2089 if (ret) 2090 goto out_buffer_fail; 2091 } 2092 2093 return 0; 2094 2095 out_buffer_fail: 2096 for (j = i - 1; j >= 0; j--) 2097 hns3_free_buffer_detach(ring, j); 2098 return ret; 2099 } 2100 2101 /* detach a in-used buffer and replace with a reserved one */ 2102 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 2103 struct hns3_desc_cb *res_cb) 2104 { 2105 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 2106 ring->desc_cb[i] = *res_cb; 2107 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma); 2108 ring->desc[i].rx.bd_base_info = 0; 2109 } 2110 2111 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 2112 { 2113 ring->desc_cb[i].reuse_flag = 0; 2114 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma 2115 + ring->desc_cb[i].page_offset); 2116 ring->desc[i].rx.bd_base_info = 0; 2117 } 2118 2119 static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes, 2120 int *pkts) 2121 { 2122 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2123 2124 (*pkts) += (desc_cb->type == DESC_TYPE_SKB); 2125 (*bytes) += desc_cb->length; 2126 /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/ 2127 hns3_free_buffer_detach(ring, ring->next_to_clean); 2128 2129 ring_ptr_move_fw(ring, next_to_clean); 2130 } 2131 2132 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h) 2133 { 2134 int u = ring->next_to_use; 2135 int c = ring->next_to_clean; 2136 2137 if (unlikely(h > ring->desc_num)) 2138 return 0; 2139 2140 return u > c ? (h > c && h <= u) : (h > c || h <= u); 2141 } 2142 2143 void hns3_clean_tx_ring(struct hns3_enet_ring *ring) 2144 { 2145 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2146 struct hns3_nic_priv *priv = netdev_priv(netdev); 2147 struct netdev_queue *dev_queue; 2148 int bytes, pkts; 2149 int head; 2150 2151 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG); 2152 rmb(); /* Make sure head is ready before touch any data */ 2153 2154 if (is_ring_empty(ring) || head == ring->next_to_clean) 2155 return; /* no data to poll */ 2156 2157 if (unlikely(!is_valid_clean_head(ring, head))) { 2158 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head, 2159 ring->next_to_use, ring->next_to_clean); 2160 2161 u64_stats_update_begin(&ring->syncp); 2162 ring->stats.io_err_cnt++; 2163 u64_stats_update_end(&ring->syncp); 2164 return; 2165 } 2166 2167 bytes = 0; 2168 pkts = 0; 2169 while (head != ring->next_to_clean) { 2170 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts); 2171 /* Issue prefetch for next Tx descriptor */ 2172 prefetch(&ring->desc_cb[ring->next_to_clean]); 2173 } 2174 2175 ring->tqp_vector->tx_group.total_bytes += bytes; 2176 ring->tqp_vector->tx_group.total_packets += pkts; 2177 2178 u64_stats_update_begin(&ring->syncp); 2179 ring->stats.tx_bytes += bytes; 2180 ring->stats.tx_pkts += pkts; 2181 u64_stats_update_end(&ring->syncp); 2182 2183 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 2184 netdev_tx_completed_queue(dev_queue, pkts, bytes); 2185 2186 if (unlikely(pkts && netif_carrier_ok(netdev) && 2187 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) { 2188 /* Make sure that anybody stopping the queue after this 2189 * sees the new next_to_clean. 2190 */ 2191 smp_mb(); 2192 if (netif_tx_queue_stopped(dev_queue) && 2193 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 2194 netif_tx_wake_queue(dev_queue); 2195 ring->stats.restart_queue++; 2196 } 2197 } 2198 } 2199 2200 static int hns3_desc_unused(struct hns3_enet_ring *ring) 2201 { 2202 int ntc = ring->next_to_clean; 2203 int ntu = ring->next_to_use; 2204 2205 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 2206 } 2207 2208 static void 2209 hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count) 2210 { 2211 struct hns3_desc_cb *desc_cb; 2212 struct hns3_desc_cb res_cbs; 2213 int i, ret; 2214 2215 for (i = 0; i < cleand_count; i++) { 2216 desc_cb = &ring->desc_cb[ring->next_to_use]; 2217 if (desc_cb->reuse_flag) { 2218 u64_stats_update_begin(&ring->syncp); 2219 ring->stats.reuse_pg_cnt++; 2220 u64_stats_update_end(&ring->syncp); 2221 2222 hns3_reuse_buffer(ring, ring->next_to_use); 2223 } else { 2224 ret = hns3_reserve_buffer_map(ring, &res_cbs); 2225 if (ret) { 2226 u64_stats_update_begin(&ring->syncp); 2227 ring->stats.sw_err_cnt++; 2228 u64_stats_update_end(&ring->syncp); 2229 2230 netdev_err(ring->tqp->handle->kinfo.netdev, 2231 "hnae reserve buffer map failed.\n"); 2232 break; 2233 } 2234 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 2235 } 2236 2237 ring_ptr_move_fw(ring, next_to_use); 2238 } 2239 2240 wmb(); /* Make all data has been write before submit */ 2241 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 2242 } 2243 2244 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 2245 struct hns3_enet_ring *ring, int pull_len, 2246 struct hns3_desc_cb *desc_cb) 2247 { 2248 struct hns3_desc *desc; 2249 u32 truesize; 2250 int size; 2251 int last_offset; 2252 bool twobufs; 2253 2254 twobufs = ((PAGE_SIZE < 8192) && 2255 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048); 2256 2257 desc = &ring->desc[ring->next_to_clean]; 2258 size = le16_to_cpu(desc->rx.size); 2259 2260 truesize = hnae3_buf_size(ring); 2261 2262 if (!twobufs) 2263 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring); 2264 2265 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len, 2266 size - pull_len, truesize); 2267 2268 /* Avoid re-using remote pages,flag default unreuse */ 2269 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id())) 2270 return; 2271 2272 if (twobufs) { 2273 /* If we are only owner of page we can reuse it */ 2274 if (likely(page_count(desc_cb->priv) == 1)) { 2275 /* Flip page offset to other buffer */ 2276 desc_cb->page_offset ^= truesize; 2277 2278 desc_cb->reuse_flag = 1; 2279 /* bump ref count on page before it is given*/ 2280 get_page(desc_cb->priv); 2281 } 2282 return; 2283 } 2284 2285 /* Move offset up to the next cache line */ 2286 desc_cb->page_offset += truesize; 2287 2288 if (desc_cb->page_offset <= last_offset) { 2289 desc_cb->reuse_flag = 1; 2290 /* Bump ref count on page before it is given*/ 2291 get_page(desc_cb->priv); 2292 } 2293 } 2294 2295 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 2296 struct hns3_desc *desc) 2297 { 2298 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2299 int l3_type, l4_type; 2300 u32 bd_base_info; 2301 int ol4_type; 2302 u32 l234info; 2303 2304 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2305 l234info = le32_to_cpu(desc->rx.l234_info); 2306 2307 skb->ip_summed = CHECKSUM_NONE; 2308 2309 skb_checksum_none_assert(skb); 2310 2311 if (!(netdev->features & NETIF_F_RXCSUM)) 2312 return; 2313 2314 /* We MUST enable hardware checksum before enabling hardware GRO */ 2315 if (skb_shinfo(skb)->gso_size) { 2316 skb->ip_summed = CHECKSUM_UNNECESSARY; 2317 return; 2318 } 2319 2320 /* check if hardware has done checksum */ 2321 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 2322 return; 2323 2324 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) || 2325 BIT(HNS3_RXD_OL3E_B) || 2326 BIT(HNS3_RXD_OL4E_B)))) { 2327 u64_stats_update_begin(&ring->syncp); 2328 ring->stats.l3l4_csum_err++; 2329 u64_stats_update_end(&ring->syncp); 2330 2331 return; 2332 } 2333 2334 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M, 2335 HNS3_RXD_OL4ID_S); 2336 switch (ol4_type) { 2337 case HNS3_OL4_TYPE_MAC_IN_UDP: 2338 case HNS3_OL4_TYPE_NVGRE: 2339 skb->csum_level = 1; 2340 /* fall through */ 2341 case HNS3_OL4_TYPE_NO_TUN: 2342 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2343 HNS3_RXD_L3ID_S); 2344 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 2345 HNS3_RXD_L4ID_S); 2346 2347 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 2348 if ((l3_type == HNS3_L3_TYPE_IPV4 || 2349 l3_type == HNS3_L3_TYPE_IPV6) && 2350 (l4_type == HNS3_L4_TYPE_UDP || 2351 l4_type == HNS3_L4_TYPE_TCP || 2352 l4_type == HNS3_L4_TYPE_SCTP)) 2353 skb->ip_summed = CHECKSUM_UNNECESSARY; 2354 break; 2355 default: 2356 break; 2357 } 2358 } 2359 2360 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 2361 { 2362 if (skb_has_frag_list(skb)) 2363 napi_gro_flush(&ring->tqp_vector->napi, false); 2364 2365 napi_gro_receive(&ring->tqp_vector->napi, skb); 2366 } 2367 2368 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 2369 struct hns3_desc *desc, u32 l234info, 2370 u16 *vlan_tag) 2371 { 2372 struct pci_dev *pdev = ring->tqp->handle->pdev; 2373 2374 if (pdev->revision == 0x20) { 2375 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2376 if (!(*vlan_tag & VLAN_VID_MASK)) 2377 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2378 2379 return (*vlan_tag != 0); 2380 } 2381 2382 #define HNS3_STRP_OUTER_VLAN 0x1 2383 #define HNS3_STRP_INNER_VLAN 0x2 2384 2385 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 2386 HNS3_RXD_STRP_TAGP_S)) { 2387 case HNS3_STRP_OUTER_VLAN: 2388 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 2389 return true; 2390 case HNS3_STRP_INNER_VLAN: 2391 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 2392 return true; 2393 default: 2394 return false; 2395 } 2396 } 2397 2398 static int hns3_alloc_skb(struct hns3_enet_ring *ring, int length, 2399 unsigned char *va) 2400 { 2401 #define HNS3_NEED_ADD_FRAG 1 2402 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 2403 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2404 struct sk_buff *skb; 2405 2406 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 2407 skb = ring->skb; 2408 if (unlikely(!skb)) { 2409 netdev_err(netdev, "alloc rx skb fail\n"); 2410 2411 u64_stats_update_begin(&ring->syncp); 2412 ring->stats.sw_err_cnt++; 2413 u64_stats_update_end(&ring->syncp); 2414 2415 return -ENOMEM; 2416 } 2417 2418 prefetchw(skb->data); 2419 2420 ring->pending_buf = 1; 2421 ring->frag_num = 0; 2422 ring->tail_skb = NULL; 2423 if (length <= HNS3_RX_HEAD_SIZE) { 2424 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 2425 2426 /* We can reuse buffer as-is, just make sure it is local */ 2427 if (likely(page_to_nid(desc_cb->priv) == numa_node_id())) 2428 desc_cb->reuse_flag = 1; 2429 else /* This page cannot be reused so discard it */ 2430 put_page(desc_cb->priv); 2431 2432 ring_ptr_move_fw(ring, next_to_clean); 2433 return 0; 2434 } 2435 u64_stats_update_begin(&ring->syncp); 2436 ring->stats.seg_pkt_cnt++; 2437 u64_stats_update_end(&ring->syncp); 2438 2439 ring->pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE); 2440 __skb_put(skb, ring->pull_len); 2441 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 2442 desc_cb); 2443 ring_ptr_move_fw(ring, next_to_clean); 2444 2445 return HNS3_NEED_ADD_FRAG; 2446 } 2447 2448 static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc, 2449 struct sk_buff **out_skb, bool pending) 2450 { 2451 struct sk_buff *skb = *out_skb; 2452 struct sk_buff *head_skb = *out_skb; 2453 struct sk_buff *new_skb; 2454 struct hns3_desc_cb *desc_cb; 2455 struct hns3_desc *pre_desc; 2456 u32 bd_base_info; 2457 int pre_bd; 2458 2459 /* if there is pending bd, the SW param next_to_clean has moved 2460 * to next and the next is NULL 2461 */ 2462 if (pending) { 2463 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) % 2464 ring->desc_num; 2465 pre_desc = &ring->desc[pre_bd]; 2466 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info); 2467 } else { 2468 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2469 } 2470 2471 while (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { 2472 desc = &ring->desc[ring->next_to_clean]; 2473 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2474 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2475 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 2476 return -ENXIO; 2477 2478 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 2479 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 2480 HNS3_RX_HEAD_SIZE); 2481 if (unlikely(!new_skb)) { 2482 netdev_err(ring->tqp->handle->kinfo.netdev, 2483 "alloc rx skb frag fail\n"); 2484 return -ENXIO; 2485 } 2486 ring->frag_num = 0; 2487 2488 if (ring->tail_skb) { 2489 ring->tail_skb->next = new_skb; 2490 ring->tail_skb = new_skb; 2491 } else { 2492 skb_shinfo(skb)->frag_list = new_skb; 2493 ring->tail_skb = new_skb; 2494 } 2495 } 2496 2497 if (ring->tail_skb) { 2498 head_skb->truesize += hnae3_buf_size(ring); 2499 head_skb->data_len += le16_to_cpu(desc->rx.size); 2500 head_skb->len += le16_to_cpu(desc->rx.size); 2501 skb = ring->tail_skb; 2502 } 2503 2504 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 2505 ring_ptr_move_fw(ring, next_to_clean); 2506 ring->pending_buf++; 2507 } 2508 2509 return 0; 2510 } 2511 2512 static void hns3_set_gro_param(struct sk_buff *skb, u32 l234info, 2513 u32 bd_base_info) 2514 { 2515 u16 gro_count; 2516 u32 l3_type; 2517 2518 gro_count = hnae3_get_field(l234info, HNS3_RXD_GRO_COUNT_M, 2519 HNS3_RXD_GRO_COUNT_S); 2520 /* if there is no HW GRO, do not set gro params */ 2521 if (!gro_count) 2522 return; 2523 2524 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count 2525 * to skb_shinfo(skb)->gso_segs 2526 */ 2527 NAPI_GRO_CB(skb)->count = gro_count; 2528 2529 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 2530 HNS3_RXD_L3ID_S); 2531 if (l3_type == HNS3_L3_TYPE_IPV4) 2532 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 2533 else if (l3_type == HNS3_L3_TYPE_IPV6) 2534 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 2535 else 2536 return; 2537 2538 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 2539 HNS3_RXD_GRO_SIZE_M, 2540 HNS3_RXD_GRO_SIZE_S); 2541 if (skb_shinfo(skb)->gso_size) 2542 tcp_gro_complete(skb); 2543 } 2544 2545 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 2546 struct sk_buff *skb) 2547 { 2548 struct hnae3_handle *handle = ring->tqp->handle; 2549 enum pkt_hash_types rss_type; 2550 struct hns3_desc *desc; 2551 int last_bd; 2552 2553 /* When driver handle the rss type, ring->next_to_clean indicates the 2554 * first descriptor of next packet, need -1 here. 2555 */ 2556 last_bd = (ring->next_to_clean - 1 + ring->desc_num) % ring->desc_num; 2557 desc = &ring->desc[last_bd]; 2558 2559 if (le32_to_cpu(desc->rx.rss_hash)) 2560 rss_type = handle->kinfo.rss_type; 2561 else 2562 rss_type = PKT_HASH_TYPE_NONE; 2563 2564 skb_set_hash(skb, le32_to_cpu(desc->rx.rss_hash), rss_type); 2565 } 2566 2567 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring, 2568 struct sk_buff **out_skb) 2569 { 2570 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2571 enum hns3_pkt_l2t_type l2_frame_type; 2572 struct sk_buff *skb = ring->skb; 2573 struct hns3_desc_cb *desc_cb; 2574 struct hns3_desc *desc; 2575 u32 bd_base_info; 2576 u32 l234info; 2577 int length; 2578 int ret; 2579 2580 desc = &ring->desc[ring->next_to_clean]; 2581 desc_cb = &ring->desc_cb[ring->next_to_clean]; 2582 2583 prefetch(desc); 2584 2585 length = le16_to_cpu(desc->rx.size); 2586 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2587 2588 /* Check valid BD */ 2589 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 2590 return -ENXIO; 2591 2592 if (!skb) 2593 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset; 2594 2595 /* Prefetch first cache line of first page 2596 * Idea is to cache few bytes of the header of the packet. Our L1 Cache 2597 * line size is 64B so need to prefetch twice to make it 128B. But in 2598 * actual we can have greater size of caches with 128B Level 1 cache 2599 * lines. In such a case, single fetch would suffice to cache in the 2600 * relevant part of the header. 2601 */ 2602 prefetch(ring->va); 2603 #if L1_CACHE_BYTES < 128 2604 prefetch(ring->va + L1_CACHE_BYTES); 2605 #endif 2606 2607 if (!skb) { 2608 ret = hns3_alloc_skb(ring, length, ring->va); 2609 *out_skb = skb = ring->skb; 2610 2611 if (ret < 0) /* alloc buffer fail */ 2612 return ret; 2613 if (ret > 0) { /* need add frag */ 2614 ret = hns3_add_frag(ring, desc, &skb, false); 2615 if (ret) 2616 return ret; 2617 2618 /* As the head data may be changed when GRO enable, copy 2619 * the head data in after other data rx completed 2620 */ 2621 memcpy(skb->data, ring->va, 2622 ALIGN(ring->pull_len, sizeof(long))); 2623 } 2624 } else { 2625 ret = hns3_add_frag(ring, desc, &skb, true); 2626 if (ret) 2627 return ret; 2628 2629 /* As the head data may be changed when GRO enable, copy 2630 * the head data in after other data rx completed 2631 */ 2632 memcpy(skb->data, ring->va, 2633 ALIGN(ring->pull_len, sizeof(long))); 2634 } 2635 2636 l234info = le32_to_cpu(desc->rx.l234_info); 2637 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 2638 2639 /* Based on hw strategy, the tag offloaded will be stored at 2640 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 2641 * in one layer tag case. 2642 */ 2643 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 2644 u16 vlan_tag; 2645 2646 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 2647 __vlan_hwaccel_put_tag(skb, 2648 htons(ETH_P_8021Q), 2649 vlan_tag); 2650 } 2651 2652 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) { 2653 u64_stats_update_begin(&ring->syncp); 2654 ring->stats.non_vld_descs++; 2655 u64_stats_update_end(&ring->syncp); 2656 2657 dev_kfree_skb_any(skb); 2658 return -EINVAL; 2659 } 2660 2661 if (unlikely((!desc->rx.pkt_len) || 2662 (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 2663 BIT(HNS3_RXD_L2E_B))))) { 2664 u64_stats_update_begin(&ring->syncp); 2665 if (l234info & BIT(HNS3_RXD_L2E_B)) 2666 ring->stats.l2_err++; 2667 else 2668 ring->stats.err_pkt_len++; 2669 u64_stats_update_end(&ring->syncp); 2670 2671 dev_kfree_skb_any(skb); 2672 return -EFAULT; 2673 } 2674 2675 2676 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 2677 HNS3_RXD_DMAC_S); 2678 u64_stats_update_begin(&ring->syncp); 2679 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 2680 ring->stats.rx_multicast++; 2681 2682 ring->stats.rx_pkts++; 2683 ring->stats.rx_bytes += skb->len; 2684 u64_stats_update_end(&ring->syncp); 2685 2686 ring->tqp_vector->rx_group.total_bytes += skb->len; 2687 2688 /* This is needed in order to enable forwarding support */ 2689 hns3_set_gro_param(skb, l234info, bd_base_info); 2690 2691 hns3_rx_checksum(ring, skb, desc); 2692 *out_skb = skb; 2693 hns3_set_rx_skb_rss_type(ring, skb); 2694 2695 return 0; 2696 } 2697 2698 int hns3_clean_rx_ring( 2699 struct hns3_enet_ring *ring, int budget, 2700 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 2701 { 2702 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 2703 struct net_device *netdev = ring->tqp->handle->kinfo.netdev; 2704 int recv_pkts, recv_bds, clean_count, err; 2705 int unused_count = hns3_desc_unused(ring) - ring->pending_buf; 2706 struct sk_buff *skb = ring->skb; 2707 int num; 2708 2709 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG); 2710 rmb(); /* Make sure num taken effect before the other data is touched */ 2711 2712 recv_pkts = 0, recv_bds = 0, clean_count = 0; 2713 num -= unused_count; 2714 2715 while (recv_pkts < budget && recv_bds < num) { 2716 /* Reuse or realloc buffers */ 2717 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 2718 hns3_nic_alloc_rx_buffers(ring, 2719 clean_count + unused_count); 2720 clean_count = 0; 2721 unused_count = hns3_desc_unused(ring) - 2722 ring->pending_buf; 2723 } 2724 2725 /* Poll one pkt */ 2726 err = hns3_handle_rx_bd(ring, &skb); 2727 if (unlikely(!skb)) /* This fault cannot be repaired */ 2728 goto out; 2729 2730 if (err == -ENXIO) { /* Do not get FE for the packet */ 2731 goto out; 2732 } else if (unlikely(err)) { /* Do jump the err */ 2733 recv_bds += ring->pending_buf; 2734 clean_count += ring->pending_buf; 2735 ring->skb = NULL; 2736 ring->pending_buf = 0; 2737 continue; 2738 } 2739 2740 /* Do update ip stack process */ 2741 skb->protocol = eth_type_trans(skb, netdev); 2742 rx_fn(ring, skb); 2743 recv_bds += ring->pending_buf; 2744 clean_count += ring->pending_buf; 2745 ring->skb = NULL; 2746 ring->pending_buf = 0; 2747 2748 recv_pkts++; 2749 } 2750 2751 out: 2752 /* Make all data has been write before submit */ 2753 if (clean_count + unused_count > 0) 2754 hns3_nic_alloc_rx_buffers(ring, 2755 clean_count + unused_count); 2756 2757 return recv_pkts; 2758 } 2759 2760 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group) 2761 { 2762 struct hns3_enet_tqp_vector *tqp_vector = 2763 ring_group->ring->tqp_vector; 2764 enum hns3_flow_level_range new_flow_level; 2765 int packets_per_msecs; 2766 int bytes_per_msecs; 2767 u32 time_passed_ms; 2768 u16 new_int_gl; 2769 2770 if (!tqp_vector->last_jiffies) 2771 return false; 2772 2773 if (ring_group->total_packets == 0) { 2774 ring_group->coal.int_gl = HNS3_INT_GL_50K; 2775 ring_group->coal.flow_level = HNS3_FLOW_LOW; 2776 return true; 2777 } 2778 2779 /* Simple throttlerate management 2780 * 0-10MB/s lower (50000 ints/s) 2781 * 10-20MB/s middle (20000 ints/s) 2782 * 20-1249MB/s high (18000 ints/s) 2783 * > 40000pps ultra (8000 ints/s) 2784 */ 2785 new_flow_level = ring_group->coal.flow_level; 2786 new_int_gl = ring_group->coal.int_gl; 2787 time_passed_ms = 2788 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies); 2789 2790 if (!time_passed_ms) 2791 return false; 2792 2793 do_div(ring_group->total_packets, time_passed_ms); 2794 packets_per_msecs = ring_group->total_packets; 2795 2796 do_div(ring_group->total_bytes, time_passed_ms); 2797 bytes_per_msecs = ring_group->total_bytes; 2798 2799 #define HNS3_RX_LOW_BYTE_RATE 10000 2800 #define HNS3_RX_MID_BYTE_RATE 20000 2801 2802 switch (new_flow_level) { 2803 case HNS3_FLOW_LOW: 2804 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE) 2805 new_flow_level = HNS3_FLOW_MID; 2806 break; 2807 case HNS3_FLOW_MID: 2808 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE) 2809 new_flow_level = HNS3_FLOW_HIGH; 2810 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE) 2811 new_flow_level = HNS3_FLOW_LOW; 2812 break; 2813 case HNS3_FLOW_HIGH: 2814 case HNS3_FLOW_ULTRA: 2815 default: 2816 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE) 2817 new_flow_level = HNS3_FLOW_MID; 2818 break; 2819 } 2820 2821 #define HNS3_RX_ULTRA_PACKET_RATE 40 2822 2823 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE && 2824 &tqp_vector->rx_group == ring_group) 2825 new_flow_level = HNS3_FLOW_ULTRA; 2826 2827 switch (new_flow_level) { 2828 case HNS3_FLOW_LOW: 2829 new_int_gl = HNS3_INT_GL_50K; 2830 break; 2831 case HNS3_FLOW_MID: 2832 new_int_gl = HNS3_INT_GL_20K; 2833 break; 2834 case HNS3_FLOW_HIGH: 2835 new_int_gl = HNS3_INT_GL_18K; 2836 break; 2837 case HNS3_FLOW_ULTRA: 2838 new_int_gl = HNS3_INT_GL_8K; 2839 break; 2840 default: 2841 break; 2842 } 2843 2844 ring_group->total_bytes = 0; 2845 ring_group->total_packets = 0; 2846 ring_group->coal.flow_level = new_flow_level; 2847 if (new_int_gl != ring_group->coal.int_gl) { 2848 ring_group->coal.int_gl = new_int_gl; 2849 return true; 2850 } 2851 return false; 2852 } 2853 2854 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) 2855 { 2856 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 2857 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 2858 bool rx_update, tx_update; 2859 2860 /* update param every 1000ms */ 2861 if (time_before(jiffies, 2862 tqp_vector->last_jiffies + msecs_to_jiffies(1000))) 2863 return; 2864 2865 if (rx_group->coal.gl_adapt_enable) { 2866 rx_update = hns3_get_new_int_gl(rx_group); 2867 if (rx_update) 2868 hns3_set_vector_coalesce_rx_gl(tqp_vector, 2869 rx_group->coal.int_gl); 2870 } 2871 2872 if (tx_group->coal.gl_adapt_enable) { 2873 tx_update = hns3_get_new_int_gl(tx_group); 2874 if (tx_update) 2875 hns3_set_vector_coalesce_tx_gl(tqp_vector, 2876 tx_group->coal.int_gl); 2877 } 2878 2879 tqp_vector->last_jiffies = jiffies; 2880 } 2881 2882 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 2883 { 2884 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 2885 struct hns3_enet_ring *ring; 2886 int rx_pkt_total = 0; 2887 2888 struct hns3_enet_tqp_vector *tqp_vector = 2889 container_of(napi, struct hns3_enet_tqp_vector, napi); 2890 bool clean_complete = true; 2891 int rx_budget; 2892 2893 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 2894 napi_complete(napi); 2895 return 0; 2896 } 2897 2898 /* Since the actual Tx work is minimal, we can give the Tx a larger 2899 * budget and be more aggressive about cleaning up the Tx descriptors. 2900 */ 2901 hns3_for_each_ring(ring, tqp_vector->tx_group) 2902 hns3_clean_tx_ring(ring); 2903 2904 /* make sure rx ring budget not smaller than 1 */ 2905 rx_budget = max(budget / tqp_vector->num_tqps, 1); 2906 2907 hns3_for_each_ring(ring, tqp_vector->rx_group) { 2908 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 2909 hns3_rx_skb); 2910 2911 if (rx_cleaned >= rx_budget) 2912 clean_complete = false; 2913 2914 rx_pkt_total += rx_cleaned; 2915 } 2916 2917 tqp_vector->rx_group.total_packets += rx_pkt_total; 2918 2919 if (!clean_complete) 2920 return budget; 2921 2922 if (napi_complete(napi) && 2923 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 2924 hns3_update_new_int_gl(tqp_vector); 2925 hns3_mask_vector_irq(tqp_vector, 1); 2926 } 2927 2928 return rx_pkt_total; 2929 } 2930 2931 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 2932 struct hnae3_ring_chain_node *head) 2933 { 2934 struct pci_dev *pdev = tqp_vector->handle->pdev; 2935 struct hnae3_ring_chain_node *cur_chain = head; 2936 struct hnae3_ring_chain_node *chain; 2937 struct hns3_enet_ring *tx_ring; 2938 struct hns3_enet_ring *rx_ring; 2939 2940 tx_ring = tqp_vector->tx_group.ring; 2941 if (tx_ring) { 2942 cur_chain->tqp_index = tx_ring->tqp->tqp_index; 2943 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 2944 HNAE3_RING_TYPE_TX); 2945 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2946 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX); 2947 2948 cur_chain->next = NULL; 2949 2950 while (tx_ring->next) { 2951 tx_ring = tx_ring->next; 2952 2953 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), 2954 GFP_KERNEL); 2955 if (!chain) 2956 goto err_free_chain; 2957 2958 cur_chain->next = chain; 2959 chain->tqp_index = tx_ring->tqp->tqp_index; 2960 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 2961 HNAE3_RING_TYPE_TX); 2962 hnae3_set_field(chain->int_gl_idx, 2963 HNAE3_RING_GL_IDX_M, 2964 HNAE3_RING_GL_IDX_S, 2965 HNAE3_RING_GL_TX); 2966 2967 cur_chain = chain; 2968 } 2969 } 2970 2971 rx_ring = tqp_vector->rx_group.ring; 2972 if (!tx_ring && rx_ring) { 2973 cur_chain->next = NULL; 2974 cur_chain->tqp_index = rx_ring->tqp->tqp_index; 2975 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B, 2976 HNAE3_RING_TYPE_RX); 2977 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2978 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 2979 2980 rx_ring = rx_ring->next; 2981 } 2982 2983 while (rx_ring) { 2984 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 2985 if (!chain) 2986 goto err_free_chain; 2987 2988 cur_chain->next = chain; 2989 chain->tqp_index = rx_ring->tqp->tqp_index; 2990 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 2991 HNAE3_RING_TYPE_RX); 2992 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M, 2993 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX); 2994 2995 cur_chain = chain; 2996 2997 rx_ring = rx_ring->next; 2998 } 2999 3000 return 0; 3001 3002 err_free_chain: 3003 cur_chain = head->next; 3004 while (cur_chain) { 3005 chain = cur_chain->next; 3006 devm_kfree(&pdev->dev, cur_chain); 3007 cur_chain = chain; 3008 } 3009 head->next = NULL; 3010 3011 return -ENOMEM; 3012 } 3013 3014 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 3015 struct hnae3_ring_chain_node *head) 3016 { 3017 struct pci_dev *pdev = tqp_vector->handle->pdev; 3018 struct hnae3_ring_chain_node *chain_tmp, *chain; 3019 3020 chain = head->next; 3021 3022 while (chain) { 3023 chain_tmp = chain->next; 3024 devm_kfree(&pdev->dev, chain); 3025 chain = chain_tmp; 3026 } 3027 } 3028 3029 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 3030 struct hns3_enet_ring *ring) 3031 { 3032 ring->next = group->ring; 3033 group->ring = ring; 3034 3035 group->count++; 3036 } 3037 3038 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 3039 { 3040 struct pci_dev *pdev = priv->ae_handle->pdev; 3041 struct hns3_enet_tqp_vector *tqp_vector; 3042 int num_vectors = priv->vector_num; 3043 int numa_node; 3044 int vector_i; 3045 3046 numa_node = dev_to_node(&pdev->dev); 3047 3048 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 3049 tqp_vector = &priv->tqp_vector[vector_i]; 3050 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 3051 &tqp_vector->affinity_mask); 3052 } 3053 } 3054 3055 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 3056 { 3057 struct hnae3_ring_chain_node vector_ring_chain; 3058 struct hnae3_handle *h = priv->ae_handle; 3059 struct hns3_enet_tqp_vector *tqp_vector; 3060 int ret = 0; 3061 int i; 3062 3063 hns3_nic_set_cpumask(priv); 3064 3065 for (i = 0; i < priv->vector_num; i++) { 3066 tqp_vector = &priv->tqp_vector[i]; 3067 hns3_vector_gl_rl_init_hw(tqp_vector, priv); 3068 tqp_vector->num_tqps = 0; 3069 } 3070 3071 for (i = 0; i < h->kinfo.num_tqps; i++) { 3072 u16 vector_i = i % priv->vector_num; 3073 u16 tqp_num = h->kinfo.num_tqps; 3074 3075 tqp_vector = &priv->tqp_vector[vector_i]; 3076 3077 hns3_add_ring_to_group(&tqp_vector->tx_group, 3078 priv->ring_data[i].ring); 3079 3080 hns3_add_ring_to_group(&tqp_vector->rx_group, 3081 priv->ring_data[i + tqp_num].ring); 3082 3083 priv->ring_data[i].ring->tqp_vector = tqp_vector; 3084 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector; 3085 tqp_vector->num_tqps++; 3086 } 3087 3088 for (i = 0; i < priv->vector_num; i++) { 3089 tqp_vector = &priv->tqp_vector[i]; 3090 3091 tqp_vector->rx_group.total_bytes = 0; 3092 tqp_vector->rx_group.total_packets = 0; 3093 tqp_vector->tx_group.total_bytes = 0; 3094 tqp_vector->tx_group.total_packets = 0; 3095 tqp_vector->handle = h; 3096 3097 ret = hns3_get_vector_ring_chain(tqp_vector, 3098 &vector_ring_chain); 3099 if (ret) 3100 goto map_ring_fail; 3101 3102 ret = h->ae_algo->ops->map_ring_to_vector(h, 3103 tqp_vector->vector_irq, &vector_ring_chain); 3104 3105 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3106 3107 if (ret) 3108 goto map_ring_fail; 3109 3110 netif_napi_add(priv->netdev, &tqp_vector->napi, 3111 hns3_nic_common_poll, NAPI_POLL_WEIGHT); 3112 } 3113 3114 return 0; 3115 3116 map_ring_fail: 3117 while (i--) 3118 netif_napi_del(&priv->tqp_vector[i].napi); 3119 3120 return ret; 3121 } 3122 3123 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 3124 { 3125 #define HNS3_VECTOR_PF_MAX_NUM 64 3126 3127 struct hnae3_handle *h = priv->ae_handle; 3128 struct hns3_enet_tqp_vector *tqp_vector; 3129 struct hnae3_vector_info *vector; 3130 struct pci_dev *pdev = h->pdev; 3131 u16 tqp_num = h->kinfo.num_tqps; 3132 u16 vector_num; 3133 int ret = 0; 3134 u16 i; 3135 3136 /* RSS size, cpu online and vector_num should be the same */ 3137 /* Should consider 2p/4p later */ 3138 vector_num = min_t(u16, num_online_cpus(), tqp_num); 3139 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM); 3140 3141 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 3142 GFP_KERNEL); 3143 if (!vector) 3144 return -ENOMEM; 3145 3146 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 3147 3148 priv->vector_num = vector_num; 3149 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 3150 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 3151 GFP_KERNEL); 3152 if (!priv->tqp_vector) { 3153 ret = -ENOMEM; 3154 goto out; 3155 } 3156 3157 for (i = 0; i < priv->vector_num; i++) { 3158 tqp_vector = &priv->tqp_vector[i]; 3159 tqp_vector->idx = i; 3160 tqp_vector->mask_addr = vector[i].io_addr; 3161 tqp_vector->vector_irq = vector[i].vector; 3162 hns3_vector_gl_rl_init(tqp_vector, priv); 3163 } 3164 3165 out: 3166 devm_kfree(&pdev->dev, vector); 3167 return ret; 3168 } 3169 3170 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 3171 { 3172 group->ring = NULL; 3173 group->count = 0; 3174 } 3175 3176 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 3177 { 3178 struct hnae3_ring_chain_node vector_ring_chain; 3179 struct hnae3_handle *h = priv->ae_handle; 3180 struct hns3_enet_tqp_vector *tqp_vector; 3181 int i; 3182 3183 for (i = 0; i < priv->vector_num; i++) { 3184 tqp_vector = &priv->tqp_vector[i]; 3185 3186 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 3187 continue; 3188 3189 hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain); 3190 3191 h->ae_algo->ops->unmap_ring_from_vector(h, 3192 tqp_vector->vector_irq, &vector_ring_chain); 3193 3194 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain); 3195 3196 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) { 3197 irq_set_affinity_notifier(tqp_vector->vector_irq, 3198 NULL); 3199 irq_set_affinity_hint(tqp_vector->vector_irq, NULL); 3200 free_irq(tqp_vector->vector_irq, tqp_vector); 3201 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED; 3202 } 3203 3204 hns3_clear_ring_group(&tqp_vector->rx_group); 3205 hns3_clear_ring_group(&tqp_vector->tx_group); 3206 netif_napi_del(&priv->tqp_vector[i].napi); 3207 } 3208 } 3209 3210 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 3211 { 3212 struct hnae3_handle *h = priv->ae_handle; 3213 struct pci_dev *pdev = h->pdev; 3214 int i, ret; 3215 3216 for (i = 0; i < priv->vector_num; i++) { 3217 struct hns3_enet_tqp_vector *tqp_vector; 3218 3219 tqp_vector = &priv->tqp_vector[i]; 3220 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 3221 if (ret) 3222 return ret; 3223 } 3224 3225 devm_kfree(&pdev->dev, priv->tqp_vector); 3226 return 0; 3227 } 3228 3229 static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 3230 int ring_type) 3231 { 3232 struct hns3_nic_ring_data *ring_data = priv->ring_data; 3233 int queue_num = priv->ae_handle->kinfo.num_tqps; 3234 struct pci_dev *pdev = priv->ae_handle->pdev; 3235 struct hns3_enet_ring *ring; 3236 int desc_num; 3237 3238 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL); 3239 if (!ring) 3240 return -ENOMEM; 3241 3242 if (ring_type == HNAE3_RING_TYPE_TX) { 3243 desc_num = priv->ae_handle->kinfo.num_tx_desc; 3244 ring_data[q->tqp_index].ring = ring; 3245 ring_data[q->tqp_index].queue_index = q->tqp_index; 3246 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET; 3247 } else { 3248 desc_num = priv->ae_handle->kinfo.num_rx_desc; 3249 ring_data[q->tqp_index + queue_num].ring = ring; 3250 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index; 3251 ring->io_base = q->io_base; 3252 } 3253 3254 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 3255 3256 ring->tqp = q; 3257 ring->desc = NULL; 3258 ring->desc_cb = NULL; 3259 ring->dev = priv->dev; 3260 ring->desc_dma_addr = 0; 3261 ring->buf_size = q->buf_size; 3262 ring->desc_num = desc_num; 3263 ring->next_to_use = 0; 3264 ring->next_to_clean = 0; 3265 3266 return 0; 3267 } 3268 3269 static int hns3_queue_to_ring(struct hnae3_queue *tqp, 3270 struct hns3_nic_priv *priv) 3271 { 3272 int ret; 3273 3274 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 3275 if (ret) 3276 return ret; 3277 3278 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 3279 if (ret) { 3280 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring); 3281 return ret; 3282 } 3283 3284 return 0; 3285 } 3286 3287 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 3288 { 3289 struct hnae3_handle *h = priv->ae_handle; 3290 struct pci_dev *pdev = h->pdev; 3291 int i, ret; 3292 3293 priv->ring_data = devm_kzalloc(&pdev->dev, 3294 array3_size(h->kinfo.num_tqps, 3295 sizeof(*priv->ring_data), 3296 2), 3297 GFP_KERNEL); 3298 if (!priv->ring_data) 3299 return -ENOMEM; 3300 3301 for (i = 0; i < h->kinfo.num_tqps; i++) { 3302 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv); 3303 if (ret) 3304 goto err; 3305 } 3306 3307 return 0; 3308 err: 3309 while (i--) { 3310 devm_kfree(priv->dev, priv->ring_data[i].ring); 3311 devm_kfree(priv->dev, 3312 priv->ring_data[i + h->kinfo.num_tqps].ring); 3313 } 3314 3315 devm_kfree(&pdev->dev, priv->ring_data); 3316 return ret; 3317 } 3318 3319 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 3320 { 3321 struct hnae3_handle *h = priv->ae_handle; 3322 int i; 3323 3324 for (i = 0; i < h->kinfo.num_tqps; i++) { 3325 devm_kfree(priv->dev, priv->ring_data[i].ring); 3326 devm_kfree(priv->dev, 3327 priv->ring_data[i + h->kinfo.num_tqps].ring); 3328 } 3329 devm_kfree(priv->dev, priv->ring_data); 3330 } 3331 3332 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 3333 { 3334 int ret; 3335 3336 if (ring->desc_num <= 0 || ring->buf_size <= 0) 3337 return -EINVAL; 3338 3339 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]), 3340 GFP_KERNEL); 3341 if (!ring->desc_cb) { 3342 ret = -ENOMEM; 3343 goto out; 3344 } 3345 3346 ret = hns3_alloc_desc(ring); 3347 if (ret) 3348 goto out_with_desc_cb; 3349 3350 if (!HNAE3_IS_TX_RING(ring)) { 3351 ret = hns3_alloc_ring_buffers(ring); 3352 if (ret) 3353 goto out_with_desc; 3354 } 3355 3356 return 0; 3357 3358 out_with_desc: 3359 hns3_free_desc(ring); 3360 out_with_desc_cb: 3361 kfree(ring->desc_cb); 3362 ring->desc_cb = NULL; 3363 out: 3364 return ret; 3365 } 3366 3367 static void hns3_fini_ring(struct hns3_enet_ring *ring) 3368 { 3369 hns3_free_desc(ring); 3370 kfree(ring->desc_cb); 3371 ring->desc_cb = NULL; 3372 ring->next_to_clean = 0; 3373 ring->next_to_use = 0; 3374 ring->pending_buf = 0; 3375 if (ring->skb) { 3376 dev_kfree_skb_any(ring->skb); 3377 ring->skb = NULL; 3378 } 3379 } 3380 3381 static int hns3_buf_size2type(u32 buf_size) 3382 { 3383 int bd_size_type; 3384 3385 switch (buf_size) { 3386 case 512: 3387 bd_size_type = HNS3_BD_SIZE_512_TYPE; 3388 break; 3389 case 1024: 3390 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 3391 break; 3392 case 2048: 3393 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3394 break; 3395 case 4096: 3396 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 3397 break; 3398 default: 3399 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 3400 } 3401 3402 return bd_size_type; 3403 } 3404 3405 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 3406 { 3407 dma_addr_t dma = ring->desc_dma_addr; 3408 struct hnae3_queue *q = ring->tqp; 3409 3410 if (!HNAE3_IS_TX_RING(ring)) { 3411 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, 3412 (u32)dma); 3413 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 3414 (u32)((dma >> 31) >> 1)); 3415 3416 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 3417 hns3_buf_size2type(ring->buf_size)); 3418 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 3419 ring->desc_num / 8 - 1); 3420 3421 } else { 3422 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 3423 (u32)dma); 3424 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 3425 (u32)((dma >> 31) >> 1)); 3426 3427 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 3428 ring->desc_num / 8 - 1); 3429 } 3430 } 3431 3432 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 3433 { 3434 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 3435 int i; 3436 3437 for (i = 0; i < HNAE3_MAX_TC; i++) { 3438 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i]; 3439 int j; 3440 3441 if (!tc_info->enable) 3442 continue; 3443 3444 for (j = 0; j < tc_info->tqp_count; j++) { 3445 struct hnae3_queue *q; 3446 3447 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp; 3448 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, 3449 tc_info->tc); 3450 } 3451 } 3452 } 3453 3454 int hns3_init_all_ring(struct hns3_nic_priv *priv) 3455 { 3456 struct hnae3_handle *h = priv->ae_handle; 3457 int ring_num = h->kinfo.num_tqps * 2; 3458 int i, j; 3459 int ret; 3460 3461 for (i = 0; i < ring_num; i++) { 3462 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring); 3463 if (ret) { 3464 dev_err(priv->dev, 3465 "Alloc ring memory fail! ret=%d\n", ret); 3466 goto out_when_alloc_ring_memory; 3467 } 3468 3469 u64_stats_init(&priv->ring_data[i].ring->syncp); 3470 } 3471 3472 return 0; 3473 3474 out_when_alloc_ring_memory: 3475 for (j = i - 1; j >= 0; j--) 3476 hns3_fini_ring(priv->ring_data[j].ring); 3477 3478 return -ENOMEM; 3479 } 3480 3481 int hns3_uninit_all_ring(struct hns3_nic_priv *priv) 3482 { 3483 struct hnae3_handle *h = priv->ae_handle; 3484 int i; 3485 3486 for (i = 0; i < h->kinfo.num_tqps; i++) { 3487 hns3_fini_ring(priv->ring_data[i].ring); 3488 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring); 3489 } 3490 return 0; 3491 } 3492 3493 /* Set mac addr if it is configured. or leave it to the AE driver */ 3494 static int hns3_init_mac_addr(struct net_device *netdev, bool init) 3495 { 3496 struct hns3_nic_priv *priv = netdev_priv(netdev); 3497 struct hnae3_handle *h = priv->ae_handle; 3498 u8 mac_addr_temp[ETH_ALEN]; 3499 int ret = 0; 3500 3501 if (h->ae_algo->ops->get_mac_addr && init) { 3502 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 3503 ether_addr_copy(netdev->dev_addr, mac_addr_temp); 3504 } 3505 3506 /* Check if the MAC address is valid, if not get a random one */ 3507 if (!is_valid_ether_addr(netdev->dev_addr)) { 3508 eth_hw_addr_random(netdev); 3509 dev_warn(priv->dev, "using random MAC address %pM\n", 3510 netdev->dev_addr); 3511 } 3512 3513 if (h->ae_algo->ops->set_mac_addr) 3514 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 3515 3516 return ret; 3517 } 3518 3519 static int hns3_init_phy(struct net_device *netdev) 3520 { 3521 struct hnae3_handle *h = hns3_get_handle(netdev); 3522 int ret = 0; 3523 3524 if (h->ae_algo->ops->mac_connect_phy) 3525 ret = h->ae_algo->ops->mac_connect_phy(h); 3526 3527 return ret; 3528 } 3529 3530 static void hns3_uninit_phy(struct net_device *netdev) 3531 { 3532 struct hnae3_handle *h = hns3_get_handle(netdev); 3533 3534 if (h->ae_algo->ops->mac_disconnect_phy) 3535 h->ae_algo->ops->mac_disconnect_phy(h); 3536 } 3537 3538 static int hns3_restore_fd_rules(struct net_device *netdev) 3539 { 3540 struct hnae3_handle *h = hns3_get_handle(netdev); 3541 int ret = 0; 3542 3543 if (h->ae_algo->ops->restore_fd_rules) 3544 ret = h->ae_algo->ops->restore_fd_rules(h); 3545 3546 return ret; 3547 } 3548 3549 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list) 3550 { 3551 struct hnae3_handle *h = hns3_get_handle(netdev); 3552 3553 if (h->ae_algo->ops->del_all_fd_entries) 3554 h->ae_algo->ops->del_all_fd_entries(h, clear_list); 3555 } 3556 3557 static void hns3_nic_set_priv_ops(struct net_device *netdev) 3558 { 3559 struct hns3_nic_priv *priv = netdev_priv(netdev); 3560 3561 if ((netdev->features & NETIF_F_TSO) || 3562 (netdev->features & NETIF_F_TSO6)) 3563 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso; 3564 else 3565 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx; 3566 } 3567 3568 static int hns3_client_start(struct hnae3_handle *handle) 3569 { 3570 if (!handle->ae_algo->ops->client_start) 3571 return 0; 3572 3573 return handle->ae_algo->ops->client_start(handle); 3574 } 3575 3576 static void hns3_client_stop(struct hnae3_handle *handle) 3577 { 3578 if (!handle->ae_algo->ops->client_stop) 3579 return; 3580 3581 handle->ae_algo->ops->client_stop(handle); 3582 } 3583 3584 static int hns3_client_init(struct hnae3_handle *handle) 3585 { 3586 struct pci_dev *pdev = handle->pdev; 3587 u16 alloc_tqps, max_rss_size; 3588 struct hns3_nic_priv *priv; 3589 struct net_device *netdev; 3590 int ret; 3591 3592 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 3593 &max_rss_size); 3594 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 3595 if (!netdev) 3596 return -ENOMEM; 3597 3598 priv = netdev_priv(netdev); 3599 priv->dev = &pdev->dev; 3600 priv->netdev = netdev; 3601 priv->ae_handle = handle; 3602 priv->tx_timeout_count = 0; 3603 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 3604 3605 handle->kinfo.netdev = netdev; 3606 handle->priv = (void *)priv; 3607 3608 hns3_init_mac_addr(netdev, true); 3609 3610 hns3_set_default_feature(netdev); 3611 3612 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 3613 netdev->priv_flags |= IFF_UNICAST_FLT; 3614 netdev->netdev_ops = &hns3_nic_netdev_ops; 3615 SET_NETDEV_DEV(netdev, &pdev->dev); 3616 hns3_ethtool_set_ops(netdev); 3617 hns3_nic_set_priv_ops(netdev); 3618 3619 /* Carrier off reporting is important to ethtool even BEFORE open */ 3620 netif_carrier_off(netdev); 3621 3622 ret = hns3_get_ring_config(priv); 3623 if (ret) { 3624 ret = -ENOMEM; 3625 goto out_get_ring_cfg; 3626 } 3627 3628 ret = hns3_nic_alloc_vector_data(priv); 3629 if (ret) { 3630 ret = -ENOMEM; 3631 goto out_alloc_vector_data; 3632 } 3633 3634 ret = hns3_nic_init_vector_data(priv); 3635 if (ret) { 3636 ret = -ENOMEM; 3637 goto out_init_vector_data; 3638 } 3639 3640 ret = hns3_init_all_ring(priv); 3641 if (ret) { 3642 ret = -ENOMEM; 3643 goto out_init_ring_data; 3644 } 3645 3646 ret = hns3_init_phy(netdev); 3647 if (ret) 3648 goto out_init_phy; 3649 3650 ret = register_netdev(netdev); 3651 if (ret) { 3652 dev_err(priv->dev, "probe register netdev fail!\n"); 3653 goto out_reg_netdev_fail; 3654 } 3655 3656 ret = hns3_client_start(handle); 3657 if (ret) { 3658 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 3659 goto out_client_start; 3660 } 3661 3662 hns3_dcbnl_setup(handle); 3663 3664 hns3_dbg_init(handle); 3665 3666 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */ 3667 netdev->max_mtu = HNS3_MAX_MTU; 3668 3669 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 3670 3671 return ret; 3672 3673 out_client_start: 3674 unregister_netdev(netdev); 3675 out_reg_netdev_fail: 3676 hns3_uninit_phy(netdev); 3677 out_init_phy: 3678 hns3_uninit_all_ring(priv); 3679 out_init_ring_data: 3680 hns3_nic_uninit_vector_data(priv); 3681 out_init_vector_data: 3682 hns3_nic_dealloc_vector_data(priv); 3683 out_alloc_vector_data: 3684 priv->ring_data = NULL; 3685 out_get_ring_cfg: 3686 priv->ae_handle = NULL; 3687 free_netdev(netdev); 3688 return ret; 3689 } 3690 3691 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 3692 { 3693 struct net_device *netdev = handle->kinfo.netdev; 3694 struct hns3_nic_priv *priv = netdev_priv(netdev); 3695 int ret; 3696 3697 hns3_client_stop(handle); 3698 3699 hns3_remove_hw_addr(netdev); 3700 3701 if (netdev->reg_state != NETREG_UNINITIALIZED) 3702 unregister_netdev(netdev); 3703 3704 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 3705 netdev_warn(netdev, "already uninitialized\n"); 3706 goto out_netdev_free; 3707 } 3708 3709 hns3_del_all_fd_rules(netdev, true); 3710 3711 hns3_force_clear_all_rx_ring(handle); 3712 3713 hns3_uninit_phy(netdev); 3714 3715 hns3_nic_uninit_vector_data(priv); 3716 3717 ret = hns3_nic_dealloc_vector_data(priv); 3718 if (ret) 3719 netdev_err(netdev, "dealloc vector error\n"); 3720 3721 ret = hns3_uninit_all_ring(priv); 3722 if (ret) 3723 netdev_err(netdev, "uninit ring error\n"); 3724 3725 hns3_put_ring_config(priv); 3726 3727 hns3_dbg_uninit(handle); 3728 3729 priv->ring_data = NULL; 3730 3731 out_netdev_free: 3732 free_netdev(netdev); 3733 } 3734 3735 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 3736 { 3737 struct net_device *netdev = handle->kinfo.netdev; 3738 3739 if (!netdev) 3740 return; 3741 3742 if (linkup) { 3743 netif_carrier_on(netdev); 3744 netif_tx_wake_all_queues(netdev); 3745 netdev_info(netdev, "link up\n"); 3746 } else { 3747 netif_carrier_off(netdev); 3748 netif_tx_stop_all_queues(netdev); 3749 netdev_info(netdev, "link down\n"); 3750 } 3751 } 3752 3753 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc) 3754 { 3755 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3756 struct net_device *ndev = kinfo->netdev; 3757 3758 if (tc > HNAE3_MAX_TC) 3759 return -EINVAL; 3760 3761 if (!ndev) 3762 return -ENODEV; 3763 3764 return hns3_nic_set_real_num_queue(ndev); 3765 } 3766 3767 static int hns3_recover_hw_addr(struct net_device *ndev) 3768 { 3769 struct netdev_hw_addr_list *list; 3770 struct netdev_hw_addr *ha, *tmp; 3771 int ret = 0; 3772 3773 /* go through and sync uc_addr entries to the device */ 3774 list = &ndev->uc; 3775 list_for_each_entry_safe(ha, tmp, &list->list, list) { 3776 ret = hns3_nic_uc_sync(ndev, ha->addr); 3777 if (ret) 3778 return ret; 3779 } 3780 3781 /* go through and sync mc_addr entries to the device */ 3782 list = &ndev->mc; 3783 list_for_each_entry_safe(ha, tmp, &list->list, list) { 3784 ret = hns3_nic_mc_sync(ndev, ha->addr); 3785 if (ret) 3786 return ret; 3787 } 3788 3789 return ret; 3790 } 3791 3792 static void hns3_remove_hw_addr(struct net_device *netdev) 3793 { 3794 struct netdev_hw_addr_list *list; 3795 struct netdev_hw_addr *ha, *tmp; 3796 3797 hns3_nic_uc_unsync(netdev, netdev->dev_addr); 3798 3799 /* go through and unsync uc_addr entries to the device */ 3800 list = &netdev->uc; 3801 list_for_each_entry_safe(ha, tmp, &list->list, list) 3802 hns3_nic_uc_unsync(netdev, ha->addr); 3803 3804 /* go through and unsync mc_addr entries to the device */ 3805 list = &netdev->mc; 3806 list_for_each_entry_safe(ha, tmp, &list->list, list) 3807 if (ha->refcount > 1) 3808 hns3_nic_mc_unsync(netdev, ha->addr); 3809 } 3810 3811 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 3812 { 3813 while (ring->next_to_clean != ring->next_to_use) { 3814 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 3815 hns3_free_buffer_detach(ring, ring->next_to_clean); 3816 ring_ptr_move_fw(ring, next_to_clean); 3817 } 3818 } 3819 3820 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 3821 { 3822 struct hns3_desc_cb res_cbs; 3823 int ret; 3824 3825 while (ring->next_to_use != ring->next_to_clean) { 3826 /* When a buffer is not reused, it's memory has been 3827 * freed in hns3_handle_rx_bd or will be freed by 3828 * stack, so we need to replace the buffer here. 3829 */ 3830 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3831 ret = hns3_reserve_buffer_map(ring, &res_cbs); 3832 if (ret) { 3833 u64_stats_update_begin(&ring->syncp); 3834 ring->stats.sw_err_cnt++; 3835 u64_stats_update_end(&ring->syncp); 3836 /* if alloc new buffer fail, exit directly 3837 * and reclear in up flow. 3838 */ 3839 netdev_warn(ring->tqp->handle->kinfo.netdev, 3840 "reserve buffer map failed, ret = %d\n", 3841 ret); 3842 return ret; 3843 } 3844 hns3_replace_buffer(ring, ring->next_to_use, 3845 &res_cbs); 3846 } 3847 ring_ptr_move_fw(ring, next_to_use); 3848 } 3849 3850 return 0; 3851 } 3852 3853 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 3854 { 3855 while (ring->next_to_use != ring->next_to_clean) { 3856 /* When a buffer is not reused, it's memory has been 3857 * freed in hns3_handle_rx_bd or will be freed by 3858 * stack, so only need to unmap the buffer here. 3859 */ 3860 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 3861 hns3_unmap_buffer(ring, 3862 &ring->desc_cb[ring->next_to_use]); 3863 ring->desc_cb[ring->next_to_use].dma = 0; 3864 } 3865 3866 ring_ptr_move_fw(ring, next_to_use); 3867 } 3868 } 3869 3870 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h) 3871 { 3872 struct net_device *ndev = h->kinfo.netdev; 3873 struct hns3_nic_priv *priv = netdev_priv(ndev); 3874 struct hns3_enet_ring *ring; 3875 u32 i; 3876 3877 for (i = 0; i < h->kinfo.num_tqps; i++) { 3878 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3879 hns3_force_clear_rx_ring(ring); 3880 } 3881 } 3882 3883 static void hns3_clear_all_ring(struct hnae3_handle *h) 3884 { 3885 struct net_device *ndev = h->kinfo.netdev; 3886 struct hns3_nic_priv *priv = netdev_priv(ndev); 3887 u32 i; 3888 3889 for (i = 0; i < h->kinfo.num_tqps; i++) { 3890 struct netdev_queue *dev_queue; 3891 struct hns3_enet_ring *ring; 3892 3893 ring = priv->ring_data[i].ring; 3894 hns3_clear_tx_ring(ring); 3895 dev_queue = netdev_get_tx_queue(ndev, 3896 priv->ring_data[i].queue_index); 3897 netdev_tx_reset_queue(dev_queue); 3898 3899 ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3900 /* Continue to clear other rings even if clearing some 3901 * rings failed. 3902 */ 3903 hns3_clear_rx_ring(ring); 3904 } 3905 } 3906 3907 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 3908 { 3909 struct net_device *ndev = h->kinfo.netdev; 3910 struct hns3_nic_priv *priv = netdev_priv(ndev); 3911 struct hns3_enet_ring *rx_ring; 3912 int i, j; 3913 int ret; 3914 3915 for (i = 0; i < h->kinfo.num_tqps; i++) { 3916 ret = h->ae_algo->ops->reset_queue(h, i); 3917 if (ret) 3918 return ret; 3919 3920 hns3_init_ring_hw(priv->ring_data[i].ring); 3921 3922 /* We need to clear tx ring here because self test will 3923 * use the ring and will not run down before up 3924 */ 3925 hns3_clear_tx_ring(priv->ring_data[i].ring); 3926 priv->ring_data[i].ring->next_to_clean = 0; 3927 priv->ring_data[i].ring->next_to_use = 0; 3928 3929 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring; 3930 hns3_init_ring_hw(rx_ring); 3931 ret = hns3_clear_rx_ring(rx_ring); 3932 if (ret) 3933 return ret; 3934 3935 /* We can not know the hardware head and tail when this 3936 * function is called in reset flow, so we reuse all desc. 3937 */ 3938 for (j = 0; j < rx_ring->desc_num; j++) 3939 hns3_reuse_buffer(rx_ring, j); 3940 3941 rx_ring->next_to_clean = 0; 3942 rx_ring->next_to_use = 0; 3943 } 3944 3945 hns3_init_tx_ring_tc(priv); 3946 3947 return 0; 3948 } 3949 3950 static void hns3_store_coal(struct hns3_nic_priv *priv) 3951 { 3952 /* ethtool only support setting and querying one coal 3953 * configuation for now, so save the vector 0' coal 3954 * configuation here in order to restore it. 3955 */ 3956 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal, 3957 sizeof(struct hns3_enet_coalesce)); 3958 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal, 3959 sizeof(struct hns3_enet_coalesce)); 3960 } 3961 3962 static void hns3_restore_coal(struct hns3_nic_priv *priv) 3963 { 3964 u16 vector_num = priv->vector_num; 3965 int i; 3966 3967 for (i = 0; i < vector_num; i++) { 3968 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal, 3969 sizeof(struct hns3_enet_coalesce)); 3970 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal, 3971 sizeof(struct hns3_enet_coalesce)); 3972 } 3973 } 3974 3975 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 3976 { 3977 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 3978 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 3979 struct net_device *ndev = kinfo->netdev; 3980 struct hns3_nic_priv *priv = netdev_priv(ndev); 3981 3982 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 3983 return 0; 3984 3985 /* it is cumbersome for hardware to pick-and-choose entries for deletion 3986 * from table space. Hence, for function reset software intervention is 3987 * required to delete the entries 3988 */ 3989 if (hns3_dev_ongoing_func_reset(ae_dev)) { 3990 hns3_remove_hw_addr(ndev); 3991 hns3_del_all_fd_rules(ndev, false); 3992 } 3993 3994 if (!netif_running(ndev)) 3995 return 0; 3996 3997 return hns3_nic_net_stop(ndev); 3998 } 3999 4000 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 4001 { 4002 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 4003 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 4004 int ret = 0; 4005 4006 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4007 4008 if (netif_running(kinfo->netdev)) { 4009 ret = hns3_nic_net_open(kinfo->netdev); 4010 if (ret) { 4011 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 4012 netdev_err(kinfo->netdev, 4013 "hns net up fail, ret=%d!\n", ret); 4014 return ret; 4015 } 4016 } 4017 4018 return ret; 4019 } 4020 4021 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 4022 { 4023 struct net_device *netdev = handle->kinfo.netdev; 4024 struct hns3_nic_priv *priv = netdev_priv(netdev); 4025 int ret; 4026 4027 /* Carrier off reporting is important to ethtool even BEFORE open */ 4028 netif_carrier_off(netdev); 4029 4030 ret = hns3_get_ring_config(priv); 4031 if (ret) 4032 return ret; 4033 4034 ret = hns3_nic_alloc_vector_data(priv); 4035 if (ret) 4036 goto err_put_ring; 4037 4038 hns3_restore_coal(priv); 4039 4040 ret = hns3_nic_init_vector_data(priv); 4041 if (ret) 4042 goto err_dealloc_vector; 4043 4044 ret = hns3_init_all_ring(priv); 4045 if (ret) 4046 goto err_uninit_vector; 4047 4048 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 4049 4050 return ret; 4051 4052 err_uninit_vector: 4053 hns3_nic_uninit_vector_data(priv); 4054 priv->ring_data = NULL; 4055 err_dealloc_vector: 4056 hns3_nic_dealloc_vector_data(priv); 4057 err_put_ring: 4058 hns3_put_ring_config(priv); 4059 priv->ring_data = NULL; 4060 4061 return ret; 4062 } 4063 4064 static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle) 4065 { 4066 struct net_device *netdev = handle->kinfo.netdev; 4067 bool vlan_filter_enable; 4068 int ret; 4069 4070 ret = hns3_init_mac_addr(netdev, false); 4071 if (ret) 4072 return ret; 4073 4074 ret = hns3_recover_hw_addr(netdev); 4075 if (ret) 4076 return ret; 4077 4078 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags); 4079 if (ret) 4080 return ret; 4081 4082 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true; 4083 hns3_enable_vlan_filter(netdev, vlan_filter_enable); 4084 4085 /* Hardware table is only clear when pf resets */ 4086 if (!(handle->flags & HNAE3_SUPPORT_VF)) { 4087 ret = hns3_restore_vlan(netdev); 4088 if (ret) 4089 return ret; 4090 } 4091 4092 return hns3_restore_fd_rules(netdev); 4093 } 4094 4095 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 4096 { 4097 struct net_device *netdev = handle->kinfo.netdev; 4098 struct hns3_nic_priv *priv = netdev_priv(netdev); 4099 int ret; 4100 4101 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 4102 netdev_warn(netdev, "already uninitialized\n"); 4103 return 0; 4104 } 4105 4106 hns3_force_clear_all_rx_ring(handle); 4107 4108 hns3_nic_uninit_vector_data(priv); 4109 4110 hns3_store_coal(priv); 4111 4112 ret = hns3_nic_dealloc_vector_data(priv); 4113 if (ret) 4114 netdev_err(netdev, "dealloc vector error\n"); 4115 4116 ret = hns3_uninit_all_ring(priv); 4117 if (ret) 4118 netdev_err(netdev, "uninit ring error\n"); 4119 4120 hns3_put_ring_config(priv); 4121 priv->ring_data = NULL; 4122 4123 clear_bit(HNS3_NIC_STATE_INITED, &priv->state); 4124 4125 return ret; 4126 } 4127 4128 static int hns3_reset_notify(struct hnae3_handle *handle, 4129 enum hnae3_reset_notify_type type) 4130 { 4131 int ret = 0; 4132 4133 switch (type) { 4134 case HNAE3_UP_CLIENT: 4135 ret = hns3_reset_notify_up_enet(handle); 4136 break; 4137 case HNAE3_DOWN_CLIENT: 4138 ret = hns3_reset_notify_down_enet(handle); 4139 break; 4140 case HNAE3_INIT_CLIENT: 4141 ret = hns3_reset_notify_init_enet(handle); 4142 break; 4143 case HNAE3_UNINIT_CLIENT: 4144 ret = hns3_reset_notify_uninit_enet(handle); 4145 break; 4146 case HNAE3_RESTORE_CLIENT: 4147 ret = hns3_reset_notify_restore_enet(handle); 4148 break; 4149 default: 4150 break; 4151 } 4152 4153 return ret; 4154 } 4155 4156 int hns3_set_channels(struct net_device *netdev, 4157 struct ethtool_channels *ch) 4158 { 4159 struct hnae3_handle *h = hns3_get_handle(netdev); 4160 struct hnae3_knic_private_info *kinfo = &h->kinfo; 4161 bool rxfh_configured = netif_is_rxfh_configured(netdev); 4162 u32 new_tqp_num = ch->combined_count; 4163 u16 org_tqp_num; 4164 int ret; 4165 4166 if (ch->rx_count || ch->tx_count) 4167 return -EINVAL; 4168 4169 if (new_tqp_num > hns3_get_max_available_channels(h) || 4170 new_tqp_num < 1) { 4171 dev_err(&netdev->dev, 4172 "Change tqps fail, the tqp range is from 1 to %d", 4173 hns3_get_max_available_channels(h)); 4174 return -EINVAL; 4175 } 4176 4177 if (kinfo->rss_size == new_tqp_num) 4178 return 0; 4179 4180 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 4181 if (ret) 4182 return ret; 4183 4184 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 4185 if (ret) 4186 return ret; 4187 4188 org_tqp_num = h->kinfo.num_tqps; 4189 ret = h->ae_algo->ops->set_channels(h, new_tqp_num, rxfh_configured); 4190 if (ret) { 4191 ret = h->ae_algo->ops->set_channels(h, org_tqp_num, 4192 rxfh_configured); 4193 if (ret) { 4194 /* If revert to old tqp failed, fatal error occurred */ 4195 dev_err(&netdev->dev, 4196 "Revert to old tqp num fail, ret=%d", ret); 4197 return ret; 4198 } 4199 dev_info(&netdev->dev, 4200 "Change tqp num fail, Revert to old tqp num"); 4201 } 4202 ret = hns3_reset_notify(h, HNAE3_INIT_CLIENT); 4203 if (ret) 4204 return ret; 4205 4206 return hns3_reset_notify(h, HNAE3_UP_CLIENT); 4207 } 4208 4209 static const struct hnae3_client_ops client_ops = { 4210 .init_instance = hns3_client_init, 4211 .uninit_instance = hns3_client_uninit, 4212 .link_status_change = hns3_link_status_change, 4213 .setup_tc = hns3_client_setup_tc, 4214 .reset_notify = hns3_reset_notify, 4215 }; 4216 4217 /* hns3_init_module - Driver registration routine 4218 * hns3_init_module is the first routine called when the driver is 4219 * loaded. All it does is register with the PCI subsystem. 4220 */ 4221 static int __init hns3_init_module(void) 4222 { 4223 int ret; 4224 4225 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 4226 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright); 4227 4228 client.type = HNAE3_CLIENT_KNIC; 4229 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s", 4230 hns3_driver_name); 4231 4232 client.ops = &client_ops; 4233 4234 INIT_LIST_HEAD(&client.node); 4235 4236 hns3_dbg_register_debugfs(hns3_driver_name); 4237 4238 ret = hnae3_register_client(&client); 4239 if (ret) 4240 goto err_reg_client; 4241 4242 ret = pci_register_driver(&hns3_driver); 4243 if (ret) 4244 goto err_reg_driver; 4245 4246 return ret; 4247 4248 err_reg_driver: 4249 hnae3_unregister_client(&client); 4250 err_reg_client: 4251 hns3_dbg_unregister_debugfs(); 4252 return ret; 4253 } 4254 module_init(hns3_init_module); 4255 4256 /* hns3_exit_module - Driver exit cleanup routine 4257 * hns3_exit_module is called just before the driver is removed 4258 * from memory. 4259 */ 4260 static void __exit hns3_exit_module(void) 4261 { 4262 pci_unregister_driver(&hns3_driver); 4263 hnae3_unregister_client(&client); 4264 hns3_dbg_unregister_debugfs(); 4265 } 4266 module_exit(hns3_exit_module); 4267 4268 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 4269 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 4270 MODULE_LICENSE("GPL"); 4271 MODULE_ALIAS("pci:hns-nic"); 4272 MODULE_VERSION(HNS3_MOD_VERSION); 4273